HD74ALVC2G74 Single D-type Flip Flops with Preset and Clear REJ03D0169–0300Z (Previous ADE-205-639B (Z)) Rev.3.00 Dec.18.2003 Description The HD74ALVC2G74 has independent data, preset, clear, and clock inputs Q and Q outputs in an 8 pin package. The input data is transferred to the output at the rising edge of clock pulse CLK. Low voltage and high-speed operation is suitable for the battery powered products (e.g., notebook computers), and the low power consumption extends the battery life. Features • The basic gate function is lined up as Renesas uni logic series. • Supplied on emboss taping for high-speed automatic mounting. • Supply voltage range : 1.2 to 3.6 V Operating temperature range: −40 to +85°C • All inputs VIH (Max.) = 3.6 V (@VCC = 0 V to 3.6 V) All outputs VO (Max.) = 3.6 V (@VCC = 0 V) • Output current ±2 mA (@VCC = 1.2 V) ±4 mA (@VCC = 1.4 V to 1.6 V) ±6 mA (@VCC = 1.65 V to 1.95 V) ±18 mA (@VCC = 2.3 V to 2.7 V) ±24 mA (@VCC = 3.0 V to 3.6 V) • Ordering Information Part Name Package Type Package Code Package Abbreviation Taping Abbreviation (Quantity) HD74ALVC2G74USE SSOP-8 pin TTP-8DBV US E (3,000 pcs/reel) Rev.3.00, Dec.18.2003, page 1 of 10 HD74ALVC2G74 Outline and Article Indication • HD74ALVC2G74 Index band Lot No. Y M W A 7 4 Y : Year code (the last digit of year) M : Month code W : Week code SSOP-8 Marking Function Table Inputs Outputs PRE CLR CLK D Q Q L H X X H L H L X X L H *1 H *1 L L X X H H H ↑ H H L H H ↑ L L H H H ↓ X Q0 Q0 H : High level L : Low level X : Immaterial ↑ : Low to high transition ↓ : High to low transition Q0 : The level of Q immediately before the input conditions shown in the above table are determined. Note : 1. Q and Q will remain high as long as preset and clear are low, but Q and Q are unpredictable, if preset and clear go high simultaneously. Rev.3.00, Dec.18.2003, page 2 of 10 HD74ALVC2G74 Pin Arrangement CLK 1 8 VCC D 2 7 PRE Q 3 6 CLR GND 4 5 Q (Top view) Absolute Maximum Ratings Item Symbol Ratings Unit Supply voltage range VCC −0.5 to 4.6 V Input voltage range *1 VI −0.5 to 4.6 V VO −0.5 to VCC+0.5 V Output voltage range *1, 2 −0.5 to 4.6 Conditions Output : H or L VCC : OFF Input clamp current IIK −50 mA VI < 0 Output clamp current IOK ±50 mA VO < 0 or VO > VCC Continuous output current IO ±50 mA VO = 0 to VCC Continuous current through VCC or GND ICC or IGND ±100 mA Maximum power dissipation *3 at Ta = 25°C (in still air) PT 200 mW Storage temperature Tstg −65 to 150 °C Notes: The absolute maximum ratings are values, which must not individually be exceeded, and furthermore, no two of which may be realized at the same time. 1. The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. This value is limited to 4.6 V maximum. 3. The maximum package power dissipation was calculated using a junction temperature of 150°C. Rev.3.00, Dec.18.2003, page 3 of 10 HD74ALVC2G74 Recommended Operating Conditions Item Symbol Min Max Unit Supply voltage range VCC 1.2 3.6 V Input voltage range VI 0 3.6 V Output voltage range VO 0 VCC V Output current IOH −2 mA −4 VCC = 1.4 V −6 VCC = 1.65 V −18 VCC = 2.3 V −24 VCC = 3.0 V 2 VCC = 1.2 V 4 VCC = 1.4 V 6 VCC = 1.65 V 18 VCC = 2.3 V IOL ∆t / ∆v Input transition rise or fall rate Operating free-air temperature Ta 24 0 20 0 10 −40 85 Conditions VCC = 1.2 V VCC = 3.0 V ns / V VCC = 1.2 to 2.7 V VCC = 3.3±0.3 V °C Note: Unused or floating inputs must be held high or low. Logic Diagram PRE C CLK C C Q TG D C C TG TG TG C C C CLR Rev.3.00, Dec.18.2003, page 4 of 10 C C Q HD74ALVC2G74 Electrical Characteristics (Ta = −40 to 85°C) Item Symbol VCC (V) * Min Input voltage VIH 1.2 VIL Output voltage VOH VOL Typ Max Unit VCC×0.75 V 1.4 to 1.6 VCC×0.7 1.65 to 1.95 VCC×0.7 2.3 to 2.7 1.7 3.0 to 3.6 2.0 1.2 VCC×0.25 1.4 to 1.6 VCC×0.3 1.65 to 1.95 VCC×0.3 2.3 to 2.7 0.7 3.0 to 3.6 0.8 Min to Max VCC−0.2 1.2 0.9 IOH = −2 mA 1.4 1.1 IOH = −4 mA 1.65 1.2 IOH = −6 mA 2.3 1.7 IOH = −18 mA 3.0 2.2 IOH = −24 mA Min to Max 0.2 IOL = 100 µA 1.2 0.3 IOL = 2 mA 1.4 0.3 IOL = 4 mA 1.65 0.3 IOL = 6 mA 2.3 0.55 IOL = 18 mA 3.0 0.55 IOL = 24 mA V Test conditions IOH = −100 µA Input current IIN 3.6 ±5 µA VIN = 3.6 V or GND Quiescent supply current ICC 3.6 10 µA VIN = VCC or GND, IO = 0 Output leakage current IOFF 0 5 µA VIN or VO = 0 to 3.6 V Input capacitance CIN 3.3 4.5 pF VIN = VCC or GND Note: For conditions shown as Min or Max, use the appropriate values under recommended operating conditions. Rev.3.00, Dec.18.2003, page 5 of 10 HD74ALVC2G74 Switching Characteristics (Ta = −40 to 85°C) VCC = 1.2 V Item Symbol Min Typ Max Unit Test conditions Maximum clock frequency fmax 200 MHz CL = 15 pF Propagation 9.0 ns CL = 15 pF delay time tPLH tPHL 10.5 Setup time tsu 5.0 -3.0 FROM (Input) TO (Output) PRE/CLR Q or Q CLK D ns PRE or CLR inactive Hold time th -5.0 ns Pulse width tw 3.0 ns 3.0 PRE or CLR “L” CLK “H” or “L” VCC = 1.5±0.1 V Item Symbol Min Typ Max Unit Test conditions Maximum clock frequency fmax 100 350 MHz CL = 15 pF Propagation 2.0 11.0 ns CL = 15 pF delay time tPLH tPHL 2.0 11.0 Setup time tsu 4.5 5.0 TO (Output) PRE/CLR Q or Q CLK ns D PRE or CLR inactive Hold time th 0.0 ns Pulse width tw 3.5 ns 3.5 Rev.3.00, Dec.18.2003, page 6 of 10 FROM (Input) PRE or CLR “L” CLK “H” or “L” HD74ALVC2G74 VCC = 1.8±0.15 V Item Symbol Min Typ Max Unit Test conditions Maximum clock frequency fmax 160 350 MHz CL = 30 pF Propagation 1.5 8.0 ns CL = 30 pF delay time tPLH tPHL 1.5 8.0 Setup time tsu 3.5 3.0 Hold time th 0.0 ns Pulse width tw 2.5 ns 2.5 FROM (Input) TO (Output) PRE/CLR Q or Q CLK D ns PRE or CLR inactive PRE or CLR “L” CLK “H” or “L” VCC = 2.5±0.2 V Item Symbol Min Typ Max Unit Test conditions Maximum clock frequency fmax 160 400 MHz CL = 30 pF Propagation tPLH 1.0 5.0 ns CL = 30 pF delay time tPHL 1.0 5.0 Setup time tsu 2.5 2.0 FROM (Input) TO (Output) PRE/CLR Q or Q CLK ns D PRE or CLR inactive Hold time th 0.0 ns Pulse width tw 2.0 ns 2.0 PRE or CLR “L” CLK “H” or “L” VCC = 3.3±0.3 V Item Symbol Min Typ Max Unit Test conditions Maximum clock frequency fmax 200 450 MHz CL = 30 pF Propagation 1.0 3.5 ns CL = 30 pF delay time tPLH tPHL 1.0 3.5 Setup time tsu 2.0 2.0 TO (Output) PRE/CLR Q or Q CLK ns D PRE or CLR inactive Hold time th 0.0 ns Pulse width tw 2.0 ns 2.0 Rev.3.00, Dec.18.2003, page 7 of 10 FROM (Input) PRE or CLR “L” CLK “H” or “L” HD74ALVC2G74 Operating Characteristics (Ta = 25°C) Item Symbol VCC (V) Min Typ Max Unit Test conditions Power dissipation capacitance CPD 1.5 13.5 pF f = 10 MHz 1.8 13.5 2.5 20.0 3.3 22.0 Test Circuit VCC VCC Input PRE Pulse Generator Zout = 50 Ω D Symbol RL CL Input Pulse Generator Zout = 50 Ω Output Q Q CLK CLR Output Q Q CL RL V CC = 1.2 V, V = 2.5±0.2 V, V = 1.8±0.15 V CC 1.5±0.1 V CC 3.3±0.3 V RL 2.0 kΩ 1.0 kΩ 500 Ω CL 15 pF 30 pF 30 pF Notes: 1. C L includes probe and jig capacitance. 2. Test is put into the each flip flops. Rev.3.00, Dec.18.2003, page 8 of 10 HD74ALVC2G74 Waveforms • Waveform – 1 tf tr 10 % t su VIH 90 % 90 % Timing input Vref 10 % th GND VIH Data input Vref Vref GND tw VIH Input Vref Vref GND • Waveform – 2 tf tr 90 % Input 10 % 90 % Vref Vref VIH 10 % GND t PHL t PLH VOH Same-phase output Vref Vref VOL t PHL t PLH VOH Vref Opposite-phase output Vref VOL Symbol V CC = 1.2 V, 1.5±0.1 V, V CC = 2.5±0.2 V 1.8±0.15 V V CC = 3.3±0.3 V tr / t f 2.0 ns 2.5 ns 2.5 ns V IH VCC VCC 2.7 V V ref 50% 50% 1.5 V Note: Input waveform : PRR = 10 MHz, duty cycle 50% Rev.3.00, Dec.18.2003, page 9 of 10 HD74ALVC2G74 Package Dimensions 2.0 ± 0.2 1.5 ± 0.2 + 0.1 (0.17) 8 − 0.2 − 0.05 Package Code JEDEC JEITA Mass (reference value) Rev.3.00, Dec.18.2003, page 10 of 10 + 0.1 0.13 − 0.05 0 − 0.1 0.7 ± 0.1 (0.4) 2.3 ± 0.1 (0.5) (0.5) (0.5) 3.1 ± 0.3 (0.4) Unit: mm TTP–8DBV 0.010 g Sales Strategic Planning Div. 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