IRDC3473

IRDC3473
SupIRBuck
TM
USER GUIDE FOR IRDC3473 EVALUATION BOARD
DESCRIPTION
The IR3473 SupIRBuckTM is an easy-to-use,
fully integrated and highly efficient DC/DC
voltage regulator. The onboard constant on
time hysteretic controller and MOSFETs make
IR3473 a space-efficient solution that delivers
up to 6A of precisely controlled output voltage.
IR3473 is housed in a 4mmx5mm QFN
package.
Key features offered by IR3473 include:
programmable switching frequency, soft start,
temperature
compensated
over
current
protection, and thermal shutdown allowing a
very flexible solution suitable for many different
applications and an ideal choice for battery
powered applications.
Additional features include pre-bias startup, a
very precise 0.5V reference, forced continuous
conduction mode option, over/under voltage
protection, power good output, and enable input
with voltage monitoring capability.
This user guide contains the schematic, bill of
materials, and operating instructions of the
IRDC3473 evaluation board. Detailed product
specifications, application information and
performance curves at different operating
conditions are available in the IR3473 data
sheet.
BOARD FEATURES
•
•
•
•
•
•
•
•
VIN = +12V
VCC = +5V
VOUT = +1.05V
IOUT = 0 to 6A
FS = 300kHz @ CCM
L = 2.2µH
CIN = 22µF (ceramic 1210) + 68µF (electrolytic)
COUT = 47µF (ceramic 0805) + 150µF (POSCAP)
1
IRDC3473
CONNECTIONS and OPERATING INSTRUCTIONS
An input supply in the range of 8 to 19V should be connected from VIN to PGND. A maximum load
of 6A may be connected to VOUT and PGND. The connection diagram is shown in Fig. 1, and the
inputs and outputs of the board are listed in Table 1.
IRDC3473 has two input supplies, one for biasing (VCC) and the other for input voltage (VIN).
Separate supplies should be applied to these inputs. VCC input should be a well regulated 4.5V to
5.5V supply connected to VCC and PGND. Enable (EN) is controlled by the first switch of SW1, and
FCCM option can be selected by the second switch of SW1. Toggle the switch to the ON position
(marked by a solid square) to enable switching or to select FCCM. The absolute maximum voltage
of the external signal applied to EN (TP4) and FCCM is +8V.
Table 1. Connections
Connection
Signal Name
VIN (TP2)
VIN
PGND (TP5)
Ground for VIN
VCC (TP16)
VCC Input
PGND (TP17)
Ground for VCC Input
VOUT (TP7)
VOUT (+1.05V)
PGND (TP10)
Ground for VOUT
EN (TP4)
Enable Input
LAYOUT
The PCB is a 4-layer board. All layers are 1 oz. copper. IR3473 and other components are mounted
on the top and bottom layers of the board.
The power supply decoupling capacitors, bootstrap capacitor and feedback components are located
close to IR3473. To improve efficiency, the circuit board is designed to minimize the length of the onboard power ground current path.
2
IRDC3473
CONNECTION DIAGRAM
VIN
GROUND
Control Switch for:
EN
FCCM
GROUND
VCC = +5.0V
VOUT = +1.05V
GROUND
Fig. 1: Connection Diagram of IRDC3473 Evaluation Board
3
IRDC3473
PCB Board Layout
Fig. 2: Board Layout, Top Components
Fig. 3: Board Layout, Bottom Components
4
IRDC3473
PCB Board Layout
Fig. 4: Board Layout, Top Layer
Fig. 5: Board Layout, Bottom Layer
5
IRDC3473
PCB Board Layout
Fig. 6: Board Layout, Mid-layer I
Fig. 7: Board Layout, Mid-layer II
6
SW1
EN / FCCM
4
3
TP11
PGOOD
1
2
TP4
EN
TP17
PGND
TP16
VCC
C23
open
VCC
TP14
+3.3V
TP26
AGND
+3.3V
TP13
SS
NC1
SS
FB
GND1
PGOOD
ISET
FCCM
R12
4.99
C21
1uF
R3
200K
TP28
VID
TP27
A
C25
1uF
TP25
B
C22
open
R10
open
R11
20
IR3473
PHASE
12
U1
IR3473
1
C4
0.22uF
Q1
open
R9
open
R6
open
VSW
VIN
C14
open
L1
2.2uH
C13
open
C24
open
R13
open
C1
1uF
R8
2.55K
R7
2.80K
C2
22uF
+ C3
68uF
C15
open
C6
open
C16
open
C7
open
C17
open
C8
open
TP6
PGNDS
TP1
VINS
Fig. 8: Schematic of the IRDC3473 Evaluation Board
7
6
C20
0.1uF
5
4
3
2
1
SS
PGOOD
ISET
FB
R5
10K
+3.3V
VSW
R4
15.8K
FCCM
EN
17
GND
16
EN
NC2
9
VCC
10
3VCBP
8
15
FF
14
BOOT
13
VIN
PGND
11
R1
10K
C18
open
C9
150uF
TP5
PGND
TP2
VIN
C19
open
C10
47uF
C26
open
C11
open
C27
open
C12
0.1uF
VOUT
10
R2
10K
+3.3V
2
3
6
-Vins
+Vins
7
1
VIN
-Vdd1s
2
VCC
+Vdd1s
8
-Vdd2s
9
4
+Vdd2s
3
+3.3V
+Vout1s -Vout1s
VOUT
+Vout2s -Vout2s
5
VCC
TP10
PGND
TP7
VOUT
TP18
VOLTAGE SENSE
TP24
PGNDS
TP23
VOUTS
IRDC3473
7
IRDC3473
Bill of Materials
QTY
3
1
2
1
1
1
1
1
1
3
1
1
1
1
1
1
1
REF DESIGNATOR
C1, C21, C25
C10
C12, C20
C2
C3
C4
C9
L1
R4
R1, R2, R5
R11
R12
R3
R7
R8
SW1
U1
VALUE
1.00uF
47uF
0.100uF
22.0uF
68uF
0.22uF
150uF
2.2uH
15.8K
10.0K
20
4.99
200K
2.80K
2.55K
SPST
IR3473
DESCRIPTION
capacitor, X7R, 1.00uF, 25V, 0.1, 0603
capacitor, 47uF, 6.3V, 805
capacitor, X7R, 0.100uF, 25V, 0.1, 603
capacitor, X5R, 22.0uF, 16V, 20%, 1206
capacitor, electrolytic, 68uF, 25V, 0.2, SMD
capacitor, X5R, 0.22uF, 10V, 0.1, 0603
capacitor, tantalum polymer, 150uF, 6.3V, 20%, 7343
inductor, ferrite, 2.2uH, 8.0A, 11.2mOhm, SMT
resistor, thick film, 15.8K, 1/10W, 0.01, 603
resistor, thick film, 10.0K, 1/10W, 0.01, 0603
resistor, thick film, 20, 1/10W, 0.01, 603
resistor, thick film, 4.99, 1/8W, 0.01, 603
resistor, thick film, 200K, 1/10W, 0.01, 603
resistor, thick film, 2.80K, 1/10W, 0.01, 603
resistor, thick film, 2.55K, 1/10W, 0.01, 0603
switch, DIP, SPST, 2 position, SMT
4mm X 5mm QFN
MANUFACTURER
PART NUMBER
Murata
GRM188R71E105KA12D
TDK
C2012X5R0J476M
TDK
C1608X7R1E104K
Taiyo Yuden
EMK316BJ226ML-T
Panasonic
EEV-FK1E680P
TDK
C1608X5R1A224K
Sanyo
6TPC150M
Cyntec
PCMB065T-2R2MS
KOA
RK73H1JLTD1582F
KOA
RK73H1J1002F
KOA
RK73H1JLTD20R0F
KOA
RK73H1J4R99F
KOA
RK73H1JLTD2003F
KOA
RK73H1JLTD2801F
KOA
RK73H1J2551F
C&K Components
SD02H0SK
IRF
IR3473MTRPBF
8
IRDC3473
TYPICAL OPERATING WAVEFORMS
Tested with demoboard shown in Fig. 8, VIN = 12V, VCC = 5V, VOUT = 1.05V, Fs = 300kHz, TA = 25oC, no airflow,
unless otherwise specified
EN
EN
PGOOD
PGOOD
SS
SS
VOUT
VOUT
5V/div 5V/div 1V/div 500mV/div
5ms/div
5V/div 5V/div 1V/div 500mV/div
500µs/div
Fig. 10: Shutdown
Fig. 9: Startup
VOUT
VOUT
PHASE
PHASE
iL
iL
20mV/div 10V/div 500mA/div
5µs/div
Fig. 11: DCM (IOUT = 0.1A)
20mV/div 10V/div 5A/div
2µs/div
Fig. 12: CCM (IOUT = 6A)
PGOOD
PGOOD
SS
FB
VOUT
VOUT
iL
5V/div 1V/div 500mV/div 10A/div
iL
2ms/div
Fig. 13: Over Current Protection (tested by
shorting VOUT to PGND)
5V/div 1V/div 500mV/div 2A/div
50µs/div
Fig. 14: Over Voltage Protection
(tested by shorting FB to VOUT)
9
IRDC3473
TYPICAL OPERATING WAVEFORMS
Tested with demoboard shown in Fig. 8, VIN = 12V, VCC = 5V, VOUT = 1.05V, Fs = 300kHz, TA = 25oC, no airflow,
unless otherwise specified
VOUT
VOUT
PHASE
PHASE
iL
iL
50mV/div 10V/div 2A/div
100µs/div
Fig. 15: Load Transient 0-3A
50mV/div 10V/div 5A/div
100µs/div
Fig. 16: Load Transient 3-6A
TYPICAL PERFORMANCE
VIN = 12V, VCC = 5V, VOUT = 1.05V, Fs = 300kHz, IOUT = 6A, TA = 25oC, no airflow
Fig. 17: Thermal Image (IR3473: 70oC, Inductor: 49oC, PCB: 38oC)
10
IRDC3473
TYPICAL OPERATING DATA
VIN = 12V, VCC = 5V, VOUT = 1.05V, Fs = 300kHz, IOUT = 0 ~ 6A, TA = 25oC, no airflow,
unless otherwise specified
90%
350
Switching Frequency (kHz)
85%
Efficiency
80%
75%
70%
65%
60%
55%
50%
45%
0.01
300
250
200
150
100
50
0
0.1
1
10
0
1
2
Load Current (A)
1.090
1.090
1.085
1.085
1.080
1.080
1.075
1.070
1.065
1.060
1.055
1.050
1.065
1.060
1.055
1.050
1.040
1.040
3
4
Load Current (A)
Fig. 20: Load Regulation
6
1.070
1.045
2
5
1.075
1.045
1
4
Fig. 19: Switching Frequency vs. Output
Current
Output Voltage (V)
Output Voltage (V)
Fig. 18: Efficiency vs. Output Current
0
3
Load Current (A)
5
6
8
9
10
11
12
13
14
15
16
17
18
19
Input Voltage (V)
Fig. 21: Line Regulation at 6A Load
11
IRDC3473
PCB Metal and Components Placement
Lead lands (the 13 IC pins) width should be equal to nominal part lead width. The minimum lead to lead spacing
should be ≥ 0.2mm to minimize shorting.
Lead land length should be equal to maximum part lead length + 0.3 mm outboard extension. The outboard
extension ensures a large toe fillet that can be easily inspected.
Pad lands (the 4 big pads) length and width should be equal to maximum part pad length and width. However, the
minimum metal to metal spacing should be no less than 0.17mm for 2 oz. Copper, or no less than 0.1mm for 1 oz.
Copper, or no less than 0.23mm for 3 oz. Copper.
12
IRDC3473
Solder Resist
It is recommended that the lead lands are Non Solder Mask Defined (NSMD). The solder resist should be pulled
away from the metal lead lands by a minimum of 0.025mm to ensure NSMD pads.
The land pad should be Solder Mask Defined (SMD), with a minimum overlap of the solder resist onto the copper of
0.05mm to accommodate solder resist misalignment.
Ensure that the solder resist in between the lead lands and the pad land is ≥ 0.15mm due to the high aspect ratio of
the solder resist strip separating the lead lands from the pad land.
13
IRDC3473
Stencil Design
The Stencil apertures for the lead lands should be approximately 80% of the area of the lead lads. Reducing the
amount of solder deposited will minimize the occurrences of lead shorts. If too much solder is deposited on the
center pad, the part will float and the lead lands will open.
The maximum length and width of the land pad stencil aperture should be equal to the solder resist opening minus
an annular 0.2mm pull back in order to decrease the risk of shorting the center land to the lead lands when the part
is pushed into the solder paste.
14
IRDC3473
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information
Data and specifications subject to change without notice. 02/2011
15