IRDC3876 SupIRBuck TM USER GUIDE FOR IR3876 EVALUATION BOARD DESCRIPTION The IR3876 SupIRBuckTM is an easy-to-use, fully integrated and highly efficient DC/DC voltage regulator. The onboard constant on time hysteretic controller and MOSFETs make IR3876 a space-efficient solution that delivers up to 12A of precisely controlled output voltage at 60°C ambient temperature without airflow. IR3876 is housed in a 20-lead 5mmx6mm QFN package. Additional features include pre-bias startup, a very precise 0.5V reference, over/under voltage protection, power good output, and enable input with voltage monitoring capability. This user guide contains the schematic, bill of materials, and operating instructions of the IR3876 evaluation board. Detailed application information for IR3876 is available in the IR3876 data sheet. Key features offered by IR3876 include: programmable switching frequency, soft start, and over current protection allowing a very flexible solution suitable for many different applications and an ideal choice for battery powered applications. BOARD FEATURES • • • • • • • VIN = +12.6V VCC = +5V VOUT = +1.05V @ 0 ~ 12A FS = 300kHz @ CCM L = 1.0µH CIN = 22µF (ceramic 1210) + 68µF (electrolytic) COUT = 47µF (ceramic 0805) + 330µF (SP-Cap) 1 IRDC3876 CONNECTIONS and OPERATING INSTRUCTIONS An input supply in the range of 7 to 16V should be connected from VIN to PGND. A maximum load of 12A may be connected to VOUT and PGND. The connection diagram is shown in Fig. 1, and the inputs and outputs of the board are listed in Table 1. IRDC3876 has two input supplies, one for biasing (VCC) and the other for input voltage (VIN). Separate supplies should be applied to these inputs. VCC input should be a well regulated 4.5V to 5.5V supply connected to VCC and PGND. Enable (EN) is controlled by the first switch of SW1. Toggle the switch to the ON position (marked by a solid square) to enable switching. The absolute maximum voltage of the external signal applied to EN (TP4) is +8V. Table 1. Connections Connection Signal Name VIN (TP2) VIN PGND (TP5) Ground for VIN VCC (TP16) VCC Input PGND (TP17) Ground for VCC Input VOUT (TP7) VOUT (+1.05V) PGND (TP10) Ground for VOUT EN (TP4) Enable Input AGND (TP26) Ground for Enable LAYOUT The PCB is a 4-layer board. All layers are 1 oz. copper. IR3876 and other components are mounted on the top and bottom layers of the board. The power supply decoupling capacitors, bootstrap capacitor and feedback components are located close to IR3876. To improve efficiency, the circuit board is designed to minimize the length of the onboard power ground current path. 2 IRDC3876 CONNECTION DIAGRAM VIN = +12.6V GROUND EN GROUND VCC = +5.0V GROUND VOUT = +1.05V Fig. 1: Connection Diagram of IR3876 Evaluation Board 3 IRDC3876 PCB Board Layout Fig. 2: Board Layout, Top Components Single point connection between analog and power ground. Fig. 3: Board Layout, Bottom Components 4 IRDC3876 PCB Board Layout Fig. 4: Board Layout, Top Layer Fig. 5: Board Layout, Bottom Layer 5 IRDC3876 PCB Board Layout Fig. 6: Board Layout, Mid-layer I Fig. 7: Board Layout, Mid-layer II 6 SW1 EN / FCCM 4 3 1 2 TP19 FB R10 open R9 0 TP11 PGOOD +Vdd2s TP17 PGND TP16 VCC TP26 AGND C23 open VCC -Vdd2s +3.3V TP14 +3.3V NC1 SS FB GND1 PGOOD ISET NC C21 1uF R3 200K 15 C25 1uF IR3876 13 PHASE C22 open -Vdd1s 2 TP20 +Vin1s +Vdd1s -Vout1s 12 U1 IR3876 C4 0.1uF +Vin1s 5 L1 1.0uH TP22 +Vsws C14 open TP25 -Vin1s TP15 -Vout1s TP21 -Vsws TP12 VSWS R6 open VSW VIN C13 open C1 1uF R12 open R11 open R8 2.55K R7 2.80K TP9 +Vout1s VOUT C2 22uF C24 open + C3 68uF R13 open C15 open C6 open -Vins Fig. 8: Schematic of the IR3876 Evaluation Board 7 6 C20 0.1uF 5 4 3 2 SS PGOOD 1 FB C5 open ISET TP13 SS R5 10K +3.3V VSW R4 7.87K FCCM EN 16 EN TP4 EN 17 GND 3V3BP 8 FF VCC 10 NC2 9 14 BOOT TP3 FCCM 3 VIN PGND 11 1 4 R2 10K R14 open C16 open C7 open C17 open C8 open TP6 PGNDS TP1 VINS C18 open C9 330uF TP5 PGND TP2 VIN C19 open C10 47uF C26 open C11 open C12 0.1uF C27 open 1 +Vins -Vdd1s +Vin1s R1 open -Vdd2s 2 TP23 +Vsws 1 3 +3.3V -Vout1s 6 -Vins +Vins 7 2 -Vdd1s -Vout1s 9 +Vdd1s +Vdd1s 8 -Vdd2s +Vdd2s 3 +Vdd2s +Vout1s -Vout1s 4 Vout 10 +Vout2s -Vout2s 5 TP10 PGND 5 TP8 VOUTS TP7 VOUT TP18 VOLTAGE SENSE TP24 +Vsws 4 VCC IRDC3876 7 IRDC3876 Bill of Materials Quantity 3 1 1 1 1 3 1 2 1 1 1 1 1 1 1 Reference C1, C21, C25 C2 C3 C9 C10 C4, C12, C20 L1 R2, R5 R9 R3 R4 R7 R8 SW1 U1 Value 1uF 22uF 68uF 330uF 47uF 0.1uF 1uH 10K 0 200K 7.87K 2.8K 2.55K SPST IR3876 Description CAP,CER,1.0uF,25V,X7R,0603 CAP,22uF,25V,CERAMIC,X5R,1210 CAP,68uF,25V,ELECT,FK,SMD SP-CAP, 330uF, 2V, 4.5mΩ, 20% CAP,CER,47uF,6.3V,X5R,0805 CAP,CER,0.1uF,50V,10%,X7R,0603 INDUCTOR, 1uH, 20A, 2.7mΩ,SMD RES,10.0kΩ,1/10W,1%,0603,SMD RES,0Ω,1/10W,1%,0603,SMD RES,200kΩ,1/10W,1%,0603,SMD RES,7.87kΩ,1/10W,1%,0603,SMD RES,2.8kΩ,1/10W,1%,0603,SMD RES,2.55kΩ,1/10W,1%,0603,SMD SWITCH, DIP, SPST, SMT 5mm x 6mm QFN Manufacturer Murata Electronics Panasonic Panasonic Panasonic TDK TDK CYNTEC Vishay/Dale Vishay/Dale Vishay/Dale Vishay/Dale Vishay/Dale Vishay/Dale C&K Components IR Part-Number GRM188R71E105KA12D ECJ-4YB1E226M EEV-FK1E680P EEF-SX0D331E4 C2012X5R0J476M C1608X7R1H104K PIMB103E-1R0MS-39 CRCW060310K0FKEA CRCW06030000Z0EAHP CRCW0603200KFKEA CRCW06037K87FKEA CRCW06032K80FKEA CRCW06032K55FKEA SD02H0SK IR3876MPBF 8 IRDC3876 TYPICAL OPERATING WAVEFORMS Tested with demoboard shown in Fig. 8, VIN = 12.6V, VCC = 5V, VOUT = 1.05V, Fs = 300kHz, TA = 25oC, no airflow, unless otherwise specified EN EN PGOOD PGOOD SS SS VOUT VOUT 5V/div 5V/div 1V/div 500mV/div Fig. 9: 5ms/div 5V/div 5V/div 1V/div 500mV/div Fig. 10: Startup1 200µs/div Shutdown1 VOUT VOUT PHASE PHASE iL iL 20mV/div 5V/div 2A/div Fig. 11: DCM (IOUT = 10µs/div 0.1A)2 20mV/div 5V/div 5A/div 2µs/div Fig. 12: CCM (IOUT = 12A)2 PGOOD PGOOD SS FB VOUT VOUT IOUT iL 5V/div 1V/div 1V/div 10A/div 2ms/div Fig. 13: Over Current Protection (tested by shorting VOUT to PGND) 5V/div 1V/div 500mV/div 2A/div 50µs/div Fig. 14: Over Voltage Protection (tested by shorting FB to VOUT) Note1: EN is pulled up to VCC after VIN = 12.6V and VCC = 5V are applied. Note2: VOUT ripple is measured across the 47µF output capacitor. 9 IRDC3876 TYPICAL OPERATING WAVEFORMS Tested with demoboard shown in Fig. 8, VIN = 12.6V, VCC = 5V, VOUT = 1.05V, Fs = 300kHz, TA = 25oC, no airflow, unless otherwise specified VOUT VOUT PHASE PHASE iL iL 50mV/div 10V/div 5A/div 20µs/div Fig. 15: Load Transient 0-8A 50mV/div 10V/div 5A/div 20µs/div Fig. 16: Load Transient 4-12A TYPICAL PERFORMANCE VIN = 12.6V, VCC = 5V, VOUT = 1.05V, Fs = 300kHz, IOUT = 12A, TA = 25oC, no airflow Fig. 17: Thermal Image (IR3876: 81oC, Inductor: 58oC, PCB: 54oC) 10 IRDC3876 TYPICAL OPERATING DATA 95% 350 85% 300 Frequency (kHz) Efficiency VIN = 12.6V, VCC = 5V, VOUT = 1.05V, Fs = 300kHz, IOUT = 0 ~ 12A, TA = 25oC, no airflow, unless otherwise specified 75% 65% 55% 45% 250 200 150 100 50 35% 0.01 0 0.1 1 10 100 0 2 4 Output Current (A) 8 10 12 Output Current (A) Fig. 18: Efficiency vs. Output Current Fig. 19: Switching Frequency vs. Output Current 1.058 Output Voltage (V) 1.058 Output Voltage (V) 6 1.057 1.056 1.055 1.057 1.056 1.055 1.054 1.054 0 2 4 6 8 Output Current (A) Fig. 20: Load Regulation 10 12 6 7 8 9 10 11 12 13 14 15 16 17 Input Voltage (V) Fig. 21: Line Regulation at 12A Load 11 IRDC3876 PCB Metal and Components Placement Lead lands (the 13 IC pins) width should be equal to nominal part lead width. The minimum lead to lead spacing should be ≥ 0.2mm to minimize shorting. Lead land length should be equal to maximum part lead length + 0.3 mm outboard extension. The outboard extension ensures a large toe fillet that can be easily inspected. Pad lands (the 4 big pads) length and width should be equal to maximum part pad length and width. However, the minimum metal to metal spacing should be no less than; 0.17mm for 2 oz. Copper or no less than 0.1mm for 1 oz. Copper or no less than 0.23mm for 3 oz. Copper. 12 IRDC3876 Solder Resist It is recommended that the lead lands are Non Solder Mask Defined (NSMD). The solder resist should be pulled away from the metal lead lands by a minimum of 0.025mm to ensure NSMD pads. The land pad should be Solder Mask Defined (SMD), with a minimum overlap of the solder resist onto the copper of 0.05mm to accommodate solder resist misalignment. Ensure that the solder resist in between the lead lands and the pad land is ≥ 0.15mm due to the high aspect ratio of the solder resist strip separating the lead lands from the pad land. 13 IRDC3876 Stencil Design The Stencil apertures for the lead lands should be approximately 80% of the area of the lead lads. Reducing the amount of solder deposited will minimize the occurrences of lead shorts. If too much solder is deposited on the center pad the part will float and the lead lands will open. The maximum length and width of the land pad stencil aperture should be equal to the solder resist opening minus an annular 0.2mm pull back in order to decrease the risk of shorting the center land to the lead lands when the part is pushed into the solder paste. 14 IRDC3876 DIM A A1 b b1 c D E e e1 e2 MILIMITERS MIN MAX 0.800 1.000 0.000 0.050 0.375 0.475 0.250 0.350 0.203 REF. 5.000 BASIC 6.000 BASIC 1.033 BASIC 0.650 BASIC 0.852 BASIC INCHES MIN MAX 0.0315 0.0394 0.0000 0.0020 0.1477 0.1871 0.0098 0.1379 0.008 REF. 1.969 BASIC 2.362 BASIC 0.0407 BASIC 0.0256 BASIC 0.0335 BASIC DIM L M N O P Q R S t1, t2, t3 t4 t5 MILIMITERS MIN MAX 0.350 0.450 2.441 2.541 0.703 0.803 2.079 2.179 3.242 3.342 1.265 1.365 2.644 2.744 1.500 1.600 0.401 BASIC 1.153 BASIC 0.727 BASIC INCHES MIN MAX 0.0138 0.0177 0.0961 0.1000 0.0277 0.0316 0.0819 0.0858 0.1276 0.1316 0.0498 0.0537 0.1041 0.1080 0.0591 0.0630 0.016 BACIS 0.045 BASIC 0.0286 BASIC IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information Data and specifications subject to change without notice. 05/2012 15