HT1585 Real Time Clock Module Features General Description • Integrated 32768Hz high stability oscillator This device is a real time clock with full temperature compensation function capable of providing an accurate time source for a wide range of applications. The device includes a fully integrated 32768Hz oscillator and has an I2C bus interface for external communication. In addition to providing a full calendar function including, year, month, date, day, hour, minute and second function, the device also includes a clock counter function and a range of other functions such as alarm function, fixed-cycle timer function, time update interrupt function. An output which generates a fixed 32768Hz output is also provided for additional flexibility. Fabricated using CMOS technology the devices have low power consumption which allow for long-term battery backup. The device is supplied in an SOP package type. 2 • Integrated 400kHz high speed I C • Alarm interrupt function – day, date, hour. and minute settings • Fixed-cycle timer interrupt function • Time update interrupt function – seconds, minutes • 32768Hz output with CE function • Auto leap year correction – years 2000 to 2099 • Wide interface voltage range: 1.6V to 5.5V • Low current consumption: typically 0.8μA at 3V • 14-pin SOP package Block Diagram Rev. 1.00 1 December 25, 2014 HT1585 Pin Assignment Pin Description Pin Name Type Description FOUT O FOUT: Frequency output FOE I FOE: FOUT output enable control pin 0: FOUT disabled 1: FOUT enabled SDA – SDA: I2C address/data pin NC – Test pin – leave open circuit SCL I SCL: I2C clock input pin INT OD RTC open drain interrupt output AVDD/VDD PWR Digital positive power supply AVSS/VSS PWR Analog negative power supply Pin type legend: PWR: power supply I: Logic Input O: Logic Output OD: Open Drain Absolute Maximum Ratings Supply Voltage ............................VSS-0.3V to VSS+6.0V IOL Total ............................................................ 150mA Input Voltage ............................ VSS-0.3V to VDD+0.3V IOH Total............................................................ -100mA Storage Temperature ........................... -50°C to 125°C Total Power Dissipation................................... 500mW Operating Temperature.......................... -40°C to 85°C Note: These are stress ratings only. Stresses exceeding the range specified under "Absolute Maximum Ratings" may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability. Rev. 1.00 2 December 25, 2014 HT1585 D.C. Characteristics Symbol *Unless otherwise specified. GND=0V, VDD=1.8V to 5.5V, Ta=-40 to +85°C Test Condition Parameter VDD Condition Min. Typ. Max. — 1.2 3.4 — 1.0 2.1 Unit IDD1 Current Consumption. I2C Inactive, 5V fSCL=0Hz, INT=VDD, FOE=GND FOUT Inactive. Temperature FOUT: output Off (High Z) Compensation Active 3V Compensation interval 2.0s IDD2 Current Consumption. I2C Inactive, 5V fSCL=0Hz, INT=VDD, FOE=GND FOUT Active, Temperature FOUT: 32.768kHz, CL=0pF Compensation Active 3V Compensation interval 2.0s — 3 7.5 — 2 5 IDD3 Current Consumption. I2C Inactive, 5V fSCL=0Hz, INT=VDD, FOE=GND Temperature Compensation FOUT: 32.768kHz, CL =30pF Active, FOUT Active 3V Compensation interval 2.0s — 8.2 20 — 5.2 12 IDD4 Current Consumption. I2C Inactive, 5V fSCL=0Hz, INT=VDD, FOE=GND FOUT Inactive, Temperature FOUT: output Off ( High Z) Compensation Inactive 3V Compensation Off — 1.15 2.95 — 0.75 1.85 IDD5 Current Consumption. I2C Inactive, 5V fSCL=0Hz, INT=VDD, FOE=GND FOUT Inactive, Temperature FOUT: output Off ( High Z) Compensation Active 3V Compensation On ( peak) — 430 900 — 180 350 FOE pin 0.8 × VDD — VDD + 0.3 SCL and SDA pins 0.7 × VDD — 5.5 FOE pin 0 — 0.2 × VDD SCL and SDA pins 0 — 0.3 × VDD Min. Typ. Max. Unit VIH VIL High-level Input Voltage — Low-level Input Voltage — µA µA µA µA µA V V RTC Recommended Operating Conditions Symbol Parameter Condition VDD Operating supply voltage Interface voltage 1.6 3.0 5.5 V VTEMP Temp. compensation voltage Temperature compensation voltage 2.7 3.0 5.2 V VCLK Clock supply voltage 1.6 3.0 5.5 V TOPR Operating temperature -40 +25 +85 °C — No condensation Frequency Characteristics Symbol Parameter Δf/f Frequency stability f/V Frequency/voltage characteristics tSTART Oscillation start time fYEAR Aging Rev. 1.00 Test Condition VDD Condition Min. Typ. Max. Unit 3V Ta= 0 ~ +50°C — ±3.8 — ×10-6 3V Ta= -40 ~ +85°C — ±5.0 — ×10-6 2.7V~ Ta= +25°C 5.2V — — ±1.0 ×10-6/V 1.6V Ta= +25°C — — 1.0 s 1.6V~ Ta= -40 ~ +85°C 5.5V — — 3.0 s — — ±3 ×10-6/ year 3V Ta= 25°C, first year 3 December 25, 2014 HT1585 A.C. Characteristics Symbol tFOUTD *Unless otherwise specified. GND=0V, VDD=1.8V to 5.5V, Ta=-40 to +85°C Parameter Remark FOUT duty 50% of VDD level Min. Typ. Max. Unit 40 50 60 % I2C Interface Remark Min. Typ. Max. Unit fSCL Symbol Clock frequency Parameter ― ― ― 400 kHz tHIGH Clock High Time ― 600 ― ― ns tLOW Clock Low Time ― 1300 ― ― ns tr SDA and SCL Rise Time Note ― ― 300 ns tf SDA and SCL Fall Time Note ― ― 300 ns tHD:STA START Condition Hold Time After this period, the first clock pulse is generated. 600 ― ― ns tSU:STA START Condition Setup Time Only relevant for repeated START condition. 600 ― ― ns tHD:DAT Data Input Hold Time ― 0 ― ― ns tSU:DAT Data Input Setup Time ― 100 ― ― ns tSU:STO STOP Condition Setup Time ― 600 ― ― ns tAA Output Valid from Clock ― ― ― 900 ns 1300 ― ― ns ― ― 50 ns tBUF Bus Free Time Time in which the bus must be free before a new transmission can start tSP Input Filter Time Constant (SDA and SCL Pins) Noise suppression time Note: These parameters are periodically sampled but not 100% tested. I2C Timing Diagram SDA tBUF tSU:DAT tf tLOW tHD:STA tr tSP SCL tHD:SDA S tHD:DAT tHIGH tSU:STA tAA tSU:STO P Sr S SDA OUT Backup and Recovery Symbol Condition Min. Typ. Max. Unit VDET Power Supply Detection for Stopping Temperature Compaersation — — — 2.2 V VLOW Power Supply Detection for Low voltage — — — 1.8 V Rev. 1.00 Parameter 4 December 25, 2014 HT1585 Functional Description change to a high level and the INT pin will change to a low level. This will only happen if the TUIE bit in the interrupt control register is high. After a 500ms or 7.89ms time interval the INT will be cleared automatically to a high impedance state. Clock Functions Data for the month, day, hour, date, minute, second and the last two digits of the year data is setup and read out using this function. With regard to the special case of leap years note that any two digit year that is a multiple of 4 will be seen as a leap year. Its value will be worked out automatically with a maximum value of year 2099. Alarm Interrupt Function There is a function called the alarm interrupt that will generate an interrupt when a previously setup alarm condition occurs. The alarm can be setup for date, day, hour, and minutes. When such an interrupt is generated the ALF bit will be set high and the INT pin will change to a low level. Fixed-cycle Interrupt Generation Function There is a function, called the fixed cycle interrupt, that will generate a timer interrupt at fixed time events for any set value between 244.14 us and 4095 minutes. When the interrupt occurs, the external INT pin will change to a low level. At the same time the TF bit will be set high to indicate that an interrupt has occurred. Note that the INT pin low level will only happen if the FCTIE bit in the interrupt control register is high. The INT status will be cleared automatically 7.8ms after the interrupt occurs. When this happens the INT pin will be placed into a high impedance state. 32.768kHz Clock Output The FOUT pin is a CMOS output pin which can be used to output the 32768Hz clock signal. The FOUT pin will output this clock if the FOE pin is set to a high level. The FOUT pin will be low if the FOE pin is high impedance. Interfacing to an external MCU The time data in the device is read out and written using an external MCU using the SCL and SDA lines of its l2C bus. As there are no protection diodes connected to VDD on the SCL and SDA lines, these two lines can be interfaced to external MCU bus lines which have different supply voltages. When VDD≥1.8V, the maximum SCL clock frequency is 400kHz, which means it can support the I2C bus high-speed mode. Time Update Interrupt Function There is a function called the time update interrupt that will generate fixed interrupts at one-second or one-minute intervals. These interrupt occur in accordance to the internal clock timing. When one of these interrupts is generated, the TUF bit value will Register Description The following is an overall register map of the device. Address (I2C) Name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 00H SECOND — SEC40 SEC20 SEC10 SEC8 SEC4 SEC2 SEC1 01H MINUTE — MIN40 MIN20 MIN10 MIN8 MIN4 MIN2 MIN1 02H HOUR — — HOUR20 HOUR10 HOUR8 HOUR4 HOUR2 HOUR1 03H WEEK — SAT FRI THU WED TUE MON SUN 04H DAY — — DAY20 DAY10 DAY8 DAY4 DAY2 DAY1 05H MONTH — — — MONTH10 MONTH8 MONTH4 MONTH2 MONTH1 06H YEAR YEAR80 YEAR40 YEAR20 YEAR10 YEAR8 YEAR4 YEAR2 YEAR1 07H RTC_DR D7 D6 D5 D4 D3 D2 D1 D0 08H AL_MIN MIN_AE M40A M20A M10A M8A M4A M2A M1A 09H AL_HOUR HOUR_AE reg H20A H10A H8A H4A H2A H1A 0AH AL_WK_ DY WD_AE W6A W5D20A W4D10A W3D8A W2D4A W1D2A W0D1A 0BH FCTL D7 D6 D5 D4 D3 D2 D1 D0 0CH FCTH reg reg reg reg D11 D10 D9 D8 0DH RTC_EXT RTC_TEST ALWD TUISEL FCTE FOSEL1 FOSEL0 FCTS1 FCTS0 0EH RTC_FLAG — — TUF FCTF ALF — VLF VDF 0FH RTC_CTRL CISEL1 CISEL0 TUIE FCTIE ALIE — — RTC_RST Rev. 1.00 5 December 25, 2014 HT1585 Register Details The following gives a description of the registers and their associated bits. SECOND Register Bit Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Name ― SEC40 SEC20 SEC10 SEC8 SEC4 SEC2 SEC1 R/W ― R/W R/W R/W R/W R/W R/W R/W POR ― x x x x x x x 'x': unknown '–': unimplemented, read as'0' Bit 7 Unimplemented, read as "0" Bit 6~0 This register is a BCD format counter. It counts from "00" to "59", after which it starts again from 00. Note with caution that writing non-existent time data may interfere with normal operation of the clock counter. MINUTE Register Bit Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Name ― MIN40 MIN20 MIN10 MIN8 MIN4 MIN2 MIN1 R/W ― R/W R/W R/W R/W R/W R/W R/W POR ― x x x x x x x 'x': unknown '–': unimplemented, read as'0' Bit 7 Unimplemented, read as "0" Bit 6~0 This register is a BCD format counter. It counts from "00" to "59", after which it starts again from 00. Note with caution that writing non-existent time data may interfere with normal operation of the clock counter. HOUR Register Bit Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Name ― ― HOUR20 HOUR10 HOUR8 HOUR4 HOUR2 HOUR1 R/W ― ― R/W R/W R/W R/W R/W R/W POR ― ― x x x x x x 'x': unknown '–': unimplemented, read as'0 Bit 7~6 Unimplemented, read as "0" Bit 5~0 This register is a BCD format counter. It counts from "00" to "23", after which it starts again from 00. Note with caution that writing non-existent time data may interfere with normal operation of the clock counter. WEEK Register Bit Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Name ― SAT FRI THU WED TUE MON SUN R/W ― R/W R/W R/W R/W R/W R/W R/W POR ― x x x x x x x 'x': unknown '–': unimplemented, read as'0 Bit 7 Unimplemented, read as "0" Bit 6~0 The day of the week. Don’t set "1" to more than one day at the same time. Rev. 1.00 6 December 25, 2014 HT1585 DAY Register Bit Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Name ― ― DAY20 DAY10 DAY8 DAY4 DAY2 DAY1 R/W ― ― R/W R/W R/W R/W R/W R/W POR ― ― x x x x x x 'x': unknown '–': unimplemented, read as'0 Bit 7~6 Unimplemented, read as "0" Bit 5~0 This register is a BCD format counter. It counts from "00" to "31", after which it starts again from 00. MONTH Register Bit Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Name ― ― ― MONTH10 MONTH8 MONTH4 MONTH2 MONTH1 R/W ― ― ― R/W R/W R/W R/W R/W POR ― ― ― x x x x x 'x': unknown '–': unimplemented, read as'0' Bit 7~5 Unimplemented, read as "0" Bit 4~0 This register is a BCD format counter. It counts from "00" to "12", after which it starts again from 00. YEAR Register Bit Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Name YEAR80 YEAR40 YEAR20 YEAR10 YEAR8 YEAR4 YEAR2 YEAR1 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR x x x x x x x x 'x': unknown Bit 7~0 This register is a BCD format counter. It counts from "00" to "99", after which it starts again from 00. RTC_DR Register Bit Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Name D7 D6 D5 D4 D3 D2 D1 Bit0 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR x x x x x x x x 'x': unknown Bit 7~0 Read/write data 00h~FFh. AL_MIN Register Bit Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Name MIN_AE M40A M20A M10A M8A M4A M2A M1A R/W R/W R/W R/W R/W R/W R/W R/W R/W POR x x x x x x x x 'x': unknown Bit 7 Every minute alarm enable. 0: alarm only at minute match 1: every minute alarm enable Bit 5~0 Minute setting from "00" to "59" for alarm. Rev. 1.00 7 December 25, 2014 HT1585 AL_HOUR Register Bit Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Name HOUR_AE ― H20A H10A H8A H4A H2A H1A R/W R/W ― R/W R/W R/W R/W R/W R/W POR x ― x x x x x x 'x': unknown '–': unimplemented, read as'0' Bit 7 Every hour alarm enable. 0: alarm only during an hour match 1: every hour alarm enable Bit 6 dummy register. Bit 5~0 Hour setting from "00" to "23" for alarm. AL_WK_DY Register Bit Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Name WD_AE W6A W5D20A W4D10A W3D8A W2D4A W1D2A W0D1A R/W R/W R/W R/W R/W R/W R/W R/W R/W POR x x x x x x x x 'x': unknown Bit 7 every week/day alarm enable.(depend on WADA) 0: alarm only at week/day match (depend on WADA) 1: every day alarm enable Bit 6~0 Week/day setting for alarm. FCTL Register Bit Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Name D7 D6 D5 D4 D3 D2 D1 Bit0 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR x x x x x x x x 'x': unknown '–': unimplemented, read as'0' Bit 7~0 Fixed-cycle timer low byte value. FCTH Register Bit Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Name ― ― ― ― D11 D10 D9 Bit0 D8 R/W ― ― ― ― R/W R/W R/W R/W POR ― ― ― ― x x x x 'x': unknown '–': unimplemented, read as'0' Bit 7~4 dummy register. Bit 3~0 Fixed-cycle timer high byte value. Rev. 1.00 8 December 25, 2014 HT1585 RTC_EXT Register Bit Bit7 Bit6 Bit5 Bit4 Bit3 Name RTC_TEST ALED UISEL FCTE FOUTSEL1 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 x x x 0 0 x x Bit 7 Bit2 Bit1 Bit0 FOUTSEL0 FCTSEL1 FCTSEL0 RTC_TEST: Test bit. Its value should always be "0". 0: Normal operation 1: Setting prohibited Bit 6 ALED: Week Alarm/Day Alarm bit 0: WEEK is the comparison object 1: DAY is the comparison object Bit 5 UISEL: Update Interrupt Select bit 0: second update 1: minute update Bit 4 FCTE: This bit controls the start/stop setting for the fixed-cycle timer interrupt function. Writing a "1" to this bit specifies starting of the fixed-cycle timer interrupt function (a countdown starts from a preset value). Writing a "0" to this bit specifies stopping of the fixed-cycle timer interrupt function. Bit 3~2 FOUTSEL1~0: freq. select bits 00: 32768Hz output 01: 1024Hz output 10: 1Hz output 11: 32768Hz output Bit 1~0 FCTSEL1~0: set the countdown period (source clock) for the fixed-cycle timer interrupt function 00: 4096Hz/Once per 244.14us 01: 64Hz/Once per 15.625ms 10: "Second" update/Once per second 11: "Minute" update/Once per minute Rev. 1.00 9 December 25, 2014 HT1585 RTC_FLAG Register Bit Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Name ― ― TUF FCTF ALF ― VLF VDF R/W ― ― R/W0 R/W0 R/W0 ― R/W0 R/W0 POR ― ― x x x ― 1 1 'x': unknown '–': unimplemented, read as'0' Bit 7~6 unimplemented, read as'0' Bit 5 TUF: Time updated interrupt request flag Write "1" invalid. 0: no request 1: interrupt request Bit 4 FCTF: Fixed-cycke timer interrupt request flag 0: no request 1: interuupte request Bit 3 ALF: Alarm interrupt request flag 0: no request 1: interrupt request Bit 2 unimplemented, read as '0' Bit 1 VLF: Voltage Low interrupt request flag 0: no request 1: Interrupt request. Data is lost and all registers must be ininialised. Bit 0 VDF: Voltage drop detection interrupt request flag for temperature compensation 0: No request. Temperature compensation is normal. 1: Interrupt request. Temperature compensation is stopped. Note: The interrupt reuest flags will not be automatically reset and must be manually reset by the application program. RTC_CTRL Register Bit Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Name CISEL1 CISEL0 TUIE FCTIE ALIE ― ― RTC_RST R/W R/W R/W R/W R/W R/W ― ― R/W POR 0 1 x x x ― ― x 'x': unknown '–': unimplemented, read as'0' Bit 7~6 CISEL1~0: Compensation Interval Select 00: 0.5s 01: 2.0s 10: 10s 11: 30s Bit 5 TUIE: Time updated interrupt control bit enable 0: disable 1: enable Bit 4 FCTIE: Fixed-cycle timer interrupt control bit 0: disable 1: enable Bit 3 ALIE: Alarm interrupt control bit 0: disable 1: enable Bit 2~1 unimplemented, read as'0' Bit 0 Rev. 1.00 RTC_RST: RTC reset bit 0: Restart RTC operation 1: Stop RTC operation 10 December 25, 2014 HT1585 I2C Serial Interface Byte Format 2 Every byte put on the SDA line must be 8-bits long. The number of bytes that can be transmitted per transfer is unrestricted. Each byte has to be followed by an acknowledge bit. Data is transferred with the most significant bit (MSB) first. 2 The HT1385 includes an I C serial interface. The I C bus is used for bidirectional, two-line communication between multiple I2C devices. The two lines of the interface are the serial data line (SDA) and the serial clock line (SCL). Both lines are connected to the positive supply via a pull-up resistor externally. Sr When the bus is free, both lines will be high. The output stages of the devices connected to the bus must have open-drain or open-collector output types to implement the wired-AND function necessary for connection. Data transfer is initiated only when the bus is not busy. SCL SCL Data line stable; Change of data Data valid allowed START and STOP Conditions A HIGH to LOWtransition on the SDA line while SCL is HIGH defines a START condition. A LOW to HIGH transition on the SDA line while SCL is HIGH defines a STOP condition. START and STOP conditions are always generated by the master. The bus is considered to be busy after the START condition. The bus is considered to be free again a certain time after the STOP condition. The bus stays busy if a repeated START(Sr) is generated instead of a STOP condition. In this respect, a START(S) and repeated START(Sr) conditions are functionally identical. 7 8 9 1 2 3-8 P or Sr 9 ACK ACK DATA OUTPUT BY TRANSMITER not acknowledge DATA OUTPUT BY RECEIVER acknowledge SCL FROM MASTER 1 S 2 7 8 START condition 9 clk pulse for acknowledgement Device Addressing The slave address byte is the first byte received following the START condition from the master device. The first seven bits of the first byte make up the slave address. The eighth bit defines a read or write operation to be performed. When this R/W bit is “1”, then a read operation is selected. A “0” selects a write operation. The device address bits are “1101000”. When an address byte is sent, the device compares the first seven bits after the START condition. If they match, the device outputs an acknowledge on the SDA line. SDA SCL S 2 The acknowledging device must first pull down the SDA line during the acknowledge clock pulse so that it remains LOW during the HIGH period of this clock pulse. Amaster receiver must signal an end of data to the slave by generating a not-acknowledge (NACK) bit on the last byte that has been clocked out of the slave. In this case, the master receiver must leave the data line HIGH during the 9th pulse to not acknowledge. The master will generate a STOP or repeated START condition. SDA START condition 1 Each bytes of eight bits is followed by one acknowledge bit. This acknowledge bit is a low level placed on the bus by the receiver. The master generates an extra acknowledge related clock pulse. A slave receiver which is addressed must generate an acknowledge (ACK) after the reception of each byte. The data on the SDAline must be stable during the HIGH period of the clock. The HIGH or LOWstate of the data line can only change when the clock signal on the SCL line is LOW. SCL S or Sr Acknowledge Data Validity SDA P SDA P STOP condition MSB 1 LSB 1 0 1 0 0 0 R/W The first byte after the START Rev. 1.00 11 December 25, 2014 HT1585 Write Operation Read Operation • Byte Write Operation A byte write operation requires a START condition, a slave address with R/W bit, a valid Register Address, the required Data and a STOP condition. After each of the three byte transfers, the device responds with an ACK. In this mode, the master reads the device data after setting the slave address. Following the R/W bit (=“0”) and the acknowledge bit, the register address (An) is written to the address W pointer. Next the START condition and slave address are repeated followed by the R/W bit (=“1”). The data which was addressed is then transmitted. The address pointer is only incremented on reception of an acknowledge clock. The device will then place the data at address An+1 on the bus. The master reads and acknowledges the new byte and the address pointer is incremented to “An+2”. After reaching the memory location 0Fh, the pointer will be reset to 00h. This cycle of reading consecutive addresses will continue until the master sends a STOP condition. This cycle of reading consecutive addresses will continue until the master sends a STOP condition. Slave Address Register Address (An) Data (n) P S 1 1 0 1 0 0 0 0 Write ACK ACK ACK Byte Write Sequence • Page Write Operation Following a START condition and slave address, a R/W bit is placed on the bus which indicates to the addressed device that a Register Address will follow which is to be written to the address pointer. The data to be written to the memory follows next and the internal address pointer is incremented to the next address location on the reception of an acknowledge clock. After reaching memory location 0Fh, the pointer will be reset to 00h. Slave Address Register Address(An) Data(n) Data(n+1) ACK ACK ACK ACK P ACK Slave Address Data(n) Data(n+1) Data(n+x) P S 1 1 0 1 0 0 0 1 P ACK Register Address(An) ACK Write Data(n+x) S1 1 0 1 0 0 0 0 Write Slave Address S 1 1 0 1 0 0 0 0 ACK Read ACK ACK ACK ACK Read Sequence ACK Page Write Sequence Application Circuits VDD Schottky Barrier Diode SCL Battery VDD MCU SDA I/O I/O VDD FOUT SCL VDD HT1585 FOE INT SDA VDD VDD Pull-up Resistor VSS SCL SDA Rev. 1.00 12 December 25, 2014 HT1585 Package Information Note that the package information provided here is for consultation purposes only. As this information may be updated at regular intervals users are reminded to consult the Holtek website for the latest version of the package information. Additional supplementary information with regard to packaging is listed below. Click on the relevant section to be transferred to the relevant website page. • Further Package Information (include Outline Dimensions, Product Tape and Reel Specifications) • Packing Meterials Information • Carton information Rev. 1.00 13 December 25, 2014 HT1585 14-pin SOP (209mil) Outline Dimensions Symbol Min. Nom. Max. A 0.301 0.307 0.311 B 0.197 0.209 0.220 C 0.012 0.018 0.020 C' 0.396 0.402 0.413 D ― ― 0.079 E ― 0.050 ― F 0.002 ― G 0.022 0.030 0.037 H 0.004 ― 0.010 α 0° ― 8° Symbol Rev. 1.00 Dimensions in inch Dimensions in mm Min. Nom. Max. A 7.65 7.80 7.90 B 5.00 5.30 5.60 C 0.31 0.45 0.51 C' 10.05 10.20 10.50 D ― ― 2.00 E ― 1.27 ― F 0.05 ― G 0.55 0.75 0.95 H 0.09 ― 0.25 α 0° ― 8° 14 December 25, 2014 HT1585 Copyright© 2014 by HOLTEK SEMICONDUCTOR INC. The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. Holtek's products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw. Rev. 1.00 15 December 25, 2014