XICOR X1205S8I

Preliminary Information
New Features
Repetitive Alarms &
Temperature Compensation
2-Wire™ RTC
X1205
Real Time Clock/Calendar
FEATURES
R
A
• Real Time Clock/Calendar
—Tracks time in Hours, Minutes, and Seconds
—Day of the Week, Day, Month, and Year
• 2 Polled Alarms (Non-volatile)
—Settable on the Second, Minute, Hour, Day of
the Week, Day, or Month
—Repeat Mode (periodic interrupts)
• Oscillator Compensation on chip
—Internal feedback resistor and compensation
capacitors
—64 position Digitally Controlled Trim Capacitor
—6 digital frequency adjustment settings to
±30ppm
• Battery Switch or Super Cap Input
• 2-Wire™ Interface interoperable with I2C*
—400kHz data transfer rate
• Low Power CMOS
—1.25µA Operating Current (Typical)
• Small Package Options
—8-Lead SOIC and 8-Lead TSSOP
Modems
Network Routers, Hubs, Switches, Bridges
Cellular Infrastructure Equipment
Fixed Broadband Wireless Equipment
Pagers / PDA
POS Equipment
Test Meters / Fixtures
Office Automation (Copiers, Fax)
Home Appliances
Computer Products
Other Industrial / Medical / Automotive
Y
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•
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DESCRIPTION
APPLICATIONS
Utility Meters
HVAC Equipment
Audio / Video Components
Set Top Box / Television
EL
•
•
•
•
PR
BLOCK DIAGRAM
32.768kHz
IM
IN
The X1205 device is a Real Time Clock with clock/
calendar, two polled alarms, oscillator compensation,
and battery backup switch.
The oscillator uses an external, low-cost 32.768kHz
crystal. All compensation and trim components are
integrated on the chip. This eliminates several external
discrete components and a trim capacitor, saving
board area and component cost.
The Real-Time Clock keeps track of time with separate
registers for Hours, Minutes, and Seconds. The
Calendar has separate registers for Date, Month, Year
and Day-of-week. The calendar is correct through
2099, with automatic leap year correction.
OSC
Compensation
X1
Frequency
Divider
Oscillator
X2
SDA
Serial
Interface
Decoder
Control
Registers
Status
Registers
(EEPROM)
(SRAM)
Timer
Calendar
Logic
Time
Keeping
Registers
(SRAM)
Compare
Alarm
Mask
SCL
Control
Decode
Logic
1Hz
Alarm Regs
(EEPROM)
8
Interrupt Enable
IRQ
Alarm
*I2C is a Trademark of Philips.
REV 1.0.9 8/29/02
www.xicor.com
Characteristics subject to change without notice.
1 of 22
X1205 – Preliminary Information
The powerful Dual Alarms can be set to any Clock/
Calendar value for a match. For instance, every
minute, every Tuesday, or 5:23 AM on March 21. The
alarms can be polled in the Status Register or provide
a hardware interrupt (IRQ Pin). There is a repeat
mode for the alarms allowing a periodic interrupt.
Figure 1. Recommended Crystal connection
R
The device offers a backup power input pin. This
VBACK pin allows the device to be backed up by battery
or SuperCap. The entire X1205 device is fully
operational from 2.7 to 5.5 volts and the clock/calendar
portion of the X1205 device remains fully operational
down to 1.8 volts (Standby Mode).
X1, X2
The X1 and X2 pins are the input and output,
respectively, of an inverting amplifier. An external
32.768kHz quartz crystal is used with the X1205 to
supply a timebase for the real time clock. The
recommended crystal is a Citizen CFS206-32.768KDZF.
Internal compensation circuitry is included to form a
complete oscillator circuit. Care should be taken in the
placement of the crystal and the layout of the circuit.
Plenty of ground plane around the device and short
traces to X1 and X2 are highly recommended. See
Application section for more recommendations.
Y
DESCRIPTION (continued)
PIN DESCRIPTIONS
8-Pin SOIC
IRQ
VSS
8-Pin TSSOP
8
VCC
7
VBACK
3
6
SCL
4
5
SDA
VBACK
VCC
X1
X2
1
2
3
4
8
7
6
5
SCL
SDA
VSS
IRQ
NC = No internal connection
EL
Serial Clock (SCL)
The SCL input is used to clock all data into and out of
the device. The input buffer on this pin is always active
(not gated).
POWER CONTROL OPERATION
The power control circuit accepts a VCC and a VBACK
input. The power control circuit powers the clock from
VBACK when VCC < VBACK - 0.2V. It will switch back to
power the device from VCC when VCC exceeds VBACK.
Figure 2. Power Control
VCC
Voltage
On
VBACK
In
Off
PR
Serial Data (SDA)
SDA is a bidirectional pin used to transfer data into and
out of the device. It has an open drain output and may
be wire ORed with other open drain or open collector
outputs. The input buffer is always active (not gated).
An open drain output requires the use of a pull-up
resistor. The output circuitry controls the fall time of the
output signal with the use of a slope controlled pulldown. The circuit is designed for 400kHz 2-wire interface speeds.
VBACK
This input provides a backup supply voltage to the
device. VBACK supplies power to the device in the
event the VCC supply fails. This pin can be connected
to a battery, a Supercap or tied to ground if not used.
Interrupt Output – IRQ
This is an interrupt signal output. This signal notifies a
host processor that an alarm has occurred and
requests action. It is an open drain active low output.
REV 1.0.9 8/29/02
X1
X2
IN
X2
1
2
IM
X1
A
X1205
REAL TIME CLOCK OPERATION
The Real Time Clock (RTC) uses an external
32.768kHz quartz crystal to maintain an accurate internal representation of second, minute, hour, day, date,
month, and year. The RTC has leap-year correction.
The clock also corrects for months having fewer than
31 days and has a bit that controls 24 hour or AM/PM
format. When the X1205 powers up after the loss of
both VCC and VBACK, the clock will not operate until at
least one byte is written to the clock register.
Reading the Real Time Clock
The RTC is read by initiating a Read command and
specifying the address corresponding to the register of
the Real Time Clock. The RTC Registers can then be
read in a Sequential Read Mode. Since the clock runs
continuously and a read takes a finite amount of time,
there is the possibility that the clock could change during
www.xicor.com
Characteristics subject to change without notice.
2 of 22
X1205 – Preliminary Information
The CCR is divided into 5 sections. These are:
Y
Alarm 0 (8 bytes; non-volatile)
Alarm 1 (8 bytes; non-volatile)
Control (4 bytes; non-volatile)
Real Time Clock (8 bytes; volatile)
Status (1 byte; volatile)
R
1.
2.
3.
4.
5.
Each register is read and written through buffers. The
non-volatile portion (or the counter portion of the RTC) is
updated only if RWEL is set and only after a valid write
operation and stop bit. A sequential read or page write
operation provides access to the contents of only one
section of the CCR per operation. Access to another section requires a new operation. Continued reads or writes,
once reaching the end of a section, will wrap around to
the start of the section. A read or write can begin at any
address in the CCR.
IM
IN
Writing to the Real Time Clock
The time and date may be set by writing to the RTC
registers. To avoid changing the current time by an
uncompleted write operation, the current time value is
loaded into a separate buffer at the falling edge of the
clock on the ACK bit before the RTC data input bytes,
the clock continues to run. The new serial input data
replaces the values in the buffer. This new RTC value
is loaded back into the RTC Register by a stop bit at
the end of a valid write sequence. An invalid write
operation aborts the time update procedure and the
contents of the buffer are discarded. After a valid write
operation the RTC will reflect the newly loaded data
beginning with the next “one second clock cycle” after
the stop bit is written. The RTC continues to update
the time while an RTC register write is in progress and
the RTC continues to run during any nonvolatile write
sequences. A single byte may be written to the RTC
without affecting the other bytes.
CCR access
The contents of the CCR can be modified by performing a byte or a page write operation directly to any
address in the CCR. Prior to writing to the CCR
(except the status register), however, the WEL and
RWEL bits must be set using a two step process (See
section “Writing to the Clock/Control Registers.”)
A
the course of a read operation. In this device, the time is
latched by the read command (falling edge of the clock
on the ACK bit prior to RTC data output) into a separate
latch to avoid time changes during the read operation.
The clock continues to run. Alarms occurring during a
read are unaffected by the read operation.
PR
EL
Accuracy of the Real Time Clock
The accuracy of the Real Time Clock depends on the
frequency of the quartz crystal that is used as the time
base for the RTC. Since the resonant frequency of a
crystal is temperature dependent, the RTC performance will also be dependent upon temperature. The
frequency deviation of the crystal is a function of the
turnover temperature of the crystal from the crystal’s
nominal frequency. For example, a >20ppm frequency
deviation translates into an accuracy of >1 minute per
month. These parameters are available from the
crystal manufacturer. Xicor’s RTC family provides onchip crystal compensation networks to adjust loadcapacitance to tune oscillator frequency from +116
ppm to –37 ppm when using a 12.5 pF load crystal.
For more detail information see the Application
section.
CLOCK/CONTROL REGISTERS (CCR)
The Control/Clock Registers are located in an area
accessible following a slave byte of “1101111x” and
reads or writes to addresses [0000h:003Fh]. The
clock/control memory map has memory addresses
from 0000h to 003Fh. The defined addresses are
described in the Table 1. Writing to and reading from
the undefined addresses are not recommended.
REV 1.0.9 8/29/02
It is not necessary to set the RWEL bit prior to writing
the status register. Section 5 supports a single byte
read or write only. Continued reads or writes from this
section terminates the operation.
The state of the CCR can be read by performing a random read at any address in the CCR at any time. This
returns the contents of that register location. Additional registers are read by performing a sequential
read. The read instruction latches all Clock registers
into a buffer, so an update of the clock does not
change the time being read. A sequential read of the
CCR will not result in the output of data from the memory array. At the end of a read, the master supplies a
stop condition to end the operation and free the bus.
After a read of the CCR, the address remains at the
previous address +1 so the user can execute a current
address read of the CCR and continue reading the
next Register.
ALARM REGISTERS
There are two alarm registers whose contents mimic the
contents of the RTC register, but add enable bits and
exclude the 24 hour time selection bit. The enable bits
specify which registers to use in the comparison between
the Alarm and Real Time Registers. For example:
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Characteristics subject to change without notice.
3 of 22
X1205 – Preliminary Information
– Setting the Enable Month Bit (EMOn*) bit in combination with other enable bits and a specific alarm
time, the user can establish an alarm that triggers at
the same time once a year.
– The user can set the X1205 to alarm every Wednesday at 8:00 AM by setting the EDWn*, the EHRn*
and EMNn* enable bits to ‘1’ and setting the DWAn*,
HRAn* and MNAn* Alarm registers to 8:00AM
Wednesday.
*n = 0 for Alarm 0: N = 1 for Alarm 1
– A daily alarm for 9:30PM results when the EHRn*
and EMNn* enable bits are set to ‘1’ and the HRAn*
and MNAn* registers are set to 9:30PM.
When there is a match, an alarm flag is set. The occurrence of an alarm can be determined by polling the
AL0 and AL1 bits or by enabling the IRQ output, using
it as hardware flag.
*n = 0 for Alarm 0: N = 1 for Alarm 1
Table 1. Clock/Control Memory Map
Reg
Name
7
6
5
4
003F
Status
SR
BAT
AL1
AL0
0
0037
RTC (SRAM)
Y2K
0
0
Y2K21
0036
DW
0
0
0
0035
YR
Y23
Y22
Y21
0034
MO
0
0
0033
DT
0
0
0032
HR
MIL
0
0031
MN
0
M22
0030
SC
0
S22
0
0
0
0
0
ATR5
IM
AL1E
AL0E
0
DTR
(NONVOLATILE)
ATR
0011
INT
0010
000E
0
Alarm1
(NONVOLATILE) DWA1
000D
MOA1
000B
000A
0009
0008
Alarm0
0
0
RWEL
WEL
RTCF
01h
Y2K13
0
0
Y2K10
20h
0
0
DY2
DY1
DY0
0-6
00h
Y13
Y12
Y11
Y10
0-99
00h
G20
G13
G12
G11
G10
1-12
00h
D20
D13
D12
D11
D10
1-31
00h
H21
H20
H13
H12
H11
H10
0-23
00h
M21
M20
M13
M12
M11
M10
0-59
00h
S21
S20
S13
S12
S11
S10
0-59
00h
0
0
DTR2
DTR1
DTR0
00h
ATR4
ATR3
ATR2
ATR1
ATR0
00h
0
0
X
X
X
00h
0
0
0
0
0
00h
0
0
A1Y2K10
20h
DY2
DY1
DY0
0-6
00h
0
0
0
0
EDW1
0
EMO1
0
0
A1G20
A1G13
A1G12
A1G11
A1G10
1-12
00h
YRA1
000C
0007
Y2K1
PR
000F
1
Y20
IM
Control
0012
2
D21
EL
0013
0
Y2K20
Range
3
IN
Type
A
Bit
Addr.
Default
R
Y
The alarm enable bits are located in the MSB of the
particular register. When all enable bits are set to ‘0’,
there are no alarms.
A1Y2K21 A1Y2K20 A1Y2K13
0
0
0
Unused – Default = RTC Year value – Future expansion
DTA1
EDT1
0
A1D21
A1D20
A1D13
A1D12
A1D11
A1D10
1-31
00h
HRA1
EHR1
0
A1H21
A1H20
A1H13
A1H12
A1H11
A1H10
0-23
00h
MNA1
EMN1
A1M22
A1M21
A1M20
A1M13
A1M12
A1M11
A1M10
0-59
00h
SCA1
ESC1
A1S22
A1S21
A1S20
A1S13
A1S12
A1S11
A1S10
0-59
00h
Y2K0
0
0
0
0
A0Y2K10
19/20
20h
EDW0
0
DY2
DY1
DY0
0-6
00h
0006
(NONVOLATILE) DWA0
0005
YRA0
0004
MOA0
A0Y2K21 A0Y2K20 A0Y2K13
0
0
0
Unused – Default = RTC Year value – Future expansion
EMO0
0
0
A0G20
A0G13
A0G12
A0G11
A0G10
1-12
00h
0003
DTA0
EDT0
0
A0D21
A0D20
A0D13
A0D12
A0D11
A0D10
1-31
00h
0002
HRA0
EHR0
0
A0H21
A0H20
A0H13
A0H12
A0H11
A0H10
0-23
00h
0001
MNA0
EMN0
A0M22
A0M21
A0M20
A0M13
A0M12
A0M11
A0M10
0-59
00h
0000
SCA0
ESC0
A0S22
A0S21
A0S20
A0S13
A0S12
A0S11
A0S10
0-59
00h
REV 1.0.9 8/29/02
www.xicor.com
Characteristics subject to change without notice.
4 of 22
X1205 – Preliminary Information
IM
IN
24 Hour Time
If the MIL bit of the HR register is 1, the RTC uses a
24-hour format. If the MIL bit is 0, the RTC uses a 12hour format and H21 bit functions as an AM/PM indicator with a ‘1’ representing PM. The clock defaults to
standard time with H21=0.
RWEL: Register Write Enable Latch—Volatile
This bit is a volatile latch that powers up in the LOW
(disabled) state. The RWEL bit must be set to “1” prior
to any writes to the Clock/Control Registers. Writes to
RWEL bit do not cause a nonvolatile write cycle, so the
device is ready for the next operation immediately after
the stop condition. A write to the CCR requires both
the RWEL and WEL bits to be set in a specific
sequence.
Y
Date of the Week Register (DW)
This register provides a Day of the Week status and
uses three bits DY2 to DY0 to represent the seven
days of the week. The counter advances in the cycle
0-1-2-3-4-5-6-0-1-2-… The assignment of a numerical
value to a specific day of the week is arbitrary and may
be decided by the system software designer. The
default value is defined as ‘0’.
R
Clock/Calendar Registers (SC, MN, HR, DT, MO, YR)
These registers depict BCD representations of the
time. As such, SC (Seconds) and MN (Minutes) range
from 00 to 59, HR (Hour) is 1 to 12 with an AM or PM
indicator (H21 bit) or 0 to 23 (with MIL=1), DT (Date) is
1 to 31, MO (Month) is 1 to 12, YR (Year) is 0 to 99.
AL1, AL0: Alarm bits—Volatile
These bits announce if either alarm 0 or alarm 1 match
the real time clock. If there is a match, the respective
bit is set to ‘1’. The falling edge of the last data bit in a
SR Read operation resets the flags. Note: Only the AL
bits that are set when an SR read starts will be reset.
An alarm bit that is set by an alarm occurring during an
SR read operation will remain set after the read operation is complete.
A
REAL TIME CLOCK REGISTERS
STATUS REGISTER (SR)
EL
Leap Years
Leap years add the day February 29 and are defined
as those years that are divisible by 4. Years divisible by
100 are not leap years, unless they are also divisible
by 400. This means that the year 2000 is a leap year,
the year 2100 is not. The X1205 does not correct for
the leap year in the year 2100.
PR
The Status Register is located in the CCR memory
map at address 003Fh. This is a volatile register only
and is used to control the WEL and RWEL write
enable latches, read two power status and two alarm
bits. This register is separate from both the array and
the Clock/Control Registers (CCR).
Table 2. Status Register (SR)
Addr
003Fh
Default
7
BAT
0
6
AL1
0
5
AL0
0
4
0
0
3
0
0
2
RWEL
0
1
WEL
0
0
RTCF
1
BAT: Battery Supply—Volatile
This bit set to “1” indicates that the device is operating
from VBACK, not VCC. It is a read-only bit and is set/
reset by hardware (X1205 internally). Once the device
begins operating from VCC, the device sets this bit to
“0”.
REV 1.0.9 8/29/02
WEL: Write Enable Latch—Volatile
The WEL bit controls the access to the CCR and
memory array during a write operation. This bit is a
volatile latch that powers up in the LOW (disabled)
state. While the WEL bit is LOW, writes to the CCR or
any array address will be ignored (no acknowledge will
be issued after the Data Byte). The WEL bit is set by
writing a “1” to the WEL bit and zeroes to the other bits
of the Status Register. Once set, WEL remains set
until either reset to 0 (by writing a “0” to the WEL bit
and zeroes to the other bits of the Status Register) or
until the part powers up again. Writes to WEL bit do
not cause a nonvolatile write cycle, so the device is
ready for the next operation immediately after the stop
condition.
RTCF: Real Time Clock Fail Bit—Volatile
This bit is set to a ‘1’ after a total power failure. This is
a read only bit that is set by hardware (X1205 internally) when the device powers up after having lost all
power to the device. The bit is set regardless of
whether VCC or VBACK is applied first. The loss of only
one of the supplies does not result in setting the RTCF
bit. The first valid write to the RTC after a complete
power failure (writing one byte is sufficient) resets the
RTCF bit to ‘0’.
Unused Bits:
This device does not use bits 3 or 4 in the SR, but
must have a zero in these bit positions. The Data Byte
output during a SR read will contain zeros in these bit
locations.
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Characteristics subject to change without notice.
5 of 22
X1205 – Preliminary Information
INTERRUPT CONTROL REGISTER (INT)
A range from -30ppm to +30ppm can be represented
by using three bits above.
Table 3. Digital Trimming Registers
DTR Register
DTR2
DTR1
DTR0
Estimated frequency
PPM
0
0
0
0 (default)
0
1
0
+10
0
0
1
+20
0
1
1
+30
Pulse Interrupt Mode
The pulsed interrupt mode allows for repetitive or
recurring alarm functionality. Hence an repetitive or
recurring alarm can be set for every nth second, or nth
minute, or nth hour, or nth date, or for the same day of
the week. The pulsed interrupt mode can be considered a repetitive interrupt mode, with the repetition
rate set by the time setting fo the alarm.
1
0
0
0
1
0
-10
1
0
1
-20
1
1
1
-30
IM
IN
A
1
R
Two volatile bits (AL1 and AL0), associated with the two
alarms respectively, indicate if an alarm has happened.
These bits are set on an alarm condition regardless of
whether the IRQ interrupt is enabled. The AL1 and AL0
bits in the status register are reset by the falling edge of
the eighth clock of a read of the register containing the
bits.
Y
Interrupt Control and Status Bits (IM, AL1E, AL0E)
There are two Interrupt Control bits, Alarm 1 Interrupt
Enable (AL1E) and Alarm 0 Interrupt Enable (AL0E) to
specifically enable or disable the alarm interrupt signal
output (IRQ). The interrupts are enabled when either the
AL1E and AL0E bits are set to “1”, respectively.
DTR1 and DTR0 are scale bits. DTR1 gives 10 ppm
adjustment and DTR0 gives 20 ppm adjustment.
The Pulse Interrupt Mode is enabled when the IM bit is
set.
IM Bit
Interrupt / Alarm Frequency
Single Time Event Set By Alarm
1
Repetitive / Recurring Time Event Set By Alarm
EL
0
PR
The Alarm IRQ output will output a single pulse of
short duration (approximately 10-40ms) once the
alarm condition is met. If the interrupt mode bit (IM bit)
is set, then this pulse will be periodic.
Analog Trimming Register (ATR) (Non-volatile)
Six analog trimming Bits from ATR5 to ATR0 are provided to adjust the on-chip loading capacitance range.
The on-chip load capacitance ranges from 3.25pF to
18.75pF. Each bit has a different weight for capacitance adjustment. In addition, using a Citizen CFS-206
crystal with different ATR bit combinations provides an
estimated ppm range from +116ppm to -37ppm to the
nominal frequency compensation. The combination of
digital and analog trimming can give up to +146ppm
adjustment.
The on-chip capacitance can be calculated as follows:
CATR = [(ATR value, decimal) x 0.25pF] + 11.0pF
ON-CHIP OSCILLATOR COMPENSATION
Note that the ATR values are in two’s complement,
with ATR(000000) = 11.0pF, so the entire range runs
from 3.25pF to 18.75pF in 0.25pF steps.
Digital Trimming Register (DTR) — DTR2, DTR1
and DTR0 (Non-Volatile)
The digital trimming Bits DTR2, DTR1 and DTR0
adjust the number of counts per second and average
the ppm error to achieve better accuracy.
The values calculated above are typical, and total load
capacitance seen by the crystal will include approximately 2pF of package and board capacitance in addition to the ATR value.
DTR2 is a sign bit. DTR2=0 means frequency
compensation is > 0. DTR2=1 means frequency
compensation is < 0.
REV 1.0.9 8/29/02
See Application section and Xicor’s Application Note
AN154 for more information.
www.xicor.com
Characteristics subject to change without notice.
6 of 22
X1205 – Preliminary Information
– Write a 06h to the Status Register to set both the
Register Write Enable Latch (RWEL) and the WEL
bit. This is also a volatile cycle. The zeros in the data
byte are required. (Operation preceeded by a start
and ended with a stop).
Stop Condition
All communications must be terminated by a stop
condition, which is a LOW to HIGH transition of SDA
when SCL is HIGH. The stop condition is also used to
place the device into the Standby power mode after a
read sequence. A stop condition can only be issued
after the transmitting device has released the bus. See
Figure 4.
IM
IN
– Write one to 8 bytes to the Clock/Control Registers
with the desired clock, alarm, or control data. This
sequence starts with a start bit, requires a slave byte
of “11011110” and an address within the CCR and is
terminated by a stop bit. A write to the CCR changes
nonvolatile register values so these initiate a nonvolatile write cycle and will take up to 10ms to complete. Writes to undefined areas have no effect. The
RWEL bit is reset by the completion of a nonvolatile
write cycle, so the sequence must be repeated to
again initiate another change to the CCR contents.
If the sequence is not completed for any reason
(by sending an incorrect number of bits or sending a
start instead of a stop, for example) the RWEL bit is
not reset and the device remains in an active mode.
Start Condition
All commands are preceded by the start condition,
which is a HIGH to LOW transition of SDA when SCL
is HIGH. The device continuously monitors the SDA
and SCL lines for the start condition and will not
respond to any command until this condition has been
met. See Figure 4.
Y
– Write a 02h to the Status Register to set the Write
Enable Latch (WEL). This is a volatile operation, so
there is no delay after the write. (Operation preceeded by a start and ended with a stop).
R
Changing any of the nonvolatile bits of the clock/control register requires the following steps:
Clock and Data
Data states on the SDA line can change only during
SCL LOW. SDA state changes during SCL HIGH are
reserved for indicating start and stop conditions. See
Figure 3.
A
WRITING TO THE CLOCK/CONTROL REGISTERS
EL
– Writing all zeros to the status register resets both the
WEL and RWEL bits.
PR
– A read operation occurring between any of the previous operations will not interrupt the register write
operation.
SERIAL COMMUNICATION
Interface Conventions
The device supports a bidirectional bus oriented protocol. The protocol defines any device that sends data
onto the bus as a transmitter, and the receiving device
as the receiver. The device controlling the transfer is
called the master and the device being controlled is
called the slave. The master always initiates data
transfers, and provides the clock for both transmit and
receive operations. Therefore, the devices in this family operate as slaves in all applications.
REV 1.0.9 8/29/02
Acknowledge
Acknowledge is a software convention used to indicate
successful data transfer. The transmitting device,
either master or slave, will release the bus after transmitting eight bits. During the ninth clock cycle, the
receiver will pull the SDA line LOW to acknowledge
that it received the eight bits of data. Refer to Figure 5.
The device will respond with an acknowledge after recognition of a start condition and if the correct Device
Identifier and Select bits are contained in the Slave
Address Byte. If a write operation is selected, the
device will respond with an acknowledge after the
receipt of each subsequent eight bit word. The device
will acknowledge all incoming data and address bytes,
except for:
– The Slave Address Byte when the Device Identifier
and/or Select bits are incorrect
– All Data Bytes of a write when the WEL in the Write
Protect Register is LOW
– The 2nd Data Byte of a Status Register Write
Operation (only 1 data byte is allowed)
www.xicor.com
Characteristics subject to change without notice.
7 of 22
X1205 – Preliminary Information
Figure 3. Valid Data Changes on the SDA Bus
SCL
SDA
Data Change
Data Stable
Y
Data Stable
R
Figure 4. Valid Start and Stop Conditions
A
SCL
Start
Figure 5. Acknowledge Response From Receiver
IM
SCL from
Master
1
Start
PR
Stop
8
EL
Data Output
from Transmitter
Data Output
from Receiver
IN
SDA
9
Acknowledge
In the read mode, the device will transmit eight bits of
data, release the SDA line, then monitor the line for an
acknowledge. If an acknowledge is detected and no
stop condition is generated by the master, the device
will continue to transmit data. The device will terminate
further data transmissions if an acknowledge is not
detected. The master must then issue a stop condition
to return the device to Standby mode and place the
device into a known state.
DEVICE ADDRESSING
Following a start condition, the master must output a
Slave Address Byte. Slave bits ‘1101’ access the CCR.
Bit 3 through Bit 1 of the slave byte specify the device
select bits. These are set to ‘111’.
The last bit of the Slave Address Byte defines the operation to be performed. When this R/W bit is a one, then
a read operation is selected. A zero selects a write
operation. Refer to Figure 6.
After loading the entire Slave Address Byte from the
SDA bus, the X1205 compares the device identifier
and device select bits with ‘1101111’. Upon a correct
compare, the device outputs an acknowledge on the
SDA line.
REV 1.0.9 8/29/02
www.xicor.com
Characteristics subject to change without notice.
8 of 22
X1205 – Preliminary Information
Following the Slave Byte is a two byte word address.
The word address is either supplied by the master
device or obtained from an internal counter. On power
up the internal address counter is set to address 0H,
so a current address read of the CCR array starts at
address 0. When required, as part of a random read,
the master must supply the 2 Word Address Bytes as
shown in Figure 6.
In a random read operation, the slave byte in the
“dummy write” portion must match the slave byte in the
“read” section. For a random read of the Clock/Control
Registers, the slave byte must be 1101111x in both
places.
1
0
0
0
0
A7
A6
A5
A4
A3
D7
D6
D5
Write Operations
1
0
D4
R/W
0
A2
D3
D2
EL
0
1
A
1
0
IN
0
IM
1
1
R
Y
Figure 6. Slave Address, Word Address, and Data Bytes
PR
Byte Write
For a write operation, the device requires the Slave
Address Byte and the Word Address Bytes. This gives
the master access to any one of the words in the CCR.
(Note: Prior to writing to the CCR, the master must
write a 02h, then 06h to the status register in two preceding operations to enable the write operation. See
“Writing to the Clock/Control Registers.” Upon receipt
Slave Address Byte
Byte 0
Word Address 1
Byte 1
A1
A0
Word Address 0
Byte 2
D1
D0
Data Byte
Byte 3
of each address byte, the X1205 responds with an
acknowledge. After receiving both address bytes the
X1205 awaits the eight bits of data. After receiving the
8 data bits, the X1205 again responds with an
acknowledge. The master then terminates the transfer
by generating a stop condition. The X1205 then begins
an internal write cycle of the data to the nonvolatile
memory. During the internal write cycle, the device
inputs are disabled, so the device will not respond to
any requests from the master. The SDA output is at high
impedance. See Figure 7.
Figure 7. Byte Write Sequence
Signals from
the Master
SDA Bus
Signals From
The Slave
REV 1.0.9 8/29/02
S
t
a
r
t
Word
Address 1
Slave
Address
110 1 1 110
Word
Address 0
S
t
o
p
Data
00000000
A
C
K
A
C
K
www.xicor.com
A
C
K
A
C
K
Characteristics subject to change without notice.
9 of 22
X1205 – Preliminary Information
Stop and Write Modes
Stop conditions that terminate write operations must
be sent by the master after sending at least 1 full data
byte and it’s associated ACK signal. If a stop is issued
in the middle of a data byte, or before 1 full data byte +
ACK is sent, then the X1205 resets itself without performing the write. The contents of the array are not
affected.
Figure 9. Acknowledge Polling Sequence
Byte load completed
by issuing STOP.
Enter ACK Polling
Issue START
Acknowledge Polling
Disabling of the inputs during nonvolatile write cycles
can be used to take advantage of the typical 5mS write
cycle time. Once the stop condition is issued to indicate the end of the master’s byte load operation, the
X1205 initiates the internal nonvolatile write cycle.
Acknowledge polling can begin immediately. To do this,
the master issues a start condition followed by the
Slave Address Byte for a write or read operation. If the
X1205 is still busy with the nonvolatile write cycle then
no ACK will be returned. When the X1205 has completed the write operation, an ACK is returned and the
host can proceed with the read or write operation.
Refer to the flow chart in Figure 9.
Y
Issue Slave
Address Byte
(Read or Write)
A
IN
IM
EL
PR
YES
nonvolatile write
Cycle complete. Continue
command sequence?
Read Operations
There are three basic read operations: Current
Address Read, Random Read, and Sequential Read.
Current Address Read
Internally the X1205 contains an address counter that
maintains the address of the last word read incremented by one. Therefore, if the last read was to
address n, the next read operation would access data
from address n+1. Upon receipt of the Slave Address
Byte with the R/W bit set to one, the X1205 issues an
acknowledge, then transmits eight data bits. The master terminates the read operation by not responding
with an acknowledge during the ninth clock and issuing
a stop condition. Refer to Figure 8 for the address,
acknowledge, and data transfer sequence.
NO
R
ACK
returned?
Issue STOP
NO
Issue STOP
YES
Continue normal
Read or Write
command
sequence
PROCEED
It should be noted that the ninth clock cycle of the read
operation is not a “don’t care.” To terminate a read
operation, the master must either issue a stop condition during the ninth cycle or hold SDA HIGH during
the ninth clock cycle and then issue a stop condition.
Figure 8. Current Address Read Sequence
Signals from
the Master
SDA Bus
Signals from
the Slave
REV 1.0.9 8/29/02
S
t
a
r
t
S
t
o
p
Slave
Address
11 0 11 1 11
A
C
K
www.xicor.com
Data
Characteristics subject to change without notice.
10 of 22
X1205 – Preliminary Information
activity will be ignored until a start is detected. This
operation loads the new address into the address
counter. The next Current Address Read operation will
read from the newly loaded address. This operation
could be useful if the master knows the next address it
needs to read, but is not ready for the data.
The master issues the start condition and the slave
address byte, receives an acknowledge, then issues
the word address bytes. After acknowledging receipt of
each word address byte, the master immediately
issues another start condition and the slave address
byte with the R/W bit set to one. This is followed by an
acknowledge from the device and then by the eight bit
data word. The master terminates the read operation
by not responding with an acknowledge and then issuing a stop condition. Refer to Figure 10 for the address,
acknowledge, and data transfer sequence.
Sequential Read
Sequential reads can be initiated as either a current
address read or random address read. The first data
byte is transmitted as with the other modes; however,
the master now responds with an acknowledge, indicating it requires additional data. The device continues
to output data for each acknowledge received. The master terminates the read operation by not responding with
an acknowledge and then issuing a stop condition.
A
R
Y
Random Read
Random read operations allow the master to access
any location in the X1205. Prior to issuing the Slave
Address Byte with the R/W bit set to zero, the master
must first perform a “dummy” write operation.
The data output is sequential, with the data from
address n followed by the data from address n + 1.
Refer to Figure 11 for the acknowledge and data transfer sequence.
SDA Bus
Slave
Address
Word
Address 1
11 0 11 1 1 0
S
t
a
r
t
Word
Address 0
A
C
K
A
C
K
S
t
o
p
Slave
Address
11 0 1 1 1 11
00 00000
PR
Signals from
the Slave
S
t
a
r
t
EL
Signals from
the Master
IM
Figure 10. Random Address Read Sequence
IN
In a similar operation called “Set Current Address,” the
device sets the address if a stop is issued instead of
the second start shown in Figure 10. The X1205 then
goes into standby mode after the stop and all bus
A
C
K
A
C
K
Data
Figure 11. Sequential Read Sequence
Signals from
the Master
SDA Bus
Signals from
the Slave
Slave
Address
A
C
K
S
t
o
p
A
C
K
A
C
K
1
A
C
K
Data
(1)
Data
(2)
Data
(n-1)
Data
(n)
(n is any integer greater than 1)
REV 1.0.9 8/29/02
www.xicor.com
Characteristics subject to change without notice.
11 of 22
X1205 – Preliminary Information
ABSOLUTE MAXIMUM RATINGS
Temperature Under Bias ................... -65°C to +135°C
Storage Temperature......................... -65°C to +150°C
Voltage on VCC, VBACK and IRQ
pin (respect to ground) ............................-0.5V to 7.0V
Voltage on SCL, SDA, X1 and X2
pin (respect to ground) ............... -0.5V to 7.0V or 0.5V
above VCC or VBACK (whichever is higher)
DC Output Current .............................................. 5 mA
Lead Temperature (Soldering, 10 sec) ...............300°C
Y
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only and the functional operation
of the device at these or any other conditions above
those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
VBACK
Conditions
Min
Main Power Supply
2.7
Backup Power Supply
VCB
Switch to Backup Supply
VBC
Switch to Main Supply
1.8
OPERATING CHARACTERISTICS
Parameter
Conditions
Max
Unit
5.5
V
5.5
V
VBACK -0.2
VBACK -0.1
V
VBACK
VBACK +0.2
V
Max
Unit
Min
Typ
IM
Symbol
Typ
IN
VCC
Parameter
A
Symbol
R
DC OPERATING CHARACTERISTICS (Temperature = -40°C to +85°C, unless otherwise stated.)
Read Active Supply
Current
VCC = 2.7V
400
µA
VCC = 5.5V
800
µA
ICC2
Program Supply Current
(nonvolatile)
VCC = 2.7V
2.5
mA
VCC = 5.5V
3.0
mA
ICC3
Main Timekeeping
Current
VCC = 2.7V
5
µA
VCC = 5.5V
10
µA
Timekeeping Current
Notes
1, 5, 7, 14
2, 5, 7, 14
3, 7, 8, 14, 15
VBACK = 1.8V
1.25
µA
3, 6, 9, 14, 15
VBACK = 3.3V
1.5
µA
“See Performance Data”
PR
IBACK
EL
ICC1
Notes
ILI
Input Leakage Current
10
µA
10
ILO
Output Leakage Current
10
µA
10
VIL
Input LOW Voltage
-0.5
VCC x 0.2 or
VBACK x 0.2
V
13
VIH
Input HIGH Voltage
VCC x 0.7 or
VBACK x 0.7
VCC + 0.5 or
VBACK + 0.5
V
13
V
13
V
11
VHYS
VOL
Schmitt Trigger Input
Hysteresis
Output LOW Voltage for
SDA/IRQ
REV 1.0.9 8/29/02
VCC related level
.05 x VCC or
.05 x VBACK
VCC = 2.7V
0.4
VCC = 5.5V
0.4
www.xicor.com
Characteristics subject to change without notice.
12 of 22
X1205 – Preliminary Information
R
Y
Notes: (1) The device enters the Active state after any start, and remains active: for 9 clock cycles if the Device Select Bits in the Slave
Address Byte are incorrect or until 200nS after a stop ending a read or write operation.
(2) The device enters the Program state 200nS after a stop ending a write operation and continues for t WC.
(3) The device goes into the Timekeeping state 200nS after any stop, except those that initiate a nonvolatile write cycle; t WC after a
stop that initiates a nonvolatile write cycle; or 9 clock cycles after any start that is not followed by the correct Device Select Bits in
the Slave Address Byte.
(4) For reference only and not tested.
(5) VIL = VCC x 0.1, VIH = VCC x 0.9, fSCL = 400KHz
(6) VCC = 0V
(7) VBACK = 0V
(8) VSDA = VSCL=VCC, Others = GND or VCC
(9) VSDA =VSCL=VBACK, Others = GND or VBACK
(10) VSDA = GND or VCC, VSCL = GND or VCC
(11) IOL = 3.0mA at 5V, 1mA at 2.7V
(13) Threshold voltages based on the higher of Vcc or Vback.
(14) Using recommended crystal and oscillator network applied to X1 and X2 (25°C).
(15) Typical values are for TA = 25°C
Symbol
(1)
CIN
Parameter
Output Capacitance (SDA, IRQ)
Max.
Units
Test Conditions
10
pF
VOUT = 0V
pF
VIN = 0V
IN
COUT(1)
A
Capacitance TA = 25°C, f = 1.0 MHz, VCC = 5V
Input Capacitance (SCL)
10
AC CHARACTERISTICS
AC Test Conditions
IM
Notes: (1) This parameter is not 100% tested.
(2) The input capacitance between x1 and x2 pins can be varied between 5pF and 19.75pF by using analog trimming registers
VCC x 0.1 to VCC x 0.9
Input Rise and Fall Times
10ns
Input and Output Timing
Levels
VCC x 0.5
Standard Output Load
PR
Output Load
EL
Input Pulse Levels
Figure 14. Standard Output Load for testing the device with VCC = 5.0V
Equivalent AC Output Load Circuit for VCC = 5V
5.0V
5.0V
1533Ω
For VOL= 0.4V
1316Ω
and IOL = 3 mA
IRQ
SDA
806Ω
100pF
REV 1.0.9 8/29/02
www.xicor.com
100pF
Characteristics subject to change without notice.
13 of 22
X1205 – Preliminary Information
AC Specifications (TA = -40°C to +85°C, VCC = +2.7V to +5.5V, unless otherwise specified.)
Symbol
Parameter
fSCL
Min.
SCL Clock Frequency
tIN
Pulse width Suppression Time at inputs
Max.
Units
400
kHz
(1)
50
ns
Time the bus must be free before a new transmission can start
1.3
µs
tLOW
Clock LOW Time
1.3
µs
tHIGH
Clock HIGH Time
0.6
µs
0.6
µs
0.6
µs
100
ns
0
µs
0.6
µs
50
ns
tHD:STA
Start Condition Hold Time
tSU:DAT
Data In Setup Time
tHD:DAT
Data In Hold Time
tSU:STO
Stop Condition Setup Time
A
R
Start Condition Setup Time
Y
SCL LOW to SDA Data Out Valid
tSU:STA
0.9
µs
tAA
tBUF
SDA and SCL Rise Time
tR
tF
SDA and SCL Fall Time
Cb
Capacitive load for each bus line
TIMING DIAGRAMS
EL
Bus Timing
tHIGH
tF
SCL
20 +.1Cb(1)(2)
300
ns
+.1Cb(1)(2)
300
ns
400
pF
20
IM
Notes: (1) This parameter is not 100% tested.
(2) Cb = total capacitance of one bus line in pF.
IN
Data Output Hold Time
tDH
tLOW
tR
PR
tSU:DAT
tSU:STA
SDA IN
SDA OUT
REV 1.0.9 8/29/02
tHD:STA
tHD:DAT
tSU:STO
tAA
www.xicor.com
tDH
tBUF
Characteristics subject to change without notice.
14 of 22
X1205 – Preliminary Information
Write Cycle Timing
SCL
8th Bit of Last Byte
SDA
ACK
tWC
Start
Condition
Power Up Timing
Parameter
(1)
Time from Power Up to Read
(1)
Time from Power Up to Write
tPUR
tPUW
Min.
Typ.(2)
R
Symbol
Y
Stop
Condition
Max.
Units
1
ms
5
ms
Nonvolatile Write Cycle Timing
Symbol
(1)
tWC
Write Cycle Time
Min.
Typ.(1)
Max.
Units
5
10
ms
IM
(1) tWC is the time from a valid stop condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle.
It is the minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used.
PR
EL
Note:
Parameter
IN
A
Notes: (1) Delays are measured from the time VCC is stable until the specified operation can be initiated. These parameters are not 100%
tested. VCC slew rate should be between 0.2mV/µsec and 50mV/µsec.
(2) Typical values are for TA = 25°C and VCC = 5.0V
REV 1.0.9 8/29/02
www.xicor.com
Characteristics subject to change without notice.
15 of 22
X1205 – Preliminary Information
The Xicor RTC family uses an oscillator circuit with onchip crystal compensation network, including adjustable load-capacitance. The only external component
required is the crystal. The compensation network is
optimized for operation with certain crystal parameters
which are common in many of the surface mount or
tuning-fork crystals available today. Table 6 summarizes these parameters.
In addition to the analog compensation afforded by the
adjustable load capacitance, a digital compensation
feature is available for the Xicor RTC family. There are
three bits known as the Digital Trimming Register or
DTR, and they operate by adding or skipping pulses in
the clock signal. The range provided is ±30ppm in
increments of 10ppm. The default setting is 0ppm. The
DTR control can be used for coarse adjustments of
frequency drift over temperature or for crystal initial
accuracy correction.
IN
Table 7 contains some crystal manufacturers and part
numbers that meet the requirements for the Xicor RTC
products.
Y
Xicor has now integrated the oscillator compensation
circuity on-chip, to eliminate the need for external components and adjust for crystal drift over temperature
and enable very high accuracy timekeeping (<5ppm
drift).
R
CRYSTAL OSCILLATOR AND TEMPERATURE
COMPENSATION
cally 25 deg C, and a peak drift of >110ppm occurs at
the temperature extremes of –40 and +85 deg C. It is
possible to address this variable drift by adjusting the
load capacitance of the crystal, which will result in predictable change to the crystal frequency. The Xicor
RTC family allows this adjustment over temperature
since the devices include on-chip load capacitor trimming. This control is handled by the Analog Trimming
Register, or ATR, which has 6 bits of control . The load
capacitance range covered by the ATR circuit is
approximately 3.25pF to 18.75pF, in 0.25pf increments. Note that actual capacitance would also
include about 2pF of package related capacitance. Incircuit tests with commercially available crystals demonstrate that this range of capacitance allows frequency control from +116ppm to –37ppm, using a
12.5pF load crystal.
A
APPLICATION SECTION
IM
The turnover temperature in Table 6 describes the
temperature where the apex of the of the drift vs. temperature curve occurs. This curve is parabolic with the
drift increasing as (T-T0)2. For an Epson MC-405
device, for example, the turnover temperature is typi-
Parameter
Frequency
Freq. Tolerance
Min
PR
Turnover Temperature
EL
Table 6. Crystal Parameters Required for Xicor RTC’s
Operating Temperature Range
20
Typ
32.768
25
-40
Parallel Load Capacitance
Equivalent Series Resistance
Max
Units
Notes
kHz
±100
ppm
30
°C
85
°C
12.5
Down to 20ppm if desired
Typically the value used for most
crystals
pF
50
kΩ
For best oscillator performance
Table 7. Crystal Manufacturers
Manufacturer
Part Number
Temp Range
+25°C Freq Toler.
Citizen
CM201, CM202, CM200S
-40 to +85°C
±20ppm
Epson
MC-405, MC-406
-40 to +85°C
±20ppm
Raltron
RSM-200S-A or B
-40 to +85°C
±20ppm
SaRonix
32S12A or B
-40 to +85°C
±20ppm
Ecliptek
ECPSM29T-32.768K
-10 to +60°C
±20ppm
ECS
ECX-306/ECX-306I
-10 to +60°C
±20ppm
Fox
FSM-327
-40 to +85°C
±20ppm
REV 1.0.9 8/29/02
www.xicor.com
Characteristics subject to change without notice.
16 of 22
X1205 – Preliminary Information
EL
IM
Y
IN
Layout Considerations
The crystal input at X1 has a very high impedance and
will pick up high frequency signals from other circuits
on the board. Since the X2 pin is tied to the other side
of the crystal, it is also a sensitive node. These signals
can couple into the oscillator circuit and produce double clocking or mis-clocking, seriously affecting the
accuracy of the RTC. Care needs to be taken in layout
of the RTC circuit to avoid noise pickup. Below in Figure 15 is a suggested layout for the X1205 SOIC
device.
Assembly
Most electronic circuits do not have to deal with
assembly issues, but with the RTC devices assembly
includes insertion or soldering of a live battery into an
unpowered circuit. If a socket is soldered to the board,
and a battery is inserted in final assembly, then there
are no issues with operation of the RTC. If the battery
is soldered to the board directly, then the RTC device
Vback pin will see some transient upset from either soldering tools or intermittent battery connections which
can stop the circuit from oscillating. Once the battery is
soldered to the board, the only way to assure the circuit
will start up is to momentarily (very short period of
time!) short the Vback pin to ground and the circuit will
begin to oscillate.
R
For more detailed operation see Xicor’s application
note AN154 on Xicor’s website at www.xicor.com.
The X1 and X2 connections to the crystal are to be
kept as short as possible. A thick ground trace around
the crystal is advised to minimize noise intrusion, but
ground near the X1 and X2 pins should be avoided as
it will add to the load capacitance at those pins. Keep in
mind these guidelines for other PCB layers in the vicinity of the RTC device. A small decoupling capacitor at
the Vcc pin of the chip is mandatory, with a solid connection to ground.
A
A final application for the ATR control is in-circuit calibration for high accuracy applications, along with a
temperature sensor chip. Once the RTC circuit is powered up with battery backup, the PHZ output is set at
32.768kHz and frequency drift is measured. The ATR
control is then adjusted to a setting which minimizes
drift. Once adjusted at a particular temperature, it is
possible to adjust at other discrete temperatures for
minimal overall drift, and store the resulting settings in
the EEPROM. Extremely low overall temperature drift
is possible with this method. The Xicor evaluation
board contains the circuitry necessary to implement
this control.
PR
Figure 15. Suggested Layout for Xicor RTC in SO-8
REV 1.0.9 8/29/02
Oscillator Measurements
When a proper crystal is selected and the layout guidelines above are observed, the oscillator should start up
in most circuits in less than one second. Some circuits
may take slightly longer, but startup should definitely
occur in less than 5 seconds. When testing RTC circuits, the most common impulse is to apply a scope
probe to the circuit at the X2 pin (oscillator output) and
observe the waveform. DO NOT DO THIS! Although in
some cases you may see a useable waveform, due to
the parasitics (usually 10pF to ground) applied with the
scope probe, there will be no useful information in that
waveform other than the fact that the circuit is oscillating. The X2 output is sensitive to capacitive impedance
so the voltage levels and the frequency will be affected
by the parasitic elements in the scope probe. Applying
a scope probe can possibly cause a faulty oscillator to
start up, hiding other issues (although in the Xicor
RTC’s, the internal circuitry assures startup when
using the proper crystal and layout).
www.xicor.com
Characteristics subject to change without notice.
17 of 22
X1205 – Preliminary Information
The best way to analyze the RTC circuit is to power it
up and read the real time clock as time advances, or if
the chip has the PHZ output, look at the output of that
pin on an oscilloscope (after enabling it with the control
register, and using a pullup resistor for an open-drain
output). Alternatively, the X1226/1286/1205 devices
have an IRQ- output which can be checked by setting
an alarm for each minute. Using the pulse interrupt
mode setting, the once-per-minute interrupt functions
as an indication of proper oscillation.
Figure 16. Supercapactor charging circuit
Backup Battery Operation
Many types of batteries can be used with the Xicor
RTC products. 3.0V or 3.6V Lithium batteries are
appropriate, and sizes are available that can power a
Xicor RTC device for up to 10 years. Another option is
to use a supercapacitor for applications where Vcc may
disappear intermittently for short periods of time.
Depending on the value of supercapacitor used,
backup time can last from a few days to two weeks
(with >1F). A simple silicon or Schottky barrier diode
can be used in series with Vcc to charge the supercapacitor, which is connected to the Vback pin. Do not
use the diode to charge a battery (especially lithium
batteries!).
Since the battery switchover occurs at Vcc=Vback0.1V (see Figure 16), the battery voltage must always
be lower than the Vcc voltage during normal operation
or the battery will be drained.
2.7-5.5V
VCC
Vback
Supercapacitor
R
Y
VSS
Table 8. Battery Backup Operation
IM
IN
A
The summary of conditions for backup battery operation is given in Table 8:
Condition
EL
1. Example Application, Vcc=5V, Vback=3.0V
Vcc
Vback
Vtrip
Iback
5.00
3.00
4.38
<<1µA
5.00
0
4.38
0
0–1.8
1.8-3.0
4.38
<2µA
Vcc
Vback
Vtrip
Iback
a. Normal Operation
3.30
3.00
2.65
<<1µA
b. Vcc on with no battery
3.30
0
2.65
0
c. Backup Mode
0–1.8
1.8–3.0*
2.65
<2µA*
Timekeeping only
2.65 - 3.30
> Vcc
2.65
up to 3mA
Internal
Vcc=Vback
a. Normal Operation
b. Vcc on with no battery
PR
c. Backup Mode
Notes
Timekeeping only
2. Example Application, Vcc=3.3V,Vback=3.0V
Condition
d. UNWANTED - Vcc ON, Vback powering
*since Vback>2.65V is higher than Vtrip, the battery is powering the entire device
REV 1.0.9 8/29/02
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Characteristics subject to change without notice.
18 of 22
X1205 – Preliminary Information
IBACK Performance
IBACK vs. Temperature
Multi-Lot Process Variation Data
1.4
3.3V
1.2
1.8V
1.0
Y
0.8
0.6
0.2
-40
A
0
R
0.4
25
60
Temperature °C
85
IN
One way to prevent operation in battery backup mode
above the Vtrip level is to add a diode drop (silicon
diode preferred) to the battery to insure it is below
Vtrip. This will also provide reverse leakage protection
which may be needed to get safety agency approval.
PERFORMANCE DATA
IBACK (µA)
Referring to Figure 16, Vtrip applies to the “Internal
Vcc” node which powers the entire device. This means
that if Vcc is powered down and the battery voltage at
Vback is higher than the Vtrip voltage, then the entire
chip will be running from the battery. If Vback falls to
lower than Vtrip, then the chip shuts down and all outputs are disabled except for the oscillator and timekeeping circuitry. The fact that the chip can be powered
from Vback is not necessarily an issue since standby
current for the RTC devices is <2µA for this mode
(called “main timekeeping current” in the data sheet).
Only when the serial interface is active is there an
increase in supply current, and with Vcc powered
down, the serial interface will most likely be inactive.
PR
EL
IM
One mode that should always be avoided is the operation of the RTC device with Vback greater than both
Vcc and Vtrip (Condition 2d in Table 8). This will cause
the battery to drain quickly as serial bus communication and non-volatile writes will require higher supplier
current.
REV 1.0.9 8/29/02
www.xicor.com
Characteristics subject to change without notice.
19 of 22
X1205 – Preliminary Information
PACKAGING INFORMATION
Y
8-Lead Plastic, SOIC, Package Code S8
0.150 (3.80) 0.228 (5.80)
0.158 (4.00) 0.244 (6.20)
R
Pin 1 Index
IN
0.014 (0.35)
0.019 (0.49)
A
Pin 1
0.188 (4.78)
0.197 (5.00)
IM
(4X) 7°
0.053 (1.35)
0.069 (1.75)
0.004 (0.19)
0.010 (0.25)
EL
0.050 (1.27)
0° - 8°
PR
0.010 (0.25)
X 45°
0.020 (0.50)
0.050"Typical
0.050"
Typical
0.0075 (0.19)
0.010 (0.25)
0.250"
0.016 (0.410)
0.037 (0.937)
0.030"
Typical
8 Places
FOOTPRINT
NOTE: ALL DIMENSIONS IN INCHES (IN P ARENTHESES IN MILLIMETERS)
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Characteristics subject to change without notice.
20 of 22
X1205 – Preliminary Information
PACKAGING INFORMATION
8-Lead Plastic, TSSOP, Package Code V8
Y
.025 (.65) BSC
A
R
.169 (4.3)
.252 (6.4) BSC
.177 (4.5)
IN
.114 (2.9)
.122 (3.1)
IM
.047 (1.20)
0° – 8°
EL
.0075 (.19)
.0118 (.30)
.002 (.05)
.006 (.15)
.010 (.25)
Gage Plane
Seating Plane
PR
.019 (.50)
.029 (.75)
(4.16) (7.72)
Detail A (20X)
(1.78)
.031 (.80)
.041 (1.05)
(0.42)
(0.65)
All Measurements Are Typical
See Detail “A”
NOTE: ALL DIMENSIONS IN INCHES (IN P ARENTHESES IN MILLIMETERS)
REV 1.0.9 8/29/02
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Characteristics subject to change without notice.
21 of 22
X1205 – Preliminary Information
ORDERING INFORMATION
VCC Range
Package
Operating Temperature Range
Part Number
2.7-5.5V
8L SOIC
0–70°C
X1205S8
-40–85°C
X1205S8I
0–70°C
X1205V8
-40–85°C
X1205V8I
8L TSSOP
Y
PART MARK INFORMATION
8-Lead SOIC
YWW
XXXXX
X1205 X
YWW XX
Blank = 8-Lead SOIC
A
R
8-Lead TSSOP
Blank = 2.7 to 5.5V, 0 to +70°C
I = 2.7 to 5.5V, -40 to 85°C
LIMITED WARRANTY
PR
EL
IM
IN
1205 = 2.7 to 5.5V, 0 to +70°C
1205I = 2.7 to 5.5V, -40 to 85°C
©Xicor, Inc. 2001 Patents Pending
Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty,
express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement.
Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices
at any time and without notice.
Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, or licenses are implied.
COPYRIGHTS AND TRADEMARKS
Xicor, Inc., the Xicor logo, E2POT, XDCP, XBGA, AUTOSTORE, Direct Write cell, Concurrent Read-Write, PASS, MPS, PushPOT, Block Lock, IdentiPROM,
E2KEY, X24C16, SecureFlash, and SerialFlash are all trademarks or registered trademarks of Xicor, Inc. All other brand and product names mentioned herein are
used for identification purposes only, and are trademarks or registered trademarks of their respective holders.
U.S. PATENTS
Xicor products are covered by one or more of the following U.S. Patents: 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846;
4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874,967; 4,883,976; 4,980,859; 5,012,132; 5,003,197; 5,023,694; 5,084,667; 5,153,880; 5,153,691;
5,161,137; 5,219,774; 5,270,927; 5,324,676; 5,434,396; 5,544,103; 5,587,573; 5,835,409; 5,977,585. Foreign patents and additional patents pending.
LIFE RELATED POLICY
In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection
and correction, redundancy and back-up features to prevent such an occurrence.
Xicor’s products are not authorized for use in critical components in life support devices or systems.
1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to
perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or effectiveness.
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Characteristics subject to change without notice.
22 of 22