PATENTED

HT1625
RAM Mapping 64´8 LCD Controller for I/O MCU
PATENTED
PAT No. : TW 099352
Features
· Operating voltage: 2.7V~5.2V
· Built-in LCD display RAM
· Built-in RC oscillator
· R/W address auto increment
· External 32.768kHz crystal or 32kHz frequency
· Two selectable buzzer frequencies (2kHz or 4kHz)
source input
· Power down command reduces power consumption
· 1/4 bias, 1/8 duty, frame frequency is 64Hz
· Software configuration feature
· Max. 64´8 patterns, 8 commons, 64 segments
· Data mode and Command mode instructions
· Built-in internal resistor type bias generator
· Three data accessing modes
· 3-wire serial interface
· VLCD pin to adjust LCD operating voltage
· 8 kinds of time base or WDT selection
· 100-pin LQFP package
· Time base or WDT overflow output
General Description
HT1625 make it suitable for multiple LCD applications
including LCD modules and display subsystems. Only
three lines are required for the interface between the
host controller and the HT1625. The HT162X series
have many kinds of products that match various applications.
HT1625 is a peripheral device specially designed for I/O
type MCU used to expand the display capability. The
max. display segment of the device are 512 patterns
(64´8). It also supports serial interface, buzzer sound,
Watchdog Timer or time base timer functions. The
HT1625 is a memory mapping and multi-function LCD
controller. The software configuration feature of the
Selection Table
HT162X
HT1620
HT1621
HT1622
HT16220
HT1623
HT1625
HT1626
COM
4
4
8
8
8
8
16
SEG
32
32
32
32
48
64
48
Built-in Osc.
¾
Ö
Ö
¾
Ö
Ö
Ö
Crystal Osc.
Ö
Ö
¾
Ö
Ö
Ö
Ö
Rev. 1.60
1
April 29, 2011
PATENTED
HT1625
Block Diagram
D is p la y R A M
O S C O
O S C I
C S
C o n
a n
T im
C ir c
R D
W R
tro l
d
in g
u it
C O M 0
C O M 7
L C D D r iv e r /
B ia s C ir c u it
D A T A
S E G 0
S E G 6 3
V D D
V L C D
V S S
B Z
W a tc h d o g T im e r
a n d
T im e B a s e G e n e r a to r
T o n e F re q u e n c y
G e n e ra to r
B Z
IR Q
Pin Assignment
4 4
4 5
4 6
4 7
4 8
4 9
5 0
5 1
5 2
5 3
5 4
5 5
5 6
5 7
5 8
5 9
6 0
6 1
6 2
6 3
S E G 4 0
S E G 4 1
S E G 4 2
N C
4 3
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
C S
R D
W R
D A T A
V S S
O S C I
O S C O
V D D
V L C D
IR Q
B Z
B Z
T 1
T 2
T 3
N C
C O M 0
C O M 1
C O M 2
C O M 3
N C
N C
N C
N C
C O M 4
1 0 0 9 9 9 8 9 7 9 6 9 5 9 4 9 3 9 2 9 1 9 0 8 9 8 8 8 7 8 6 8 5 8 4 8 3 8 2 8 1 8 0 7 9 7 8 7 7 7 6
1
2
7 5
7 4
7 3
3
7 2
4
5
6
7
8
9
1 0
1 1
1 2
H T 1 6 2 5
1 0 0 L Q F P -A
1 3
1 4
1 5
1 6
1 7
1 8
1 9
2 0
2 1
2 2
2 3
2 4
2 5
2 6 2 7 2 8 2 9 3 0 3 1 3 2 3 3 3 4 3 5 3 6 3 7 3 8 3 9 4 0 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 4 9 5 0
7 1
7 0
6 9
6 8
6 7
6 6
6 5
6 4
6 3
6 2
6 1
6 0
5 9
5 8
5 7
5 6
5 5
5 4
5 3
5 2
5 1
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
N C
N C
S E G
S E G
S E G
S E G
3 9
3 8
3 7
3 6
3 5
3 4
3 3
3 2
3 1
3 0
2 9
2 8
2 7
2 6
2 5
2 4
2 3
2 2
2 1
2 0
1 9
1 8
1 7
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
N C
N C
C O M
N C
C O M
N C
C O M
N C
1 6
1 5
1 4
1 3
1 2
1 1
1 0
9
8
7
2
6
5
4
3
2
1
0
7
6
5
Rev. 1.60
April 29, 2011
PATENTED
HT1625
Pad Assignment
S E G 5 7
S E G 5 6
S E G 5 5
S E G 5 4
S E G 5 3
S E G 5 2
S E G 5 1
S E G 5 0
S E G 4 9
S E G 4 8
S E G 4 7
S E G 4 6
S E G 4 5
S E G 4 4
S E G 4 3
O S C I
S E G 5 8
4
S E G 5 9
V S S
S E G 6 0
3
S E G 6 1
D A T A
S E G 6 2
W R
2
S E G 6 3
1
C S
R D
8 7
8 6
8 5
8 4
8 3
8 2
8 1
8 0
7 9
7 8
7 7
7 6
7 5
7 4
7 3
7 2
7 1
7 0
6 9
6 8
6 7
6 6
5
6 5
S E G 4 2
6 4
S E G 4 1
6 3
S E G 4 0
6 2
S E G 3 9
6 1
S E G 3 8
6 0
S E G 3 7
5 9
S E G 3 6
O S C O
6
V D D
7
V L C D
8
5 8
S E G 3 5
IR Q
9
5 7
S E G 3 4
B Z
1 0
5 6
S E G 3 3
B Z
1 1
5 5
S E G 3 2
T 1
1 2
T 2
1 3
5 4
S E G 3 1
T 3
1 4
5 3
S E G 3 0
C O M 0
1 5
5 2
C O M 1
1 6
S E G 2 9
5 1
C O M 2
S E G 2 8
1 7
C O M 3
1 8
5 0
S E G 2 7
4 9
S E G 2 6
4 8
S E G 2 5
4 7
S E G 2 4
4 6
S E G 2 3
4 5
S E G 2 2
4 4
S E G 2 1
4 3
S E G 2 0
C O M 4
(0 , 0 )
1 9
S E G 2
S E G 3
S E G 4
S E G 5
3 4
3 5
3 6
3 7
3 8
3 9
4 0
4 1
4 2
S E G 1 9
S E G 1
3 3
S E G 1 8
S E G 0
3 2
S E G 1 7
C O M 7
3 1
S E G 1 6
C O M 6
3 0
S E G 1 5
C O M 5
2 9
S E G 1 4
2 8
S E G 1 3
2 7
S E G 1 2
2 6
S E G 1 1
2 5
S E G 1 0
2 4
S E G 9
2 3
S E G 8
2 2
S E G 7
2 1
S E G 6
2 0
Chip size: 118 ´ 128 (mil)2
* The IC substrate should be connected to VDD in the PCB layout artwork.
Rev. 1.60
3
April 29, 2011
PATENTED
HT1625
Pad Coordinates
Unit: mm
Pad No.
X
Y
Pad No.
X
Y
1
-1399.087
1514.994
45
1396.978
-1327.281
2
-1399.087
1415.973
46
1396.978
-1228.182
3
-1399.087
1316.263
47
1396.978
-1082.807
4
-1399.087
1140.800
48
1396.978
-983.707
5
-1399.087
876.062
49
1396.978
-798.327
6
-1399.087
684.333
50
1396.978
-699.227
7
-1399.087
585.273
51
1396.978
-513.846
8
-1399.087
486.214
52
1396.978
-414.747
9
-1399.087
387.114
53
1396.978
-229.367
10
-1400.132
237.773
54
1396.978
11
-1400.132
87.535
55
1396.978
-130.266
55.114
12
-1400.132
-53.536
56
1396.978
154.214
13
-1400.132
-152.637
57
1396.978
339.594
14
-1400.132
-251.656
58
1396.978
438.693
15
-1400.132
-350.758
59
1396.978
624.073
16
-1400.132
-449.776
60
1396.978
723.173
17
-1400.132
-548.878
61
1396.978
908.553
18
-1400.132
-647.896
62
1396.978
1007.654
19
-1400.132
-1401.530
63
1396.978
1193.033
20
-1254.633
-1523.957
64
1396.978
1292.134
21
-1155.531
-1523.957
65
1364.057
1521.618
22
-1056.513
-1523.957
66
1172.328
1521.618
23
-957.411
-1523.957
67
1073.228
1521.618
24
-858.392
-1523.957
68
881.497
1521.618
25
-759.292
-1523.957
69
782.397
1521.618
26
-660.272
-1523.957
70
590.667
1521.618
27
-561.172
-1523.957
71
485.994
1521.618
28
-462.153
-1523.957
72
386.972
1521.618
29
-363.052
-1523.957
73
287.874
1521.618
30
-264.033
-1523.957
74
188.852
1521.618
31
-164.932
-1523.957
75
89.753
1521.618
32
-65.912
33.188
-1523.957
76
-9.267
1521.618
-1523.957
77
-108.367
1521.618
33
34
132.208
-1523.957
78
-207.387
1521.618
35
231.309
-1523.957
79
-306.487
1521.618
36
330.328
-1523.957
80
-405.508
1521.618
37
429.159
-1523.957
81
-504.607
1521.618
38
614.539
-1523.957
82
-603.628
1521.618
39
713.638
-1523.957
83
-702.727
1521.618
40
899.018
-1523.957
84
-801.747
1521.618
41
998.119
-1523.957
85
-900.846
1521.618
42
1183.499
-1523.957
86
-999.868
1521.618
43
1396.978
-1525.401
87
-1098.967
1521.618
44
1396.978
-1426.302
Rev. 1.60
4
April 29, 2011
PATENTED
HT1625
Pad Description
Pad No.
Pad Name
I/O
Description
1
RD
I
READ clock input with pull-high resistor. Data in the RAM of the HT1625 are
clocked out on the falling edge of the RD signal. The clocked out data will appear on the data line. The host controller can use the next rising edge to latch
the clocked out data.
2
WR
I
WRITE clock input with pull-high resistor. Data on the DATA line are latched
into the HT1625 on the rising edge of the WR signal.
3
DATA
I/O
Serial data input or output with pull-high resistor
4
VSS
¾
Negative power supply, ground
5
OSCI
I
6
OSCO
O
7
VDD
¾
8
VLCD
I
LCD operating voltage input pad.
9
IRQ
O
Time base or Watchdog Timer overflow flag, NMOS open drain output
10, 11
BZ, BZ
O
2kHz or 4kHz tone frequency output pair
12~14
T1~T3
I
Not connected
15~22
COM0~COM7
O
LCD common outputs
23~86
SEG0~SEG63
O
LCD segment outputs
I
Chip selection input with pull-high resistor. When the CS is logic high, the
data and command read from or write to the HT1625 are disabled. The serial
interface circuit is also reset. But if the CS is at logic low level and is input to
the CS pad, the data and command transmission between the host controller
and the HT1625 are all enabled.
87
CS
The OSCI and OSCO pads are connected to a 32.768kHz crystal in order to
generate a system clock. If the system clock comes from an external clock
source, the external clock source should be connected to the OSCI pad. But
if an on-chip RC oscillator is selected instead, the OSCI and OSCO pads can
be left open.
Positive power supply
Absolute Maximum Ratings
Supply Voltage .........................................-0.3V to 5.5V
Storage Temperature ............................-50°C to 125°C
Input Voltage.............................VSS-0.3V to VDD+0.3V
Operating Temperature...........................-25°C to 75°C
Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may
cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed
in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.
Rev. 1.60
5
April 29, 2011
PATENTED
HT1625
D.C. Characteristics
Symbol
VDD
IDD1
IDD2
IDD11
IDD22
ISTB
VIL
VIH
IOL1
IOH1
IOL1
IOH1
IOL2
IOH2
IOL3
IOH3
RPH
Parameter
Operating Voltage
Operating Current
Operating Current
Operating Current
Operating Current
Standby Current
Input Low Voltage
Input High Voltage
Ta=25°C
Test Conditions
VDD
Conditions
¾
¾
3V
5V
3V
5V
3V
5V
3V
5V
3V
5V
3V
5V
BZ, BZ
DATA
DATA
LCD Common Sink Current
LCD Common Source Current
LCD Segment Sink Current
LCD Segment Source Current
Pull-high Resistor
¾
5.2
V
No load or LCD ON
On-chip RC oscillator
310
mA
¾
260
420
mA
No load or LCD ON
Crystal oscillator
¾
150
310
mA
¾
250
420
mA
No load or LCD OFF
On-chip RC oscillator
¾
8
30
mA
¾
20
60
mA
No load or LCD OFF
Crystal oscillator
¾
¾
20
mA
¾
¾
35
mA
¾
1
12
mA
¾
2
24
mA
0
¾
0.6
V
0
¾
1.0
V
2.4
¾
3
V
VOL=0.3V
4.0
¾
5
V
0.9
1.8
¾
mA
5V
VOL=0.5V
1.7
3
¾
mA
3V
VOH=2.7V
-0.9
-1.8
¾
mA
5V
VOH=4.5V
-1.7
-3
¾
mA
3V
VOL=0.3V
0.9
1.8
¾
mA
5V
VOL=0.5V
1.7
3
¾
mA
3V
VOH=2.7V
-0.9
-1.8
¾
mA
5V
VOH=4.5V
-1.7
-3
¾
mA
3V
VOL=0.3V
80
160
¾
mA
5V
VOL=0.5V
180
360
¾
mA
3V
VOH=2.7V
-40
-80
¾
mA
5V
VOH=4.5V
-90
-180
¾
mA
3V
VOL=0.3V
50
100
¾
mA
5V
VOL=0.5V
120
240
¾
mA
3V
VOH=2.7V
-30
-60
¾
mA
5V
VOH=4.5V
-70
-140
¾
mA
100
200
300
kW
50
100
150
kW
3V
DATA, WR, CS, RD
5V
A.C. Characteristics
Symbol
Parameter
fSYS1
System Clock
Unit
155
DATA, WR, CS, RD
5V
Max.
¾
DATA, WR, CS, RD
3V
Typ.
2.7
No load, Power down mode
3V
BZ, BZ, IRQ
Min.
Ta=25°C
Test Conditions
VDD
Conditions
5V
On-chip RC oscillator
Min.
Typ.
Max.
Unit
24
32
40
kHz
fSYS2
System Clock
¾
External clock source
¾
32
¾
kHz
fLCD1
LCD Frame Frequency
5V
On-chip RC oscillator
48
64
80
Hz
fLCD2
LCD Frame Frequency
¾
External clock source
¾
64
¾
Hz
Rev. 1.60
6
April 29, 2011
PATENTED
Symbol
Test Conditions
Parameter
VDD
¾
tCOM
LCD Common Period
fCLK1
Serial Data Clock (WR Pin)
fCLK2
Serial Data Clock (RD Pin)
tCS
Serial Interface Reset Pulse Width
(Figure 3)
3V
5V
3V
5V
¾
3V
WR, RD Input Pulse Width
(Figure 1)
tCLK
HT1625
5V
Conditions
Min.
Typ.
Max.
Unit
¾
n/fLCD
¾
sec
4
¾
150
kHz
4
¾
300
kHz
¾
¾
75
kHz
¾
¾
150
kHz
700
800
¾
ns
n: Number of COM
Duty cycle 50%
Duty cycle 50%
CS
Write mode
3.34
¾
125
Read mode
6.67
¾
¾
Write mode
1.67
¾
125
Read mode
3.34
¾
¾
ms
ms
t r, t f
Rise or Fall Time Serial Data Clock
Width (Figure 1)
¾
¾
¾
120
160
ns
tsu
Setup Time for DATA to WR, RD
Clock Width (Figure 2)
¾
¾
60
120
¾
ns
th
Hold Time for DATA to WR, RD Clock
Width (Figure 2)
¾
¾
700
800
¾
ns
tsu1
Setup Time for CS to WR, RD Clock
Width (Figure 3)
¾
¾
500
600
¾
ns
th1
Hold Time for CS to WR, RD Clock
Width (Figure 3)
¾
¾
700
800
¾
ns
5V
On-chip RC oscillator
¾
Tone Frequency (2KHz)
ftone
Tone Frequency (4KHz)
1.5
2.0
2.5
kHz
3.0
4.0
5.0
kHz
VDD drop down to 0V
20
¾
¾
ms
tOFF
VDD OFF Times (Figure 4)
tSR
VDD Rising Slew Rate (Figure 4)
¾
¾
0.05
¾
¾
V/ms
tRSTD
Delay Time after Reset (Figure 4)
¾
¾
1
¾
¾
ms
Note:
1. If the conditions of Power-on Reset timing are not satisfied in power On/Off sequence, the internal
Power-on Reset (POR) circuit will not operate normally.
2. If the VDD drops below the minimum voltage of operating voltage spec. during operating, the conditions
of Power-on Reset timing must be satisfied also. That is, the VDD must drop to 0V and keep at 0V for
20ms (min.) before rising to the normal operating voltage.
V A L ID D A T A
tf
W R , R D
C lo c k
9 0 %
5 0 %
1 0 %
tr
tC
V
tC
L K
ts
G N D
th
u
V
5 0 %
Figure 1
tS
tC
W R , R D
C lo c k
S
V
th
G N D
V
F F
0 .9 V
D D
tR
S T D
L a s t C lo c k
D D
C S
G N D
Figure 3
Rev. 1.60
tO
R
1
5 0 %
F ir s t C lo c k
0 V
D D
5 0 %
u 1
D D
G N D
Figure 2
V D D
ts
D D
G N D
L K
W R , R D
C lo c k
C S
V
5 0 %
D B
D D
Figure 4 Power-on Reset Timing
7
April 29, 2011
PATENTED
HT1625
Functional Description
Display Memory - RAM Structure
If an external clock is selected as the source of system
frequency, the SYS DIS command turns out invalid and
the power down mode fails to be carried out until the external clock source is removed.
The static display RAM is organized into 128´4 bits and
stores the display data. The contents of the RAM are directly mapped to the contents of the LCD driver. Data in
the RAM can be accessed by the READ, WRITE and
READ-MODIFY-WRITE commands. The following is a
mapping from the RAM to the LCD patterns.
Buzzer Tone Output
A simple tone generator is implemented in the HT1625.
The tone generator can output a pair of differential driving signals on the BZ and BZ which are used to generate
a single tone.
Time Base and Watchdog Timer - WDT
The time base generator and WDT share the same divided (/256) counter. TIMER DIS/EN/CLR
, WDT DIS/EN/CLR and IRQ EN/DIS are independent
from each other. Once the WDT time-out occurs, the
IRQ pin will remain at logic low level until the CLR WDT
or the IRQ DIS command is issued.
C O M 7
C O M 6
C O M 5
Command Format
The HT1625 can be configured by the software setting.
There are two mode commands to configure the
HT1625 resource and to transfer the LCD display data.
C O M 3
C O M 4
C O M 2
C O M 1
C O M 0
S E G 0
1
0
S E G 1
3
2
S E G 2
5
4
S E G 3
7
6
1 2 7
S E G 6 3
D 3
D 2
D 1
D 0
A d d r e s s 7 B its
(A 6 , A 5 , ...., A 0 )
1 2 6
A d d r
D 3
D a ta
D 2
D 1
D 0
A d d r
D a ta
D a ta 4 B its
(D 3 , D 2 , D 1 , D 0 )
RAM Mapping
T im e B a s e
T IM E R
/2 5 6
C lo c k S o u r c e
V
C L R
T im e r
W D T E N /D IS
D D
W D T
/4
Q
D
C K
C L R
IR Q
E N /D IS
IR Q
E N /D IS
R
W D T
Timer and WDT Configurations
Rev. 1.60
8
April 29, 2011
PATENTED
The following are the data mode ID and the command
mode ID:
Operation
Mode
ID
READ
Data
110
WRITE
Data
101
READ-MODIFY-WRITE
Data
101
Command
100
COMMAND
Name
HT1625
If successive commands have been issued, the command mode ID can be omitted. While the system is operating in the non-successive command or the
non-successive address data mode, the CS pin should
be set to ²1² and the previous operation mode will be reset also. The CS pin returns to ²0², a new operation
mode ID should be issued first.
Command Code
Function
TONE OFF
0000-1000-X
Turn-off tone output
TONE 4K
010X-XXXX-X
Turn-on tone output, tone frequency is 4kHz
TONE 2K
0110-XXXX-X
Turn-on tone output, tone frequency is 2kHz
Timing Diagrams
READ Mode (Command Code : 1 1 0)
C S
W R
R D
D A T A
1
0
1
A 6
A 5
A 4
A 3
A 2
A 1
A 0
D 0
D 2
D 1
D 3
1
A 6
0
1
D a ta (M A 1 )
M e m o ry A d d re s s 1 (M A 1 )
A 5
A 4
A 3
A 2
A 1
A 0
D 0
M e m o ry A d d re s s 2 (M A 2 )
D 1
D 2
D 3
D a ta (M A 2 )
READ Mode (Successive Address Reading)
C S
W R
R D
D A T A
1
1
0
A 6
A 5
A 4
A 3
A 2
A 1
M e m o ry A d d re s s (M A )
Rev. 1.60
A 0
D 0
D 1
D 2
D a ta (M A )
9
D 3
D 0
D 1
D 2
D a ta (M A + 1 )
D 3
D 0
D 1
D 2
D a ta (M A + 2 )
D 3
D 0
D 1
D 2
D 3
D 0
D a ta (M A + 3 )
April 29, 2011
PATENTED
HT1625
WRITE Mode (Command Code : 1 0 1)
C S
W R
1
D A T A
A 6
1
0
A 5
A 3
A 4
A 2
A 1
A 0
D 0
M e m o ry A d d re s s 1 (M A 1 )
D 2
D 1
D 3
1
A 6
1
0
A 5
D a ta (M A 1 )
A 4
A 3
A 2
A 1
A 0
D 0
M e m o ry A d d re s s 2 (M A 2 )
D 2
D 1
D 3
D a ta (M A 2 )
WRITE Mode (Successive Address Writing)
C S
W R
1
D A T A
1
0
A 6
A 5
A 3
A 4
A 2
A 1
A 0
D 0
D 2
D 1
M e m o ry A d d re s s (M A )
D 3
D 0
D 2
D 1
D 3
D 0
D a ta (M A + 1 )
D a ta (M A )
D 1
D 2
D 3
D 0
D a ta (M A + 2 )
D 2
D 1
D 3
D 0
D a ta (M A + 3 )
READ-MODIFY-WRITE Mode (Command Code : 1 0 1)
C S
W R
R D
D A T A
1
A 6
1
0
A 5
A 4
A 3
A 2
A 1
A 0
D 0
M e m o ry A d d re s s 1 (M A 1 )
D 2
D 1
D 3
D 0
D 1
D 2
D 3
1
0
1
A 6
D a ta (M A 1 )
D a ta (M A 1 )
A 5
A 4
A 3
A 2
A 1
A 0
M e m o ry A d d re s s 2 (M A 2 )
D 0
D 2
D 1
D 3
D a ta (M A 2 )
READ-MODIFY-WRITE Mode (Successive Address Accessing)
C S
W R
R D
D A T A
1
0
1
A 6
A 5
A 4
A 3
A 2
A 1
M e m o ry A d d re s s (M A )
Rev. 1.60
A 0
D 0
D 1
D 2
D 3
D 0
D 1
D 2
D a ta (M A )
D a ta (M A )
10
D 3
D 0
D 1
D 2
D a ta (M A + 1 )
D 3
D 0
D 1
D 2
D a ta (M A + 1 )
D 3
D 0
D 1
D 2
D 3
D 0
D a ta (M A + 2 )
April 29, 2011
PATENTED
HT1625
Command Mode (Command Code : 1 0 0)
C S
W R
D A T A
1
0
0
C 8
C 7
C 6
C 5
C 4
C 3
C o m m a n d 1
C 2
C 1
C 8
C 0
C o m m a n d ...
C 7
C 6
C 5
C 4
C 3
C 2
C 1
C 0
C o m m a n d i
C o m m a n d
o r
D a ta M o d e
Mode (Data and Command Mode)
C S
W R
D A T A
C o m m a n d
o r
D a ta M o d e
A d d re s s a n d D a ta
C o m m a n d
o r
D a ta M o d e
A d d re s s a n d D a ta
C o m m a n d
o r
D a ta M o d e
A d d re s s a n d D a ta
R D
Rev. 1.60
11
April 29, 2011
PATENTED
HT1625
Application Circuits
C S
*
V D D
R D
*V R
W R
D A T A
M C U
V L C D
H T 1 6 2 5
*R
B Z
P ie z o
IR Q
B Z
O S C I
C lo c k O u t
O S C O
C O M 0 ~ C O M 7
S E G 0 ~ S E G 6 3
E x te r n a l C lo c k 1 ( 3 2 k H z )
E x te r n a l C lo c k 2 ( 3 2 k H z )
1 /4 B ia s , 1 /8 D u ty
O n - c h ip O S C
L C D
P a n e l
C ry s ta l
3 2 7 6 8 H z
The connection of IRQ and RD pin can be selected depending on the requirement of the MCU.
Note:
The voltage applied to VLCD pin must be equal to or lower than VDD.
Adjust VR to fit LCD display, at VDD=5V, VLCD=4V, VR=15kW±20%.
Adjust R (external Pull-high resistance) to fit user¢s time base clock.
Instruction Set Summary
Name
ID
Command Code
D/C
Function
READ
1 1 0 A6A5A4A3A2A1A0D0D1D2D3
D
Read data from the RAM
WRITE
Def.
1 0 1 A6A5A4A3A2A1A0D0D1D2D3
D
Write data to the RAM
READ-MODIFY1 0 1 A6A5A4A3A2A1A0D0D1D2D3
WRITE
D
Read and Write data to the RAM
SYS DIS
1 0 0 0000-0000-X
C
Turn off both system oscillator and LCD bias
generator
SYS EN
1 0 0 0000-0001-X
C
Turn on system oscillator
LCD OFF
1 0 0 0000-0010-X
C
Turn off LCD display
LCD ON
1 0 0 0000-0011-X
C
Turn on LCD display
TIMER DIS
1 0 0 0000-0100-X
C
Disable time base output
Yes
WDT DIS
1 0 0 0000-0101-X
C
Disable WDT time-out flag output
Yes
TIMER EN
1 0 0 0000-0110-X
C
Enable time base output
WDT EN
1 0 0 0000-0111-X
C
Enable WDT time-out flag output
TONE OFF
1 0 0 0000-1000-X
C
Turn off tone outputs
CLR TIMER
1 0 0 0000-1101-X
C
Clear the contents of the time base generator
CLR WDT
1 0 0 0000-1111-X
C
Clear the contents of the WDT stage
RC 32K
1 0 0 0001-10XX-X
C
System clock source, on-chip RC oscillator
EXT (XTAL) 32K 1 0 0 0001-11XX-X
C
System clock source, external 32kHz clock
source or crystal oscillator 32.768kHz
Rev. 1.60
12
Yes
Yes
Yes
Yes
April 29, 2011
PATENTED
Name
ID
Command Code
D/C
HT1625
Function
TONE 4K
1 0 0 010X-XXXX-X
C
Tone frequency output: 4kHz
TONE 2K
1 0 0 0110-XXXX-X
C
Tone frequency output: 2kHz
IRQ DIS
1 0 0 100X-0XXX-X
C
Disable IRQ output
IRQ EN
1 0 0 100X-1XXX-X
C
Enable IRQ output
F1
1 0 0 101X-0000-X
C
Time base clock output: 1Hz
The WDT time-out flag after: 4s
F2
1 0 0 101X-0001-X
C
Time base clock output: 2Hz
The WDT time-out flag after: 2s
F4
1 0 0 101X-0010-X
C
Time base clock output: 4Hz
The WDT time-out flag after: 1s
F8
1 0 0 101X-0011-X
C
Time base clock output: 8Hz
The WDT time-out flag after: 1/2s
F16
1 0 0 101X-0100-X
C
Time base clock output: 16Hz
The WDT time-out flag after: 1/4s
F32
1 0 0 101X-0101-X
C
Time base clock output: 32Hz
The WDT time-out flag after: 1/8s
F64
1 0 0 101X-0110-X
C
Time base clock output: 64Hz
The WDT time-out flag after: 1/16s
F128
1 0 0 101X-0111-X
C
Time base clock output: 128Hz
The WDT time-out flag after: 1/32s
TEST
1 0 0 1110-0000-X
C
Test mode, user don¢t use.
NORMAL
1 0 0 1110-0011-X
C
Normal mode
Note:
Def.
Yes
Yes
Yes
X : Don¢t care
A6~A0 : RAM address
D3~D0 : RAM data
D/C : Data/Command mode
Def. : Power on reset default
All the bold forms, namely 1 1 0, 1 0 1, and 1 0 0, are mode commands. Of these, 1 0 0 indicates the command
mode ID. If successive commands have been issued, the command mode ID except for the first command will
be omitted. The source of the tone frequency and of the time base or WDT clock frequency can be derived from
an on-chip 32kHz RC oscillator, a 32.768kHz crystal oscillator, or an external 32kHz clock. Calculation of the
frequency is based on the system frequency sources as stated above. It is recommended that the host controller should initialize the HT1625 after power on reset, for power on reset may fail, which in turn leads to the malfunctioning of the HT1625.
Rev. 1.60
13
April 29, 2011
PATENTED
HT1625
Package Information
100-pin LQFP (14mm´14mm) Outline Dimensions
C
D
7 5
G
5 1
H
I
5 0
7 6
F
A
B
E
1 0 0
2 6
K
=
J
2 5
1
Symbol
Nom.
Max.
A
0.626
¾
0.634
B
0.547
¾
0.555
C
0.626
¾
0.634
D
0.547
¾
0.555
E
¾
0.020
¾
F
¾
0.008
¾
G
0.053
¾
0.057
H
¾
¾
0.063
I
¾
0.004
¾
J
0.018
¾
0.030
K
0.004
¾
0.008
a
0°
¾
7°
Symbol
A
Rev. 1.60
Dimensions in inch
Min.
Dimensions in mm
Min.
Nom.
Max.
15.90
¾
16.10
B
13.90
¾
14.10
C
15.90
¾
16.10
D
13.90
¾
14.10
E
¾
0.50
¾
F
¾
0.20
¾
G
1.35
¾
1.45
H
¾
¾
1.60
I
¾
0.10
¾
J
0.45
¾
0.75
K
0.10
¾
0.20
a
0°
¾
7°
14
April 29, 2011
PATENTED
HT1625
Holtek Semiconductor Inc. (Headquarters)
No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan
Tel: 886-3-563-1999
Fax: 886-3-563-1189
http://www.holtek.com.tw
Holtek Semiconductor Inc. (Taipei Sales Office)
4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan
Tel: 886-2-2655-7070
Fax: 886-2-2655-7373
Fax: 886-2-2655-7383 (International sales hotline)
Holtek Semiconductor Inc. (Shenzhen Sales Office)
5F, Unit A, Productivity Building, No.5 Gaoxin M 2nd Road, Nanshan District, Shenzhen, China 518057
Tel: 86-755-8616-9908, 86-755-8616-9308
Fax: 86-755-8616-9722
Holtek Semiconductor (USA), Inc. (North America Sales Office)
46729 Fremont Blvd., Fremont, CA 94538, USA
Tel: 1-510-252-9880
Fax: 1-510-252-9885
http://www.holtek.com
Copyright Ó 2011 by HOLTEK SEMICONDUCTOR INC.
The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used
solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable
without further modification, nor recommends the use of its products for application that may present a risk to human life
due to malfunction or otherwise. Holtek¢s products are not authorized for use as critical components in life support devices
or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information,
please visit our web site at http://www.holtek.com.tw.
Rev. 1.60
15
April 29, 2011