HT1650 64´32 LCD Controller for I/O MCU PATENTED PAT No. : 099352 Technical Document · Tools Information · FAQs · Application Note Features · Operating voltage: 2.7V~5.2V · Six-wire interface (four data wires) · Built-in 32kHz RC oscillator · Eight kinds of time base or WDT selection · External 32.768kHz crystal oscillator or 32kHz fre- · Time base or WDT overflow output quency source input · R/W address auto increment · Standby current: <1mA at 3V, <2mA at 5V · Built-in buzzer driver (2kHz/4kHz) · Internal resistor type: 1/6 bias or 1/5 bias, 1/32 duty, · Power down command reduces power consumption and 1/16 duty · Software configuration feature · Three selectable LCD frame frequencies: 64Hz, · Data mode and Command mode instructions 89Hz or 170Hz · Three data accessing modes · Max. of 64´32 patterns, 64 segments and 32 com- · Provides VLCD pin to adjust LCD operating voltage mons and max. VLCD voltage up to 7V · 80 segments and 16 commons selectable by com- · Provides three kinds of bias current programming mand method · Control of TN-type and STN-type LCDs · Built-in bit-map display RAM: 2048 bits (=64´32 bits) · 128-pin QFP package · Built-in internal resistor type bias generator Applications · Leisure products · Cellular phone · Games · Global positioning system · Personal digital assistant · Consumer electronics General Description HT1650 is a peripheral device specially designed for I/O type MCUs which are used to expand the display capability. The max. display segment of the device are 2048 patterns (64 segments and 32 commons). It also supports four data bits interface, buzzer sound, Watchdog Timer or time base timer functions. The HT1650 is a memory mapping and multi-function LCD controller. It Rev. 1.80 can control TN-type (Twisted Nematic) or STN-type (Super Twisted Nematic) LCDs. The software configuration feature of the HT1650 make it suitable for multiple LCD applications including LCD modules and display subsystems. Only six lines (CS, WR, DB0~DB3) are required for the interface between the host controller and the HT1650. 1 November 9, 2010 PATENTED HT1650 Block Diagram O S C O D is p la y R A M O S C I C S C o n tro l & T im in g C ir c u it R D W R D B 0 C O M 0 C O M 3 1 L C D D r iv e r / B ia s C ir c u it S E G 0 D B 3 S E G 6 3 V D D V L C D V S S B Z W a tc h d o g T im e r & T im e B a s e G e n e r a to r T o n e F re q u e n c y G e n e ra to r B Z N o te : C S : C h ip s B Z , B Z : T o W R , R D : W D B 0 ~ D B 3 : C O M 0 ~ C O IR Q : T im e IR Q e le c tio n n e o u tp u ts R IT E c lo c k , R E A D c lo c k D a ta b u s M 3 1 , S E G 0 ~ S E G 6 3 : L C D o u tp u ts b a s e o r W D T o v e r flo w o u tp u t Pin Assignment S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G C O M C O M C O M C O M C O M C O M C O M C O M C O M C O M C O M C O M C O M 5 1 5 2 5 3 5 4 5 5 5 6 5 7 5 8 5 9 6 0 6 1 6 2 6 3 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 C O M 1 8 C O M 1 7 C O M 1 6 N C N C N C N C N C N C C S R D W R D B 0 D B 1 D B 2 D B 3 V S S O S C I O S C O V D D V L C D IR Q B Z B Z T 1 T 2 T 3 T 4 T 0 0 0 V L C D N C N C N C N C N C C O M 0 C O M 1 C O M 2 1 1 2 8 1 2 7 1 2 6 1 2 5 1 2 4 1 2 3 1 2 2 1 2 1 1 2 0 1 1 9 1 1 8 1 1 7 1 1 6 1 1 5 1 1 4 1 1 3 1 1 2 1 1 1 1 1 0 1 0 9 1 0 8 1 0 7 1 0 6 1 0 5 1 0 4 1 0 3 1 0 2 2 1 0 1 3 1 0 0 4 9 9 5 9 8 6 9 7 7 9 6 8 9 5 9 9 4 1 0 9 3 1 1 9 2 1 2 9 1 1 3 9 0 1 4 8 9 1 5 8 8 1 6 8 7 1 7 8 6 1 8 8 5 H T 1 6 5 0 1 2 8 Q F P -A 1 9 2 0 2 1 8 4 8 3 8 2 2 2 8 1 2 3 8 0 2 4 7 9 2 5 7 8 2 6 7 7 2 7 7 6 2 8 7 5 2 9 7 4 3 0 7 3 3 1 7 2 3 2 7 1 3 3 7 0 3 4 6 9 3 5 6 8 3 6 6 7 3 7 6 6 3 8 6 5 3 9 4 0 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 4 9 5 0 5 1 5 2 5 3 5 4 5 5 5 6 5 7 5 8 5 9 6 0 6 1 6 2 6 3 6 4 S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G 5 0 4 9 4 8 4 7 4 6 4 5 4 4 4 3 4 2 4 1 4 0 3 9 3 8 3 7 3 6 3 5 3 4 3 3 3 2 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G C O M C O M C O M C O M C O M C O M C O M C O M C O M C O M C O M C O M C O M 1 2 1 1 1 0 9 8 7 6 5 4 3 1 5 2 2 1 0 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 Rev. 1.80 November 9, 2010 PATENTED HT1650 Pad Assignment S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 1 0 2 1 0 1 1 0 0 2 7 2 8 1 1 3 1 1 2 1 1 1 1 1 0 1 0 9 1 0 8 1 0 7 1 0 6 1 0 5 1 0 4 1 0 3 2 9 3 0 3 1 3 2 3 3 3 4 3 5 3 6 3 7 3 8 3 9 4 0 1 1 6 1 1 5 1 1 4 4 1 4 2 1 1 7 4 3 4 4 4 5 4 6 1 9 9 9 8 9 7 9 6 9 5 9 4 9 3 9 2 9 1 9 0 8 9 S E G 4 7 2 S E G 4 8 S E G 4 9 3 S E G 5 0 5 S E G 5 1 6 S E G 5 2 7 S E G 5 3 8 S E G 5 4 9 S E G 5 5 1 0 S E G 5 6 1 1 7 9 S E G 5 7 1 2 7 8 S E G 5 8 1 3 7 7 S E G 5 9 1 4 S E G 6 0 1 5 7 5 S E G 6 1 1 6 7 4 S E G S E G C O M C O M C O M C O M C O M C O M C O M C O M C O M C O M C O M C O M C O M 1 7 7 3 6 2 6 3 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 4 8 8 S E G 1 6 8 7 S E G S E G S E G S E G S G E S E G S E G S E G S E G 1 5 6 8 6 8 5 8 4 8 3 8 2 8 1 8 0 1 4 1 3 1 2 1 1 1 0 9 8 7 2 9 6 1 3 0 6 0 3 1 5 9 S E G S E G S E G S E G S E G S E G S E G C O M C O M C O M C O M C O M C O M C O M C O M C O M C O M C O M C O M C O M 5 8 C O M 2 (0 ,0 ) 7 6 1 8 7 2 1 9 7 1 2 0 7 0 2 1 6 9 6 8 2 2 2 3 6 7 2 4 6 6 2 5 6 5 2 6 6 4 2 7 6 3 2 8 6 2 3 5 3 6 3 7 3 8 3 9 4 0 4 1 4 2 4 3 4 4 3 2 3 3 3 4 4 6 4 5 4 7 4 8 4 9 5 0 5 1 5 2 5 3 5 4 5 5 5 6 5 7 5 4 3 2 1 0 1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 O I 1 6 1 7 1 8 C O M 1 C O M 0 V L C D T 0 0 0 T 4 T 3 T 2 T 1 B Z B Z IR Q V L C D V D D O S C O S C V S S D D 3 D D 2 D D 1 D D 0 W R R D C S C O M C O M C O M Chip size: 3555´3970 (mm)2 * The IC substrate should be connected to VSS in the PCB layout artwork. Pad Coordinates Unit: mm Pad No. X Y Pad No. X Y Pad No. X Y 1 2 3 4 5 6 7 8 9 10 11 12 -1329.500 -1672.500 -1672.500 -1672.500 -1672.500 -1672.500 -1672.500 -1672.500 -1672.500 -1672.500 -1672.500 -1672.500 1880.000 1738.050 1359.300 1249.300 1129.300 1007.500 887.500 765.700 645.700 523.900 403.900 282.100 40 41 42 43 44 45 46 47 48 49 50 51 -383.700 -293.700 -190.500 -95.000 5.300 111.400 183.950 308.850 414.450 509.450 630.250 743.850 -1784.900 -1784.900 -1784.900 -1784.900 -1784.900 -1853.850 -1753.850 -1794.400 -1794.400 -1794.400 -1770.250 -1770.250 79 80 81 82 83 84 85 86 87 88 89 90 1672.500 1672.500 1672.500 1672.500 1672.500 1672.500 1672.500 1672.500 1672.500 1672.500 1425.500 1330.500 382.400 495.400 608.400 721.400 834.400 947.400 1060.400 1173.400 1286.400 1736.100 1880.000 1880.000 Rev. 1.80 3 November 9, 2010 PATENTED HT1650 Pad No. X Y Pad No. X Y Pad No. X Y 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 -1672.500 -1672.500 -1672.500 -1672.500 -1672.500 -1672.500 -1672.500 -1672.500 -1672.500 -1672.500 -1672.500 -1672.500 -1672.500 -1672.500 -1672.500 -1672.500 -1672.500 -1672.500 -1672.500 -1208.550 -1113.550 -1018.550 -895.500 -789.900 -694.900 -589.300 -494.300 162.100 40.300 -79.700 -201.500 -321.500 -416.500 -511.500 -606.500 -701.500 -796.500 -891.500 -986.500 -1081.500 -1176.500 -1271.500 -1366.500 -1461.500 -1556.500 -1651.500 -1880.000 -1880.000 -1880.000 -1784.900 -1784.900 -1784.900 -1784.900 -1784.900 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 857.450 971.050 1084.650 1206.800 1330.200 1427.200 1672.500 1672.500 1672.500 1672.500 1672.500 1672.500 1672.500 1672.500 1672.500 1672.500 1672.500 1672.500 1672.500 1672.500 1672.500 1672.500 1672.500 1672.500 1672.500 1672.500 1672.500 -1770.250 -1770.250 -1770.250 -1848.100 -1880.000 -1880.000 -1880.000 -1643.600 -1548.600 -1453.600 -1358.600 -1263.600 -1168.600 -1073.600 -978.600 -883.600 -788.600 -693.600 -598.600 -503.600 -408.600 -295.600 -182.600 -69.600 43.400 156.400 269.400 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 1235.500 1140.500 1045.500 950.500 855.500 760.500 665.500 570.500 475.500 380.500 285.500 190.500 95.500 0.500 -94.500 -189.500 -284.500 -379.500 -474.500 -569.500 -664.500 -759.500 -854.500 -949.500 -1044.500 -1139.500 -1234.500 1880.000 1880.000 1880.000 1880.000 1880.000 1880.000 1880.000 1880.000 1880.000 1880.000 1880.000 1880.000 1880.000 1880.000 1880.000 1880.000 1880.000 1880.000 1880.000 1880.000 1880.000 1880.000 1880.000 1880.000 1880.000 1880.000 1880.000 Pad Description Pad No. Pad Name I/O Description 1~17 71~117 SEG47~SEG63 SEG0~SEG46 O LCD segment outputs 18~33 55~70 COM31~COM16 COM0~COM15 O LCD common outputs, under 80´16 command mode, COM16~COM31 will be s har e d w i t h S E G 6 4 ~S E G 7 9 . C O M 3 1 / S E G 6 4 , C O M 3 0 / S E G 6 5 , COM29/SEG66....., COM18/SEG77, COM17/SEG78, COM16/SEG79 I Chip selection input with pull-high resistor. When the CS is logic high, the data and command read from or write to the HT1650 are disabled. The serial interface circuit is also reset. But if the CS is at a logic low level and is input to the CS pad, the data and command transmission between the host controller and the HT1650 are all enabled. 34 CS 35 RD I READ clock input with pull-high resistor. Data in the RAM of the HT1650 are clocked out on the falling edge of the RD signal. The clocked out data will appear on the data line. The host controller can use the next rising edge to latch the clocked out data. 36 WR I WRITE clock input with pull-high resistor. Data on the DATA line are latched into the HT1650 on the rising edge of the WR signal. 37~40 DB0~DB3 I/O Parallel data input/output with pull-high resistor 41 VSS ¾ Negative power supply for logic circuit, ground 42 43 OSCI OSCO I O The OSCI and OSCO pads are connected to a 32.768kHz crystal in order to generate a system clock. If the system clock comes from an external clock source, the external clock source should be connected to the OSCI pad. But if an on-chip RC oscillator is selected, the OSCI and OSCO pads can be left open. 44 VDD ¾ Positive power supply for logic circuit 45 VLCD I Rev. 1.80 Power supply for LCD driver circuit 4 November 9, 2010 PATENTED Pad No. Pad Name I/O HT1650 Description 46 IRQ O Time base or Watchdog Timer overflow flag, NMOS open drain output. 47, 48 BZ, BZ O 2kHz or 4kHz frequency output pair (tristate output buffer) 49~53 T1~T4, T000 I Vary bias current pin It is usually not connected Absolute Maximum Ratings Supply Voltage ...........................VSS-0.3V to VSS+5.5V Storage Temperature ............................-50°C to 125°C Input Voltage.............................VSS-0.3V to VDD+0.3V Operating Temperature...........................-25°C to 75°C Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability. D.C. Characteristics Symbol Parameter VDD Operating Voltage IDD1 Operating Current IDD2 Operating Current IDD11 Operating Current IDD22 Operating Current ISTB Standby Current VIL Input Low Voltage VIH Input High Voltage IOL1 BZ, BZ, IRQ Sink Current IOH1 BZ, BZ Source Current IOL2 DB0~DB3 Sink Current IOH2 DB0~DB3 Source Current IOL3 LCD Common Sink Current IOH3 LCD Common Source Current Rev. 1.80 Ta=25°C Test Conditions VDD Conditions ¾ ¾ 3V 5V 3V 5V 3V 5V 3V 5V 3V 5V 3V 5V 3V 5V No load/LCD ON On-chip RC oscillator No load/LCD ON Crystal oscillator Min. Typ. Max. Unit 2.7 ¾ 5.2 V ¾ 150 250 mA ¾ 250 370 mA ¾ 135 200 mA ¾ 200 300 mA No load/LCD OFF On-chip RC oscillator ¾ 15 30 mA ¾ 50 70 mA No load/LCD OFF Crystal oscillator ¾ 2 10 mA ¾ 3 10 mA No load, Power down mode ¾ ¾ 1 mA ¾ ¾ 2 mA 0 ¾ 0.6 V 0 ¾ 1.0 V DB0~DB3, WR, CS, RD DB0~DB3, WR, CS, RD 2.4 ¾ 3 V 4.0 ¾ 5 V 3V VOL=0.3V 1.2 2.5 ¾ mA 5V VOL=0.5V 3 6 ¾ mA 3V VOH=2.7V -0.9 -1.8 ¾ mA 5V VOH=4.5V -2 -4 ¾ mA 3V VOL=0.3V 1.2 2.5 ¾ mA 5V VOL=0.5V 3 6 ¾ mA 3V VOH=2.7V -0.9 -1.8 ¾ mA 5V VOH=4.5V -2 -4 ¾ mA 3V VOL=0.3V 80 160 ¾ mA 5V VOL=0.5V 180 360 ¾ mA 3V VOH=2.7V -40 -80 ¾ mA 5V VOH=4.5V -90 -180 ¾ mA 5 November 9, 2010 PATENTED Symbol IOL4 IOH4 RPH Parameter LCD Segment Sink Current LCD Segment Source Current Pull-high Resistor Test Conditions VDD Conditions HT1650 Min. Typ. Max. Unit 3V VOL=0.3V 50 100 ¾ mA 5V VOL=0.5V 120 240 ¾ mA 3V VOH=2.7V -30 -60 ¾ mA 5V VOH=4.5V 3V 5V DB0~DB3, WR, CS, RD -70 -140 ¾ mA 150 250 410 kW 60 125 210 kW A.C. Characteristics Symbol fSYS1 fSYS2 fSYS3 Parameter System Clock System Clock System Clock fLCD1 LCD Frame Frequency fLCD2 LCD Frame Frequency fLCD3 LCD Frame Frequency tCOM LCD Common Period fCLK1 4-Bit Data Clock (WR Pin) fCLK2 4-Bit Data Clock (RD Pin) tCS 4-Bit Interface Reset Pulse Width (Figure 3) Ta=25°C Test Conditions VDD 3V 5V 3V 5V 3V 5V 3V 5V 3V 5V 3V 5V ¾ 3V 5V 3V 5V ¾ 3V tCLK WR, RD Input Pulse Width (Figure 1) 5V Conditions On-chip RC oscillator Crystal oscillator External clock source On-chip RC oscillator Crystal oscillator External clock source n: Number of COM Duty cycle 50% Duty cycle 50% CS Min. Typ. Max. Unit 22 32 40 kHz 24 32 40 kHz ¾ 32.768 ¾ kHz ¾ 32.768 ¾ kHz ¾ 32 ¾ kHz ¾ 32 ¾ kHz 61/117 89/170 111/213 Hz 61/117 89/170 111/213 Hz ¾ 64 ¾ Hz ¾ 64 ¾ Hz ¾ 64 ¾ Hz ¾ 64 ¾ Hz ¾ n/fLCD ¾ sec ¾ ¾ 150 kHz ¾ ¾ 300 kHz ¾ ¾ 75 kHz ¾ ¾ 150 kHz ¾ 250 ¾ ns ¾ ¾ ms ¾ ¾ ms Write mode 3.34 Read mode 6.67 Write mode 1.67 Read mode 3.34 tr, tf Rise/Fall Time Serial Data Clock 3V Width (Figure 1) 5V ¾ ¾ 120 ¾ ns tsu Setup Time for DB to WR, RD Clock 3V Width (Figure 2) 5V ¾ ¾ 120 ¾ ns th Hold Time for DB to WR, RD Clock 3V Width (Figure 2) 5V ¾ ¾ 120 ¾ ns tsu1 Setup Time for CS to WR, RD Clock 3V Width (Figure 3) 5V ¾ ¾ 100 ¾ ns th1 Hold Time for CS to WR, RD Clock 3V Width (Figure 3) 5V ¾ ¾ 100 ¾ ns Rev. 1.80 6 November 9, 2010 PATENTED HT1650 V a lid D a ta tf W R , R D C lo c k 9 0 % 5 0 % 1 0 % D B tr tC V tC L K ts D D G N D W R , R D C lo c k L K tC 5 0 % ts W R , R D C lo c k th u 1 1 S F ir s t C lo c k L a s t C lo c k 5 0 % G N D V D D G N D V 5 0 % th u D D G N D Figure 2 Figure 1 C S V 5 0 % D D G N D Figure 3 Functional Description The LCD OFF command is used to turn the LCD bias generator off. After the LCD bias generator switches off by issuing the LCD OFF command, using the SYS DIS command reduces power consumption, thus serving as a system power down command. But if the external clock source is chosen as the system clock, using the SYS DIS command can neither turn the oscillator off nor carry out the power down mode. The crystal oscillator option can be applied to connect an external frequency source of 32kHz to the OSCI pin. In this case, the system fails to enter the power down mode, similar to the case of the external 32kHz clock source operation. At the initial system power on, the HT1650 is at the SYS DIS state. System Oscillator The HT1650 system clock is used to generate the time base or Watchdog Timer (WDT) clock frequency, LCD driving clock, and tone frequency. The clock source may be from an on-chip RC oscillator (32kHz), a crystal oscillator (32.768kHz), or an external 32kHz clock by the S/W setting. The configuration of the system oscillator is as shown. After the SYS DIS command is executed, the system clock will stop and the LCD bias generator will turn off. That command is available only for the on-chip RC oscillator or for the crystal oscillator. Once the system clock stops, the LCD display will become blank, and the time base/WDT loses its function as well. O S C I O S C O C r y s ta l O s c illa to r 3 2 7 6 8 H z E x te r n a l C lo c k S o u r c e 3 2 k H z S y s te m C lo c k O n - c h ip R C O s c illa to r 3 2 k H z System Oscillator Configuration Rev. 1.80 7 November 9, 2010 PATENTED HT1650 Display Memory - RAM Structure The static display RAM is organized into 512´4 bits and stores the display data. The contents of the RAM are directly mapped to the contents of the LCD driver. Data in the RAM can be accessed by the READ, WRITE and READ-MODIFY-WRITE commands. The following is a mapping from the RAM to the LCD patterns. 00H 08H 1E8H 1F0H 1F8H COM0 Bit0 Bit0 Bit0 Bit0 Bit0 COM1 Bit1 Bit1 Bit1 Bit1 Bit1 COM2 Bit2 Bit2 Bit2 Bit2 Bit2 COM3 Bit3 Bit3 01H 09H COM4 Bit0 COM5 COM6 COM7 20H - - - - - - - - - 1D8H 1E0H Bit3 Bit3 Bit3 1F1H 1F9H Bit0 Bit0 Bit0 Bit0 Bit1 Bit1 Bit1 Bit1 Bit1 Bit2 Bit2 Bit2 Bit2 Bit2 Bit3 Bit3 0AH COM8 Bit0 COM9 COM10 11H 19H 21H - - - - - - - - - 1D9H 1E1H Bit3 Bit3 Bit3 1EAH 1F2H 1FAH Bit0 Bit0 Bit0 Bit0 Bit1 Bit1 Bit1 Bit1 Bit1 Bit2 Bit2 Bit2 Bit2 Bit2 12H Bit3 Bit3 03H 0BH 13H COM12 Bit0 Bit0 COM13 Bit1 Bit1 COM14 Bit2 Bit2 COM15 18H 1E9H 02H COM11 10H 1AH 22H- - - - - - - - - 1DAH 1E2H Bit3 Bit3 Bit3 1EBH 1F3H 1FBH Bit0 Bit0 Bit0 Bit0 Bit1 Bit1 Bit1 Bit1 Bit2 Bit2 Bit2 Bit2 Bit3 Bit3 Bit3 04H 0CH 14H COM16 Bit0 Bit0 COM17 Bit1 Bit1 COM18 Bit2 COM19 Bit3 1BH 23H- - - - - - - - - 1DBH 1E3H Bit3 Bit3 Bit3 1ECH 1F4H 1FCH Bit0 Bit0 Bit0 Bit0 Bit1 Bit1 Bit1 Bit1 Bit2 Bit2 Bit2 Bit2 Bit2 Bit3 Bit3 Bit3 Bit3 Bit3 05H 0DH 15H 1EDH 1F5H 1FDH COM20 Bit0 Bit0 Bit0 Bit0 Bit0 Bit0 COM21 Bit1 Bit1 Bit1 Bit1 Bit1 Bit1 COM22 Bit2 Bit2 Bit2 Bit2 Bit2 Bit2 COM23 Bit3 Bit3 Bit3 Bit3 Bit3 Bit3 06H 0EH 16H 1EEH 1F6H 1FEH COM24 Bit0 Bit0 Bit0 Bit0 Bit0 Bit0 COM25 Bit1 Bit1 Bit1 Bit1 Bit1 Bit1 COM26 Bit2 Bit2 Bit2 Bit2 Bit2 Bit2 COM27 Bit3 Bit3 Bit3 Bit3 Bit3 Bit3 1CH 1DH 1EH 1FH 24H- - - - - - - - - 1DCH 25H- - - - - - - - - 1DDH 26H - - - - - - - - - 1DEH 1E4H 1E5H 1E6H 07H 0FH 17H 1EFH 1F7H 1FFH COM28 Bit0 Bit0 Bit0 Bit0 Bit0 Bit0 COM29 Bit1 Bit1 Bit1 Bit1 Bit1 Bit1 COM30 Bit2 Bit2 Bit2 Bit2 Bit2 Bit2 COM31 Bit3 Bit3 Bit3 Bit3 Bit3 Bit3 SEG0 SEG1 SEG2 SEG61 SEG62 SEG63 27H - - - - - - - - - 1DFH SEG3 1E7H SEG60 64´32 Selection Mode RAM Mapping Table Rev. 1.80 8 November 9, 2010 PATENTED 00H 04H COM0 Bit0 COM1 Bit1 COM2 COM3 08H 134H 138H 13CH Bit0 Bit0 Bit0 Bit0 Bit1 Bit1 Bit1 Bit1 Bit2 Bit2 Bit2 Bit2 Bit2 Bit3 Bit3 Bit3 Bit3 Bit3 01H 05H 135H 139H 13DH COM4 Bit0 Bit0 Bit0 Bit0 Bit0 COM5 Bit1 Bit1 Bit1 Bit1 Bit1 COM6 Bit2 Bit2 Bit2 Bit2 Bit2 COM7 Bit3 Bit3 Bit3 Bit3 Bit3 02H 06H 136H 13AH 13EH COM8 Bit0 Bit0 Bit0 Bit0 Bit0 COM9 Bit1 Bit1 Bit1 Bit1 Bit1 COM10 Bit2 Bit2 Bit2 Bit2 Bit2 COM11 Bit3 Bit3 Bit3 Bit3 Bit3 03H 07H 0BH 137H 13BH 13FH COM12 Bit0 Bit0 Bit0 Bit0 Bit0 Bit0 COM13 Bit1 Bit1 Bit1 Bit1 Bit1 Bit1 COM14 Bit2 Bit2 Bit2 Bit2 Bit2 Bit2 COM15 Bit3 Bit3 Bit3 Bit3 Bit3 Bit3 SEG0 SEG1 SEG2 SEG77 SEG78 SEG79 09H 0AH 0CH HT1650 0DH 0EH 0FH 10H - - - - - - - 12CH 11H - - - - - - - - - 12DH 12H - - - - - - - - - 12EH 13H - - - - - - - - - 12FH SEG3 130H 131H 132H 133H SEG76 80´16 Selection Mode RAM Mapping Table Name Command Code 80´16 Mode X100-0001-1111-XXXX Function Change segment from 64 to 80 and common from 32 to 16 The default value after power ON reset is 64´32 mode, set ²Normal² command will change 80´16 mode to 64´32 mode. Frame Frequency The HT1650 provides three kinds of frame frequency options by command code; 64Hz, 89Hz and 170Hz respectively. FRAME 64Hz provides 64Hz frame frequency. FRAME 89Hz provides 89Hz frame frequency. FRAME 170Hz provides 170Hz frame frequency. Name Command Code Function FRAME 170Hz X100-0001-1000-XXXX Select 170Hz frame frequency FRAME 89Hz X100-0001-1101-XXXX Select 89Hz frame frequency FRAME 64Hz X100-0001-1110-XXXX Select 64Hz frame frequency Frame Frequency Selection Command Code Time Base and Watchdog Timer - WDT The time base generator and WDT share the same counter which is divided by 256. The IRQ clock can be programmed as 1Hz, 2Hz, ...., 128Hz output. TIMER DIS/EN/CLR, WDT DIS/EN/CLR and IRQ EN/DIS are independent from each other. Once the WDT time-out occurs, the IRQ pin will remain at a logic low level until the CLR WDT or the IRQ DIS command is issued. If an external clock is selected as the system frequency source, the SYS DIS command turns out invalid and the power down mode fails to be carried out until the external clock source is removed. Rev. 1.80 9 November 9, 2010 PATENTED HT1650 command, a system frequency selection command, an LCD configuration command, a tone frequency selection command, a bias current selection command, a timer/WDT setting command, and an operating command. The data mode, on the other hand, includes READ, WRITE, and READ-MODIFY-WRITE operations. Buzzer Tone Output A simple tone generator is implemented in the HT1650. The tone generator can output a pair of differential driving signals on the BZ and BZ which are used to generate a single tone. By executing the TONE 4K and TONE 2K commands there are two tone frequency outputs selectable that can turn on the tone output. The TONE 4K and TONE 2K commands set the tone frequency to 4kHz and 2kHz, respectively. The tone output can be turned off by invoking the TONE OFF command. The tone outputs, namely, BZ and BZ, are a pair of differential driving outputs used to drive a piezo buzzer. Once the system is disabled or the tone output is inhibited, the BZ and the BZ outputs will remain at low level. The following are the data mode ID and the command mode ID: Operation Mode ID READ Data 110 WRITE Data 101 READ-MODIFY-WRITE Data 101 Command 100 COMMAND Command Format If successive commands have been issued, the command mode ID can be omitted. While the system is operating in the non-successive command or the non-successive address data mode, the CS pin should be set to ²1² and the previous operation mode will also be reset. The CS pin returns to ²0², so a new operation mode ID should be issued first. The HT1650 can be configured by software setting. There are two mode commands to configure the HT1650 resource and to transfer the LCD display data. The configuration mode of the HT1650 is called command mode, and its command mode ID is 100. The command mode consists of a system configuration T im e B a s e C lo c k S o u r c e V C L R IR Q T IM E R E N /D IS ¸ 2 5 6 T im e r W D T E N /D IS D D Q D W D T ¸ 4 C K IR Q E N /D IS R C L R W D T Time Base and WDT Configurations Name Command Code Function TONE OFF X100-0000-1000-XXXX Turn-off the tone output TONE 4K X100-0001-0000-XXXX Turn-on the tone output, the tone frequency is 4kHz TONE 2K X100-0001-0001-XXXX Turn-on the tone output, the tone frequency is 2kHz Buzzer Tone Output Command Code The following are the data mode ID and the command ID: Mode ID READ Operation Data 110 WRITE Data 101 READ-MODIFY-WRITE Data 101 Command 100 COMMAND If successive commands have been issued, the command mode ID can be omitted. While the system is operating in the non-successive address data mode, the CS pin should be set to ²1² and the previous operation mode will also be reset. The CS pin returns to ²0², so a new operation mode ID should be issued first. Rev. 1.80 10 November 9, 2010 PATENTED Bias Generator data and command issued between the host controller and the HT1650 are first disabled and then initialized. Before issuing a mode command or mode switching, a high level pulse is required to initialize the serial interface of the HT1650. The DB0~DB3 are the 4-bit parallel data input/output lines. Data to be read or written or commands to be written have to pass through the DB0~DB3 lines. The RD line is the READ clock input. Data in the RAM are clocked out on the falling edge of the RD signal, and the clocked out data will then appear on the DB0~DB3 lines. It is recommended that the host controller read correct data during the interval between the rising edge and the next falling edge of the RD signal. The WR line is the WRITE clock input. The data, address, and command on the DB0~DB3 lines are all clocked into the HT1650 on the rising edge of the WR signal. There is an optional IRQ line to be used as an interface between the host controller and the HT1650. The IRQ pin can be selected as a timer output or a WDT overflow flag output by the S/W setting. The host controller can perform the time base or the WDT function by connecting with the IRQ pin of the HT1650. The HT1650 bias voltage belongs to the internal resistor type. It provides two kinds of bias options, namely 1/6 bias and 1/5 bias respectively. It also provides three kinds of bias current options by programming to suitably drive an LCD panel. The three kinds of bias current are large, middle, and small, respectively. Usually, large panel LCD can be excellently displayed by large bias current. Relatively, it consumes large current when LCD ON command is used. Small bias current provides low power consumption during on condition when the LCD is normally displayed. The following are the reference value table. When the bias current for LCD is more than Large Bias Current setting. It is recommended to add external circuit to increase driving current. Interfacing Only six lines are required to interface with the HT1650. The CS line is used to initialize the serial interface circuit and to terminate the communication between the host controller and the HT1650. If the CS pin is set to 1, the Bias HT1650 VLCD Large Bias Current Middle Bias Current Small Bias Current 3V 165mA 70mA 30mA 5V 270mA 110mA 50mA 3V 140mA 55mA 25mA 5V 225mA 90mA 40mA 1/5 1/6 P o w e r P o w e r V R V L C D V R V L C D R R (T 1 ) V 1 (T 1 ) V 1 R R (T 2 ) V 2 (T 2 ) V 2 R R V 3 V 3 R V V 4 R L C D V V 4 R L C D R (T 3 ) V 5 (T 3 ) V 5 R R (T 4 ) V 6 (T 4 ) V 6 R R V S S 1 /5 B ia s V S S 1 /6 B ia s Internal Resistor Type Bias Generator Configurations Note: The voltage applied to VLCD pin must be equal to or lower than 7V. Adjust VR to fit LCD display. Rev. 1.80 11 November 9, 2010 PATENTED V V HT1650 V L C D V L C D L C D L C D R R T 1 T 1 C R T 2 B ia s B lo c k C R T 3 T 0 0 0 R B ia s B lo c k C R T 0 0 0 1 /5 B ia s C R T 4 C C 2 R T 3 C R T 4 C R T 2 1 /6 B ia s Increase Driver Current Configurations Note: The external resistors are used to increment the driving current. And the external capacitors are used to keep the bias voltage stable. Timing Diagrams READ Mode (Command ID Code: 1 1 0) C S W R R D D B 3 A 8 A 7 A 3 D 3 A 8 A 7 A 3 D 3 D 3 D 3 D 3 D 3 D 3 D 3 D 3 D 3 D 3 D 3 D 3 D 3 D 3 D 3 D 3 D B 2 1 A 6 A 2 D 2 1 A 6 A 2 D 2 D 2 D 2 D 2 D 2 D 2 D 2 D 2 D 2 D 2 D 2 D 2 D 2 D 2 D 2 D 2 A 5 A 1 D 1 A 5 A 1 D 1 D 1 D 1 D 1 D 1 D 1 D 1 D 1 D 1 D 1 D 1 D 1 D 1 D 1 D 1 D 1 0 A 4 A 0 D 0 0 A 4 A 0 D 0 D 0 D 0 D 0 D 0 D 0 D 0 D 0 D 0 D 0 D 0 D 0 D 0 D 0 D 0 D 0 C o m m a n d ID A d d re s s (M A ) M e m o ry D a ta (M A ) C o m m a n d ID c o d e A d d re s s (M A ) M e m o ry D a ta (M A ) D a ta (M A + 1 ) D a ta (M A + 2 ) D a ta (M A + 3 ) D a ta (M A + 4 ) D a ta (M A + 5 ) D a ta (M A + 6 ) D a ta (M A + 7 ) D a ta (M A + 8 ) D a ta (M A + 9 ) D a ta (M A + 1 0 ) D a ta (M A + 1 1 ) D a ta (M A + 1 2 ) D a ta (M A + 1 3 ) D a ta (M A + 1 4 ) D a ta (M A + 1 5 ) 1 D B 1 D B 0 1 c o d e ( S in g le a d d r e s s r e a d in g ) Rev. 1.80 ( S u c c e s s iv e a d d r e s s r e a d in g ) 12 November 9, 2010 PATENTED HT1650 WRITE Mode (Command ID Code: 1 0 1) C S W R R D A 7 A 3 D 3 D 3 D 3 D 3 D 3 D 3 D 3 D 3 D 3 D 3 D 3 D 3 D 3 D 3 D 3 D 3 D B 2 1 A 6 A 2 D 2 1 A 6 A 2 D 2 D 2 D 2 D 2 D 2 D 2 D 2 D 2 D 2 D 2 D 2 D 2 D 2 D 2 D 2 D 2 A 5 A 1 D 1 A 5 A 1 D 1 D 1 D 1 D 1 D 1 D 1 D 1 D 1 D 1 D 1 D 1 D 1 D 1 D 1 D 1 D 1 A 4 A 0 D 0 1 A 4 A 0 D 0 D 0 D 0 D 0 D 0 D 0 D 0 D 0 D 0 D 0 D 0 D 0 D 0 D 0 D 0 D 0 A d d re s s (M A ) M e m o ry D a ta (M A ) C o m m a n d ID A d d re s s (M A ) M e m o ry D a ta (M A ) D a ta (M A + 1 ) D a ta (M A + 2 ) D a ta (M A + 3 ) D a ta (M A + 4 ) D a ta (M A + 5 ) D a ta (M A + 6 ) 0 D B 1 1 D B 0 0 D a ta (M A + 1 3 ) D a ta (M A + 1 4 ) D a ta (M A + 1 5 ) A 8 A 7 A 3 D 3 D 3 A 8 A 7 A 3 D 3 D 3 D 3 D 3 D 3 D 3 D 3 D 3 D 3 D 3 D 3 D 3 D 3 D 3 D B 2 1 A 6 A 2 D 2 D 2 1 A 6 A 2 D 2 D 2 D 2 D 2 D 2 D 2 D 2 D 2 D 2 D 2 D 2 D 2 D 2 D 2 D B 1 0 A 5 A 1 D 1 D 1 A 5 A 1 D 1 D 1 D 1 D 1 D 1 D 1 D 1 D 1 D 1 D 1 D 1 D 1 D 1 D 1 D B 0 1 A 4 A 0 D 0 D 0 1 A 4 A 0 D 0 D 0 D 0 D 0 D 0 D 0 D 0 D 0 D 0 D 0 D 0 D 0 D 0 D 0 A d d re s s (M A ) M e m o ry D a ta (M A ) D a ta (M A ) C o m m a n d ID M e m o ry D a ta (M A ) D a ta (M A ) D a ta (M A + 1 ) D a ta (M A + 1 ) D a ta (M A + 2 ) D a ta (M A + 2 ) D a ta (M A + 3 ) D a ta (M A + 3 ) D a ta (M A + 4 ) D a ta (M A + 4 ) D a ta (M A + 5 ) D a ta (M A + 5 ) D a ta (M A + 6 ) D a ta (M A + 6 ) c o d e c o d e D B 3 C o m m a n d ID C o m m a n d ID D a ta (M A + 1 2 ) A 8 D a ta (M A + 1 1 ) D 3 D a ta (M A + 1 0 ) A 3 D a ta (M A + 9 ) A 7 D a ta (M A + 8 ) A 8 D a ta (M A + 7 ) D B 3 ( S in g le a d d r e s s w r itin g ) ( S u c c e s s iv e a d d r e s s w r itin g ) READ-MODIFY-WRITE Mode (Command ID Code: 1 0 1) C S W R R D 0 A d d re s s (M A ) c o d e c o d e ( S in g le a d d r e s s a c c e s s in g ) Rev. 1.80 ( S u c c e s s iv e a d d r e s s a c c e s s in g ) 13 November 9, 2010 PATENTED HT1650 Command Mode (Command ID Code: 1 0 0) C S W R R D X D B 3 C 7 1 D B 2 0 D B 1 0 D B 0 C 3 C 6 C 2 C 5 C 1 C 4 C 0 X X 1 X 0 X 0 X C 7 C 3 X C 7 C 3 X C 7 C 3 X C 7 C 3 X C 7 C 3 X C 7 C 3 X C 6 C 2 X C 6 C 2 X C 6 C 2 X C 6 C 2 X C 6 C 2 X C 6 C 2 X C 5 C 1 X C 5 C 1 X C 5 C 1 X C 5 C 1 X C 5 C 1 X C 5 C 1 X C 4 C 0 X C 4 C 0 X C 4 C 0 X C 4 C 0 X C 4 C 0 X C 4 C 0 X C o m m a n d 6 C o m m a n d 5 C o m m a n d 4 C o m m a n d 3 C o m m a n d 2 C o m m a n d 1 C o m m a n d ID c o d e C o m m a n d C o m m a n d ID c o d e ( S in g le c o m m a n d ) ( S u c c e s s iv e c o m m a n d ) Note: ²X² stands for don¢t care Application Circuits Host Controller With an HT1650 Display System M a x . 7 V C S * R D *V R W R D B 0 ~ D B 3 M C U *R V L C D H T 1 6 5 0 B Z P ie z o IR Q B Z O S C I C lo c k O u t O S C O C O M 0 ~ C O M 3 1 S E G 0 ~ S E G 6 3 E x te r n a l C lo c k 1 ( 3 2 k H z ) * 1 /6 B ia s o r 1 /5 B ia s , 1 /3 2 D u ty o r 1 /1 6 D u ty E x te r n a l C lo c k 2 ( 3 2 k H z ) O n - c h ip O S C * L C D P a n e l C ry s ta l 3 2 7 6 8 H z *Note: The connection of IRQ and RD pin can be selected depending on the MCU. Adjust VR to fit LCD display Adjust R (external pull-high resistance) to fit user¢s time base clock. It is recommended that the internal equivalent capacitance between SEG and COM of LCD panel should be lower than 10pF. (LCR meter test condition: frequency in 1KHz) Rev. 1.80 14 November 9, 2010 PATENTED HT1650 Instruction Set Summary Name Command Code D/C Function READ A8110-A7A6A5A4A3A2A1A0D3D2D1D0 D Read data from the RAM WRITE Def. A8101-A7A6A5A4A3A2A1A0D3D2D1D0 D Write data to the RAM READ-MODIFYA8101-A7A6A5A4A3A2A1A0D3D2D1D0 WRITE D Read from and Write data to the RAM SYS DIS X100-0000-0000-XXXX C Turn Off both system oscillator and LCD bias Yes generator SYS EN X100-0000-0001-XXXX C Turn On system oscillator LCD OFF X100-0000-0010-XXXX C Turn Off LCD display LCD ON X100-0000-0011-XXXX C Turn On LCD display TIMER DIS X100-0000-0100-XXXX C Disable time base output Yes WDT DIS X100-0000-0101-XXXX C Disable WDT time-out flag output Yes TIMER EN X100-0000-0110-XXXX C Enable time base output WDT EN X100-0000-0111-XXXX C Enable WDT time-out flag output TONE OFF X100-0000-1000-XXXX C Turn Off tone outputs CLR TIMER X100-0000-1101-XXXX C Clear the contents of the time base generator CLR WDT X100-0000-1111-XXXX C Clear the contents of the WDT stage TONE 4K X100-0001-0000-XXXX C Turn on tone output, tone frequency output: 4kHz TONE 2K X100-0001-0001-XXXX C Turn on tone output, tone frequency output: 2kHz Yes Yes IRQ DIS X100-0001-0010-XXXX C Disable IRQ output IRQ EN X100-0001-0011-XXXX C Enable IRQ output RC 32K X100-0001-0100-XXXX C System clock source, on-chip RC oscillator EXT (X¢TAL) X100-0001-0101-XXXX C System clock source, external 32kHz clock source or crystal oscillator 32.768kHz LARGE BIAS X100-0001-0110-XXXX C Large bias current option MIDDLE BIAS X100-0001-0111-XXXX C Middle bias current option SMALL BIAS X100-0001-1000-XXXX C Small bias current option BIAS 1/6 X100-0001-1010-XXXX C LCD 1/6 bias option BIAS 1/5 X100-0001-1001-XXXX C LCD 1/5 bias option FRAME 170Hz X100-0001-1100-XXXX C Selects 170Hz frame frequency FRAME 89Hz X100-0001-1101-XXXX C Selects 89Hz frame frequency FRAME 64Hz X100-0001-1110-XXXX C Selects 64Hz frame frequency Select 80´16 X100-0001-1111-XXXX C This command will change segment from 64 to 80 and common from 32 to 16 F1 X100-1010-0000-XXXX C Time base clock output: 1Hz The WDT time-out flag after 4s F2 X100-1010-0001-XXXX C Time base clock output: 2Hz The WDT time-out flag after 2s F4 X100-1010-0010-XXXX C Time base clock output: 4Hz The WDT time-out flag after 1s Rev. 1.80 15 Yes Yes Yes Yes Yes November 9, 2010 PATENTED Name Command Code D/C HT1650 Function Def. F8 X100-1010-0011-XXXX C Time base clock output: 8Hz The WDT time-out flag after 1/2s F16 X100-1010-0100-XXXX C Time base clock output: 16Hz The WDT time-out flag after 1/4s F32 X100-1010-0101-XXXX C Time base clock output: 32Hz The WDT time-out flag after 1/8s F64 X100-1010-0110-XXXX C Time base clock output: 64Hz The WDT time-out flag after 1/16s F128 X100-1010-0111-XXXX C Time base clock output: 128Hz The WDT time-out flag after 1/32s TEST X100-1111-1111-XXXX C Test mode, not for use by the user NORMAL X100-1111-1110-XXXX C Normal mode, 64´32 mode will be set Note: Yes Yes ²X² stands for don¢t care A8~A0: RAM address D3~D0: RAM data D/C: Data/Command mode Def.: Power-on reset default All the bold forms, namely, 1 1 0, 1 0 1, and 1 0 0, are mode commands. Of these, 1 0 0 indicates the command mode ID. If successive commands have been issued, the command mode ID except for the first command will be omitted. The tone frequency source and the time base or WDT clock frequency source can be derived from an on-chip 32kHz RC oscillator, a 32.768kHz crystal oscillator, or an external 32kHz clock. Calculation of the frequency is based on the system frequency sources as stated above. It is recommended that the host controller should initialize the HT1650 after power-on reset, otherwise, power on reset may fail, which in turn leads to the malfunctioning of the HT1650. Rev. 1.80 16 November 9, 2010 PATENTED HT1650 Package Information 128-pin QFP (14mm´20mm) Outline Dimensions C H D 1 0 2 G 6 5 I 6 4 1 0 3 F A B E 1 2 8 3 9 K a J 3 8 1 Symbol A Rev. 1.80 Dimensions in inch Min. Nom. Max. 0.669 ¾ 0.689 B 0.547 ¾ 0.555 C 0.906 ¾ 0.925 D 0.783 ¾ 0.791 E ¾ 0.020 ¾ F ¾ 0.008 ¾ G 0.098 ¾ 0.122 H ¾ ¾ 0.134 I ¾ 0.004 ¾ J 0.026 ¾ 0.037 K 0.004 ¾ 0.008 a 0° ¾ 7° 17 November 9, 2010 PATENTED Symbol A Rev. 1.80 HT1650 Dimensions in mm Min. Nom. Max. 17.00 ¾ 17.50 B 13.90 ¾ 14.10 C 23.00 ¾ 23.50 D 19.90 ¾ 20.10 E ¾ 0.50 ¾ F ¾ 0.20 ¾ G 2.50 ¾ 3.10 H ¾ ¾ 3.40 I ¾ 0.10 ¾ J 0.65 ¾ 0.95 K 0.10 ¾ 0.20 a 0° ¾ 7° 18 November 9, 2010 PATENTED HT1650 Holtek Semiconductor Inc. (Headquarters) No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan Tel: 886-3-563-1999 Fax: 886-3-563-1189 http://www.holtek.com.tw Holtek Semiconductor Inc. (Taipei Sales Office) 4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan Tel: 886-2-2655-7070 Fax: 886-2-2655-7373 Fax: 886-2-2655-7383 (International sales hotline) Holtek Semiconductor Inc. (Shenzhen Sales Office) 5F, Unit A, Productivity Building, No.5 Gaoxin M 2nd Road, Nanshan District, Shenzhen, China 518057 Tel: 86-755-8616-9908, 86-755-8616-9308 Fax: 86-755-8616-9722 Holtek Semiconductor (USA), Inc. (North America Sales Office) 46729 Fremont Blvd., Fremont, CA 94538, USA Tel: 1-510-252-9880 Fax: 1-510-252-9885 http://www.holtek.com Copyright Ó 2010 by HOLTEK SEMICONDUCTOR INC. The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. Holtek¢s products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw. Rev. 1.80 19 November 9, 2010