ISL6745 ® PRELIMINARY Data Sheet November 22, 2004 FN9161.3 主要特点 数据资料 精确的死区時間控制的桥型控制器 ISL6745是成本低、双端控制器。主要应用于全桥和半桥型拓 扑结构的电源和线调节的总线变换器。器件的主要特点是精 确的开关频率控制、可调软启动、和过流关断保护。另外， ISL6745 可 精 确 地 调 整 MOSFET 不 交 迭 的 死 区 時 間 低 至 35ns ， 允 許 电 源 设 计 师 优 化 开 环 总 线 变 换 器 的 效 率 。 ISL6745 还包括电压控制输入适合于闭环PWM控制和线压前 馈控制。 ISL6745的低启动和运作电流特点，使其在AC-DC和DC-DC 应用容易地偏压。 这先进的BiCMOS设计特点是可调开关频率高至1MHz，1A FET驱动器，和非常低的传输延迟适合于过流快反应。 定购资料 零件号码 温度范围(°C) 包装 包装图号 # ISL6745AU ISL6745AUZ (See Note) -40 to 105 10 Ld MSOP 10 Ld MSOP (Pb-free) M10.118 -40 to 105 M10.118 • • • • • • • • • • • 精确的占空比和死区時間控制 100µA 启动电流 可调延迟过流关断和重新启动 可调振荡器频率高至 2MHz 1A MOSFET 门极驱动器 可调软启动 内部过热保护 控制到输出的延迟是 35ns 体积小和极少的外部元件 输入欠压保护 不含 Pb 的包装 应用 • • • • 半桥和全桥型拓扑结构的变换器 线调节的总线变换器 AC-DC 电源 通信、信息和档案服务器的电源 插脚引线 (顶视图) Add -T suffix to part number for tape and reel packaging NOTE: Intersil Pb-free products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020C. 1 ISL6745 (MSOP) SS 1 10 VDD RTD 2 9 VDDP VERR 3 8 OU TB CS 4 7 OU TA CT 5 6 GN D CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143|Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2004. All Rights Reserved All other trademarks mentioned are the property of their respective owners ISL6745 VDDP FL VBIAS VBIAS 5.00 V VDD OUTA Q UVLO + - BG T Q OUTB PWM TOGGLE VBIAS INTERNAL OT SHUTDOWN 130 - 150 C 70 uA GND ON SS VBIAS + - SS CLAMP RTD - 2.0 V IRTD + - + 15 uA SS CHARGED 3.9 V 4.0 V VBIAS 160 uA S Q R Q OC LATCH ON - 2.8 V PEAK + CT - I DCH= 55 x IRTD Q R Q CLK RESET DOMINANT VALLEY + 0.8 V S Q SS LOW Q 50 µS RETRIGGERABLE ONE SHOT FAULT LATCH SET DOMINANT S Q IDCH R Q S Q R Q PWM LATCH SET DOMINANT ON VBIAS UV + BG 0.6 V + - OC DETECT PWM COMPARATOR VBIAS + - CT 15 uA VERR SS 0.8 0.8 ISL6745 内部电路结构 2 SS FL VBIAS 4.65V ↓ 4.80V ↑ CS 0.27 V + - ISL6745 额定值 Voltage Ratings bsolute 热性能的资料 Thermal Information Supply Voltage, VDD ----------------------GND-0.3V to +20V OUTA, OUTB ------------------------------- GND -0.3V to VDD Signal Pins------------------------------------- GND-0.3V to 5V Peak GATE Current ------------------------------------------- 1A ESD Classification Thermal Resistance (Typical, Note 1) ---------- θJA ( C/W) 10 Lead MSOP ------------------------------------------------ 128 o o Maximum Junction Temperature ---------- -55 C to 150 C o o Maximum Storage Temperature Range - -65 C to 150 C o Maximum Lead Temperature (Soldering 10s)------300 C o Human Body Model (Per JEDEC22 std. Method A114-B)---Class 2 Machine Model (Per JEDEC22 std. Method A115-A)---------Class A Recommended Operating Conditions 运行条件 Supply Voltage Range (Typical) -------------------9-16VDC Temperature Range o o ISL6745AU--------------------------------- -40 C to 105 C CAUTION: Stress above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. NOTES: 1) θJA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 2) All voltages are to be measured with respect to GND, unless otherwise specified. Electrical Specifications 电气规范 Recommended Operating Conditions, Unless Otherwise Noted. Refer to Block Diagram and Typical Application Schematic. o o o 9V<VDD<16V, RTD= 51.1KΩ, CT = 470pF, TA = -40 C to 105 C (Note 4), Typical values are at TA= 25 C. PARAMETER TEST CONDITIONS MIN TYP MAX UNITS SUPPLY VOLTAGE Start-Up Current, IDD VDD< START Threshold - - 175 µA Operating Current, IDD COUTA, B = 1nF - 5 8.5 mA 5.9 6.3 6.6 V UVLO START Threshold UVLO STOP Threshold Hysteresis 5.3 5.7 6.3 V - 0.6 - V 0.55 0.6 0.65 V CURRENT SENSE Current Limit Threshold (Note 4) - 35 - ns CS Sink Current 8 10 - mA Input Bias Current -1 - 1 µA CS to OUT Delay PULSE WIDTH MODULATOR Minimum Duty Cycle VERROR < CT Offset - - 0 % Maximum Duty Cycle CT = 470pF, RTD = 51.1KΩ - 94 - % CT = 470pF, RTD = 1.1KΩ (Note 4) - 99 - % VERR to PWM Comparator Input Gain - 0.8 - V/V CT to PWM Comparator Input Gain (Note 4) - 1 - V/V SS to PWM Comparator Input Gain (Note 4) - 0.8 - V/V 143 156 170 µA 1.925 2 2.075 V 45 - 65 µA/µA OSCILLATOR o TA = 25 C Charge Current RTD Voltage Discharge Current Gain 3 ISL6745 Electrical Specifications 电气规范 Recommended Operating Conditions, Unless Otherwise Noted. Refer to Block Diagram and Typical Application Schematic. o o o 9V<VDD<16V, RTD= 51.1KΩ, CT = 470pF, TA = -40 C to 105 C (Note 4), Typical values are at TA= 25 C. (Continued) PARAMETER TEST CONDITIONS MIN TYP MAX UNITS CT Valley Voltage 0.75 0.8 0.85 V CT Peak Voltage 2.70 2.80 2.90 V 45 - 68 µA 3.8 4.0 4.2 V - 3.9 - V 12 15 23 µA 0.25 0.27 0.30 V - 0.5 2.0 V Low Level Output Voltage (VOL) VDD – VOUTA or VOUTB, IOUT = -100mA IOUT = 100mA - 0.5 1.0 V Rise Time CGATE = 1nF, VDD = 12V - 17 60 ns Fall Time CGATE = 1nF, VDD = 12V - 20 60 ns Thermal Shutdown (Note 4) - 145 - o Thermal Shutdown Clear (Note 4) - o Hysteresis, Internal Protection (Note 4) - o SOFT-START Net Charging Current SS Clamp Voltage Overcurrent Shutdown Threshold Voltage Overcurrent Discharge Current (Note 4) Reset Threshold Voltage (Note 4) OUTPUT High Level Output Voltage (VOH) THERMAL PROTECTION NOTES: o 3. Specifications at -40 C are guaranteed by design, not production tested. 4. Guaranteed by design, not 100% tested in production. 4 - 130 15 C C C ISL6745 典型性能曲线图 5 ISL6745 OUTA and OUTB ISL6745各管脚简介 OUTA 和 OUTB 为交替半周期输出端。每个输出具有 1A 峰 VDD 值电流的输出能力可驱动 MOSFETs 或 MOSFET 驱动器，且 VDD 为电源输入端。要优化抗扰度，用一个陶瓷电容器尽可 能靠近并挎接在VDD和GND引脚。 以非常低的阻抗降低过冲和下冲。 SS IC总供应电流，IDD ，取决于OUTA和OUTB输出端的负载。 IDD 电流是 静态电流和平均输出电流的总和。平均输出电流 (IOUT)与操工作频率(FSW)和每输出端的负载电容的电荷量(Q) 在这个引脚与 GND 之间连接软启动定时电容器来控制软启动 的时间。电容值决定启动时占空比的增长率，且控制过流关 断延迟和过流与短路间歇再启动周期。 成正比，其值可用下式 计 算: IOUT = 2 × Q × FSW (EQ. 1) 功能概述 RTD 这是振荡器定时电容放电电流控制引脚。一个电阻器应连接 主要特点 在这引脚和GND之间。而流经这个电阻的电流决定放电电流 ISL6745 为那些以低成本的桥型拓扑结构且要求准确频率和 的大小。放电电流的通常值则是这电流的55倍。PWM死区时 死区时间控制的应用提供了一个极佳的选择。它有很多特 间由定时电容放电时间决定。 点，其中有 1AFET 驱动器、可调软启动、过流保护和内部过 热保护，因而 ISL6745 能以最少量的外部元件做出一个高度 CT 灵活的设计。 振荡器定时电容应连接在这引脚和GND之 间。 CS 振荡器 ISL6745通过改变电阻RTD 和电容CT 来调振荡器频率高达2M 这是过流保护比较器的输入端。过流比较器门限值设置为典 Hz。开关周期是定时电容充电和放电时间之和。充电时间由 型值0.600V。在每个开关周期的末端，CS引脚短接于GND。 CT和内部电流源(在式中采用160µA)决定，而放电时间取决于 根据电流传感源阻抗，由于内部时钟和外部电力开关间的延 RTD 和CT。 迟，可能要求串联一个电阻。 超出过流门限值会启动延迟关断程序。一旦检测出过流情 况，软启动充电电流源就会被截止。而软启动电容通过15µA 电流源放电，如果软启动电压降至于3.9V(可承受的过流门限 值) 关断条件出现，OUTA和OUTB输出会强制降低。当软启 动电压降至0.27V(重新设置门限值)，一个新软启动周期开 TC ≈ 1.25 × 10 4 • CT TD ≈ s (EQ.2) 1 • RTD • CT CTDisch arg eCurrentGain TOSC = TC + TD = 1 FOSC s s (EQ. 3) (EQ. 4) 始。 TC和TD分别是大概的充电和放电时间，TOSC是振荡器自由运 如 果 过 流 情 况 中 断 ， 且 在 50µs 时 间 内 未 达 到 关 断 门 限 值 行 周 期 ， 而 FOSC 是 振 荡 器 频 率 。 放 电 电 流 增 益 （3.9V），过流关断是不会发生。软启动充电电流重新运行 (DischargeCurrentGain=45 to 65)可在第3页的表(或Figure1) 且软启动电压复位。 找到。一个输出的开关周期等于二个振荡器周期。由于传输 GND 延迟约5ns，实际 时间比所计算的时间稍微长。这个延迟直 接增加到开关时间，且引起定时电容峰值和谷电压门限过 器件上所有功能和电源地都以这个引脚为基准。由于高峰值 电流和高频工作，布局必须是低阻抗的。故建议使用地线板 块和短接线。 冲，因而增大了定时电容峰-峰的电压。另外，如果使用非常 低充电和 放电电流， 时间误差将会因CT引脚处的输入阻抗而 增加。 6 ISL6745 EQ.2至4可帮助估计振荡器频率。在实际上，寄生电部的CT 过热保护 电容，RTD电压的变化和充电电流遍及温度的变化及其他变化 内热传感器保护器件芯片结温不超出145˚C，而热迟滞约15˚ 是不可被忽视的。这些对频率的影响最好在真的电路板里评 价。EQ. 2依据于基本的电容电流公式，I=C*dV/dt。根据RTD 电压的变化(如图4)和充电电流变化(如图5)，公式2的结果将 会不同计算出的结果。典型性能曲线和上述的公式一起更精 确地估计工作频率。 最大占空比（DMAX）和死区时间（DT）可用以下公式计算： DMAX = TC (EQ. 5) TOSC DT = TOSC × (1 − DMAX ) (EQ. 6) 软启动运作 ISL6745使用外部电容和内部电流电源来作软启动。软启动降 低启动期间的电压和浪涌电流。 在用以驱动 PWM 门控的软启动比较器里，振荡器电容 CT 信 号与软启动 SS 电压作比较。当软启动电压（SS）少于 2.8V 时，占空比会受到限制。输出脉宽随着软启动电容电压的增 加而增加。这使软启动期间的占空比可从零增加到最大脉 宽。当软启动电压超过 2.8V，软启动完成。软启动开始于起 动或因过流关断而复位时。 软启动电压被钳位在 4V. 门极驱动器 ISL6745可灌出和吸收1A峰值电流，且可连接一个MOSFET 驱动器如ISL6700作电平转移之用。如要限制峰值电流通过 IC，一个外部电阻应连接在IC的推拉输出(OUTA或OUTB引 脚)和 MOSFET的门极之间。而这个小串联电阻能阻尼由线组 寄生 电感和FET的输入电容的共振所产生的振荡。 过流运作 软启动周期完成后，过流延迟关断保护才启动。如果检测出 过流情况，软启动充电电流电源就会中止，且软启动电容通 过15µA电源放电。过流情况停止后，在50µs时间内，如果软 启动电容器放电至3.9V，输出停止。这种状态持续到软启动 电压降至270mV，开始新软启动周期。如果在软启动电压降 至的3.9V前，且过流情况停止至少50µs，软启动充电电流会 恢复正常运作，而软启动电压会复位。 7 C。 ISL6745 Mini Small Outline Plastic Packages (MSOP) M10.118 (JEDEC MO-187BA) E1 10 LEAD SHRINK NARROW BODY SMALL OUTLINE PLASTIC PACKAGE E SYMBOL -B- INDEX AREA 1 2 0.20 (0.008) A B C 4X θ R1 GAUGE PL ANE SEATING PLANE -CA 4X θ A2 A1 0.10 (0.004) b -H- L L1 SEATING PLANE C -A- e D C C a SIDE VIEW CL E1 0.20 (0.008) C D -B- END VIEW NOTES: 1. These package dimensions are within allowable dimensions of JEDEC MO-187BA. 2. Dimensioning and tolerancing per ANSI Y14.5M-1994. 3. Dimension “D” does not include mold flash, protrusions or gate burrs and are measured at Datum Plane. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E1” does not include interlead flash or protrusions and are measured at Datum Plane. Interlead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. Formed leads shall be planar with respect to one another within 0.10mm (.004) at seating Plane. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension “b” does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of “b” dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07mm (0.0027 inch). 10. Datums -A- and -B-to be determined at Datum plane -H- . 11. Controlling dimension: MILLIMETER. Converted inch dimensions are for reference only NOTES MAX MIN MAX A 0.037 0.043 0.94 1.10 - A1 0.002 0.006 0.05 0.15 - A2 0.030 0.037 0.75 0.95 - b 0.007 0.011 0.18 0.27 9 c 0.004 0.008 0.09 0.20 - D 0.116 0.120 2.95 3.05 3 E1 0.116 0.120 2.95 3.05 4 e 0.20 (0.008) MILLIMETERS MIN T OP VIEW 0.25 (0.010) INCHES 0.020 BSC 0.50 BSC - E 0.187 0.199 4.75 5.05 - L 0.016 0.028 0.40 0.70 6 L1 0.037 REF 0.95 REF - N 10 10 7 R 0.003 - R1 0.003 - θ α 5 o 15 0 o o 6 o 0.07 - 0.07 - 5 o 15 0 o 6 o o Rev.0 12/02 All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 8