High Frequency AGC Has Digital Control TM Application Note June 1998 AN9816 Introduction The gain span limits the AGC circuit’s ability to compensate for input voltage changes greater than the gain span, 16.8dB. If the input voltage change will exceed the gain span it can be almost doubled by putting two long-tailed pair in series; this is aided by the HFA3102 because it contains two long-tailed pairs. AC connect the collectors of the first stage differently to the bases of the second stage. Connecting the bases of the current source transistors in parallel enables the AGC circuit to maintain the same control function, while the gains of the two long-tailed pairs are multiplied thus, essentially doubling the gain span. Many systems (especially communications) require an AGC which will function at 50MHz. Self-calibrating systems such as automatic test equipment also need the high frequency response, but they add a requirement that the AGC output voltage be set by a digital signal. During the calibration cycle this test equipment will calculate the AGC output voltage needed to achieve the accuracy requirements, and they will increment the AGC output voltage until the system is within specifications. The AGC circuit described in Figure 1 uses a DAC to accomplish the digital control, and because the DAC is the reference input for the AGC circuit, it ultimately sets the AGC output voltage. The HI5731 was chosen for the DAC because it is inexpensive, it functions with 5V supplies, the output interfaces well with the AGC circuit, and it can be updated at a 100MHz rate. The heart of the AGC circuit is a variable gain amplifier made from a three transistor, longtailed pair configuration, Q1, Q2, and Q3. When the base voltage of Q3 is varied the emitter current of the long-tailed pair changes, forcing a gain change according to the following equation, where K is a function of the emitter current and VB3 is the base voltage of Q3: (EQ. 1) G = KV IN V B3 The gain-control and bias-stability parameters of the circuit depend on the transistor matching, so the circuit uses a HFA3102-matched, long tailed array for Q1 through Q3. The usable range of VB3 is -0.04 to -4.1V, which corresponds to a gain range of 0.8 to 17.6dB, respectively (VIN = 100mV). This gain span is a total of 16.8dB. The gain is proportional to R4. Increasing R4 increases the gain, but the gain span stays constant at approximately 16.8dB while the frequency response decreases. 3-1 1-888-INTERSIL or 321-724-7143 The input signal is amplified by the long-tailed pair to make the gained up output signal, which in turn is half-wave rectified by the HFA1103 to produce a quasi DC control voltage. The HFA1103 is a high speed op amp that has the lower half of the output stage disconnected, so because the output can’t go below ground it make a fine half wave rectifier or sync stripper. R9, through R12 set the gain to two, and add a few mV of bias to ensure that the output is always positive. This DC voltage is compared with the DAC output voltage in the input stage of the CA5160 integrator. Because the integrator has a large DC gain it’s output voltage will swing to any point within the supplies in an attempt to lock the loop. The DAC output sinks current from ground. R5 and R16 form a voltage divider with DC offset, and this DC voltage, which is the reference input, VR, for the AGC circuit, is compared with the output of U1 in the integrator, U2. The signal path has excellent frequency response because the HFA3102 is the only component in the signal path. The control path through U1 does not have quite as good a frequency response, so R4 or the input signal must be increased to provide control past 50MHz. The DAC transfers the digital input to an internal register on the rising edge of the clock pulses. The circuit uses the non-inverting DAC output to yield a positive-increasing transfer function, but you can obtain the inverse-transfer function by using the inverting DAC output (Table 1). | Intersil and Design is a trademark of Intersil Corporation. | Copyright © Intersil Corporation 2000 Application Note 9816 TABLE 1. AGC PERFORMANCE SUMMARY PARAMETER MINIMUM MAXIMUM Gain (dB) 0.8 17.6 VB3 (V) -0.04 -4.1 VR (V) -0.045 -0.275 Digital Input/Non-Inverting Output 1111 1111 1111 0000 0000 0000 0000 Digital Input/Inverting Output 0000 0000 0000 0000 1111 1111 1111 1111 the interface circuit (U2 and associated components) if the DAC output current swing changes. If the value of C1 is decreased the amplitude of the output signal will tend to follow the DAC updates, thus, if the DAC updates are done in a sinusoidal manner the output signal will be amplitude modulated by the DAC update frequency. Fast DAC updates will not affect the output signal with the selected value of C1 = 1µF because the integrator filters out the change. When the DAC updates, the output voltage will slowly change to the new value. If the circuit is only used for system calibration where slow DAC updates are the rule, you can use a slower DAC. However, you may have to redesign +5 R4 200 +5 SIGNAL INPUT Q1 OUTPUT 0.1 Q2 R3 1K R1 1K +5V R2 140 U2 +5 CA5160 7 + 4 -5V +5V +5V C1 1µF HFA3102 Q3 HI5731 VCC 0.2 HFA3102 -5 U3 R8 10K R9 5600 6 R6 10K 0.1 0.01 CONTROL IN 0.1 D0 DIGITAL INPUT D11 U1 3 HFA1103 + - 2 4 R7 1K -5 -5V -5V R5 1.33K CONTROL OUT R10 49.9 R11 750 R12 750 IOUT CLK 0.1 RESET 0.01 R16 13.3 V R IOUT R13 50 DVEE ARTN AVEE AGND R14 976 R15 50 Q1 - Q3, HFA3102 -5V -5V 0.1 0.01 FIGURE 1. HIGH FREQUENCY AGC HAS DIGITAL CONTROL All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. 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