CA5260, CA5260A ® Data Sheet August 3, 2010 3MHz, BiMOS Microprocessor Operational Amplifiers with MOSFET Input/CMOS Output The CA5260A and CA5260 are integrated-circuit operational amplifiers that combine the advantage of both CMOS and bipolar transistors on a monolithic chip. The CA5260 series circuits are dual versions of the popular CA5160 series. They are designed and guaranteed to operate in microprocessor or logic systems that use +5V supplies. Gate-protected P-Channel MOSFET (PMOS) transistors are used in the input circuit to provide very-high-input impedance, very-low-input current, and exceptional speed performance. The use of PMOS field-effect transistors in the input stage results in common-mode input-voltage capability down to 0.5V below the negative-supply terminal, an important attribute in single-supply applications. A complementary-symmetry MOS (CMOS) transistor-pair, capable of swinging the output voltage to within 10mV of either supply-voltage terminal (at very high values of load impedance), is employed as the output circuit. The CA5260 Series circuits operate at supply voltages ranging from 4.5V to 16V, or ±2.25V to ±8V when using split supplies. The CA5260, CA5260A have guaranteed specifications for 5V operation over the full military temperature range of -55°C to +125°C. FN1929.8 Features • MOSFET Input Stage provides - Very High ZI . . . . . . . . . . . . . 1.5TΩ (1.5 x 1012Ω) (Typ) - Very Low II . . . . . . . . . . . . . 5pA (Typ) at 15V Operation 2pA (Typ) at 5V Operation • Ideal for Single Supply Applications • Common Mode Input Voltage Range Includes Negative Supply Rail; Input Terminals Can be Swung 0.5V Below Negative Supply Rail • CMOS Output Stage Permits Signal Swing to Either (or Both) Supply Rails • CA5260A, CA5260 Have Full Military Temperature Range Guaranteed Specifications for V+ = 5V • CA5260A, CA5260 are Guaranteed to Operate Down to 4.5V for AOL • Fully Guaranteed to Operate from -55°C to +125°C at V+ = 5V, V- = GND • Pb-Free Available (RoHS Compliant) Applications • Ground Referenced Single Supply Amplifiers • Fast Sample-Hold Amplifiers • Long Duration Timers/Monostables • Ideal Interface with Digital CMOS • High Input Impedance Wideband Amplifiers Pinout • Voltage Followers (e.g., Follower for Single Supply D/A Converter) CA5260, CA5260A (8 LD SOIC) TOP VIEW OUTPUT (A) 1 • Voltage Regulators (Permits Control of Output Voltage Down to 0V) • Wien Bridge Oscillators 8 V+ 7 OUTPUT (B) 6 INV. INPUT (B) 5 NON INV. INPUT (B) A INV. INPUT (A) 2 NON INV. INPUT (A) 3 V- 4 - + • Voltage Controlled Oscillators • Photo Diode Sensor Amplifiers B + - 1 • 5V Logic Systems • Microprocessor Interface CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2003, 2004, 2009, 2010. All Rights Reserved All other trademarks mentioned are the property of their respective owners. CA5260, CA5260A Ordering Information PART NUMBER (Note 3) PART MARKING TEMP. RANGE (°C) PACKAGE (Pb-Free) PKG. DWG. # CA5260AM96 (Note 1) 5260A -55 to +125 8 Ld SOIC (Tape and Reel) M8.15 CA5260MZ96 (Note 2) CA5260 MZ -55 to +125 8 Ld SOIC M8.15 CA5260M (Notes 1) 5260 -55 to +125 8 Ld SOIC (Tape and Reel) M8.15 CA5260MZ (Note 2) CA5260 MZ -55 to +125 8 Ld SOIC M8.15 NOTES: 1. Please refer to TB347 for details on reel specifications. 2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 3. For Moisture Sensitivity Level (MSL), please see device information page for CA5260, CA5260A. For more information on MSL please see techbrief TB363. 2 FN1929.8 August 3, 2010 CA5260, CA5260A Absolute Maximum Ratings Thermal Information Supply Voltage (Between V+ and V- Terminals) . . . . . . . . . . . . 16V Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8V Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . (V+ +8V) to (V- -0.5V) Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1mA Output Short Circuit Duration (Note 4). . . . . . . . . . . . . . . . Indefinite Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C Thermal Resistance (Typical, Note 5) θJA (°C/W) SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 Maximum Junction Temperature (Die) . . . . . . . . . . . . . . . . . . . 175°C Maximum Junction Temperature (Plastic Package) . . . . . . +150°C Maximum Storage Temperature Range . . . . . . . . . -65°C to +150°C Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 4. Short circuit may be applied to ground or to either supply. 5. θJA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications Typical Values Intended Only for Design Guidance, V+ = 5V, V- = 0V, TA = +25°C, Unless Otherwise Specified TYPICAL VALUES PARAMETER SYMBOL Input Resistance RI Input Capacitance CI Unity Gain Crossover Frequency fT Slew Rate SR Transient Response Rise Time tr Overshoot OS Settling Time (To <0.1%, VIN = 4VP-P) Electrical Specifications PARAMETER tS TEST CONDITIONS CA5260 CA5260A UNITS 1.5 1.5 TΩ 4.3 4.3 pF 3 3 MHz 5 5 V/µs 0.09 0.09 µs 10 10 % 1.8 1.8 µs f = 1MHz VOUT = 2.5VP-P CL = 25pF, RL = 2kΩ (Voltage Follower) CL = 25pF, RL = 2kΩ (Voltage Follower) TA = +25°C, V+ = 5V, V- = 0V SYMBOL TEST CONDITIONS CA5260 CA5260A MIN TYP MAX MIN TYP MAX UNITS Input Offset Voltage VIO VO = 2.5V - 2 15 - 1.5 4 mV Input Offset Current IIO VO = 2.5V - 1 10 - 1 10 pA II VO = 2.5V - 2 15 - 2 15 pA VCM = 0V to 1V 70 85 - 74 85 - dB VCM = 0V to 2.5V 50 55 - 50 55 - dB Input Current Common Mode Rejection Ratio CMRR Common Mode Input Voltage Range VlCR+ 2.5 3 - 2.5 3 - V VlCR- - -0.5 0 - -0.5 0 V Power Supply Rejection Ratio PSRR 70 84 - 75 84 - dB - 111 - - 113 - dB 80 86 - 83 86 - dB Large Signal Voltage Gain (Note 6) Source Current Sink Current AOL ΔV+ = 1V; ΔV- = 1V RL = ∞, VO = 0.5V to 4V RL = 10kΩ, VO = 0.5V to 3.6V ISOURCE VO = 0V 1.75 2.2 - 1.75 2.2 - mA ISINK VO = 5V 1.70 2 - 1.70 2 - mA 3 FN1929.8 August 3, 2010 CA5260, CA5260A Electrical Specifications PARAMETER TA = +25°C, V+ = 5V, V- = 0V (Continued) TEST CONDITIONS SYMBOL Output Voltage TYP MAX MIN TYP MAX UNITS 4.99 5 - 4.99 5 - V - 0 0.01 - 0 0.01 V 4.4 4.7 - 4.4 4.7 - V - 0 0.01 - 0 0.01 V 3 3.4 - 3 3.4 - V - 0 0.01 - 0 0.01 V VO = 0V - 1.60 2.0 - 1.60 2.0 mA VO = 2.5V - 1.80 2.25 - 1.80 2.25 mA TYP MAX (Note 8) UNITS VOMVOM+ RL = 10kΩ VOMVOM+ RL = 2kΩ VOMSupply Current ISUPPLY CA5260A MIN RL = ∞ VOM+ CA5260 NOTE: 6. For V+ = 4.5V and V- = GND; VOUT = 0.5V to 3.2V at RL = 10kΩ. Electrical Specifications TA = -55°C to +125°C, V+ = 5V, V- = 0V CA5260 PARAMETER SYMBOL TEST CONDITIONS MIN (Note 8) TYP CA5260A MAX MIN (Note 8) (Note 8) Input Offset Voltage VIO VO = 2.5V - 3 20 - 2 15 mV Input Offset Current IIO VO = 2.5V - 1 10 - 1 10 nA II VO = 2.5V - 2 15 - 2 15 nA VCM = 0 to 1V 60 78 - 65 78 - dB VCM = 0 to 2.5V 50 60 - 50 60 - dB Input Current Common Mode Rejection Ratio CMRR Common Mode Input Voltage Range VlCR+ 2.5 3 - 2.5 3 - V VlCR- - -0.5 0 - -0.5 0 V Power Supply Rejection Ratio PSRR ΔV+ = 1V; ΔV- = 1V 60 65 - 62 65 - dB RL = ∞, VO = 0.5 to 4V 70 78 - 70 78 - dB RL = 10kΩ, VO = 0.5 to 3.6V 60 65 - 60 65 - dB ISOURCE VO = 0V 1.3 1.6 - 1.3 1.6 - mA Sink Current ISINK VO = 5V 1.2 1.4 - 1.2 1.4 - mA Output Voltage VOM+ RL = ∞ 4.99 5 - 4.99 5 - V - 0 0.01 - 0 0.01 V 4.2 4.4 - 4.2 4.4 - V - 0 0.01 - 0 0.01 V 2.5 2.7 - 2.5 2.7 - V - 0 0.01 - 0 0.01 V VO = 0V - 1.65 2.2 - 1.65 2.2 mA VO = 2.5V - 1.95 2.35 - 1.95 2.35 mA Large Signal Voltage Gain (Note 7) Source Current AOL VOMVOM+ RL = 10kΩ VOMVOM+ RL = 2kΩ VOMSupply Current ISUPPLY NOTES: 7. For V+ = 4.5V and V- = GND; VOUT = 0.5V to 3.2V at RL = 10kΩ. 8. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. 4 FN1929.8 August 3, 2010 CA5260, CA5260A Electrical Specifications Each Amplifier at TA = +25°C, V+ = 15V, V- = 0V, Unless Otherwise Specified PARAMETER SYMBOL TEST CONDITIONS CA5260 CA5260A MIN TYP MAX MIN TYP MAX UNITS Input Offset Voltage VIO VS = ±7.5 - 6 15 - 2 5 mV Input Offset Current IIO VS = ±7.5 - 0.5 30 - 0.5 20 pA II VS = ±7.5 - 5 50 - 5 30 pA 40 320 - 40 320 - kV/V 92 110 - 92 110 - dB CMRR 70 90 - 80 95 - dB Common Mode Input Voltage Range VlCR 10 -0.5 to 12 0 10 -0.5 to 12 0 V Power Supply Rejection Ratio, ΔVIO/ ΔV± PSRR VS = ±7.5 - 32 320 - 32 150 µV/V Maximum Output Voltage VOM+ RL = 10kΩ 11 13.3 - 11 13.3 - V - 0.002 0.01 - 0.002 0.01 V 14.99 15 - 14.99 15 - V - 0 0.01 - 0 0.01 V 12 22 45 12 22 45 mA 12 20 45 12 20 45 mA VO (Amp A) = 7.5V VO (Amp B) = 7.5V - 9 16.5 - 9 16.5 mA VO (Amp A) = 0V VO (Amp B) = 0V - 1.2 4 - 1.2 4 mA VO (Amp A) = 0V VO (Amp B) = 7.5V - 5 9.5 - 5 9.5 mA - 8 - - 6 - µV/oC - 120 - - 120 - dB Input Current Large Signal Voltage Gain AOL Common Mode Rejection Ratio VO = 10VP-P, RL = 10kΩ VOMVOM+ RL = ∞ VOMIOM+ (Source) Maximum Output Current VO = 7.5V IOM- (Sink) Total Supply Current, RL = ∞ I+ ΔVIO/ΔT Input Offset Voltage Temperature Drift Crosstalk f = 1kHz 5 FN1929.8 August 3, 2010 CA5260, CA5260A Schematic Diagram V+ 8 AMPLIFIER A Q11 Q7 Q6 Q10 D2 Q13 Q14 C3 D4 R5 2k Q22 Q8 C1 30pF R4 1k R3 1k D5 R12 2k C2 30pF R11 1k R1 1k R2 1k R9 1k Q24 D8 Q16 Q15 Q26 R10 Q27 1k Q18 Q4 Q25 D7 Q19 Q5 Q3 R7 300k Q20 D6 Q1 Q2 Q12 Q21 Q23 Q9 D3 D1 R6 200k AMPLIFIER B Q17 Q28 R14 300Ω R8 1k C4 R13 200k 3 2 1 7 6 5 4 +IN -IN OUT -IN +IN V- 6 FN1929.8 August 3, 2010 CA5260, CA5260A Small Outline Plastic Packages (SOIC) M8.15 (JEDEC MS-012-AA ISSUE C) 8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE N INDEX AREA 0.25(0.010) M H B M INCHES E SYMBOL -B1 2 3 L SEATING PLANE -A- A D h x 45° -C- e A1 B 0.25(0.010) M C 0.10(0.004) C A M MIN MAX MIN MAX NOTES A 0.0532 0.0688 1.35 1.75 - A1 0.0040 0.0098 0.10 0.25 - B 0.013 0.020 0.33 0.51 9 C 0.0075 0.0098 0.19 0.25 - D 0.1890 0.1968 4.80 5.00 3 E 0.1497 0.1574 3.80 4.00 4 e α B S 0.050 BSC 1.27 BSC - H 0.2284 0.2440 5.80 6.20 - h 0.0099 0.0196 0.25 0.50 5 L 0.016 0.050 0.40 1.27 6 N α NOTES: MILLIMETERS 8 0° 8 8° 0° 7 8° 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95. Rev. 1 6/05 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 7 FN1929.8 August 3, 2010