Application Note 1516 EBL4270-EVALZ: QLx4270-DP Display Port Lane Extender Evaluation Board User Guide Table of Contents Introduction ........................................................................................................................................ 2 Operation of Evaluation Board ............................................................................................................. 2 QLx4270 Board ................................................................................................................................. Power Supply ................................................................................................................................... Providing Power from External 5V Power Supply ................................................................................ High Speed Data_I/O Interface Connectors........................................................................................... Detection Threshold (DT) ................................................................................................................... Impedance Select ............................................................................................................................. Boost Setting Control Pins .............................................................................................................. 2 2 3 3 4 4 5 Evaluation Board Schematic ................................................................................................................ 7 QLx4270 Bill of Materials..................................................................................................................... 8 About Q:ACTIVE® ................................................................................................................................ 9 January 18, 2010 AN1516.0 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2010. All Rights Reserved All other trademarks mentioned are the property of their respective owners. Application Note 1516 Introduction Operation of Evaluation Board The QLx4270 Evaluation Board is a versatile stand-alone card developed to evaluate the performance of Intersil QLx4270 Quad Equalizer. After a brief description of the board design and layout we will describe the different features and options to operate the board. In particular we will describe: The Evaluation Kit Includes: • Providing power to the board through an external supply • EBL4270-EVALZ evaluation board • Power cable • The eight high speed differential I/O • The impedance select function Key Features • The variable Detection Threshold • QLx4270 series IC • Controling the equalizer boost via Control Pins • Single 5V external power supply QLx4270 Board • On board regulators provide all voltages required for MCU and IC operation • On board DC/DC converter that provides the 1.2V supply to the IC • Optional on board boost selection for each channel via two sets of headers The QLx4270 Evaluation Board is a 4-layer, 4”(w) x 5.6”(h) x 0.059”(t) in dimension, and fabricated with (Allied-Signal) FR-408 dielectric material. 100Ω differential signal traces are laid out with 0.0062” width and 0.0058” spacing. 50Ω single ended traces are 0.009” wide. Figure 1 shows the top view of the board. • Adjustable Detection Threshold for quiescent modes • 8 sets of SMA connectors for high speed signals input and output FIGURE 1. QLx4270 EVALUATION BOARD PCB OUTLINE Power Supply Power can be supplied to the board by using an external power supply. On board voltage regulators supply the appropriate 1.2V to the QLx4270 IC. 2 AN1516.0 January 18, 2010 Application Note 1516 PROVIDING POWER FROM EXTERNAL 5V POWER SUPPLY Table 1 provides description of the connector P1. A power cable is provided with the evaluation kit. The evaluation board can also be powered by an independent external 5.0V power supply via header P1 as highlighted on Figure 2. The maximum current consumption for the board including the voltage regulators, micro-controller circuits, and the IC together is approximately 245mA with all channels active. TABLE 1. P1 CONNECTOR DESCRIPTION 8 – NC 7 – NC 6 – 5.0V 5 – 5.0V 4 – NC 3 – NC 2 – GND 1 – GND High Speed Data_I/O Interface Connectors There are sixteen SMA connectors on the board, eight for the CML differential inputs and eight for the CML differential outputs. All the connections from the SMA connectors to the QLx4270 chip are AC coupled with a 220nF broad band capacitor. Figure 3 shows each channel by their name, direction, and their polarities. FIGURE 2. QLx4270 EVALUATION BOARD EXTERNAL POWER SUPPLY POWER CONNECTOR FIGURE 3. QLx4270 EVALUATION BOARD RF-I/O INTERFACE 3 AN1516.0 January 18, 2010 Application Note 1516 FIGURE 4. QLx4270 EVALUATION BOARD DT POTENTIOMETER Detection Threshold (DT) Impedance Select The DT is another very important feature of the QLx4270 IC. On the evaluation board, the DT can be changed by adjusting the potentiometer VR1 (Figure 4). Two 3x2 headers, JP4 and JP5, provide interfaces to the “impedance select” pins of the QLx4270 ICs. With this function the user can put any equalizer channel into a standby or reset state by placing a jumper across the header for the selected channel. When in the reset state, the single-ended input impedance of the equalizer channel goes in excess of 200kΩ (from its nominal value of 50Ω) to indicate to a transmitter that the receiver channel is down and not passing data. Additionally, power consumption for a channel is reduced when in the standby state. In normal operation, the potentiometer should be set so that the voltage across the adjacent 10K resistor is 0V. For applications that need to adjust this level it can be simply done by changing the potentiometer and reading the voltage across the 10k resistor in order to infer the current coming from the DT pin. For example measuring a voltage of -200mV across the 10K resistor indicates a 20µA current from the DT pin. 4 AN1516.0 January 18, 2010 Application Note 1516 IS1/LOS1 IS2/LOS2 IS4/LOS4 IS3/LOS3 FIGURE 5. QLx4270 EVALUATION BOARD IMPEDANCE SELECT Boost Setting Control Pins In order to enable boost setting control via Control Pins, JP5-pin2 must be jumpered to ground. The boost setting configuration (compensation setting) for each individual equalizer channel is done through a 3x3 header. There are four sets of headers, one for each equalizer channel. Figure 6 illustrates the location of the headers. FIGURE 6. EQUALIZER BOOST CONTROL HEADERS 5 AN1516.0 January 18, 2010 Application Note 1516 The notation CP[1-4]_[A – C] refers to the QLx4270 quad equalizer CPs. They are associated with the 4 channels 3-digit number where ‘A’ is the MSB and ‘C’ is the LSB. Table 2 describes the relationship between the CPs and the equalizer boost setting. Bit A can only take one of two values, either Low (L) or High (H), while bit B and C can take one of three values, Low (L), Middle (M) and High (H). Hence eighteen of the thirty-two different boost levels are accessible through the CPs for each equalizer channel. TABLE 2. CP AND EQUALIZER BOOST SETTING RELATIONSHIP CP[1-4]_A CP[1-4]_B CP[1-4]_C BOOST L L L 0 L L M 2 L L H 4 L M L 6 L M M 8 L M H 10 L H L 12 L H M 14 L H H 15 H L L 16 H L M 17 H L H 19 H M L 21 H M M 23 H M H 24 H H L 26 H H M 28 H H H 31 FIGURE 7. ILLUSTRATION OF SETTINGS FOR CP1 = (H,M,L) AND CP2 = (H,L,L) For channels 3 and 4, we use headers JP1-3 in a similar fashion except High is achieved using the bottom two pins and middle is achieved by using the top two pins. Figure 8 illustrates how one could set the CPs for a boost value of 18 (H,L,M) on channel 3 and a value of 14 (L,H,M) on channel 4. On Figure 8 please also note how pin 2 on JP5 is jumpered to ground in order to enable the CP control feature. FIGURE 8. ILLUSTRATION OF SETTINGS FOR CP3 = (H,L,M) AND CP4 = (L,H,M) For channels 1 and 2, the headers JP6-8 are used to set the CPs. High state is achieved by placing a jumper between the top two pins of the header and the middle state is achieved by placing a jumper between the bottom two pins. Low state is simply achieved by using no jumper at all. Figure 7 illustrates how one could set the CPs for a QLx4270 boost value of 21 (H,M,L) on channel 1 and a boost of 16 (H,L,L) on channel 2. 6 AN1516.0 January 18, 2010 Evaluation Board Schematic 7 Application Note 1516 AN1516.0 January 18, 2010 FIGURE 9. SCHEMATIC OF THE QLx4270 EVALUATION BOARD Application Note 1516 QLx4270 Bill of Materials Ref Des C-1,37,38 C-35,36 C-22 ~ 27 C-3,4,33,34,34a,39 C-40,41,42,43,44,46 C-5 ~ 20 C1A~C16A D-1 J-1 ~ 16 JP-1,2,4,5,6,7,9,11 JP-10, P-1 JP-3, JP-8, P-9 L-1,2,3,4 L-5,6 LED-1 P-8 Q1 R-1,6 R-10 R-11 ~ 15 R-18 R-29 R-3,4,5,23,24,25 R-30 ~ 41 R-42 R-7,8,9,20,26,27,28 R-19 U-1 U-2,3 U-4 U-5 VR-1 VR-2 Description Part No. (Digikey) Qty 25 Brd Qty Notes 10nF PCC103BQCT-ND 5 125 Do not install C-35 10nf/1uf doublestack PCC103BQCT-ND / PCC2268CT-ND 2 / 2 50 / 50 100pF PCC101CQCT-ND 6 150 10uF TANT CAP 478-1673-1-ND 6 150 220nF PCC2272CT-ND 6 150 DLI + 220nF double-stack P42BN820Z5S (DLI)/ PCC2272CT-ND 16 / 16 400 / 400 10nF PCC103BQCT-ND 16 400 SMD DIODE Install 0 ohm 0603, P0.0GCT-ND 1 25 Real P/N MAJ11600LCT-ND SMA FLUSH MNT A24691-ND 16 400 2x3 HDR WM26806-ND 6 150 Do not istall JP-9 and JP-11 2x4 HDR WM26808-ND 2 50 1x6 WM6506-ND 2 50 1206 SMD IND LQH31CN2R2M03L (Murata) 4 100 BEAD do not install 2 50 1206 LED 350-1566-1-ND 1 25 USB CONN H2959CT-ND 1 25 NPN XSISTOR 2SC248000LCT-ND 1 25 3.9K P3.9KJCT-ND 2 50 6K P6.04KLCT-ND 1 25 10K 311-10.0KLRCT-ND 5 125 100 311-100JRCT-ND 1 25 680 ohm P680JCT-ND 1 25 1.5K P1.5KJCT-ND 6 150 25K 541-25.5KLCT-ND 12 300 10K P10KJCT-ND 1 25 1K RHM1.00KLCT-ND 6 150 Do not install R-20 180 P180JCT-ND 1 25 EQ-4xxx Quellan Part - do not install 1 25 LM-1117 VOLT REG LM1117MP-ADJCT-ND 2 50 CY8C24894 MCU CY8C24894-24LFXI (Cypress) 1 25 65220 ESD 296-9694-1-ND 1 25 1K TRIM POT CT94EW102-ND 1 25 500 TRIM POT CT94EW501-ND 1 25 Do not install. Short two "outboard pads" 8 AN1516.0 January 18, 2010 Application Note 1516 About Q:ACTIVE® Intersil has long realized that to enable the complex server clusters of next generation datacenters, it is critical to manage the signal integrity issues of electrical interconnects. To address this, Intersil has developed its groundbreaking Q:ACTIVE® product line. By integrating its analog ICs inside cabling interconnects, Intersil is able to achieve unsurpassed improvements in reach, power consumption, latency, and cable gauge size as well as increased airflow in tomorrow’s datacenters. This new technology transforms passive cabling into intelligent “roadways” that yield lower operating expenses and capital expenditures for the expanding datacenter. Intersil Lane Extenders allow greater reach over existing cabling while reducing the need for thicker cables. This significantly reduces cable weight and clutter, increases airflow, and improves power consumption. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that the Application Note or Technical Brief is current before proceeding. For information regarding Intersil Corporation and its products, see www.intersil.com 9 AN1516.0 January 18, 2010