THS770006 www.ti.com SBOS520 – JULY 2010 Broadband, Fully-Differential, 14-/16-Bit ADC DRIVER AMPLIFIER Check for Samples: THS770006 FEATURES DESCRIPTION • • • • The THS770006 is a fixed-gain of +6dB, wideband, fully-differential amplifier designed and optimized specifically for driving 16-bit analog-to-digital converters (ADCs) at input frequencies up to 130MHz, and 14-bit ADCs at input frequencies up to 200MHz. This device provides high bandwidth, high-voltage output with low distortion and low noise, critical in high-speed data acquisition systems that require very high dynamic range, such as wireless base stations and test and measurement applications. This device also makes an excellent differential amplifier for general-purpose, high-speed differential signal chain and short line driver applications. 1 2.4GHz Bandwidth 3100V/µs Slew Rate, VOUT =2V step Fixed Voltage Gain: +6dB IMD3: –107dBc, VOUT = 2VPP, RL = 400Ω, f = 100MHz OIP3: 48dBm, f = 100MHz Noise Figure: 11dB, f = 100MHz 23 • • APPLICATIONS • • 14/16-bit ADC Driver ADC Driver for Wireless Base Station Signal Chains: GSM, WCDMA, MC-GSM ADC Driver for High Dynamic Range Test and Measurement Equipment • THS770006 Driving ADS5493 100W RO 50W VINVIN+ 50W 100W VOCM AIN+ 30MHz Bandpass Filter VOCM The THS7700 operates on a nominal +5V single supply, offers very fast, 7.5ns maximum recovery time from overdrive conditions, and has a power-down mode for power saving. The THS770006 is offered in a Pb-free (RoHS compliant) and green, QFN-24 thermally-enhanced package. It is characterized for operation over the industrial temperature range of –40°C to +85°C. ADS5493 AIN- RELATED DEVICES RO DEVICE THS770006 dBFS FFT Plot with Two-Tone Input at 96MHz and 100MHz (see Application Information section). 10 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 130 140 THS4509 PGA870 Wideband, low-noise, low-distortion, fully-differential, digitally-programmable gain amplifier ADS5481 to ADS5485 0 5 10 15 20 25 30 35 40 Frequency (MHz) 45 50 55 DESCRIPTION Wideband, low-noise, low-distortion, fully-differential amplifier 16-bit, 80MSPS to 200MSPS ADCs ADS5493 16-bit, 130MSPS ADC ADS6145 14-bit, 125MSPS ADC ADS6149 14-bit, 250MSPS ADC 61 1 2 3 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2010, Texas Instruments Incorporated THS770006 SBOS520 – JULY 2010 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. PACKAGE/ORDERING INFORMATION (1) PRODUCT PACKAGE TYPE PACKAGE DESIGNATOR SPECIFIED TEMPERATURE RANGE THS770006 VQFN-24 RGE –40°C to +85°C (1) PACKAGE MARKING ORDERING NUMBER TRANSPORT MEDIA, QUANTITY THS770006IGRE THS770006IRGET Tape and reel, 250 THS770006IGRE THS770006IRGER Tape and reel, 3000 For the most current package and ordering information see the Package Option Addendum at the end of this document, or visit the device product folder on www.ti.com. DEVICE MARKING INFORMATION = Pin 1 designator THS7700 06IRGE THS770006IRGE = device name TI = TI LETTERS YM = YEAR MONTH DATE CODE TI YMS LLLL S = ASSEMBLY SITE CODE LLLL = ASSY LOT CODE ABSOLUTE MAXIMUM RATINGS (1) Over operating free-air temperature range, unless otherwise noted. Power supply (VS+ to GND) THS770006 UNIT 5.5 V Input voltage range Ground to VS+ V Differential input voltage, VID Ground to VS+ V Continuous input current, II 10 mA Continuous output current, IO 100 mA –40°C to +125°C °C Maximum junction temperature, TJ +150 °C Maximum junction temperature, continuous operation, long term reliability +125 °C Human body model (HBM) 2500 V Charged device model (CDM) 1000 V Machine model (MM) 100 V Storage temperature range, Tstg ESD ratings (1) 2 Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): THS770006 THS770006 www.ti.com SBOS520 – JULY 2010 THERMAL INFORMATION THS770006 THERMAL METRIC (1) RGE UNITS 24 PINS qJA Junction-to-ambient thermal resistance qJC(top) Junction-to-case(top) thermal resistance qJB Junction-to-board thermal resistance 19 yJT Junction-to-top characterization parameter 0.5 yJB Junction-to-board characterization parameter 18.8 qJC(bottom) Junction-to-case(bottom) thermal resistance 8.9 (1) 44.1 35 °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. ELECTRICAL CHARACTERISTICS Test conditions are at TA = +25°C, VS+ = +5V, VOCM = +2.5V, VOUT = 2VPP, RL = 400Ω differential, G = +6dB, differential input and output, and input and output referenced to midsupply, unless otherwise noted. Measured using evaluation module as discussed in Test Circuits section. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT TEST LEVEL (1) AC PERFORMANCE Small-signal bandwidth VOUT = 200mVPP 2.4 GHz C VOUT = 2VPP 675 MHz C VOUT = 3VPP 485 MHz C VOUT = 2VPP 360 MHz C VOUT = 3VPP 325 MHz C VOUT = 2V step 3100 V/µs C VOUT = 4V step 3200 V/µs C Rise time VOUT = 2V step 0.6 ns C Fall time VOUT = 2V step 0.6 ns C Settling time to 0.1% VOUT = 2V step 2.2 ns C Input return loss, s11 See s-Parameters section, f < 200MHz –20 dB C Output return loss, s22 See s-Parameters section, f < 200MHz –20 dB C Reverse isolation, s12 See s-Parameters section, f < 200MHz –70 dB C f = 10MHz –87 dBc C f = 50MHz –81 dBc C f = 100MHz –78 dBc C f = 200MHz –74 dBc C f = 10MHz –103 dBc C f = 50MHz –91 dBc C f = 100MHz –86 dBc C f = 200MHz –77 dBc C f = 50MHz, 10MHz spacing –80 dBc C f = 100MHz, 10MHz spacing –79 dBc C f = 150MHz, 10MHz spacing –77 dBc C f = 200MHz, 10MHz spacing –76 dBc C f = 50MHz, 10MHz spacing –107 dBc C f = 100MHz, 10MHz spacing –107 dBc C f = 150MHz, 10MHz spacing –97 dBc C f = 200MHz, 10MHz spacing –82 dBc C RL = 20Ω 19.6 dBm C RL = 400Ω 8.7 dBm C Large-signal bandwidth Bandwidth for 0.1dB flatness Slew rate Second-order harmonic distortion Third-order harmonic distortion Second-order intermodulation distortion Third-order intermodulation distortion 1dB compression point (1) f = 100MHz Test levels: (A) 100% tested at +25°C. Over-temperature limits by characterization and simulation. (B) Limits set by characterization and simulation. (C) Typical value only for information. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): THS770006 3 THS770006 SBOS520 – JULY 2010 www.ti.com ELECTRICAL CHARACTERISTICS (continued) Test conditions are at TA = +25°C, VS+ = +5V, VOCM = +2.5V, VOUT = 2VPP, RL = 400Ω differential, G = +6dB, differential input and output, and input and output referenced to midsupply, unless otherwise noted. Measured using evaluation module as discussed in Test Circuits section. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT TEST LEVEL (1) Output third-order intercept point At device outputs, RL = 400Ω, f = 100MHz 48 dBm C Input-referred voltage noise f > 100kHz 1.7 nV/√Hz C Ouput-referred voltage noise f > 100kHz 3.4 nV/√Hz C 10.5 dB C f = 100 MHz 11 dB C f = 200 MHz 13 dB C f = 50 MHz Noise figure 100Ω differential source Overdrive recovery Overdrive = ±0.5V Output balance error f = 200MHz Output impedance f = 100MHz 5 7.5 ns B -60 dB C 4.4 Ω C DC PERFORMANCE Gain Output offset Common-mode rejection ratio TA = +25°C, RL = 400Ω 5.75 6 6.25 dB A TA = +25°C, RL = 100Ω 5.5 5.7 5.9 dB B TA = –40°C to +85°C, RL = 400Ω 5.7 6.3 dB B TA = –40°C to +85°C, RL = 100Ω 5.45 5.95 dB B TA = +25°C –10 10 mV A 12.5 mV B dB A dB B 115 Ω A 2.75 V A V A V B 1.4 V A 1.45 V B V A V B 1.5 V A 1.55 V B VPP B VPP B TA = –40°C to +85°C ±1 –12.5 TA = +25°C 36 TA = –40°C to +85°C 35 60 INPUT Differential input resistance Input common-mode range 85 Inputs shorted together, VOCM = 2.5V 100 2.25 OUTPUT Most positive output voltage Each output with 200Ω to midsupply TA = +25°C 3.64 TA = –40°C to +85°C 3.59 Least positive output voltage Each output with 200Ω to midsupply TA = +25°C Most positive output voltage Each output with 50Ω to midsupply TA = +25°C 3.59 TA = –40°C to +85°C 3.54 Least positive output voltage Each output with 50Ω to midsupply TA = +25°C Differential output voltage Differential output current drive 3.7 1.3 TA = –40°C to +85°C 3.6 1.3 TA = –40°C to +85°C TA = +25°C, RL = 400Ω 4.4 TA = –40°C to +85°C, RL = 400Ω 4.2 4.85 TA = +25°C, RL = 10Ω 80 mA B TA = –40°C to +85°C, RL =10Ω 80 mA B OUTPUT COMMON-MODE VOLTAGE CONTROL VOCM small-signal bandwidth VOUT_CM = 200mVPP 525 MHz C VOCM slew rate VOUT_CM = 500mVPP 180 V/µs C VOCM voltage range Supplied by external source (2) 2.25 2.5 2.75 V C VOCM gain VOCM = 2.5V 0.98 1 1.02 V/V A Output common-mode offset from VOCM input VOCM = 2.5V –30 12 30 mV A VOCM input bias current 2.25V ≤ VOCM ≤ 2.75V –400 ±30 400 µA A (2) 4 Limits set by best harmonic distortion with VOUT = 3VPP. VOCM voltage range can be extended if lower output swing is used or distortion degradation is allowed, and increased bias current into pin is acceptable. For more information, see Figure 12 and Figure 30. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): THS770006 THS770006 www.ti.com SBOS520 – JULY 2010 ELECTRICAL CHARACTERISTICS (continued) Test conditions are at TA = +25°C, VS+ = +5V, VOCM = +2.5V, VOUT = 2VPP, RL = 400Ω differential, G = +6dB, differential input and output, and input and output referenced to midsupply, unless otherwise noted. Measured using evaluation module as discussed in Test Circuits section. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT TEST LEVEL (1) POWER SUPPLY Specified operating voltage Quiescent current Power-supply rejection ratio 4.75 5 5.25 V C TA = +25°C 85 100 115 mA A TA = –40°C to +85°C 80 125 mA B TA = +25°C, VCC ±0.25V 60 dB A TA = –40°C to +85°C, VCC ±0.5V 59 dB B V A V A A 90 POWER-DOWN Enable voltage threshold Device powers on below 0.5V Disable voltage threshold Device powers down above 2.0V 0.5 2 Power-down quiescent current 0.8 3 mA Input bias current 80 100 µA A 10 µs C 0.15 µs C Turn-on time delay Time to VOUT = 90% of final value Turn-off time delay Time to VOUT = 10% of original value THERMAL CHARACTERISTICS Specified operating range –40 Thermal resistance, qJC (3) Junction to case (bottom) Thermal resistance, qJA (3) Junction to ambient (3) °C C 8.9 +85 °C/W C 44.1 °C/W C Tested using JEDEC High-K test PCB. Thermal management of the final printed circuit board (PCB) should keep the junction temperature below +125°C for long term reliability. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): THS770006 5 THS770006 SBOS520 – JULY 2010 www.ti.com PIN CONFIGURATION NC NC VS+ VS+ VS+ VS+ NC 24 23 22 21 20 19 RGE PACKAGE VQFN-24 (TOP VIEW) 1 18 NC 17 Unused 16 VOUT+ 15 VOUT- 100W PD 2 50W VIN- 3 VOCM 50W VIN+ 4 VOCM 5 14 Unused NC 6 13 NC 12 NC 10 GND 11 9 GND GND 8 GND NC 7 100W PIN DESCRIPTIONS PIN NO. NAME 1 NC No internal connection 2 PD Power down. High = low power (sleep) mode. Low = active. 3 VIN– Inverting input pin 4 VIN+ Noninverting input pin 5 VOCM Output common-mode voltage control input pin 6, 7 NC 8, 9, 10, 11 GND 12, 13 NC 14 No internal connection Ground. Must be connected to thermal pad. No internal connection Unused Bonded to die, but not used. Tie to GND. 15 VOUT– Inverting output pin 16 VOUT+ Noninverting output pin 17 Unused Bonded to die, but not used. Tie to GND. 18, 19 NC No internal connection 20, 21, 22, 23 VS+ Power supply pins, +5V nominal 24 NC No internal connection Thermal pad 6 DESCRIPTION Thermal pad on bottom of device is used for heat dissipation and must be tied to GND Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): THS770006 THS770006 www.ti.com SBOS520 – JULY 2010 TYPICAL CHARACTERISTICS TABLE OF GRAPHS TITLE FIGURE Frequency Response Magnitude (with Transformers) Figure 1 Frequency Response Magnitude (no Transformers) Figure 2 Frequency Response Phase (no Transformers) Figure 3 Small- and Large-Signal Pulse Response Figure 4 Slew Rate vs Output Voltage Step Figure 5 Overdrive Recovery Figure 6 Single-Ended Input Harmonic Distortion vs Frequency Figure 7 Harmonic Distortion vs Frequency, VOUT = 1VPP, 2VPP, 3VPP Figure 8 Harmonic Distortion vs Frequency, VOUT = 0.9VPP Figure 9 Harmonic Distortion vs VOUT Figure 10 Harmonic Distortion vs RL Figure 11 Harmonic Distortion vs VOCM Figure 12 Intermodulation Distortion vs Frequency, VOUT = 2VPP, 3VPP Envelope Figure 13 Intermodulation Distortion vs Frequency, VOUT = 0.9VPP Envelope Figure 14 Output Intercept Point vs Frequency Figure 15 Maximum Differential Output Voltage Swing Peak-to-Peak vs Differential Load Resistance Figure 16 Maximum/Minimum Single-Ended Output Voltage vs Differential Load Resistance Figure 17 Differential Output Impedance vs Frequency Figure 18 s-Parameters (Magnitude) Figure 19 Frequency Response vs Capacitive Load Figure 20 Recommended RO vs Capacitive Load Figure 21 Common-Mode Rejection Ratio vs Frequency Figure 22 Power-Supply Rejection Ratio vs Frequency Figure 23 VOCM Pulse Response Figure 24 Turn-On Time Figure 25 Turn-Off Time Figure 26 Input and Output Voltage Noise vs Frequency Figure 27 Output Balance Error vs Frequency Figure 28 VOCM Small-Signal Frequency Response Figure 29 VOCM Input Bias Current vs VOCM Input Voltage Figure 30 Noise Figure vs Frequency Figure 31 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): THS770006 7 THS770006 SBOS520 – JULY 2010 www.ti.com TYPICAL CHARACTERISTICS At TA = +25°C, VS+ = +5V, VOCM = +2.5V, VOUT = 2VPP, RL = 400Ω differential, G = +6dB, differential input and output, and input and output pins referenced to midsupply, unless otherwise noted. Measured using EVM as discussed in Test Circuits section. FREQUENCY RESPONSE MAGNITUDE (WITH TRANSFORMERS) 12 Measured on EVM using transformers. See Frequency Response: 200mVPP, 2VPP, 3VPP section. 6 Gain Magnitude (dB) 6 3 0 -3 VO = 200mVPP VO = 2VPP VO = 3VPP -6 -9 10M VOUT = 200mVPP 9 3 0 -3 VOUT = 2VPP Measured on EVM; no transformers. See Frequency Response: 200mVPP, 2VPP, 3VPP section. -6 -9 100M 1G Frequency (Hz) -12 100k 10G 1M 10M 100M Frequency (Hz) Figure 1. SMALL- AND LARGE-SIGNAL PULSE RESPONSE 45 3 2 0 Differential VOUT (V) Gain Phase (°) VOUT = 200mVPP -45 -90 VOUT = 2VPP Measured on EVM; no transformers. VOUT = 3VPP See Frequency Response: 200mVPP, 2VPP, 3VPP section. -180 100k 1M 10M 100M Frequency (Hz) 1 0 -1 -2 1G 0.5V Step Input 2.5V Step Input -3 10G 0 20 Figure 3. 40 60 TIme (ns) 100 120 OVERDRIVE RECOVERY 2.0 4000 VIN Differential VOUT 1.5 3000 VIN (V) Slew Rate (V/mS) 80 Figure 4. SLEW RATE vs OUTPUT VOLTAGE STEP 2000 0 1 2 3 4 5 4 3 1.0 2 0.5 1 0 0 -0.5 -1 -1.0 -2 -1.5 -3 -2.0 1000 -4 0 VOUT (VPP) Figure 5. 8 10G 1G Figure 2. FREQUENCY RESPONSE PHASE (NO TRANSFORMERS) -135 VOUT = 3VPP Differential VOUT (V) 9 Gain Magnitude (dB) FREQUENCY RESPONSE MAGNITUDE (NO TRANSFORMERS) 20 40 60 Time (ns) 80 100 Figure 6. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): THS770006 THS770006 www.ti.com SBOS520 – JULY 2010 TYPICAL CHARACTERISTICS (continued) At TA = +25°C, VS+ = +5V, VOCM = +2.5V, VOUT = 2VPP, RL = 400Ω differential, G = +6dB, differential input and output, and input and output pins referenced to midsupply, unless otherwise noted. Measured using EVM as discussed in Test Circuits section. SINGLE-ENDED INPUT HARMONIC DISTORTION vs FREQUENCY HARMONIC DISTORTION vs FREQUENCY VOUT = 1VPP, 2VPP, 3VPP -60 -60 -65 -70 HD2, VOUT = 2VPP -70 -75 HD2, VOUT = 1VPP Harmonic Distortion (dBc) -80 -85 -90 -95 -100 HD3, VOUT = 3VPP -105 HD3, VOUT = 2VPP -110 HD3, VOUT = 1VPP -115 10M 100M Frequency (Hz) Harmonic Distortion (dBc) HD2, VOUT = 3VPP RL = 400W -65 1G HD2, VOUT = 1VPP -75 -80 -85 -90 -95 -100 HD3, VOUT = 3VPP -105 HD3, VOUT = 2VPP -110 HD3, VOUT = 1VPP 100M Frequency (Hz) 1G Figure 7. Figure 8. HARMONIC DISTORTION vs FREQUENCY VOUT = 0.9VPP HARMONIC DISTORTION vs VOUT -65 Harmonic Distortion (dBc) RL = 400W VOUT = 0.9VPP -40 -50 -60 -70 HD2 -80 -90 HD3 f = 100MHz RL = 400W -70 -75 HD2 -80 HD3 -85 -90 -95 -100 -110 100M -100 1G 0 1 2 3 VOUT Differential (V) Frequency (Hz) 4 Figure 9. Figure 10. HARMONIC DISTORTION vs RL HARMONIC DISTORTION vs VOCM 5 -20 -65 f = 100MHz VOUT = 3VPP f = 100MHz RL = 400W -30 -70 Harmonic Distortion (dBc) Harmonic Distortion (dBc) RL = 400W HD2, VOUT = 2VPP -115 10M -30 Harmonic Distortion (dBc) HD2, VOUT = 3VPP -75 HD2 -80 HD3 -85 -40 HD2, VOUT = 3VPP -50 HD3, VOUT = 3VPP -60 -70 -80 -90 HD3, VOUT = 2VPP -100 HD2, VOUT = 2VPP -110 -90 0 200 400 600 800 1k 2 RL (W) Figure 11. 2.25 2.5 VOCM (V) 2.75 3 Figure 12. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): THS770006 9 THS770006 SBOS520 – JULY 2010 www.ti.com TYPICAL CHARACTERISTICS (continued) At TA = +25°C, VS+ = +5V, VOCM = +2.5V, VOUT = 2VPP, RL = 400Ω differential, G = +6dB, differential input and output, and input and output pins referenced to midsupply, unless otherwise noted. Measured using EVM as discussed in Test Circuits section. INTERMODULATION DISTORTION vs FREQUENCY, VOUT = 2VPP, 3VPP ENVELOPE -65 -75 -80 -85 -90 -95 -100 IMD3, VOUT = 3VPP Envelope IMD3, VOUT = 2VPP Envelope -105 -110 50M 75M 100M 125M 150M Frequency (Hz) 175M -50 -60 IMD2 -70 -80 IMD3 -90 -100 -110 100M 200M 1G Frequency (Hz) Figure 13. Figure 14. OUTPUT INTERCEPT POINT vs FREQUENCY MAXIMUM DIFFERENTIAL OUTPUT VOLTAGE SWING PEAK-TO-PEAK vs DIFFERENTIAL LOAD RESISTANCE 90 5.5 OIP2 80 Output Intercept Point (dBm) RL = 400W VOUT = 0.9VPP Envelope -40 Harmonic Distortion (dBc) Harmonic Distortion (dBc) -30 RL = 400W IMD2, VOUT = 3VPP Envelope IMD2, VOUT = 2VPP Envelope -70 INTERMODULATION DISTORTION vs FREQUENCY, VOUT = 0.9VPP ENVELOPE 5.0 70 Maximum Differential VOUT_PP Differential VOUT (V) 4.5 60 OIP3 50 40 30 20 4.0 3.5 3.0 2.5 2.0 RL = 400W VOUT = 3VPP Envelope 10 0 50M 1.5 1.0 100M 150M Frequency (Hz) 200M 10 100 Load Resistance (W) 1k Figure 15. Figure 16. MAXIMUM/MINIMUM SINGLE-ENDED OUTPUT VOLTAGE vs DIFFERENTIAL LOAD RESISTANCE DIFFERENTIAL OUTPUT IMPEDANCE vs FREQUENCY 4.0 1k Maximum Single-Ended VOUT Differential ZOUT (W) Single-Ended VOUT (V) 3.5 3.0 2.5 2.0 100 10 Minimum Single-Ended VOUT 1.5 1.0 1 10 100 Load Resistance (W) 1k 1M Figure 17. 10 10M 100M Frequency (Hz) 1G 10G Figure 18. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): THS770006 THS770006 www.ti.com SBOS520 – JULY 2010 TYPICAL CHARACTERISTICS (continued) At TA = +25°C, VS+ = +5V, VOCM = +2.5V, VOUT = 2VPP, RL = 400Ω differential, G = +6dB, differential input and output, and input and output pins referenced to midsupply, unless otherwise noted. Measured using EVM as discussed in Test Circuits section. s-PARAMETERS (MAGNITUDE) FREQUENCY RESPONSE vs CAPACITIVE LOAD 20 9 s22 Gain Magnitude (dB) 0 6 Gain (dB) -20 s11 -40 -60 3 0 s12 -3 -80 -100 1M 10M 100M Frequency (Hz) 1G -6 10M 10G CL = 10pF, RO = 35W CL = 24pF, RO = 18.7W CL = 44pF, RO = 13W CL = 94pF, RO = 8.2W CL = 660pF, RO = 0.7W 100M 1G Frequency (Hz) 10G Figure 19. Figure 20. RECOMMENDED RO vs CAPACITIVE LOAD COMMON-MODE REJECTION RATIO vs FREQUENCY 100 1k 90 80 70 RO (W) CMRR (dB) 100 10 60 50 40 30 20 10 0 1 1 10 100 Capacitive Load (pF) 1M 1k 10M 100M Frequency (Hz) Figure 21. Figure 22. POWER-SUPPLY REJECTION RATIO vs FREQUENCY VOCM PULSE RESPONSE 3.0 90 2.9 80 2.8 VOUT Common-Mode (V) 100 70 PSRR (dB) 1G 60 50 40 30 20 10 2.7 2.6 2.5 2.4 2.3 2.2 2.1 0 2.0 10k 100k 1M 10M Frequency (Hz) 100M 1G 0 Figure 23. 50 100 150 200 250 Time (ns) 300 350 400 Figure 24. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): THS770006 11 THS770006 SBOS520 – JULY 2010 www.ti.com TYPICAL CHARACTERISTICS (continued) At TA = +25°C, VS+ = +5V, VOCM = +2.5V, VOUT = 2VPP, RL = 400Ω differential, G = +6dB, differential input and output, and input and output pins referenced to midsupply, unless otherwise noted. Measured using EVM as discussed in Test Circuits section. TURN-ON TIME TURN-OFF TIME 4 Power-Down Input and VOUT (V) Power-Down Input and VOUT (V) 4 3 Power-Down 2 1 0 VOUT 0 4 8 12 16 20 24 Time (ms) 28 32 36 1 0 Power-Down 0 40 2 6 8 10 12 Time (ms) 14 16 Figure 26. INPUT AND OUTPUT VOLTAGE NOISE vs FREQUENCY OUTPUT BALANCE ERROR vs FREQUENCY 10 18 20 0 -10 Output Noise Input Noise -20 -30 -40 -50 -60 -70 -80 1 -90 10k 100k 1M Frequency (Hz) 10M 100M 1M 10M 100M Frequency (Hz) 1G Figure 27. Figure 28. VOCM SMALL-SIGNAL FREQUENCY RESPONSE VOCM INPUT BIAS CURRENT vs VOCM INPUT VOLTAGE 200 0 150 VOCM Input Bias Current (mA) 3 -3 -6 -9 -12 -15 -18 10G VO = 200mVPP 100 50 0 -50 -100 -150 -200 1M 10M 100M Frequency (Hz) 1G 2.1 Figure 29. 12 4 Figure 25. Output Balance Error (dB) Input and Output Voltage Noise (nVÖHz) VOUT 2 -1 -1 Gain (dB) 3 2.3 2.5 2.7 VOCM Input Voltage (V) 2.9 Figure 30. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): THS770006 THS770006 www.ti.com SBOS520 – JULY 2010 TYPICAL CHARACTERISTICS (continued) At TA = +25°C, VS+ = +5V, VOCM = +2.5V, VOUT = 2VPP, RL = 400Ω differential, G = +6dB, differential input and output, and input and output pins referenced to midsupply, unless otherwise noted. Measured using EVM as discussed in Test Circuits section. NOISE FIGURE vs FREQUENCY 20 18 100W Differential Source Noise Figure (dB) 16 14 12 10 8 6 4 2 0 10M 100M 200M Frequency (Hz) Figure 31. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): THS770006 13 THS770006 SBOS520 – JULY 2010 www.ti.com TEST CIRCUITS OVERVIEW The standard THS770006 evaluation module (EVM) is used for testing the typical performance shown in the Typical Characteristics, with changes as noted below. The EVM schematic is shown in Figure 32. The signal generators and analyzers used for most tests have single-ended 50Ω input and output impedance. The THS770006 EVM is configured to convert to and from a differential 50Ω impedance by using RF transformers or baluns (CX2156NL from Pulse, supplied as a standard configuration of the EVM). For line input termination, two 49.9Ω resistors (R5 and R6) are placed to ground on the input transformer output pins (terminals 1 and 3). In combination with the 100Ω input impedance of the device, the total impedance seen by the line is 50Ω. A resistor network is used on the amplifier output to present various loads (RL) and maintain line output termination to 50Ω. Depending on the test conditions, component values are changed as shown in Table 1, or as otherwise noted. As a result of the voltage divider on the output formed by the load component values, the amplifier output is attenuated. The Loss column in Table 1 shows the attenuation expected from the resistor divider. The output transformer causes slightly more loss, so these numbers are approximate. Table 1. Load Component Values (1) LOAD RL (1) 14 R15 AND R17 R16 LOSS 100Ω 25Ω Open 6dB 200Ω 86.6Ω 69.8Ω 16.8dB 400Ω 187Ω 57.6Ω 25.5dB 1kΩ 487Ω 52.3Ω 31.8dB The total load includes 50Ω termination by the test equipment. Components are chosen to achieve load and 50Ω line termination through a 1:1 transformer. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): THS770006 THS770006 www.ti.com SBOS520 – JULY 2010 Figure 32. THS770006IRGE EVM Schematic Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): THS770006 15 THS770006 SBOS520 – JULY 2010 www.ti.com TEST DESCRIPTIONS The following sections describe how the tests were performed, as well as the EVM circuit modifications that were made (if any). Modifications made for test purposes include changing capacitors to resistors, resistors to capacitors, the shorting/opening of components, etc., as noted. Unless otherwise noted, C1, C2, C9, and C13 are all changed to 0.1µF. Frequency Response: 200mVPP, 2VPP, 3Vpp This test is run with and without transformers in the signal path. For tests with transformers, the standard EVM is used and only the gain magnitude is shown. A network analyzer is connected to the input and output of the EVM with 50Ω coaxial cables and set to measure the forward transfer function (s21). The input signal frequency is swept with the signal level set for the desired output amplitude. The use of transformers gives better magnitude response that correlates best with detailed design simulation in terms of peaking in the response due to better control of parasitic capacitance at the device output pins, but also results in excess phase shift. So only magnitude is plotted. For tests without transformers, the standard EVM is used, with the gain magnitude and phase shown. A network analyzer is connected to the input of the EVM with 50Ω coaxial cable, the output is terminated with a 50Ω load, and a high impedance differential probe is used for the measurement. The analyzer is set to measure the forward transfer function (s21). The analyzer with a probe input is calibrated at the input pins of the device and signal is measured at the output pin, thus effectively removing the transformers from the transfer function. The input signal frequency is swept with signal level set for desired output amplitude. Not using transformers gives better phase response that correlates best with detailed design simulations, but as a result of extra parasitic capacitance at the device output pins gives significantly more peaking in the magnitude response. The –3dB points of the magnitude response measured without transformers correlates better with measured slew rate, so both magnitude and phase are plotted. s-Parameters: s11, s22, and s12 The standard EVM is used with both R15 and R17 = 24.9Ω, and R16 = open, to test the input return loss, output return loss, and reverse isolation. A network analyzer is connected to the input and output of the EVM with 50Ω coaxial cables and set to measure the appropriate transfer function: s11, s22, or s12. Note the transformers are included in the signal chain in order to retrieve proper measurements with single-ended test equipment. The impact is minimal from 10MHz to 200MHz, but further analysis is required to fully de-embed the respective effects. Frequency Response with Capacitive Load The standard EVM is used with R15 and R17 = RO, R16 = CLOAD, C9 and C13 = 953Ω, R21 = open, T2 removed, and jumpers placed across terminals 3 to 4 and 1 to 6. A network analyzer is connected to the input and output of the EVM with 50Ω coaxial cables and set to measure the forward transfer function (s21). Different values of load capacitance are placed on the output (at R16) and the output resistor values (R15 and R17) changed until an optimally flat frequency response is achieved with maximum bandwidth. Distortion The standard EVM is used for measurement of single-tone harmonic distortion and two-tone intermodulation distortion. For differential distortion measurements, the standard EVM is used with no modification. For single-ended input distortion measurements, the standard EVM is used with with T1 removed and jumpers placed across terminals 3 to 4 and 1 to 6, and R5 and R6 = 100Ω. A signal generator is connected to the J1 input of the EVM with 50Ω coaxial cables, with filters inserted inline to reduce distortion from the generator. The J3 output of the EVM is connected with 50Ω coaxial cables to a spectrum analyzer to measure the fundamental(s) and distortion products. Noise Figure The standard EVM is used with T1 changed to a 1:2 impedance ratio transformer (Mini-Circuits ADT2), R15 and R17 = 24.9Ω, and R5, R6, and R16 = open. A noise figure analyzer is connected to the input and output of the EVM with 50Ω coaxial cables. The noise figure analyzer provides a 50Ω (noise) source so that the data are adjusted to refer to a 100Ω source. 16 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): THS770006 THS770006 www.ti.com SBOS520 – JULY 2010 Transient Response, Slew Rate, Overdrive Recovery The standard EVM is used with T1 and T2 removed and jumpers placed across terminals 3 to 4 and 1 to 6; R15, R17, and R25 = 49.9Ω; C1, C2, C9, and C13 = 0Ω; and R5, R6, R16, and R21 = open. A differential waveform generator is connected to the input of the EVM with 50Ω coaxial cables at J1 and J2. The differential output at J3 and J4 is connected with 50Ω coaxial cables to an oscilloscope to measure the outputs. Waveform math in the oscilloscope is used to combine the differential output of the device. Power-Down The standard EVM is used with T1 and T2 removed, jumpers placed across terminals 3 to 4 and 1 to 6, R15 and R17 = 49.9Ω, C9 and C13 = 0Ω, and R5, R6, R16, and R21 = open. A waveform generator is connected to the power-down input of the EVM with a 50Ω coaxial cable at J8. The differential output at J3 and J4 is connected with 50Ω coaxial cables to an oscilloscope to measure the outputs. J1 is left disconnected so that the output is driven to the VOCM voltage when the device is active, and discharged through the resistive load on the output when disabled. Both outputs are the same and only one is shown. Differential Z-out The standard EVM is used with R15 and R17 = 24.9Ω, and R16 = open. A network analyzer is connected to the output of the EVM at J3 with 50Ω coaxial cable, both inputs are terminated with a 50Ω load, and a high-impedance differential probe is used for the measurement. The analyzer is set to measure the forward transfer function (s21). The analyzer with probe input is calibrated across the open resistor pads of R16 and the signal is measured at the output pins of the device. The output impedance is calculated using the known resistor values and the attenuation caused by R15 and R17. Output Balance Error The standard EVM is used with R15 and R17 = 100Ω, and R16 = 0Ω. A network analyzer is connected to the input of the EVM with 50Ω coaxial cable, the output is left open, and a high-impedance differential probe is used for the measurement. The analyzer is set to measure the forward transfer function (s21). The analyzer with probe input is calibrated at the input pins of the device and the signal is measured from the shorted pads of R16 to ground. Common-Mode Rejection The standard EVM is used with T1 removed and jumpers place across terminals 3 to 4, 1 to 6, and 1 to 3. A network analyzer is connected to the input and output of the EVM with 50Ω coaxial cable and set to measure the forward transfer function (s21). VOCM Frequency Response The standard EVM is used with T2 removed and jumpers across terminals 3 to 4 and 1 to 6; R10, R15, and R17 = 49.9Ω; C3 and C4 = 0Ω; and R9, R16, and R21 = open. A network analyzer is connected to the VOCM input of the EVM at J7 and output of the EVM with 50Ω coaxial cable, and set to measure the forward transfer function (s21). The input signal frequency is swept with the signal level set for 200mV. Each output at J3 and J4 is measured as single-ended, and because both are the same, only one output is shown. VOCM Slew Rate and Pulse Response The standard EVM is used with T2 removed and jumpers across terminals 3 to 4 and 1 to 6; R10, R15, and R17 = 49.9Ω; C9 and C13 = 0Ω; and C3, C4, R9, R16, and R21 = open. A waveform generator is connected to the VOCM input of the EVM at J7 with 50Ω coaxial cable. The differential output at J3 and J4 is connected with 50Ω coaxial cable to an oscilloscope to measure the outputs. J1 is left disconnected so that the output is driven to the VOCM voltage. Both outputs are the same, so only one is shown. Input/Output Voltage Noise, Settling Time, and Power-Supply Rejection These parameters are taken from simulation. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): THS770006 17 THS770006 SBOS520 – JULY 2010 www.ti.com THEORY OF OPERATION GENERAL DESCRIPTION The THS770006 is a fixed-gain of +6dB, wideband, fully-differential amplifier designed and optimized specifically for driving 14-bit and 16-bit ADCs at input frequencies up to 200MHz. This device provides high bandwidth, low distortion, and low noise, which are critical parameters in high-speed data acquisition systems that require very high dynamic range, such as wireless base stations and test and measurement applications. It also makes an excellent differential amplifier for general-purpose, high-speed differential signal chain and short line-driver applications. The device has an operating power-supply range of 4.75V to 5.5V. The THS770006 has proprietary circuitry to provide very fast recovery from overdrive conditions and has a power-down mode for power saving. The THS770006 is offered in a Pb-free (RoHS compliant) and green, QFN-24 thermally-enhanced package. It is characterized for operation over the industrial temperature range of –40°C to +85°C. The amplifier uses two negative-feedback loops. One is for the primary differential amplifier and the other controls the common-mode operation. Primary Differential Amplifier The primary amplifier of the THS770006 is a fully-differential op amp with on-chip gain setting resistors (RF = 100Ω and RG = 50Ω) that fix the differential gain at 2V/V, or 6dB, by use of negative feedback. VOCM Control Loop The output common-mode voltage is controlled through a second negative-feedback loop. The output common-mode voltage is internally sensed and compared to the VOCM pin. The loop then works to drive the difference, or error voltage, to zero in order to maintain the output common-mode voltage = VOCM (within the loop gain and bandwidth of the loop). For more details on fully-differential amplifier theory and use, see application report SLOA054, Fully-Differential Amplifiers, available for download from www.ti.com. OPERATION Differential to Differential The THS770006 is a fixed gain of 6dB, fully-differential amplifier that can be used to amplify differential input signals to differential output signals. A basic block diagram of the circuit is shown in Figure 33. The differential input to differential output configuration gives the best performance; the signal source and load should be balanced. 100W Differential Input Differential Output 50W VIN- VOUT+ VIN+ VOUT50W 100W THS770006 Figure 33. Differential Input to Differential Output Amplifier 18 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): THS770006 THS770006 www.ti.com SBOS520 – JULY 2010 Single-Ended to Differential The THS770006 can be used to amplify and convert single-ended input signals to differential output signals. A basic block diagram of the circuit is shown in Figure 34. The gain from the single-ended input to the differential output is 6dB. In order to maintain proper balance in the amplifier and avoid offsets at the output, the alternate input must be biased and the impedance matched to the signal input. For example, if a 50Ω source biased to 2.5V provides the input, the alternate input should be tied to 2.5V through 50Ω. If a 50Ω source is ac-coupled to the input, the alternate input should be ac-coupled to ground through 50Ω. Note that the ac coupling should provide a similar frequency response to balance the gain over frequency. VREF 100W Bias and Impedance Match Differential Output 50W VOUT+ Single-Ended Input VOUT50W 100W THS770006 Figure 34. Single-Ended Input to Differential Output Amplifier Setting the Output Common-Mode Voltage The VOCM input controls the output common-mode voltage. VOCM has no internal biasing network and must be driven by an external source or resistor divider network to the positive power supply. In ac-coupled applications, the VOCM input impedance and bias current are not critical, but in dc-coupled applications where more accuracy is desired, the input bias current of the pin should be considered. For best harmonic distortion with VOUT = 3VPP, the VOCM input should be maintained within the operating range of 2.25V to 2.75V. The VOCM input voltage can be operated outside this range if lower output swing is used or distortion degradation is allowed, and increased bias current into the pin is acceptable. For more information, see Figure 12 and Figure 30. It is recommended to use a 0.1µF decoupling capacitor from the VOCM pin to ground to prevent noise and other spurious signals from coupling into the common-mode loop of the amplifier. Input Common-Mode Voltage Range The THS770006 is designed primarily for ac-coupled operation. With input dc blocking, the input common-mode voltage of the device is driven to the same voltage as VOCM by the outputs. Therefore, as long as the VOCM input is maintained within the operating range of 2.25V to 2.75V, the input common-mode of the main amplifier is also maintained within its linear operating range of 2.25V to 2.75V. If the device is used with dc coupled input, the driving source needs to bias the input to its linear operating range of 2.25V to 2.75V for proper operation. Operation with Split Supply ±2.5V The THS770006 can be operated using a split ±2.5V supply. In this case, VS+ is connected to +2.5V, and GND (and any other pin noted to be connected to GND) is connected to -2.5V. As with any device, the THS770006 is impervious to what the user decides to name the levels in the system. In essence, it is simply a level shift of the power pins by –2.5V. If everything else is level-shifted by the same amount, the device sees no difference. With a ±2.5V power supply, the VOCM range is 0V ±0.25V; therefore, power-down levels are –2.5V = on and +2.5V = off, and input and output voltage ranges are symmetrical about 0V. This design has certain advantages in systems where signals are referenced to ground, and as noted in the following section, for driving ADCs with low input common-mode voltage requirements in dc-coupled applications. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): THS770006 19 THS770006 SBOS520 – JULY 2010 www.ti.com Driving Capcitive Loads The THS770006 is tested as described previously, with the data shown in the typical graphs. As a result of the fixed gain architecture of the device, the only practical means to avoid stability problems such as overshoot/ringing, gain peaking, and oscillation when driving capacitive loads is to place small resistors in series with the outputs (RO) to isolate the phase shift caused by the capacitive load from the feedback loop of the amplifier. The Typical Characteristics graphs show recommended values for an optimally flat frequency response with maximum bandwidth. Smaller values of RO can be used if more peaking is allowed, and larger values can be used to - reduce the bandwidth. Driving ADCs The THS770006 is designed and optimized for the highest performance to drive differential input ADCs. Figure 35 shows a generic block diagram of the THS770006 driving an ADC. The primary interface circuit between the amplifier and the ADC is usually a filter of some type for antialias purposes, and provides a means to bias the signal to the input common-mode voltage required by the ADC. Filters range from single-order real RC poles to higher-order LC filters, depending on the requirements of the application. Output resistors (RO) are shown on the amplifier outputs to isolate the amplifier from any capacitive loading presented by the filter. 100W 50W VOUT+ RO VIN- Filter and Bias VOCM VIN+ 50W VOCM 100W VOUT- RO AIN+ ADC AIN- CM THS770006 Figure 35. Generic ADC Driver Block Diagram The key points to consider for implementation are described in the following three subsections. SNR Considerations The signal-to-noise ratio (SNR) of the amplifier + filter + ADC adds in RMS fashion. Noise from the amplifier is bandwidth-limited by the filter. Depending on the amplitude of the signal and the bandwidth of the filter, the SNR of the amplifier + filter can be calculated. To get the combined SNR, this value is then squared, added to the square of the ADC SNR, and the square-root is taken. If the SNR of the amplifier + filter equals the SNR of the ADC, the combined SNR is 3dB higher and for minimal inpact on the ADC's SNR the SNR of the amplifier + filter should be 10dB or more lower. The combined SNR calculated in this manner is usually accurate to within ±1dB of actual implementation. SFDR Considerations Theoretically, the spurious-free dynamic range (SFDR) of the amplifier + filter + ADC adds linearly on a spur-by-spur basis. The amplifier output spurs are linearly related solely to the input signal and the SFDR is usually set by second-order or third-order harmonic distortion for single-tone inputs, and by second-order or third-order intermodulation distortion for two-tone inputs. Harmonic and second-order intermodulation distortion can be filtered to some degree by the antialias filter, but not third-order intermodulation distortion. Generally, the ADC also has the same distortion products, but as a result of the sampling nature and potential for clock feedthrough, there may be spurs not linearly related solely to the input signal. When the spurs from the amplifier + filter are known, each can be directly added to the same spur from the ADC. This is a worst-case analysis based on the assumption the spurs sources are in phase. If the spur of the amplifier + filter equals the spur of the ADC, the combined spur is 6dB higher. The combined spur calculated in this manner is usually accurate to within ±6dB of actual implementation, but higher variations have been observed especially in second-order performance as a result of phase shift in the filter. 20 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): THS770006 THS770006 www.ti.com SBOS520 – JULY 2010 Common-mode phase shift introduced by the filter nullifies the basic assumption that the spur sources are in phase. This phase shift can lead to better performance than predicted as the spurs become phase shifted, and there is the potential for cancellation as the phase shift reaches 180°. Differential phase shift in the filter as a result of mismatched components caused by nominal tolerance can severely degrade the second-order distortion of the ADC. Single-order RC filters cause very little differential phase shift with nominal tolerances of 5% or less, but higher-order LC filters are very sensitive to component mismatch. For instance, a third-order Butterworth bandpass filter with 100MHz center frequency and 20MHz bandwidth shows up to 20° differential phase imbalance in a Spice Monte Carlo analysis with 2% component tolerances. Therefore, while a prototype may work, production variance is unacceptable. A transformer or balun is recommended at the ADC input in these applications to restore the phase balance in the input signal to the ADC. ADC Input Common-Mode Voltage Considerations The input common-mode voltage range of the ADC must be observed for proper operation. In an ac-coupled application between the amplifier and the ADC, the input common-mode voltage bias of the ADC is accomplished in different ways depending on the ADC. Some use internal bias networks and others use external components, such as resistors, from each input to the CM output of the ADC. When ac coupling, the output common-mode voltage of the amplifier is a don’t care for the ADC, and VOCM should be set for optimum performance of the amplifier. DC-coupled applications vary in complexity and requirements, depending on the ADC. Devices such as the ADS5424 require a nominal 2.4V input common-mode, while others such as the ADS5485 require a nominal 3.1V input common-mode, and still others like the ADS6149 require 1.5V and the ADS4149 require 0.95V. Given the THS770006 output common-mode range, ADCs with input common-mode closer to 2.5V are easier to dc-couple to, and require little or no level shifting. For applications that require a different common-mode voltage between the amplifier and the ADC, a resistor network can be used, as shown in Figure 36. With ADCs that have internal resistors (RINT) that bias the ADC input to VCM, the bias resistors do not affect the desired value of RP, but do cause more attenuation of the differential input signal. Knowing the differential input resistance is required and sometimes, that is all that is provided. VREF VAMP+ RP RO VADC+ RINT Amp ADC VCM VAMP- RO RP VADC- RINT VREF Figure 36. Resistor Network to DC Level Shift Common-Mode Voltage For common-mode analysis, assume that VAMP± = VOCM and VADC± = VADC (the specification for the ADC input common-mode voltage). VREF is chosen to be a voltage within the system (such as the ADC or amplifier analog supply) or ground, depending on whether the voltage must be pulled up or down, and RO is chosen to be a reasonable value, such as 49.9Ω. With these known values, RP can be found by using Equation 1: 1 RP = 1 VAMP - VADC VCM - VADC + VADC - VREF RO RINT (1) The insertion of this resistor network also attenuates the amplifier output signal. The gain (or loss) can be calculated by Equation 2: GAIN = RP || RINT RO + (RP || RINT) (2) Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): THS770006 21 THS770006 SBOS520 – JULY 2010 www.ti.com Using the gain and knowing the full-scale input of the ADC, VADC the network can be calculated using Equation 3: VAMP PP = VADC FS ´ GAIN FS, the required amplitude to drive the ADC with (3) Using the ADC examples given previously, Table 2 shows sample calculations of the value of RP and VAMP FS for full-scale drive, and then for –1dB (often times, the ADC drive is backed off from full-scale in applications, so lower amplitudes may be acceptable). All voltages are in volts, resistors in Ω (the nearest standard value should be used), and gain as noted. Table 2 does not include the ADS5424 because no level shift is required with this device. Table 2. Example RP for Various ADCs ADC VOCM (VDC) VADC (VDC) VREF (VDC) RINT (Ω) RO (Ω) ADS5485 2.5 3.1 5 1k 50 ADS5493 2.5 3.15 5 1k 50 ADS6149 2.5 1.5 0 NA ADS4149 2.5 0.95 0 NA ADS4149 0 (1) 0.95 2.5 NA (1) VADC FS (VPP) VAMP PP FS (VPP) VAMP PP –1dBFS (VPP) –2.71 2 4.10 3.65 –2.93 2.5 3.50 3.12 0.60 –4.44 2 3.33 2.97 0.38 –8.40 2 5.26 4.69 0.62 –4.15 2 3.23 2.88 RP (Ω) GAIN (V/V) GAIN (dB) 158.3 0.73 142.3 0.71 50 75.0 50 30.6 50 81.6 THS770006 with ±2.5V supply. The calculated values for the ADS5485 give the lowest attenuation, and because of the high VFS, it requires 3.65VPP from the amplifier to drive to –1dBFS. Performance of the THS770006 is still very good up to 130MHz at this level, but the designer may want to further back off from full-scale for best performance and consider trading reduced SNR performance for better SFDR performance. The calculated values for the ADS5493 have lower attenuation as a result of reduced VFS, and requires 3.12VPP from the amplifier to drive to –1dBFS. Performance of the THS770006 is excellent at this level up to 130MHz. The values calculated for the ADS6149 show reasonable design targets and should work with good performance. Note the ADS6149 does not have buffered inputs, and the inputs have equivalent resistive impedance that varies with sampling frequency. In order to account for the increased loss, half of this resistance should be used for the value of RINT in Equation 2. The values calculated for the low input common-mode of the ADS4149 result in large attenuation of the amplifier signal leading to 5.26VPP being required for full-scale ADC drive. This amplitude is greater than the maximum capability of the device. With a single +5V supply, the THS770006 is not suitable to drive this ADC in dc-coupled applications unless the ADC input is backed off towards –6dBFS. Another option is to operate the THS770006 with a split ±2.5V supply, and is shown in the last row of Table 2. For this situation, if the +2.5V is used as the pull-up voltage, only 2.88VPP is required for the –1dBFS input to the ADS4149. See the Operation with Split Supply ±2.5V section for more detail. Note that the ADS4149 does not have buffered inputs and the inputs have equivalent resistive impedance that varies with sampling frequency. In order to account for the increased loss, half of this resistance should be used for the value of RINT in Equation 2. As with any design, testing is recommended to validate whether it meets the specific design goals. 22 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): THS770006 THS770006 www.ti.com SBOS520 – JULY 2010 APPLICATION INFORMATION THS770006 DRIVING ADS5493 To illustrate the performance of the THS770006 as an ADC driver, the device is tested with the ADS5493. The ADS5493 is a 16-bit, 130MSPS ADC with LVDS-compatible digital outputs on four data pairs. The device has an analog input buffer to isolate the internal switching of the sampling stage from the inputs. Designed for high SFDR, the ADC has low-noise performance and outstanding spurious-free dynamic range over a large input-frequency range. Key information points to consider when interfacing to an amplifier are: • Input buffer with constant load vs frequency • 3.15V analog input common mode • Full-scale differential input programmable from 1.5VPP to 2.5VPP • 2kΩ differential input impedance with internal common-mode bias • 4.6pF to 5.6pF for each analog input to ground (depending on PCB layout) • SNR = 75.2dBFS (typ) at fIN = 100MHz • SFDR = 100dBc (typ) at fIN = 100MHz • HD2 = 100dBc (typ) at fIN = 100MHz • HD3 = 100dBc (typ) at fIN = 100MHz The ADS5493 EVM is designed for flexible options to ease design work. Used in conjunction with the TSW1200EVM High Speed ADC LVDS Evaluation System, it reduces evaluation times to help the designer get from prototype to production more quickly. The ADS5493 EVM provides an input transformer for converting single-ended test signals to differential. The differential outputs are configurable to drive the ADC directly through passive components or to insert the THS770006 along with options for antialias filtering in the signal path to drive the ADC. The schematic of the antialias filter components is shown in Figure 37. Note: the circuit shown is from an early prototype of the ADS5493 EVM available at the time this data sheet was written and is provided as a reference only. The final released board may have changes. THS7700 Output ADS5493 Input Figure 37. ADS5493 EVM Antialias Filter Components Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): THS770006 23 THS770006 SBOS520 – JULY 2010 www.ti.com TESTING THE ADS5493 WITH AN AC-COUPLED BANDPASS FILTER For testing purposes, a 30MHz, third-order Butterworth bandpass filter with center frequency at 100MHz is designed and built on the EVM. The design target for the source impedance is 40Ω differential, and for load impedance is 400Ω differential. Therefore, approximately 1dB insertion loss is expected in the pass-band, requiring the amplifier output amplitude to be 2.5VPP to drive the ADC to –1dBFS. The output noise voltage specification for the THS770006 is 3.4 nV/√Hz. With 2.5VPP amplifier output voltage swing and 30MHz bandwidth, the expected SNR from the amplifier + antialias filter is 93.5dB. When added in combination with the ADS5493, the expected total SNR is 75.1dBFS for the typical case. Figure 38 shows the resulting FFT plot when driving the ADC to –1dBFS with a single-tone 100MHz sine wave, and sampling at 125MSPS. Test results show 98dBc SFDR from the second-order harmonic and 75.6 dBFS SNR; analysis of the plot is shown in Table 3 versus typical ADC specifications. The test results from circuit board to circuit board shows over 10dB of variation in the second order harmonic and a balun is inserted between the filter and ADC inputs to get repeatable performance. With balun, the minimum expected results should be better than 90dBc SFDR and 75dBFS SNR. Figure 38 shows the same circuit with a two-tone input at 96MHz and 100MHz. The near-in 3rd order intermodulation terms are about -100dBc. 0 -10 -20 dBFS -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 0 5 10 15 20 25 30 35 40 45 Frequency (MHz) 50 55 62.5 Figure 38. FFT Plot of THS770006 + 30MHz BPF + ADS5493 with Single-Tone at 100MHz Table 3. Analysis of FFT for THS770006 + BPF + ADS5493 at 100MHz vs Typical ADC Specifications ADC INPUT SNR HD2 HD3 –1dBFS 75.6dBFS –98dBc –107dBc ADS5493 Only (typ) –1dBFS 75.2dBFS –100dBc –100dBc dBFS CONFIGURATION THS770006 + BPF + ADS5493 10 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 130 140 0 5 10 15 20 25 30 35 40 Frequency (MHz) 45 50 55 61 Figure 39. FFT Plot of THS770006 + 30MHz BPF + ADS5493 with Two-Tone Input at 96MHz and 100MHz 24 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): THS770006 THS770006 www.ti.com SBOS520 – JULY 2010 TESTING THE ADS5493 WITH AN AC-COUPLED LOW-PASS FILTER For testing the ADS5493, a 150MHz, first-order, low-pass filter is built on the EVM with the following component changes: R10, R16, L3, and L24 = 100Ω, and C148 = 1.2pF. AC-coupling is done by inserting a 1µF capacitor for C133 and C136. This design gives approximately 1.6dB insertion loss at low frequency, requiring the amplifier signal be 2.7VPP in order to drive the ADC to -1dBFS. With 2.7VPP amplifier output voltage swing and 180MHz (–3dB) bandwidth, the expected SNR from the amplifier + antialias filter is 84.4dB. When added in combination with the ADS5493, the total expected SNR is 74.7dBFS for the typical case. Note the frequency response is approximately -1dB at 100MHz, which requires even higher amplitude for the following test. dBFS Figure 40 shows the resulting FFT plot when driving the ADC to –1dBFS with a 100MHz sine wave, and sampling at 125MSPS. Test results showed 91dBc SFDR from second- and third-order harmonic and 73.1dBFS SNR; analysis of the plot is shown in Table 4 versus typical ADC specifications. As a result of harmonic attenuation and phase shift between the amplifier and ADC, harmonic performance is better than predicted from the worst-case scenario described previously. Typical expected results should be approximately 90dBc SFDR and 73dBFS SNR. 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 0 5 10 15 20 25 30 35 40 45 Frequency (MHz) 50 55 62.5 Figure 40. FFT Plot of THS770006 + 180MHz LPF + ADS5493 with Single-Tone at 100MHz Table 4. Analysis of FFT for THS770006 + 180MHz LPF + ADS5493 at 100MHz vs Typical ADC Specifications CONFIGURATION ADC INPUT SNR HD2 HD3 THS770006 + BPF + ADS5493 –1dBFS 73.1dBFS –91dBc –91dBc ADS5493 Only (typ) –1dBFS 75.2dBFS –100dBc –100dBc Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): THS770006 25 THS770006 SBOS520 – JULY 2010 www.ti.com EVM AND LAYOUT RECOMMENDATIONS Figure 32 is the THS770006RGE EVM schematic, and Figure 41 through Figure 44 show the layout details of the EVM PCB. Table 5 is the bill of materials for the EVM as supplied from TI. It is recommended to follow the layout of the external components as close as possible to the amplifier, ground plane construction, and power routing. General layout guidelines are: 1. Place a 2.2µF to 10µF capacitor on each supply pin within 2 inches from the device. It can be shared among other op amps. 2. Place a 0.01µF to 0.1µF capacitor on each supply pin to ground as close as possible to the device. Placement within 1mm of the device supply pins ensures best performance. 3. Keep input and output traces as short as possible to minimize parasitic capacitance and inductance. Doing so reduces unwanted characteristics such as reduced bandwidth and peaking in the frequency response, overshoot, and ringing in the pulse response, and results in a more stable design. 4. To reduce parasitic capacitance, ground plane and power-supply planes should be removed from device input pins and output pins. 5. The VOCM pin must be biased to a voltage between 2.25V to 2.75V for proper operation. Place a 0.1µF to 0.22µF capacitor to ground as close as possible to the device to prevent noise coupling into the common-mode. 6. For best performance, drive circuits and loads should be balanced and biased to keep the input and output common-mode voltage between 2.25V to 2.75V. AC-coupling is a simple way to achieve this performance. 7. The THS770006 is provided in a thermally enhanced PowerPAD™ package. The package is constructed using a downset leadframe on which the die is mounted. This arrangement results in low thermal resistance to the thermal pad on the underside of the package. Excellent thermal performance can be achieved by following the guidelines in TI application reports SLMA002, PowerPAD™ Thermally-Enhanced Package and SLMA004, PowerPAD™ Made Easy. For proper operation, the thermal pad on the bottom of the device must be tied to the same voltage potential as the GND pin on the device. Figure 41. EVM Layout: Top Layer 26 Figure 42. EVM Layout: Bottom Layer Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): THS770006 THS770006 www.ti.com SBOS520 – JULY 2010 Figure 43. EVM Layout: Layer 2 Figure 44. EVM Layout: Layer 3 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): THS770006 27 THS770006 SBOS520 – JULY 2010 www.ti.com Table 5. THS770006RGE EVM Bill of Materials ITEM 28 DESCRIPTION SMD SIZE REFERENCE DESIGNATOR QTY MANUFACTURER PART NUMBER DISTRIBUTOR PART NUMBER 1 CAP, 10.0uF, CERAMIC, X7R, 10V 1206 C4, C5, C6 3 (TDK) C3216X7R1A106K (DIGI-KEY) 445-4043-1-ND 2 CAP, 0.1uF, CERAMIC, X7R, 16V 0603 C7, C8 2 (AVX) 0603YC104KAT2A (DIGI-KEY) 478-1239-1-ND 3 CAP, 0.01uF, CERAMIC, X7R, 16V 0402 C10, C11 2 (AVX) 0402YC103KAT2A (DIGI-KEY) 478-1114-1-ND 4 CAP, 100pF, CERAMIC, NPO, 50V 0402 C12 1 (AVX) 04025A101KAT2A (DIGI-KEY) 478-4979-1-ND 5 (AVX) 04025C102KAT2A (DIGI-KEY) 478-1101-1-ND 5 CAP, 1000pF, CERAMIC, X7R, 50V 0402 C1, C2, C3, C9, C13 6 OPEN 0402 R11, R12, R13, R14 4 7 RESISTOR, 0 OHM 0402 R4, R21 2 (PANASONIC) ERJ-2GE0R00X (DIGI-KEY) P0.0JCT-ND 8 RESISTOR, 49.9 OHM, 1/10W, 1% 0402 R5, R6 2 (PANASONIC) ERJ-2RKF49R9X (DIGI-KEY) P49.9LCT-ND 9 RESISTOR, 57.6 OHM, 1/10W, 1% 0402 R16 1 (PANASONIC) ERJ-2RKF57R6X (DIGI-KEY) P57.6LCT-ND 10 RESISTOR, 187 OHM, 1/10W, 1% 0402 R15, R17 2 (PANASONIC) ERJ-2RKF1870X (DIGI-KEY) P187LCT-ND 11 RESISTOR, 1K OHM, 1/10W, 1% 0402 R9, R10 2 (PANASONIC) ERJ-2RKF1001X (DIGI-KEY) P1.00KLCT-ND 12 RESISTOR, 10K OHM, 1/10W, 1% 0603 R25, R26 2 (PANASONIC) ERJ-3EKF1002V (DIGI-KEY) P10.0KHCT-ND 13 TRANSFORMER, BALUN T1, T2 2 (PULSE) CX2156NL (DIGI-KEY) 553-1499-ND 14 JACK, BANANA RECEPTANCE, 0.25" DIA. HOLE J5, J6 3 (SPC) 15459 (NEWARK) 79K5034 15 CONNECTOR, SMA PCB JACK (NEWARK) 34C8151 16 CONNECTOR, EDGE, SMA PCB JACK 17 HEADER, 0.1" CTRS, 0.025" SQ. PINS 18 SHUNTS 19 TEST POINT, RED 20 TEST POINT, BLACK 21 IC, THS770006 22 STANDOFF, 4-40 HEX, 0.625" LENGTH 4 (KEYSTONE) 1808 (DIGI-KEY) 1808K-ND 23 SCREW, PHILLIPS, 4-40, .250" 4 PMSSS 440 0025 PH (DIGI-KEY) H703-ND 24 BOARD, PRINTED CIRCUIT 3 POS. J7, J8 2 (AMPHENOL) 901-144-8RFX J1, J2, J3, J4 4 (JOHNSON) 142-0701-801 (NEWARK) 90F2624 JP1, JP2 2 (SULLINS) PBC36SAAN (DIGI-KEY) S1011E-36-ND JP1, JP2 2 (SULLINS) SSC02SYAN (DIGI-KEY) S9002-ND TP3 1 (KEYSTONE) 5000 (DIGI-KEY) 5000K-ND TP1, TP2 2 (KEYSTONE) 5001 (DIGI-KEY) 5001K-ND U1 1 (TI) THS770006RGE (TI) EDGE# 6515711 REV.A Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): THS770006 THS770006 www.ti.com SBOS520 – JULY 2010 Evaluation Board/Kit Important Notice Texas Instruments (TI) provides the enclosed product(s) under the following conditions: This evaluation board/kit is intended for use for ENGINEERING DEVELOPMENT, DEMONSTRATION, OR EVALUATION PURPOSES ONLY and is not considered by TI to be a finished end-product fit for general consumer use. Persons handling the product(s) must have electronics training and observe good engineering practice standards. As such, the goods being provided are not intended to be complete in terms of required design-, marketing-, and/or manufacturing-related protective considerations, including product safety and environmental measures typically found in end products that incorporate such semiconductor components or circuit boards. This evaluation board/kit does not fall within the scope of the European Union directives regarding electromagnetic compatibility, restricted substances (RoHS), recycling (WEEE), FCC, CE or UL, and therefore may not meet the technical requirements of these directives or other related directives. Should this evaluation board/kit not meet the specifications indicated in the User’s Guide, the board/kit may be returned within 30 days from the date of delivery for a full refund. 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TI assumes no liability for applications assistance, customer product design, software performance, or infringement of patents or services described herein. Please read the User’s Guide and, specifically, the Warnings and Restrictions notice in the User’s Guide prior to handling the product. This notice contains important safety information about temperatures and voltages. For additional information on TI’s environmental and/or safety programs, please contact the TI application engineer or visit www.ti.com/esh. No license is granted under any patent right or other intellectual property right of TI covering or relating to any machine, process, or combination in which such TI products or services might be or are used. FCC Warning This evaluation board/kit is intended for use for ENGINEERING DEVELOPMENT, DEMONSTRATION, OR EVALUATION PURPOSES ONLY and is not considered by TI to be a finished end-product fit for general consumer use. It generates, uses, and can radiate radio frequency energy and has not been tested for compliance with the limits of computing devices pursuant to part 15 of FCC rules, which are designed to provide reasonable protection against radio frequency interference. Operation of this equipment in other environments may cause interference with radio communications, in which case the user at his own expense will be required to take whatever measures may be required to correct this interference. EVM Warnings and Restrictions It is important to operate this EVM within the input voltage range of 0V to +5.5V and the output voltage range of 0V to +5.5V. Exceeding the specified input range may cause unexpected operation and/or irreversible damage to the EVM. If there are questions concerning the input range, please contact a TI field representative prior to connecting the input power. Applying loads outside of the specified output range may result in unintended operation and/or possible permanent damage to the EVM. Please consult the EVM User's Guide prior to connecting any load to the EVM output. If there is uncertainty as to the load specification, please contact a TI field representative. During normal operation, some circuit components may have case temperatures greater than +85°C. The EVM is designed to operate properly with certain components above +85°C as long as the input and output ranges are maintained. These components include but are not limited to linear regulators, switching transistors, pass transistors, and current sense resistors. These types of devices can be identified using the EVM schematic located in the EVM User's Guide. When placing measurement probes near these devices during operation, please be aware that these devices may be very warm to the touch. Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): THS770006 29 PACKAGE OPTION ADDENDUM www.ti.com 19-Aug-2010 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) Samples (Requires Login) THS770006IRGER ACTIVE VQFN RGE 24 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Request Free Samples THS770006IRGET ACTIVE VQFN RGE 24 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Purchase Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. 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Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 27-Aug-2010 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant THS770006IRGER VQFN RGE 24 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2 THS770006IRGET VQFN RGE 24 250 180.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 27-Aug-2010 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) THS770006IRGER VQFN RGE 24 3000 346.0 346.0 29.0 THS770006IRGET VQFN RGE 24 250 190.5 212.7 31.8 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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