TB457: Understanding Intersil Hot Plug Devices

Understanding Intersil Hot Plug Devices
®
Technical Brief
April 18, 2006
TB457.0
Authors: Eric Josefson and Sean Barr
Overview
Devices Under Observation
Hot Plug controllers have two primary responsibilities,
control inrush currents during turn-on and control load
currents to a safe pre-determined level in the event of a high
current fault/short during static operation.
• ISL6116 (+5V)
• ISL6116 (-12V)
• ISL6116 (-48V)
• ISL6115 (+12V)
• HIP1012A (+5V and +3.3V)
• ISL6173 (+3.3V and +2.5V)
• ISL6111(+12V, -12V, +3.3V, +5V)
• ISL6118 (+5V x2)
• Setting the Overcurrent Trip Point
CTIM DISCHARGED
RISET IS USED TO SET THE
DEVICE’S OVERCURRENT
THRESHOLD POINT*
IS VSENSE > VSET?
NO
YES
CURRENT THROUGH RISENSE
GENERATES A VOLTAGE TO BE
COMPARED TO THRESHOLD
POINT DEFINED BY RISET
CTIM CHARGED
HAS TIMEOUT
OCCURRED?**
NO
YES
FAULT CONDITION
*See respective controller datasheet for equations to select RISET
**Timeout is proportional to CTIM and varies by controller
(see datasheets)
OVERCURRENT TRIP POINT OPERATION
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
Technical Brief 457
ISL6116 (+5V)
Figures 1 and 2 show the ISL6116 in an ISL6115 high side
switch application eval board. Jumper JP1 is removed from
the original configuration so a +5V Power Source can be
applied to B2. +12V is needed to bias the IC and is applied
at B1. The overcurrent set point is 1.5A.
In Figure 3, notice the soft-start ramp up of GATE after
PWRON is initiated, thus allowing the gradual ramp up of
ILOAD. In Figure 4, starting up into a short is shown. Upon
PWRON being asserted, CTIM is immediately begins
charging. The nominal time-out period is CTIM x 93kΩ . An
overcurrent (OC) event occurs when the current through the
sense resistor exceeds the user programmed OC threshold
(see data sheet). The controller enters current regulation
(CR) and capacitor CTIM begins charging. The nominal
time-out period is CTIM x 93kΩ. (see Figure 5A). A transient
event from 500mA to 1A occurs. PGOOD is pulled low due
to a temporary undervoltage condition occurring on +5VOUT,
but CTIM stays low as a true OC event never occurs (See
Figure 5B).
ISL6116 (+5V) Figures
+
LOAD
B3
B4
+5V
R2
R1
1
8
2
ISL6116
7
3
U1
6
R3
R5
5
4
Q1
PWRON
PGOOD
D1
DD1
3.3V
C2
C1
B5
JP1
+5V
D2
R4
C3
+12V
VBIAS
V+ B2
B1
FIGURE 1. EVAL BOARD SCHEMATIC
ICR = 1.5A
FIGURE 2. EVAL BOARD PICTURE
ICR = 1.5A
Ch3 PGOOD
Ch2 PWRON
Ch2 CTIM
Ch4 ILOAD
Ch1 GATE
Ch1 GATE
Ch4 ILOAD
Ch3 PGOOD
FIGURE 3. TURN ON VIA PWRON INTO NOMINAL LOAD
2
FIGURE 4. TURN ON VIA PWRON INTO SHORT
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April 18, 2006
Technical Brief 457
ISL6116 (+5V) Figures (Continued)
ICR = 1.5A
Ch3PGOOD
Ch3 PGOOD
Ch1 +5VOUT
Ch4 IOUT
Ch1 GATE
Ch4 ILOAD
Ch2 CTIM
Ch2CTIM
FIGURE 5A. RESPONSE TO OC DURING OPERATION
FIGURE 5B. RESPONSE TO FALSE FAULT EVENT
FIGURE 5.
ISL6116 (-12V)
Figures 6 and 7 show the ISL6116 reconfigured for -12V low
side switch application. The following components were
removed: RG1, R6 & R11. C2 was added (0.047µf 0805
size). In Figure 8, notice that GATE is 0V to fully enhance the
FET because of -12V operation. Also note that PGOOD is
disabled due to low side configuration. Upon power up,
current regulation mode is entered and CTIM is immediately
begins charging. The nominal time-out period is CTIM x
93kΩ, and again PGOOD is disabled (see Figure 9). An OC
event occurs when the current through the sense resistor
exceeds the user programmed OC threshold (see data
sheet). The controller enters CR mode and capacitor CTIM
begins charging. The nominal time-out period is CTIM x
93kΩ (see Figure 10).
ISL6116 (-12V) Figures
HI J2
LOAD
-12V APPL.
J3 LO
R1
Q2
GND
J1
+VBUS
J4
-VBUS
C1
-12V*
R2
R7
REMOVE:
RG1, R6, R11
ADD C2
1
2
3
4
ISL6116
C3
U1
8
7
6
5
LOGIN
TP9
C2
R10
R8
D2
DD1
3.3V
R5
R9
OFF
0-5V
OT1
ON
FIGURE 6. ISL6116EVAL1 NEGATIVE VOLTAGE LOW SIDE
CONTROLLER
3
FIGURE 7. ISL6116 EVAL BOARD PICTURE
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April 18, 2006
Technical Brief 457
ISL6116 (-12V) Figures (Continued)
ICR = 2.4A
ICR = 2.4A
Ch4 ILOAD
Ch1 GATE
Ch4 ILOAD
Ch1 GATE
Ch2 CTIM
Ch3 PGOOD
Ch2 CTIM/Ch3 PGOOD
FIGURE 8. TURN ON INTO NOMINAL LOAD
FIGURE 9. TURN ON INTO OVERCURRENT
ICR = 2.4A
Ch4 ILOAD
Ch1 GATE
Ch2 CTIM
FIGURE 10. RESPONSE TO OC DURING OPERATION
4
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April 18, 2006
Technical Brief 457
ISL6116 (-48V)
Figure 11 and 12 show the ISL6116 in -48V Low Side Switch
Application. The eval board uses a HIP5600 to bias the
ISL6116 12V higher than the -48V. Note C2 was intentionally
left empty. Tests were done at -36V to keep the power
dissipated to the load low. Results would be essentially the
same at -48V.
In Figure 13, notice soft-start ramp up of GATE upon LOGIN
is being driven low. Keep in mind that PGOOD is disabled in
low side applications. Upon an OC at turn on, GATE begins
to soft-start, then attempts to regulate, then is shut down
(see Figure 14). Note CTIM’s behavior due to the eval board
setup (C2 DNP).
In Figure 15, the load is switched from an open to 2Ω. The
controller immediately pulls GATE down, CTIM up, and the
load is isolated. When LOGIN is forced high, the controller
shuts down (see Figure 16).
ISL6116 (-48V) Figures
HI J2
LOAD
J3 LO
R1
Q2
GND
J4
-VBUS
-48V
C1
J1
+VBUS
R2
R7
C2 = EMPTY
2
1
3
4
ISL6116
U1
C3
8
7
6
5
R
G
1
LOGIN
TP9
C2
R11
R10
R8
R6
D2
DD1
3.3V
R5
R9
OFF
0-5V
OT1
ON
FIGURE 11. ISL6116 EVAL BOARD SCHEMATIC
FIGURE 12. ISL6116 EVAL BOARD PICTURE
ICR = 2.4A
ICR = 2.4A
Ch2 GATE
Ch1 LOGIN
Ch1 LOGIN
Ch2 GATE
Ch4 ILOAD
Ch3 CTIM
Ch4 ILOAD
Ch3 CTIM
FIGURE 13. TURN ON VIA LOGIN
5
FIGURE 14. TURN ON INTO OC
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April 18, 2006
Technical Brief 457
ISL6116 (-48V) Figures (Continued)
ICR = 2.4A
ICR = 2.4A
Ch1 LOGIN
Ch2 GATE
Ch2 GATE
Ch3 CTIM
Ch4 ILOAD
Ch4 ILOAD
Ch3 CTIM
FIGURE 15. RESPONSE TO OC DURING OPERATION
ISL6115 (+12V)
Figures 17 and 18 show the ISL6115 in a +12V high side
switch application.
Refer to Figures 19 and 20. After PWRON is asserted,
notice the soft-start ramp of GATE to assure inrush current is
limited. Observe the PGOOD delay as well.
FIGURE 16. TURN OFF VIA LOGIN
Both Figures 21 and 22 show an OC event; Figure 21 shows
turning on into a short, and Figure 22 shows a short
occurring during normal operation. An OC event occurs
when the current through the sense resistor exceeds the
user programmed OC threshold (see data sheet). The
controller enters CR mode and capacitor CTIM begins
charging. The nominal time-out period is CTIM x 93kΩ.
ISL6115 (+12V) Figures
+
B3
LOAD
B4
-
R2
R1
Q1
1
8
2
7
ISL6115
3
6
4
5
R3
PWRON
R5
D1
DD1
3.3V
C2
D2
R4
C3
C1
B5
JP1
V+ B2
+12V
VBIAS
B1
FIGURE 17. ISL6115 EVAL BOARD SCHEMATIC
6
FIGURE 18. ISL6115 EVAL BOARD PICTURE
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April 18, 2006
Technical Brief 457
ISL6115 (+12V) Figures (Continued)
ICR = 1.5A
ICR = 1.5A
Ch3 PGOOD
Ch1 GATE
Ch2 PWRON
Ch4 ILOAD
FIGURE 20. TURN OFF VIA PWRON
FIGURE 19. TURN ON VIA PWRON INTO NOMINAL LOAD
ICR = 1.5A
ICR = 1.5A
Ch2 CTIM
Ch3 PGOOD
Ch1 GATE
Ch4 ILOAD
Ch4 ILOAD
Ch1 GATE
Ch3 PGOOD
Ch2 CTIM
FIGURE 21. TURN ON INTO OC
7
FIGURE 22. RESPONSE TO OC DURING OPERATION
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April 18, 2006
Technical Brief 457
HIP1012A (+5V and +3.3V)
Figures 29 and 30 both show the same event. Figure 29
shows 5VG and Figure 30 shows I3.3V. Controller is
shutdown by forcing PWRON2 high.
Figures 23 and 24 show the HIP1012A dual Hot Swap
controller. To configure for +3.3V and +5V, remove JP1, and
apply a function generator at pin2 of JP1 for (PWRON2)’.
Figures 31 and 32 show turning on into an OC condition.
Figure 31 shows 3/12VG and PWRON2, while Figure 32
shows I5V and PGOOD. An OC event occurs when the
current through the sense resistor exceeds the user
programmed OC threshold (see data sheet). The controller
enters CR mode and capacitor CTIM begins charging. The
nominal time-out period is CTIM x 200kΩ.
Figures 25 and 26 show the HIP1012A dual Hot Swap
controller load card.
TABLE 1. HOT SWAP CONTROLLER LOAD CARD
3.3V LOAD
5V LOAD
00 = Off
00 = Off
01 = 1.0Ω (3.3A)
01 = 10.1Ω (0.5A)
10 = 1.8Ω (1.8A)
10 = 7.0Ω (0.7A)
11 = 0.7Ω (4.7A)
11 = 4.2Ω (1.2A)
Both Figures 33 and 34 show an OC event. Figure 33 shows
a 700mA to 1.2A load step into OC range during normal
operation, while Figure 34 shows a short occurring during
normal operation. Notice that in the “short condition”, Figure
34, 5VG is pulled instantly to GND, then slowly ramped up.
Both Figures 27 and 28 show the same event. Figure 27
shows 5VG and Figure 28 shows I3.3V. After PWRON2 is
asserted (forced low), notice the soft-start ramp of 3/12VG to
assure inrush current is limited. Observe the PGOOD delay
as well.
An OC event occurs on the 5V line. Notice that the 3.3V line
continues operating normally until CTIM times out and the
device latches off (see Figure 35).
HIP1012A (+5V and +3.3V) Figures
CEC2
CEC1
R2
Q2
3 /12VIN
3 / 12VOUT
GND
R4
20mΩ
C4
20Ω
C1
0.01µF
JP2
GND
GND
GND
0.1µF
1
U1
JP1
1
2
C5
0.1µF
3/12ISEN
3/12VG
RILIM
3
VDD
JP4 4 MODE/
PWRON1
5
PWRON2
6
5VG
7
5VS
VDD
5VOUT
JP3
3/12VS
HIP1012A
5VIN
GND
CPUMP
CTIM
PGOOD
5VISEN
14
13
10kΩ
R5
12
11
10
9
8
C2
0.047µF
R101
R3
20Ω
LED1
C3
0.01µF
R1
Q1
100mΩ
Note: Test point number equals HIP1012A pin number.
FIGURE 23. HIP1012A EVAL BOARD SCHEMATIC
8
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April 18, 2006
Technical Brief 457
HIP1012A (+5V and +3.3V) Figures (Continued)
FIGURE 24. HIP1012A EVAL BOARD PICTURE
CEF
SW13
CEF 1,2,3
RL3
0.8Ω
R102
SW14
1.6Ω
LED2
RL4
CEF 4,5,6,
7,8,10
SW11
CEF 9,11,
12
RL1
7Ω
R103
SW12
RL2
10Ω
LED3
FIGURE 25. LOAD CIRCUIT SCHEMATIC
5VICR = 1A
Ch2 5VG
FIGURE 26. LOAD CIRCUIT EVAL BOARD PICTURE
5VICR = 1A
3.3VICR = 5A
3.3VICR = 5A
Ch2 5VG
Ch1 3/12VG
Ch4 PGOOD
Ch4 PGOOD
Ch2 I3.3V
Ch3 (PWRON2)’
FIGURE 27. TURN ON SHOWING BOTH CHANNELS
9
Ch3 (PWRON2)’
FIGURE 28. TURN ON SHOWING +3.3V DETAILS
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April 18, 2006
Technical Brief 457
HIP1012A (+5V and +3.3V) Figures (Continued)
5VICR = 1A
5VICR = 1A
3.3VICR = 5A
3.3VICR = 5A
Ch3 (PWRON2)’
Ch3 (PWRON2)’
Ch4 PGOOD
Ch4 PGOOD
Ch2 5VG
Ch2 I3.3V
Ch1 3/12VG
Ch1 3/12VG
FIGURE 29. TURN OFF VIA SHOWING BOTH CHANNELS
Ch1 3/12VG
5VICR = 1A
FIGURE 30. TURN OFF VIA SHOWING +3.3V DETAILS
5VICR = 1A
3.3VICR = 5A
3.3VICR = 5A
Ch2 5VG
Ch2 5VG
Ch4 (PWRON2)’
Ch1 I5V
Ch3 CTIM
Ch3 CTIM
Ch4 PGOOD
FIGURE 31. TURN ON INTO OC SHOWING BOTH CHANNELS
5VICR = 1A
5VICR = 1A
3.3VICR = 5A
3.3VICR = 5A
Ch2 5VG
Ch2 5VG
Ch1 I5V
Ch1 I5V
Ch3 CTIM
Ch3 CTIM
Ch4 PGOOD
Ch4 PGOOD
FIGURE 33. RESPONSE TO SHORT DURING OPERATION
10
FIGURE 32. TURN ON INTO OC SHOWING +5V DETAILS
FIGURE 34. RESPONSE TO OC DURING OPERATION1
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April 18, 2006
Technical Brief 457
HIP1012A (+5V and +3.3V) Figures (Continued)
Ch1 3V/12VG
5VICR = 1A
3.3VICR = 5A
Ch2 5VG
Ch4 PGOOD
Ch3 CTIM
FIGURE 35. RESPONSE TO OC SHOWING BOTH CHANNELS
HIP1012A (+5V and 12V)
The HIP1012A eval board can also be configured for +5V &
+12V Hot Swap control. To do this, jumpers JP3 and JP4
must be removed.
HIP1012A (+5V and 12V) Figures
CEC2
CEC1
R2
Q2
3 /12VIN
3 / 12VOUT
GND
R4
20mΩ
C4
20Ω
C1
0.01µF
JP2
GND
GND
GND
0.1µF
1
U1
JP1
1
2
0.1µF
3/12ISEN
3/12VG
RILIM
3
VDD
JP4 4 MODE/
PWRON1
5
PWRON2
6
5VG
7
5VS
VDD
C5
5VOUT
JP3
3/12VS
HIP1012A
5VIN
GND
CPUMP
CTIM
PGOOD
5VISEN
14
13
10kΩ
R5
12
11
10
9
8
C2
0.047µF
R101
R3
LED1
20Ω
C3
0.01µF
R1
Q1
100mΩ
Note: Test point number equals HIP1012A pin number.
FIGURE 36. SCHEMATIC FOR +5V AND +12V OPERATION
11
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April 18, 2006
Technical Brief 457
HIP1012A (+5V and 12V) Figures (Continued)
FIGURE 37. +5V AND +12V EVAL BOARD PICTURE
ISL6173 (+3.3V and +2.5V)
Figure 38 shows the ISL6173 dual low voltage Hot Swap
controller. This IC targets applications between +2.1V and
+3.6V for +Vin1, with a second channel controlling
applications from +0.7V to +Vin1. The ISL6173 is biased via
+Vin1. For the following measurements, channel 1 will
control +3.3V, and channel 2 +2.5V.
Both Figures 41 and 42 show the device turning on due to
the enable lines being asserted (forced low). Figure 41
shows each output in a soft-start ramp up after being
enabled, while Figure 42 shows more detail regarding only
channel 1 (+3.3V in this case) during soft-start.
Figures 43 and 44 show an OC condition occurring during
operation on channel 1 (+3.3V). The device enters CR
mode until CT1 times out, at which point the switch on
channel 1 latches off. In Figure 44, note that (PG1)’ is
triggered upon VO1 dipping, while (FLT1)’ stays high until
CT1 times out. The nominal time-out for this device is
(CTIM*1.178)/10µA.
Both Figures 45 and 46 show an OC condition occurring
during operation on channel 1 (+3.3V). Figure 45 shows the
gate signal and output voltage of channel 2 staying high
while channel 1 shuts down. Figure 46 shows the Power
Good and Fault signals for each channel, again note that
(PG1)’ and (FLT1)’ are tripped, while (PG2)’ and (FLT2)’
remain unaffected.
Figures 47 and 48 show an OC condition occurring during
operation on channel 1 (+3.3V). The device enters CR
mode but the load recovers before CT1 has a chance to time
out. Notice that (PG1)’ is triggered with the dip in VO1, then
recovers, while (FLT1)’ stays high due to CT1 never timing
out. The nominal time-out for this device is
(CTIM*1.178)/10µA.
In Figure 49, the ISL6173 is in reset mode, which means the
device will attempt to bring up channel 1 again after
discharging CT1 64 times. This process will repeat infinitely.
In the case of high di/dt shorts, a WOC condition exists (see
Figure 65). The controller will immediately pull GT to GND
before attempting to enter CR mode. Note that the load is
released before timeout occurs here.
Both channels are disabled by bringing their respective
enable lines high (see Figure 66).
12
TB457.0
April 18, 2006
1
2
3
M1
IRF7821
5
6
7
8
ISL6173 (+3.3V and +2.5V) Figures
J4
1
1
C12
0.15µF
R15
C6
0
1000pF
TP16
NO STUFF
R19
10K
R18
10K
D1
MBR130P
5V
D2
FLT1
LED55B/TO
D3
LED55B/TO
TP7
1
GND_OUT
J9
1
TP13
TP17 TP18
1
1
R11
14.7K
1
1
4
1
TP3
1
TP14
R31
1K
TP8
R32
1.1K
R16
10K
J2
CON2
R25
390
R26
390
5V
1
R12 R9
1K 2.55K
D4
PG2
LED55B/TO
D5
FLT2
LED55B/TO
1
2
7
20
SNS2 GT2 VO2
CT2 VS2
CON2
J3
TP15
J10
C17
47µF
VO2
1
1
R27
0.01
4
1
2
C10
FLT2 17
C9
19
SS2
0.033µF
UV2 23
GND
CT1
1
1
TP10
1
OCREF 25
29
GND1
PG2 16
R17
10K
VO1
R3
390
1K
0.033µF
PGND
C11
0.15µF
Vi_2
24
1
10
9
TP9
C18
220µF
ISL6173
R30
1
C13
0.47µF
27
TP4
PG1 6
FLT1 5
3
SS1
U1
11 CPQ-
1
CLOSE = Retry
13 CPQ+
2
R2
390
C21
10µF
R8
3.57K
18
GND_IN
J6
UV1
14 CPVDD
OPEN = Latch
R14
0
R53
100
Technical Brief 457
CLOSE = Enable
C14
2.2µF
5V
R10
1K
SNS1 GT1 VO1
VS1
21
1
OPEN = Disable
C22
0.022µF
EN1 EN2
8 RTR/LTCH
12 BIAS
22
1
SW3
TP12
C19
0.01µF
15
TP11
1
SW1 SW2
RS1
1K
R20
0
26
5V
J5
C3
0.1µF
1
13
C4
0.1µF
R29
1.1K C5
1000pF
C20
0.01µF NO STUFF
TP5
28
TP6
RS2
1K
C2
47µF
1
1
2
TP1
J1
CON2
Vi_2
J7
1
4
1
C1
220µF
5V
VO1
R1
0.01
3.3V
Vi_1
J8
TP2
Vi_1
2.5V
1
2
3
M2
IRF7821
5
6
7
8
R54
100
FIGURE 38. EVAL BOARD SCHEMATIC
D6
MBR130P
VO2
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April 18, 2006
VO1
TP27
TP28
1
1
R38
1
R37
1
R64
5
R42
1
R63
5
R40
5
R39
5
R41
5 TP29
TP30
TP31
1
1
M3
IRF7821
14
4
2
SW4
4
3
1
1
SW5
5
6
7
8
M4
IRF7821
R33
J11
R59
49.9
5
6
7
8
1
2
3
10
R55
1K
R34
TP26
4
1
1
2
3
10
TP25
1
R49
01
U2
R50
01
5V
NC1
NC8
IN2 OUTA
GND
V+
IN2_ OUTB
8
7
6
5
EL7202/SO
VO2
TP19
TP24
1
R44
1
SW6
1
1
M5
IRF7821
2
4
3
TP35
TP33
TP34
1
1
TP36
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April 18, 2006
1
R61
5
R47
5
R46
5
R48
5
TP23
5
6
7
8
1
M6
IRF7821
5
6
7
8
R35
J12
1
R62
5
SW7
R45
1 TP20
1
TP32
4
R43
1
1
R60
49.9
10
R57
1K
1
2
3
R36
4
10
TP21
R58
1K
1
TP22
1
R52
01
R51
01
U3
1
2
3
4
NC1
NC8
IN2 OUTA
GND
V+
IN2_ OUTB
EL7202/SO
FIGURE 39. EVAL BOARD SCHEMATIC (CONTINUED)
1
2
3
5V
8
7
6
5
Technical Brief 457
1
2
3
4
R56
1K
Technical Brief 457
ISL6173 (+3.3V & +2.5V) Figures
FIGURE 40. ISL6173 EVAL BOARD PICTURE
BOTH CHANNELS ICR = 2.2A
BOTH CHANNELS ICR = 2.2A
BOTH CHANNELS IWOC = 6.6A
BOTH CHANNELS IWOC = 6.6A
CH4 GT1
CH3 SS1
CH3 (EN1)’
CH1 VO1
CH4 (EN2)’
CH1 VO1
CH2 VO2
CH2 (PG1)’
FIGURE 41. TURN ON VIA (EN)’ SHOWING BOTH CHANNELS
15
FIGURE 42. TURN ON SHOWING CHANNEL 1 DETAILS
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April 18, 2006
Technical Brief 457
ISL6173 (+3.3V & +2.5V) Figures (Continued)
BOTH CHANNELS ICR = 2.2A
BOTH CHANNELS ICR = 2.2A
BOTH CHANNELS IWOC = 6.6A
BOTH CHANNELS IWOC = 6.6A
CH3 (FLT1)’
CH2 GT1
CH2 (PG1)’
CH4 ILOAD3.3V
CH1 VO1
CH4 ILOAD3.3V
CH1 VO1
CH3 CT1
FIGURE 43. RESPONSE TO OC IN LATCH MODE (CT)
FIGURE 44. RESPONSE TO OC IN LATCH MODE ((PG)’)
BOTH CHANNELS ICR = 2.2A
BOTH CHANNELS ICR = 2.2A
BOTH CHANNELS IWOC = 6.6A
BOTH CHANNELS IWOC = 6.6A
CH4 GT2
CH2 GT1
CH4 (PG2)’
CH3 VO2
CH2 (FTL1)’
CH1 (PG1)’
CH1 VO1
CH3 (PG2)’
FIGURE 45. OC CHANNEL COMPARISON (VO AND GT)
FIGURE 46. OC CHANNEL COMPARISON ((FLT)’ AND (PG)’)
BOTH CHANNELS ICR = 2.2A
BOTH CHANNELS ICR = 2.2A
BOTH CHANNELS IWOC = 6.6A
BOTH CHANNELS IWOC = 6.6A
CH3 (FTL1)’
CH2 GT1
CH2 (PG1)’
CH4 ILOAD3.3V
CH4 ILOAD3.3V
CH1 VO1
CH1 VO1
CH3 CT1
FIGURE 47. OC WITH RECOVERY BEFORE TIMEOUT (CT)
16
FIGURE 48. OC WITH RECOVERY BEFORE TIMEOUT ((PG)’)
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April 18, 2006
Technical Brief 457
ISL6173 (+3.3V & +2.5V) Figures (Continued)
BOTH CHANNELS ICR = 2.2A
BOTH CHANNELS ICR = 2.2A
BOTH CHANNELS IWOC = 6.6A
BOTH CHANNELS IWOC = 6.6A
CH2 GT1
CH2 GT1
CH4 ILOAD3.3V
CH1 VO1
CH1 VO1
CH3 CT1
CH3 CT1
CH4 ILOAD3.3V
FIGURE 50. RESPONSE TO WOC
FIGURE 49. OC IN RESET MODE
BOTH CHANNELS ICR = 2.2A
BOTH CHANNELS IWOC = 6.6A
CH4 (EN2)’
CH1 VO1
CH3 (EN1)’
CH2 VO2
FIGURE 51. TURN OFF VIA (EN)’
ISL6111 (+12V, -12V, +3.3V, +5V)
Figures 52 and 53 show the ISL6111 PCI Hot Plug power
switch controller. This IC provides power control for the four
legacy supplies (+12V, -12V, 3.3V, 5V) to a PCI or PCI-X
slot. The +12V and -12V switches are integrated, while the
higher power 3.3V and 5V lines require external N-channel
FETs.
Refer to Figures 54 and 55. Though on different time scales,
both figures show the same event; Figure 54 shows all four
output voltages ramping up, and Figure 55 gives detailed
information pertaining to a single rail (+3.3V) at startup.
There is a 1Ω resistive load on the +3.3V output.
17
Refer to Figures 56 and 57. Though on different time scales,
both figures show the same event; Figure 56 shows all four
output approaching GND, and Figure 57 gives detailed
information pertaining to a single rail (+3.3V) at shutdown by
EN. There is a 1Ω resistive load on the +3.3V output.
Both Figures 58 and 59 show the same event, each with a
different set of details. Note that PGOOD goes low as soon
as 3.3VS drops, but FLTLN waits until CR mode has expired.
The nominal time-out period for this device is CTIM x 150kΩ.
Turning on into a direct short, the +3.3V section of the
controller goes immediately into CR mode until CRTIM times
out. The nominal time-out period for this device is CTIM x
150kΩ (see Figure 46).
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April 18, 2006
Technical Brief 457
ISL6111 (+12V, -12V, +3.3V, +5V) Figures
FIGURE 52. EVAL BOARD SCHEMATIC
FIGURE 53. EVAL BOARD PICTURE
18
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April 18, 2006
Technical Brief 457
ISL6111 (+12V, -12V, +3.3V, +5V) Figures (Continued)
+5VICR = 1A
+3.3VICR = 5A
+12VICR = 650mA
CH2 +12VOUT
-12VICR = 140mA
CH4 +5VOUT
CH3 +3.3VOUT
CH3 3VG
CH4 ILOAD3.3V
+5VICR = 1A
CH2 EN
CH1 -12VOUT
+3.3VICR = 5A
+12VICR = 650mA
CH1 +3.3VOUT
-12VICR = 140mA
FIGURE 54. TURN ON SHOWING ALL OUTPUTS
CH2 +12VOUT
FIGURE 55. TURN ON SHOWING +3.3V DETAILS
+5VICR = 1A
+5VICR = 1A
+3.3VICR = 5A
+12VICR = 650mA
+3.3VICR = 5A
+12VICR = 650mA
-12VICR = 140mA
-12VICR = 140mA
CH4 +5VOUT
CH3 +3.3VOUT
CH3 3VG
CH4 ILOAD3.3V
CH2 EN
CH1 -12VOUT
CH1 +3.3VOUT
FIGURE 56. TURN OFF SHOWING ALL OUTPUTS
+5VICR = 1A
FIGURE 57. TURN OFF SHOWING +3.3V DETAILS
+5VICR = 1A
CH2 3VG
+3.3VICR = 5A
+12VICR = 650mA
+3.3VICR = 5A
+12VICR = 650mA
-12VICR = 140mA
-12VICR = 140mA
CH4 ILOAD3.3V
CH4 ILOAD3.3V
CH3 FTLN
CH3 PGOOD
CH1 3VS
CH1 +3.3VOUT
CH2 CRTIM
FIGURE 58. RESPONSE TO OC ON +3.3V CHANNEL
19
FIGURE 59. RESPONSE TO OC ON +3.3V CHANNEL
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April 18, 2006
Technical Brief 457
ISL6111 (+12V, -12V, +3.3V, +5V) Figures (Continued)
CH4 ILOAD3.3V
+5VICR = 1A
+3.3VICR = 5A
+12VICR = 650mA
-12VICR = 140mA
CH3 3VG
CH2 CRTIM
CH1 +3.3VOUT
FIGURE 60. TURN ON INTO SHORT ON +3.3V
ISL6118 (+5V x2)
notice that FAULT2 is only an indicator of an OC timeout,
thus is not an indicator of under voltage conditions.
Figures 61 and 62 show the ISL6118 dual power supply
controller. This IC provides fully independent OC fault
protection for the +2.5V to +5.5V environment, with
integrated MOSFETs. For ease of testing, EN1 and EN2
were tied together on this board.
Refer to Figures 63 and 64. After EN is asserted, notice the
soft-start ramp of both outputs to VIN, in this case +5V. Also
Figure 65 shows an OC condition occurring through
channel 2 of the IC. Note that channel 1 stays up regardless
of the condition of channel 2. Figure 66 shows turning on
into an OC condition on channel 2. Again, channel 1 is
unaffected.
ISL6118 (+5V x2) Figures
C2
R1
R6
D2
R8
D3
C1
C3
FAULT_OUT1 8
1
TP2
(VIN)
2
VIN
TP3
3
EN1
TP4
4 EN2 FAULT_OUT2 5
OUT1 7
ISL6118
R4
TP7
TP6
OUT2 6
R2
D4
R7
D1
R9
SW1
C4
R5
TP9
TP10
F1
R3
D5
FIGURE 61. EVAL BOARD SCHEMATIC
20
R10
FIGURE 62. EVAL BOARD PICTURE
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April 18, 2006
Technical Brief 457
ISL6118 (+5V x2) Figures (Continued)
BOTH CHANNELS ICR = 600mA
BOTH CHANNELS ICR = 600mA
CH1 OUT_1/CH2 OUT_2
CH3 EN_1&2
CH4 FAULT2
CH4 FAULT2
CH3 EN_1&2
CH1 OUT_1/CH2 OUT_2
FIGURE 63. TURN ON VIA EN
FIGURE 64. TURN OFF VIA EN
BOTH CHANNELS ICR = 600mA
BOTH CHANNELS ICR = 600mA
CH1 OUT_1/CH3 EN_1&2
CH3 EN_1&2
CH1 OUT_1
CH4 FAULT2
CH4 FAULT2
CH2 OUT_2
CH2 OUT_2
FIGURE 65. RESPONSE TO OC CONDITION
21
FIGURE 66. TURN ON INTO SHORT
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April 18, 2006
Technical Brief 457
Setting the Overcurrent Trip Point
In general, Intersil hot plug devices sense load current
through a sense resistor, then compare the voltage
generated across this sense resistor to a voltage
programmed via a “set” resistor
Steps to Set OC Trip Point: (Steps may vary slightly by
part)
NOMINAL CURRENT REGULATION LEVEL
(10%) FOR EACH SUPPLY
SUPPLY
(V ICR)
Setting Hot Plug Over Current Trip Points
+3.3
((100µA x RCRSET)/8.54)/RRSENSE
+5.0
((100µA x RCRSET)/12)/RRSENSE
+12
(100µA x RCRSET)/0.7
-12
(100µA x RCRSET)/3.3
ISL6173 (+3.3V and +2.5V)
1. Select desired OC trip point level
To set ISL6173 CR level, use the equation:
2. Determine RISET by selecting sense threshold voltage to
design to
( I SET • R SET )
I CR = --------------------------------------I SNS
3. Calculate RISENSE based on OC level selected in step 1
HIP1012A, ISL6115, ISL6116 Devices
To set HIP1012A, ISL6115, and ISL6116 CR levels, use the
equation:
V th
R ISENSE = ---------I OC
Where:
I REF
V OCREF
I SET = ------------- and I REF = -----------------------4
R OCREF
I REF = ( typically 80µA )
ISL6118
The ISL6118 current sense and limiting circuitry sets the
current limit to a nominal 600mA.
With:
HIP1012A
V th = R ISET • 10µA
700
NOMINAL OC VTH (mV)
10k
200
4.99k
100
2.5k
50
750
15
-40°C
650
IOUT (mA)
RISET RESISTOR (Ω)
600
25°C
550
Or
85°C
ISL6115, ISL6116
V th = R ISET • 20µA
500
1.25
RILIM RESISTOR (kΩ)
NOMINAL OC VTH (mV)
15
150
10
100
7.5
75
4.99
50
1.50
1.75
2.00 2.25
VOUT (V)
2.50
2.75
3.00
FIGURE 67. CURRENT REGULATION vs VOUT (VIN = 3.3V)
700
-40°C
For PCI Applications:
Set RCRSET to 4.22kΩ, which provides a nominal current trip
level 110%-130% higher than maximum specified PCI range
For Non-PCI Applications:
Do NOT use RCRSET > 15kΩ (thermal considerations)
IOUT (mA)
650
25°C
600
85°C
550
Do select RCRSET > 3.0kΩ to avoid noise faults
500
1.3 1.5
2.0
2.5
3.0
VOUT (V)
3.5
4.0
4.5 4.8
FIGURE 68. CURRENT REGULATION vs VOUT (VIN = 5V)
22
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April 18, 2006
Technical Brief 457
Summary of Overcurrent Response
HIP1012A - If programmed OC setpoint is exceeded, gate is
modulated to regulate current to current regulation level until
programmed timeout occurs. If timeout occurs, both gates
latch off. If the load current exceeds 300% of the
programmed OC setpoint, affected gate is immediately
pulled to ground, then modulated to regulate current to
current regulation level until timeout occurs.
ISL6141/51 - If programmed OC setpoint is exceeded, gate
is modulated to regulate current to current regulation level
until 500µs timeout occurs. If the overcurrent voltage
threshold is exceeded by more than 150mV, the affected
gate is immediately pulled to ground, then modulated to
regulate current to current regulation level until 500µs
timeout occurs. If timeout occurs, the gate latches off.
HIP1013 - If OC setpoint is exceeded, both gates will latch
off ~2µs after OC event
ISL6142/52 - If programmed OC setpoint is exceeded, gate
is modulated to regulate current to current regulation level
until programmed timeout occurs. If the overcurrent voltage
threshold is exceeded by more than 150mV, the affected
gate is immediately pulled to ground, then modulated to
regulate current to current regulation level until programmed
timeout occurs. If timeout occurs, the gate latches off.
HIP1011, A, B, D, E - If programmed OC setpoint is
exceeded, all outputs latch off.
ISL6115, ISL6116, ISL6117, ISL6120 - If programmed OC
setpoint is exceeded, gate is modulated to regulate current
to current regulation level until programmed timeout occurs.
If timeout occurs, the gate latches off. If the overcurrent
voltage threshold is exceeded by more than 150mV, the
affected gate is immediately pulled to ground, then
modulated to regulate current to current regulation level until
timeout occurs.
ISL6118, ISL619, ISL6121 - If OC setpoint is exceeded,
current is regulated then the gate latches off ~12ms after OC
event.
ISL6161 - If programmed OC setpoint is exceeded, gate is
modulated to regulate current to current regulation level until
programmed timeout occurs. If timeout occurs, both gates
latch off. If the load current exceeds 300% of the
programmed OC setpoint, affected gate is immediately
pulled to ground, then modulated to regulate current to
current regulation level until timeout occurs.
ISL6111 - If programmed OC setpoint is exceeded, gate is
modulated to regulate current to current regulation level until
programmed timeout occurs. If timeout occurs, all four
gates latch off.
HIP1020 - This device does not provide current monitoring.
ISL6140, ISL6150 - If programmed OC setpoint is exceeded
for more than 2µs, gate will latch off.
ISL6173 - Two levels of overcurrent detection are present,
CR mode and WOC (Way Overcurrent) mode. If load
current reaches OC setpoint, the gate is modulated to
regulate current to current regulation level until current drops
below CR or programmed timeout occurs. If timeout occurs,
output will either latch off or indefinitely retry depending on
condition of RTR/LTCH pin. WOC mode is reached upon a
very high di/dt spike of >300% CR. Gate is pulled to GND
immediately, then the device enters CR mode.
23
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April 18, 2006
Technical Brief 457
Hot Plug/Hot Swap Target Applications
HOT SWAP/HOT PLUG
BIAS
VOLTAGE
(V)
CONTROLLED
VOLTAGE(S)
(V)
HIP1011
+12
HIP1011A
INTERSIL
PART
NUMBER
TARGET APPLICATIONS
PCI
COMPACT
PCI
+12, -12, +5,
+3.3
Y
Y
+12
+12, -12, +5,
+3.3
Y
Y
HIP1011B
+12
+12, -12, +5,
+3.3
Y
Y
HIP1011D
+12
+12, -12, +3.3,
+5 x2
Y
HIP1011E
+12
+12, -12, +3.3,
+5 x2
Y
HIP1012A
+12
+12/+5 or
+5/+3.3
Y
HIP1013
+12
+12/+5 or
+5/+3.3
Y
HIP1020
+12 to +5
+12/+5/+3.3 or
+5/+3.3
Y
ISL6111
+12
+12, -12, +5,
+3.3
ISL6115
+12
+12
Y
ISL6116
+12 or -V
+5 or -V
Y
Y
Y
ISL6117
+12
+3.3
Y
Y
Y
ISL6118
+2.5 to +5.5
2.5 to 5.5
ISL6119
+2.5 to +5.5
2.5 to 5.5
ISL6120
+12
+2.5
ISL6121
+2.5 to +5.5
2.5 to 5.5
ISL6140/50
-10 to -80
-10 to -80
Y
Y
ISL6141/51
-20 to -80
-20 to -80
Y
Y
ISL6142/52
-20 to -80
-20 to -80
Y
Y
ISL6160
+12 and +5
+12/+5
ISL6161
+12
+12/+3.3
ISL6173
+2.1 to +3.6
+2.17 to +3.6,
+0.7 to VBIAS
24
Y
Y
STORAGE
SYSTEMS
-48V
TELECOM
USB
INFINIBAND
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
GENERAL
PURPOSE
Y
Y
TB457.0
April 18, 2006
Technical Brief 457
List of Figures
Page
ISL6116 (+5V) Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
EVAL BOARD SCHEMATIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
EVAL BOARD PICTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
TURN ON VIA PWRON INTO NOMINAL LOAD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
TURN ON VIA PWRON INTO SHORT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
RESPONSE TO OC DURING OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
RESPONSE TO FALSE FAULT EVENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
ISL6116 (-12V) Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
ISL6116EVAL1 NEGATIVE VOLTAGE LOW SIDE CONTROLLER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
ISL6116 EVAL BOARD PICTURE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
TURN ON INTO NOMINAL LOAD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
TURN ON INTO OVERCURRENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
RESPONSE TO OC DURING OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
ISL6116 (-48V) Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
ISL6116 EVAL BOARD SCHEMATIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
ISL6116 EVAL BOARD PICTURE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
TURN ON VIA LOGIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
TURN ON INTO OC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
RESPONSE TO OC DURING OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
TURN OFF VIA LOGIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
ISL6115 (+12V) Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
ISL6115 EVAL BOARD SCHEMATIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
ISL6115 EVAL BOARD PICTURE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
TURN ON VIA PWRON INTO NOMINAL LOAD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
TURN OFF VIA PWRON. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
TURN ON INTO OC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
RESPONSE TO OC DURING OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
HIP1012A (+5V and +3.3V) Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
HIP1012A EVAL BOARD SCHEMATIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
HIP1012A EVAL BOARD PICTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
LOAD CIRCUIT SCHEMATIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
LOAD CIRCUIT EVAL BOARD PICTURE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
TURN ON SHOWING BOTH CHANNELS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
TURN ON SHOWING +3.3V DETAILS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
TURN OFF VIA SHOWING BOTH CHANNELS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
TURN OFF VIA SHOWING +3.3V DETAILS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
TURN ON INTO OC SHOWING BOTH CHANNELS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
TURN ON INTO OC SHOWING +5V DETAILS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
RESPONSE TO SHORT DURING OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
RESPONSE TO OC DURING OPERATION1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
RESPONSE TO OC SHOWING BOTH CHANNELS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
HIP1012A (+5V and 12V) Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
SCHEMATIC FOR +5V AND +12V OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
+5V AND +12V EVAL BOARD PICTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
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Technical Brief 457
ISL6173 (+3.3V and +2.5V) Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
EVAL BOARD SCHEMATIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
EVAL BOARD SCHEMATIC (CONTINUED) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
ISL6173 EVAL BOARD PICTURE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
TURN ON VIA (EN)’ SHOWING BOTH CHANNELS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
TURN ON SHOWING CHANNEL 1 DETAILS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
RESPONSE TO OC IN LATCH MODE (CT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
RESPONSE TO OC IN LATCH MODE ((PG)’) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
OC CHANNEL COMPARISON (VO AND GT). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
OC CHANNEL COMPARISON ((FLT)’ AND (PG)’) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
OC WITH RECOVERY BEFORE TIMEOUT (CT). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
OC WITH RECOVERY BEFORE TIMEOUT ((PG)’) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
OC IN RESET MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
RESPONSE TO WOC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
TURN OFF VIA (EN)’ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
ISL6111 (+12V, -12V, +3.3V, +5V) Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
EVAL BOARD SCHEMATIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
EVAL BOARD PICTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
TURN ON SHOWING ALL OUTPUTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
TURN ON SHOWING +3.3V DETAILS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
TURN OFF SHOWING ALL OUTPUTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
TURN OFF SHOWING +3.3V DETAILS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
RESPONSE TO OC ON +3.3V CHANNEL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
RESPONSE TO OC ON +3.3V CHANNEL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
TURN ON INTO SHORT ON +3.3V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
ISL6118 (+5V x2) Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
EVAL BOARD SCHEMATIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
EVAL BOARD PICTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
TURN ON VIA EN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
TURN OFF VIA EN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
RESPONSE TO OC CONDITION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
TURN ON INTO SHORT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
ISL6118 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
CURRENT REGULATION vs VOUT (VIN = 3.3V). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
CURRENT REGULATION vs VOUT (VIN = 5V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to
verify that the Application Note or Technical Brief is current before proceeding.
For information regarding Intersil Corporation and its products, see www.intersil.com
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