Powering Crusoe™ CPU with ISL6211 TM Application Note November 2001 AN9989 Author: Vladimir A. Muratov Introduction performance modes, Figure 2. The output voltage changes are synchronized with corresponding on-board load transitions. The Crusoe™ family of x86 compatible processors combines strong performance with remarkably low power consumption. The new technology for designing microprocessors underlies the achievement. The new technology is fundamentally software based: the power savings come from replacing large numbers of transistors with software. The CPU emulator can be disabled by S1 (see Figure 1 and Table 3). In this case, the output voltage is set by the Performance 1 VID combination. The conveniently provided scope probe sockets allow for monitoring of the output voltage and the switching waveforms. The Crusoe processor solutions consist of a hardware engine logically surrounded by a software layer. The engine is a very long instruction word (VLIW) CPU capable of executing up to four operations in each clock cycle. The software layer is called Code Morphing™ software because it dynamically “morphs” x86 instructions into VLIW instructions. The surrounding software layer gives x86 programs the impression that they are running on x86 hardware. The Code Morphing™ software is a major, but not the only one contributor to power reduction. LongRun™ power management is another facility that further minimizes the processor's power. The LongRun™ software continuously monitors the demand on the processor and dynamically sets the right clock speed and core voltage needed to run the application. The PLL power supply is also placed on the evaluation board for testing and evaluation of the core voltage tracking circuit that powers clock PLL, Figure 3. Quick Start Evaluation Out Of The Box The ISL6211EVAL comes in a “ready-to-test” state. The board comes equipped with several jumpers pre-populated for operation with the load emulator on. Use Table 1 for jumper description. Table 3 describes the S1 function. NOTE: pre-populated positions are highlighted in bold. Required Test Equipment To fully test the ISL6211 chip functionality characterized by this Application Note, the follow equipment is needed: • 4 channel oscilloscope with probes All these advances in microprocessor architecture require adequate performance from the VRM. • 1 electronic load The ISL6211 CPU core PWM controller fits especially well into the requirements specified by the Crusoe™ family processors operating in conjunction with LongRun™ technology. The controller can operate a synchronous buck converter on selectable 300kHz/600kHz frequency. The VID codes can be dynamically changed with a controlled slew rate that dramatically simplifies support of different generations of CPUs. The output voltage can be programmed in two ways, either by the VID code, or by using the analog reference input. The last feature significantly reduces the number of external components required to support START and DSX CPU modes. • 2 bench power supplies (0-5V, 0-24V @ > 2.5A) • Precision digital multi-meters TABLE 1. JUMPER FUNCTIONALITY JUMPER # STATE JP1 JP2 JP3 For more information on ISL6211 features see the data sheet FN9043 [1]. Evaluation Board Overview The ISL6211EVAL board presents itself as a flexible tool to evaluate performance of the CPU core regulator without involving a real CPU, Figure 1. The built-in CPU load emulator performs dynamic output voltage changes that simulate transitions between START, DSX, and two 1 JP4 FUNCTION POP Normal Operation NOP Measure operating current IVCC POP Enable hysteretic operation in DSX mode only NOP Enables hysteretic mode control by SW2 POP Engages external circuit for maximum voltage limiting NOP Disconnects the circuit POP Connects CPU leakage simulating resistors to the output NOP Disconnects leakage resistors for efficiency measurements Crusoe™, Code Morphing™ and LongRun™ are trademarks of Transmeta Corp. CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2001. All Rights Reserved 1 5V PGOOD J9 DSX START 1 VDSX=10uA*R9 VSTART=10uA*R8 VCC J4 1 2 1 1 R22 680R 1 1 1 1 2 R6 R4 C9 1.0 10V 2 2 R16 10k 1 R1 10R Q6 BSS123LT1 R9 75k0 10k 2 10k 2 PGOOD Q7 BSS123LT1 GREEN 1 CR1 LXA3025IGC-TR R23 680R 5V 1 1 Q5 BSS123LT1 R8 105k 1 2 R15 10k RED 1 1 1 2 2 JUMPER 1 JP1 1 J10 12 11 10 9 8 ISL6211 VID0 VID1 VID2 VID3 VID4 FREQ ALTV FCCM# EN PGOOD VCC GND 2 R18 10k 2 R20 200 2 1 GND 1 JP2 JUMPER 1 1 J11 2 8 7 6 5 1 2 3 4 KAL2104ER S1 1 TP3 SOFT 13 14 15 16 17 18 19 20 21 22 23 24 5V 2 1 2 C14 0.22 16V R2 0R 300kHz/600kHz FCCM ENABLE LOAD EMULATOR ON/OFF SOFT VIN SOFT OCSET VSEN VRTN BOOT UGATE PHASE ISEN PGND LGATE PVCC 1 1 + 2 1 R14 100k R5 3k57 2 C3 1 68u 16V 2 C4 1.0 10V 1 2 R3 0R BAT54WT1 2 D1 4 Q1 NOP Q3 uPA1707 4 4 Q2 uPA1707 2 2 2 R21 7k5 R19 24k3 Q4 NOP 2 1 2 R17 1 + C1 56u 25V _ 2k00 C13 1n 50V R7 5R1 + 2 220u 1 2.5V C5 3 TP2 Probe Socket 3 2 1 R10 LMV331 IN- + OUT 5V 4 5 2k00 80R6 270u 2.5V C11 2 10uF 1 6.3V C6 VCC R11 GND IN+ U2 + 220u 2.5V C10 L1 1uH Panasonic ETQP6F1R0SFA TP1 Probe Socket PHASE LM4041-ADJ + FB U3 2 2 1 1 C8 0.15 16V C2 1.0uF 25V 1 VLIM=1.24[(R21/R19)+1]=1.6V 1 1 4 FIGURE 1. ISL6211 EVALUATION BOARD. DC_DC CONVERTER ENABLE R61 200 5S 1 DSX HYS@DSX ONLY VID0 VID1 VID2 VID3 VID4 7 6 5 4 3 2 1 U1 1 2 1 3 1 1 J2 1 1 GND 3 2 3 2 2 2 1 2 3 1 2 2 1 4 1 3 2 2 2 3 1 2 5 6 7 8 5 6 7 8 1 2 3 5 6 7 8 1 2 3 5 6 7 8 1 2 3 2 2 1 2 2 1 1 2 + 1 1 1 1 J5 J6 J3 J1 JP3 2 JUMPER 1 VOUT LIM 220u 2.5V C12 10uF 6.3V C7 1 1 SOFT J7 J8 GND GND V_CORE V_CORE VCORE GND Vin Application Note 9989 20 19 18 17 16 15 14 13 12 11 C37 1.0 10V 1 C36 1.0 10V 1 2 1 2 C38 1.0 10V C33 1.0 10V 2 1 R39 0.1R 2 1 R40 0.1R 2 2 1 4 Q10 Si4410DY 1 R41 NOP MODE 2 10R R49 R42 NOP 2 1 C B A Ax Ay Aout Bout Vdd Vss Vee INH Cx Cout Cy Bx By R44 0.2R 2 10R Q8 Si4410DY R47 4 1 R43 0.1R 2 C B A Ax Ay Aout Bout Vdd U10 CD4053BCM Vss Vee INH Cx Cout Cy Bx By U7 CD4053BCM MODE 1 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 9 10 11 12 13 14 15 16 2 1 C35 1.0 10V 5S 5V 9 10 11 12 13 14 15 16 5 6 7 8 NC IN B GND IN A 4 3 2 1 5 6 7 8 1 IN B GND IN A NC 1K R36 ICL7667SM OUT B VCC OUT A NC U13 2 1nF 50V C21 4 3 2 1 + 2 1 2 R32 10k C16 68u 16V 1 2 1 2 1 4 3 2 1 C34 2nF 50V C30 1nF 50V 4 3 2 1 C17 33nF 50V 2 R62 1K 2400us CV THR DIS VCC CV THR DIS VCC 1 11 R48 1K Q11 BSS123LT1 2 100us_1 R Q TR GND U8 ICM7555CBA R Q TR GND U4 ICM7555CBA R29 332K 2 2 1 C24 10nF 50V R33 9K09 1 2 1 Q9 BSS123LT1 C23 1 10nF 50V 2 C18 10nF 50V R30 110K 1 5 6 7 8 2 1 5 6 7 8 R50 1K FIGURE 2. ISL6211 EVALUATION BOARD. CPU EMULATOR ICL7667SM OUT B VCC OUT A NC U12 0- Mode 1 1- Mode 2 MODE CONTROL VID0 VID1 VID2 VID3 VID4 1 2 5V 1 2 2 C32 1.0 10V 1 2 1 R46 6.8R 2 2 2 1 1 R45 6.8R 1 JP4 LEAKAGE C31 1.0 10V 1 2 VCORE MODE 2 1 2 3 4 5 6 7 8 9 10 MODE 1 SW1 KAL2110ER 8 7 6 5 3 2 1 8 7 6 5 3 2 1 10K 10K 10K 10K 10K 1 1 1 1 1 3 3 2 3 3 2 IN B GND IN A NC U5 BAT54WT1 2 D2 4 3 2 1 DSX 5 6 7 8 BAT54WT1 2 D3 OUT B VCC OUT A NC ICL7667SM 1 4 3 2 1 2 50% DC CV THR DIS VCC 4 3 1 10nF 50V R37 10k 5 6 7 8 2 2 CV Q R START TP5 200us DIS THR TR VCC GND 2 1 5 6 7 8 C25 1 10nF 50V 1 1 5 6 7 2 2 2 8 C19 1 10nF 50V 1 U11 ICM7555CBA 100us_2 R Q TR GND U9 ICM7555CBA 2 START CV THR DIS VCC MODE CONTROL R Q TR GND U6 ICM7555CBA 1 C27 R34 10k R31 25K5 BAT54WT1 2 D4 1 TP4 DSX 1nF 50V C22 2 1 2 4 3 2 1 1 2 2 1 2 1 1 3 1 2 2 1 3 R24 R25 R26 R27 R28 2 C28 1 10nF 50V 1 2 C26 10nF 50V R35 9K09 C20 33nF 50V C29 10nF 50V R38 20k Application Note 9989 1 2 Application Note 9989 5V Vref=1.2349*(R56+R57)/R56 Vref=2.0V R53 2 R51 2k00 VCORE 1k U15 2 C40 3 1 R56 2 40k2 1 1 J13 + _ 3 6 7 LM4041-ADJ C41 1n 50V U14 5 FB Q13 BSS123LT1 1 CPU_EN R54 0R D5 NOP 2 R55 40k2 0.01 50V C39 NOP 50V 1 8 + GND - + OUT - VCC OUT 4 D6 MMBD4148 2 R52 0R 1 3 2 1 Q12 2N2222 R57 J12 LM358 V_PLL_CPU 2 24k9 R60 2 2 NOP R59 40k2 C42 1 R58 1k C43 1 0.01 50V NOP 50V FIGURE 3. ISL6211 EVALUATION BOARD PLL POWER SUPPLY TABLE 2. BILL OF MATERIALS REFERENCE DESCRIPTION CR1 LED C1 Capacitor 56µF C2 C3, C16 VENDOR PART NO. QTY LXA3025IGC-TR 1 Sanyo OSCON 25SP56M 1 Capacitor 10µF Tayo Yuden TMK432BJ106KM 1 Capacitor 68µF Kemet T494D686(1)016AS 1 C4, C9, C31, C32, C33, C35, C36, Capacitor 1.0µF C37, C38 Kemet C1206C105K8RAC 9 C5, C6, C7, C10, C11, C12 Capacitor 220µF Sanyo POSCAP 2R5TPB220M 6 C8, C14 Capacitor 0.22µF Kemet C0805C224K4RAC 2 C13, C21, C22, C27, C30, C39, C41 Capacitor 1.0nF Kemet C0805C102K5RAC 7 C17, C20 Capacitor 33nF Kemet C0805C333K4RAC 2 C18, C19, C23, C24, C25, C26, C28, C29, C40, C42, C43 Capacitor 0.01µF Kemet C0805C103K4RAC 11 C34 Capacitor 2.0nF Kemet C0805C202K5RAC 1 D1, D2, D3, D4 Shottky Diode Motorola BAT54WT1 4 L1 Inductor 1.8uH Sumida CEP1231R8MH 1 Q1, Q2 NMOS Transistor NEC uPA1707 1 Q3, Q4 NMOS Transistor NEC uPA1707 1 Q5, Q6, Q7, Q9, Q11,Q13 NMOS Transistor Motorola BSS123LT1 6 Q8, Q10 NMOS Transistor Fairchild HUF76131SK8 2 Q12 NPN Transistor Motorola MMBT2222A 1 R1, R47, R49 Resistor 10Ω, 5% - 0805 3 R2, R3 Jumper 0Ω - 0805 2 - 0805 14 R4, R6, R15, R16, R18,R24, R25, Resistor 10.0kΩ, 1% R26, R27, R28, R32, R34, R37, R62 4 Rev. 1 Application Note 9989 TABLE 2. BILL OF MATERIALS REFERENCE DESCRIPTION VENDOR PART NO. QTY R5 Resistor 3.57kΩ, 1% - 0805 4 R7 Resistor 5.1Ω, 10% - 0805 1 R8 Resistor 105kΩ, 1% - 0805 1 R9 Resistor 75kΩ, 1% - 0805 1 R10 Resistor 80.6Ω, 1% - 0805 1 R11, R17, R51 Resistor 2.00kΩ, 1% - 0805 3 R14, R60 Resistor 100kΩ, 1% - 0805 2 R19 Resistor 7k50kΩ, 1% - 0805 1 R20 Resistor 200Ω, 5% - 0805 1 R21 Resistor 24.3kΩ, 1% - 0805 1 R22, R23 Resistor 680Ω, 5% - 0805 2 R29 Resistor 332kΩ, 1% - 0805 1 R30 Resistor 110kΩ, 1% - 0805 1 R31, R56 Resistor 25.5kΩ, 1% - 0805 2 R33, R35 Resistor 9.09kΩ, 1% - 0805 2 R38 Resistor 20kΩ, 1% - 0805 1 R39, R42 Resistor 0.2Ω, 10% Vishay WSL2512 2 R40, R41, R43, R44 Resistor 0.1Ω, 10% Vishay WSL2512 4 R45, R46 Resistor 6.8Ω, 10% Panasonic P6.8WCT-ND 2 R55, R57, R59 Resistor 40.2kΩ, 1% - 0805 3 R61 Resistor 23.2kΩ, 1% - 0805 1 S1 Switch E-Switch KAL2104ER 1 SW1 Switch E-Switch KAL2110ER 1 TP1, TP2 Probe Socket - U1 Power Controller IC Intersil Corp. ISL6211 1 U2 Comparator National LMV331 1 U3, U15 Reference National LM4041DEM3-ADJ 2 U4, U6, U8, U9, U11 Timer Intersil Corp. ICM7555CBA 5 U5, U12, U13 Driver Intersil Corp. ICL7667SM 3 U7, U10 Multiplexer TI CD4053BCM 2 U14 Amplifier National LM358 2 5 2 Application Note 9989 Schematic Description The evaluation board electrical schematic is presented in the Figures 1-3. The bill of materials is detailed in Table 2. The DC-DC converter schematic is presented in Figure 1. The board layout is shown in Figures 9-14. The electrical components that comprise the evaluation board are arranged in several blocks that are outlined on the silk screen. TABLE 3. S1 FUNCTIONALITY SWITCH POSITION FROM THE LEFT 300kHz/600kHz FCCM# Enable Load Emulator On/Off STATE (UP - CLOSED) (DOWN - OPEN) Two scope receptacles, TP1 and TP2, provide easy and convenient connection to observe PHASE and VOUT waveforms. Power Connections FUNCTION Down 300kHz Up 600kHz Down FCCM activated Up Hysteretic Operation Enabled Down ISL6211 Disabled Up ISL6211 Enabled Down The Emulator is OFF Up The Emulator is ON The components that are directly related to the DC-DC converter are positioned in a square shaped envelope in the center-right part of the board. Those components include the PWM controller U1 ISL6211, MOSFETs Q2 and Q3, the filter inductor L1, and the output capacitors C10, C11, C12, and C5. Feedback and bias components are also located in this envelope. The components, like dip-switches, signaling LEDs, jumpers, etc. that provide service functions and are not usually present in real applications, are positioned outside the converter envelope. The PLL power supply components U15, U16, Q6, Q12, etc. are assembled in the separate block outlined on the silk screen and marked CPU PLL. The load emulator components SW1, U4-U13, Q8, Q10, etc. are grouped in the L-shaped rectangular block located in the upper left portion of the board that is marked LOAD EMULATOR. To provide maximum flexibility the evaluation board schematic has multiple positions for the most critical components like MOSFETs and output capacitors. The board can accommodate two MOSFETs for the upper switch and two MOSFETS for the lower switch. One pair of MOSFETs is positioned on the component side of the board. A second pair of MOSFETs can be placed on the bottom side of the board. Optional positions allow evaluation of different MOSFET combinations in the study of efficiency. 6 The output voltage is set by the dip-switch SW1 (Figure 1) by directly dialing appropriate VID codes. For START and DSX modes, the voltage is set by resistors R8 and R9, accordingly. In the simplest configuration only one 5V DC source is required to begin evaluation. The board can accommodate up to six surface mount, D-size electrolytic capacitors. With the all supplies turned OFF, connect the 0-24V power supply positive terminal to the VIN post (J1) and the negative terminal to the nearest GND post (J3). Then connect the 0-5V power supply positive terminal to the VCC post (J4) and the negative terminal to the nearest GND post (J2). In the minimal configuration only one 0-5V supply can be used. In this case, connect the VIN post to the VCC post with a jump wire. NOTE: Do not forget to remove this wire when proceeding to tests with voltages higher than 5V! Not removing the wire can permanently destroy the IC if high voltage is applied to the VCC pin. Connect the electronic load positive terminal to the V_CORE posts (J5, J6) and the negative terminal to GND posts (J7, J8). In the minimal configuration the internal LOAD EMULATOR can be used. Put the ‘Load On/Off’ switch of the S1 switch assembly in the upper position and close the JP4 jumper to activate the emulator. Performance Characterization This section shows captured performance data from a standard bench setup. It will include descriptions of the experiments performed and the conditions applied. Switching Frequency The ISL6211 PWM controller can operate on either 300kHz, or 600kHz switching frequency. The frequency can be changed by switching the S1 switch. The lower position sets the lower switching frequency, and the higher position sets the higher frequency. If not otherwise stated, the measurements in this application note are made with the 300kHz switching frequency. Soft-Start In a start up event, the IC is ramping-up the output voltage smoothly to the programmed level by following voltage on the SOFT pin. During voltage ramp-up, the under-voltage and PGOOD signals are disabled until the output has risen to within 75% of its target. Only then are the protections enabled and PGOOD is released to be reported. Application Note 9989 Figure 4 shows the output voltage response to the application of supply voltages and the EN signal. The scope is set to trigger in a single-shot mode on EN going high. VOUT 1 CCM PHASE EN 2 2 HYSTERETIC VOUT 1 PHASE SOFT 2 1 VOUT 3 CH1 20.0MV CH3 PGOOD CH2 10.0V CH4 M 1.00µs 4 FIGURE 6. SWITCHING AND RIPPLE WAVEFORMS Vin = 10.0V CH1 500MV CH3 CH2 5.0V CH4 5.0V M 5.00ms Adaptive Voltage Positioning FIGURE 4. INITIAL START UP Steady-State Operation Depending on the load level and the control signals applied, ISL6211 can operate either in continuous conduction (CCM), or discontinuous hysteretic mode. The CCM mode is usually associated with higher currents. Output and the phase node waveforms for both modes of operation are presented in Figures 5 and 6. To reduce the size of the output filter, an adaptive voltage positioning is used in the CPU power applications. The technique is based on lowering the output voltage as the load increases. VCPU VID CODE PROGRAMMED VOLTAGE 1.3V VDROOP LOAD LINE CCM VOUT 1 PHASE 2 0 IMAX ICPU VOUT HYSTERETIC FIGURE 7. OUTPUT VOLTAGE DROOP 1 PHASE 2 CH1 20.0mV CH3 CH2 5.00V CH4 M 1.00µs The output voltage varies with the load as if a resistor were connected in series with the converter’s output, as it is shown in Figure 7. When done as a part of the feedback in a closed loop, the output voltage droop is not associated with substantial power losses, because the feature is emulated by the feedback. FIGURE 5. SWITCHING AND RIPPLE WAVEFORMS Vin = 5.0V To observe the waveforms shown in Figures 5 and 6, place the scope probes into the receptacles TP1 and TP2. Enable the hysteretic mode of operation by putting the FCCM switch (S1) in the high position. Synchronize the scope to the channel connected to the TP1 (PHASE) test point. The output voltage variation for the TM5800 CPU is specified as +5%/-2% of the set voltage. The recommended use of the allowed regulation window is presented in Figure 8. The maximum allowed ripple is assumed to be no more than 2% of the nominal output voltage determined by the VID code, or potential on the ALTV pin. The 1% safe margins on both sides of the regulation window provide required guard toward components tolerance. With assumed ripple and margins, the initial voltage rise and droop value are about 3%. 7 Application Note 9989 +6% CPU Emulator MIN LOAD CURRENT (0A) MAX LOAD CURRENT (5A) UPPER LIMIT 1% +4% +2% VDROOP ~3% VRIPPLE < 2% VCPUnom To simplify the task of core regulator supply evaluation, the board is equipped with a CPU emulator. The emulator applies control signals and VID codes to the converter in a repeatable manner actively changing its operating modes. The output voltage and the load current is shown in Figure 10. The electrical schematic of the converter is presented in Figure 2. The square wave generator U4 generates the DSX signal that is applied to the gate of Q2. When the DSX signal is high it commands the converter into DSX mode. The output voltage is programmed by the resistor R9 and the VID code is disregarded. When the DSX signal is low, operation using VID codes is enabled. Just after the DSX turns from high to low, the START signal is generated by single-shot U11. 1% -2% LOWER LIMIT -4% FIGURE 8. ADAPTIVE VOLTAGE POSITIONING Transient Response The converter response to the load step of 5A is shown in Figure 9. At zero load current, the output voltage is raised ~40mV above nominal value of 1.30V. When the load current increases to its maximum value, the output voltage drops down. Due to the use of droop, the converter’s output voltage adaptively changes with the load current allowing better utilization of the regulation window. DSX 2400µs T = 7600µs ENABLED LOAD CONTROL MODE MODE MODE 2 1 2 MODE CONTROL 600µs 600µs IO TRANSITION CONTROL IL 2 1 UPPER LIMIT 100µs MODE MODE MODE MODE 2 1 2 1 TRANSITION CONTROL LOAD CURRENT VOUT 3 200µs START LOWER LIMIT CH1 5.00AΩ CH3 20.0mV CH2 5.00AΩ CH4 M 20.0µs FIGURE 9. TRANSIENT RESPONSE TO THE LOAD STEP 0A...5A Auxiliary Over-Voltage Protection Circuit While evaluating a new platform, mistakes and mishaps are almost inevitable. The TM5800 family CPUs have maximum operating voltage VCPU = 1.4V and can be easily damaged by applying a wrong VID code for a long time. To protect a valuable CPU from being destroyed during evaluation, an external over-voltage circuit is incorporated in the evaluation board as an extra protection and convenience measure. The circuit consists of the reference voltage source U3 and the comparator U2. The divider R19/R21 sets the reference voltage to a desired level. The circuit is engaged when jumper JP3 is closed. When engaged, the over-voltage circuit limits the SOFT voltage to the level predetermined by the reference source. 8 FIGURE 10. CPU EMULATOR TIME DIAGRAM The START signal is applied to the gate of Q5 and programs the output voltage by the resistor R8. In the START mode the VID code is rejected. While DSX stays low, the multi-stable generator with 50% duty-factor U6 changes its output from high to low and backwards for several cycles. The MODE CONTROL signal is applied to two multiplexers U7 and U10 that are connected to the VID lines of the controller and switch between two VID codes dialed by SW1. The low MODE CONTROL signal is associated with MODE1, which usually has a lower CPU voltage. The high MODE CONTROL signal is, correspondingly, associated with the higher output voltage mode, MODE 2. As the MODE CONTROL signal changes its state, Q8 and Q10 apply load resistors R39...R44 to the converters output. The resistors’ values are chosen to coordinate with current loading that a real CPU would produce. The CPU leakage current is represented by R45 and R46. Application Note 9989 To achieve a higher degree of resemblance of the waveforms produced by the load emulator, the load is reduced to the leakage level during LongRun™ transitions as it would happen with a real CPU. This is done by two oneshots U8 and U9 that generate short pulses every time the mode changes. These pulses turn off Q8 and Q10, which in turn disconnect loading resistors from the converter output. The time interval during which load is disconnected can be matched to the LongRun™ transition time by changing the time constant of the circuits R33/C24 and R35/C26. The output waveform generated by the converter with activated CPU emulator is shown in Figure 11. NOTE: When measuring efficiency, do not forget to turn off the CPU emulator and open the jumper JP4. To measure current consumed by the control IC and the gate drive circuitry, open the jumper JP1 and place ampere-meter across the jumper posts. PLL Supply The TM5500...TM5800 processors require that V_CPU_PLL track the core voltage within ±50mV down to the lower boundary of 1.0V. As the core voltage drops lower than 1.0V, the V_CPU_PLL must remain at 1.0V. During LongRun transitions, V_CPU_PLL must settle to within the ±50mV of V_CPU_CORE voltage in 25µs. Figure 13 graphically shows this requirement. VPLL MODE2 START VCPU MODE1 1V VOUT VPLL 0 VCPU DSX DSX 1 FIGURE 13. PLL SUPPLY OUTPUT CHARACTERISTIC CH1 100mV CH3 M 500µs CH2 CH4 FIGURE 11. CONVERTER WAVEFORM WITH LOAD EMULATOR Efficiency Efficiency curves captured at different input voltages with the output voltage Vo = 1.3V are captured in Figure 12. 95% Vin=5.0V 85% 80% Vin=10.0V Vin=20.0V HYSTERETIC OPERATION EFFICIENCY 90% 75% 70% 0.00 1.00 2.00 3.00 LOAD CURRENT 4.00 5.00 FIGURE 12. ISL6211 EFFICIENCY The efficiency curves are captured with and without hysteretic mode enabled in light loads. The dashed lines show efficiency improvement when the hysteretic mode of operation is enabled. 9 The schematic in Figure 3 depicts the circuit that provides the required tracking function. The circuit includes the enable switch Q13; the reference voltage source U15, R51, R56, and R57; the ‘ideal’ diode U14a and D6; and the output buffer U14b and Q12. The R55/R59 divider creates a 1.0V reference for the minimum V_CPU_PLL operating voltage that is applied to the positive input of the error amplifier U14a with a diode in its feedback. The negative input of U14a will be regulated to the voltage on its positive input due to high gain of the amplifier. Due to the diode D6 in the feedback path of U14a the regulation will be achieved only if the core voltage is lower than the voltage on R59. For core voltages higher than 1.0V, the diode D6 will be blocked and the voltage on the negative input of U14a will follow the V_CPU_CORE via R53. The voltage follower U14b and Q12 provides the required current capability for the PLL supply and circuits separation. The circuit is enabled by connecting the Q13 gate to the CPU regulator PGOOD signal. Considering ±50mV tolerance requirements, the PLL circuit can be significantly simplified by eliminating the reference source U15. The 1.0V voltage on the resistor R59 should be derived from any system voltage available. The emitter follower Q12 can also be eliminated if V_CPU_PLL current requirements fall within the amplifier loading capabilities. Check the CPU data sheet and Transmeta design guidelines for updates. Application Note 9989 Typical Application Circuit The typical application circuit to be populated in custom designs is presented in Figure 14. F1 VDC=5.0V...24V 2A D1 1 GND 1 C1 1 C2 10uF 10uF 25V 25V 2 2 BAT54WT1 2 R1 5R1 3 2 1 VCC 6 7 1 VID4 R6 105k R7 75k 2 3 2 VID0 1 3 D2 BAT54WT1 11 12 FCCM# PHASE ALTV UGATE FREQ BOOT VID4 NC VID3 VSEN VID2 OCSET VID1 SOFT VID0 VIN 5 6 7 8 22 1 R3 3k57 2 VCORE 1 20 1 R4 5R1 R5 80R6 1 2 1 4 18 Q2 uPA1707 17 C8 1n 50V 2 15 14 13 1 C11 0.22 16V 2 R8 100k + 2 1 1 1 2 FIGURE 14. PRACTICAL POWER SUPPLY DESIGN FOR TM5800 CPU ISL6211 EVAL2 Layout Drawings of the evaluation board layout, by layer, FIGURE 15. TOP SILK LAYER 10 C9 220u 2.5V + R9 2k00 1 10k + 2 16 Q5 BSS123LT1 1 + C7 220u 2.5V 19 2 3 R10 CPU_STOP# C6 220u 2.5V 1 21 2 Q4 BSS123LT1 1 10 ISEN 2 3 2 9 PGND EN L1 1.8uH SumidaCEP1231R8MH ISL6211 2 1 VID2 VID1 Q3 BSS123LT1 1 FORCE_STARTUP_V VID3 8 PGOOD 2 4 1 1 LGATE 23 2 5 VCC 24 1 4 PVCC FIGURE 16. TOP WIRE LAYER 2 3 GND 1 EN 2 2 1 2 PGOOD 2 1 1 C4 0.22 16V Q1 uPA1707 1 2 3 1 C3 1 4.7uF 10V U1 5 6 7 8 C5 4.7uF 10V 1 2 3 R2 10k C10 220u 2.5V Application Note 9989 ISL6211 EVAL2 Layout Drawings of the evaluation board layout, by layer, (Continued) FIGURE 17. GROUND LAYERS FIGURE 18. BOTTOM WIRE LAYER FIGURE 19. POWER LAYERS 1&2 FIGURE 20. BOTTOM SILK LAYER References Intersil documents are available on the web at http://www.intersil.com. [1] ISL6211 Data Sheet, Intersil Corporation, File No. FN9043. All Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 11