ORCA Series 2 Data Sheet

ORCA™ Series 2 Device Datasheet
June 2010
Select Devices Discontinued!
Product Change Notifications (PCNs) have been issued to discontinue select devices in
this data sheet.
The original datasheet pages have not been modified and do not reflect those changes.
Please refer to the table below for reference PCN and current product status.
Product Line
OR2C04A
OR2C06A
OR2C08A
OR2C10A
OR2C12A
Ordering Part Number
OR2C04A4T100-DB
OR2C04A3T100I-DB
OR2C04A4T144-DB
OR2C04A3T144I-DB
OR2C04A4J160-DB
OR2C04A4S208-DB
OR2C06A4T100-DB
OR2C06A4T144-DB
OR2C06A3T144I-DB
OR2C06A4J160-DB
OR2C06A3J160I-DB
OR2C06A4S208-DB
OR2C06A3S208I-DB
OR2C06A3S240I-DB
OR2C06A4BA256-DB
OR2C06A3BA256I-DB
OR2C08A3J160I-DB
OR2C08A4S208-DB
OR2C08A3S208I-DB
OR2C08A3S240I-DB
OR2C08A3M84I-D
OR2C10A4J160-DB
OR2C10A3J160I-DB
OR2C10A4S208-DB
OR2C10A3BA256I-DB
OR2C10A4BA352-DB
OR2C10A3BA352I-DB
OR2C12A3S208-DB
OR2C12A4S208-DB
OR2C12A3S208I-DB
OR2C12A3S240-DB
OR2C12A4S240-DB
OR2C12A3S240I-DB
Product Status
Reference PCN
Discontinued
PCN#02-06
Discontinued
PCN#02-06
Discontinued
PCN#02-06
Discontinued
PCN#02-06
Discontinued
PCN#02-06
5555 N.E. Moore Ct. z Hillsboro, Oregon 97124-6421 z Phone (503) 268-8000 z FAX (503) 268-8347
Internet: http://www.latticesemi.com
Product Line
OR2C12A
(Cont’d)
OR2C15A
OR2C26A
OR2C40A
OR2T04A
OR2T08A
Ordering Part Number
OR2C12A4BA256-DB
OR2C12A3BA256I-DB
OR2C12A4S304-DB
OR2C12A3S304I-DB
OR2C12A4BA352-DB
OR2C12A3BA352I-DB
OR2C12A4M84-D
OR2C15A4S208-DB
OR2C15A3S208I-DB
OR2C15A3PS208I-DB
OR2C15A4S240-DB
OR2C15A3S240I-DB
OR2C15A4PS240-DB
OR2C15A3PS240I-DB
OR2C15A4BA256-DB
OR2C15A3BA256I-DB
OR2C15A4S304-DB
OR2C15A4BA352-DB
OR2C15A3BA352I-DB
OR2C15A3M84I-D
OR2C26A4PS208-DB
OR2C26A3PS208I-DB
OR2C26A4PS208I-DB
OR2C26A4PS240-DB
OR2C26A3PS240I-DB
OR2C26A4PS304-DB
OR2C26A3PS304I-DB
OR2C40A4PS208-DB
OR2C40A3PS208I-DB
OR2C40A4PS208I-DB
OR2C40A4PS240-DB
OR2C40A4PS304-DB
OR2C40A3PS304I-DB
OR2T04A4T100I-DB
OR2T04A4T144-DB
OR2T04A4S208I-DB
OR2T08A5J160-DB
OR2T08A4J160I-DB
OR2T08A5S208-DB
OR2T08A4S208-DB
OR2T08A4S208I-DB
OR2T08A4S240I-DB
OR2T08A5BA256-DB
OR2T08A4BA256-DB
OR2T08A4BA256I-DB
Product Status
Reference PCN
Discontinued
PCN#02-06
Discontinued
PCN#02-06
Discontinued
PCN#02-06
Discontinued
PCN#02-06
Discontinued
PCN#02-06
Discontinued
PCN#02-06
5555 N.E. Moore Ct. z Hillsboro, Oregon 97124-6421 z Phone (503) 268-8000 z FAX (503) 268-8347
Internet: http://www.latticesemi.com
Product Line
OR2T10A
OR2T15A
OR2T15B
OR2T26A
OR2T40A
OR2T40B
Ordering Part Number
OR2T10A4J160I-DB
OR2T10A4S208-DB
OR2T10A4S208I-DB
OR2T10A5S240-DB
OR2T10A4S240-DB
OR2T10A4BA256-DB
OR2T15A7S208-DB
OR2T15A6S208-DB
OR2T15A6S208I-DB
OR2T15A7S240-DB
OR2T15A6S240-DB
OR2T15A6S240I-DB
OR2T15A7BA256-DB
OR2T15A6BA256-DB
OR2T15A7BA352-DB
OR2T15A6M84-D
OR2T15B8S208-DB
OR2T15B7S208-DB
OR2T15B7S208I-DB
OR2T15B7S240I-DB
OR2T15B8BA256-DB
OR2T15B7BA256-DB
OR2T15B7BA352-DB
OR2T15B7BA352I-DB
OR2T26A7S208-DB
OR2T26A6S208-DB
OR2T26A6S208I-DB
OR2T26A7PS240-DB
OR2T26A6PS240-DB
OR2T26A6PS240I-DB
OR2T26A6BA352I-DB
OR2T26A6BC432-DB
OR2T26A6BC432I-DB
OR2T40A7PS208-DB
OR2T40A6PS208-DB
OR2T40A6PS208I-DB
OR2T40A7PS240-DB
OR2T40A6PS240-DB
OR2T40A6PS240I-DB
OR2T40A7BA352-DB
OR2T40A6BA352I-DB
OR2T40B7PS208I-DB
OR2T40B8BA352-DB
OR2T40B7BA352-DB
OR2T40B7BA352I-DB
OR2T40B8BC432-DB
OR2T40B7BC432-DB
OR2T40B7BC432I-DB
Product Status
Reference PCN
Discontinued
PCN#02-06
Discontinued
PCN#09-10
Active / Orderable
Discontinued
PCN#12A-09
Discontinued
Active / Orderable
Discontinued
Discontinued
PCN#09-10
PCN#02-06
PCN#09-10
Discontinued
PCN#02-06
Discontinued
PCN#09-10
Active / Orderable
Discontinued
PCN#06-07
Discontinued
PCN#02-06
Discontinued
PCN#06-07
Discontinued
PCN#02-06
Discontinued
PCN#02-06
5555 N.E. Moore Ct. z Hillsboro, Oregon 97124-6421 z Phone (503) 268-8000 z FAX (503) 268-8347
Internet: http://www.latticesemi.com
5555 N.E. Moore Ct. z Hillsboro, Oregon 97124-6421 z Phone (503) 268-8000 z FAX (503) 268-8347
Internet: http://www.latticesemi.com
Data Sheet
November 2006
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ORCA® Series 2
Field-Programmable Gate Arrays
Features
■
■
■
■
■
■
■
■
■
■
■
High-performance, cost-effective, low-power
0.35 µm CMOS technology (OR2CxxA), 0.3 µm CMOS
technology (OR2TxxA), and 0.25 µm CMOS technology
(OR2TxxB), (four-input look-up table (LUT) delay less
than 1.0 ns with -8 speed grade)
High density (up to 43,200 usable, logic-only gates; or
99,400 gates including RAM)
Up to 480 user I/Os (OR2TxxA and OR2TxxB I/Os are
5 V tolerant to allow interconnection to both 3.3 V and
5 V devices, selectable on a per-pin basis)
Four 16-bit look-up tables and four latches/flip-flops per
PFU, nibble-oriented for implementing 4-, 8-, 16-, and/or
32-bit (or wider) bus structures
Eight 3-state buffers per PFU for on-chip bus structures
Fast, on-chip user SRAM has features to simplify RAM
design and increase RAM speed:
— Asynchronous single port: 64 bits/PFU
— Synchronous single port: 64 bits/PFU
— Synchronous dual port: 32 bits/PFU
Improved ability to combine PFUs to create larger RAM
structures using write-port enable and 3-state buffers
Fast, dense multipliers can be created with the multiplier
mode (4 x 1 multiplier/PFU):
— 8 x 8 multiplier requires only 16 PFUs
— 30% increase in speed
Flip-flop/latch options to allow programmable priority of
synchronous set/reset vs. clock enable
Enhanced cascadable nibble-wide data path
capabilities for adders, subtractors, counters, multipliers,
and comparators including internal fast-carry operation
■
■
■
■
■
■
■
■
■
Innovative, abundant, and hierarchical nibbleoriented routing resources that allow automatic use of
internal gates for all device densities without sacrificing
performance
Upward bit stream compatible with the ORCA ATT2Cxx/
ATT2Txx series of devices
Pinout-compatible with new ORCA Series 3 FPGAs
TTL or CMOS input levels programmable per pin for the
OR2CxxA (5 V) devices
Individually programmable drive capability:
12 mA sink/6 mA source or 6 mA sink/3 mA source
Built-in boundary scan (IEEE *1149.1 JTAG) and
3-state all I/O pins, (TS_ALL) testability functions
Multiple configuration options, including simple, low pincount serial ROMs, and peripheral or JTAG modes for insystem programming (ISP)
Full PCI bus compliance for all devices
Supported by industry-standard CAE tools for design
entry, synthesis, and simulation with ispLEVER Development System support (for back-end implementation)
New, added features (OR2TxxB) have:
— More I/O per package than the OR2TxxA family
— No dedicated 5 V supply (VDD5)
— Faster configuration speed (40 MHz)
— Pin selectable I/O clamping diodes provide 5V or 3.3V
PCI compliance and 5V tolerance
— Full PCI bus compliance in both 5V and 3.3V PCI systems
* IEEE is a registered trademark of The Institute of Electrical and
Electronics Engineers, Inc.
Table 1. ORCA Series 2 FPGAs
Device
Usable
Gates*
# LUTs
Registers
Max User
RAM Bits
User
I/Os
Array Size
OR2C04A/OR2T04A
OR2C06A
OR2C08A/OR2T08A
OR2C10A/OR2T10A
OR2C12A
OR2C15A/OR2T15A/OR2T15B
OR2C26A/OR2T26A
OR2C40A/OR2T40A/OR2T40B
4,800—11,000
6,900—15,900
9,400—21,600
12,300—28,300
15,600—35,800
19,200—44,200
27,600—63,600
43,200—99,400
400
576
784
1024
1296
1600
2304
3600
400
576
724
1024
1296
1600
2304
3600
6,400
9,216
12,544
16,384
20,736
25,600
36,864
57,600
160
192
224
256
288
320
384
480
10 x 10
12 x 12
14 x 14
16 x 16
18 x 18
20 x 20
24 x 24
30 x 30
* The first number in the usable gates column assumes 48 gates per PFU (12 gates per four-input LUT/FF pair) for logic-only designs. The
second number assumes 30% of a design is RAM. PFUs used as RAM are counted at four gates per bit, with each PFU capable of
implementing a 16 x 4 RAM (or 256 gates) per PFU.
Data Sheet
November 2006
ORCA Series 2 FPGAs
Table of Contents
Contents
Page
Page
Boundary-Scan Instructions................................. 57
ORCA Boundary-Scan Circuitry ..........................58
ORCA Timing Characteristics ..................................62
Estimating Power Dissipation ..................................63
OR2CxxA .............................................................63
OR2TxxA .............................................................65
OR2T15B and OR2T40B .....................................67
Pin Information ........................................................68
Pin Descriptions ...................................................68
Package Compatibility .........................................70
Compatibility with Series 3 FPGAs .......................72
Package Thermal Characteristics ..........................128
Theta JA ............................................................128
Theta JC ............................................................128
Theta JC ............................................................128
Theta JB ............................................................128
Package Coplanarity .............................................129
Package Parasitics ................................................129
Absolute Maximum Ratings ...................................131
Recommended Operating Conditions ...................131
Electrical Characteristics .......................................132
Timing Characteristics ...........................................134
Series 2 ..............................................................162
Measurement Conditions .......................................171
Output Buffer Characteristics ................................172
OR2CxxA ...........................................................172
OR2TxxA ...........................................................173
OR2TxxB ...........................................................174
Package Outline Drawings ....................................175
Terms and Definitions ........................................175
84-Pin PLCC ......................................................176
100-Pin TQFP ....................................................177
144-Pin TQFP ....................................................178
160-Pin QFP ......................................................179
208-Pin SQFP ....................................................180
208-Pin SQFP2 ..................................................181
240-Pin SQFP ....................................................182
240-Pin SQFP2 ..................................................183
256-Pin PBGA ...................................................184
304-Pin SQFP ....................................................185
304-Pin SQFP2 ..................................................186
352-Pin PBGA ...................................................187
432-Pin EBGA ...................................................188
Ordering Information .............................................189
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Features ....................................................................1
Description .................................................................3
ispLEVER Development System Overview ...............7
Architecture ...............................................................7
Programmable Logic Cells ........................................7
Programmable Function Unit .................................7
Look-Up Table Operating Modes ..........................9
Latches/Flip-Flops ...............................................17
PLC Routing Resources ......................................19
PLC Architectural Description ..............................24
Programmable Input/Output Cells ...........................27
Inputs ...................................................................27
Outputs ................................................................28
5 V Tolerant I/O (OR2TxxB) ................................29
PCI Compliant I/O ................................................29
PIC Routing Resources .......................................30
PIC Architectural Description ...............................31
PLC-PIC Routing Resources ...............................32
Interquad Routing ....................................................34
Subquad Routing (OR2C40A/OR2T40A Only) ....36
PIC Interquad (MID) Routing ...............................38
Programmable Corner Cells ....................................39
Programmable Routing ........................................39
Special-Purpose Functions ..................................39
Clock Distribution Network ....................................... 39
Primary Clock ......................................................39
Secondary Clock .................................................40
Selecting Clock Input Pins ...................................41
FPGA States of Operation .......................................42
Initialization ..........................................................42
Configuration .......................................................43
Start-Up ...............................................................44
Reconfiguration ...................................................44
Partial Reconfiguration ........................................45
Other Configuration Options ................................45
Configuration Data Format ......................................45
Using ispLEVER to Generate
Configuration RAM Data ...................................46
Configuration Data Frame ...................................46
Bit Stream Error Checking .......................................49
FPGA Configuration Modes .....................................49
Master Parallel Mode ...........................................49
Master Serial Mode .............................................50
Asynchronous Peripheral Mode .......................... 51
Synchronous Peripheral Mode ............................51
Slave Serial Mode ...............................................52
Slave Parallel Mode .............................................52
Daisy Chain .........................................................53
Special Function Blocks ..........................................54
Single Function Blocks ........................................54
Boundary Scan ....................................................56
Contents
2
Lattice Semiconductor
Data Sheet
November 2006
ORCA Series 2 FPGAs
Description
The PLC architecture provides a balanced mix of logic
and routing that allows a higher utilized gate/PFU than
alternative architectures. The routing resources carry
logic signals between PFUs and I/O pads. The routing
in the PLC is symmetrical about the horizontal and vertical axes. This improves routability by allowing a bus of
signals to be routed into the PLC from any direction.
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The ORCA Series 2 series of SRAM-based FPGAs are
an enhanced version of the ATT2C/2T architecture.
The latest ORCA series includes patented architectural
enhancements that make functions faster and easier to
design while conserving the use of PLCs and routing
resources.
mable input/output cells (PICs). An array of PLCs is
surrounded by PICs as shown in Figure 1. Each PLC
contains a programmable function unit (PFU). The
PLCs and PICs also contain routing resources and
configuration RAM. All logic is done in the PFU. Each
PFU contains four 16-bit look-up tables (LUTs) and four
latches/flip-flops (FFs).
The Series 2 devices can be used as drop-in replacements for the ATT2Cxx/ATT2Txx series, respectively,
and they are also bit stream compatible with each
other. The usable gate counts associated with each
series are provided in Table 1. Both series are offered
in a variety of packages, speed grades, and temperature ranges.
Some examples of the resources required and the performance that can be achieved using these devices are
represented in Table 2.
The ORCA series FPGA consists of two basic elements: programmable logic cells (PLCs) and programTable 2. ORCA Series 2CA System Performance
Function
16-bit loadable up/down
counter
16-bit accumulator
8 x 8 parallel multiplier:
— Multiplier mode,
unpipelined1
— ROM mode, unpipelined2
— Multiplier mode, pipelined3
32 x 16 RAM:
— Single port (read and write/
cycle)4
— Single port5
— Dual port6
36-bit parity check (internal)
32-bit address decode
(internal)
#
PFUs
Speed Grade
Unit
-3
-4
4
66.7
87.0
MHz
4
66.7
87.0
MHz
22
9
44
19.3
55.6
69.0
25.1
71.9
82.0
MHz
MHz
MHz
9
28.6
36.2
MHz
9
16
4
3.25
52.6
52.6
11.0
9.5
69.0
83.3
9.1
7.5
MHz
MHz
ns
ns
1.Implemented using 4 x 1 multiplier mode (unpipelined), register-to-register, two 8-bit inputs, one 16-bit output.
2. Implemented using two 16 x 12 ROMs and one 12-bit adder, one 8-bit input, one fixed operand, one 16-bit output.
3. Implemented using 4 x 1 multiplier mode (fully pipelined), two 8-bit inputs, one 16-bit output (28 of 44 PFUs contain only pipelining registers).
4. Implemented using 16 x 4 synchronous single-port RAM mode allowing both read and write per clock cycle, including write/read address
multiplexer.
5. Implemented using 16 x 4 synchronous single-port RAM mode allowing either read or write per clock cycle, including write/read address multiplexer.
6. Implemented using 16 x 2 synchronous dual-port RAM mode.
Lattice Semiconductor
3
Data Sheet
November 2006
ORCA Series 2 FPGAs
Table 3. ORCA Series 2TA System Performance
Speed Grade
Function
4
Unit
-4
-5
-6
-7
87.0
104.2
129.9
144.9
MHz
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16-bit loadable up/down
counter
16-bit accumulator
8 x 8 parallel multiplier:
— Multiplier mode,
unpipelined1
— ROM mode, unpipelined2
— Multiplier mode, pipelined3
32 x 16 RAM:
— Single port (read and write/
cycle)4
— Single port5
— Dual port6
36-bit parity check (internal)
32-bit address decode
(internal)
#
PFUs
4
87.0
104.2
129.9
144.9
MHz
22
9
44
25.1
71.9
82.0
31.0
87.7
103.1
36.0
107.5
125.0
40.3
122.0
142.9
MHz
MHz
MHz
9
36.2
53.8
53.8
62.5
MHz
9
16
4
3.25
69.0
83.3
9.1
7.5
92.6
92.6
7.4
6.1
92.6
92.6
96.2
96.2
MHz
MHz
ns
ns
5.6
5.2
4.6
4.3
1.Implemented using 4 x 1 multiplier mode (unpipelined), register-to-register, two 8-bit inputs, one 16-bit output.
2. Implemented using two 16 x 12 ROMs and one 12-bit adder, one 8-bit input, one fixed operand, one 16-bit output.
3. Implemented using 4 x 1 multiplier mode (fully pipelined), two 8-bit inputs, one 16-bit output (28 of 44 PFUs contain only pipelining registers).
4. Implemented using 16 x 4 synchronous single-port RAM mode allowing both read and write per clock cycle, including write/read address
multiplexer.
5. Implemented using 16 x 4 synchronous single-port RAM mode allowing either read or write per clock cycle, including write/read address multiplexer.
6. Implemented using 16 x 2 synchronous dual-port RAM mode.
4
Lattice Semiconductor
Data Sheet
November 2006
ORCA Series 2 FPGAs
Table 4. ORCA Series 2TB System Performance
Function
Speed Grade
Unit
-7
-8
4
131.6
149.3
MHz
4
131.6
149.3
MHz
22
9
44
37.7
103.1
123.5
44.8
120.5
142.9
MHz
MHz
MHz
9
57.5
69.4
MHz
9
16
4
3.25
97.7
97.7
112.4
112.4
6.1
5.1
4.8
4.0
MHz
MHz
ns
ns
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16-bit loadable up/down
counter
16-bit accumulator
8 x 8 parallel multiplier:
— Multiplier mode,
unpipelined1
— ROM mode, unpipelined2
— Multiplier mode, pipelined3
32 x 16 RAM:
— Single port (read and write/
cycle)4
— Single port5
— Dual port6
36-bit parity check (internal)
32-bit address decode
(internal)
#
PFUs
1.Implemented using 4 x 1 multiplier mode (unpipelined), register-to-register, two 8-bit inputs, one 16-bit output.
2. Implemented using two 16 x 12 ROMs and one 12-bit adder, one 8-bit input, one fixed operand, one 16-bit output.
3. Implemented using 4 x 1 multiplier mode (fully pipelined), two 8-bit inputs, one 16-bit output (28 of 44 PFUs contain only pipelining registers).
4. Implemented using 16 x 4 synchronous single-port RAM mode allowing both read and write per clock cycle, including write/read address
multiplexer.
5. Implemented using 16 x 4 synchronous single-port RAM mode allowing either read or write per clock cycle, including write/read address
multiplexer.
6. Implemented using 16 x 2 synchronous dual-port RAM mode.
Lattice Semiconductor
5
Data Sheet
November 2006
ORCA Series 2 FPGAs
Description (continued)
PL1
R1C1
R1C2
R1C3
R1C4
R1C5
R1C6
R1C7
R1C8
R1C9
PL2
R2C1
R2C2
R2C3
R2C4
R2C5
R2C6
R2C7
R2C8
R2C9
PL3
R3C1
R3C2
R3C3
R3C4
R3C5
R3C6
R3C7
R3C8
PL4
R4C1
R4C2
R4C3
R4C4
R4C5
R4C6
R4C7
PL5
R5C1
R5C2
R5C3
R5C4
R5C5
R5C6
PL6
R6C1
R6C2
R6C3
R6C4
R6C5
PL7
R7C1
R7C2
R7C3
R7C4
PL8
R8C1
R8C2
R8C3
R9C1
R9C2
R9C3
TMID
PT10
PT11
PT12
PT13
PT14
PT15
PT16
PT17
PT18
R1C10 R1C11 R1C12 R1C13 R1C14 R1C15 R1C16 R1C17
R1C18
R2C10 R2C11 R2C12 R2C13 R2C14 R2C15 R2C16 R2C17
R2C18
R3C9
R3C10 R3C11 R3C12 R3C13 R3C14 R3C15 R13C16 R3C17
R3C18
R4C8
R4C9
R4C10 R4C11 R4C12 R4C13 R4C14 R4C15 R4C16 R4C17
R4C18
R5C7
R5C8
R5C9
R5C10 R5C11 R5C12 R5C13 R5C14 R5C15 R5C16 R5C17
R5C18
R6C6
R6C7
R6C8
R6C9
R6C10 R6C11 R6C12 R6C13 R6C14 R6C15 R6C16 R6C17
R6C18
R7C5
R7C6
R7C7
R7C8
R7C9
R7C10 R7C11 R7C12 R7C13 R7C14 R7C15 R7C16 R7C17
R7C18
R8C4
R8C5
R8C6
R8C7
R8C8
R8C9
R8C10 R8C11 R8C12 R8C13 R8C14 R8C15 R8C16 R8C17
R8C18
R9C4
R9C5
R9C6
R9C7
R9C8
R9C9
R9C10 R9C11 R9C12 R9C13 R9C14 R9C15 R9C16 R9C17
R9C18
PR9
PT9
PR8
PT8
PR7
PT7
PR6
PT6
PR5
PT5
PR4
PT4
PR3
PT3
PR2
PT2
PR1
PT1
PL9
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The FPGA’s functionality is determined by internal configuration RAM. The FPGA’s internal initialization/configuration circuitry loads the configuration data at powerup or under system control. The RAM is loaded by using one of
several configuration modes. The configuration data resides externally in an EEPROM, EPROM, or ROM on the
circuit board, or any other storage media. Serial ROMs provide a simple, low pin count method for configuring
FPGAs, while the peripheral and JTAG configuration modes allow for easy, in-system programming (ISP).
vIQ
LMID
PL10
R10C1 R10C2 R10C3
R10C4 R10C5 R10C6
R10C7 R10C8 R10C9
R10C10 R10C11 R10C12 R10C13 R10C14 R10C15 R10C16 R10C17 R10C18
RMID
PL11
R11C1 R11C2 R11C3
R11C4 R11C5 R11C6 R11C7 R11C8 R11C9
R11C10 R11C11 R11C12 R11C13 R11C14 R11C15 R11C16 R11C17 R11C18
PR11
PL12
R12C1 R12C2 R12C3
R12C4 R12C5 R12C6 R12C7 R12C8 R12C9
R12C10 R12C11 R12C12 R12C13 R12C14 R12C15 R12C16 R12C17 R12C18
PR12
PL13
R13C1 R13C2 R13C3
R13C4 R13C5 R13C6 R13C7 R13C8 R13C9
R13C10 R13C11 R13C12 R13C13 R13C14 R13C15 R13C16 R13C17 R13C18
PR13
PL14
R14C1 R14C2 R14C3
R14C4 R14C5 R14C6 R14C7 R14C8 R14C9
R14C10 R14C11 R14C12 R14C13 R14C14 R14C15 R14C16 R14C17 R14C18
PR14
PL15
R15C1 R15C2 R15C3
R15C4 R15C5 R15C6 R15C7 R15C8 R15C9
R15C10 R15C11 R15C12 R15C13 R15C14 R15C15 R15C16 R15C17 R15C18
PR15
PL16
R16C1 R16C2 R16C3
R16C4 R16C5 R16C6 R16C7 R16C8 R16C9
R16C10 R16C11 R16C12 R16C13 R16C14 R16C15 R16C16 R16C17 R16C18
PR16
PL17
R17C1 R17C2 R17C3
R17C4 R17C5 R17C6 R17C7 R17C8 R17C9
R17C10 R17C11 R17C12 R17C13 R17C14 R17C15 R17C16 R17C17 R17C18
PR17
PL18
R18C1 R18C2 R18C3
R18C4 R18C5 R18C6 R18C7 R18C8 R18C9
R18C10 R18C11 R18C12 R18C13 R18C14 R18C15 R18C16 R18C17 R18C18
PR18
PR10
hIQ
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PB8
PB9
PB10
BMID
PB11
PB12
PB13
PB14
PB15
PB16
PB17
PB18
5-6779(F)
Figure 1. Series 2 Array
6
Lattice Semiconductor
Data Sheet
November 2006
ispLEVER Development System Overview
or six-input logic functions. In ripple mode, the highspeed carry logic is used for arithmetic functions, the
new multiplier function, or the enhanced data path
functions. In memory mode, the LUTs can be used as a
16 x 4 read/write or read-only memory (asynchronous
mode or the new synchronous mode) or a new 16 x 2
dual-port memory.
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The ispLEVER development system interfaces to frontend design entry tools and provides the tools to produce a configured FPGA. In the design flow, the user
defines the functionality of the FPGA at two points: at
design entry and at the bit stream generation stage.
ORCA Series 2 FPGAs
Following design entry, the development system’s map,
place, and route tools translate the netlist into a routed
FPGA. Its bit stream generator is then used to generate
the configuration data which is loaded into the FPGA’s
internal configuration RAM. When using the bit stream
generator, the user selects options that affect the functionality of the FPGA. Combined with the front-end
tools, ispLEVER produces configuration data that
implements the various logic and routing options discussed in this data sheet.
Architecture
The ORCA Series FPGA is comprised of two basic
elements: PLCs and PICs. Figure 1 shows an array of
programmable logic cells (PLCs) surrounded by programmable input/output cells (PICs). The Series 2 has
PLCs arranged in an array of 20 rows and 20 columns.
PICs are located on all four sides of the FPGA between
the PLCs and the IC edge.
The location of a PLC is indicated by its row and column so that a PLC in the second row and third column
is R2C3. PICs are indicated similarly, with PT (top) and
PB (bottom) designating rows and PL (left) and PR
(right) designating columns, followed by a number. The
routing resources and configuration RAM are not
shown, but the interquad routing blocks (hIQ, vIQ)
present in the Series 2 series are shown.
Each PIC contains the necessary I/O buffers to interface to bond pads. The PICs also contain the routing
resources needed to connect signals from the bond
pads to/from PLCs. The PICs do not contain any useraccessible logic elements, such as flip-flops.
Combinatorial logic is done in look-up tables (LUTs)
located in the PFU. The PFU can be used in different
modes to meet different logic requirements. The LUT’s
configurable medium-/large-grain architecture can be
used to implement from one to four combinatorial logic
functions. The flexibility of the LUT to handle wide input
functions, as well as multiple smaller input functions,
maximizes the gate count/PFU.
Programmable Logic Cells
The programmable logic cell (PLC) consists of a programmable function unit (PFU) and routing resources.
All PLCs in the array are identical. The PFU, which contains four LUTs and four latches/FFs for logic implementation, is discussed in the next section.
Programmable Function Unit
The PFUs are used for logic. Each PFU has 19 external inputs and six outputs and can operate in several
modes. The functionality of the inputs and outputs
depends on the operating mode.
The PFU uses three input data buses (A[4:0], B[4:0],
WD[3:0]), four control inputs (C0, CK, CE, LSR), and a
carry input (CIN); the last is used for fast arithmetic
functions. There is a 5-bit output bus (O[4:0]) and a
carry-out (COUT).
PROGRAMMABLE LOGIC CELL (PLC)
WD3
WD2
WD1
WD0
A4
A3
A2
A1
A0
COUT
PROGRAMMABLE
FUNCTION UNIT
(PFU)
O4
O3
O2
O1
O0
B4
B3
B2
B1
B0
CIN
C0 CK CE LSR
(ROUTING RESOURCES, CONFIGURATION RAM)
5-2750(F).r3
Figure 2. PFU Ports
The LUTs can be programmed to operate in one of
three modes: combinatorial, ripple, or memory. In combinatorial mode, the LUTs can realize any four-, five-,
Lattice Semiconductor
7
Data Sheet
November 2006
ORCA Series 2 FPGAs
Programmable Logic Cells (continued))
COUT
CARRY
A4
A3
QLUT3
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A4
A2
A3
F3
C
A1
WD3
REG3
CARRY
A1
A3
A2
A1
A0
Q3
D3
A2
C
PFU_NAND
SR
F2
EN
O4
QLUT2
A4
A0
Q2
D2
O3
REG2
WD2
C
CARRY
B4
B4
B3
B2
B3
QLUT1
B3
B2
B1
O1
SR
EN
F0
Q0
D0
QLUT0
WD0
C
T
T
T
T
T
T
T
C
C
EN
C
C0
LSR
GSR
T
REG0
B4
SR
CIN
O0
REG1
WD1
PFU_XOR
C
B0
Q1
D1
C
CARRY
O2
EN
F1
PFU_MUX
B1
B2
B1
B0
SR
C
WD[3:0]
C
CK
CKEN
TRI
5-4573(F)
Key: C = controlled by configuration RAM.
Figure 3. Simplified PFU Diagram
Figure 2 and Figure 3 show high-level and detailed
views of the ports in the PFU, respectively. The ports
are referenced with a two- to four-character suffix to a
PFU’s location. As mentioned, there are two 5-bit input
data buses (A[4:0] and B[4:0]) to the LUT, one 4-bit
input data bus (WD[3:0]) to the latches/FFs, and an
output data bus (O[4:0]).
Figure 3 shows the four latches/FFs (REG[3:0]) and the
64-bit look-up table (QLUT[3:0]) in the PFU. The PFU
does combinatorial logic in the LUT and sequential
logic in the latches/FFs. The LUT is static random
access memory (SRAM) and can be used for read/
write or read-only memory. The eight 3-state buffers
8
found in each PLC are also shown, although they actually reside external to the PFU.
Each latch/FF can accept data from the LUT. Alternatively, the latches/FFs can accept direct data from
WD[3:0], eliminating the LUT delay if no combinatorial
function is needed. The LUT outputs can bypass the
latches/FFs, which reduces the delay out of the PFU. It
is possible to use the LUT and latches/FFs more or
less independently. For example, the latches/FFs can
be used as a 4-bit shift register, and the LUT can be
used to detect when a register has a particular pattern
in it.
Lattice Semiconductor
Data Sheet
November 2006
ORCA Series 2 FPGAs
used as LUT inputs. The use of these ports changes
based on the PFU operating mode.
Table 5 lists the basic operating modes of the LUT. The
operating mode affects the functionality of the PFU
input and output ports and internal PFU routing. For
example, in some operating modes, the WD[3:0] inputs
are direct data inputs to the PFU latches/FFs. In the
dual 16 x 2 memory mode, the same WD[3:0] inputs
are used as a 4-bit data input bus into LUT memory.
The functionality of the LUT is determined by its operating mode. The entries in Table 5 show the basic
modes of operation for combinatorial logic, ripple, and
memory functions in the LUT. Depending on the operating mode, the LUT can be divided into sub-LUTs. The
LUT is comprised of two 32-bit half look-up tables,
HLUTA and HLUTB. Each half look-up table (HLUT) is
comprised of two quarter look-up tables (QLUTs).
HLUTA consists of QLUT2 and QLUT3, while HLUTB
consists of QLUT0 and QLUT1. The outputs of QLUT0,
QLUT1, QLUT2, and QLUT3 are F0, F1, F2, and F3,
respectively.
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Programmable Logic Cells (continued)
The PFU is used in a variety of modes, as illustrated in
Figures 4 through 11, and it is these specific modes
that are most relevant to PFU functionality.
PFU Control Inputs
The four control inputs to the PFU are clock (CK), local
set/reset (LSR), clock enable (CE), and C0. The CK,
CE, and LSR inputs control the operation of all four
latches in the PFU. An active-low global set/reset
(GSRN) signal is also available to the latches/FFs in
every PFU. Their operation is discussed briefly here,
and in more detail in the Latches/Flip-Flops section.
The polarity of the control inputs can be inverted.
The CK input is distributed to each PFU from a vertical
or horizontal net. The CE input inhibits the latches/FFs
from responding to data inputs. The CE input can be
disabled, always enabling the clock. Each latch/FF can
be independently programmed to be set or reset by the
LSR and the global set/reset (GSRN) signals. Each
PFU’s LSR input can be configured as synchronous or
asynchronous. The GSRN signal is always asynchronous. The LSR signal applies to all four latches/FFs in
a PFU. The LSR input can be disabled (the default).
The asynchronous set/reset is dominant over clocked
inputs.
The C0 input is used as an input into the special PFU
gates for wide functions in combinatorial logic mode.
In the memory modes, this input is also used as the
write-port enable input. The C0 input can be disabled
(the default).
Table 5. Look-Up Table Operating Modes
Mode
Function
F4A
Two functions of four inputs, some inputs
shared (QLUT2/QLUT3)
F4B Two functions of four inputs, some inputs
shared (QLUT0/QLUT1)
F5A One function of five inputs (HLUTA)
F5B One function of five inputs (HLUTB)
R
4-bit ripple (LUT)
MA 16 x 2 asynchronous memory (HLUTA)
MB 16 x 2 asynchronous memory (HLUTB)
SSPM 16 x 4 synchronous single-port memory
SDPM 16 x 2 synchronous dual-port memory
For combinatorial logic, the LUT can be used to do any
single function of six inputs, any two functions of five
inputs, or four functions of four inputs (with some inputs
shared), and three special functions based on the two
five-input functions and C0.
Look-Up Table Operating Modes
The look-up table (LUT) can be configured to operate
in one of three general modes:
■
Combinatorial logic mode
■
Ripple mode
■
Memory mode
The combinatorial logic mode uses a 64-bit look-up
table to implement Boolean functions. The two 5-bit
logic inputs, A[4:0] and B[4:0], and the C0 input are
Lattice Semiconductor
9
Data Sheet
November 2006
ORCA Series 2 FPGAs
Programmable Logic Cells (continued)
A4
A4
A3
A3
A2
A2
A1
A1
HLUTA
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The LUT ripple mode operation offers standard arithmetic functions, such as 4-bit adders, subtractors,
adder/subtractors, and counters. In the ORCA
Series 2, there are two new ripple modes available. The
first new mode is a 4 x 1 multiplier, and the second is a
4-bit comparator. These new modes offer the advantages of faster speeds as well as denser logic capabilities.
independent functions of up to five inputs is shown in
Figure 5. In this case, the LUT is configured in the F5A
and F5B modes. As a variation, the LUT can do one
function of up to five input variables and two four-input
functions using F5A and F4B modes or F4A and F5B
modes.
When the LUT is configured to operate in the memory
mode, a 16 x 2 asynchronous memory fits into an
HLUT. Both the MA and MB modes were available in
previous ORCA architectures, and each mode can be
configured in an HLUT separately. In the Series 2,
there are two new memory modes available. The first is
a 16 x 4 synchronous single-port memory (SSPM), and
the second is a 16 x 2 synchronous dual-port memory
(SDPM). These new modes offer easier implementation, faster speeds, denser RAMs, and a dual-port
capability that wasn’t previously offered as an option in
the ATT2Cxx/ATT2Txx families.
If the LUT is configured to operate in the ripple mode, it
cannot be used for basic combinatorial logic or memory
functions. In modes other than the ripple, SSPM, and
SDPM modes, combinations of operating modes are
possible. For example, the LUT can be configured as a
16 x 2 RAM in one HLUT and a five-input combinatorial
logic function in the second HLUT. This can be done by
configuring HLUTA in the MA mode and HLUTB in the
F5B mode (or vice versa).
F4A/F4B Mode—Two Four-Input Functions
Each HLUT can be used to implement two four-input
combinatorial functions, but the total number of inputs
into each HLUT cannot exceed five. The two QLUTs
within each HLUT share three inputs. In HLUTA, the
A1, A2, and A3 inputs are shared by QLUT2 and
QLUT3. Similarly, in HLUTB, the B1, B2, and B3 inputs
are shared by QLUT0 and QLUT1. The four outputs are
F0, F1, F2, and F3. The results can be routed to the
D0, D1, D2, and D3 latch/FF inputs or as an output of
the PFU. The use of the LUT for four functions of up to
four inputs each is given in Figure 4.
F5A/F5B Mode—One Five-Input Variable Function
Each HLUT can be used to implement any five-input
combinatorial function. The input ports are A[4:0] and
B[4:0], and the output ports are F0 and F3. One five or
less input function is input into A[4:0], and the second
five or less input function is input into B[4:0]. The
results are routed to the latch/FF D0 and latch/FF D3
inputs, or as a PFU output. The use of the LUT for two
10
A3
A3
A2
A2
A1
A1
A0
A0
B4
B4
B3
B3
B2
B2
B1
B1
B3
B3
B2
B2
B1
B1
B0
B0
F3
QLUT3
F2
QLUT2
HLUTB
F1
QLUT1
F0
QLUT0
5-2753(F).r2
Figure 4. F4 Mode—Four Functions of FourInput Variables
HLUTA
WEA
A4
A3
A3
A2
A2
A1
A1
A0
A0
WD3
WD3
WD2
WD2
QLUT3
QLUT2
F3
F2
c0
WPE
HLUTB
B4
B4
B3
B3
B2
B2
B1
B1
B0
B0
QLUT1
F0
QLUT0
5-2845(F).r2
Figure 5. F5 Mode—Two Functions of Five-Input
Variables
Lattice Semiconductor
Data Sheet
November 2006
ORCA Series 2 FPGAs
Programmable Logic Cells (continued)
F5M and F5X Modes—Special Function Modes
C0
The PFU contains logic to implement two special function modes which are variations on the F5 mode. As
with the F5 mode, the LUT implements two independent five-input functions. Figure 6 and Figure 7 show
the schematics for F5M and F5X modes, respectively.
The F5X and F5M functions differ from the basic F5A/
F5B functions in that there are three logic gates which
have inputs from the two 5-input LUT outputs. In some
cases, this can be used for faster and/or wider logic
functions.
A4
A4
A3
A3
A2
A2
F3
QLUT3
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F3
As can be seen, two of the three inputs into the NAND,
XOR, and MUX gates, F0 and F3, are from the LUT.
The third input is from the C0 input into PFU. Since the
C0 input bypasses the LUTs, it has a much smaller
delay through the PFU than for all other inputs into the
special PFU gates. This allows multiple PFUs to be
cascaded together while reducing the delay of the critical path through the PFUs. The output of the first special function (either XOR or MUX) is F1. Since the XOR
and MUX share the F1 output, the F5X and F5M
modes are mutually exclusive. The output of the NAND
PFU gate is F2 and is always available in either mode.
To use either the F5M or F5X functions, the LUT must
be in the F5A/F5B mode; i.e., only 5-input LUTs
allowed. In both the F5X and F5M functions, the outputs of the five-input combinatorial functions, F0 and
F3, are also usable simultaneously with the special
PFU gate outputs.
A1
A1
A0
A0
B4
B4
B3
B3
B2
B2
B1
B1
B0
B0
F2
QLUT2
QLUT1
F0
F1
QLUT0
F0
5-2754(F).r3
Figure 6. F5M Mode—Multiplexed Function of Two
Independent Five-Input Variable
Functions
C0
A4
A4
A3
A3
A2
A2
A1
A1
A0
A0
B4
B4
B3
B3
B2
B2
B1
B1
B0
B0
F3
HLUTA
F3
F2
The output of the MUX is:
F1 = (HLUTA & C0) + (HLUTB & C0)
F1 = (F3 & C0) + (F0 & C0)
The output of the exclusive OR is:
F1 = HLUTA ⊕ HLUTB ⊕ C0
F1 = F3 ⊕ F0 ⊕ C0
The output of the NAND is:
F2 = HLUTA & HLUTB & C0
F2 = F3 & F0 & C0
Lattice Semiconductor
HLUTB
F1
F0
F0
5-2755(F).r2
Figure 7. F5X Mode—Exclusive OR Function of Two
Independent Five-Input Variable
Functions
11
Data Sheet
November 2006
ORCA Series 2 FPGAs
Programmable Logic Cells (continued)
two operands are input into A[3:0] and B[3:0]. The four
result bits, one per QLUT, are F[3:0] (see Figure 9).
The ripple output from QLUT3 can be routed to dedicated carry-out circuitry into any of four adjacent PLCs,
or it can be placed on the O4 PFU output, or both. This
allows the PLCs to be cascaded in the ripple mode so
that nibble-wide ripple functions can be expanded easily to any length.
C0
A4
A3
A3
A2
A2
A1
A1
A0
A0
QLUT3
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A4
F3
QLUT2
COUT
F1
F3
A3
B3 COUT
QLUT3
A3
B2
B2
F2
A2
A2 QLUT2
B1
A1
B1
QLUT1
A1
F1
B0
A0
B0
QLUT0
A0
CIN
F0
B3
B4
B4
B3
B3
B2
B2
B1
B1
B0
B0
QLUT1
F0
QLUT0
5-2751(F).r3
Figure 8. F5M Mode—One Six-Input Variable
Function
F5M Mode—One Six-Input Variable Function
The LUT can be used to implement any function of sixinput variables. As shown in Figure 8, five input signals
(A[4:0]) are routed into both the A[4:0] and B[4:0] ports,
and the C0 port is used for the sixth input. The output
port is F1.
Ripple Mode
The LUT can do nibble-wide ripple functions with highspeed carry logic. Each QLUT has a dedicated carryout net to route the carry to/from the adjacent QLUT.
Using the internal carry circuits, fast arithmetic and
counter functions can be implemented in one PFU.
Similarly, each PFU has carry-in (CIN) and carry-out
(COUT) ports for fast-carry routing between adjacent
PFUs.
The ripple mode is generally used in operations on two
4-bit buses. Each QLUT has two operands and a ripple
(generally carry) input, and provides a result and ripple
(generally carry) output. A single bit is rippled from the
previous QLUT and is used as input into the current
QLUT. For QLUT0, the ripple input is from the PFU CIN
port. The CIN data can come from either the fast-carry
routing or the PFU input B4, or it can be tied to logic 1
or logic 0.
CIN
5-2756(F).r32
Figure 9. Ripple Mode
The ripple mode can be used in one of four submodes.
The first of these is adder/subtractor mode. In this
mode, each QLUT generates two separate outputs.
One of the two outputs selects whether the carry-in is
to be propagated to the carry-out of the current QLUT
or if the carry-out needs to be generated. The result of
this selection is placed on the carry-out signal, which is
connected to the next QLUT or the COUT signal, if it is
the last QLUT (QLUT3).
The other QLUT output creates the result bit for each
QLUT that is connected to F[3:0]. If an adder/subtractor
is needed, the control signal to select addition or subtraction is input on A4. The result bit is created in onehalf of the QLUT from a single bit from each input bus,
along with the ripple input bit. These inputs are also
used to create the programmable propagate.
The resulting output and ripple output are calculated by
using generate/propagate circuitry. In ripple mode, the
12
Lattice Semiconductor
Data Sheet
November 2006
ORCA Series 2 FPGAs
Programmable Logic Cells (continued)
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The second submode is the counter submode (see
Figure 10). The present count is supplied to input
A[3:0], and then output F[3:0] will either be incremented by one for an up counter or decremented by
one for a down counter. If an up counter or down
counter is needed, the control signal to select the direction (up or down) is input on A4. Generally, the latches/
FFs in the same PFU are used to hold the present
count value.
In the third submode, multiplier submode, a single
PFU can affect a 4 x 1-bit multiply and sum with a partial product (see Figure 11). The multiplier bit is input at
A4, and the multiplicand bits are input at B[3:0], where
B3 is the most significant bit (MSB). A[3:0] contains the
partial product (or other input to be summed) from a
previous stage. If A4 is logical 1, the multiplicand is
added to the partial product. If A4 is logical zero, zero is
added to the partial product, which is the same as
passing the partial product. CIN can hold the carry-in
from the less significant PFUs if the multiplicand is
wider than 4 bits, and COUT holds any carry-out from
the addition, which may then be used as part of the
product or routed to another PFU in multiplier mode for
multiplicand width expansion.
LUT
COUT
A3
A2
COUT
QLUT3
QLUT2
F3
D Q
Q3
A3
F2
D Q
A2
B3
Q2
B2
A1
B1
A0
B0
0
0
0
0
1 0
1 0
1 0
1 0
A4
COUT
A1
A0
QLUT1
QLUT0
CIN
F1
F0
D Q
+
+
+
F3
F2
F1
F0
CIN
Q1
5-4620(F)
Figure 11. Multiplier Submode
D Q
Q0
CIN
5-4643(F).r1
Figure 10. Counter Submode with Flip-Flops
Lattice Semiconductor
+
Ripple mode’s fourth submode features equality
comparators, where one 4-bit bus is input on B[3:0],
another 4-bit bus is input on B[3:0], and the carry-in is
tied to 0 inside the PFU. The carry-out (≠) signal will be
0 if A = B or will be 1 if A ≠ B. If larger than 4 bits, the
carry-out (≠) signal can be cascaded using fast-carry
logic to the carry-in of any adjacent PFU. Comparators
for greater than or equal or less than (>, =, <) continue
to be supported using the ripple mode subtractor. The
use of this submode could be shown using Figure 9
with CIN tied to 0.
13
Data Sheet
November 2006
ORCA Series 2 FPGAs
Programmable Logic Cells (continued)
enable 4 bits of data from a PLC onto the read data
bus.
Asynchronous Memory Modes—MA and MB
The ORCA Series 2 series also has a new AND function available for each PFU in RAM mode. The inputs to
this function are the write-enable (WE) signal and the
write-port enable (WPE) signal. The write-enable signal
is A4 for HLUTA and B4 for HLUTB, while the other
input into the AND gates for both HLUTs is the writeport enable, input on C0 or CIN. Generally, the WPE
input is driven by the same RAM bank-enable signal
that controls the BIDIs in each PFU.
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The LUT in the PFU can be configured as either read/
write or read-only memory. A read/write address
(A[3:0], B[3:0]), write data (WD[1:0], WD[3:2]), and two
write-enable (WE) ports are used for memory. In asynchronous memory mode, each HLUT can be used as a
16 x 2 memory. Each HLUT is configured independently, allowing functions such as a 16 x 2 memory in
one HLUT and a logic function of five input variables or
less in the other HLUT.
Figure 12 illustrates the use of the LUT for a 16 x 4
memory. When the LUTs are used as memory, there
are independent address, input data, and output data
buses. If the LUT is used as a 16 x 4 read/write memory, the A[3:0] and B[3:0] ports are address inputs
(A[3:0]). The A4 and B4 ports are write-enable (WE)
signals. The WD[3:0] inputs are the data inputs. The
F[3:0] data outputs can be routed out on the O[4:0]
PFU outputs or to the latch/FF D[3:0] inputs.
WEA
A4
A3
A3
A2
A2
A1
A1
A0
A0
HLUTA
F3
F2
WD3
WD3
WD2
WD2 C0
The selection of which RAM bank to write data into
does not require the use of LUTs from other PFUs, as
in previous ORCA architectures. This reduces the number of PFUs required for RAMs larger than 16 words in
depth. Note that if either HLUT is in MA/MB mode, then
the same WPE is active for both HLUTs.
To increase the memory’s word size (e.g., 16 x 8), two
or more PLCs are used again. The address, writeenable, and write-port enable of the PLCs are tied
together (bit by bit), and the data is different for each
PLC. Increasing both the address locations and word
size is done by using a combination of these two techniques.
The LUT can be used simultaneously for both memory
and a combinatorial logic function. Figure 13 shows the
use of a LUT implementing a 16 x 2 RAM (HLUTA) and
any function of up to five input variables (HLUTB).
HLUTA
WPE
WEA
A4
A3
A3
WD1
A2
A2
WD0
A1
A1
WEB
B4
WD1
WD0
B3
B3
B2
B2
B1
B1
B0
B0
C0 HLUTB
F1
F0
A0
WD3
QLUT3
F3
QLUT2
F2
A0
WD3
C0
WPE
HLUTB
5-2757(F).r3
Figure 12. MA/MB Mode—16 x 4 RAM
To increase memory word depth above 16 (e.g., 32 x
4), two or more PLCs can be used. The address and
write data inputs for the two or more PLCs are tied
together (bit by bit), and the data outputs are routed
through the four 3-statable BIDIs available in each PFU
and are then tied together (bit by bit).
B4
B4
B3
B3
B2
B2
B1
B1
B0
B0
QLUT1
F0
QLUT0
5-2845(F).a.r1
The control signal of the 3-statable BIDIs, called a RAM
bank-enable, is created from a decode of upper
address bits. The RAM bank-enable is then used to
14
Figure 13. MA/F5 Mode—16 x 2 Memory and One
Function of Five Input Variables
Lattice Semiconductor
Data Sheet
November 2006
ORCA Series 2 FPGAs
Programmable Logic Cells (continued)
Synchronous Memory Modes—SSPM and SDPM
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The MA/MB asynchronous memory modes described
previously allow the PFU to perform as a 16 x 4
(64 bits) single-port RAM. Synchronously writing to this
RAM requires the write-enable control signal to be
gated with the clock in another PFU to create a write
pulse. To simplify this functionality, the Series 2 devices
contain a synchronous single-port memory (SSPM)
mode, where the generation of the write pulse is done
in each PFU.
The write address (WA[3:0]) and write data (WD[3:0])
are also latched by the RAM clock in order to simplify
the timing. Reading data from the RAM is done asynchronously; thus, the read address (RA[3:0]) is not
latched. The result from the read operation is placed on
the LUT outputs (F[3:0]). The F[3:0] data outputs can
be routed out of the PFU or sent to the latch/FF D[3:0]
inputs.
With SSPM mode, the entire LUT becomes a 16 x 4
RAM, as shown in Figure 14. In this mode, the input
ports are write enable (WE), write-port enable (WPE),
read/write address (A[3:0]), and write data (WD[3:0]).
To synchronously write the RAM, WE (input into a4)
and WPE (input into either C0 or CIN) are latched and
ANDed together. The result of this AND function is sent
to a pulse generator in the LUT, which writes the RAM
synchronous to the RAM clock. This RAM clock is the
same one sent to the PFU latches/FFs; however, if necessary, it can be programmably inverted.
A4
WE
D Q
WRITE PULSE
GENERATOR
HLUTA
WR
CIN, C0
WPE
F3
The write address is supplied on the phase of the clock
that allows for setup to the RAM clock, and the read
address is supplied on the phase of the clock that
allows the read data to be set up to the latch/FF clock.
If a higher-speed RAM is required that allows both a
read and write in each clock cycle, the synchronous
dual-port memory mode (SDPM) can be used, since it
does not require the use of an external multiplexer.
D Q
F2
WA[3:0]
RA[3:0]
WD[3:2]
A[3:0]
There are two ways to use the latches/FFs in conjunction with the SSPM. If the phase of the latch/FF clock
and the RAM clock are the same, only a read address
or write address can be supplied to the RAM that
meets the synchronous timing requirements of both
the RAM clock and latch/FF clock. Therefore, either a
write to the RAM or a read from the RAM can be done
in each clock cycle, but not both. If the RAM clock is
inverted from the latch/FF clock, then both a write to
the RAM and a read from the RAM can occur in each
clock cycle. This is done by adding an external write
address/read address multiplexer as shown in
Figure 15.
A[3:0], B[3:0]
SSPM
WRITE ADDRESS
READ ADDRESS
WD[3:0] WD[3:0]
1
WD
A
0
WE
D Q
D
Q
WPE
D Q
HLUTB
RAM CLK
WR
F1
WA[3:0]
RA[3:0]
WD[1:0]
F0
CLOCK
PFU
5-4642(F).r1
5-4644(F).r1
Figure 15. SSPM with Read/Write per Clock Cycle
Figure 14. SSPM Mode—16 x 4 Synchronous
Single-Port Memory
Lattice Semiconductor
15
Data Sheet
November 2006
ORCA Series 2 FPGAs
Programmable Logic Cells (continued)
UPPER
ADDRESS
BITS
ADDRESS
DECODE
LUT1
BANK_EN1
WPE
DO
4
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DI
WR
BIDI
16 x 4 RAM +
4 BUFFERS/PFU
UPPER
ADDRESS
BITS
ADDRESS
DECODE
LUT2
BANK_EN2
4
DOUT
WPE
DIN
WR
4
CLK
DI
WR
DO
4
BIDI
16 x 4 RAM +
4 BUFFERS/PFU
5-4640(F)
Note: The lower address bits are not shown.
Figure 16. Synchronous RAM with Write-Port Enable (WPE)
To increase memory word depth above 16 (e.g., 32 x
4), two or more PLCs can be used. The address and
write data inputs for the two or more PLCs are tied
together (bit by bit), and the data outputs are routed
through the four 3-statable BIDIs available in each
PFU. The BIDI outputs are then tied together (bit by
bit), as seen in Figure 16.
The control signals of the 3-statable BIDIs, called RAM
bank-enable (BANK_EN1 and BANK_EN2), are created from a decode of upper address bits. The RAM
bank-enable is then used to enable 4 bits of data from
a PLC onto the read data (DOUT) bus.
The Series 2 series now has a new AND function available for each PFU in RAM mode. The inputs to this
function are the write-enable (WE) signal and the writeport enable (WPE) signal. The write-enable signal is
input on A4, while the write-port enable is input on C0
or CIN. Generally, the WPE input is driven by the same
RAM bank-enable signal that controls the BIDIs in each
PFU.
16
The selection as to which RAM bank to write data into
does not require the use of LUTs from other PFUs, as
in previous ORCA architectures. This reduces the number of PFUs required for RAMs larger than 16 words in
depth.
A special use of this method can be to increase word
depth to 32 words. Since both the WPE input into the
RAM and the 3-state input into the BIDI can be
inverted, a decode of the one upper address bit is not
required. Instead, the bank-enable signal for both
banks is tied to the upper address bit, with the WPE
and 3-state inputs active-high for one bank and activelow for the other.
To increase the memory’s word size (e.g., 16 x 8), two
or more PLCs are used again. The address, writeenable, and write-port enable of the PLCs are tied
together (bit by bit), and the data is different for each
PLC. Increasing both the address locations and word
size is accomplished by using a combination of these
two techniques.
Lattice Semiconductor
Data Sheet
November 2006
ORCA Series 2 FPGAs
Programmable Logic Cells (continued)
WE
A4
D Q
Latches/Flip-Flops
WRITE PULSE
GENERATOR
HLUTA
CIN, C0
F3
D Q
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WPE
SSPM OUTPUT
WR
The four latches/FFs in the PFU can be used in a variety of configurations. In some cases, the configuration
options apply to all four latches/FFs in the PFU. For
other options, each latch/FF is independently programmable.
WA[3:0]
RA[3:0]
WD[1:0]
WA[3:0] A[3:0]
WD[1:0] WD[1:0]
F2
D Q
D Q
HLUTB
F1
RA[3:0] B[3:0]
WA[3:0]
RA[3:0]
WD[1:0]
F0
SDPM OUTPUT
WR
5-4641(F).r1
Figure 17. SDPM Mode—16 x 2 Synchronous
Dual-Port Memory
The Series 2 devices have added a second synchronous memory mode known as the synchronous dualport memory (SDPM) mode. This mode writes data
into the memory synchronously in the same manner
described previously for SSPM mode. The SDPM
mode differs in that two separate 16 x 2 memories are
created in each PFU that have the same WE, WPE,
write data (WD[1:0]), and write address (WA[3:0])
inputs, as shown in Figure 17.
The outputs of HLUTA (F[3:2]) operate the same way
they do in SSPM mode—the read address comes
directly from the A[3:0] inputs used to create the
latched write address. The outputs of HLUTB (F[1:0])
operate in a dual-port mode where the write address
comes from the latched version of A[3:0], and the read
address comes directly from RA[3:0], which is input on
B[3:0].
Table 6 summarizes these latch/FF options. The
latches/FFs can be configured as either positive or
negative level-sensitive latches, or positive or negative
edge-triggered flip-flops. All latches/FFs in a given PFU
share the same clock, and the clock to these latches/
FFs can be inverted. The input into each latch/FF is
from either the corresponding QLUT output (F[3:0]) or
the direct data input (WD[3:0]). For latches/FFs located
in the two outer rings of PLCs, additional inputs are
possible. These additional inputs are fast paths from
I/O pads located in PICs in the same row or column as
the PLCs. If the latch/FF is not located in the two outer
rings of the PLCs, the latch/FF input can also be tied to
logic 0, which is the default. The four latch/FF outputs,
Q[3:0], can be placed on the five PFU outputs, O[4:0].
Table 6. Configuration RAM Controlled Latch/
Flip-Flop Operation
Function
Options
Functionality Common to All Latch/FFs in PFU
LSR Operation
Asynchronous or synchronous
Clock Polarity
Noninverted or inverted
Front-End Select
Direct (WD[3:0]) or from LUT
(F[3:0])
LSR Priority
Either LSR or CE has priority
Functionality Set Individually in Each Latch/FF in PFU
Latch/FF Mode
Latch or flip-flop
Set/Reset Mode
Set or Reset
The four latches/FFs in a PFU share the clock (CK),
clock enable (CE), and local set/reset (LSR) inputs.
When CE is disabled, each latch/FF retains its previous
value when clocked. Both the clock enable and LSR
inputs can be inverted to be active-low.
Since external multiplexing of the write address and
read address is not required, extremely fast RAMs can
be created. New system applications that require an
interface between two different asynchronous clocks
can also be implemented using the SDPM mode. An
example of this is accomplished by creating FIFOs
where one clock controls the synchronous write of data
into the FIFO, and the other clock controls the read
address to allow reading of data at any time from the
FIFO.
Lattice Semiconductor
17
Data Sheet
November 2006
ORCA Series 2 FPGAs
Programmable Logic Cells (continued)
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The set/reset operation of the latch/FF is controlled by
two parameters: reset mode and set/reset value. When
the global set/reset (GSRN) or local set/reset (LSR) are
inactive, the storage element operates normally as a
latch or FF. The reset mode is used to select a synchronous or asynchronous LSR operation. If synchronous,
LSR is enabled only if clock enable (CE) is active. For
the Series 2 series, a new option called the LSR priority allows the synchronous LSR to have priority over the
CE input, thereby setting or resetting the FF independent of the state of CE. The clock enable is supported
on FFs, not latches. The clock enable function is implemented by using a two-input multiplexer on the FF
input, with one input being the previous state of the FF
and the other input being the new data applied to the
FF. The select of this two-input multiplexer is clock
enable (CE), which selects either the new data or the
previous state. When CE is inactive, the FF output does
not change when the clock edge arrives.
For PLCs that are in the two outside rows or columns of
the array, the latch/FFs can have two inputs in addition
to the F and WD inputs mentioned above. One input is
from an I/O pad located at the PIC closest to either the
left or right of the given PLC (if the PLC is in the left two
columns or right two columns of the array). The other
input is from an I/O pad located at the closest PIC
either above or below the given PLC (if the PLC is in
the top or the bottom two rows). It should be noted that
both inputs are available for a 2 x 2 array of PLCs in
each corner of the array. For the entire array of PLCs, if
either or both of these inputs is unavailable, the latch/
FF data input can be tied to a logic 0 instead (the
default).
The GSRN signal is only asynchronous, and it sets/
resets all latches/FFs in the FPGA based upon the set/
reset configuration bit for each latch/FF. The set/reset
value determines whether GSRN and LSR are set or
reset inputs. The set/reset value is independent for
each latch/FF.
If the local set/reset is not needed, the latch/FF can be
configured to have a data front-end select. Two data
inputs are possible in the front-end select mode, with
the LSR signal used to select which data input is used.
The data input into each latch/FF is from the output of
its associated QLUT F[3:0] or direct from WD[3:0],
bypassing the LUT. In the front-end data select mode,
both signals are available to the latches/FFs.
CE
PDINTB
PDINLR
F
WD
LOGIC 0
To speed up the interface between signals external to
the FPGA and the latches/FFs, there are direct paths
from latch/FF outputs to the I/O pads. This is done for
each PLC that is adjacent to a PIC.
The latches/FFs can be configured in three modes:
1. Local synchronous set/reset: the input into the PFU’s
LSR port is used to synchronously set or reset each
latch/FF.
2. Local asynchronous set/reset: the input into LSR
asynchronously sets or resets each latch/FF.
3. Latch/FF with front-end select: the data select signal
(actually LSR) selects the input into the latches/FFs
between the LUT output and direct data in.
For all three modes, each latch/FF can be independently programmed as either set or reset. Each latch/
FF in the PFU is independently configured to operate
as either a latch or flip-flop. Figure 18 provides the logic
functionality of the front-end select, global set/reset,
and local set/reset operations.
CE
D
CE
Q
S_SET
PDINTB
PDINLR
F
WD
LOGIC 0
D
CE
Q
PDINTB
PDINLR
F
WD
LOGIC 0
LSR
CE
D
WD
CE
Q
LSR
S_RESET
CLK
GSRN
LSR
CLK
CLK
SET RESET
SET RESET
GSRN
SET RESET
GSRN
CD
CD
CD
Note: CD = configuration data.
5-2839(F).a
Figure 18. Latch/FF Set/Reset Configurations
18
Lattice Semiconductor
Data Sheet
November 2006
ORCA Series 2 FPGAs
Programmable Logic Cells (continued)
INDEPENDENT CIP
PLC Routing Resources
B
Generally, the ispLEVER development system is used
to automatically route interconnections. Interactive
routing with the ispLEVER design editor (EPIC) is also
available for design optimization. To use EPIC for interactive layout, an understanding of the routing
resources is needed and is provided in this section.
CD
=
A
B
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A
The routing resources consist of switching circuitry and
metal interconnect segments. Generally, the metal
lines which carry the signals are designated as routing
nodes (lines). The switching circuitry connects the routing nodes, providing one or more of three basic functions: signal switching, amplification, and isolation. A
net running from a PFU or PIC output (source) to a
PLC or PIC input (destination) consists of one or more
lines, connected by switching circuitry designated as
configurable interconnect points (CIPs).
The following sections discuss PLC, PIC, and interquad
routing resources. This section discusses the PLC
switching circuitry, intra-PLC routing, inter-PLC routing,
and clock distribution.
Configurable Interconnect Points
The process of connecting lines uses three basic types
of switching circuits: two types of configurable interconnect points (CIPs) and bidirectional buffers (BIDIs). The
basic element in CIPs is one or more pass transistors,
each controlled by a configuration RAM bit. The two
types of CIPs are the mutually exclusive (or multiplexed) CIP and the independent CIP.
A mutually exclusive set of CIPs contains two or more
CIPs, only one of which can be on at a time. An independent CIP has no such restrictions and can be on
independent of the state of other CIPs. Figure 19
shows an example of both types of CIPs.
Lattice Semiconductor
MULTIPLEXED CIP
CD
O
2
A
B
C
A
B
O
C
f.13(F)
Figure 19. Configurable Interconnect Point
3-Statable Bidirectional Buffers
Bidirectional buffers provide isolation as well as amplification for signals routed a long distance. Bidirectional
buffers are also used to drive signals directly onto
either vertical or horizontal XL and XH lines (to be
described later in the inter-PLC routing section). BIDIs
are also used to indirectly route signals through the
switching lines. Any number from zero to eight BIDIs
can be used in a given PLC.
The BIDIs in a PLC are divided into two nibble-wide
sets of four (BIDI and BIDIH). Each of these sets has a
separate BIDI controller that can have an application
net connected to its TRI input, which is used to 3-state
enable the BIDIs. Although only one application net
can be connected to both BIDI controllers, the sense of
this signal (active-high, active-low, or ignored) can be
configured independently. Therefore, one set can be
used for driving signals, the other set can be used to
create 3-state buses, both sets can be used for 3-state
buses, and so forth.
19
Data Sheet
November 2006
ORCA Series 2 FPGAs
Programmable Logic Cells (continued)
TRI
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BIDI
CONTROLLER
Switching Lines. There are four sets of switching lines
in each PLC, one in each corner. Each set consists of
five switching elements, labeled SUL[4:0], SUR[4:0],
SLL[4:0], and SLR[4:0], for the upper-left, upper-right,
lower-left, and lower-right sections of the PFUs,
respectively. The switching lines connect to the PFU
inputs and outputs as well as the BIDI and BIDIH lines,
to be described later. They also connect to both the
horizontal and vertical X1 and X4 lines (inter-PLC routing resources, described below) in their specific corner.
RIGHT-LEFT BIDI
LEFT-RIGHT BIDI
UNUSED BIDI
LEFT-RIGHT BIDI
BIDIH
CONTROLLER
RIGHT-LEFT BIDIH
LEFT-RIGHT BIDIH
UNUSED BIDIH
LEFT-RIGHT BIDIH
5-4479p2(F)
Figure 20. 3-Statable Bidirectional Buffers
One of the four sets of switching lines can be connected to a set of switching lines in each of the four
adjacent PLCs or PICs. This allows direct routing of up
to five signals without using inter-PLC routing.
BIDI/BIDIH Lines. There are two sets of bidirectional
lines in the PLC, each set consisting of four bidirectional buffers. They are designated BIDI and BIDIH and
have similar functionality. The BIDI lines are used in
conjunction with the XL lines, and the BIDIH lines are
used in conjunction with the XH lines. Each side of the
four BIDIs in the PLC is connected to a BIDI line on the
left (BL[3:0]) and on the right (BR[3:0]). These lines can
be connected to the XL lines through CIPs, with BL[3:0]
connected to the vertical XL lines and BR[3:0] connected to the horizontal XL lines. Both BL[3:0] and
BR[3:0] have CIPs which connect to the switching
lines.
Similarly, each side of the four BIDIHs is connected to a
BIDIH line: BLH[3:0] on the left and BRH[3:0] on the
right. These lines can also be connected to the XH
lines through CIPs, with BLH[3:0] connected to the vertical XH lines and BRH[3:0] connected to the horizontal
XH lines. Both BLH[3:0] and BRH[3:0] have CIPs which
connect to the switching lines.
CIPs are also provided to connect the BIDIH and BIDIL
lines together on each side of the BIDIs. For example,
BLH3 can connect to BL3, while BRH3 can connect to
BR3.
Intra-PLC Routing
The function of the intra-PLC routing resources is to
connect the PFU’s input and output ports to the routing
resources used for entry to and exit from the PLC.
These are nets for providing PFU feedback, turning
corners, or switching from one type of routing resource
to another.
PFU Input and Output Ports. There are 19 input ports
to each PFU. The PFU input ports are labeled A[4:0],
B[4:0], WD[3:0], C0, CK, LSR, CIN, and CE. The six
output ports are O[4:0] and COUT. These ports correspond to those described in the PFU section.
20
Lattice Semiconductor
Data Sheet
November 2006
VX4[7:4]
VX1[7:4]
VXH[3:0]
VXL[3:0]
Programmable Logic Cells (continued)
Inter-PLC Routing Resources
HX4[7:4]
HX1[7:4]
CKL, CKR
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The inter-PLC routing is used to route signals between
PLCs. The lines occur in groups of four, and differ in the
numbers of PLCs spanned. The X1 lines span one
PLC, the X4 lines span four PLCs, the XH lines span
one-half the width (height) of the PLC array, and the XL
lines span the width (height) of the PLC array. All types
of lines run in both horizontal and vertical directions.
DIRECT[4:0]
CKB, CKT
VX1[3:0]
VX4[3:0]
ORCA Series 2 FPGAs
Table 5 shows the groups of inter-PLC lines in each
PLC. In the table, there are two rows/columns each for
X1 and X4 lines. In the design editor, the horizontal X1
and X4 lines are located above and below the PFU.
Similarly, the vertical segments are located on each
side. The XL and XH lines only run below and to the left
of the PFU. The indexes specify individual lines within a
group. For example, the VX4[2] line runs vertically to
the left of the PFU, spans four PLCs, and is the third
line in the 4-bit wide bus.
Table 5. Inter-PLC Routing Resources
Horizontal
Lines
Vertical
Lines
Distance
Spanned
HX1[3:0]
HX1[7:4]
HX4[3:0]
HX4[7:4]
HXL[3:0]
HXH[3:0]
CKL, CKR
VX1[3:0]
VX1[7:4]
VX4[3:0]
VX4[7:4]
VXL[3:0]
VXH[3:0]
CKT, CKB
One PLC
One PLC
Four PLCs
Four PLCs
PLC Array
1/2 PLC Array
PLC Array
Figure 21 shows the inter-PLC routing within one PLC.
Figure 22 provides a global view of inter-PLC routing
resources across multiple PLCs.
Lattice Semiconductor
DIRECT[4:0]
PROGRAMMABLE
FUNCTION UNIT
DIRECT[4:0]
HXL[3:0]
HXH[3:0]
HX1[3:0]
HX4[3:0]
DIRECT[4:0]
5-4528(F)
Figure 21. Single PLC View of Inter-PLC Lines
X1 Lines. There are a total of 16 X1 lines per PLC:
eight vertical and eight horizontal. Each of these is subdivided into nibble-wide buses: HX1[3:0], HX1[7:4],
VX1[3:0], and VX1[7:4]. An X1 line is one PLC long.
If a net is longer than one PLC, an X1 line can be
lengthened to n times its length by turning on n – 1
CIPs. A signal is routed onto an X1 line via the switching lines.
X4 Lines. There are four sets of four X4 lines, for a total
of 16 X4 lines per PLC. They are HX4[3:0], HX4[7:4],
VX4[3:0], and VX4[7:4]. Each set of X4 lines is twisted
each time it passes through a PLC, and one of the four
is broken with a CIP. This allows a signal to be routed
for a length of four cells in any direction on a single line
without additional CIPs. The X4 lines can be used to
route any nets that require minimum delay. A longer net
is routed by connecting two X4 lines together by a CIP.
The X4 lines are accessed via the switching lines.
21
Data Sheet
November 2006
ORCA Series 2 FPGAs
Programmable Logic Cells (continued)
This feature is discussed in detail in the Clock Distribution Network section.
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XL Lines. The long XL lines run vertically and horizontally the height and width of the array, respectively.
There are a total of eight XL lines per PLC: four horizontal (HXL[3:0]) and four vertical (VXL[3:0]). Each
PLC column has four XL lines, and each PLC row has
four XL lines. Each of the XL lines connects to the two
PICs at either end. The Series 2, which consists of a
18 x 18 array of PLCs, contains 72 VXL and 72 HXL
lines. They are intended primarily for global signals
which must travel long distances and require minimum
delay and/or skew, such as clocks.
The clock lines are designed to be a clock spine. In
each PLC, there is a fast connection available from the
clock line to the long-line driver (described earlier).
With this connection, one of the clock lines in each PLC
can be used to drive one of the four XL lines perpendicular to it, which, in turn, creates a clock tree.
There are three methods for routing signals onto the XL
lines. In each PLC, there are two long-line drivers: one
for a horizontal XL line, and one for a vertical XL line.
Using the long-line drivers produces the least delay.
The XL lines can also be driven directly by PFU outputs
using the BIDI lines. In the third method, the XL lines
are accessed by the bidirectional buffers, again using
the BIDI lines.
XH Lines. Four by half (XH) lines run horizontally and
four XH lines run vertically in each row and column in
the array. These lines travel a distance of one-half the
PLC array before being broken in the middle of the
array, where they connect to the interquad block (discussed later). They also connect at the periphery of the
FPGA to the PICs, like the XL lines. The XH lines do
not twist like XL lines, allowing nibble-wide buses to be
routed easily.
Two of the three methods of routing signals onto the
XL lines can also be used for the XH lines. A special
XH line driver is not supplied for the XH lines.
Minimizing Routing Delay
The CIP is an active element used to connect two lines.
As an active element, it adds significantly to the resistance and capacitance of a net, thus increasing the
net’s delay. The advantage of the X1 line over a X4 line
is routing flexibility. A net from PLC db to PLC cb is
easily routed by using X1 lines. As more CIPs are
added to a net, the delay increases. To increase speed,
routes that are greater than two PLCs away are routed
on the X4 lines because a CIP is located only in every
fourth PLC. A net that spans eight PLCs requires seven
X1 lines and six CIPs. Using X4 lines, the same net
uses two lines and one CIP.
All routing resources in the PLC can carry 4-bit buses.
In order for data to be used at a destination PLC that is
in data path mode, the data must arrive unscrambled.
For example, in data path operation, the least significant bit 0 must arrive at either A[0] or B[0]. If the bus is
to be routed by using either X4 or XL lines (both of
which twist as they propagate), the bus must be placed
on the appropriate lines at the source PLC so that the
data arrives at the destination unscrambled. The
switching lines provide the most efficient means of connecting adjacent PLCs. Signals routed with these lines
have minimum propagation delay.
Clock Lines. For a very fast and low-skew clock (or
other global signal tree), clock lines run the entire
height and width of the PLC array. There are two horizontal clock lines per PLC row (CKL, CKR) and two
vertical clock lines per PLC column (CKT, CKB). The
source for these clock lines can be any of the four I/O
buffers in the PIC. The horizontal clock lines in a row
(CKL, CKR) are driven by the left and right PICs,
respectively. The vertical clock lines in a column (CKT,
CKB) are driven by the top and bottom PICs, respectively.
22
Lattice Semiconductor
Data Sheet
November 2006
ORCA Series 2 FPGAs
VX4[0]
VX4[3]
VX4[2]
VX4[1]
VX1[3:0]
CKB
CKT
VXL[0]
VXL[3]
VXL[2]
VXL[1]
VXH[3:0]
VX1[7:4]
VX4[4]
VX4[7]
VX4[6]
VX4[5]
VX4[0]
VX4[3]
VX4[2]
VX4[1]
VX1[3:0]
CKB
CKT
VXL[2]
VXL[1]
VXL[0]
VXL[3]
VXH[3:0]
VX1[7:4]
VX4[4]
VX4[7]
VX4[6]
VX4[5]
VX4[0]
VX4[3]
VX4[2]
VX4[1]
VX1[3:0]
CKB
CKT
Programmable Logic Cells (continued)
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HX4[7]
HX4[6]
HX4[5]
HX4[4]
HX1[7:4]
CKL
CKR
PFU
PFU
HX4[4]
HX4[7]
HX4[6]
HX4[5]
HX1[7:4]
CKL
CKR
PFU
HXL[3]
HXL[2]
HXL[1]
HXL[0]
HXH[3:0]
HX1[3:0]
HXL[2]
HXL[1]
HXL[0]
HXL[3]
HXH[3:0]
HX1[3:0]
HX4[3]
HX4[2]
HX4[1]
HX4[0]
HX4[0]
HX4[3]
HX4[2]
HX4[1]
HX4[7]
HX4[6]
HX4[5]
HX4[4]
HX4[4]
HX4[7]
HX4[6]
HX4[5]
HX1[7:4]
CKL
CKR
PFU
PFU
HX1[7:4]
CKL
CKR
PFU
HXL[3]
HXL[2]
HXL[1]
HXL[0]
HXL[2]
HXL[1]
HXL[0]
HXL[3]
HXH[3:0]
HXH[3:0]
HX1[3:0]
HX1[3:0]
HX4[3]
HX4[2]
HX4[1]
HX4[0]
HX4[0]
HX4[3]
HX4[2]
HX4[1]
HX4[7]
HX4[6]
HX4[5]
HX4[4]
HX4[4]
HX4[7]
HX4[6]
HX4[5]
HX1[7:4]
CKL
CKR
CKL
CKR
VX4[3]
VX4[2]
VX4[1]
VX4[0]
VX1[3:0]
VXL[3]
VXL[2]
VXL[1]
VXL[0]
VX1[7:4]
VXH[3:0]
VX4[7]
VX4[6]
VX4[5]
VX4[4]
VX4[3]
VX4[2]
VX4[1]
VX4[0]
VX1[3:0]
PFU
CKB
CKT
VXL[3]
VXL[2]
VXL[1]
VXL[0]
VX1[7:4]
VXH[3:0]
VX4[7]
VX4[6]
VX4[5]
VX4[4]
VX4[3]
VX4[2]
VX4[1]
VX4[0]
VX1[3:0]
CKB
CKT
PFU
CKB
CKT
PFU
HX1[7:4]
SHOWS PLCs
5-2841(F)2C.r9
Figure 22. Multiple PLC View of Inter-PLC Routing
Lattice Semiconductor
23
ORCA Series 2 FPGAs
Programmable Logic Cells (continued)
PLC Architectural Description
D. The X4 lines are twisted at each PLC. One of the
four X4 lines is broken with a CIP, which allows a signal to be routed a distance of four PLCs in any direction on a single line without an intermediate CIP. The
X4 lines are less populated with CIPs than the X1
lines to increase their speed. A CIP can be enabled
to extend an X4 line four more PLCs, and so on.
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Figure 23 is an architectural drawing of the PLC which
reflects the PFU, the lines, and the CIPs. A discussion
of each of the letters in the drawing follows.
Data Sheet
November 2006
A. These are switching lines which give the router flexibility. In general switching theory, the more levels of
indirection there are in the routing, the more routable
the network is. The switching lines can also connect
to adjacent PLCs.
For example, if an application signal is routed onto
HX4[4] in a PLC, it appears on HX4[5] in the PLC to
the right. This signal step-up continues until it
reaches HX4[7], two PLCs later. At this point, the
user can break the connection or continue the signal
for another four PLCs.
The switching lines provide direct connections to
PLCs directly to the top, bottom, left, and right, without using other routing resources. The ability to disable this connection between PLCs is provided so
that each side of these connections can be used
exclusively as switching lines in their respective
PLC.
E. These symbols are bidirectional buffers (BIDIs).
There are four BIDIs per PLC, and they provide signal amplification as needed to decrease signal
delay. The BIDIs are also used to transmit signals on
XL lines.
B. These CIPs connect the X1 routing. These are
located in the middle of the PLC to allow the block to
connect to either the left end of the horizontal X1 line
from the right or the right end of the horizontal X1
line from the left, or both. By symmetry, the same
principle is used in the vertical direction. The X1
lines are not twisted, making them suitable for data
paths.
C. This set of CIPs is used to connect the X1 and X4
nets to the switching lines or to other X1 and X4
nets. The CIPs on the major diagonal allow data to
be transmitted from X1 nets to the switching lines
without being scrambled. The CIPs on the major
diagonal also allow unscrambled data to be passed
between the X1 and X4 nets.
In addition to the major diagonal CIPs for the X1
lines, other CIPs provide an alternative entry path
into the PLC in case the first one is already used.
The other CIPs are arrayed in two patterns, as
shown. Both of these patterns start with the main
diagonal, but the extra CIPs are arrayed on either a
parallel diagonal shifted by one or shifted by two
(modulo the size of the vertical bus (5)). This allows
any four application nets incident to the PLC corner
to be transferred to the five switching lines in that
corner. Many patterns of five nets can also be transferred.
24
F. These are the BIDI and BIDIH controllers. The 3state control signal can be disabled. They can be
configured as active-high or active-low independently of each other.
G. This set of CIPs allows a BIDI to get or put a signal
from one set of switching lines on each side. The
BIDIs can be accessed by the switching lines. These
CIPs allow a nibble of data to be routed though the
BIDIs and continue to a subsequent block. They also
provide an alternative routing resource to improve
routability.
H.These CIPs are used to take data from/to the BIDIs
to/from the XL lines. These CIPs have been optimized to allow the BIDI buffers to drive the large load
usually seen when using XL lines.
I. Each latch/FF can accept data: from an LUT output;
from a direct data input signal from general routing;
or, as in the case of PLCs located in the two rows
(columns) adjacent to PICs, directly from the pad. In
addition, the LUT outputs can bypass the latches/
FFs completely and output data on the general routing resources. The four inputs shown are used as
the direct input to the latches/FFs from general routing resources. If the LUT is in memory mode, the
four inputs WD[3:0] are the data input to the memory.
Lattice Semiconductor
HX4[3]
HX4[2]
HX4[1]
HX4[0]
HX1[3]
HX1[2]
HX1[1]
HX1[0]
HXH[3]
HXH[2]
HXH[1]
HXH[0]
HXL[3]
HXL[2]
HXL[1]
HXL[0]
INL[4]
INL[3]
INL[2]
INL[1]
INL[0]
A
U
D
VX4[7]
VX4[6]
VX4[5]
VX4[4]
VX4[4]
VX4[7]
VX4[6]
VX4[5]
CKL
CKR
CARRY_L
T
C
B
C
VX1[7]
VX1[6]
VX1[5]
VX1[4]
VX1[7]
VX1[6]
VX1[5]
VX1[4]
T
O
VXH[3]
VXH[2]
VXH[1]
VXH[0]
VXH[3]
VXH[2]
VXH[1]
VXH[0]
HX1[7]
HX1[6]
HX1[5]
HX1[4]
H
L
VXL[3]
VXL[2]
VXL[1]
VXL[0]
VXL[0]
VXL[3]
VXL[2]
VXL[1]
S
L
W
M
C
R
A
C
D
Q
G
A
B
D
U
B
P
F
E
SEE FIGURE 14
V
A
N
K
G
A
Q
O
A
M
O[4]
O[3]
O[2] J
O[1]
O[0]
COUT
CIN
WD[3]
WD[2]I
WD[1]
WD[0]
C0
B[4]
B[3]
B[2]
B[1]
B[0]
A[4]
A[3]
A[2]
A[1]
A[0]
CE
LSR
H
CK
N
U
R
A
C
PFU:R1C2
INT[4]
INT[3]
INT[2]
INT[1]
INT[0]
GSRN
INB[4]
INB[3]
INB[2]
INB[1]
INB[0]
HX4[7]
HX4[6]
HX4[5]
HX4[4]
CARRY_T
CARRY_B
A
L
HCK
VCK
L
C
T
S
B
C
C
T
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GSRN
CKB
CKT
GSRN
CKB
CKT
Lattice Semiconductor
VX1[3]
VX1[2]
VX1[1]
VX1[0]
VX1[3]
VX1[2]
VX1[1]
VX1[0]
D
U
HX4[2]
HX4[1]
HX4[0]
HX4[3]
HX1[3]
HX1[2]
HX1[1]
HX1[0]
HXH[3]
HXH[2]
HXH[1]
HXH[0]
HXL[0]
HXL[3]
HXL[2]
HXL[1]
INR[4]
INR[3]
INR[2]
INR[1]
INR[0]
CKL
CKR
CARRY_R
HX1[7]
HX1[6]
HX1[5]
HX1[4]
HX4[6]
HX4[5]
HX4[4]
HX4[7]
Data Sheet
November 2006
ORCA Series 2 FPGAs
Programmable Logic Cells (continued)
5-4479(F).r2
Figure 23. PLC Architecture
25
VX4[3]
VX4[2]
VX4[1]
VX4[0]
VX4[0]
VX4[3]
VX4[2]
VX4[1]
ORCA Series 2 FPGAs
Programmable Logic Cells (continued)
N. These are the 11 logic inputs to the LUT. The A[4:0]
inputs are provided into HLUTA, and the B[4:0]
inputs are provided into HLUTB. The C0 input
bypasses the main LUT and is used in the pfumux,
pfuxor, and pfunand functions (F5M, F5X modes).
Since this input bypasses the LUT, it can be used as
a fast path around the LUT, allowing the implementation of fast, wide combinatorial functions. The C0
input can be disabled or inverted.
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J. Any five of the eight output signals can be routed out
of the PLC. The eight signals are the four LUT outputs (F0, F1, F2, and F3) and the four latch/FF outputs (Q0, Q1, Q2, and Q3). This allows the user to
access all four latch/FF outputs, read the present
state and next state of a latch/FF, build a 4-bit shift
register, etc. Each of the outputs can drive any number of the five PFU outputs. The speed of a signal
can be increased by dividing its load among multiple
PFU output drivers.
Data Sheet
November 2006
K. These lines deliver the auxiliary signals’ clock
enable and set/reset to the latches/FFs. All four of
the latches/FFs share these signals.
L. This is the clock input to the latches/FFs. Any of the
horizontal and vertical XH or XL lines can drive the
clock of the PLC latches/FFs. Long-line drivers are
provided so that a PLC can drive one XL line in the
horizontal direction and one XL line in the vertical
direction. The XL lines in each direction exhibit the
same properties as X4 lines, except there are no
CIPs. The clock lines (CKL, CKR, CKT, and CKB)
and multiplexers/drivers are used to connect to the
XL lines for low-skew, low-delay global signals.
The long lines run the length or width of the PLC
array. They rotate to allow four PLCs in one row or
column to generate four independent global signals.
These lines do not have to be used for clock routing.
Any highly used application net can use this
resource, especially one requiring low skew.
M. These lines are used to route the fast carry signal to/
from the neighboring four PLCs. The carry-out
(COUT) of the PFU can also be routed out of the
PFU onto the fifth output (O4). The carry-in (CIN)
signal can also be supplied by the B4 input to the
PFU.
26
O. The XH lines run one-half the length (width) of the
array before being broken by a CIP.
P. The BIDIHs are used to access the XH lines.
Q. The BIDIH lines are used to connect the BIDIHs to
the XSW lines, the XH lines, or the BIDI lines.
R. These CIPs connect the BIDI lines and the BIDIH
lines.
S. These are clock lines (CKT, CKB, CKL, and CKR)
with the multiplexers and drivers to connect to the
XL lines.
T. These CIPs connect X1 lines which cross in each
corner to allow turns on the X1 lines without using
the XSW lines.
U. These CIPs connect X4 lines and xsw lines, allowing
nets that run a distance that is not divisible by four to
be routed more efficiently.
V. This routing structure allows any PFU output, including LUT and latch/FF outputs, to be placed on O4
and be routed onto the fast carry routing.
W.This routing structure allows the fast carry routing to
be routed onto the C0 PFU input.
Lattice Semiconductor
Data Sheet
November 2006
ORCA Series 2 FPGAs
Inputs
The programmable input/output cells (PICs) are
located along the perimeter of the device. Each PIC
interfaces to four bond pads and contains the necessary routing resources to provide an interface between
I/O pads and the PLCs. Each PIC is composed of input
buffers, output buffers, and routing resources as
described below. Table 6 provides an overview of the
programmable functions in an I/O cell. A is a simplified
diagram of the functionality of the OR2CxxA series I/O
cells, while B is a simplified functional diagram of the
OR2TxxA and OR2TxxB series I/O cells.
Each I/O can be configured to be either an input, an
output, or bidirectional I/O. Inputs for the OR2CxxA can
be configured as either TTL or CMOS compatible. The
I/O for the OR2TxxA and OR2TxxB series devices are
5 V tolerant, and will be described in a later section of
this data sheet. Pull-up or pull-down resistors are available on inputs to minimize power consumption.
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Programmable Input/Output Cells
Table 6. Input/Output Cell Options
Input
Input Levels
Option
Input Speed
Float Value
Direct-in to FF
TTL/CMOS (OR2CxxA only)
5 V PCI compliant (OR2CxxA only)
3.3 V PCI compliant (OR2TxxA only)
3.3 V and 5 V PCI compliant
(OR2TxxB only)
Fast/Delayed
Pull-up/Pull-down/None
Fast/Delayed
Output
Option
Output Drive
Output Speed
Output Source
Output Sense
3-State Sense
12 mA/6 mA or 6 mA/3 mA
Fast/Slewlim/Sinklim
FF Direct-out/General Routing
Active-high/-low
Active-high/-low (3-state)
Lattice Semiconductor
To allow zero hold time to PLC latches/FFs, the input
signal can be delayed. When enabled, this delay affects
the input signal driven to general routing, but does not
affect the clock input or the input lines that drive the
TRIDI buffers (used to drive onto XL, XH, BIDI, and
BIDIH lines).
A fast path from the input buffer to the clock lines is
also provided. Any one of the four I/O pads on any PIC
can be used to drive the clock line generated in that
PIC. This path cannot be delayed.
To reduce the time required to input a signal into the
FPGA, a dedicated path (PDIN) from the I/O pads to
the PFU flip-flops is provided. Like general input signals, this signal can be configured as normal or
delayed. The delayed direct input can be selected independently from the delayed general input.
Inputs should have transition times of less than 500 ns
and should not be left floating. If an input can float, a
pull-up or pull-down should be enabled. Floating inputs
increase power consumption, produce oscillations, and
increase system noise. The OR2CxxA inputs have a
typical hysteresis of approximately 280 mV (200 mV for
the OR2TxxA and OR2TxxB) to reduce sensitivity to
input noise. The PIC contains input circuitry which provides protection against latch-up and electrostatic discharge.
27
Data Sheet
November 2006
ORCA Series 2 FPGAs
Programmable Input/Output Cells
Outputs
(continued)
The PIC’s output drivers have programmable drive
capability and slew rates. Three propagation delays
(fast, slewlim, sinklim) are available on output drivers.
The sinklim mode has the longest propagation delay
and is used to minimize system noise and minimize
power consumption. The fast and slewlim modes allow
critical timing to be met.
VDD
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PULL-UP
DELAY
The drive current is 12 mA sink/6 mA source for the
slewlim and fast output speed selections and
6 mA sink/3 mA source for the sinklim output. Two adjacent outputs can be interconnected to increase the output sink current to 24 mA.
dintb, dinlr
in
TTL/CMOS
POLARITY
PAD
All outputs that are not speed critical should be configured as sinklim to minimize power and noise. The number of outputs that switch simultaneously in the same
direction should be limited to minimize ground bounce.
To minimize ground bounce problems, locate heavily
loaded output buffers near the ground pads. Ground
bounce is generally a function of the driving circuits,
traces on the PCB, and loads and is best determined
with a circuit simulation.
TRI
DOUT/OUT
SLEW RATE
POLARITY
PULL-DOWN
5-4591(F)
A. Simplified Diagram of OR2CxxA Programmable
I/O Cell (PIC)
VDD
PULL-UP
5 V Tolerant I/O (OR2TxxA)
DELAY
The I/O on the OR2TxxA series devices allow interconnection to both 3.3 V and 5 V device (selectable on a
per-pin basis) by way of special VDD5 pins that have
been added to the OR2TxxA devices. If any I/O on the
OR2TxxA device interfaces to a 5 V input, then all of
the VDD5 pins must be connected to the 5 V supply. If
no pins on the device interface to a 5 V signal, then the
VDD5 pins must be connected to the 3.3 V supply.
dintb, dinlr
in
PAD
Outputs can be inverted, and 3-state control signals
can be active-high or active-low. An open-drain output
may be obtained by using the same signal for driving
the output and 3-state signal nets so that the buffer output is enabled only by a low. At powerup, the output
drivers are in slewlim mode, and the input buffers are
configured as TTL-level compatible with a pull-up. If an
output is not to be driven in the selected configuration
mode, it is 3-stated.
POLARITY
TRI
DOUT/OUT
SLEW RATE
POLARITY
PULL-DOWN
If the VDD5 pins are disconnected (i.e., they are floating), the device will not be damaged; however, the
device may not operate properly until VDD5 is returned
to a proper voltage level. If the VDD5 pins are then
shorted to ground, a large current flow will develop, and
the device may be damaged.
5-4591.T(F)
B. Simplified Diagram of OR2TxxA/OR2TxxB
Programmable I/O Cell (PIC)
Figure 24. Simplified Diagrams
28
Lattice Semiconductor
Data Sheet
November 2006
Programmable Input/Output Cells
(continued)
the input buffer characteristics of the other device when
driven at the OR2TxxB output buffer voltage levels.
The OR2TxxB device has internal programmable pullups on the I/O buffers. These pull-up voltages are
always referenced to VDD and are always sufficient to
pull the input buffer of the OR2TxxB device to a high
state. The pin on the OR2TxxB device will be at a level
1.0 V below VDD (minimum of 2.0 V with a minimum
VDD of 3.0 V). This voltage is sufficient to pull the external pin up to a 3.3 V CMOS high-input level (1.8 V, min)
or a TTL high input level (2.0 V, min) in a 5 V tolerant
system. Therefore, in a 5 V tolerant system using 5 V
CMOS parts, care must be taken to evaluate the use of
these pull-ups to pull the pin of the OR2TxxB device to
a typical 5 V CMOS high-input level (2.2 V, min).
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Regardless of the power supply that the VDD5 pins are
connected to (5 V or 3.3 V), the OR2TxxA devices will
drive the pin to the 3.3 V levels when the output buffer
is enabled. If the other device being driven by the
OR2TxxA device has TTL-compatible inputs, then the
device will not dissipate much input buffer power. This
is because the OR2TxxA output is being driven to a
higher level than the TTL level required. If the other
device has a CMOS-compatible input, the amount of
input buffer power will also be small. Both of these
power values are dependent upon the input buffer characteristics of the other device when driven at the
OR2TxxA output buffer voltage levels.
ORCA Series 2 FPGAs
The 2TxxA device has internal programmable pull-ups
on the I/O buffers. These pull-up voltages are always
referenced to VDD. This means that the VDD5 voltage
has no effect on the value of the pull-up voltage at the
pad. This voltage level is always sufficient to pull the
input buffer of the 2TxxA device to a high state. The pin
on the 2TxxA device will be at a level 1.0 V below VDD
(minimum of 2.0 V with a minimum VDD of 3.0 V). This
voltage is sufficient to pull the external pin up to a 3.3 V
CMOS high-input level (1.8 V min) or a TTL high-input
level (2.0 V min) in a 5 V tolerant system, but it will
never pull the pad up to the VDD5 rail. Therefore, in a
5 V tolerant system using 5 V CMOS parts, care must
be taken to evaluate the use of these pull-ups to pull
the pin of the 2TxxA device to a typical 5 V CMOS
high-input level (2.2 V min).
For more information on 5 V tolerant I/Os, please see
ORCA® Series 5 V Tolerant I/Os Application Note
(AP99-027FPGA), May 1999.
5 V Tolerant I/O (OR2TxxB)
PCI Compliant I/O
The I/O on the OR2TxxB Series devices allows compliance with PCI local bus (Rev. 2.1) 5 V and 3.3 V signaling environments. The signaling environment used for
each input buffer can be selected on a per-pin basis.
The selection provides the appropriate I/O clamping
diodes for PCI compliance.
OR2TxxB devices have 5 V tolerant I/Os as previously
explained, but can optionally be selected on a pin-bypin basis to be PCI bus 3.3 V signaling compliant (PCI
bus 5 V signaling compliance occurs in 5 V tolerant
operation mode). Inputs may have a pull-up or pulldown resistor selected on an input for signal stabilization and power management. Input signals in a PIO
can be passed to PIC routing on any of three paths,
two general signal paths into PIC routing, and/or a fast
route into the clock routing system.
OR2TxxA series devices are only compliant in 3.3 V
PCI Local Bus (Rev 2.1) signalling environments.
OR2CxxA devices are only compliant in 5 V PCI Local
Bus (Rev 2.1) signalling environments.
The I/O on the OR2TxxB Series devices allow interconnection to both 3.3 V and 5 V device (selectable on a
per-pin basis). Unlike the OR2TxxA family, when interfaceing into a 5 V signal, it no longer requires a VDD5
supply.
The OR2TxxB devices will drive the pin to the 3.3 V levels when the output buffer is enabled. If the other
device being driven by the OR2TxxB device has TTLcompatible inputs, then the device will not dissipate
much input buffer power. This is because the OR2TxxB
output is being driven to a higher level than the TTL
level required. If the other device has a CMOS-compatible input, the amount of input buffer power will also be
small. Both of these power values are dependent upon
Lattice Semiconductor
29
Data Sheet
November 2006
ORCA Series 2 FPGAs
Programmable Input/Output Cells
sides are left (L), right (R), top (T), and bottom (B). The
individual I/O pad is indicated by a single letter (either
A, B, C, or D) placed at the end of the PIC name. As an
example, PL10A indicates a pad located on the left
side of the array in the tenth row.
(continued)
PIC Routing Resources
Each PIC has four pads and each pad can be configured as an input, an output (3-statable), a direct output,
or a bidirectional I/O. When the pads are used as
inputs, the external signals are provided to the internal
circuitry at IN[3:0]. When the pads are used to provide
direct inputs to the latches/FFs, they are connected
through DIN[3:0]. When the pads are used as outputs,
the internal signals connect to the pads through
OUT[3:0]. When the pads are used as direct outputs,
the output from the latches/flip-flops in the PLCs to the
PIC is designated DOUT[3:0]. When the outputs are
3-statable, the 3-state enable signals are TS[3:0].
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The PIC routing is designed to route 4-bit wide buses
efficiently. For example, any four consecutive I/O pads
can have both their input and output signals routed into
one PLC. Using only PIC routing, either the input or
output data can be routed to/from a single PLC from/to
any eight pads in a row, as in Figure 25.
The connections between PLCs and the I/O pad are
provided by two basic types of routing resources.
These are routing resources internal to the PIC and
routing resources used for PIC-PLC connection.
Figure 26 and Figure 27 show a high-level and detailed
view of these routing resources, respectively.
Routing Resources Internal to the PIC
PXL PXH PX2 PX1
2
4
4
4
2
4
PAD D
I/O3
PAD C
I/O2
PAD B
I/O1
PAD A
I/O0
4
4
5
4
PIC
SWITCHING
MATRIX
4
4
4
4
4
4
4
4
2
4
4
CK
PLC X4
PLC X1
PLC PSW
PLC DOUT
PLC XL
PLC XH
PLC X1
PLC X4
PLC DIN
4
PXL PXH PX2 PX1
5-4504(F)
Figure 25. Simplified PIC Routing Diagram
The PIC’s name is represented by a two-letter designation to indicate on which side of the device it is located
followed by a number to indicate in which row or column it is located. The first letter, P, designates that the
cell is a PIC and not a PLC. The second letter indicates
the side of the array where the PIC is located. The four
30
For inter-PIC routing, the PIC contains 14 lines used to
route signals around the perimeter of the FPGA. Figure
25 shows these lines running vertically for a PIC
located on the left side. Figure 26 shows the lines running horizontally for a PIC located at the top of the
FPGA.
PXL Lines. Each PIC has two PXL lines, labeled
PXL[1:0]. Like the XL lines of the PLC, the PXL lines
span the entire edge of the FPGA.
PXH Lines. Each PIC has four PXH lines, labeled
PXH[3:0]. Like the XH lines of the PLC, the PXH lines
span half the edge of the FPGA.
PX2 Lines. There are four PX2 lines in each PIC,
labeled PX2[3:0]. The PX2 lines pass through two adjacent PICs before being broken. These are used to
route nets around the perimeter equally a distance of
two or more PICs.
PX1 Lines. Each PIC has four PX1 lines, labeled
PX1[3:0]. The PX1 lines are one PIC long and are
extended to adjacent PICs by enabling CIPs.
Lattice Semiconductor
Data Sheet
November 2006
Programmable Input/Output Cells
(continued)
PIC Architectural Description
I. The four TRIDIH buffers allow connections from the
pads to the PLC XH lines. The TRIDIHs also allow
connections between the PLC XH lines and the
pBIDIH lines, which are described in K below.
J. The PBIDI lines (bidi[3:0]) connect the PXL lines,
PXH lines, and the PX1 lines. These are bidirectional in that the path can be from the PXL, PXH, or
PX1 lines to the XL lines, or from the XL lines to the
PXL, PXH, or PX1 lines.
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The PIC architecture given in Figure 26 is described
using the following letter references. The figure depicts
a PIC at the top of the array, so inter-PIC routing is horizontal and the indirect PIC-PLC routing is horizontal to
vertical. In some cases, letters are provided in more
than one location to indicate the path of a line.
ORCA Series 2 FPGAs
A. As in the PLCs, the PIC contains a set of lines which
run the length (width) of the array. The PXL lines
connect in the corners of the array to other PXL
lines. The PXL lines also connect to the PIC BIDI,
PIC BIDIH, and LLDRV lines. As in the PLC XL lines,
the PXH lines twist as they propagate through the
PICs.
B. As in the PLCs, the PIC contains a set of lines which
run one-half the length (width) of the array. The PXH
lines connect in the corners and in the middle of the
array perimeter to other PXH lines. The PXH lines
also connect to the PIC BIDI, PIC BIDIH, and
LLDRV lines. As in the PLC XH lines, the PXH lines
do not twist as they propagate through the PICs.
C. The PX2[3:0] lines span a length of two PICs before
intersecting with a CIP. The CIP allows the length of
a path using PX2 lines to be extended two PICs.
D. The PX1[3:0] lines span a single PIC before intersecting with a CIP. The CIP allows the length of a
path using PX1 lines to be extended by one PIC.
E. These are four dedicated direct output lines connected to the output buffers. The DOUT[3:0] signals
go directly from a PLC latch/FF to an output buffer,
minimizing the latch/FF to pad propagation delay.
F. This is a direct path from the input pad to the PLC
latch/flip-flops in the two rows (columns) adjacent to
PICs. This input allows a reduced setup time. Direct
inputs from the top and bottom PIC rows are
PDINTB[3:0]. Direct inputs from the left and right
PIC columns are PDINLR[3:0].
G. The OUT[3:0], TS[3:0], and IN[3:0] signals for each I/
O pad can be routed directly to the adjacent PLC’s
switching lines.
K. The pBIDIH lines (BIDIH[3:0]) connect the PXL
lines, PXH lines, and the PX1 lines. These are bidirectional in that the path can be from the PXL, PXH,
or PX1 lines to the XH lines, or from the XH lines to
the PXL, PXH, or PX1 lines.
L. The LLIN[3:0] lines provide a fast connection from
the I/O pads to the XL and XH lines.
M.This set of CIPs allows the eight X1 lines (four on
each side) of the PLC perpendicular to the PIC to be
connected to either the PX1 or PX2 lines in the PIC.
N. This set of CIPs allows the eight X4 lines (four on
each side) of the PLC perpendicular to the PIC to be
connected to the PX1 lines. This allows fast access
to/from the I/O pads from/to the PLCs.
O. All four of the PLC X4 lines in a group connect to all
four of the PLC X4 lines in the adjacent PLC through
a CIP. (This differs from the ORCA 1C Series in
which two of the X4 lines in adjacent PLCs are
directly connected without any CIPs.)
P. The long-line driver (LLDRV) line can be driven by
the XSW4 switching line of the adjacent PLC. To provide connectivity to the pads, the LLDRV line can
also connect to any of the four PXH or to one of the
PXL lines. The 3-state enable (TS[i]) for all four I/O
pads can be driven by XSW4, PXH, or PXL lines.
Q. For fast clock routing, one of the four I/O pads in
each PIC can be selected to be driven onto a dedicated clock line. The clock line spans the length
(width) of the PLC array. This dedicated clock line is
typically used as a clock spine. In the PLCs, the
spine is connected to an XL line to provide a clock
branch in the perpendicular direction. Since there is
another clock line in the PIC on the opposite side of
the array, only one of the I/O pads in a given row
(column) can be used to generate a global signal in
this manner, if all PLCs are driven by the signal.
H. The four TRIDI buffers allow connections from the
pads to the PLC XL lines. The TRIDIs also allow
connections between the PLC XL lines and the
PBIDI lines, which are described in J below.
Lattice Semiconductor
31
Data Sheet
November 2006
ORCA Series 2 FPGAs
Programmable Input/Output Cells (continued)
PA
DT
PB
DT
PC
PD
DT
DT
DOUT3
TS3
OUT3
IN3
DOUT2
TS2
OUT2
IN2
DOUT1
TS1
OUT1
IN1
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DOUT0
TS0
OUT0
IN0
PIC DETAIL
BIDI3
BIDI2
BIDI1
BIDI0
K
BIDIH3
BIDIH2
BIDIH1
BIDIH0
F
Q
J
PXL[1]
A PXL[0]
PXL[0]
PXL[1] A
PXH[0]
PXH[1]
B PXH[2]
PXH[0]
PXH[1]
PXH[2] B
PXH[3]
PXH[3]
P
PX2[2]
PX2[3]
C PX2[0]
PX2[1]
PX2[0]
PX2[1]
PX2[2] C
PX2[3]
C
M
PX1[0]
PX1[1]
D PX1[2]
PX1[3]
M
N
LLIN3
LLIN2
LLIN1
LLIN0
D
PX1[0]
PX1[1]
PX1[2] D
PX1[3]
N
O
I
O
P
LLDRV
P
L
G
VX4[3]
VX4[2]
VX4[1]
VX4[0]
XSW[4]
XSW[3]
XSW[2]
XSW[1]
XSW[0]
E
CKT
DOUT[3]
DOUT[2]
DOUT[1]
DOUT[0]
F
VX1[3]
VX1[2]
VX1[1]
VX1[0]
PDINTB[3]
PDINTB[2]
PDINTB[1]
PDINTB[0]
VXL[3]
VXL[2]
VXL[1]
VXL[0]
VXH[3]
VXH[2]
VXH[1]
VXH[0]
VX1[7]
VX1[6]
VX1[5]
VX1[4]
VX4[7]
VX4[6]
VX4[5]
VX4[4]
Q
5-2843(F).r8
Figure 26. PIC Architecture
PLC-PIC Routing Resources
nections are also available between the PIC PX2 lines
and the PLC X1 lines.
There is no direct connection between the inter-PIC
lines and the PLC lines. All connections to/from the
PLC must be done through the connecting lines which
are perpendicular to the lines in the PIC. The use of
perpendicular and parallel lines will be clearer if the
PLC and PIC architectures (Figure 23 and Figure 26)
are placed side by side. Twenty-nine lines in the PLC
can be connected to the 15 lines in the PIC.
There are eight tridirectional (four TRIDI/four TRIDIH)
buffers in each PIC; they can do the following:
Multiple connections between the PIC PX1 lines and
the PLC X1 lines are available. These allow buses
placed in any arbitrary order on the I/O pads to be
unscrambled when placed on the PLC X1 lines. Con-
32
■
Drive a signal from an I/O pad onto one of the adjacent PLC’s XL or XH lines
■
Drive a signal from an I/O pad onto one of the two
PXL or four PXH lines in the PIC
■
Drive a signal from the PLC XL or XH lines onto one
of the two PXL or four PXH lines in the PIC
■
Drive a signal from the PIC PXL or PXH lines onto
one of the PLC XL or XH lines
Lattice Semiconductor
Data Sheet
November 2006
ORCA Series 2 FPGAs
Programmable Input/Output Cells
(continued)
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Figure 27 shows paths to and from pads and the use of MUX CIPs to connect lines. Detail A shows six MUX CIPs
for the pad P0 used to construct the net for the 3-state signal. In the MUX CIP, one of six lines is connected to a line
to form the net. In this case, the ts0 signal can be driven by either of the two PXLs, PX1[0], PX1[1], XSW[0], or the
LLDRV lines. Detail B shows the four MUX CIPs used to drive the P1 output. The source line for OUT1 is either
XSW[1], PX1[1], PX1[3], or PX2[2].
PD
DT
DT
DOUT3
TS3
OUT3
IN3
DT
PC
DOUT2
TS2
OUT2
IN2
DOUT0
TS0
OUT0
IN0
DT
PB
DOUT1
TS1
OUT1
IN1
PA
PXL[1]
PXL[0]
PXL[1]
PXL[0]
PXH[0]
PXH[1]
PXH[2]
PXH[3]
PXH[0]
PXH[1]
PXH[2]
PXH[3]
PX2[2]
PX2[3]
PX2[0]
PX2[1]
PX2[2]
PX2[3]
PX2[0]
PX2[1]
PX1[0]
PX1[1]
PX1[2]
PX1[3]
PX1[0]
PX1[1]
PX1[2]
PX1[3]
XSW[0]
XSW[1]
XSW[2]
XSW[3]
LLDRV
A
B
DOUT[0]
DOUT[1]
DOUT[2]
DOUT[3]
5-2843.BL(F).2C.r3
Figure 27. PIC Detail
Lattice Semiconductor
33
Data Sheet
November 2006
ORCA Series 2 FPGAs
Interquad Routing
The interquad routing connects XL and XH lines. It
does not affect local routing (XSW, X1, X4, fast carry),
so local routing is the same, whether PLC-PLC connections cross quadrants or not. There are no connections to the local lines in the interquad blocks. Figure 28
presents a (not to scale) view of interquad routing.
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In all the ORCA Series 2 devices, the PLC array is split
into four equal quadrants. In between these quadrants,
routing has been added to route signals between the
quadrants, especially to the quadrant in the opposite
corner. The two types of interquad blocks, vertical and
horizontal, are pitch matched to PICs. Vertical interquad blocks (vIQ) run between quadrants on the left
and right, while horizontal interquad blocks (hIQ) run
between top and bottom quadrants. Since hIQ and vIQ
blocks have the same logic, only the hIQ block is
described below.
TMID
vIQ3[4:0]
vIQ2[4:0]
vIQ1[4:0]
vIQ0[4:0]
5 5 5 5
SEE
DETAIL IN
FIGURE 29
5
LMID
5
5
5
hIQ3[4:0]
hIQ2[4:0]
RMID
hIQ1[4:0]
hIQ0[4:0]
BMID
5-4538(F)
Figure 28. Interquad Routing
34
Lattice Semiconductor
Data Sheet
November 2006
ORCA Series 2 FPGAs
Interquad Routing (continued)
VX4[3]
VX4[2]
VX4[1]
VX4[0]
VX1[3]
VX1[2]
VX1[1]
VX1[0]
CKB
CKT
CARRY
VXL[3]
VXL[2]
VXL[1]
VXL[0]
VXH[3]
VXH[2]
VXH[1]
VXH[0]
VX1[7]
VX1[6]
VX1[5]
VX1[4]
VX4[7]
VX4[6]
VX4[5]
VX4[4]
In the hIQ block, the 20 hIQ lines span the array in a
horizontal direction. The 20 hIQ lines consist of four
INB[4]
INB[3]
INB[2]
INB[1]
INB[0]
GSRN
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In the hIQ block in Figure 29, the XH lines from one
quadrant connect through a CIP to its counterpart in
the opposite quadrant, creating a path that spans the
PLC array. Since a passive CIP is used to connect the
two XH lines, a 3-state signal can be routed on the two
XH lines in the opposite quadrants, and then they can
be connected through this CIP.
groups of five lines each. To effectively route nibblewide buses, each of these sets of five lines can connect
to only one of the bits of the nibble for both the XH and
XL. For example, hIQ0 lines can only connect to the
XH0 and XL0 lines, and the hIQ1 lines can connect
only to the XH1 and XL1 lines, etc. Buffers are provided
for routing signals from the XH and XL lines onto the
hIQ lines and from the hIQ lines onto the XH and XL
lines. Therefore, a connection from one quadrant to
another can be made using only two XH lines (one in
each quadrant) and one interquad line.
VX4[3]
VX4[2]
VX4[1]
VX4[0]
VX1[3]
VX1[2]
VX1[1]
VX1[0]
CKB
CKT
INT[4]
INT[3]
INT[2]
INT[1]
INT[0]
GSRN
CARRY
VXL[3]
VXL[2]
VXL[1]
VXL[0]
hIQ1[4]
hIQ1[3]
hIQ1[2]
hIQ1[1]
hIQ1[0]
hIQ0[4]
hIQ0[3]
hIQ0[2]
hIQ0[1]
hIQ0[0]
VXH[3]
VXH[2]
VXH[1]
VXH[0]
hIQ1[4]
hIQ1[3]
hIQ1[2]
hIQ1[1]
hIQ1[0]
hIQ0[4]
hIQ0[3]
hIQ0[2]
hIQ0[1]
hIQ0[0]
VX1[7]
VX1[6]
VX1[5]
VX1[4]
hIQ3[4]
hIQ3[3]
hIQ3[2]
hIQ3[1]
hIQ3[0]
hIQ2[4]
hIQ2[3]
hIQ2[2]
hIQ2[1]
hIQ2[0]
VX4[7]
VX4[6]
VX4[5]
VX4[4]
hIQ3[4]
hIQ3[3]
hIQ3[2]
hIQ3[1]
hIQ3[0]
hIQ2[4]
hIQ2[3]
hIQ2[2]
hIQ2[1]
hIQ2[0]
5-4537(F).r3
Figure 29. hIQ Block Detail
Lattice Semiconductor
35
Data Sheet
November 2006
ORCA Series 2 FPGAs
Interquad Routing (continued)
Subquad Routing (OR2C40A/OR2T40A Only)
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In the ORCA OR2C40A/OR2T40A/OR2T40B, each
quadrant of the device is split into smaller arrays of
PLCs called subquads. Each of these subquads is
made of a 4 x 4 array of PLCs (for a total of 16 per subquadrant), except at the outer edges of array, which
have less than 16 PLCs per subquad. New routing
resources, called subquad lines, have been added
between each adjacent pair of subquads to enhance
the routability of the device. A portion of the center of
the OR2C40A and OR2T40A array is shown in Figure
30, including the subquad blocks containing a 4 x 4
array of PLCs, the interquad routing lines, and the subquad routing lines.
All of the inter-PLC routing resources discussed previously continue to be routed between a PLC and its
adjacent PLC, even if the two adjacent PLCs are in different subquad blocks. Since the PLC routing has not
been modified for the OR2C40A/OR2T40A architectures, this means that all of the same routing connections are possible for these devices as for any other
ORCA 2C series device. In this way, both the
OR2C40A and OR2T40A/OR2T40B are upwardly compatible when compared with the ATT2Cxx series
devices. As the inter-PLC routing runs between subquad blocks, it crosses the new subquad lines. When
this happens, CIPs are used to connect the subquad
lines to the X4 and/or the XH lines which lie along the
other axis of the PLC array.
SEE DETAIL
IN FIGURES 25
AND 26
SUBQUAD
(4 x 4 PLCs)
SUBQUAD
(4 x 4 PLCs)
SUBQUAD
(4 x 4 PLCs)
SUBQUAD
(4 x 4 PLCs)
SUBQUAD
(4 x 4 PLCs)
SUBQUAD
(4 x 4 PLCs)
SUBQUAD
(4 x 4 PLCs)
SUBQUAD
(4 x 4 PLCs)
HORIZONTAL
INTERQUAD
ROUTING
(hIQ)
SUBQUAD
(4 x 4 PLCs)
SUBQUAD
(4 x 4 PLCs)
SUBQUAD
(4 x 4 PLCs)
SUBQUAD
(4 x 4 PLCs)
HORIZONTAL
SUBQUAD
ROUTING
(HSUB)
SUBQUAD
(4 x 4 PLCs)
SUBQUAD
(4 x 4 PLCs)
VERTICAL
SUBQUAD
ROUTING
(VSUB)
SUBQUAD
(4 x 4 PLCs)
SUBQUAD
(4 x 4 PLCs)
VERTICAL
INTERQUAD
ROUTING
(vIQ)
5-4200(F).r5
Figure 30. Subquad Blocks and Subquad Routing
36
Lattice Semiconductor
Data Sheet
November 2006
ORCA Series 2 FPGAs
subquad blocks, four of the blocks shown in Figure 31
are used, one for each pair of vertical PLCs.
VX4[3]
VX4[2]
VX4[1]
VX4[0]
VX4[3]
VX4[2]
VX4[1]
VX4[0]
VX4[7]
VX4[6]
VX4[5]
VX4[4]
Interquad Routing (continued)
HSUB[11]
HSUB[10]
HSUB[9]
HSUB[8]
HSUB[7]
HSUB[6]
HSUB[5]
HSUB[4]
HSUB[7]
HSUB[6]
HSUB[5]
HSUB[4]
HSUB[3]
HSUB[2]
HSUB[1]
HSUB[0]
HSUB[3]
HSUB[2]
HSUB[1]
HSUB[0]
A
The new subquad lines travel a length of eight PLCs
(seven PLCs on the outside edge) before they are broken. Unlike other inter-PLC lines, they cannot be connected end-to-end. As shown in Figure 30, some of the
horizontal (vertical) subquad lines have connectivity to
the subquad to the left of (above) the current subquad,
while others have connectivity to the subquad to the
right (below). This allows connections to/from the current subquad from/to the PLCs in all subquads that surround it.
Between all subquads, including in the center of the
array, there are three groups of subquad lines where
each group contains four lines. Figure 31 shows the
connectivity of these three groups of subquad lines
(HSUB) to the VX4 and VXH lines running between a
vertical pair of PLCs. Between each vertical pair of
Lattice Semiconductor
VX4[3]
VX4[2]
VX4[1]
VX4[0]
HSUB[11]
HSUB[10]
HSUB[9]
HSUB[8]
A
HSUB[15]
HSUB[14]
HSUB[13]
HSUB[12]
D
HSUB[7]
HSUB[6]
HSUB[5]
HSUB[4]
HSUB[7]
HSUB[6]
HSUB[5]
HSUB[4]
C
HSUB[3]
HSUB[2]
HSUB[1]
HSUB[0]
HSUB[3]
HSUB[2]
HSUB[1]
HSUB[0]
B
HSUB[11]
HSUB[10]
HSUB[9]
HSUB[8]
HSUB[15]
HSUB[14]
HSUB[13]
HSUB[12]
VX4[3]
VX4[2]
VX4[1]
VX4[0]
The X4 and XH lines make the only connections to the
subquad lines; therefore, the array remains symmetrical and homogeneous. Since each subquad is made
from a 4 x 4 array of PLCs, the distance between sets
of subquad lines is four PLCs, which is also the distance between the breaks of the X4 lines. Therefore,
each X4 line will cross exactly one set of subquad lines.
Since all X4 lines make the same connections to the
subquad lines that they cross, all X4 lines in the array
have the same connectivity, and the symmetry of the
routing is preserved. Since all XH lines cross the same
number of subquad blocks, the symmetry is maintained
for the XH lines as well.
VX4[3]
VX4[2]
VX4[1]
VX4[0]
Figure 31. Horizontal Subquad Routing
Connectivity
VX4[3]
VX4[2]
VX4[1]
VX4[0]
5-4201(F).r4
VX4[7]
VX4[6]
VX4[5]
VX4[4]
B
At the center row and column of each quadrant, a
fourth group of subquad lines has been added. These
subquad lines only have connectivity to the XH lines.
The XH lines are also broken at this point, which
means that each XH line travels one-half of the quadrant (i.e., one-quarter of the device) before it is broken
by a CIP. Since the XH lines can be connected end-toend, the resulting line can be either one-quarter, onehalf, three-quarters, or the entire length of the array.
The connectivity of the XH lines and this fourth group of
subquad lines, indicated as D, are detailed in Figure
32. Again, the connectivity for the vertical subquad
routing (VSUB) is the same as the horizontal subquad
routing, when rotated onto the other axis.
VX4[7]
VX4[6]
VX4[5]
VX4[4]
C
VX4[3]
VX4[2]
VX4[1]
VX4[0]
VX4[3]
VX4[2]
VX4[1]
VX4[0]
VX4[7]
VX4[6]
VX4[5]
VX4[4]
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HSUB[11]
HSUB[10]
HSUB[9]
HSUB[8]
The first two groups, depicted as A and B, have connectivity to only one of the two sets of X4 lines between
pairs of PLCs. Since they are very lightly loaded, they
are very fast. The third group, C, connects to both
groups of X4 lines between pairs of PLCs, as well as all
of the XH lines between pairs of PLCs, providing high
flexibility. The connectivity for the vertical subquad routing (Vsub) is the same as described above for the horizontal subquad routing, when rotated onto the other
axis.
5-4202(F).r3
Figure 32. Horizontal Subquad Routing
Connectivity (Half Quad)
37
Data Sheet
November 2006
ORCA Series 2 FPGAs
Interquad Routing (continued)
PIC Interquad (MID) Routing
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Between the PICs in each quadrant, there is also connectivity between the PIC routing and the interquad
routing. These blocks are called LMID (left), TMID
(top), RMID (right), and BMID (bottom). The TMID routing is shown in Figure 33. As with the hIQ and vIQ
blocks, the only connectivity to the PIC routing is to the
global PXH and PXL lines.
The PXH lines from the one quadrant can be connected through a CIP to its counterpart in the opposite
quadrant, providing a path that spans the array of PICs.
Since a passive CIP is used to connect the two PXH
lines, a 3-state signal can be routed on the two PXH
lines in the opposite quadrants, and then connected
through this CIP. As with the hIQ and vIQ blocks, CIPs
and buffers allow nibble-wide connections between the
interquad lines, the XH lines, and the XL lines.
PXH[3]
PXH[2]
PXH[1]
PXH[0]
PX4[3]
PX4[2]
PX4[1]
PX4[0]
PX4[3]
PX4[2]
PX4[1]
PX4[0]
PX1[3]
PX1[2]
PX1[1]
PX1[0]
PX1[3]
PX1[2]
PX1[1]
PX1[0]
HX4[3]
HX4[2]
HX4[1]
HX4[0]
HX4[3]
HX4[2]
HX4[1]
HX4[0]
VIQ1[0]
VIQ3[0]
PXH[3]
PXH[2]
PXH[1]
PXH[0]
VIQ2[0]
PXL[1]
PXL[0]
VIQ0[0]
PXL[1]
PXL[0]
5-4201(F).r4
Figure 33. Top (TMID) Routing
38
Lattice Semiconductor
Data Sheet
November 2006
ORCA Series 2 FPGAs
Programmable Corner Cells
Clock Distribution Network
Programmable Routing
The ORCA Series 2 clock distribution schemes use primary and secondary clocks. This provides the system
designer with additional flexibility in assigning clock
input pins.
One advantage is that board-level clock traces routed
to the FPGA are shorter. On a PC board, the added
length of high-speed clock traces routed to dedicated
clock input pins can significantly increase the parasitic
impedances. The primary advantage of the ORCA
clock distribution is the availability of a large number of
clocks, since all I/O pins are configurable as clocks.
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The programmable corner cell (PCC) contains the circuitry to connect the routing of the two PICs in each
corner of the device. The PIC PX1 and PX2 lines are
directly connected together from one PIC to another.
The PIC PXL lines are connected from one block to
another through tridirectional buffers. Four CIPs in
each corner connect the four PXH lines from each side
of the device.
Special-Purpose Functions
In addition to routing functions, special-purpose functions are located in each FPGA corner. The upper-left
PCC contains connections to the boundary-scan logic.
The upper-right PCC contains connections to the readback logic and the connectivity to the global 3-state
signal (TS_ALL). The lower-left PCC contains connections to the internal oscillator.
The lower-right PCC contains connections to the startup and global reset logic. During configuration, the
RESET input pad always initiates a configuration abort,
as described in the FPGA States of Operation section.
After configuration, the global set/reset signal (GSRN)
can either be disabled (the default), directly connected
to the RESET input pad, or sourced by a lower-right
corner signal. If the RESET input pad is not used as a
global reset after configuration, this pad can be used
as a normal input pad. During start-up, the release of
the global set/reset, the release of the I/Os, and the
release of the external DONE signal can each be timed
individually based upon the start-up clock. The start-up
clock can come from CCLK or it can be routed into the
start-up block using the lower-right corner routing
resources. More details on start-up can be found in the
FPGA States of Operation section.
Lattice Semiconductor
Primary Clock
The primary clock distribution is shown in Figure 34. If
the clock signal is from an I/O pad, it can be driven onto
a clock line. The clock lines do not provide clock signals
directly to the PFU; they act as clock spines from which
clocks are branched to XL lines. The XL lines then feed
the clocks to PFUs. A multiplexer in each PLC is used
to transition from the clock spine to the branch.
For a clock spine in the horizontal direction, the inputs
into the multiplexer are the two lines from the left and
right PICs (CKL and CKR) and the local clock line from
the perpendicular direction (HCK). This signal is then
buffered and driven onto one of the vertical XL lines,
forming the branches. The same structure is used for a
clock spine in the vertical direction. In this case, the
multiplexer selects from lines from the top and bottom
PICs (CKT, CKB, and VCK) and drives the signal onto
one of the horizontal XL lines.
Figure 34 illustrates the distribution of the low-skew primary clock to a large number of loads using a main
spine and branches. Each row (column) has two dedicated clock lines originating from PICs on opposite
sides of the array. The clock is input from the pads to
the dedicated clock line CKT to form the clock spine
(see Figure 34, Detail A). From the clock spine, net
branches are routed using horizontal XL lines and then
PLC clock inputs are tapped from the XL lines, as
shown in Figure 34, Detail B.
39
Data Sheet
November 2006
ORCA Series 2 FPGAs
Clock Distribution Network (continued)
Secondary Clock
There are times when a primary clock is either not
available or not desired, and a secondary clock is
needed. For example:
SEE DETAIL A
CLK PIN
SEE DETAIL B
Only one input pad per PIC can be placed on the
clock routing. If a second input pad in a given PIC
requires global signal routing, a secondary clock
route must be used.
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■
CLOCK
BRANCHES
■
Since there is only one branch driver in each PLC for
either direction (vertical and horizontal), both clock
lines in a particular row or column (CKL and CKR, for
example) cannot drive a branch. Therefore, two
clocks should not be placed into I/O pads in PICs on
the opposite sides of the same row or column if global clocks are to be used.
■
Since the clock lines can only be driven from input
pads, internally generated clocks should use secondary clock routing.
CLOCK SPINE
Figure 35 illustrates the secondary clock distribution. If
the clock signal originates from either the left or right
side of the FPGA, it can be routed through the TRIDI
buffers in the PIC onto one of the adjacent PLC’s horizontal XL lines. If the clock signal originates from the
top or bottom of the FPGA, the vertical XL lines are
used for routing. In either case, an XL line is used as
the clock spine. In the same manner, if a clock is only
going to be used in one quadrant, the XH lines can be
used as a clock spine. The routing of the clock spine
from the input pads to the VXL (VXH) using the BIDIs
(BIDIHs) is shown in Figure 35, Detail A.
PIC PT8
A
DT
B
DT
C
D
DT
DT
PLC R1C8
CLOCK SPINE
PLC R18C8
DETAIL A
HCK
HCK
R7C7
R7C8
CKT
In each PLC, a low-skew connection through a longline driver can be used to connect a horizontal XL line
to a vertical XL line or vice versa. As shown in Figure
35, Detail B, this is used to route the branches from the
clock spine. If the clock spine is a vertical XL line, then
the branches are horizontal XL lines and vice versa.
The clock is then routed into each PLC from the XL line
clock branches.
To minimize skew, the PLC clock input for all PLCs
must be connected to the branch XL lines, not the
spine XL line. Even in PLCs where the clock is routed
from the spine to the branches, the clock should be
routed back into the PLC from the clock branch.
HXL
HXL
CLOCK
BRANCH
If the clock is to drive only a limited number of loads,
the PFUs can be connected directly to the clock spine.
In this case, all flip-flops driven by the clock must be
located in the same row or column.
CLOCK
SPINES
DETAIL B
CKB
CKT
5-4480(F).r3
Figure 34. Primary Clock Distribution
40
Lattice Semiconductor
Data Sheet
November 2006
ORCA Series 2 FPGAs
Clock Distribution Network (continued)
The following equation can be used to determine pin
names:
Alternatively, the clock can be routed from the spine to
the branches by using the BIDIs instead of the long-line
drivers. This results in added delay in the clock net, but
the clock skew is approximately equal to the clock
routed using the long-line drivers. This method can be
used to create a clock that is used in only one quadrant. The XH lines act as a clock spine, which is then
routed to perpendicular XH lines (the branches) using
the BIDIHs.
Pad number = P[RL][TB]n ± (i x 4)[A – D]
Where i = 1—8, and n is the current PIC number.
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For more information, please refer to Utilizing the
ORCA® OR2C/TxxA Clock Distribution Network Application Note (AP97-055FPGA).
SEE DETAIL A
SEE DETAIL B
CLK PIN
Clock signals, such as the output of a counter, can also
be generated in PLCs and routed onto an XL line,
which then acts as a clock spine. Although the clock
can be generated in any PLC, it is recommended that
the clock be located as close to the center of the FPGA
as possible to minimize clock skew.
CLOCK
BRANCHES
Selecting Clock Input Pins
Any user I/O pin on an ORCA FPGA can be used as a
very fast, low-skew clock input. Choosing the first clock
pin is completely arbitrary, but using a pin that is near
the center of an edge of the device (as shown in Figures 34 and 35) will provide the lowest skew clock network. The pin-to-pin timing numbers in the Timing
Characteristics section of this data book assume that
the clock pin is in one of the four PICs at the center of
any side of the device.
CLOCK SPINE
PA
DT
PB
DT
PC
DT
PD
DT
If it is desired to use a pin for one of the first eight
clocks that is not within the center four PICs of any side
of the device and primary clock routing is desired, the
pad names (see Pin Information) of the two clock pins
on the top or bottom of the device cannot be a multiplier of four PICs away. The same rule applies to clock
pins on the left or right side of the device.
VXL[3]
VXL[2]
VXL[1]
VXL[0]
These rules should be followed iteratively until a total of
eight clocks (or other global signals) have been
selected: four from the left/right sides of the device, and
four from the top/bottom sides of the device. If more
than eight clocks are needed, then select another pin
outside the center four PICs to use primary-clock routing, use secondary clock routing for any pin, or use
local clock routing.
VXH[3]
VXH[2]
VXH[1]
VXH[0]
Once the first clock pin has been chosen, there are
only two sets of pins (within the center four PICs on
each side of the device) that should not be chosen as
the second clock pin: a pin from the same PIC, and/or a
pin from the PIC on the exact opposite edge of the die
(i.e., if a pin from a PIC on the top edge is chosen for
the first clock, the same PIC on the bottom edge should
not be chosen for the second clock).
DETAIL A
HCK
VCK
PFU
DETAIL B
5-4481(F).r2
Figure 35. Secondary Clock Distribution
Lattice Semiconductor
41
Data Sheet
November 2006
ORCA Series 2 FPGAs
FPGA States of Operation
operating voltage (4.75 V for OR2CxxA commercial
devices and 3.0 V for OR2TxxA/B devices).
Prior to becoming operational, the FPGA goes through a
sequence of states, including initialization, configuration,
and start-up. Figure 36 outlines these three FPGA
states.
At the end of initialization, the default configuration
option is that the configuration RAM is written to a low
state. This prevents shorts prior to configuration. As a
configuration option, after the first configuration (i.e., at
reconfiguration), the user can reconfigure without
clearing the internal configuration RAM first.
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POWERUP
– POWER-ON TIME DELAY
The active-low, open-drain initialization signal INIT is
released and must be pulled high by an external resistor when initialization is complete. To synchronize the
configuration of multiple FPGAs, one or more INIT pins
should be wire-ANDed. If INIT is held low by one or
more FPGAs or an external device, the FPGA remains
in the initialization state. INIT can be used to signal that
the FPGAs are not yet initialized. After INIT goes high
for two internal clock cycles, the mode lines (M[3:0])
are sampled and the FPGA enters the configuration
state.
INITIALIZATION
– CLEAR CONFIGURATION MEMORY
– INIT LOW, HDC HIGH, LDC LOW
RESET,
INIT,
OR
PRGM
LOW
BIT
ERROR
YES
NO
YES
NO
CONFIGURATION
– M[3:0] MODE IS SELECTED
– CONFIGURATION DATA FRAME WRITTEN
– INIT HIGH, HDC HIGH, LDC LOW
– DOUT ACTIVE
RESET
OR
PRGM
LOW
The high during configuration (HDC), low during configuration (LDC), and DONE signals are active outputs in
the FPGA’s initialization and configuration states. HDC,
LDC, and DONE can be used to provide control of
external logic signals such as reset, bus enable, or
PROM enable during configuration. For parallel master
configuration modes, these signals provide PROM
enable control and allow the data pins to be shared
with user logic signals.
START-UP
– ACTIVE I/O
– RELEASE INTERNAL RESET
– DONE GOES HIGH
PRGM
LOW
OPERATION
5-4529(F).r6
Figure 36. FPGA States of Operation
Initialization
Upon powerup, the device goes through an initialization
process. First, an internal power-on-reset circuit is triggered when power is applied. When VDD reaches the
voltage at which portions of the FPGA begin to operate
(2.5 V to 3 V for the OR2CxxA, 2.2 V to 2.7 V for the
OR2TxxA/OR2TxxB), the I/Os are configured based on
the configuration mode, as determined by the mode
select inputs M[2:0]. A time-out delay is initiated when
VDD reaches between 3.0 V and 4.0 V (OR2CxxA) or
2.7 V to 3.0 V (OR2TxxA/2TxxB) to allow the power
supply voltage to stabilize. The INIT and DONE outputs
are low. At powerup, if VDD does not rise from 2.0 V to
VDD in less than 25 ms, the user should delay configuration by inputting a low into INIT, PRGM, or RESET
until VDD is greater than the recommended minimum
42
If configuration has begun, an assertion of RESET or
PRGM initiates an abort, returning the FPGA to the initialization state. The PRGM and RESET pins must be
pulled back high before the FPGA will enter the configuration state. During the start-up and operating states,
only the assertion of PRGM causes a reconfiguration.
In the master configuration modes, the FPGA is the
source of configuration clock (CCLK). In this mode, the
initialization state is extended to ensure that, in daisychain operation, all daisy-chained slave devices are
ready. Independent of differences in clock rates, master
mode devices remain in the initialization state an additional six internal clock cycles after INIT goes high.
When configuration is initiated, a counter in the FPGA
is set to 0 and begins to count configuration clock
cycles applied to the FPGA. As each configuration data
frame is supplied to the FPGA, it is internally assembled into data words. Each data word is loaded into the
internal configuration memory. The configuration loading process is complete when the internal length count
equals the loaded length count in the length count field,
and the required end of configuration frame is written.
Lattice Semiconductor
Data Sheet
November 2006
ORCA Series 2 FPGAs
FPGA States of Operation (continued)
VDD
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RESET
PRGM
INIT
M[3:0]
CCLK
HDC
LDC
DONE
USER I/O
INTERNAL
RESET
(gsm)
INITIALIZATION
CONFIGURATION
START-UP
OPERATION
5-4482(F)
Figure 37. Initialization/Configuration/Start-Up Waveforms
All OR2CxxA I/Os operate as TTL inputs during configuration (OR2TxxA/OR2TxxB I/Os are CMOS-only). All
I/Os that are not used during the configuration process
are 3-stated with internal pull-ups. During configuration, the PLC latch/FFs are held set/reset and the internal BIDI buffers are 3-stated. The TRIDIs in the PICs
are not 3-stated. The combinatorial logic begins to
function as the FPGA is configured. Figure 37 shows
the general waveform of the initialization, configuration,
and start-up states.
Lattice Semiconductor
Configuration
The ORCA Series FPGA functionality is determined by
the state of internal configuration RAM. This configuration RAM can be loaded in a number of different
modes. In these configuration modes, the FPGA can
act as a master or a slave of other devices in the system. The decision as to which configuration mode to
use is a system design issue. The next section discusses configuration in detail, including the configuration data format and the configuration modes used to
load the configuration data in the FPGA.
43
Data Sheet
November 2006
ORCA Series 2 FPGAs
FPGA States of Operation (continued)
Start-Up
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After configuration, the FPGA enters the start-up
phase. This phase is the transition between the configuration and operational states and begins when the
number of CCLKs received after INIT goes high is
equal to the value of the length count field in the configuration frame and when the end of configuration frame
has been written. The system design issue in the startup phase is to ensure the user I/Os become active
without inadvertently activating devices in the system
or causing bus contention. A second system design
concern is the timing of the release of global set/reset
of the PLC latches/FFs.
as an active-high ready signal, an active-low PROM
enable, or a reset to other portions of the system.
When used in SYNC mode, these ANDed DONE pins
can be used to synchronize the other two start-up
events, since they can all be synchronized to the same
external signal. This signal will not rise until all FPGAs
release their DONE pins, allowing the signal to be
pulled high.
There are configuration options that control the relative
timing of three events: DONE going high, release of the
set/reset of internal FFs, and user I/Os becoming
active. Figure 38 shows the start-up timing for both the
ORCA and ATT3000 Series FPGAs. The system
designer determines the relative timing of the I/Os
becoming active, DONE going high, and the release of
the set/reset of internal FFs. In the ORCA Series
FPGA, the three events can occur in any arbitrary
sequence. This means that they can occur before or
after each other, or they can occur simultaneously.
There are four main start-up modes: CCLK_NOSYNC,
CCLK_SYNC, UCLK_NOSYNC, and UCLK_SYNC.
The only difference between the modes starting with
CCLK and those starting with UCLK is that for the
UCLK modes, a user clock must be supplied to the
start-up logic. The timing of start-up events is then
based upon this user clock, rather than CCLK. The difference between the SYNC and NOSYNC modes is
that, for SYNC mode, the timing of two of the start-up
events (release of the set/reset of internal FFs and the
I/Os becoming active) is triggered by the rise of the
external DONE pin followed by a variable number of
rising clock edges (either CCLK or UCLK). For the
NOSYNC mode, the timing of these two events is
based only on either CCLK or UCLK.
DONE is an open-drain bidirectional pin that may
include an optional (enabled by default) pull-up resistor
to accommodate wired ANDing. The open-drain DONE
signals from multiple FPGAs can be tied together
(ANDed) with a pull-up (internal or external) and used
44
The default for ORCA is the CCLK_SYNC synchronized start-up mode where DONE is released on the
first CCLK rising edge, C1 (see Figure 38). Since this is
a synchronized start-up mode, the open-drain DONE
signal can be held low externally to stop the occurrence
of the other two start-up events. Once the DONE pin
has been released and pulled up to a high level, the
other two start-up events can be programmed individually to either happen immediately or after up to four rising edges of CCLK (Di, Di + 1, Di + 2, Di + 3, Di + 4).
The default is for both events to happen immediately
after DONE is released and pulled high.
A commonly used design technique is to release
DONE one or more clock cycles before allowing the I/O
to become active. This allows other configuration
devices, such as PROMs, to be disconnected using the
DONE signal so that there is no bus contention when
the I/Os become active. In addition to controlling the
FPGA during start-up, other start-up techniques that
avoid contention include using isolation devices
between the FPGA and other circuits in the system,
reassigning I/O locations and maintaining I/Os as
3-stated outputs until contentions are resolved.
Each of these start-up options can be selected during
bit stream generation in ispLEVER, using Advanced
Options. For more information, please see the
ispLEVER documentation.
Reconfiguration
To reconfigure the FPGA when the device is operating
in the system, a low pulse is input into PRGM. The configuration data in the FPGA is cleared, and the I/Os not
used for configuration are 3-stated. The FPGA then
samples the mode select inputs and begins reconfiguration. When reconfiguration is complete, DONE is
released, allowing it to be pulled high.
Lattice Semiconductor
Data Sheet
November 2006
ORCA Series 2 FPGAs
FPGA States of Operation (continued)
ATT3000
Partial Reconfiguration
All ORCA device families have been designed to allow
a partial reconfiguration of the FPGA at any time. This
is done by setting a bit stream option in the previous
configuration sequence that tells the FPGA to not reset
all of the configuration RAM during a reconfiguration.
Then only the configuration frames that are to be modified need to be rewritten, thereby reducing the configuration time.
CCLK PERIOD
F
DONE
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I/O
GLOBAL
RESET
Other bit stream options are also available that allow
one portion of the FPGA to remain in operation while a
partial reconfiguration is being done. If this is done, the
user must be careful to not cause contention between
the two configurations (the bit stream resident in the
FPGA and the partial reconfiguration bit stream) as the
second reconfiguration bit stream is being loaded.
ORCA CCLK_NOSYNC
F
DONE
C1
C2
C3
C4
C1
C2
C3
C4
C1
C2
C3
C4
I/O
GSRN
ACTIVE
Other Configuration Options
ORCA CCLK_SYNC
Configuration options used during device start-up were
previously discussed in the FPGA States of Operation
section of this data sheet. There are many other configuration options available to the user that can be set
during bit stream generation in ispLEVER. These
include options to enable boundary scan, readback
options, and options to control and use the internal
oscillator after configuration.
DONE IN
DONE
C1, C2, C3, OR C4
I/O
GSRN
ACTIVE
F
Di
Di + 1
Di + 2
Di + 3
Di + 4
Di
Di + 1
Di + 2
Di + 3
Di + 4
ORCA UCLK_NOSYNC
UCLK
Other useful options that affect the next configuration
(not the current configuration process) include options
to disable the global set/reset during configuration, disable the 3-state of I/Os during configuration, and disable the reset of internal RAMs during configuration to
allow for partial configurations (see above). For more
information on how to set these and other configuration
options, please see the ispLEVER documentation.
F
DONE
I/O
C1
GSRN
ACTIVE
U1
U2
U3
U4
U1
U2
U3
U4
U1
U2
U3
U4
ORCA UCLK_SYNC
Configuration Data Format
DONE IN
DONE
I/O
C1
F
U1, U2, U3, OR U4
Di
GSRN
ACTIVE
Di + 1
Di + 2
Di + 3
Di Di + 1
Di + 2
Di + 3
Di + 4
The ispLEVER development system interfaces with
front-end design entry tools and provides the tools to
produce a fully configured FPGA. This section discusses using the ispLEVER development system to
generate configuration RAM data and then provides
the details of the configuration frame format.
UCLK PERIOD
SYNCHRONIZATION UNCERTAINTY
F = finished, no more CLKs required.
5-2761(F).r4
Figure 38. Start-Up Waveforms
Lattice Semiconductor
The ORCA Series 2 series of FPGAs are enhanced
versions of the ORCA ATT2Cxx/ATT2Txx architectures
that provide upward bit stream compatibility for both
series of devices as well as with each other.
45
Data Sheet
November 2006
ORCA Series 2 FPGAs
Configuration Data Format (continued)
Using ispLEVER to Generate
Configuration RAM Data
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The configuration data defines the I/O functionality,
logic, and interconnections. The bit stream is generated
by the development system. The bit stream created by
the bit stream generation tool is a series of 1s and 0s
used to write the FPGA configuration RAM. The bit
stream can be loaded into the FPGA using one of the
configuration modes discussed later. In the bit stream
generator, the designer selects options which affect the
FPGA’s functionality. Using the output of the bit stream
generator, circuit.bit, the development system’s download tool can load the configuration data into the ORCA
series FPGA evaluation board from a PC or workstation. Alternatively, a user can program a PROM (such
as the ATT1700A Series Serial ROM or a standard
EPROM) and load the FPGA from the PROM. The
development system’s PROM programming tool produces a file in .mks or .exo format.
FPGAs. Following the header frame is an optional ID
frame. This frame contains data used to determine if
the bit stream is being loaded to the correct type of
ORCA FPGA (i.e., a bit stream generated for an
OR2C15A is being sent to an OR2C15A). Since the
OR2CxxA devices are bit stream compatible with the
ATT2Cxx, ATT2Txx, OR2TxxA, and OR2TxxB families,
a bit stream from any of these devices will not cause an
error when loaded into an OR2CxxA, OR2TxxA, or
OR2TxxB device. The ID frame has a secondary function of optionally enabling the parity checking logic for
the rest of the data frames.
Configuration Data Frame
A detailed description of the frame format is shown in
Figure 39. The header frame begins with a series of 1s
and a preamble of 0010, followed by a 24-bit length
count field representing the total number of configuration clocks needed to complete the loading of the
The configuration data frames follow. Each frame starts
with a 0 start bit and ends with three or more 1 stop
bits. Following each start bit are four control bits: a program bit, set to 1 if this is a data frame; a compress bit,
set to 1 if this is a compressed frame; and the opar and
epar parity bits (see Bit Stream Error Checking). An
11-bit address field that determines in which column
the FPGA is to be written is followed by alignment and
write control bits. For uncompressed frames, the data
bits needed to write one column in the FPGA are next.
For compressed frames, the data bits from the previous
frame are sent to a different FPGA column, as specified by the new address bits; therefore, new data bits
are not required. When configuration of the current
FPGA is finished, an end-of-configuration frame (where
the program bit is set to 0) is sent to the FPGA. The
length and number of data frames and information on
the PROM size for the Series 3 FPGAs are given in
Table 7.
Table 7. Configuration Frame Size
OR2C/
2T04A
OR2C06
OR2C/
2T08A
OR2C/
2T10A
OR2C12A
OR2C/
2T15A/B
OR2C/
2T26A
OR2C/
2T40A/B
# of Frames
480
568
656
744
832
920
1096
1378
Data Bits/Frame
110
130
150
170
190
210
250
316
Configuration Data
(# of frames x # of data bits/frame)
52,800
73,840
98,400
126,480
158,080
193,200
274,000
435,448
Maximum Total # Bits/Frame
(align bits, 1 write bit, 8 stop bits)
136
160
176
200
216
240
280
344
Maximum Configuration Data
(# bits x # of frames)
65,280
90,880
115,456
148,800
179,712
220,800
306,880
474,032
Maximum PROM Size (bits)
(add 48-bit header, ID frame, and
40-bit end of configuration frame)
65,504
91,128
115,720
149,088
180,016
221,128
307,248
474,464
Devices
46
Lattice Semiconductor
Data Sheet
November 2006
ORCA Series 2 FPGAs
Configuration Data Format (continued)
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The data frames for all the Series 2 series devices are given in Table 8. An alignment field is required in the slave
parallel mode for the uncompressed format. The alignment field (shown by [A]) is a series of 0s: five for the
OR2C06A, OR2C10A/OR2T10A, OR2C15A/OR2T15A/OR2T15B, and OR2C26A/OR2T26A; three for the
OR2C40A/OR2T40A/OR2T40B; and one for the OR2C04A/OR2T04A, OR2C08A/OR2T08A, and OR2C12A. The
alignment field is not required in any other mode.
Table 8. Configuration Data Frames
OR2C04A/OR2T04A
Uncompressed
010 opar epar [addr10:0] [A]1[Data109:0]111
Compressed
011 opar epar [addr10:0] 111
OR2C06A
Uncompressed
010 opar epar [addr10:0] [A]1[Data129:0]111
Compressed
011 opar epar [addr10:0] 111
OR2C08A/OR2T08A
Uncompressed
010 opar epar [addr10:0] [A]1[Data149:0]111
Compressed
011 opar epar [addr10:0] 111
OR2C10A/OR2T10A
Uncompressed
010 opar epar [addr10:0] [A]1[Data169:0]111
Compressed
011 opar epar [addr10:0] 111
OR2C12A
Uncompressed
010 opar epar [addr10:0] [A]1[Data189:0]111
Compressed
011 opar epar [addr10:0] 111
OR2C15A/OR2T15A/OR2T15B
Uncompressed
010 opar epar [addr10:0] [A]1[Data209:0]111
Compressed
011 opar epar [addr10:0] 111
OR2C26A/OR2T26A
Uncompressed
010 opar epar [addr10:0] [A]1[Data249:0]111
Compressed
011 opar epar [addr10:0] 111
OR2C40A/OR2T40A/OR2T40B
Uncompressed
010 opar epar [addr10:0] [A]1[Data315:0]111
Compressed
011 opar epar [addr10:0] 111
EIGHT 1s
0010
PREAMBLE
24-bit
LENGTH
COUNT
LEADING HEADER
DATA FRAMES
FPGA #1
DATA FRAMES
FPGA #2
END OF
CONFIGURATION
FRAME
FPGA #1
POSTAMBLE
END OF
CONFIGURATION
FRAME
FPGA #2
5-4530(F)
Figure 39. Serial Configuration Data Format
Lattice Semiconductor
47
Data Sheet
November 2006
ORCA Series 2 FPGAs
Configuration Data Format (continued)
Table 9. Configuration Frame Format and Contents
Leading header—4 bits minimum dummy bits
Preamble
Configuration frame length
Trailing header—4 bits minimum dummy bits
Frame start
Must be set to 1 to indicate data frame
Must be set to 0 to indicate uncompressed
Frame parity bits
ID frame address
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Header
11111111
0010
24-Bit Length Count
1111
0
P—1
C—0
Opar, Epar
Addr[10:0] =
11111111111
Prty_En
Reserved [42:0]
ID
111
0
P—1 or 0
C—1 or 0
ID Frame
(Optional)
Configuration
Data
Frame
(repeated for
each data frame)
End of
Configuration
Postamble
Opar, Epar
Addr[10:0]
A
1
Data Bits
.
.
111
0010011111111111
Set to 1 to enable parity
Reserved bits set to 0
20-bit part ID
Three or more stop bits (high) to separate frames
Frame start
1 indicates data frame; 0 indicates all frames are written
Uncompressed—0 indicates data and address are supplied;
Compressed—1 indicates only address is supplied
Frame parity bits
Column address in FPGA to be written
Alignment bit (different number of 0s needed for each part)
Write bit—used in uncompressed data frame
Needed only in an uncompressed data frame
.
.
One or more stop bits (high) to separate frames
16 bits—00 indicates all frames are written
111111 . . . . .
Additional 1s
Note: For slave parallel mode, the byte containing the preamble must be 11110010. The number of leading header dummy bits must
be (n * 8) + 4, where n is any nonnegative integer and the number of trailing dummy bits must be (n * 8), where n is any positive
integer. The number of stop bits/frame for slave parallel mode must be (x * 8), where x is a positive integer. Note also that the bit
stream generator tool supplies a bit stream which is compatible with all configuration modes, including slave parallel mode.
48
Lattice Semiconductor
Data Sheet
November 2006
Bit Stream Error Checking
There are three different types of bit stream error
checking performed in the ORCA Series 2 FPGAs:
ID frame, frame alignment, and parity checking.
Table 10. Configuration Modes
M2 M1 M0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
CCLK
Output
Input
Reserved
Input
Output
Output
Output
Input
Configuration
Mode
Data
Master
Slave Parallel
Serial
Parallel
Sync Peripheral
Master (up)
Async Peripheral
Master (down)
Slave
Parallel
Parallel
Parallel
Parallel
Serial
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An optional ID data frame can be sent to a specified
address in the FPGA. This ID frame contains a unique
code for the part it was generated for which is compared within the FPGA. Any differences are flagged as
an ID error. This frame is automatically created by the
bit stream generation program in ispLEVER.
ORCA Series 2 FPGAs
Every data frame in the FPGA begins with a start bit
set to 0 and three or more stop bits set to 1. If any of
the three previous bits were a 0 when a start bit is
encountered, it is flagged as a frame alignment error.
Parity checking is also done on the FPGA for each
frame, if it has been enabled by setting the prty_en bit
to 1 in the ID frame. This is set by enabling the parity
check option in the bit stream generation program of
ispLEVER. Two parity bits, opar and epar, are used to
check the parity of bits in alternating bit positions to
even parity in each data frame. If an odd number of
ones is found for either the even bits (starting with the
start bit) or the odd bits (starting with the program bit),
then a parity error is flagged.
When any of the three possible errors occur, the FPGA
is forced into the INIT state, forcing INIT low. The FPGA
will remain in this state until either the RESET or PRGM
pins are asserted.
FPGA Configuration Modes
Master Parallel Mode
The master parallel configuration mode is generally
used to interface to industry-standard byte-wide memory, such as the 2764 and larger EPROMs. Figure 40
provides the connections for master parallel mode. The
FPGA outputs an 18-bit address on A[17:0] to memory
and reads one byte of configuration data on the rising
edge of RCLK. The parallel bytes are internally serialized starting with the least significant bit, D0.
A[17:0]
There are three basic FPGA configuration modes:
master, slave, and peripheral. The configuration data
can be transmitted to the FPGA serially or in parallel
bytes. As a master, the FPGA provides the control signals out to strobe data in. As a slave device, a clock is
generated externally and provided into CCLK. In the
peripheral mode, the FPGA acts as a microprocessor
peripheral. Table 10 lists the functions of the configuration mode pins.
Lattice Semiconductor
DOUT
CCLK
D[7:0]
OE
CE
VDD
VDD OR GND
TO DAISYCHAINED
DEVICES
D[7:0]
EPROM
PROGRAM
There are eight methods for configuring the FPGA.
Seven of the configuration modes are selected on the
M0, M1, and M2 inputs. The eighth configuration mode
is accessed through the boundary-scan interface. A
fourth input, M3, is used to select the frequency of the
internal oscillator, which is the source for CCLK in
some configuration modes. The nominal frequencies of
the internal oscillator are 1.25 MHz and 10 MHz. The
1.25 MHz frequency is selected when the M3 input is
unconnected or driven to a high state.
A[17:0]
DONE
PRGM
M2
M1
M0
ORCA
SERIES
FPGA
HDC
LDC
RCLK
5-4483(F)
Figure 40. Master Parallel Configuration Schematic
There are two parallel master modes: master up and
master down. In master up, the starting memory
address is 00000 Hex and the FPGA increments the
address for each byte loaded. In master down, the
starting memory address is 3FFFF Hex and the FPGA
decrements the address.
One master mode FPGA can interface to the memory
and provide configuration data on DOUT to additional
FPGAs in a daisy chain. The configuration data on
DOUT is provided synchronously with the falling edge
of CCLK. The frequency of the CCLK output is eight
times that of RCLK.
49
Data Sheet
November 2006
ORCA Series 2 FPGAs
FPGA Configuration Modes (continued)
Master Serial Mode
Serial ROMs can also be cascaded to support the configuration of multiple FPGAs or to load a single FPGA
when configuration data requirements exceed the
capacity of a single serial ROM. After the last bit from
the first serial ROM is read, the serial ROM outputs
CEO low and 3-states the DATA output. The next serial
ROM recognizes the low on CE input and outputs configuration data on the DATA output. After configuration
is complete, the FPGA’s DONE output into CE disables
the serial ROMs.
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In the master serial mode, the FPGA loads the configuration data from an external serial ROM. The configuration data is either loaded automatically at start-up or on
a PRGM command to reconfigure. The ATT1700 and
ATT1700A Series can be used to configure the FPGA
in the master serial mode. This provides a simple 4-pin
interface in an 8-pin package. The ATT1736, ATT1765,
and ATT17128 serial ROMs store 32K, 64K, and 128K
bits, respectively.
The FPGA DONE is routed to the CE pin. The low on
DONE enables the serial ROMs. At the completion of
configuration, the high on the FPGA's DONE disables
the serial ROM.
Configuration in the master serial mode can be done at
powerup and/or upon a configure command. The system or the FPGA must activate the serial ROM's
RESET/OE and CE inputs. At powerup, the FPGA and
serial ROM each contain internal power-on reset circuitry that allows the FPGA to be configured without
the system providing an external signal. The power-on
reset circuitry causes the serial ROM's internal address
pointer to be reset. After powerup, the FPGA automatically enters its initialization phase.
The serial ROM/FPGA interface used depends on such
factors as the availability of a system reset pulse, availability of an intelligent host to generate a configure
command, whether a single serial ROM is used or multiple serial ROMs are cascaded, whether the serial
ROM contains a single or multiple configuration programs, etc. Because of differing system requirements
and capabilities, a single FPGA/serial ROM interface is
generally not appropriate for all applications.
Data is read in the FPGA sequentially from the serial
ROM. The DATA output from the serial ROM is connected directly into the DIN input of the FPGA. The
CCLK output from the FPGA is connected to the
CLOCK input of the serial ROM. During the configuration process, CCLK clocks one data bit on each rising
edge.
Since the data and clock are direct connects, the
FPGA/serial ROM design task is to use the system or
FPGA to enable the RESET/OE and CE of the serial
ROM(s). There are several methods for enabling the
serial ROM’s RESET/OE and CE inputs. The serial
ROM's RESET/OE is programmable to function with
RESET active-high and OE active-low or RESET activelow and OE active-high.
In Figure 41, serial ROMs are cascaded to configure
multiple daisy-chained FPGAs. The host generates a
500 ns low pulse into the FPGA's PRGM input. The
FPGA’s INIT input is connected to the serial ROM’s
RESET/OE input, which has been programmed to
function with RESET active-low and OE active-high.
50
This FPGA/serial ROM interface is not used in applications in which a serial ROM stores multiple configuration programs. In these applications, the next
configuration program to be loaded is stored at the
ROM location that follows the last address for the previous configuration program. The reason the interface in
Figure 41 will not work in this application is that the low
output on the INIT signal would reset the serial ROM
address pointer, causing the first configuration to be
reloaded.
In some applications, there can be contention on the
FPGA's DIN pin. During configuration, DIN receives
configuration data, and after configuration, it is a user
I/O. If there is contention, an early DONE at start-up
(selected in ispLEVER) may correct the problem. An
alternative is to use LDC to drive the serial ROM's CE
pin. In order to reduce noise, it is generally better to run
the master serial configuration at 1.25 MHz (M3 pin
tied high), rather than 10 MHz, if possible.
DATA
DOUT
DIN
CLK
TO DAISYCHAINED
DEVICES
CCLK
ATT1700A
CE
RESET/OE
DONE
INIT
ORCA
SERIES
FPGA
CEO
DATA
CLK
PRGM
ATT1700A
CE
RESET/OE
CEO
TO MORE
SERIAL ROMs
AS NEEDED
M2
M1
M0
PROGRAM
5-4456.1(F)
Figure 41. Master Serial Configuration Schematic
Lattice Semiconductor
Data Sheet
November 2006
ORCA Series 2 FPGAs
FPGA Configuration Modes (continued)
Synchronous Peripheral Mode
Asynchronous Peripheral Mode
In the synchronous peripheral mode, byte-wide data is
input into D[7:0] on the rising edge of the CCLK input.
The first data byte is clocked in on the second CCLK
after INIT goes high. Subsequent data bytes are
clocked in on every eighth rising edge of CCLK. The
RDY signal is an output which acts as an acknowledge.
RDY goes high one CCLK after data is clocked and,
after one CCLK cycle, returns low. The process repeats
until all of the data is loaded into the FPGA. The data
begins shifting on DOUT 1.5 cycles after it is loaded in
parallel. It requires additional CCLKs after the last byte
is loaded to complete the shifting. Figure 43 shows the
connections for synchronous peripheral mode.
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Figure 42 shows the connections needed for the asynchronous peripheral mode. In this mode, the FPGA
system interface is similar to that of a microprocessorperipheral interface. The microprocessor generates the
control signals to write an 8-bit byte into the FPGA. The
FPGA control inputs include active-low CS0 and activehigh CS1 chip selects, a write WR input, and a read RD
input. The chip selects can be cycled or maintained at a
static level during the configuration cycle. Each byte of
data is written into the FPGA’s D[7:0] input pins.
The FPGA provides a RDY status output to indicate
that another byte can be loaded. A low on RDY indicates that the double-buffered hold/shift registers are
not ready to receive data, and this pin must be monitored to go high before another byte of data can be
written. The shortest time RDY is low occurs when a
byte is loaded into the hold register and the shift register is empty, in which case the byte is immediately
transferred to the shift register. The longest time for
RDY to remain low occurs when a byte is loaded into
the holding register and the shift register has just
started shifting configuration data into configuration
RAM.
The RDY status is also available on the D7 pin by
enabling the chip selects, setting WR high, and applying RD low, where the RD input is an output enable for
the D7 pin when RD is low. The D[6:0] pins are not
enabled to drive when RD is low and, thus, only act as
input pins in asynchronous peripheral mode.
DOUT
8
MICROPROCESSOR
PRGM
CCLK
D[7:0]
RDY/BUSY
INIT
DONE
ADDRESS
DECODE LOGIC
CS0
CS1
BUS
CONTROLLER
RD
WR
VDD
M2
M1
M0
TO DAISYCHAINED
DEVICES
As with master modes, the peripheral modes can be
used as the lead FPGA for a daisy chain of slave
FPGAs.
DOUT
8
TO DAISYCHAINED
DEVICES
PRGM
D[7:0]
ORCA
SERIES
FPGA
MICROPROCESSOR
CCLK
RDY/BUSY
INIT
+5 V
M2
M1
M0
HDC
LDC
5-4486(F)
Figure 43. Synchronous Peripheral Configuration
Schematic
ORCA
SERIES
FPGA
HDC
LDC
5-4484(F)
Figure 42. Asynchronous Peripheral Configuration
Schematic
Lattice Semiconductor
51
Data Sheet
November 2006
ORCA Series 2 FPGAs
FPGA Configuration Modes (continued)
Slave Parallel Mode
Slave Serial Mode
The slave parallel mode is essentially the same as the
slave serial mode except that 8 bits of data are input on
pins D[7:0] for each CCLK cycle. Due to 8 bits of data
being input per CCLK cycle, the DOUT pin does not
contain a valid bit stream for slave parallel mode. As a
result, the lead device cannot be used in the slave
parallel mode in a daisy-chain configuration.
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The slave serial mode is primarily used when multiple
FPGAs are configured in a daisy chain. The serial slave
serial mode is also used on the FPGA evaluation board
which interfaces to the download cable. A device in the
slave serial mode can be used as the lead device in a
daisy chain. Figure 44 shows the connections for the
slave serial configuration mode.
The configuration data is provided into the FPGA’s DIN
input synchronous with the configuration clock CCLK
input. After the FPGA has loaded its configuration data,
it retransmits the incoming configuration data on
DOUT. CCLK is routed into all slave serial mode
devices in parallel.
Multiple slave FPGAs can be loaded with identical configurations simultaneously. This is done by loading the
configuration data into the DIN inputs in parallel.
Figure 45 is a schematic of the connections for the
slave parallel configuration mode. WR and CS0 are
active-low chip select signals, and CS1 is an activehigh chip select signal. These chip selects allow the
user to configure multiple FPGAs in slave parallel
mode using an 8-bit data bus common to all of the
FPGAs. These chip selects can then be used to select
the FPGA(s) to be configured with a given bit stream,
but once an FPGA has been selected, it cannot be
deselected until it has been completely programmed.
8
DOUT
INIT
MICROPROCESSOR
OR
DOWNLOAD
CABLE
PRGM
DONE
INIT
MICROPROCESSOR
OR
SYSTEM
ORCA
SERIES
FPGA
D[7:0]
DONE
TO DAISYCHAINED
DEVICES
CCLK
PRGM
ORCA
SERIES
FPGA
VDD
CS1
CS0
WR
CCLK
DIN
VDD
M2
HDC
M1
LDC
M0
M2
M1
M0
HDC
5-4487(F)
LDC
5-4485(F)
Figure 45. Slave Parallel Configuration Schematic
Figure 44. Slave Serial Configuration Schematic
52
Lattice Semiconductor
Data Sheet
November 2006
ORCA Series 2 FPGAs
FPGA Configuration Modes (continued)
on the negative edge of CCLK. Figure 46 shows the
connections for loading multiple FPGAs in a daisychain configuration.
Daisy Chain
The generation of CCLK for the daisy-chained devices
which are in slave serial mode differs depending on the
configuration mode of the lead device. A master parallel mode device uses its internal timing generator to
produce an internal CCLK at eight times its memory
address rate (RCLK). The asynchronous peripheral
mode device outputs eight CCLKs for each write cycle.
If the lead device is configured in either synchronous
peripheral or a slave mode, CCLK is routed to the lead
device and to all of the daisy-chained devices.
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Multiple FPGAs can be configured by using a daisy
chain of the FPGAs. Daisy chaining uses a lead FPGA
and one or more FPGAs configured in slave serial
mode. The lead FPGA can be configured in any mode
except slave parallel mode. (Daisy chaining is not available with the boundary-scan ram_w instruction, discussed later.)
All daisy-chained FPGAs are connected in series.
Each FPGA reads and shifts the preamble and length
count in on positive CCLK and out on negative CCLK
edges.
The development system can create a composite
configuration bit stream for configuring daisy-chained
FPGAs. The frame format is a preamble, a length count
for the total bit stream, multiple concatenated data
frames, an end-of-configuration frame per device, a
postamble, and an additional fill bit per device in the
serial chain.
An upstream FPGA that has received the preamble
and length count outputs a high on DOUT until it has
received the appropriate number of data frames so that
downstream FPGAs do not receive frame start bits
(0s). After loading and retransmitting the preamble and
length count to a daisy chain of slave devices, the lead
device loads its configuration data frames. The loading
of configuration data continues after the lead device
has received its configuration data if its internal frame
bit counter has not reached the length count. When the
configuration RAM is full and the number of bits
received is less than the length count field, the FPGA
shifts any additional data out on DOUT.
As seen in Figure 46, the INIT pins for all of the FPGAs
are connected together. This is required to guarantee
that powerup and initialization will work correctly. In
general, the DONE pins for all of the FPGAs are also
connected together as shown to guarantee that all of
the FPGAs enter the start-up state simultaneously. This
may not be required, depending upon the start-up
sequence desired.
The configuration data is read into DIN of slave devices
on the positive edge of CCLK, and shifted out DOUT
CCLK
A[17:0]
EPROM
D[7:0]
D[7:0]
OE
CE
DONE
CCLK
DIN
ORCA
SERIES
FPGA
MASTER
DIN
DOUT
ORCA
SERIES
FPGA
SLAVE #1
VDD
VDD OR
GND
M2
M1
M0
INIT
HDC
LDC
RCLK
VDD
PRGM
M2
M1
M0
DOUT
ORCA
SERIES
FPGA
SLAVE #2
DONE
PRGM
PROGRAM
CCLK
DOUT
A[17:0]
VDD
DONE
INIT
VDD
HDC
LDC
RCLK
PRGM
M2
M1
M0
INIT
HDC
LDC
RCLK
VDD
5-4488(F)
Figure 46. Daisy-Chain Configuration Schematic
Lattice Semiconductor
53
ORCA Series 2 FPGAs
Special Function Blocks
Special function blocks in the Series 2 provide extra
capabilities beyond general FPGA operation. These
blocks reside in the corners of the FPGA array.
again. One bit of data is shifted out on RD_DATA at the
rising edge of CCLK. The first start bit of the readback
frame is transmitted out several cycles after the first rising edge of CCLK after RD_CFG is input low (see Table
48, Readback Timing Characteristics in the Timing
Characteristics section).
It should be noted that the RD_DATA output pin is also
used as the dedicated boundary-scan output pin, TDO.
If this pin is being used as TDO, the RD_DATA output
from readback can be routed internally to any other pin
desired. The RD_CFG input pin is also used to control
the global 3-state (TS_ALL) function. Before and during
configuration, the TS_ALL signal is always driven by
the RD_CFG input and readback is disabled. After configuration, the selection as to whether this input drives
the readback or global 3-state function is determined
by a set of bit stream options. If used as the RD_CFG
input for readback, the internal TS_ALL input can be
routed internally to be driven by any input pin.
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Single Function Blocks
Data Sheet
November 2006
Most of the special function blocks perform a specific
dedicated function. These functions are data/configuration readback control, global 3-state control (TS_ALL),
internal oscillator generation, global set/reset (GSRN),
and start-up logic.
Readback Logic
The readback logic is located in the upper right corner
of the FPGA.
Readback is used to read back the configuration data
and, optionally, the state of the PFU outputs. A readback operation can be done while the FPGA is in normal system operation. The readback operation cannot
be daisy-chained. To use readback, the user selects
options in the bit stream generator in the ispLEVER
development system.
Table 11 provides readback options selected in the bit
stream generator tool. The table provides the number
of times that the configuration data can be read back.
This is intended primarily to give the user control over
the security of the FPGA’s configuration program. The
user can prohibit readback (0), allow a single readback
(1), or allow unrestricted readback (U).
Table 11. Readback Options
Option
Function
0
Prohibit Readback
1
Allow One Readback Only
U
Allow Unrestricted Number of Readbacks
The pins used for readback are readback data
(RD_DATA), read configuration (RD_CFG), and configuration clock (CCLK). A readback operation is initiated
by a high-to-low transition on RD_CFG. The RD_CFG
input must remain low during the readback operation.
The readback operation can be restarted at frame 0 by
driving the RD_CFG pin high, applying at least two rising edges of CCLK, and then driving RD_CFG low
54
The readback frame contains the configuration data
and the state of the internal logic. During readback, the
value of all five PFU outputs can be captured. The following options are allowed when doing a capture of the
PFU outputs.
1. Do not capture data (the data written to the capture
RAMs, usually 0, will be read back).
2. Capture data upon entering readback.
3. Capture data based upon a configurable signal
internal to the FPGA. If this signal is tied to
logic 0, capture RAMs are written continuously.
4. Capture data on either options 2 or 3 above.
The readback frame has a similar, but not identical, format to the configuration frame. This eases a bitwise
comparison between the configuration and readback
data. The readback data is not inverted. Every data
frame has one low start bit and one high stop bit. The
preamble, including the length count field, is not part of
the readback frame. The readback frame contains
states in locations not used in the configuration. These
locations need to be masked out when comparing the
configuration and readback frames. The development
system optionally provides a readback bit stream to
compare to readback from the FPGA. Also note that if
any of the LUTs are used as RAM and new data is written to them, these bits will not have the same values as
the original configuration data frame either.
Lattice Semiconductor
Data Sheet
November 2006
Special Function Blocks (continued)
Global 3-State Control (TS_ALL)
The TS_ALL block resides in the upper-right corner of
the FPGA array.
Global Set/Reset (GSRN)
The GSRN logic resides in the lower-right corner of the
FPGA. GSRN is an invertible, default, active-low signal
that is used to reset all of the user-accessible latches/
FFs on the device. GSRN is automatically asserted at
powerup and during configuration of the device.
The timing of the release of GSRN at the end of configuration can be programmed in the start-up logic
described below. Following configuration, GSRN may
be connected to the RESET pin via dedicated routing,
or it may be connected to any signal via normal routing.
Within each PFU, individual FFs and latches can be
programmed to either be set or reset when GSRN is
asserted.
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To increase the testability of the ORCA Series FPGAs,
the global 3-state function (TS_ALL) disables the
device. The TS_ALL signal is driven from either an
external pin or an internal signal. Before and during
configuration, the TS_ALL signal is driven by the input
pad RD_CFG. After configuration, the TS_ALL signal
can be disabled, driven from the RD_CFG input pad, or
driven by a general routing signal in the upper-right corner. Before configuration, TS_ALL is active-low; after
configuration, the sense of TS_ALL can be inverted.
ORCA Series 2 FPGAs
The following occur when TS_ALL is activated:
1. All of the user I/O output buffers are 3-stated, the
user I/O input buffers are pulled up (with the pulldown disabled), and the input buffers are configured
with TTL input thresholds (OR2CxxA only).
2. The TDO/RD_DATA output buffer is 3-stated.
3. The RD_CFG, RESET, and PRGM input buffers remain
active with a pull-up.
4. The DONE output buffer is 3-stated, and the input
buffer is pulled-up.
Internal Oscillator
The internal oscillator resides in the lower-left corner of
the FPGA array. It has output clock frequencies of
1.25 MHz and 10 MHz. The internal oscillator is the
source of the internal CCLK used for configuration. It
may also be used after configuration as a generalpurpose clock signal.
Lattice Semiconductor
The RESET input pad has a special relationship to
GSRN. During configuration, the RESET input pad
always initiates a configuration abort, as described in
the FPGA States of Operation section. After configuration, the global set/reset signal (GSRN) can either be
disabled (the default), directly connected to the RESET
input pad, or sourced by a lower-right corner signal. If
the RESET input pad is not used as a global reset after
configuration, this pad can be used as a normal input
pad.
Start-Up Logic
The start-up logic block is located in the lower right corner of the FPGA. This block can be configured to coordinate the relative timing of the release of GSRN, the
activation of all user I/Os, and the assertion of the
DONE signal at the end of configuration. If a start-up
clock is used to time these events, the start-up clock
can come from CCLK, or it can be routed into the startup block using lower-right corner routing resources.
These signals are described in the Start-Up subsection
of the FPGA States of Operation section.
55
Data Sheet
November 2006
ORCA Series 2 FPGAs
Special Function Blocks (continued)
s
TMS TDI
TCK
TDO
Boundary Scan
U2
The increasing complexity of integrated circuits (ICs)
and IC packages has increased the difficulty of testing
printed-circuit boards (PCBs). To address this testing
problem, the IEEE standard 1149.1 - 1990 (IEEE Standard Test Access Port and Boundary-Scan Architecture) is implemented in the ORCA series of FPGAs. It
allows users to efficiently test the interconnection
between integrated circuits on a PCB as well as test
the integrated circuit itself. The IEEE 1149.1 standard
is a well-defined protocol that ensures interoperability
among boundary-scan (BSCAN) equipped devices
from different vendors.
TMS TDI
TCK
TDO
net a
net b
U1
net c
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TDI
TMS
TCK
TDO
TMS TDI
TCK
TDO
U3
Figure 48 provides a system interface for components
used in the boundary-scan testing of PCBs. The three
major components shown are the test host, boundaryscan support circuit, and the devices under test
(DUTs). The DUTs shown here are ORCA Series
FPGAs with dedicated boundary-scan circuitry. The
test host is normally one of the following: automatic test
equipment (ATE), a workstation, a PC, or a microprocessor.
56
U4
SEE ENLARGED VIEW BELOW
TDO TCK TMS TDI
The IEEE 1149.1 standard defines a test access port
(TAP) that consists of a 4-pin interface with an optional
reset pin for boundary-scan testing of integrated circuits in a system. The ORCA series FPGA provides
four interface pins: test data in (TDI), test mode select
(TMS), test clock (TCK), and test data out (TDO). The
PRGM pin used to reconfigure the device also resets
the boundary-scan logic.
The user test host serially loads test commands and
test data into the FPGA through these pins to drive outputs and examine inputs. In the configuration shown in
Figure 47, where boundary scan is used to test ICs,
test data is transmitted serially into TDI of the first
BSCAN device (U1), through TDO/TDI connections
between BSCAN devices (U2 and U3), and out TDO of
the last BSCAN device (U4). In this configuration, the
TMS and TCK signals are routed to all boundary-scan
ICs in parallel so that all boundary-scan components
operate in the same state. In other configurations, multiple scan paths are used instead of a single ring. When
multiple scan paths are used, each ring is independently controlled by its own TMS and TCK signals.
TMS TDI
TCK
TDO
PT[ij]
TAPC
BYPASS
REGISTER
BSC
SCAN
IN
BDC DCC
P_IN
P_TS
P_OUT
INSTRUCTION
REGISTER
SCAN
OUT
PL[ij]
SCAN
IN
BSC
P_TS
DCC
P_OUT
BDC
SCAN
OUT
P_IN
PLC
ARRAY
P_OUT
P_TS
P_IN
SCAN
IN
BSC
DCC BDC
PR[ij]
BDC
DCC
SCAN
OUT
P_OUT
P_TS
P_IN
SCAN
OUT
BSC
SCAN
IN
PB[ij]
ENLARGED VIEW
Fig.34.a(F).1C
Key:
BSC = boundary-scan cell, BDC = bidirectional data cell,
and DCC = data control cell.
Figure 47. Printed-Circuit Board with BoundaryScan Circuitry
The boundary-scan support circuit shown in Figure 48
is the 497AA Boundary-Scan Master (BSM). The BSM
off-loads tasks from the test host to increase test
throughput. To interface between the test host and the
DUTs, the BSM has a general microprocessor interface
and provides parallel-to-serial/serial-to-parallel conversion, as well as three 8K data buffers.
Lattice Semiconductor
Data Sheet
November 2006
ORCA Series 2 FPGAs
Special Function Blocks (continued)
CCLK
A[17:0]
DIN
DIN
DOUT
ORCA
SERIES
FPGA
MASTER
ORCA
SERIES
FPGA
SLAVE #1
DOUT
ORCA
SERIES
FPGA
SLAVE #2
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EPROM
CCLK
CCLK
DOUT
A[17:0]
D[7:0]
D[7:0]
OE
CE
DONE
DONE
PRGM
PROGRAM
VDD
VDD OR
GND
INIT
M2
M1
M0
VDD
HDC
LDC
RCLK
PRGM
M2
M1
M0
VDD
DONE
INIT
HDC
LDC
RCLK
VDD
PRGM
M2
M1
M0
INIT
HDC
LDC
RCLK
VDD
5-4488(F)
Figure 48. Boundary-Scan Interface
The BSM also increases test throughput with a dedicated automatic test-pattern generator and with compression of the test response with a signature analysis
register. The PC-based boundary-scan test card/software allows a user to quickly prototype a boundaryscan test setup.
Boundary-Scan Instructions
The ORCA Series boundary-scan circuitry is used for
three mandatory IEEE 1149.1 tests (EXTEST, SAMPLE/PRELOAD, BYPASS) and four ORCA-defined
instructions. The 3-bit wide instruction register supports
the eight instructions listed in Table 12.
Table 12. Boundary-Scan Instructions
Code
000
001
010
011
100
101
110
111
Instruction
EXTEST
PLC Scan Ring 1
RAM Write (RAM_W)
Reserved
SAMPLE/PRELOAD
PLC Scan Ring 2
RAM Read (RAM_R)
BYPASS
Lattice Semiconductor
The external test (EXTEST) instruction allows the interconnections between ICs in a system to be tested for
opens and stuck-at faults. If an EXTEST instruction is
performed for the system shown in Figure 47, the connections between U1 and U2 (shown by nets a, b, and
c) can be tested by driving a value onto the given nets
from one device and then determining whether the
same value is seen at the other device. This is determined by shifting 2 bits of data for each pin (one for the
output value and one for the 3-state value) through the
BSR until each one aligns to the appropriate pin.
Then, based upon the value of the 3-state signal, either
the I/O pad is driven to the value given in the BSR, or
the BSR is updated with the input value from the I/O
pad, which allows it to be shifted out TDO.
The SAMPLE instruction is useful for system debugging and fault diagnosis by allowing the data at the
FPGA’s I/Os to be observed during normal operation.
The data for all of the I/Os is captured simultaneously
into the BSR, allowing them to be shifted-out TDO to
the test host. Since each I/O buffer in the PICs is bidirectional, two pieces of data are captured for each I/O
pad: the value at the I/O pad and the value of the
3-state control signal.
57
Data Sheet
November 2006
ORCA Series 2 FPGAs
Special Function Blocks (continued)
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There are four ORCA-defined instructions. The PLC
scan rings 1 and 2 (PSR1, PSR2) allow user-defined
internal scan paths using the PLC latches/FFs. The
RAM_Write Enable (RAM_W) instruction allows the
user to serially configure the FPGA through TDI. The
RAM_Read Enable (RAM_R) allows the user to read
back RAM contents on TDO after configuration.
The BSR is a series connection of boundary-scan cells
(BSCs) around the periphery of the IC. Each I/O pad on
the FPGA, except for CCLK, DONE, and the boundaryscan pins (TCK, TDI, TMS, and TDO), is included in the
BSR. The first BSC in the BSR (connected to TDI) is
located in the first PIC I/O pad on the left of the top side
of the FPGA (PTA PIC). The BSR proceeds clockwise
around the top, right, bottom, and left sides of the array.
The last BSC in the BSR (connected to TDO) is located
on the top of the left side of the array (PLA3).
ORCA Boundary-Scan Circuitry
The ORCA Series boundary-scan circuitry includes a
test access port controller (TAPC), instruction register
(IR), boundary-scan register (BSR), and bypass register. It also includes circuitry to support the four predefined instructions.
Figure 49 shows a functional diagram of the boundaryscan circuitry that is implemented in the ORCA series.
The input pins’ (TMS, TCK, and TDI) locations vary
depending on the part, and the output pin is the dedicated TDO/RD_DATA output pad. Test data in (TDI) is
the serial input data. Test mode select (TMS) controls
the boundary-scan test access port controller (TAPC).
Test clock (TCK) is the test clock on the board.
The bypass instruction uses a single FF which resynchronizes test data that is not part of the current scan
operation. In a bypass instruction, test data received on
TDI is shifted out of the bypass register to TDO. Since
the BSR (which requires a two FF delay for each pad)
is bypassed, test throughput is increased when devices
that are not part of a test operation are bypassed.
The boundary-scan logic is enabled before and during
configuration. After configuration, a configuration
option determines whether or not boundary-scan logic
is used.
The 32-bit boundary-scan identification register contains the manufacturer’s ID number, unique part number, and version, but is not implemented in the ORCA
series of FPGAs. If boundary scan is not used, TMS,
TDI, and TCK become user I/Os, and TDO is 3-stated
or used in the readback operation.
I/O BUFFERS
DATA REGISTERS
BOUNDARY-SCAN REGISTER
PSR1 REGISTER (PLCs)
PSR2 REGISTER (PLCs)
VDD
TDI
DATA
MUX
CONFIGURATION REGISTER
(RAM_R, RAM_W)
BYPASS REGISTER
INSTRUCTION DECODER
VDD
RESET
CLOCK-DR
SHIFT-DR
UPDATE-DR
TMS
M
U
X
INSTRUCTION REGISTER
TDO
RESET
CLOCK-IR
SHIFT-IR
UPDATE-IR
VDD
SELECT
ENABLE
TCK
VDD
TAP
CONTROLLER
PUR
PRGM
5-2840(C).r7
58
Figure 49. ORCA Series Boundary-Scan Circuitry Functional Diagram
Lattice Semiconductor
Data Sheet
November 2006
ORCA Series 2 FPGAs
Special Function Blocks (continued)
ORCA Series TAP Controller (TAPC)
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The ORCA Series TAP controller (TAPC) is a 1149.1
compatible test access port controller. The 16 JTAG
state assignments from the IEEE 1149.1 specification
are used. The TAPC is controlled by TCK and TMS. The
TAPC states are used for loading the IR to allow three
basic functions in testing: providing test stimuli
(Update-DR), test execution (Run-Test/Idle), and
obtaining test responses (Capture-DR). The TAPC
allows the test host to shift in and out both instructions
and test data/results. The inputs and outputs of the
TAPC are provided in the table below. The outputs are
primarily the control signals to the instruction register
and the data register.
The TAPC generates control signals which allow capture, shift, and update operations on the instruction and
data registers. In the capture operation, data is loaded
into the register. In the shift operation, the captured
data is shifted out while new data is shifted in. In the
update operation, either the instruction register is
loaded for instruction decode, or the boundary-scan
register is updated for control of outputs.
Table 13. TAP Controller Input/Outputs
The test host generates a test by providing input into
the ORCA Series TMS input synchronous with TCK.
This sequences the TAPC through states in order to
perform the desired function on the instruction register
or a data register. Figure 50 provides a diagram of the
state transitions for the TAPC. The next state is determined by the TMS input value.
1
TEST-LOGICRESET
0
RUN-TEST/
IDLE
0
Symbol
I/O
TMS
I
Function
Test Mode Select
TCK
I
Test Clock
PUR
I
Powerup Reset
PRGM
I
BSCAN Reset
TRESET
O
Test Logic Reset
Select
O
Select IR (high); Select DR (low)
Enable
O
Test Data Out Enable
1
1
SELECTDR-SCAN
0
1
O
Capture/Parallel Load DR
Capture-IR
O
Capture/Parallel Load IR
Shift-DR
O
Shift Data Register
Shift-DR
O
Shift Instruction Register
Update-DR
O
Update/Parallel Load DR
Update-IR
O
Update/Parallel Load IR
Lattice Semiconductor
CAPTURE-IR
0
0
0
SHIFT-DR
SHIFT-IR
0
1
1
1
EXIT1-DR
EXIT1-IR
1
0
0
0
PAUSE-IR
0
1
1
0
1
0
1
CAPTURE-DR
PAUSE-DR
Capture-DR
SELECTIR-SCAN
0
EXIT2-DR
EXIT2-IR
1
1
UPDATE-DR
UPDATE-IR
1
1
0
0
5-5370(F)
Figure 50. TAP Controller State Transition Diagram
59
Data Sheet
November 2006
ORCA Series 2 FPGAs
Special Function Blocks (continued)
Boundary-Scan Cells
The TAPC signals (capture, update, shiftn, treset, and
TCK) and the MODE signal control the operation of the
BSC. The bidirectional data cell is also controlled by
the high out/low in (HOLI) signal generated by the
direction control cell. When HOLI is low, the bidirectional data cell receives input buffer data into the BSC.
When HOLI is high, the BSC is loaded with functional
data from the PLC.
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Figure 51 is a diagram of the boundary-scan cell (BSC)
in the ORCA series PICs. There are four BSCs in each
PIC: one for each pad, except as noted above. The
BSCs are connected serially to form the BSR. The BSC
controls the functionality of the in, out, and 3-state signals for each pad.
direction control cell is used to access the 3-state
value. Both cells consist of a flip-flop used to shift scan
data which feeds a flip-flop to control the I/O buffer. The
bidirectional data cell is connected serially to the direction control cell to form a boundary-scan shift register.
The BSC allows the I/O to function in either the normal
or test mode. Normal mode is defined as when an output buffer receives input from the PLC array and provides output at the pad or when an input buffer
provides input from the pad to the PLC array. In the test
mode, the BSC executes a boundary-scan operation,
such as shifting in scan data from an upstream BSC in
the BSR, providing test stimuli to the pad, capturing
test data at the pad, etc.
The primary functions of the BSC are shifting scan data
serially in the BSR and observing input (P_IN), output
(P_OUT), and 3-state (P_TS) signals at the pads. The
BSC consists of two circuits: the bidirectional data cell
is used to access the input and output data, and the
The MODE signal is generated from the decode of the
instruction register. When the MODE signal is high
(EXTEST), the scan data is propagated to the output
buffer. When the MODE signal is low (BYPASS or
SAMPLE), functional data from the FPGA’s internal
logic is propagated to the output buffer.
The boundary-scan description language (BSDL) is
provided for each device in the ORCA series of FPGAs.
The BSDL is generated from a device profile, pinout,
and other boundary-scan information.
SCAN IN
I/O BUFFER
PAD_IN
P_IN
PAD_OUT
BIDIRECTIONAL DATA CELL
0
0
0
D
1
Q
D
Q
1
PAD_TS
1
P_OUT
HOLI
0
0
P_TS
D
Q
D
Q
1
1
DIRECTION CONTROL CELL
SHIFTN/CAPTURE
TCK
SCAN OUT UPDATE/TCK
MODE
5-2844(F).r4
Figure 51. Boundary-Scan Cell
60
Lattice Semiconductor
Data Sheet
November 2006
ORCA Series 2 FPGAs
RUN-TEST/IDLE
UPDATE-IR
EXIT1-IR
SHIFT-IR
EXIT2-IR
PAUSE-IR
EXIT1-IR
SHIFT-IR
CAPTURE-IR
SELECT-IR-SCAN
SELECT-DR-SCAN
RUN-TEST/IDLE
SE
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TEST-LOGIC-RESET
Special Function Blocks (continued)
TCK
TMS
TDI
Fig.5.3(F)
Figure 52. Instruction Register Scan Timing Diagram
Boundary-Scan Timing
To ensure race-free operation, data changes on specific clock edges. The TMS and TDI inputs are clocked in on
the rising edge of TCK, while changes on TDO occur on the falling edge of TCK. In the execution of an EXTEST
instruction, parallel data is output from the BSR to the FPGA pads on the falling edge of TCK. The maximum frequency allowed for TCK is 10 MHz.
Figure 52 shows timing waveforms for an instruction scan operation. The diagram shows the use of TMS to
sequence the TAPC through states. The test host (or BSM) changes data on the falling edge of TCK, and it is
clocked into the DUT on the rising edge.
Lattice Semiconductor
61
Data Sheet
November 2006
ORCA Series 2 FPGAs
ORCA Timing Characteristics
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To define speed grades, the ORCA Series part number
designation (see Table 54) uses a single-digit number
to designate a speed grade. This number is not related
to any single ac parameter. Higher numbers indicate a
faster set of timing parameters. The actual speed sorting is based on testing the delay in a path consisting of
an input buffer, combinatorial delay through all PLCs in
a row, and an output buffer. Other tests are then done
to verify other delay parameters, such as routing
delays, setup times to FFs, etc.
Table 14A and 14B and provide approximate power
supply and junction temperature derating for OR2CxxA
commercial and industrial devices. Table 15A and 15B
provides the same information for the OR2TxxA and
OR2TxxB devices (both commercial and industrial).
The delay values in this data sheet and reported by
ispLEVER are shown as 1.00 in the tables. The method
for determining the maximum junction temperature is
defined in the Thermal Characteristics section. Taken
cumulatively, the range of parameter values for bestcase vs. worst-case processing, supply voltage, and
junction temperature can approach 3 to 1.
The most accurate timing characteristics are reported
by the timing analyzer in the ispLEVER development
system. A timing report provided by the development
system after layout divides path delays into logic and
routing delays. The timing analyzer can also provide
logic delays prior to layout. While this allows routing
budget estimates, there is wide variance in routing
delays associated with different layouts.
The logic timing parameters noted in the Electrical
Characteristics section of this data sheet are the same
as those in the design tools. In the PFU timing given in
Tables 31—79, symbol names are generally a concatenation of the PFU operating mode (as defined in
Table 5) and the parameter type. The wildcard character (*) is used in symbol names to indicate that the
parameter applies to any sub-LUT. The setup, hold,
and propagation delay parameters, defined below, are
designated in the symbol name by the SET, HLD, and
DEL characters, respectively.
The values given for the parameters are the same as
those used during production testing and speed binning of the devices. The junction temperature and supply voltage used to characterize the devices are listed
in the delay tables. Actual delays at nominal temperature and voltage for best-case processes can be much
better than the values given.
It should be noted that the junction temperature used in
the tables is generally 85 °C. The junction temperature
for the FPGA depends on the power dissipated by the
device, the package thermal characteristics (ΘJA), and
the ambient temperature, as calculated in the following
equation and as discussed further in the Package
Thermal Characteristics section:
TJmax = TAmax + (P • ΘJA) °C
Table 14A. Derating for Commercial Devices
(OR2CxxA)
TJ
(°C)
0
25
85
100
125
Power Supply Voltage
4.75 V
0.81
0.85
1.00
1.05
1.12
5.0 V
0.79
0.83
0.97
1.02
1.09
5.25 V
0.77
0.81
0.95
1.00
1.07
Table 14B. Derating for Industrial Devices
(OR2CxxA)
TJ
(°C)
–40
0
25
85
100
125
Power Supply Voltage
4.5 V
0.71
0.80
0.84
1.00
1.05
1.12
4.75 V
0.70
0.78
0.82
0.97
1.01
1.09
5.0 V
0.68
0.76
0.80
0.94
0.99
1.06
5.25 V
0.66
0.74
0.78
0.93
0.97
1.04
5.5 V
0.65
0.73
0.77
0.91
0.95
1.02
Table 15A. Derating for Commercial/Industrial
Devices (OR2TxxA)
TJ
(°C)
–40
0
25
85
100
125
Power Supply Voltage
3.0 V
0.73
0.82
0.87
1.00
1.04
1.10
3.3 V
0.66
0.73
0.78
0.90
0.94
1.00
3.6 V
0.61
0.68
0.72
0.83
0.87
0.92
Note: The user must determine this junction temperature to see if the delays from ispLEVER should
be derated based on the following derating
tables.
62
Lattice Semiconductor
Data Sheet
November 2006
ORCA Series 2 FPGAs
ORCA Timing Characteristics
transition of a clock or latch enable signal, during
which the data must be stable to ensure it is recognized as the intended value.
(continued)
■
Hold Time—the interval immediately following the
transition of a clock or latch enable signal, during
which the data must be held stable to ensure it is recognized as the intended value.
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Table 15B. Derating for Commercial/Industrial
Devices (OR2TxxB)
Power Supply Voltage
TJ
(°C) 3.0 V
3.15 V
3.3 V
3.45 V
3.6 V
–40
0
25
85
100
125
0.81
0.86
0.9
1.0
1.02
1.06
0.78
0.83
0.87
0.95
0.98
1.03
0.76
0.80
0.83
0.93
0.95
0.98
0.74
0.77
0.8
0.88
0.91
0.95
0.73
0.76
0.78
0.86
0.88
0.92
Note: The derating tables shown above are for a typical critical path
that contains 33% logic delay and 66% routing delay. Since the
routing delay derates at a higher rate than the logic delay, paths
with more than 66% routing delay will derate at a higher rate
than shown in the table. The approximate derating values vs.
temperature are 0.26% per °C for logic delay and 0.45% per °C
for routing delay. The approximate derating values vs. voltage
are 0.13% per mV for both logic and routing delays at 25 °C.
In addition to supply voltage, process variation, and
operating temperature, circuit and process improvements of the ORCA series FPGAs over time will result
in significant improvement of the actual performance
over those listed for a speed grade. Even though lower
speed grades may still be available, the distribution of
yield to timing parameters may be several speed bins
higher than that designated on a product brand. Design
practices need to consider best-case timing parameters (e.g., delays = 0), as well as worst-case timing.
The routing delays are a function of fan-out and the
capacitance associated with the CIPs and metal interconnect in the path. The number of logic elements that
can be driven (or fan-out) by PFUs is unlimited,
although the delay to reach a valid logic level can
exceed timing requirements. It is difficult to make accurate routing delay estimates prior to design compilation
based on fan-out. This is because the CAE software
may delete redundant logic inserted by the designer to
reduce fan-out, and/or it may also automatically reduce
fan-out by net splitting.
The waveform test points are given in the Measurement Conditions section of this data sheet. The timing
parameters given in the electrical characteristics tables
in this data sheet follow industry practices, and the values they reflect are described below.
■
■
Propagation Delay—the time between the specified
reference points. The delays provided are the worst
case of the tphh and tpll delays for noninverting functions, tplh and tphl for inverting functions, and tphz
and tplz for 3-state enable.
Setup Time—the interval immediately preceding the
Lattice Semiconductor
■
3-state Enable—the time from when a TS[3:0] signal
becomes active and the output pad reaches the highimpedance state.
Estimating Power Dissipation
OR2CxxA
The total operating power dissipated is estimated by
summing the standby (IDDSB), internal, and external
power dissipated. The internal and external power is
the power consumed in the PLCs and PICs, respectively. In general, the standby power is small and may
be neglected. The total operating power is as follows:
PT = Σ PPLC + Σ PPIC
The internal operating power is made up of two parts:
clock generation and PFU output power. The PFU output power can be estimated based upon the number of
PFU outputs switching when driving an average fan-out
of two:
PPFU = 0.16 mW/MHz
For each PFU output that switches, 0.16 mW/MHz
needs to be multiplied times the frequency (in MHz)
that the output switches. Generally, this can be estimated by using one-half the clock rate, multiplied by
some activity factor; for example, 20%.
The power dissipated by the clock generation circuitry
is based upon four parts: the fixed clock power, the
power/clock branch row or column, the clock power dissipated in each PFU that uses this particular clock, and
the power from the subset of those PFUs that is configured in either of the two synchronous modes (SSPM or
SDPM). Therefore, the clock power can be calculated
for the four parts using the following equations:
OR2C04A Clock Power
P
= [0.62 mW/MHz
+ (0.22 mW/MHz – Branch) (# Branches)
+ (0.022 mW/MHz – PFU) (# PFUs)
+ (0.006 mW/MHz – SMEM_PFU)
(# SMEM_PFUs)] fCLK
For a quick estimate, the worst-case (typical circuit)
OR2C04A clock power ≈ 3.9 mW/MHz.
63
Data Sheet
November 2006
ORCA Series 2 FPGAs
Estimating Power Dissipation (continued)
+ (0.022 mW/MHz – PFU) (# PFUs)
+ (0.006 mW/MHz – SMEM_PFU)
(# SMEM_PFUs)] fCLK
OR2C06A Clock Power
= [0.63 mW/MHz
+ (0.25 mW/MHz – Branch) (# Branches)
+ (0.022 mW/MHz – PFU) (# PFUs)
+ (0.006 mW/MHz – SMEM_PFU)
(# SMEM_PFUs)] fCLK
For a quick estimate, the worst-case (typical circuit)
OR2C26A clock power ≈ 17.8 mW/MHz.
OR2C40A Clock Power
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P
For a quick estimate, the worst-case (typical circuit)
OR2C06A clock power ≈ 5.3 mW/MHz.
OR2C08A Clock Power
P
= [0.65 mW/MHz
+ (0.29 mW/MHz – Branch) (# Branches)
+ (0.022 mW/MHz – PFU) (# PFUs)
+ (0.006 mW/MHz – SMEM_PFU)
(# SMEM_PFUs)] fCLK
For a quick estimate, the worst-case (typical circuit)
OR2C08A clock power ≈ 6.6 mW/MHz.
OR2C10A Clock Power
P
= [0.66 mW/MHz
+ (0.32 mW/MHz – Branch) (# Branches)
+ (0.022 mW/MHz – PFU) (# PFUs)
+ (0.006 mW/MHz – SMEM_PFU)
(# SMEM_PFUs)] fCLK
For a quick estimate, the worst-case (typical circuit)
OR2C10A clock power ≈ 8.6 mW/MHz.
OR2C12A Clock Power
P
= [0.68 mW/MHz
+ (0.35 mW/MHz – Branch) (# Branches)
+ (0.022 mW/MHz – PFU) (# PFUs)
+ (0.006 mW/MHz – SMEM_PFU)
(# SMEM_PFUs)] fCLK
For a quick estimate, the worst-case (typical circuit)
OR2C12A clock power ≈ 10.5 mW/MHz.
OR2C15A Clock Power
P
= [0.69 mW/MHz
+ (0.38 mW/MHz – Branch) (# Branches)
+ (0.022 mW/MHz – PFU) (# PFUs)
+ (0.006 mW/MHz – SMEM_PFU)
(# SMEM_PFUs)] fCLK
For a quick estimate, the worst-case (typical circuit)
OR2C15A clock power ≈ 12.7 mW/MHz.
OR2C26A Clock Power
P
64
= [0.73 mW/MHz
+ (0.44 mW/MHz – Branch) (# Branches)
P
= [0.77 mW/MHz
+ (0.53 mW/MHz – Branch) (# Branches)
+ (0.022 mW/MHz – PFU) (# PFUs)
+ (0.006 mW/MHz – SMEM_PFU)
(# SMEM_PFUs)] fCLK
For a quick estimate, the worst-case (typical circuit)
OR2C40A clock power ≈ 26.6 mW/MHz.
The power dissipated in a PIC is the sum of the power
dissipated in the four I/Os in the PIC. This consists of
power dissipated by inputs and ac power dissipated by
outputs. The power dissipated in each I/O depends on
whether it is configured as an input, output, or input/
output. If an I/O is operating as an output, then there is
a power dissipation component for PIN, as well as
POUT. This is because the output feeds back to the
input.
The power dissipated by a TTL input buffer is estimated
as:
PTTL = 2.2 mW + 0.17 mW/MHz
The power dissipated by an input buffer is estimated
as:
PCMOS = 0.17 mW/MHz
The ac power dissipation from an output or bidirectional is estimated by the following:
POUT = (CL + 8.8 pF) x VDD2 x F Watts
where the unit for CL is farads, and the unit for F is Hz.
As an example of estimating power dissipation,
suppose that a fully utilized OR2C15A has an average
of three outputs for each of the 400 PFUs, that all
20 clock branches are used, that 150 of the 400 PFUs
have FFs clocked at 40 MHz (16 of which are operating
in a synchronous memory mode), and that the PFU
outputs have an average activity factor of 20%.
Twenty TTL-configured inputs, 20 CMOS-configured
inputs, 32 outputs driving 30 pF loads, and 16 bidirectional I/Os driving 50 pF loads are also generated from
the 40 MHz clock with an average activity factor of
20%. The worst-case (VDD = 5.25 V) power dissipation
is estimated as follows:
PPFU = 400 x 3 (0.16 mW/MHz x 20 MHz x 20%)
= 768 mW
Lattice Semiconductor
Data Sheet
November 2006
Estimating Power Dissipation (continued)
SDPM). Therefore, the clock power can be calculated
for the four parts using the following equations:
OR2T04A Clock Power
P
= [0.29 mW/MHz
+ (0.10 mW/MHz – Branch) (# Branches)
+ (0.01 mW/MHz – PFU) (# PFUs)
+ (0.003 mW/MHz – SMEM_PFU)
(# SMEM_PFUs)] fCLK
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PCLK = [0.69 mW/MHz + (0.38 mW/MHz – Branch)
(20 Branches)
+ (0.022 mW/MHz – PFU) (150 PFUs)
+ (0.006 mW/MHz – SMEM_PFU)
(16 SMEM_PFUs)] [40 MHz]
= 427 mW
ORCA Series 2 FPGAs
PTTL
= 20 x [2.2 mW + (0.17 mW/MHz x 20 MHz
x 20%)]
= 57 mW
PCMOS = 20 x [0.17 mW x 20 MHz x 20%]
= 13 mW
For a quick estimate, the worst-case (typical circuit)
OR2T04A clock power ≈ 1.8 mW/MHz.
OR2T08A Clock Power
P
POUT = 30 x [(30 pF + 8.8 pF) x (5.25)2 x 20 MHz
x 20%]
= 128 mW
PBID
= 16 x [(50 pF + 8.8 pF) x (5.25)2 x 20 MHz
x 20%]
= 104 mW
= [0.31 mW/MHz
+ (0.12 mW/MHz – Branch) (# Branches)
+ (0.01 mW/MHz – PFU) (# PFUs)
+ (0.003 mW/MHz – SMEM_PFU)
(# SMEM_PFUs)] fCLK
For a quick estimate, the worst-case (typical circuit)
OR2T08A clock power ≈ 3.2 mW/MHz.
OR2T10A Clock Power
TOTAL = 1.50 W
P
OR2TxxA
The total operating power dissipated is estimated by
summing the standby (IDDSB), internal, and external
power dissipated. The internal and external power is
the power consumed in the PLCs and PICs, respectively. In general, the standby power is small and may
be neglected. The total operating power is as follows:
= [0.32 mW/MHz
+ (0.14 mW/MHz – Branch) (# Branches)
+ (0.01 mW/MHz – PFU) (# PFUs)
+ (0.003 mW/MHz – SMEM_PFU)
(# SMEM_PFUs)] fCLK
For a quick estimate, the worst-case (typical circuit)
OR2T10A clock power ≈ 4.0 mW/MHz.
PT = Σ PPLC + Σ PPIC
The internal operating power is made up of two parts:
clock generation and PFU output power. The PFU output power can be estimated based upon the number of
PFU outputs switching when driving an average fan-out
of two:
PPFU = 0.08 mW/MHz
For each PFU output that switches, 0.08 mW/MHz
needs to be multiplied times the frequency (in MHz)
that the output switches. Generally, this can be estimated by using one-half the clock rate, multiplied by
some activity factor; for example, 20%.
The power dissipated by the clock generation circuitry
is based upon four parts: the fixed clock power, the
power/clock branch row or column, the clock power dissipated in each PFU that uses this particular clock, and
the power from the subset of those PFUs that is configured in either of the two synchronous modes (SSPM or
Lattice Semiconductor
65
Data Sheet
November 2006
ORCA Series 2 FPGAs
Estimating Power Dissipation (continued)
Table 16. DC Power for 5 V Tolerant I/Os for
OR2TxxA devices
OR2T15A Clock Power
= [0.34 mW/MHz
+ (0.17 mW/MHz – Branch) (# Branches)
+ (0.01 mW/MHz – PFU) (# PFUs)
+ (0.003 mW/MHz – SMEM_PFU)
(# SMEM_PFUs)] fCLK
Device
PTOL (VDD5 = 5.25 V)
2T04A
2T08A
2T10A
2T15A
2T26A
2T40A
1.7 mW
2.4 mW
2.7 mW
3.4 mW
4.0 mW
5.0 mW
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For a quick estimate, the worst-case (typical circuit)
OR2T15A clock power ≈ 5.9 mW/MHz.
OR2T26A Clock Power
P
= [0.35 mW/MHz
+ (0.19 mW/MHz – Branch) (# Branches)
+ (0.01 mW/MHz – PFU) (# PFUs)
+ (0.003 mW/MHz – SMEM_PFU)
(# SMEM_PFUs)] fCLK
For a quick estimate, the worst-case (typical circuit)
OR2T26A clock power ≈ 8.3 mW/MHz.
OR2T40A Clock Power
P
= [0.37 mW/MHz
+ (0.23 mW/MHz – Branch) (# Branches)
+ (0.01 mW/MHz – PFU) (# PFUs)
+ (0.003 mW/MHz – SMEM_PFU)
(# SMEM_PFUs)] fCLK
For a quick estimate, the worst-case (typical circuit)
OR2T40A clock power ≈ 12.4 mW/MHz.
The power dissipated in a PIC is the sum of the power
dissipated in the four I/Os in the PIC. This consists of
power dissipated by inputs and ac power dissipated by
outputs. The power dissipated in each I/O depends on
whether it is configured as an input, output, or input/
output. If an I/O is operating as an output, then there is
a power dissipation component for PIN, as well as
POUT. This is because the output feeds back to the
input.
The power dissipated by an input buffer (VIH = VDD –
0.3 V or higher) is estimated as:
PIN = 0.09 mW/MHz
The 5 V tolerant input buffer feature dissipates additional dc power. The dc power, PTOL, is always dissipated for the OR2TxxA, regardless of the number of
5 V tolerant input buffers used when the VDD5 pins are
connected to a 5 V supply as shown in Table 16. This
power is not dissipated when the VDD5 pins are connected to the 3.3 V supply.
The ac power dissipation from an output or bidirectional is estimated by the following:
POUT = (CL + 8.8 pF) x VDD2 x F Watts
where the unit for CL is farads, and the unit for F is Hz.
As an example of estimating power dissipation,
suppose that a fully utilized OR2T15A has an average
of three outputs for each of the 400 PFUs, that all
20 clock branches are used, that 150 of the 400 PFUs
have FFs clocked at 40 MHz (16 of which are operating
in a synchronous memory mode), and that the PFU
outputs have an average activity factor of 20%.
Twenty inputs, 32 outputs driving 30 pF loads, and
16 bidirectional I/Os driving 50 pF loads are also generated from the 40 MHz clock with an average activity
factor of 20%. The worst-case (VDD = 3.6 V) power dissipation is estimated as follows:
PPFU = 400 x 3 (0.08 mW/MHz x 20 MHz x 20%)
= 384 mW
PCLK = [0.34 mW/MHz + (0.17 mW/MHz – Branch)
(20 Branches)
+ (0.01 mW/MHz – PFU) (150 PFUs)
+ (0.003 mW/MHz – SMEM_PFU)
(16 SMEM_PFUs)] [40 MHz]
= 212 mW
PIN
= 20 x [0.09 mW/MHz x 20 MHz x 20%]
= 7 mW
PTOL
= 3.4 mW
POUT = 30 x [(30 pF + 8.8 pF) x (3.6)2 x 20 MHz
x 20%]
= 60 mW
PBID
= 16 x [(50 pF + 8.8 pF) x (3.6)2 x 20 MHz
x 20%]
= 49 mW
TOTAL = 0.72 W
66
Lattice Semiconductor
Data Sheet
November 2006
Estimating Power Dissipation (continued)
OR2T15B and OR2T40B
power dissipated by inputs and ac power dissipated by
outputs. The power dissipated in each I/O depends on
whether it is configured as an input, output, or input/
output. If an I/O is operating as an output, then there is
a power dissipation component for PIN, as well as
POUT. This is because the output feeds back to the
input.
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The total operating power dissipated is estimated by
summing the standby (IDDSB), internal, and external
power dissipated. The internal and external power is
the power consumed in the PLCs and PICs, respectively. In general, the standby power is small and may
be neglected. The total operating power is as follows:
ORCA Series 2 FPGAs
PT = Σ PPLC + Σ PPIC
The internal operating power is made up of two parts:
clock generation and PFU output power. The PFU output power can be estimated based upon the number of
PFU outputs switching when driving an average fan-out
of two:
PPFU = 0.08 mW/MHz
For each PFU output that switches, 0.08 mW/MHz
needs to be multiplied times the frequency (in MHz)
that the output switches. Generally, this can be estimated by using one-half the clock rate, multiplied by
some activity factor; for example, 20%.
The power dissipated by the clock generation circuitry
is based upon four parts: the fixed clock power, the
power/clock branch row or column, the clock power dissipated in each PFU that uses this particular clock, and
the power from the subset of those PFUs that is configured in either of the two synchronous modes (SSPM or
SDPM). Therefore, the clock power can be calculated
for the four parts using the following equations:
OR2T15B Clock Power
P
= [0.30 mW/MHz
+ (0.85 mW/MHz – Branch) (# Branches)
+ (0.008 mW/MHz – PFU) (# PFUs)
+ (0.002 mW/MHz – SMEM_PFU)
(# SMEM_PFUs)] fCLK
For a quick estimate, the worst-case (typical circuit)
OR2T15B clock power ≈ 3.9 mW/MHz.
The power dissipated by an input buffer (VIH = VDD –
0.3 V or higher) is estimated as:
PIN = 0.033 mW/MHz
The OR2TxxB 5 V tolerant input buffer feature does not
dissipate additional dc power.
The ac power dissipation from an output or bidirectional is estimated by the following:
POUT = (CL + 8.8 pF) x VDD2 x F Watts
where the unit for CL is farads, and the unit for F is Hz.
As an example of estimating power dissipation,
suppose that a fully utilized OR2T15B has an average
of three outputs for each of the 400 PFUs, that all
20 clock branches are used, that 150 of the 400 PFUs
have FFs clocked at 40 MHz (16 of which are operating
in a synchronous memory mode), and that the PFU
outputs have an average activity factor of 20%.
Twenty inputs, 32 outputs driving 30 pF loads, and
16 bidirectional I/Os driving 50 pF loads are also generated from the 40 MHz clock with an average activity
factor of 20%. The worst-case (VDD = 3.6 V) power dissipation is estimated as follows:
PPFU = 400 x 3 (0.08 mW/MHz x 20 MHz x 20%)
= 384 mW
PCLK = [0.30 mW/MHz + (0.085 mW/MHz – Branch)
(20 Branches)
+ (0.008 mW/MHz – PFU) (150 PFUs)
+ (0.002 mW/MHz – SMEM_PFU)
(16 SMEM_PFUs)] [40 MHz]
= 129 mW
PIN
= 20 x [0.033 mW/MHz x 20 MHz x 20%]
= 3 mW
PTOL
= 3.4 mW
OR2T40B Clock Power
P
= [0.42 mW/MHz
+ (0.118 mW/MHz – Branch) (# Branches)
+ (0.008 mW/MHz – PFU) (# PFUs)
+ (0.002 mW/MHz – SMEM_PFU)
(# SMEM_PFUs)] fCLK
For a quick estimate, the worst-case (typical circuit)
OR2T40B clock power ≈ 5.5 mW/MHz.
The power dissipated in a PIC is the sum of the power
dissipated in the four I/Os in the PIC. This consists of
Lattice Semiconductor
POUT = 30 x [(30 pF + 8.8 pF) x (3.6)2 x 20 MHz
x 20%]
= 60 mW
PBID
= 16 x [(50 pF + 8.8 pF) x (3.6)2 x 20 MHz
x 20%]
= 49 mW
TOTAL = 0.72 W
67
Data Sheet
November 2006
ORCA Series 2 FPGAs
Pin Information
Pin Descriptions
This section describes the pins found on the Series 2 FPGAs. Any pin not described in this table is a user-programmable I/O. During configuration, the user-programmable I/Os are 3-stated with an internal pull-up resistor enabled.
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Table 17. Pin Descriptions
Symbol
I/O
Description
Dedicated Pins
VDD
—
Positive power supply.
GND
—
Ground supply.
I/O-VDD5
—
5 V tolerant select. (For 2TxxA only.) All VDD5 pins must be tied to either the 5 V power
supply if 5 V tolerant I/O buffers are to be used, or to the 3.3 V power supply (VDD) if
they are not. For 2CxxA and 2TxxB devices, these pins are user-programmable I/Os.
RESET
I
During configuration, RESET forces the restart of configuration and a pull-up is
enabled. After configuration, RESET can be used as a general FPGA input or as a
direct input, which causes all PLC latches/FFs to be asynchronously set/reset.
CCLK
I
In the master and asynchronous peripheral modes, CCLK is an output which strobes
configuration data in. In the slave or synchronous peripheral mode, CCLK is input synchronous with the data on DIN or D[7:0].
DONE
I/O
DONE is a bidirectional pin with an optional pull-up resistor. As an active-high, opendrain output, a high-level on this signal indicates that configuration is complete. As an
input, a low level on DONE delays FPGA start-up after configuration*.
PRGM
I
PRGM is an active-low input that forces the restart of configuration and resets the
boundary-scan circuitry. This pin always has an active pull-up.
RD_CFG
I
This pin must be held high during device initialization until the INIT pin goes high.
This pin always has an active pullup.
During configuration, RD_CFG is an active-low input that activates the TS_ALL function
and 3-states all of the I/O.
After configuration, RD_CFG can be selected (via a bit stream option) to activate the
TS_ALL function as described above, or, if readback is enabled via a bit stream option,
a high-to-low transition on RD_CFG will initiate readback of the configuration data,
including PFU output states, starting with frame address 0.
RD_DATA/TDO
O
RD_DATA/TDO is a dual-function pin. If used for readback, RD_DATA provides configuration data out. If used in boundary scan, TDO is test data out.
Special-Purpose Pins (Become User I/O After Configuration)
RDY/RCLK
O
During configuration in peripheral mode, RDY indicates another byte can be written to
the FPGA. If a read operation is done when the device is selected, the same status is
also available on D7 in asynchronous peripheral mode. After configuration, the pin is a
user-programmable I/O*.
During the master parallel configuration mode RCLK, which is a read output signal to an
external memory. This output is not normally used. After configuration, this pin is a userprogrammable I/O pin*.
DIN
I
During slave serial or master serial configuration modes, DIN accepts serial configuration data synchronous with CCLK. During parallel configuration modes, DIN is the D0
input. During configuration, a pull-up is enabled, and after configuration, this pin is a
user-programmable I/O pin*.
* The FPGA States of Operation section contains more information on how to control these signals during start-up. The timing of DONE
release is controlled by one set of bit stream options, and the timing of the simultaneous release of all other configuration pins (and the activation of all user I/Os) is controlled by a second set of options.
68
Lattice Semiconductor
Data Sheet
November 2006
ORCA Series 2 FPGAs
Pin Information (continued)
Table 17. Pin Descriptions (continued)
Symbol
I/O
Description
Special-Purpose Pins Special-Purpose Pins (Become User I/O After Configuration) (continued)
I
During powerup and initialization, M0—M2 are used to select the configuration mode
with their values latched on the rising edge of INIT. See Table 7 for the configuration
modes. During configuration, a pull-up is enabled, and after configuration, the pins are
user-programmable I/O*.
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M0, M1, M2
M3
I
During powerup and initialization, M3 is used to select the speed of the internal oscillator during configuration, with its value latched on the rising edge of INIT. When M3 is
low, the oscillator frequency is 10 MHz. When M3 is high, the oscillator is 1.25 MHz.
During configuration, a pull-up is enabled, and after configuration, this pin is a user-programmable I/O pin*.
TDI, TCK, TMS
I
If boundary scan is used, these pins are Test Data In, Test Clock, and Test Mode Select
inputs. If boundary scan is not selected, all boundary-scan functions are inhibited once
configuration is complete, and these pins are user-programmable I/O pins. Even if
boundary scan is not used, either TCK or TMS must be held at logic 1 during configuration. Each pin has a pull-up enabled during configuration*.
HDC
O
High During Configuration is output high until configuration is complete. It is used as a
control output indicating that configuration is not complete. After configuration, this pin
is a user-programmable I/O pin*.
LDC
O
Low During Configuration is output low until configuration is complete. It is used as a
control output indicating that configuration is not complete. After configuration, this pin
is a user-programmable I/O pin*.
INIT
I/O
INIT is a bidirectional signal before and during configuration. During configuration, a
pull-up is enabled, but an external pull-up resistor is recommended. As an active-low
open-drain output, INIT is held low during power stabilization and internal clearing of
memory. As an active-low input, INIT holds the FPGA in the wait-state before the start
of configuration. After configuration, the pin is a user-programmable I/O pin*.
CS0, CS1, WR, RD
I
CS0, CS1, WR, RD are used in the asynchronous peripheral configuration modes. The
FPGA is selected when CS0 is low and CS1 is high. When selected, a low on the write
strobe, WR, loads the data on D[7:0] inputs into an internal data buffer. WR, CS0, and
CS1 are also used as chip selects in the slave parallel mode.
A low on RD changes D7 into a status output. As a status indication, a high indicates
ready and a low indicates busy. WR and RD should not be used simultaneously. If they
are, the write strobe overrides. During configuration, a pull-up is enabled, and after configuration, the pins are user-programmable I/O pins*.
A[17:0]
O
During master parallel configuration mode, A[17:0] address the configuration EPROM.
During configuration, a pull-up is enabled, and after configuration, the pins are userprogrammable I/O pins*.
D[7:0]
I
During master parallel, peripheral, and slave parallel configuration modes, D[7:0]
receive configuration data and each pin has a pull-up enabled. After configuration, the
pins are user-programmable I/O pins*.
DOUT
O
During configuration, DOUT is the serial data output that can drive the DIN of daisychained slave LCA devices. Data out on DOUT changes on the falling edge of CCLK.
After configuration, DOUT is a user-programmable I/O pin*.
* The FPGA States of Operation section contains more information on how to control these signals during start-up. The timing of DONE
release is controlled by one set of bit stream options, and the timing of the simultaneous release of all other configuration pins (and the activation of all user I/Os) is controlled by a second set of options.
Lattice Semiconductor
69
Data Sheet
November 2006
ORCA Series 2 FPGAs
Pin Information (continued)
Package Compatibility
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The package pinouts are consistent across ORCA
Series FPGAs with the following exception: some user
I/O pins that do not have any special functions will
be converted to VDD5 pins for the OR2TxxA series.
If the designer does not use these pins for the
OR2CxxA and OR2TxxB series, then pinout compatibility will be maintained between the ORCA OR2CxxA,
OR2TxxA, and OR2TxxB series of FPGAs. Note that
they must be connected to a power supply for the
OR2TxxA series.
for each available package, and Table 18B provides the
number of user I/Os available in the ORCA OR2TxxA
series. It should be noted that the number of user I/Os
available for the OR2TxxA series is reduced from the
equivalent OR2CxxA devices by the number of
required VDD5 pins, as shown in Table 18B. The pins
that are converted from user I/O to VDD5 are denoted
as I/O-VDD5 in the pin information tables (Table 19
through 28). Each package has six dedicated configuration pins.
Package pinouts being consistent across all ORCA
Series FPGAs enables a designer to select a package
based on I/O requirements and change the FPGA without laying out the printed-circuit board again. The
change might be to a larger FPGA if additional functionality is needed, or it might be to a smaller FPGA to
decrease unit cost.
Table 18A provides the number of user I/Os available
for the ORCA OR2CxxA and OR2TxxB Series FPGAs
Table 19—Table 28. provide the package pin and pin
function for the ORCA Series 2 FPGAs and packages.
The bond pad name is identified in the PIC nomenclature used in the ispLEVER design editor.
When the number of FPGA bond pads exceeds the
number of package pins, bond pads are unused. When
the number of package pins exceeds the number of
bond pads, package pins are left unconnected (no
connects). When a package pin is to be left as a no
connect for a specific die, it is indicated as a note in the
device pad column for the FPGA. The tables provide no
information on unused pads.
Table 18A. ORCA OR2CxxA and OR2TxxB Series FPGA I/Os Summary
Device
84-Pin 100-Pin 144-Pin 160-Pin
PLCC
TQFP
TQFP
QFP
OR2C04A
User I/Os
64
VDD/VSS
14
OR2C06A
User I/Os
—
VDD/VSS
—
OR2C08A
User I/Os
—
VDD/VSS
—
OR2C10A
User I/Os
—
VDD/VSS
—
OR2C12A
User I/Os
64
VDD/VSS
14
OR2C15A/OR2T15B
User I/Os
64
VDD/VSS
14
OR2C26A
User I/Os
—
VDD/VSS
—
OR2C40A/OR2T40B
User I/Os
—
VDD/VSS
—
70
208-Pin
SQFP/
SQFP2
240-Pin
SQFP/
SQFP2
256-Pin
PBGA
304-Pin
SQFP/
SQFP2
352-Pin 432-Pin
PBGA
EBGA
77
17
114
24
130
24
160
31
—
—
—
—
—
—
—
—
—
—
77
17
114
24
130
24
171
31
192
42
192
26
—
—
—
—
—
—
—
—
—
—
130
24
171
31
192
40
—
—
—
—
—
—
—
—
—
—
—
—
130
24
171
31
—
—
221
26
—
—
256
48
—
—
—
—
—
—
—
—
171
31
192
42
223
26
252
46
288
48
—
—
—
—
—
—
—
—
171
31
192
42
223
26
252
46
298
48
—
—
—
—
—
—
—
—
171
31
192
42
—
—
252
46
—
—
—
—
—
—
—
—
—
—
171
31
192
42
—
—
252
46
—
—
—
—
Lattice Semiconductor
Data Sheet
November 2006
ORCA Series 2 FPGAs
Pin Information (continued)
Table 18B. ORCA OR2TxxA Series FPGA I/Os Summary
Device
100-Pin
TQFP
144-Pin
TQFP
160-Pin
QFP
208-Pin
SQFP/
SQFP2
240-Pin
SQFP/
SQFP2
256-Pin
PBGA
352-Pin
PBGA
432-Pin
EBGA
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OR2T04A
User I/Os
VDD/VSS
VDD5
OR2T08A
User I/Os
VDD/VSS
VDD5
OR2T10A
User I/Os
VDD/VSS
VDD5
OR2T15A
User I/Os
VDD/VSS
VDD5
OR2T26A
User I/Os
VDD/VSS
VDD5
OR2T40A
User I/Os
VDD/VSS
VDD5
84-Pin
PLCC
—
—
—
74
17
3
110
24
4
—
—
—
152
31
8
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
126
24
4
163
31
8
184
40
8
209
26
12
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
126
24
4
163
31
8
184
40
8
209
26
12
—
—
—
—
—
—
62
14
2
—
—
—
—
—
—
—
—
—
163
31
8
184
42
8
211
26
12
286
48
12
307
84
12
—
—
—
—
—
—
—
—
—
—
—
—
163
31
8
184
42
8
—
—
—
286
48
12
326
84
16
—
—
—
—
—
—
—
—
—
—
—
—
163
31
8
184
42
8
—
—
—
286
48
12
—
—
—
Lattice Semiconductor
71
Data Sheet
November 2006
ORCA Series 2 FPGAs
Pin Information (continued)
Compatibility with Series 3 FPGAs
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Pinouts for the OR2CxxA, OR2TxxA, and OR2TxxB devices will be consistent with the Series 3 FPGAs for all
devices offered in the same packages. This includes the following pins: VDD, VSS, VDD5 (OR3C/Txxx series only),
and all configuration pins. Identical to the OR2TxxB devices, Series 3 devices provide 5 V tolerant I/Os without a
dedicated VDD5 supply
The following restrictions apply:
1. There are two configuration modes supported in the OR2C/TxxA series that are not supported in the
Series 3 FPGAs series: master parallel down and synchronous peripheral modes. The Series 3 FPGAs have two
new microprocessor interface (MPI) configuration modes that are unavailable in the Series 2.
2. There are 4 pins—one per each device side—that are user I/O in the OR2C/TxxA series which can only be used
as fast dedicated clocks or global inputs in the Series 3 series. These pins are also used to drive the ExpressCLK to the I/O FFs on their given side of the device. These four middle ExpressCLK pins should not be used to
connect to a programmable clock manager (PCM). A corner ExpressCLK input should be used instead (see note
below). See Table 18C for a list of these pins in each package.
3. There are two other pins that are user I/O in both the Series 2 and Series 3 series but also have optional added
functionality in the Series 3 series. Each of these pins drives the ExpressCLKs on two sides of the device. They
also have fast connectivity to the programmable clock manager (PCM). See Table 18C for a preliminary list of
these pins in each package.
Table 18C. Series 3 ExpressCLK Pins
Pin Name/
Package
208-Pin
SQFP2
240-Pin
SQFP2
256-Pin
PBGA
352-Pin
PBGA
432-Pin
EBGA
ECKL
ECKB
ECKR
ECKT
I/O—SECKLL
I/O—SECKUR
22
80
131
178
49
159
26
91
152
207
56
184
K3
W11
K18
B11
W1
A19
N2
AE14
N23
B14
AB4
A25
R29
AH16
T2
C15
AG29
D5
Note: The ECKR, ECKL, ECKT, and ECKB pins drive the ExpressCLK on their given edge of the device, while I/O—SECKLL and
I/O—SECKUR drive an ExpressCLK on two edges of the device and provide connectivity to the programmable clock manager.
72
Lattice Semiconductor
Data Sheet
November 2006
ORCA Series 2 FPGAs
Pin Information (continued)
Table 19. OR2C04A, OR2C12A, and OR2C/2T15A 84-Pin PLCC Pinout
2C04A Pad
2C12A Pad
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
VSS
PT5A
VSS
PT4D
PT4A
PT3A
PT2D
PT2A
PT1D
PT1A
VSS
PT9A
VSS
PT8D
PT8A
PT7A
PT6D
PT5A
PT3A
PT1A
2C/2T15A
Pad
VSS
PT10A
VSS
PT9D
PT9A
PT8A
PT7D
PT6A
PT4A
PT1A
Function
VSS
I/O-D2
VSS
I/O-D1
I/O-D0/DIN
I/O-DOUT
I/O-VDD5
I/O-TDI
I/O-TMS
I/O-TCK
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Pin
RD_DATA/TDO RD_DATA/TDO RD_DATA/TDO
VDD
VSS
PL1C
PL1A
PL2D
PL2A
PL3A
PL4D
PL4A
PL5A
VDD
PL6A
VSS
PL7D
PL7A
PL8A
PL9D
PL9A
PL10D
PL10A
CCLK
VDD
VSS
PB1A
PB1D
PB2A
PB2D
PB3A
PB4A
PB4D
PB5A
VSS
VDD
VSS
PL2D
PL4A
PL5A
PL6A
PL7A
PL8D
PL8A
PL9A
VDD
PL10A
VSS
PL11D
PL11A
PL12A
PL13D
PL14B
PL16D
PL18A
CCLK
VDD
VSS
PB1A
PB3D
PB5B
PB6D
PB7A
PB8A
PB8D
PB9A
VSS
VDD
VSS
PL2D
PL5A
PL6A
PL7A
PL8A
PL9D
PL9A
PL10A
VDD
PL11A
VSS
PL12D
PL12A
PL13A
PL14D
PL15B
PL17D
PL20A
CCLK
VDD
VSS
PB1A
PB4D
PB6B
PB7D
PB8A
PB9A
PB9D
PB10A
VSS
RD_DATA/TDO
VDD
VSS
I/O-A0
I/O-A1
I/O-A2
I/O-A3
I/O-A4
I/O-A5
I/O-A6
I/O-A7
VDD
I/O-A8
VSS
I/O-A9
I/O-A10
I/O-A11
I/O-A12
I/O-A13
I/O-A14
I/O-A15
CCLK
VDD
VSS
I/O-A16
I/O-A17
I/O
I/O
I/O
I/O
I/O
I/O
VSS
Note: The pins labeled I/O-VDD5 are user I/Os for the OR2CxxA and OR2TxxB
series, but they are connected to VDD5 for the OR2TxxA series.
Lattice Semiconductor
73
Data Sheet
November 2006
ORCA Series 2 FPGAs
Pin Information (continued)
Table 19. OR2C04A, OR2C12A, and OR2C/2T15A 84-Pin PLCC Pinout (continued)
Pin
2C04A Pad
2C12A Pad
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
PB6A
VSS
PB7A
PB7D
PB8A
PB9A
PB9D
PB10A
PB10D
DONE
PB10A
VSS
PB11A
PB11D
PB12A
PB13A
PB13D
PB15A
PB18D
DONE
2C/2T15A
Pad
PB11A
VSS
PB12A
PB12D
PB13A
PB14A
PB14D
PB16A
PB20D
DONE
RESET
PRGM
RESET
PRGM
RESET
PRGM
RESET
PRGM
PR10A
PR10D
PR9A
PR9D
PR8A
PR7A
PR7D
PR6A
VDD
PR5A
VSS
PR4A
PR4D
PR3A
PR2A
PR2D
PR1A
PR1D
PR18A
PR16A
PR15D
PR13A
PR12A
PR11A
PR11D
PR10A
VDD
PR9A
VSS
PR8A
PR8D
PR7A
PR6A
PR5D
PR4A
PR2A
PR20A
PR17A
PR16D
PR14A
PR13A
PR12A
PR12D
PR11A
VDD
PR10A
VSS
PR9A
PR9D
PR8A
PR7A
PR6D
PR5A
PR3A
I/O-M0
I/O
I/O-M1
I/O
I/O-M2
I/O-M3
I/O
I/O
VDD
I/O
VSS
I/O
I/O
I/O-CS1
I/O-CS0
I/O
I/O-RD
I/O-WR
RD_CFG
RD_CFG
RD_CFG
RD_CFG
VDD
VSS
PT10C
PT9D
PT9C
PT9A
PT8A
PT7D
PT7A
PT6A
VDD
VSS
PT17D
PT15D
PT14D
PT13B
PT12A
PT11D
PT11A
PT10A
VDD
VSS
PT19A
PT16D
PT15D
PT14B
PT13A
PT12D
PT12A
PT11A
VDD
VSS
I/O-RDY/RCLK
I/O-D7
I/O
I/O-D6
I/O-D5
I/O
I/O-D4
I/O-D3
Function
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I/O-VDD5
I/O
I/O-HDC
I/O-LDC
I/O
I/O-INIT
I/O
DONE
Note: The pins labeled I/O-VDD5 are user I/Os for the OR2CxxA and OR2TxxB
series, but they are connected to VDD5 for the OR2TxxA series.
74
Lattice Semiconductor
Data Sheet
November 2006
ORCA Series 2 FPGAs
Pin Information (continued)
Table 20. OR2C/2T04A and OR2C06A 100-Pin TQFP Pinout
Pin
2C06A Pad
Function
Pin
VDD
VSS
PL1A
PL2A
PL3D
PL3A
PL4D
PL4A
PL5D
PL5A
PL6D
PL6A
VDD
PL7A
VSS
PL8D
PL8A
PL9A
PL10D
PL10C
PL10A
PL11A
PL12A
VSS
CCLK
VDD
VSS
PB1A
PB1D
PB2A
PB3A
PB3D
PB4A
PB5A
PB5D
PB6A
VSS
PB7A
VSS
PB8A
PB8D
PB9A
VDD
VSS
I/O-A0
I/O-A1
I/O-A2
I/O-A3
I/O
I/O-A4
I/O-A5
I/O-A6
I/O
I/O-A7
VDD
I/O-A8
VSS
I/O-A9
I/O-A10
I/O-A11
I/O-A12
I/O
I/O-A13
I/O-A14
I/O-A15
VSS
CCLK
VDD
VSS
I/O-A16
I/O
I/O-A17
I/O
I/O
I/O
I/O
I/O
I/O
VSS
I/O
VSS
I/O-VDD5
I/O
I/O-HDC
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
2C/2T04A
Pad
PB8C
PB8D
PB9A
PB9D
PB10A
PB10D
DONE
VDD
2C06A Pad
Function
PB9C
PB9D
PB10A
PB10D
PB11A
PB12A
DONE
VDD
I/O
I/O
I/O-LDC
I/O
I/O-INIT
I/O
DONE
VDD
RESET
PRGM
RESET
PRGM
RESET
PRGM
PR10A
PR10D
PR9A
PR9D
PR8A
PR8D
PR7A
PR7D
VSS
PR6A
VDD
PR5A
VSS
PR4A
PR4D
PR3A
PR3D
PR2A
PR2D
PR1A
PR1C
PR1D
PR12A
PR11A
PR10A
PR10D
PR9A
PR9D
PR8A
PR8D
VSS
PR7A
VDD
PR6A
VSS
PR5A
PR5D
PR4A
PR4D
PR3A
PR3D
PR2A
PR2D
PR1A
I/O-M0
I/O
I/O-M1
I/O
I/O-M2
I/O
I/O-M3
I/O
VSS
I/O
VDD
I/O
VSS
I/O-VDD5
I/O
I/O-CS1
I/O
I/O-CS0
I/O
I/O-RD
I/O
I/O-WR
RD_CFG
RD_CFG
RD_CFG
VDD
VSS
PT10C
PT9D
PT9C
PT9A
PT8D
PT8A
PT7D
VDD
VSS
PT12A
PT11A
PT10D
PT10A
PT9D
PT9A
PT8D
VDD
VSS
I/O-RDY/RCLK
I/O-D7
I/O
I/O-D6
I/O
I/O-D5
I/O
SE
L
D E
IS C
C T
O D
N E
TI VI
N C
U E
ED S
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
2C/2T04A
Pad
VDD
VSS
PL1C
PL1A
PL2D
PL2A
PL3D
PL3A
PL4D
PL4A
PL5D
PL5A
VDD
PL6A
VSS
PL7D
PL7A
PL8A
PL9D
PL9C
PL9A
PL10D
PL10A
VSS
CCLK
VDD
VSS
PB1A
PB1C
PB1D
PB2A
PB2D
PB3A
PB4A
PB4D
PB5A
VSS
PB6A
VSS
PB7A
PB7D
PB8A
Note: The pins labeled I/O-VDD5 are user I/Os for the OR2CxxA and OR2TxxB series, but they are connected to VDD5 for the OR2TxxA
series.
Lattice Semiconductor
75
Data Sheet
November 2006
ORCA Series 2 FPGAs
Pin Information (continued)
Table 20. OR2C/2T04A and OR2C06A 100-Pin TQFP Pinout (continued)
Pin
2C06A Pad
Function
Pin
PT8A
PT7D
PT7A
VSS
PT6A
VSS
PT5D
PT5A
I/O-D4
I/O
I/O-D3
VSS
I/O-D2
VSS
I/O-D1
I/O-D0/DIN
93
94
95
96
97
98
99
100
2C/2T04A
Pad
PT3D
PT3A
PT2D
PT2A
PT1D
PT1C
PT1A
2C06A Pad
Function
PT4D
PT4A
PT3D
PT3A
PT2A
PT1D
PT1A
I/O
I/O-DOUT
I/O-VDD5
I/O-TDI
I/O-TMS
I/O
I/O-TCK
RD_DATA/
TDO
RD_DATA/TDO
SE
L
D E
IS C
C T
O D
N E
TI VI
N C
U E
ED S
85
86
87
88
89
90
91
92
2C/2T04A
Pad
PT7A
PT6D
PT6A
VSS
PT5A
VSS
PT4D
PT4A
RD_DATA/
TDO
Note: The pins labeled I/O-VDD5 are user I/Os for the OR2CxxA and OR2TxxB series, but they are connected to VDD5 for the OR2TxxA
series.
76
Lattice Semiconductor
Data Sheet
November 2006
ORCA Series 2 FPGAs
Pin Information (continued)
Table 21. OR2C/2T04A and OR2C06A 144-Pin TQFP Pinout
Pin
2C06A Pad
Function
Pin
VDD
VSS
PL1A
PL2D
PL2A
PL3D
PL3A
PL4D
PL4C
PL4A
PL5D
PL5C
PL5A
VSS
PL6D
PL6C
PL6A
VDD
PL7D
PL7C
PL7A
VSS
PL8D
PL8A
PL9D
PL9C
PL9A
PL10D
PL10C
PL10A
PL11A
PL12D
PL12B
PL12A
VSS
CCLK
VDD
VSS
PB1A
PB1D
PB2A
PB3A
VDD
VSS
I/O-A0
I/O
I/O-A1
I/O-A2
I/O-A3
I/O
I/O
I/O-A4
I/O-A5
I/O
I/O-A6
VSS
I/O
I/O
I/O-A7
VDD
I/O
I/O-VDD5
I/O-A8
VSS
I/O-A9
I/O-A10
I/O
I/O
I/O-A11
I/O-A12
I/O
I/O-A13
I/O-A14
I/O
I/O
I/O-A15
VSS
CCLK
VDD
VSS
I/O-A16
I/O
I/O-A17
I/O
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
2C/2T04A
Pad
PB2B
PB2D
VDD
PB3A
PB3D
PB4A
PB4C
PB4D
PB5A
PB5C
PB5D
VSS
PB6A
PB6C
PB6D
PB7A
PB7D
PB8A
PB8C
PB8D
VDD
PB9A
PB9C
PB9D
PB10A
PB10C
PB10D
VSS
DONE
VDD
VSS
2C06A Pad
Function
PB3B
PB3D
VDD
PB4A
PB4D
PB5A
PB5C
PB5D
PB6A
PB6C
PB6D
VSS
PB7A
PB7C
PB7D
PB8A
PB8D
PB9A
PB9C
PB9D
VDD
PB10A
PB10C
PB10D
PB11A
PB11D
PB12A
VSS
DONE
VDD
VSS
I/O
I/O
VDD
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VSS
I/O
I/O
I/O
I/O-VDD5
I/O
I/O-HDC
I/O
I/O
VDD
I/O-LDC
I/O
I/O
I/O-INIT
I/O
I/O
VSS
DONE
VDD
VSS
RESET
PRGM
RESET
PRGM
RESET
PRGM
PR10A
PR10B
PR10D
PR9A
PR9C
PR9D
PR8A
PR8B
PR8D
PR12A
PR12D
PR11A
PR10A
PR10C
PR10D
PR9A
PR9B
PR9D
I/O-M0
I/O
I/O
I/O-M1
I/O
I/O
I/O-M2
I/O
I/O
SE
L
D E
IS C
C T
O D
N E
TI VI
N C
U E
ED S
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
2C/2T04A
Pad
VDD
VSS
PL1C
PL1B
PL1A
PL2D
PL2A
PL3D
PL3C
PL3A
PL4D
PL4C
PL4A
VSS
PL5D
PL5C
PL5A
VDD
PL6D
PL6C
PL6A
VSS
PL7D
PL7A
PL8D
PL8C
PL8A
PL9D
PL9C
PL9A
PL10D
PL10C
PL10B
PL10A
VSS
CCLK
VDD
VSS
PB1A
PB1C
PB1D
PB2A
Note: The pins labeled I/O-VDD5 are user I/Os for the OR2CxxA and OR2TxxB series, but they are connected to VDD5 for the OR2TxxA
series.
Lattice Semiconductor
77
Data Sheet
November 2006
ORCA Series 2 FPGAs
Pin Information (continued)
Table 21. OR2C/2T04A and OR2C06A 144-Pin TQFP Pinout (continued)
Pin
2C06A Pad
Function
Pin
PR8A
PR8D
VSS
PR7A
PR7C
PR7D
VDD
PR6A
PR6C
PR6D
VSS
PR5A
PR5C
PR5D
PR4A
PR4D
PR3A
PR3D
PR2A
PR2C
PR2D
PR1A
VSS
I/O-M3
I/O
VSS
I/O
I/O
I/O
VDD
I/O
I/O
I/O
VSS
I/O-VDD5
I/O
I/O
I/O-CS1
I/O
I/O-CS0
I/O
I/O-RD
I/O
I/O
I/O-WR
VSS
RD_CFG
RD_CFG
RD_CFG
VDD
VSS
PT10D
PT10C
PT10B
PT9D
VDD
VSS
PT12D
PT12A
PT11D
PT11A
VDD
VSS
I/O
I/O-RDY/RCLK
I/O
I/O-D7
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
2C/2T04A
Pad
PT9C
PT9B
PT9A
VDD
PT8D
PT8A
PT7D
PT7B
PT7A
PT6D
PT6C
PT6A
VSS
PT5D
PT5C
PT5A
PT4D
PT4C
PT4A
PT3D
PT3A
VDD
PT2D
PT2C
PT2A
PT1D
PT1C
PT1A
VSS
2C06A Pad
Function
PT10D
PT10C
PT10A
VDD
PT9D
PT9A
PT8D
PT8B
PT8A
PT7D
PT7C
PT7A
VSS
PT6D
PT6C
PT6A
PT5D
PT5C
PT5A
PT4D
PT4A
VDD
PT3D
PT3C
PT3A
PT2A
PT1D
PT1A
VSS
I/O
I/O
I/O-D6
VDD
I/O
I/O-D5
I/O
I/O
I/O-D4
I/O
I/O
I/O-D3
VSS
I/O
I/O
I/O-D2
I/O-D1
I/O
I/O-D0/DIN
I/O
I/O-DOUT
VDD
I/O-VDD5
I/O
I/O-TDI
I/O-TMS
I/O
I/O-TCK
VSS
RD_DATA/
TDO
RD_DATA/TDO
SE
L
D E
IS C
C T
O D
N E
TI VI
N C
U E
ED S
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
2C/2T04A
Pad
PR7A
PR7D
VSS
PR6A
PR6C
PR6D
VDD
PR5A
PR5C
PR5D
VSS
PR4A
PR4C
PR4D
PR3A
PR3D
PR2A
PR2D
PR1A
PR1B
PR1C
PR1D
VSS
RD_DATA/
TDO
Note: The pins labeled I/O-VDD5 are user I/Os for the OR2CxxA and OR2TxxB series, but they are connected to VDD5 for the OR2TxxA
series.
78
Lattice Semiconductor
Data Sheet
November 2006
ORCA Series 2 FPGAs
Pin Information (continued)
Table 22. OR2C04A, OR2C06A, OR2C/2T08A, and OR2C/2T10A 160-Pin QFP Pinout
2C04A Pad
2C06A Pad
2C/2T08A Pad
2C/2T10A Pad
Function
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
VDD
VSS
PL1D
PL1C
PL1B
PL1A
PL2D
PL2C
PL2A
PL3D
PL3C
PL3A
PL4D
PL4C
PL4A
VSS
PL5D
PL5C
PL5A
VDD
PL6D
PL6C
PL6A
VSS
PL7D
PL7B
PL7A
PL8D
PL8C
PL8A
PL9D
PL9C
PL9B
PL9A
PL10D
PL10C
PL10B
PL10A
CCLK
VSS
VDD
VSS
PL1D
PL1A
PL2D
PL2A
PL3D
PL3C
PL3A
PL4D
PL4C
PL4A
PL5D
PL5C
PL5A
VSS
PL6D
PL6C
PL6A
VDD
PL7D
PL7C
PL7A
VSS
PL8D
PL8B
PL8A
PL9D
PL9C
PL9A
PL10D
PL10C
PL10B
PL10A
PL11A
PL12D
PL12B
PL12A
CCLK
VSS
VDD
VSS
PL1D
PL2D
PL3D
PL3A
PL4D
PL4C
PL4A
PL5D
PL5C
PL5A
PL6D
PL6C
PL6A
VSS
PL7D
PL7C
PL7A
VDD
PL8D
PL8C
PL8A
VSS
PL9D
PL9B
PL9A
PL10D
PL10C
PL10A
PL11D
PL11C
PL11B
PL11A
PL12A
PL13D
PL14D
PL14A
CCLK
VSS
VDD
VSS
PL1D
PL2D
PL3D
PL3A
PL4A
PL5C
PL5A
PL6D
PL6C
PL6A
PL7D
PL7C
PL7A
VSS
PL8D
PL8C
PL8A
VDD
PL9D
PL9C
PL9A
VSS
PL10D
PL10B
PL10A
PL11D
PL11C
PL11A
PL12D
PL12C
PL12B
PL13D
PL14C
PL15D
PL16D
PL16A
CCLK
VSS
VDD
VSS
I/O
I/O-A0
I/O
I/O-A1
I/O-A2
I/O
I/O-A3
I/O
I/O
I/O-A4
I/O-A5
I/O
I/O-A6
VSS
I/O
I/O
I/O-A7
VDD
I/O
I/O-VDD5
I/O-A8
VSS
I/O-A9
I/O
I/O-A10
I/O
I/O
I/O-A11
I/O-A12
I/O
I/O
I/O-A13
I/O-A14
I/O
I/O
I/O-A15
CCLK
VSS
SE
L
D E
IS C
C T
O D
N E
TI VI
N C
U E
ED S
Pin
Note: The pins labeled I/O-VDD5 are user I/Os for the OR2CxxA and OR2TxxB series, but they are connected to VDD5 for the OR2TxxA
series.
Lattice Semiconductor
79
Data Sheet
November 2006
ORCA Series 2 FPGAs
Pin Information (continued)
Table 22. OR2C04A, OR2C06A, OR2C/2T08A, and OR2C/2T10A 160-Pin QFP Pinout (continued)
2C04A Pad
2C06A Pad
2C/2T08A Pad
2C/2T10A Pad
Function
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
VDD
VSS
PB1A
PB1B
PB1C
PB1D
PB2A
PB2B
PB2C
PB2D
VDD
PB3A
PB3D
PB4A
PB4C
PB4D
PB5A
PB5C
PB5D
VSS
PB6A
PB6C
PB6D
PB7A
PB7D
PB8A
PB8C
PB8D
VDD
PB9A
PB9B
PB9C
PB9D
PB10A
PB10B
PB10C
PB10D
VSS
DONE
VDD
VSS
VDD
VSS
PB1A
PB1C
PB1D
PB2A
PB3A
PB3B
PB3C
PB3D
VDD
PB4A
PB4D
PB5A
PB5C
PB5D
PB6A
PB6C
PB6D
VSS
PB7A
PB7C
PB7D
PB8A
PB8D
PB9A
PB9C
PB9D
VDD
PB10A
PB10B
PB10C
PB10D
PB11A
PB11C
PB11D
PB12A
VSS
DONE
VDD
VSS
VDD
VSS
PB1A
PB2A
PB2D
PB3A
PB3D
PB4A
PB4C
PB4D
VDD
PB5A
PB5D
PB6A
PB6C
PB6D
PB7A
PB7C
PB7D
VSS
PB8A
PB8C
PB8D
PB9A
PB9D
PB10A
PB10C
PB10D
VDD
PB11A
PB11D
PB12A
PB12B
PB12C
PB12D
PB13D
PB14D
VSS
DONE
VDD
VSS
VDD
VSS
PB1A
PB2A
PB2D
PB3B
PB4D
PB5A
PB5C
PB5D
VDD
PB6A
PB6D
PB7A
PB7C
PB7D
PB8A
PB8C
PB8D
VSS
PB9A
PB9C
PB9D
PB10A
PB10D
PB11A
PB11C
PB11D
VDD
PB12A
PB13A
PB13B
PB13C
PB13D
PB14A
PB15D
PB16D
VSS
DONE
VDD
VSS
VDD
VSS
I/O-A16
I/O
I/O
I/O-A17
I/O
I/O
I/O
I/O
VDD
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VSS
I/O
I/O
I/O
I/O-VDD5
I/O
I/O-HDC
I/O
I/O
VDD
I/O-LDC
I/O
I/O
I/O
I/O-INIT
I/O
I/O
I/O
VSS
DONE
VDD
VSS
SE
L
D E
IS C
C T
O D
N E
TI VI
N C
U E
ED S
Pin
Note: The pins labeled I/O-VDD5 are user I/Os for the OR2CxxA and OR2TxxB series, but they are connected to VDD5 for the OR2TxxA
series.
80
Lattice Semiconductor
Data Sheet
November 2006
ORCA Series 2 FPGAs
Pin Information (continued)
Table 22. OR2C04A, OR2C06A, OR2C/2T08A, and OR2C/2T10A 160-Pin QFP Pinout (continued)
2C04A Pad
2C06A Pad
2C/2T08A Pad
2C/2T10A Pad
Function
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
RESET
RESET
RESET
RESET
RESET
PRGM
PRGM
PRGM
PRGM
PRGM
PR10A
PR10B
PR10C
PR10D
PR9A
PR9B
PR9C
PR9D
PR8A
PR8B
PR8D
PR7A
PR7D
VSS
PR6A
PR6C
PR6D
VDD
PR5A
PR5C
PR5D
VSS
PR4A
PR4C
PR4D
PR3A
PR3B
PR3D
PR2A
PR2C
PR2D
PR1A
PR1B
PR1C
PR1D
VSS
PR12A
PR12D
PR11A
PR11B
PR10A
PR10B
PR10C
PR10D
PR9A
PR9B
PR9D
PR8A
PR8D
VSS
PR7A
PR7C
PR7D
VDD
PR6A
PR6C
PR6D
VSS
PR5A
PR5C
PR5D
PR4A
PR4B
PR4D
PR3A
PR3C
PR3D
PR2A
PR2C
PR2D
PR1A
VSS
PR14A
PR13A
PR13D
PR12A
PR11A
PR11B
PR11C
PR11D
PR10A
PR10B
PR10D
PR9A
PR9D
VSS
PR8A
PR8C
PR8D
VDD
PR7A
PR7C
PR7D
VSS
PR6A
PR6C
PR6D
PR5A
PR5B
PR5D
PR4A
PR4B
PR4D
PR3A
PR3C
PR3D
PR2A
VSS
PR16A
PR15A
PR15D
PR14A
PR13B
PR13C
PR12A
PR12B
PR11A
PR11B
PR11D
PR10A
PR10D
VSS
PR9A
PR9C
PR9D
VDD
PR8A
PR8C
PR8D
VSS
PR7A
PR7C
PR7D
PR6A
PR6B
PR6D
PR5A
PR4B
PR4D
PR3A
PR3C
PR3D
PR2A
VSS
I/O-M0
I/O
I/O
I/O
I/O-M1
I/O
I/O
I/O
I/O-M2
I/O
I/O
I/O-M3
I/O
VSS
I/O
I/O
I/O
VDD
I/O
I/O
I/O
VSS
I/O-VDD5
I/O
I/O
I/O-CS1
I/O
I/O
I/O-CS0
I/O
I/O
I/O-RD
I/O
I/O
I/O-WR
VSS
RD_CFG
RD_CFG
RD_CFG
RD_CFG
RD_CFG
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
SE
L
D E
IS C
C T
O D
N E
TI VI
N C
U E
ED S
Pin
Note: The pins labeled I/O-VDD5 are user I/Os for the OR2CxxA and OR2TxxB series, but they are connected to VDD5 for the OR2TxxA
series.
Lattice Semiconductor
81
Data Sheet
November 2006
ORCA Series 2 FPGAs
Pin Information (continued)
Table 22. OR2C04A, OR2C06A, OR2C/2T08A, and OR2C/2T10A 160-Pin QFP Pinout (continued)
2C04A Pad
2C06A Pad
2C/2T08A Pad
2C/2T10A Pad
Function
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
PT10D
PT10C
PT10B
PT10A
PT9D
PT9C
PT9B
PT9A
VDD
PT8D
PT8A
PT7D
PT7B
PT7A
PT6D
PT6C
PT6A
VSS
PT5D
PT5C
PT5A
PT4D
PT4C
PT4A
PT3D
PT3C
PT3A
VDD
PT2D
PT2C
PT2B
PT2A
PT1D
PT1C
PT1B
PT1A
VSS
RD_DATA/TDO
PT12D
PT12A
PT11D
PT11C
PT11A
PT10D
PT10C
PT10A
VDD
PT9D
PT9A
PT8D
PT8B
PT8A
PT7D
PT7C
PT7A
VSS
PT6D
PT6C
PT6A
PT5D
PT5C
PT5A
PT4D
PT4C
PT4A
VDD
PT3D
PT3C
PT3B
PT3A
PT2A
PT1D
PT1C
PT1A
VSS
RD_DATA/TDO
PT14D
PT13D
PT13A
PT12D
PT12C
PT12A
PT11D
PT11B
VDD
PT10D
PT10A
PT9D
PT9B
PT9A
PT8D
PT8C
PT8A
VSS
PT7D
PT7C
PT7A
PT6D
PT6C
PT6A
PT5D
PT5C
PT5A
VDD
PT4D
PT4C
PT4B
PT4A
PT3A
PT2A
PT1D
PT1A
VSS
RD_DATA/TDO
PT16D
PT15D
PT15A
PT14D
PT13D
PT13B
PT13A
PT12B
VDD
PT11D
PT11A
PT10D
PT10B
PT10A
PT9D
PT9C
PT9A
VSS
PT8D
PT8C
PT8A
PT7D
PT7C
PT7A
PT6D
PT6C
PT6A
VDD
PT5D
PT5A
PT4D
PT4A
PT3A
PT2A
PT1D
PT1A
VSS
RD_DATA/TDO
I/O
I/O-RDY/RCLK
I/O
I/O
I/O-D7
I/O
I/O
I/O-D6
VDD
I/O
I/O-D5
I/O
I/O
I/O-D4
I/O
I/O
I/O-D3
VSS
I/O
I/O
I/O-D2
I/O-D1
I/O
I/O-D0/DIN
I/O
I/O
I/O-DOUT
VDD
I/O-VDD5
I/O
I/O
I/O-TDI
I/O-TMS
I/O
I/O
I/O-TCK
VSS
RD_DATA/TDO
SE
L
D E
IS C
C T
O D
N E
TI VI
N C
U E
ED S
Pin
Note: The pins labeled I/O-VDD5 are user I/Os for the OR2CxxA and OR2TxxB series, but they are connected to VDD5 for the OR2TxxA
series.
82
Lattice Semiconductor
Data Sheet
November 2006
ORCA Series 2 FPGAs
Pin Information (continued)
Table 23. OR2C/2T04A, OR2C06A, OR2C/2T08A, OR2C/2T10A, OR2C12A, OR2C/2T15A/B,
OR2C/2T26A, and OR2C/2T40A/B 208-Pin SQFP/SQFP2 Pinout
2C/2T04A
Pad
2C06A Pad
2C/2T08A
Pad
2C/2T10A
Pad
2C12A Pad
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
VSS
VSS
PL1D
PL1C
PL1B
See Note
PL1A
PL2D
PL2C
PL2B
PL2A
VDD
PL3D
PL3C
PL3B
PL3A
PL4D
PL4C
PL4B
PL4A
VSS
PL5D
PL5C
PL5B
PL5A
VDD
PL6D
PL6C
PL6B
PL6A
VSS
PL7D
PL7C
PL7B
PL7A
PL8D
PL8C
PL8B
PL8A
VDD
PL9D
PL9C
PL9B
VSS
VSS
PL1D
PL1A
PL2D
PL2C
PL2A
PL3D
PL3C
PL3B
PL3A
VDD
PL4D
PL4C
PL4B
PL4A
PL5D
PL5C
PL5B
PL5A
VSS
PL6D
PL6C
PL6B
PL6A
VDD
PL7D
PL7C
PL7B
PL7A
VSS
PL8D
PL8C
PL8B
PL8A
PL9D
PL9C
PL9B
PL9A
VDD
PL10D
PL10C
PL10B
VSS
VSS
PL1D
PL2D
PL3D
PL3C
PL3A
PL4D
PL4C
PL4B
PL4A
VDD
PL5D
PL5C
PL5B
PL5A
PL6D
PL6C
PL6B
PL6A
VSS
PL7D
PL7C
PL7B
PL7A
VDD
PL8D
PL8C
PL8B
PL8A
VSS
PL9D
PL9C
PL9B
PL9A
PL10D
PL10C
PL10B
PL10A
VDD
PL11D
PL11C
PL11B
VSS
VSS
PL1D
PL2D
PL3D
PL3C
PL3A
PL4A
PL5C
PL5B
PL5A
VDD
PL6D
PL6C
PL6B
PL6A
PL7D
PL7C
PL7B
PL7A
VSS
PL8D
PL8C
PL8B
PL8A
VDD
PL9D
PL9C
PL9B
PL9A
VSS
PL10D
PL10C
PL10B
PL10A
PL11D
PL11C
PL11B
PL11A
VDD
PL12D
PL12C
PL12B
VSS
VSS
PL1D
PL2D
PL3D
PL3A
PL4A
PL5A
PL6D
PL6B
PL6A
VDD
PL7D
PL7C
PL7B
PL7A
PL8D
PL8C
PL8B
PL8A
VSS
PL9D
PL9C
PL9B
PL9A
VDD
PL10D
PL10C
PL10B
PL10A
VSS
PL11D
PL11C
PL11B
PL11A
PL12D
PL12C
PL12B
PL12A
VDD
PL13D
PL13B
PL14D
2C/2T15A/B 2C/2T26A 2C/2T40A/B
Pad
Pad
Pad
VSS
VSS
PL1D
PL2D
PL4D
PL4A
PL5A
PL6A
PL7D
PL7B
PL7A
VDD
PL8D
PL8C
PL8B
PL8A
PL9D
PL9C
PL9B
PL9A
VSS
PL10D
PL10C
PL10B
PL10A
VDD
PL11D
PL11C
PL11B
PL11A
VSS
PL12D
PL12C
PL12B
PL12A
PL13D
PL13C
PL13B
PL13A
VDD
PL14D
PL14B
PL15D
VSS
VSS
PL1D
PL2D
PL4D
PL4A
PL5A
PL6A
PL7D
PL7B
PL7A
VDD
PL8D
PL8A
PL9D
PL9A
PL10D
PL10A
PL11D
PL11A
VSS
PL12D
PL12C
PL12B
PL12A
VDD
PL13D
PL13C
PL13B
PL13A
VSS
PL14D
PL14A
PL15D
PL15A
PL16D
PL16A
PL17D
PL17A
VDD
PL18D
PL18B
PL19D
VSS
VSS
PL1D
PL3D
PL5D
PL6D
PL8D
PL9A
PL10D
PL10B
PL10A
VDD
PL11D
PL11A
PL12D
PL12A
PL13D
PL13A
PL14D
PL14A
VSS
PL15D
PL15C
PL15B
PL15A
VDD
PL16D
PL16C
PL16B
PL16A
VSS
PL17D
PL17A
PL18D
PL18A
PL19D
PL19A
PL20D
PL20A
VDD
PL21D
PL21B
PL22D
Function
VSS
VSS
I/O
I/O-A0
I/O-VDD5
I/O
I/O-A1
I/O-A2
I/O
I/O
I/O-A3
VDD
I/O
I/O
I/O
I/O-A4
I/O-A5
I/O
I/O
I/O-A6
VSS
I/O
I/O
I/O
I/O-A7
VDD
I/O
I/O-VDD5
I/O
I/O-A8
VSS
I/O-A9
I/O
I/O
I/O-A10
I/O
I/O
I/O
I/O-A11
VDD
I/O-A12
I/O
I/O
SE
L
D E
IS C
C T
O D
N E
TI VI
N C
U E
ED S
Pin
Notes:
The OR2C04A and OR2T04A do not have bond pads connected to 208-pin SQFP package pin numbers 6, 45, 47, 56, 60, 102, 153, 154, 166,
201, and 203.
The pins labeled I/O-VDD5 are user I/Os for the OR2CxxA and OR2TxxB series, but they are connected to VDD5 for the OR2TxxA series.
Lattice Semiconductor
83
Data Sheet
November 2006
ORCA Series 2 FPGAs
Pin Information (continued)
Table 23. OR2C/2T04A, OR2C06A, OR2C/2T08A, OR2C/2T10A, OR2C12A, OR2C/2T15A/B,
OR2C/2T26A, and OR2C/2T40A/B 208-Pin SQFP/SQFP2 Pinout (continued)
2C/2T04A
Pad
2C06A Pad
2C/2T08A
Pad
2C/2T10A
Pad
2C12A Pad
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
PL9A
See Note
PL10D
See Note
PL10C
PL10B
PL10A
VSS
CCLK
VSS
VSS
PB1A
See Note
PB1B
PB1C
PB1D
See Note
PB2A
PB2B
PB2C
PB2D
VDD
PB3A
PB3B
PB3C
PB3D
PB4A
PB4B
PB4C
PB4D
VSS
PB5A
PB5B
PB5C
PB5D
VSS
PB6A
PB6B
PB6C
PB6D
VSS
PB7A
PB7B
PL10A
PL11D
PL11A
PL12D
PL12C
PL12B
PL12A
VSS
CCLK
VSS
VSS
PB1A
PB1B
PB1C
PB1D
PB2A
PB2D
PB3A
PB3B
PB3C
PB3D
VDD
PB4A
PB4B
PB4C
PB4D
PB5A
PB5B
PB5C
PB5D
VSS
PB6A
PB6B
PB6C
PB6D
VSS
PB7A
PB7B
PB7C
PB7D
VSS
PB8A
PB8B
PL11A
PL12D
PL12A
PL13D
PL13A
PL14D
PL14A
VSS
CCLK
VSS
VSS
PB1A
PB1D
PB2A
PB2D
PB3A
PB3D
PB4A
PB4B
PB4C
PB4D
VDD
PB5A
PB5B
PB5C
PB5D
PB6A
PB6B
PB6C
PB6D
VSS
PB7A
PB7B
PB7C
PB7D
VSS
PB8A
PB8B
PB8C
PB8D
VSS
PB9A
PB9B
PL13D
PL13B
PL14C
PL15D
PL15A
PL16D
PL16A
VSS
CCLK
VSS
VSS
PB1A
PB1D
PB2A
PB2D
PB3B
PB4D
PB5A
PB5B
PB5C
PB5D
VDD
PB6A
PB6B
PB6C
PB6D
PB7A
PB7B
PB7C
PB7D
VSS
PB8A
PB8B
PB8C
PB8D
VSS
PB9A
PB9B
PB9C
PB9D
VSS
PB10A
PB10B
PL14B
PL15D
PL16D
PL17D
PL17A
PL18C
PL18A
VSS
CCLK
VSS
VSS
PB1A
PB1D
PB2A
PB2D
PB3D
PB4D
PB5B
PB5D
PB6B
PB6D
VDD
PB7A
PB7B
PB7C
PB7D
PB8A
PB8B
PB8C
PB8D
VSS
PB9A
PB9B
PB9C
PB9D
VSS
PB10A
PB10B
PB10C
PB10D
VSS
PB11A
PB11B
2C/2T15A/B 2C/2T26A 2C/2T40A/B
Pad
Pad
Pad
PL15B
PL16D
PL17D
PL18D
PL19D
PL19A
PL20A
VSS
CCLK
VSS
VSS
PB1A
PB2A
PB2D
PB3D
PB4D
PB5D
PB6B
PB6D
PB7B
PB7D
VDD
PB8A
PB8B
PB8C
PB8D
PB9A
PB9B
PB9C
PB9D
VSS
PB10A
PB10B
PB10C
PB10D
VSS
PB11A
PB11B
PB11C
PB11D
VSS
PB12A
PB12B
PL19B
PL20D
PL21D
PL22D
PL23D
PL23A
PL24A
VSS
CCLK
VSS
VSS
PB1A
PB2A
PB2D
PB3D
PB4D
PB5D
PB6B
PB6D
PB7B
PB7D
VDD
PB8A
PB8D
PB9A
PB9D
PB10A
PB10D
PB11A
PB11D
VSS
PB12A
PB12B
PB12C
PB12D
VSS
PB13A
PB13B
PB13C
PB13D
VSS
PB14A
PB14D
PL22B
PL23D
PL25A
PL27D
PL28D
PL28A
PL30A
VSS
CCLK
VSS
VSS
PB1A
PB3A
PB3D
PB4D
PB5D
PB6D
PB7D
PB8D
PB9D
PB10D
VDD
PB11A
PB11D
PB12A
PB12D
PB13A
PB13D
PB14A
PB14D
VSS
PB15A
PB15B
PB15C
PB15D
VSS
PB16A
PB16B
PB16C
PB16D
VSS
PB17A
PB17D
Function
I/O-A13
I/O
I/O-A14
I/O
I/O
I/O
I/O-A15
VSS
CCLK
VSS
VSS
I/O-A16
I/O
I/O-VDD5
I/O
I/O-A17
I/O
I/O
I/O
I/O
I/O
VDD
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VSS
I/O
I/O
I/O
I/O
VSS
I/O
I/O
I/O
I/O
VSS
I/O-VDD5
I/O
SE
L
D E
IS C
C T
O D
N E
TI VI
N C
U E
ED S
Pin
Notes:
The OR2C04A and OR2T04A do not have bond pads connected to 208-pin SQFP package pin numbers 6, 45, 47, 56, 60, 102, 153, 154, 166,
201, and 203.
The pins labeled I/O-VDD5 are user I/Os for the OR2CxxA and OR2TxxB series, but they are connected to VDD5 for the OR2TxxA series.
84
Lattice Semiconductor
Data Sheet
November 2006
ORCA Series 2 FPGAs
Pin Information (continued)
Table 23. OR2C/2T04A, OR2C06A, OR2C/2T08A, OR2C/2T10A, OR2C12A, OR2C/2T15A/B,
OR2C/2T26A, and OR2C/2T40A/B 208-Pin SQFP/SQFP2 Pinout (continued)
2C/2T04A
Pad
2C06A Pad
2C/2T08A
Pad
2C/2T10A
Pad
2C12A Pad
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
PB7C
PB7D
PB8A
PB8B
PB8C
PB8D
VDD
PB9A
PB9B
PB9C
PB9D
PB10A
PB10B
PB10C
PB10D
See Note
VSS
DONE
VSS
RESET
PRGM
PR10A
PR10B
PR10C
PR10D
PR9A
PR9B
PR9C
PR9D
VDD
PR8A
PR8B
PR8C
PR8D
PR7A
PR7B
PR7C
PR7D
VSS
PR6A
PR6B
PR6C
PR6D
PB8C
PB8D
PB9A
PB9B
PB9C
PB9D
VDD
PB10A
PB10B
PB10C
PB10D
PB11A
PB11C
PB11D
PB12A
PB12D
VSS
DONE
VSS
RESET
PRGM
PR12A
PR12D
PR11A
PR11B
PR10A
PR10B
PR10C
PR10D
VDD
PR9A
PR9B
PR9C
PR9D
PR8A
PR8B
PR8C
PR8D
VSS
PR7A
PR7B
PR7C
PR7D
PB9C
PB9D
PB10A
PB10B
PB10C
PB10D
VDD
PB11A
PB11D
PB12A
PB12B
PB12C
PB12D
PB13A
PB13D
PB14D
VSS
DONE
VSS
RESET
PRGM
PR14A
PR13A
PR13D
PR12A
PR11A
PR11B
PR11C
PR11D
VDD
PR10A
PR10B
PR10C
PR10D
PR9A
PR9B
PR9C
PR9D
VSS
PR8A
PR8B
PR8C
PR8D
PB10C
PB10D
PB11A
PB11B
PB11C
PB11D
VDD
PB12A
PB13A
PB13B
PB13C
PB13D
PB14A
PB15A
PB15D
PB16D
VSS
DONE
VSS
RESET
PRGM
PR16A
PR15A
PR15D
PR14A
PR13B
PR13C
PR12A
PR12B
VDD
PR11A
PR11B
PR11C
PR11D
PR10A
PR10B
PR10C
PR10D
VSS
PR9A
PR9B
PR9C
PR9D
PB11C
PB11D
PB12A
PB12B
PB12C
PB12D
VDD
PB13A
PB13D
PB14A
PB14D
PB15A
PB16A
PB17A
PB18A
PB18D
VSS
DONE
VSS
RESET
PRGM
PR18A
PR18D
PR17B
PR16A
PR15D
PR14A
PR14D
PR13A
VDD
PR12A
PR12B
PR12C
PR12D
PR11A
PR11B
PR11C
PR11D
VSS
PR10A
PR10B
PR10C
PR10D
2C/2T15A/B 2C/2T26A 2C/2T40A/B
Pad
Pad
Pad
PB12C
PB12D
PB13A
PB13B
PB13C
PB13D
VDD
PB14A
PB14D
PB15A
PB15D
PB16A
PB17A
PB18A
PB19D
PB20D
VSS
DONE
VSS
RESET
PRGM
PR20A
PR19A
PR18A
PR17A
PR16D
PR15A
PR15D
PR14A
VDD
PR13A
PR13B
PR13C
PR13D
PR12A
PR12B
PR12C
PR12D
VSS
PR11A
PR11B
PR11C
PR11D
PB15A
PB15D
PB16A
PB16D
PB17A
PB17D
VDD
PB18A
PB18D
PB19A
PB19D
PB20A
PB21A
PB22A
PB23D
PB24D
VSS
DONE
VSS
RESET
PRGM
PR24A
PR23A
PR22A
PR21A
PR20D
PR19A
PR19D
PR18A
VDD
PR17A
PR17D
PR16A
PR16D
PR15A
PR15D
PR14A
PR14D
VSS
PR13A
PR13B
PR13C
PR13D
PB18A
PB18D
PB19A
PB19D
PB20A
PB20D
VDD
PB21A
PB22D
PB23A
PB24D
PB25A
PB26A
PB27A
PB28D
PB30D
VSS
DONE
VSS
RESET
PRGM
PR30A
PR28A
PR27A
PR26A
PR23D
PR22A
PR22D
PR21A
VDD
PR20A
PR20D
PR19A
PR19D
PR18A
PR18D
PR17A
PR17D
VSS
PR16A
PR16B
PR16C
PR16D
Function
I/O
I/O
I/O-HDC
I/O
I/O
I/O
VDD
I/O-LDC
I/O
I/O
I/O
I/O-INIT
I/O
I/O
I/O
I/O
VSS
DONE
VSS
RESET
PRGM
I/O-M0
I/O
I/O
I/O
I/O-M1
I/O
I/O-VDD5
I/O
VDD
I/O-M2
I/O
I/O
I/O
I/O-M3
I/O
I/O
I/O
VSS
I/O
I/O
I/O
I/O
SE
L
D E
IS C
C T
O D
N E
TI VI
N C
U E
ED S
Pin
Notes:
The OR2C04A and OR2T04A do not have bond pads connected to 208-pin SQFP package pin numbers 6, 45, 47, 56, 60, 102, 153, 154, 166,
201, and 203.
The pins labeled I/O-VDD5 are user I/Os for the OR2CxxA and OR2TxxB series, but they are connected to VDD5 for the OR2TxxA series.
Lattice Semiconductor
85
Data Sheet
November 2006
ORCA Series 2 FPGAs
Pin Information (continued)
Table 23. OR2C/2T04A, OR2C06A, OR2C/2T08A, OR2C/2T10A, OR2C12A, OR2C/2T15A/B,
OR2C/2T26A, and OR2C/2T40A/B 208-Pin SQFP/SQFP2 Pinout (continued)
2C/2T04A
Pad
2C06A Pad
2C/2T08A
Pad
2C/2T10A
Pad
2C12A Pad
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
VDD
PR5A
PR5B
PR5C
PR5D
VSS
PR4A
PR4B
PR4C
PR4D
PR3A
PR3B
PR3C
PR3D
VDD
PR2A
PR2B
PR2C
PR2D
PR1A
PR1B
PR1C
PR1D
See Note
See Note
VSS
RD_CFG
VSS
VSS
PT10D
PT10C
PT10B
PT10A
PT9D
PT9C
PT9B
See Note
PT9A
VDD
PT8D
PT8C
PT8B
PT8A
VDD
PR6A
PR6B
PR6C
PR6D
VSS
PR5A
PR5B
PR5C
PR5D
PR4A
PR4B
PR4C
PR4D
VDD
PR3A
PR3B
PR3C
PR3D
PR2A
PR2C
PR2D
PR1A
PR1C
PR1D
VSS
RD_CFG
VSS
VSS
PT12D
PT12A
PT11D
PT11C
PT11A
PT10D
PT10C
PT10B
PT10A
VDD
PT9D
PT9C
PT9B
PT9A
VDD
PR7A
PR7B
PR7C
PR7D
VSS
PR6A
PR6B
PR6C
PR6D
PR5A
PR5B
PR5C
PR5D
VDD
PR4A
PR4B
PR4C
PR4D
PR3A
PR3C
PR3D
PR2A
PR2D
PR1A
VSS
RD_CFG
VSS
VSS
PT14D
PT13D
PT13A
PT12D
PT12C
PT12A
PT11D
PT11C
PT11B
VDD
PT10D
PT10C
PT10B
PT10A
VDD
PR8A
PR8B
PR8C
PR8D
VSS
PR7A
PR7B
PR7C
PR7D
PR6A
PR6B
PR6C
PR6D
VDD
PR5A
PR4B
PR4C
PR4D
PR3A
PR3C
PR3D
PR2A
PR2D
PR1A
VSS
RD_CFG
VSS
VSS
PT16D
PT15D
PT15A
PT14D
PT13D
PT13B
PT13A
PT12D
PT12B
VDD
PT11D
PT11C
PT11B
PT11A
VDD
PR9A
PR9B
PR9C
PR9D
VSS
PR8A
PR8B
PR8C
PR8D
PR7A
PR7B
PR7C
PR7D
VDD
PR6A
PR6B
PR5B
PR5D
PR4A
PR4D
PR3A
PR2A
PR2C
PR1A
VSS
RD_CFG
VSS
VSS
PT18D
PT17D
PT16D
PT16A
PT15D
PT14D
PT14A
PT13D
PT13B
VDD
PT12D
PT12C
PT12B
PT12A
2C/2T15A/B 2C/2T26A 2C/2T40A/B
Pad
Pad
Pad
VDD
PR10A
PR10B
PR10C
PR10D
VSS
PR9A
PR9B
PR9C
PR9D
PR8A
PR8B
PR8C
PR8D
VDD
PR7A
PR7B
PR6B
PR6D
PR5A
PR5D
PR4A
PR3A
PR2A
PR1A
VSS
RD_CFG
VSS
VSS
PT20D
PT19A
PT17D
PT17A
PT16D
PT15D
PT15A
PT14D
PT14B
VDD
PT13D
PT13C
PT13B
PT13A
VDD
PR12A
PR12B
PR12C
PR12D
VSS
PR11A
PR11D
PR10A
PR10D
PR9A
PR9D
PR8A
PR8D
VDD
PR7A
PR7B
PR6B
PR6D
PR5A
PR5D
PR4A
PR3A
PR2A
PR1A
VSS
RD_CFG
VSS
VSS
PT24D
PT23A
PT21D
PT21A
PT20D
PT19D
PT19A
PT18D
PT18B
VDD
PT17D
PT17A
PT16D
PT16A
VDD
PR15A
PR15B
PR15C
PR15D
VSS
PR14A
PR14D
PR13A
PR13D
PR12A
PR12D
PR11A
PR11D
VDD
PR10A
PR10B
PR9B
PR9D
PR8A
PR6A
PR5A
PR4A
PR3A
PR2A
VSS
RD_CFG
VSS
VSS
PT30D
PT28A
PT26D
PT26A
PT25D
PT24D
PT23D
PT22D
PT21D
VDD
PT20D
PT20A
PT19D
PT19A
Function
VDD
I/O
I/O
I/O
I/O
VSS
I/O-VDD5
I/O
I/O
I/O
I/O-CS1
I/O
I/O
I/O
VDD
I/O-CS0
I/O
I/O
I/O
I/O-RD
I/O
I/O
I/O-WR
I/O
I/O
VSS
RD_CFG
VSS
VSS
I/O
I/O-RDY/RCLK
I/O
I/O
I/O-D7
I/O-VDD5
I/O
I/O
I/O-D6
VDD
I/O
I/O
I/O
I/O-D5
SE
L
D E
IS C
C T
O D
N E
TI VI
N C
U E
ED S
Pin
Notes:
The OR2C04A and OR2T04A do not have bond pads connected to 208-pin SQFP package pin numbers 6, 45, 47, 56, 60, 102, 153, 154, 166,
201, and 203.
The pins labeled I/O-VDD5 are user I/Os for the OR2CxxA and OR2TxxB series, but they are connected to VDD5 for the OR2TxxA series.
86
Lattice Semiconductor
Data Sheet
November 2006
ORCA Series 2 FPGAs
Pin Information (continued)
Table 23. OR2C/2T04A, OR2C06A, OR2C/2T08A, OR2C/2T10A, OR2C12A, OR2C/2T15A/B,
OR2C/2T26A, and OR2C/2T40A/B 208-Pin SQFP/SQFP2 Pinout (continued)
Pin
2C06A Pad
2C/2T08A
Pad
2C/2T10A
Pad
2C12A Pad
PT7D
PT7C
PT7B
PT7A
VSS
PT6D
PT6C
PT6B
PT6A
VSS
PT5D
PT5C
PT5B
PT5A
VSS
PT4D
PT4C
PT4B
PT4A
PT3D
PT3C
PT3B
PT3A
VDD
PT2D
PT2C
PT2B
PT2A
See Note
PT1D
See Note
PT1C
PT1B
PT1A
VSS
RD_DATA/
TDO
PT8D
PT8C
PT8B
PT8A
VSS
PT7D
PT7C
PT7B
PT7A
VSS
PT6D
PT6C
PT6B
PT6A
VSS
PT5D
PT5C
PT5B
PT5A
PT4D
PT4C
PT4B
PT4A
VDD
PT3D
PT3C
PT3B
PT3A
PT2D
PT2A
PT1D
PT1C
PT1B
PT1A
VSS
RD_DATA/
TDO
PT9D
PT9C
PT9B
PT9A
VSS
PT8D
PT8C
PT8B
PT8A
VSS
PT7D
PT7C
PT7B
PT7A
VSS
PT6D
PT6C
PT6B
PT6A
PT5D
PT5C
PT5B
PT5A
VDD
PT4D
PT4C
PT4B
PT4A
PT3D
PT3A
PT2D
PT2A
PT1D
PT1A
VSS
RD_DATA/
TDO
PT10D
PT10C
PT10B
PT10A
VSS
PT9D
PT9C
PT9B
PT9A
VSS
PT8D
PT8C
PT8B
PT8A
VSS
PT7D
PT7C
PT7B
PT7A
PT6D
PT6C
PT6B
PT6A
VDD
PT5D
PT5A
PT4D
PT4A
PT3D
PT3A
PT2D
PT2A
PT1D
PT1A
VSS
RD_DATA/
TDO
PT11D
PT11C
PT11B
PT11A
VSS
PT10D
PT10C
PT10B
PT10A
VSS
PT9D
PT9C
PT9B
PT9A
VSS
PT8D
PT8C
PT8B
PT8A
PT7D
PT7C
PT7B
PT7A
VDD
PT6D
PT6A
PT5C
PT5A
PT4A
PT3A
PT2C
PT2A
PT1D
PT1A
VSS
RD_DATA/
TDO
2C/2T15A/B 2C/2T26A 2C/2T40A/B
Pad
Pad
Pad
PT12D
PT12C
PT12B
PT12A
VSS
PT11D
PT11C
PT11B
PT11A
VSS
PT10D
PT10C
PT10B
PT10A
VSS
PT9D
PT9C
PT9B
PT9A
PT8D
PT8C
PT8B
PT8A
VDD
PT7D
PT7A
PT6C
PT6A
PT5A
PT4A
PT3A
PT2A
PT1D
PT1A
VSS
RD_DATA/
TDO
PT15D
PT15A
PT14D
PT14A
VSS
PT13D
PT13C
PT13B
PT13A
VSS
PT12D
PT12C
PT12B
PT12A
VSS
PT11D
PT11A
PT10D
PT10A
PT9D
PT9A
PT8D
PT8A
VDD
PT7D
PT7A
PT6C
PT6A
PT5A
PT4A
PT3A
PT2A
PT1D
PT1A
VSS
RD_DATA/
TDO
PT18D
PT18A
PT17D
PT17A
VSS
PT16D
PT16C
PT16B
PT16A
VSS
PT15D
PT15C
PT15B
PT15A
VSS
PT14D
PT14A
PT13D
PT13A
PT12D
PT12A
PT11D
PT11A
VDD
PT10D
PT9A
PT8A
PT7A
PT6A
PT5A
PT4A
PT3A
PT2D
PT1A
VSS
RD_DATA/
TDO
Function
I/O
I/O
I/O
I/O-D4
VSS
I/O
I/O
I/O
I/O-D3
VSS
I/O
I/O
I/O-VDD5
I/O-D2
VSS
I/O-D1
I/O
I/O
I/O-D0/DIN
I/O
I/O
I/O
I/O-DOUT
VDD
I/O
I/O
I/O
I/O-TDI
I/O
I/O-TMS
I/O
I/O
I/O
I/O-TCK
VSS
RD_DATA/TDO
SE
L
D E
IS C
C T
O D
N E
TI VI
N C
U E
ED S
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
2C/2T04A
Pad
Notes:
The OR2C04A and OR2T04A do not have bond pads connected to 208-pin SQFP package pin numbers 6, 45, 47, 56, 60, 102, 153, 154, 166,
201, and 203.
The pins labeled I/O-VDD5 are user I/Os for the OR2CxxA and OR2TxxB series, but they are connected to VDD5 for the OR2TxxA series.
Lattice Semiconductor
87
Data Sheet
November 2006
ORCA Series 2 FPGAs
Pin Information (continued)
Table 24. OR2C06A, OR2C/2T08A, OR2C/2T10A, OR2C12A, OR2C/2T15A/B, OR2C/2T26A,
and OR2C/2T40A/B 240-Pin SQFP/SQFP2 Pinout
2C/2T08A
Pad
2C/2T10A
2C/2T15B
2C12A Pad
Pad
Pad
2C/2T26A 2C/2T40A/B
Pad
Pad
Function
SE
L
D E
IS C
C T
O D
N E
TI VI
N C
U E
ED S
Pin 2C06A Pad
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
VSS
VDD
PL1D
PL1C
PL1B
PL1A
VSS
PL2D
PL2C
PL2B
PL2A
PL3D
PL3C
PL3B
PL3A
VDD
PL4D
PL4C
PL4B
PL4A
PL5D
PL5C
PL5B
PL5A
VSS
PL6D
PL6C
PL6B
PL6A
VDD
PL7D
PL7C
PL7B
PL7A
VSS
PL8D
PL8C
PL8B
PL8A
PL9D
PL9C
PL9B
VSS
VDD
PL1D
PL1B
PL1A
PL2D
VSS
PL3D
PL3C
PL3B
PL3A
PL4D
PL4C
PL4B
PL4A
VDD
PL5D
PL5C
PL5B
PL5A
PL6D
PL6C
PL6B
PL6A
VSS
PL7D
PL7C
PL7B
PL7A
VDD
PL8D
PL8C
PL8B
PL8A
VSS
PL9D
PL9C
PL9B
PL9A
PL10D
PL10C
PL10B
VSS
VDD
PL1D
PL1B
PL1A
PL2D
VSS
PL3D
PL3C
PL3B
PL3A
PL4A
PL5C
PL5B
PL5A
VDD
PL6D
PL6C
PL6B
PL6A
PL7D
PL7C
PL7B
PL7A
VSS
PL8D
PL8C
PL8B
PL8A
VDD
PL9D
PL9C
PL9B
PL9A
VSS
PL10D
PL10C
PL10B
PL10A
PL11D
PL11C
PL11B
VSS
VDD
PL1D
PL1C
PL1B
PL2D
VSS
PL3D
PL3A
PL4D
PL4A
PL5A
PL6D
PL6B
PL6A
VDD
PL7D
PL7C
PL7B
PL7A
PL8D
PL8C
PL8B
PL8A
VSS
PL9D
PL9C
PL9B
PL9A
VDD
PL10D
PL10C
PL10B
PL10A
VSS
PL11D
PL11C
PL11B
PL11A
PL12D
PL12C
PL12B
VSS
VDD
PL1D
PL1C
PL1B
PL2D
VSS
PL4D
PL4A
PL5D
PL5A
PL6A
PL7D
PL7B
PL7A
VDD
PL8D
PL8C
PL8B
PL8A
PL9D
PL9C
PL9B
PL9A
VSS
PL10D
PL10C
PL10B
PL10A
VDD
PL11D
PL11C
PL11B
PL11A
VSS
PL12D
PL12C
PL12B
PL12A
PL13D
PL13C
PL13B
VSS
VDD
PL1D
PL1C
PL1B
PL2D
VSS
PL4D
PL4A
PL5D
PL5A
PL6A
PL7D
PL7B
PL7A
VDD
PL8D
PL8A
PL9D
PL9A
PL10D
PL10A
PL11D
PL11A
VSS
PL12D
PL12C
PL12B
PL12A
VDD
PL13D
PL13C
PL13B
PL13A
VSS
PL14D
PL14A
PL15D
PL15A
PL16D
PL16A
PL17D
VSS
VDD
PL1D
PL1A
PL2D
PL3D
VSS
PL5D
PL6D
PL7D
PL8D
PL9A
PL10D
PL10B
PL10A
VDD
PL11D
PL11A
PL12D
PL12A
PL13D
PL13A
PL14D
PL14A
VSS
PL15D
PL15C
PL15B
PL15A
VDD
PL16D
PL16C
PL16B
PL16A
VSS
PL17D
PL17A
PL18D
PL18A
PL19D
PL19A
PL20D
VSS
VDD
I/O
I/O
I/O
I/O-A0
VSS
I/O-VDD5
I/O
I/O
I/O-A1
I/O-A2
I/O
I/O
I/O-A3
VDD
I/O
I/O
I/O
I/O-A4
I/O-A5
I/O
I/O
I/O-A6
VSS
I/O
I/O
I/O
I/O-A7
VDD
I/O
I/O-VDD5
I/O
I/O-A8
VSS
I/O-A9
I/O
I/O
I/O-A10
I/O
I/O
I/O
Notes:
The OR2C/2T08A and OR2C/2T10A do not have bond pads connected to 240-pin SQFP package pin numbers 113 and 188.
The pins labeled I/O-VDD5 are user I/Os for the OR2CxxA and OR2TxxB series, but they are connected to VDD5 for the OR2TxxA series.
88
Lattice Semiconductor
Data Sheet
November 2006
ORCA Series 2 FPGAs
Pin Information (continued)
Table 24. OR2C06A, OR2C/2T08A, OR2C/2T10A, OR2C12A, OR2C/2T15A/B, OR2C/2T26A,
and OR2C/2T40A/B 240-Pin SQFP/SQFP2 Pinout (continued)
2C/2T08A
Pad
2C/2T10A
2C/2T15B
2C12A Pad
Pad
Pad
2C/2T26A 2C/2T40A/B
Pad
Pad
Function
SE
L
D E
IS C
C T
O D
N E
TI VI
N C
U E
ED S
Pin 2C06A Pad
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
PL9A
VDD
PL10D
PL10C
PL10B
PL10A
PL11D
PL11C
PL11B
PL11A
VSS
PL12D
PL12C
PL12B
PL12A
VSS
CCLK
VDD
VSS
VSS
PB1A
PB1B
PB1C
PB1D
VSS
PB2A
PB2B
PB2C
PB2D
PB3A
PB3B
PB3C
PB3D
VDD
PB4A
PB4B
PB4C
PB4D
PB5A
PB5B
PB5C
PB5D
PL10A
VDD
PL11D
PL11C
PL11B
PL11A
PL12D
PL12C
PL12B
PL12A
VSS
PL13D
PL13A
PL14D
PL14A
VSS
CCLK
VDD
VSS
VSS
PB1A
PB1D
PB2A
PB2D
VSS
PB3A
PB3B
PB3C
PB3D
PB4A
PB4B
PB4C
PB4D
VDD
PB5A
PB5B
PB5C
PB5D
PB6A
PB6B
PB6C
PB6D
PL11A
VDD
PL12D
PL12C
PL12B
PL13D
PL13B
PL13A
PL14D
PL14C
VSS
PL15D
PL15A
PL16D
PL16A
VSS
CCLK
VDD
VSS
VSS
PB1A
PB1D
PB2A
PB2D
VSS
PB3B
PB4B
PB4C
PB4D
PB5A
PB5B
PB5C
PB5D
VDD
PB6A
PB6B
PB6C
PB6D
PB7A
PB7B
PB7C
PB7D
PL12A
VDD
PL13D
PL13B
PL14D
PL14B
PL14A
PL15D
PL15B
PL16D
VSS
PL17D
PL17A
PL18C
PL18A
VSS
CCLK
VDD
VSS
VSS
PB1A
PB1D
PB2A
PB2D
VSS
PB3D
PB4D
PB5A
PB5B
PB5D
PB6A
PB6B
PB6D
VDD
PB7A
PB7B
PB7C
PB7D
PB8A
PB8B
PB8C
PB8D
PL13A
VDD
PL14D
PL14B
PL15D
PL15B
PL15A
PL16D
PL16B
PL17D
VSS
PL18D
PL19D
PL19A
PL20A
VSS
CCLK
VDD
VSS
VSS
PB1A
PB2A
PB2D
PB3D
VSS
PB4D
PB5D
PB6A
PB6B
PB6D
PB7A
PB7B
PB7D
VDD
PB8A
PB8B
PB8C
PB8D
PB9A
PB9B
PB9C
PB9D
PL17A
VDD
PL18D
PL18B
PL19D
PL19B
PL19A
PL20D
PL20B
PL21D
VSS
PL22D
PL23D
PL23A
PL24A
VSS
CCLK
VDD
VSS
VSS
PB1A
PB2A
PB2D
PB3D
VSS
PB4D
PB5D
PB6A
PB6B
PB6D
PB7A
PB7B
PB7D
VDD
PB8A
PB8D
PB9A
PB9D
PB10A
PB10D
PB11A
PB11D
PL20A
VDD
PL21D
PL21B
PL22D
PL22B
PL22A
PL23D
PL24D
PL25A
VSS
PL27D
PL28D
PL28A
PL30A
VSS
CCLK
VDD
VSS
VSS
PB1A
PB3A
PB3D
PB4D
VSS
PB5D
PB6D
PB7A
PB7D
PB8D
PB9A
PB9D
PB10D
VDD
PB11A
PB11D
PB12A
PB12D
PB13A
PB13D
PB14A
PB14D
I/O-A11
VDD
I/O-A12
I/O
I/O
I/O-A13
I/O
I/O
I/O
I/O-A14
VSS
I/O
I/O
I/O
I/O-A15
VSS
CCLK
VDD
VSS
VSS
I/O-A16
I/O
I/O-VDD5
I/O
VSS
I/O-A17
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VDD
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Notes:
The OR2C/2T08A and OR2C/2T10A do not have bond pads connected to 240-pin SQFP package pin numbers 113 and 188.
The pins labeled I/O-VDD5 are user I/Os for the OR2CxxA and OR2TxxB series, but they are connected to VDD5 for the OR2TxxA series.
Lattice Semiconductor
89
Data Sheet
November 2006
ORCA Series 2 FPGAs
Pin Information (continued)
Table 24. OR2C06A, OR2C/2T08A, OR2C/2T10A, OR2C12A, OR2C/2T15A/B, OR2C/2T26A,
and OR2C/2T40A/B 240-Pin SQFP/SQFP2 Pinout (continued)
2C/2T08A
Pad
2C/2T10A
2C/2T15B
2C12A Pad
Pad
Pad
2C/2T26A 2C/2T40A/B
Pad
Pad
Function
SE
L
D E
IS C
C T
O D
N E
TI VI
N C
U E
ED S
Pin 2C06A Pad
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
VSS
PB6A
PB6B
PB6C
PB6D
VSS
PB7A
PB7B
PB7C
PB7D
VSS
PB8A
PB8B
PB8C
PB8D
PB9A
PB9B
PB9C
PB9D
VDD
PB10A
PB10B
PB10C
PB10D
PB11A
PB11B
PB11C
PB11D
VSS
PB12A
PB12B
PB12C
PB12D
VSS
DONE
VDD
VSS
RESET
PRGM
PR12A
PR12B
PR12C
VSS
PB7A
PB7B
PB7C
PB7D
VSS
PB8A
PB8B
PB8C
PB8D
VSS
PB9A
PB9B
PB9C
PB9D
PB10A
PB10B
PB10C
PB10D
VDD
PB11A
PB11D
PB12A
PB12B
PB12C
PB12D
PB13A
PB13B
See Note
PB13D
PB14A
PB14B
PB14D
VSS
DONE
VDD
VSS
RESET
PRGM
PR14A
PR14D
PR13A
VSS
PB8A
PB8B
PB8C
PB8D
VSS
PB9A
PB9B
PB9C
PB9D
VSS
PB10A
PB10B
PB10C
PB10D
PB11A
PB11B
PB11C
PB11D
VDD
PB12A
PB13A
PB13B
PB13C
PB13D
PB14A
PB15A
PB15B
See Note
PB15D
PB16A
PB16B
PB16D
VSS
DONE
VDD
VSS
RESET
PRGM
PR16A
PR16D
PR15A
VSS
PB9A
PB9B
PB9C
PB9D
VSS
PB10A
PB10B
PB10C
PB10D
VSS
PB11A
PB11B
PB11C
PB11D
PB12A
PB12B
PB12C
PB12D
VDD
PB13A
PB13D
PB14A
PB14D
PB15A
PB15D
PB16A
PB16D
VSS
PB17A
PB17D
PB18A
PB18D
VSS
DONE
VDD
VSS
RESET
PRGM
PR18A
PR18C
PR18D
VSS
PB10A
PB10B
PB10C
PB10D
VSS
PB11A
PB11B
PB11C
PB11D
VSS
PB12A
PB12B
PB12C
PB12D
PB13A
PB13B
PB13C
PB13D
VDD
PB14A
PB14D
PB15A
PB15D
PB16A
PB16D
PB17A
PB17D
VSS
PB18A
PB19A
PB19D
PB20D
VSS
DONE
VDD
VSS
RESET
PRGM
PR20A
PR20D
PR19A
VSS
PB12A
PB12B
PB12C
PB12D
VSS
PB13A
PB13B
PB13C
PB13D
VSS
PB14A
PB14D
PB15A
PB15D
PB16A
PB16D
PB17A
PB17D
VDD
PB18A
PB18D
PB19A
PB19D
PB20A
PB20D
PB21A
PB21D
VSS
PB22A
PB23A
PB23D
PB24D
VSS
DONE
VDD
VSS
RESET
PRGM
PR24A
PR24D
PR23A
VSS
PB15A
PB15B
PB15C
PB15D
VSS
PB16A
PB16B
PB16C
PB16D
VSS
PB17A
PB17D
PB18A
PB18D
PB19A
PB19D
PB20A
PB20D
VDD
PB21A
PB22D
PB23A
PB24D
PB25A
PB25D
PB26A
PB26D
VSS
PB27A
PB28A
PB28D
PB30D
VSS
DONE
VDD
VSS
RESET
PRGM
PR30A
PR29D
PR28A
VSS
I/O
I/O
I/O
I/O
VSS
I/O
I/O
I/O
I/O
VSS
I/O-VDD5
I/O
I/O
I/O
I/O-HDC
I/O
I/O
I/O
VDD
I/O-LDC
I/O
I/O
I/O
I/O-INIT
I/O
I/O
I/O
VSS
I/O
I/O
I/O
I/O
VSS
DONE
VDD
VSS
RESET
PRGM
I/O-M0
I/O
I/O
Notes:
The OR2C/2T08A and OR2C/2T10A do not have bond pads connected to 240-pin SQFP package pin numbers 113 and 188.
The pins labeled I/O-VDD5 are user I/Os for the OR2CxxA and OR2TxxB series, but they are connected to VDD5 for the OR2TxxA series.
90
Lattice Semiconductor
Data Sheet
November 2006
ORCA Series 2 FPGAs
Pin Information (continued)
Table 24. OR2C06A, OR2C/2T08A, OR2C/2T10A, OR2C12A, OR2C/2T15A/B, OR2C/2T26A,
and OR2C/2T40A/B 240-Pin SQFP/SQFP2 Pinout (continued)
2C/2T08A
Pad
2C/2T10A
2C/2T15B
2C12A Pad
Pad
Pad
2C/2T26A 2C/2T40A/B
Pad
Pad
Function
SE
L
D E
IS C
C T
O D
N E
TI VI
N C
U E
ED S
Pin 2C06A Pad
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
PR12D
VSS
PR11A
PR11B
PR11C
PR11D
PR10A
PR10B
PR10C
PR10D
VDD
PR9A
PR9B
PR9C
PR9D
PR8A
PR8B
PR8C
PR8D
VSS
PR7A
PR7B
PR7C
PR7D
VDD
PR6A
PR6B
PR6C
PR6D
VSS
PR5A
PR5B
PR5C
PR5D
PR4A
PR4B
PR4C
PR4D
VDD
PR3A
PR3B
PR3C
PR13D
VSS
PR12A
PR12B
PR12C
PR12D
PR11A
PR11B
PR11C
PR11D
VDD
PR10A
PR10B
PR10C
PR10D
PR9A
PR9B
PR9C
PR9D
VSS
PR8A
PR8B
PR8C
PR8D
VDD
PR7A
PR7B
PR7C
PR7D
VSS
PR6A
PR6B
PR6C
PR6D
PR5A
PR5B
PR5C
PR5D
VDD
PR4A
PR4B
PR4C
PR15D
VSS
PR14A
PR14C
PR14D
PR13A
PR13B
PR13C
PR12A
PR12B
VDD
PR11A
PR11B
PR11C
PR11D
PR10A
PR10B
PR10C
PR10D
VSS
PR9A
PR9B
PR9C
PR9D
VDD
PR8A
PR8B
PR8C
PR8D
VSS
PR7A
PR7B
PR7C
PR7D
PR6A
PR6B
PR6C
PR6D
VDD
PR5A
PR4B
PR4C
PR17B
VSS
PR16A
PR16D
PR15A
PR15C
PR15D
PR14A
PR14D
PR13A
VDD
PR12A
PR12B
PR12C
PR12D
PR11A
PR11B
PR11C
PR11D
VSS
PR10A
PR10B
PR10C
PR10D
VDD
PR9A
PR9B
PR9C
PR9D
VSS
PR8A
PR8B
PR8C
PR8D
PR7A
PR7B
PR7C
PR7D
VDD
PR6A
PR6B
PR5B
PR18A
VSS
PR17A
PR17D
PR16A
PR16C
PR16D
PR15A
PR15D
PR14A
VDD
PR13A
PR13B
PR13C
PR13D
PR12A
PR12B
PR12C
PR12D
VSS
PR11A
PR11B
PR11C
PR11D
VDD
PR10A
PR10B
PR10C
PR10D
VSS
PR9A
PR9B
PR9C
PR9D
PR8A
PR8B
PR8C
PR8D
VDD
PR7A
PR7B
PR6B
PR22A
VSS
PR21A
PR21D
PR20A
PR20C
PR20D
PR19A
PR19D
PR18A
VDD
PR17A
PR17D
PR16A
PR16D
PR15A
PR15D
PR14A
PR14D
VSS
PR13A
PR13B
PR13C
PR13D
VDD
PR12A
PR12B
PR12C
PR12D
VSS
PR11A
PR11D
PR10A
PR10D
PR9A
PR9D
PR8A
PR8D
VDD
PR7A
PR7B
PR6B
PR27A
VSS
PR26A
PR25A
PR24A
PR24D
PR23D
PR22A
PR22D
PR21A
VDD
PR20A
PR20D
PR19A
PR19D
PR18A
PR18D
PR17A
PR17D
VSS
PR16A
PR16B
PR16C
PR16D
VDD
PR15A
PR15B
PR15C
PR15D
VSS
PR14A
PR14D
PR13A
PR13D
PR12A
PR12D
PR11A
PR11D
VDD
PR10A
PR10B
PR9B
I/O
VSS
I/O
I/O
I/O
I/O
I/O-M1
I/O
I/O-VDD5
I/O
VDD
I/O-M2
I/O
I/O
I/O
I/O-M3
I/O
I/O
I/O
VSS
I/O
I/O
I/O
I/O
VDD
I/O
I/O
I/O
I/O
VSS
I/O-VDD5
I/O
I/O
I/O
I/O-CS1
I/O
I/O
I/O
VDD
I/O-CS0
I/O
I/O
Notes:
The OR2C/2T08A and OR2C/2T10A do not have bond pads connected to 240-pin SQFP package pin numbers 113 and 188.
The pins labeled I/O-VDD5 are user I/Os for the OR2CxxA and OR2TxxB series, but they are connected to VDD5 for the OR2TxxA series.
Lattice Semiconductor
91
Data Sheet
November 2006
ORCA Series 2 FPGAs
Pin Information (continued)
Table 24. OR2C06A, OR2C/2T08A, OR2C/2T10A, OR2C12A, OR2C/2T15A/B, OR2C/2T26A,
and OR2C/2T40A/B 240-Pin SQFP/SQFP2 Pinout (continued)
2C/2T08A
Pad
2C/2T10A
2C/2T15B
2C12A Pad
Pad
Pad
2C/2T26A 2C/2T40A/B
Pad
Pad
Function
SE
L
D E
IS C
C T
O D
N E
TI VI
N C
U E
ED S
Pin 2C06A Pad
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
PR3D
PR2A
PR2B
PR2C
PR2D
VSS
PR1A
PR1B
PR1C
PR1D
VSS
RD_CFGN
VSS
VDD
VSS
PT12D
PT12C
PT12B
PT12A
VSS
PT11D
PT11C
PT11B
PT11A
PT10D
PT10C
PT10B
PT10A
VDD
PT9D
PT9C
PT9B
PT9A
PT8D
PT8C
PT8B
PT8A
VSS
PT7D
PT7C
PT7B
PT7A
PR4D
PR3A
PR3B
PR3C
PR3D
VSS
PR2A
PR2D
PR1A
PR1D
VSS
RD_CFGN
VSS
VDD
VSS
PT14D
PT14C
PT14A
PT13D
See Note
PT13B
PT13A
PT12D
PT12C
PT12A
PT11D
PT11C
PT11B
VDD
PT10D
PT10C
PT10B
PT10A
PT9D
PT9C
PT9B
PT9A
VSS
PT8D
PT8C
PT8B
PT8A
PR4D
PR3A
PR3B
PR3C
PR3D
VSS
PR2A
PR2D
PR1A
PR1D
VSS
RD_CFGN
VSS
VDD
VSS
PT16D
PT16C
PT16A
PT15D
See Note
PT15B
PT15A
PT14D
PT13D
PT13B
PT13A
PT12D
PT12B
VDD
PT11D
PT11C
PT11B
PT11A
PT10D
PT10C
PT10B
PT10A
VSS
PT9D
PT9C
PT9B
PT9A
PR5D
PR4A
PR4B
PR4D
PR3A
VSS
PR2A
PR2C
PR1A
PR1D
VSS
RD_CFGN
VSS
VDD
VSS
PT18D
PT18B
PT18A
PT17D
VSS
PT16D
PT16C
PT16A
PT15D
PT14D
PT14A
PT13D
PT13B
VDD
PT12D
PT12C
PT12B
PT12A
PT11D
PT11C
PT11B
PT11A
VSS
PT10D
PT10C
PT10B
PT10A
PR6D
PR5A
PR5B
PR5D
PR4A
VSS
PR3A
PR2A
PR1A
PR1D
VSS
RD_CFGN
VSS
VDD
VSS
PT20D
PT20A
PT19D
PT19A
VSS
PT17D
PT17C
PT17A
PT16D
PT15D
PT15A
PT14D
PT14B
VDD
PT13D
PT13C
PT13B
PT13A
PT12D
PT12C
PT12B
PT12A
VSS
PT11D
PT11C
PT11B
PT11A
PR6D
PR5A
PR5B
PR5D
PR4A
VSS
PR3A
PR2A
PR1A
PR1D
VSS
RD_CFGN
VSS
VDD
VSS
PT24D
PT24A
PT23D
PT23A
VSS
PT21D
PT21C
PT21A
PT20D
PT19D
PT19A
PT18D
PT18B
VDD
PT17D
PT17A
PT16D
PT16A
PT15D
PT15A
PT14D
PT14A
VSS
PT13D
PT13C
PT13B
PT13A
PR9D
PR8A
PR7A
PR6A
PR5A
VSS
PR4A
PR3A
PR2A
PR1D
VSS
RD_CFGN
VSS
VDD
VSS
PT30D
PT29A
PT28D
PT28A
VSS
PT26D
PT26C
PT26A
PT25D
PT24D
PT23D
PT22D
PT21D
VDD
PT20D
PT20A
PT19D
PT19A
PT18D
PT18A
PT17D
PT17A
VSS
PT16D
PT16C
PT16B
PT16A
I/O
I/O-RD
I/O
I/O
I/O
VSS
I/O-WR
I/O
I/O
I/O
VSS
RD_CFGN
VSS
VDD
VSS
I/O
I/O
I/O
I/O-RDY/RCLK
VSS
I/O
I/O
I/O
I/O-D7
I/O-VDD5
I/O
I/O
I/O-D6
VDD
I/O
I/O
I/O
I/O-D5
I/O
I/O
I/O
I/O-D4
VSS
I/O
I/O
I/O
I/O-D3
Notes:
The OR2C/2T08A and OR2C/2T10A do not have bond pads connected to 240-pin SQFP package pin numbers 113 and 188.
The pins labeled I/O-VDD5 are user I/Os for the OR2CxxA and OR2TxxB series, but they are connected to VDD5 for the OR2TxxA series.
92
Lattice Semiconductor
Data Sheet
November 2006
ORCA Series 2 FPGAs
Pin Information (continued)
Table 24. OR2C06A, OR2C/2T08A, OR2C/2T10A, OR2C12A, OR2C/2T15A/B, OR2C/2T26A,
and OR2C/2T40A/B 240-Pin SQFP/SQFP2 Pinout (continued)
2C/2T08A
Pad
2C/2T10A
2C/2T15B
2C12A Pad
Pad
Pad
2C/2T26A 2C/2T40A/B
Pad
Pad
Function
SE
L
D E
IS C
C T
O D
N E
TI VI
N C
U E
ED S
Pin 2C06A Pad
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
VSS
PT6D
PT6C
PT6B
PT6A
VSS
PT5D
PT5C
PT5B
PT5A
PT4D
PT4C
PT4B
PT4A
VDD
PT3D
PT3C
PT3B
PT3A
PT2D
PT2C
PT2B
PT2A
VSS
PT1D
PT1C
PT1B
PT1A
VSS
RD_DATA/
TDO
VSS
PT7D
PT7C
PT7B
PT7A
VSS
PT6D
PT6C
PT6B
PT6A
PT5D
PT5C
PT5B
PT5A
VDD
PT4D
PT4C
PT4B
PT4A
PT3D
PT3C
PT3B
PT3A
VSS
PT2D
PT2A
PT1D
PT1A
VSS
RD_DATA/
TDO
VSS
PT8D
PT8C
PT8B
PT8A
VSS
PT7D
PT7C
PT7B
PT7A
PT6D
PT6C
PT6B
PT6A
VDD
PT5D
PT5A
PT4D
PT4A
PT3D
PT3C
PT3B
PT3A
VSS
PT2D
PT2A
PT1D
PT1A
VSS
RD_DATA/
TDO
VSS
PT9D
PT9C
PT9B
PT9A
VSS
PT8D
PT8C
PT8B
PT8A
PT7D
PT7C
PT7B
PT7A
VDD
PT6D
PT6A
PT5C
PT5A
PT4D
PT4A
PT3D
PT3A
VSS
PT2C
PT2A
PT1D
PT1A
VSS
RD_DATA/
TDO
VSS
PT10D
PT10C
PT10B
PT10A
VSS
PT9D
PT9C
PT9B
PT9A
PT8D
PT8C
PT8B
PT8A
VDD
PT7D
PT7A
PT6C
PT6A
PT5D
PT5A
PT4D
PT4A
VSS
PT3A
PT2A
PT1D
PT1A
VSS
RD_DATA/
TDO
VSS
PT12D
PT12C
PT12B
PT12A
VSS
PT11D
PT11A
PT10D
PT10A
PT9D
PT9A
PT8D
PT8A
VDD
PT7D
PT7A
PT6C
PT6A
PT5D
PT5A
PT4D
PT4A
VSS
PT3A
PT2A
PT1D
PT1A
VSS
RD_DATA/
TDO
VSS
PT15D
PT15C
PT15B
PT15A
VSS
PT14D
PT14A
PT13D
PT13A
PT12D
PT12A
PT11D
PT11A
VDD
PT10D
PT9A
PT8A
PT7A
PT6D
PT6A
PT5D
PT5A
VSS
PT4A
PT3A
PT2D
PT1A
VSS
RD_DATA/
TDO
VSS
I/O
I/O
I/O-VDD5
I/O-D2
VSS
I/O-D1
I/O
I/O
I/O-D0/DIN
I/O
I/O
I/O
I/O-DOUT
VDD
I/O
I/O
I/O
I/O-TDI
I/O
I/O
I/O
I/O-TMS
VSS
I/O
I/O
I/O
I/O-TCK
VSS
RD_DATA/TDO
Notes:
The OR2C/2T08A and OR2C/2T10A do not have bond pads connected to 240-pin SQFP package pin numbers 113 and 188.
The pins labeled I/O-VDD5 are user I/Os for the OR2CxxA and OR2TxxB series, but they are connected to VDD5 for the OR2TxxA series.
Lattice Semiconductor
93
Data Sheet
November 2006
ORCA Series 2 FPGAs
Pin Information (continued)
Table 25. OR2C06A, OR2T08A, OR2C/2T10A, OR2C12A, and OR2C/2T15A/B
256-Pin PBGA Pinout
2C06A Pad
2T08A Pad
2C/2T10A Pad
2C12A Pad
2C/2T15A/B Pad
Function
C2
D2
D3
E4
C1
D1
E3
E2
E1
F3
G4
F2
F1
G3
G2
G1
H3
H2
H1
J4
J3
J2
J1
K2
K3
K1
L1
L2
L3
L4
M1
M2
M3
M4
N1
N2
N3
P1
P2
R1
PL1D
PL1C
PL1B
PL1A
—
—
—
PL2D
PL2C
PL2B
PL2A
—
PL3D
PL3C
PL3B
PL3A
PL4D
PL4C
PL4B
PL4A
PL5D
PL5C
PL5B
PL5A
PL6D
PL6C
PL6B
PL6A
PL7D
PL7C
PL7B
PL7A
PL8D
PL8C
PL8B
PL8A
PL9D
PL9C
PL9B
PL9A
PL1D
PL1B
PL1A
PL2D
PL2C
PL2B
PL2A
PL3D
PL3C
PL3B
PL3A
—
PL4D
PL4C
PL4B
PL4A
PL5D
PL5C
PL5B
PL5A
PL6D
PL6C
PL6B
PL6A
PL7D
PL7C
PL7B
PL7A
PL8D
PL8C
PL8B
PL8A
PL9D
PL9C
PL9B
PL9A
PL10D
PL10C
PL10B
PL10A
PL1D
PL1B
PL1A
PL2D
PL2C
PL2B
PL2A
PL3D
PL3C
PL3B
PL3A
PL4D
PL4A
PL5C
PL5B
PL5A
PL6D
PL6C
PL6B
PL6A
PL7D
PL7C
PL7B
PL7A
PL8D
PL8C
PL8B
PL8A
PL9D
PL9C
PL9B
PL9A
PL10D
PL10C
PL10B
PL10A
PL11D
PL11C
PL11B
PL11A
PL1D
PL1C
PL1B
PL2D
PL2C
PL2B
PL2A
PL3D
PL3A
PL4D
PL4A
PL5D
PL5A
PL6D
PL6B
PL6A
PL7D
PL7C
PL7B
PL7A
PL8D
PL8C
PL8B
PL8A
PL9D
PL9C
PL9B
PL9A
PL10D
PL10C
PL10B
PL10A
PL11D
PL11C
PL11B
PL11A
PL12D
PL12C
PL12B
PL12A
PL1D
PL1C
PL1B
PL2D
PL2A
PL3D
PL3A
PL4D
PL4A
PL5D
PL5A
PL6D
PL6A
PL7D
PL7B
PL7A
PL8D
PL8C
PL8B
PL8A
PL9D
PL9C
PL9B
PL9A
PL10D
PL10C
PL10B
PL10A
PL11D
PL11C
PL11B
PL11A
PL12D
PL12C
PL12B
PL12A
PL13D
PL13C
PL13B
PL13A
I/O
I/O
I/O
I/O-A0
I/O
I/O
I/O
I/O-VDD5
I/O
I/O
I/O-A1
I/O
I/O-A2
I/O
I/O
I/O-A3
I/O
I/O
I/O
I/O-A4
I/O-A5
I/O
I/O
I/O-A6
I/O
I/O
I/O
I/O-A7
I/O
I/O-VDD5
I/O
I/O-A8
I/O-A9
I/O
I/O
I/O-A10
I/O
I/O
I/O
I/O-A11
SE
L
D E
IS C
C T
O D
N E
TI VI
N C
U E
ED S
Pin
Notes:
The W3 pin on the 256-pin PBGA package is unconnected for all devices listed in this table.
The OR2C/2T08A do not have bond pads connected to the 256-pin PBGA package pins F2 and Y17.
The pins labeled I/O-VDD5 are user I/Os for the OR2CxxA and OR2TxxB series, but they are connected to VDD5 for the OR2TxxA series.
The pins labeled VSS-ETC are the 4 x 4 array of thermal balls located at the center of the package. The balls can be attached to the ground
plane of the board for enhanced thermal capability (see Table 29), or they can be left unconnected.
94
Lattice Semiconductor
Data Sheet
November 2006
ORCA Series 2 FPGAs
Pin Information (continued)
Table 25. OR2C06A, OR2T08A, OR2C/2T10A, OR2C12A, and OR2C/2T15A/B
256-Pin PBGA Pinout (continued)
2C06A Pad
2T08A Pad
2C/2T10A Pad
2C12A Pad
2C/2T15A/B Pad
Function
P3
R2
T1
P4
R3
T2
U1
T3
U2
V1
T4
U3
V2
W1
V3
W2
Y1
Y2
W4
V4
U5
Y3
Y4
V5
W5
Y5
V6
U7
W6
Y6
V7
W7
Y7
V8
W8
Y8
U9
V9
W9
Y9
PL10D
PL10C
PL10B
PL10A
PL11D
PL11C
PL11B
PL11A
—
PL12D
PL12C
PL12B
—
—
—
PL12A
CCLK
PB1A
—
PB1B
PB1C
PB1D
—
—
PB2A
PB2B
PB2C
PB2D
PB3A
PB3B
PB3C
PB3D
PB4A
PB4B
PB4C
PB4D
PB5A
PB5B
PB5C
PB5D
PL11D
PL11C
PL11B
PL11A
PL12D
PL12C
PL12B
PL12A
PL13D
PL13C
PL13B
PL13A
PL14D
PL14C
PL14B
PL14A
CCLK
PB1A
PB1C
PB1D
PB2A
PB2B
PB2C
PB2D
PB3A
PB3B
PB3C
PB3D
PB4A
PB4B
PB4C
PB4D
PB5A
PB5B
PB5C
PB5D
PB6A
PB6B
PB6C
PB6D
PL12D
PL12C
PL12B
PL13D
PL13B
PL13A
PL14D
PL14C
PL15D
PL15C
PL15B
PL15A
PL16D
PL16C
PL16B
PL16A
CCLK
PB1A
PB1C
PB1D
PB2A
PB2B
PB2C
PB2D
PB3B
PB4B
PB4C
PB4D
PB5A
PB5B
PB5C
PB5D
PB6A
PB6B
PB6C
PB6D
PB7A
PB7B
PB7C
PB7D
PL13D
PL13B
PL14D
PL14B
PL14A
PL15D
PL15B
PL16D
PL17D
PL17C
PL17B
PL17A
PL18D
PL18C
PL18B
PL18A
CCLK
PB1A
PB1C
PB1D
PB2A
PB2B
PB2C
PB2D
PB3D
PB4D
PB5A
PB5B
PB5D
PB6A
PB6B
PB6D
PB7A
PB7B
PB7C
PB7D
PB8A
PB8B
PB8C
PB8D
PL14D
PL14B
PL15D
PL15B
PL15A
PL16D
PL16B
PL17D
PL18D
PL18C
PL18A
PL19D
PL19C
PL19A
PL20D
PL20A
CCLK
PB1A
PB1D
PB2A
PB2D
PB3A
PB3C
PB3D
PB4D
PB5D
PB6A
PB6B
PB6D
PB7A
PB7B
PB7D
PB8A
PB8B
PB8C
PB8D
PB9A
PB9B
PB9C
PB9D
I/O-A12
I/O
I/O
I/O-A13
I/O
I/O
I/O
I/O-A14
I/O-VDD5
I/O
I/O
I/O
I/O
I/O
I/O
I/O-A15
CCLK
I/O-A16
I/O
I/O
I/O-VDD5
I/O
I/O
I/O
I/O-A17
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
SE
L
D E
IS C
C T
O D
N E
TI VI
N C
U E
ED S
Pin
Notes:
The W3 pin on the 256-pin PBGA package is unconnected for all devices listed in this table.
The OR2C/2T08A do not have bond pads connected to the 256-pin PBGA package pins F2 and Y17.
The pins labeled I/O-VDD5 are user I/Os for the OR2CxxA and OR2TxxB series, but they are connected to VDD5 for the OR2TxxA series.
The pins labeled VSS-ETC are the 4 x 4 array of thermal balls located at the center of the package. The balls can be attached to the ground
plane of the board for enhanced thermal capability (see Table 29), or they can be left unconnected.
Lattice Semiconductor
95
Data Sheet
November 2006
ORCA Series 2 FPGAs
Pin Information (continued)
Table 25. OR2C06A, OR2T08A, OR2C/2T10A, OR2C12A, and OR2C/2T15A/B
256-Pin PBGA Pinout (continued)
2C06A Pad
2T08A Pad
2C/2T10A Pad
2C12A Pad
2C/2T15A/B Pad
Function
W10
V10
Y10
Y11
W11
V11
U11
Y12
W12
V12
U12
Y13
W13
V13
Y14
W14
Y15
V14
W15
Y16
U14
V15
W16
Y17
V16
W17
Y18
U16
V17
W18
Y19
V18
W19
Y20
W20
V19
U19
U18
T17
V20
PB6A
PB6B
PB6C
PB6D
PB7A
PB7B
PB7C
PB7D
PB8A
PB8B
PB8C
PB8D
PB9A
PB9B
PB9C
PB9D
PB10A
PB10B
PB10C
PB10D
—
—
PB11A
—
—
PB11B
PB11C
PB11D
PB12A
PB12B
PB12C
PB12D
—
DONE
PB7A
PB7B
PB7C
PB7D
PB8A
PB8B
PB8C
PB8D
PB9A
PB9B
PB9C
PB9D
PB10A
PB10B
PB10C
PB10D
PB11A
PB11B
PB11C
PB11D
PB12A
PB12B
PB12C
—
PB12D
PB13A
PB13B
PB13C
PB13D
PB14A
PB14B
PB14C
PB14D
DONE
PB8A
PB8B
PB8C
PB8D
PB9A
PB9B
PB9C
PB9D
PB10A
PB10B
PB10C
PB10D
PB11A
PB11B
PB11C
PB11D
PB12A
PB12C
PB12D
PB13A
PB13B
PB13C
PB13D
PB14A
PB14B
PB15A
PB15B
PB15C
PB15D
PB16A
PB16B
PB16C
PB16D
DONE
PB9A
PB9B
PB9C
PB9D
PB10A
PB10B
PB10C
PB10D
PB11A
PB11B
PB11C
PB11D
PB12A
PB12B
PB12C
PB12D
PB13A
PB13B
PB13C
PB13D
PB14A
PB14D
PB15A
PB15D
PB16A
PB16D
PB17A
PB17C
PB17D
PB18A
PB18B
PB18C
PB18D
DONE
PB10A
PB10B
PB10C
PB10D
PB11A
PB11B
PB11C
PB11D
PB12A
PB12B
PB12C
PB12D
PB13A
PB13B
PB13C
PB13D
PB14A
PB14B
PB14C
PB14D
PB15A
PB15D
PB16A
PB16D
PB17A
PB17D
PB18A
PB18D
PB19A
PB19D
PB20A
PB20B
PB20D
DONE
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O-VDD5
I/O
I/O
I/O
I/O-HDC
I/O
I/O
I/O
I/O-LDC
I/O
I/O
I/O
I/O
I/O
I/O-INIT
I/O
I/O-VDD5
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
DONE
RESET
PRGM
RESET
PRGM
RESET
PRGM
RESET
PRGM
RESET
PRGM
RESET
PRGM
PR12A
—
—
—
PR14A
PR14C
PR14D
PR13A
PR16A
PR16C
PR16D
PR15A
PR18A
PR18C
PR18D
PR17A
PR20A
PR20D
PR19A
PR19D
I/O-M0
I/O
I/O
I/O
SE
L
D E
IS C
C T
O D
N E
TI VI
N C
U E
ED S
Pin
Notes:
The W3 pin on the 256-pin PBGA package is unconnected for all devices listed in this table.
The OR2C/2T08A do not have bond pads connected to the 256-pin PBGA package pins F2 and Y17.
The pins labeled I/O-VDD5 are user I/Os for the OR2CxxA and OR2TxxB series, but they are connected to VDD5 for the OR2TxxA series.
The pins labeled VSS-ETC are the 4 x 4 array of thermal balls located at the center of the package. The balls can be attached to the ground
plane of the board for enhanced thermal capability (see Table 29), or they can be left unconnected.
96
Lattice Semiconductor
Data Sheet
November 2006
ORCA Series 2 FPGAs
Pin Information (continued)
Table 25. OR2C06A, OR2T08A, OR2C/2T10A, OR2C12A, and OR2C/2T15A/B
256-Pin PBGA Pinout (continued)
2C06A Pad
2T08A Pad
2C/2T10A Pad
2C12A Pad
2C/2T15A/B Pad
Function
U20
T18
T19
T20
R18
P17
R19
R20
P18
P19
P20
N18
N19
N20
M17
M18
M19
M20
L19
L18
L20
K20
K19
K18
K17
J20
J19
J18
J17
H20
H19
H18
G20
G19
F20
G18
F19
E20
G17
F18
PR12B
PR12C
PR12D
PR11A
PR11B
PR11C
PR11D
PR10A
PR10B
PR10C
PR10D
PR9A
PR9B
PR9C
PR9D
PR8A
PR8B
PR8C
PR8D
PR7A
PR7B
PR7C
PR7D
PR6A
PR6B
PR6C
PR6D
PR5A
PR5B
PR5C
PR5D
PR4A
PR4B
PR4C
PR4D
PR3A
PR3B
PR3C
PR3D
PR2A
PR13B
PR13C
PR13D
PR12A
PR12B
PR12C
PR12D
PR11A
PR11B
PR11C
PR11D
PR10A
PR10B
PR10C
PR10D
PR9A
PR9B
PR9C
PR9D
PR8A
PR8B
PR8C
PR8D
PR7A
PR7B
PR7C
PR7D
PR6A
PR6B
PR6C
PR6D
PR5A
PR5B
PR5C
PR5D
PR4A
PR4B
PR4C
PR4D
PR3A
PR15B
PR15C
PR15D
PR14A
PR14C
PR14D
PR13A
PR13B
PR13C
PR12A
PR12B
PR11A
PR11B
PR11C
PR11D
PR10A
PR10B
PR10C
PR10D
PR9A
PR9B
PR9C
PR9D
PR8A
PR8B
PR8C
PR8D
PR7A
PR7B
PR7C
PR7D
PR6A
PR6B
PR6C
PR6D
PR5A
PR4B
PR4C
PR4D
PR3A
PR17B
PR17C
PR17D
PR16A
PR16D
PR15A
PR15C
PR15D
PR14A
PR14D
PR13A
PR12A
PR12B
PR12C
PR12D
PR11A
PR11B
PR11C
PR11D
PR10A
PR10B
PR10C
PR10D
PR9A
PR9B
PR9C
PR9D
PR8A
PR8B
PR8C
PR8D
PR7A
PR7B
PR7C
PR7D
PR6A
PR6B
PR5B
PR5D
PR4A
PR18A
PR18B
PR18D
PR17A
PR17D
PR16A
PR16C
PR16D
PR15A
PR15D
PR14A
PR13A
PR13B
PR13C
PR13D
PR12A
PR12B
PR12C
PR12D
PR11A
PR11B
PR11C
PR11D
PR10A
PR10B
PR10C
PR10D
PR9A
PR9B
PR9C
PR9D
PR8A
PR8B
PR8C
PR8D
PR7A
PR7B
PR6B
PR6D
PR5A
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O-M1
I/O
I/O-VDD5
I/O
I/O-M2
I/O
I/O
I/O
I/O-M3
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O-VDD5
I/O
I/O
I/O
I/O-CS1
I/O
I/O
I/O
I/O-CS0
I/O
I/O
I/O
I/O-RD
SE
L
D E
IS C
C T
O D
N E
TI VI
N C
U E
ED S
Pin
Notes:
The W3 pin on the 256-pin PBGA package is unconnected for all devices listed in this table.
The OR2C/2T08A do not have bond pads connected to the 256-pin PBGA package pins F2 and Y17.
The pins labeled I/O-VDD5 are user I/Os for the OR2CxxA and OR2TxxB series, but they are connected to VDD5 for the OR2TxxA series.
The pins labeled VSS-ETC are the 4 x 4 array of thermal balls located at the center of the package. The balls can be attached to the ground
plane of the board for enhanced thermal capability (see Table 29), or they can be left unconnected.
Lattice Semiconductor
97
Data Sheet
November 2006
ORCA Series 2 FPGAs
Pin Information (continued)
Table 25. OR2C06A, OR2T08A, OR2C/2T10A, OR2C12A, and OR2C/2T15A/B
256-Pin PBGA Pinout (continued)
2C06A Pad
2T08A Pad
2C/2T10A Pad
2C12A Pad
2C/2T15A/B Pad
Function
E19
D20
E18
D19
C20
E17
D18
C19
B20
C18
B19
A20
A19
B18
B17
C17
D16
A18
A17
C16
B16
A16
C15
D14
B15
A15
C14
B14
A14
C13
B13
A13
D12
C12
B12
A12
B11
C11
A11
A10
PR2B
PR2C
PR2D
PR1A
PR1B
PR1C
PR1D
—
—
—
—
PR3B
PR3C
PR3D
PR2A
PR2B
PR2C
PR2D
PR1A
PR1B
PR1C
PR1D
PR3B
PR3C
PR3D
PR2A
PR2B
PR2C
PR2D
PR1A
PR1B
PR1C
PR1D
PR4B
PR4D
PR3A
PR2A
PR2B
PR2C
PR2D
PR1A
PR1B
PR1C
PR1D
PR5B
PR5D
PR4A
PR3A
PR3B
PR2A
PR2D
PR1A
PR1B
PR1C
PR1D
I/O
I/O
I/O-VDD5
I/O-WR
I/O
I/O
I/O
I/O
I/O
I/O
I/O
RD_CFGN
RD_CFGN
RD_CFGN
RD_CFGN
RD_CFGN
RD_CFGN
—
PT12D
PT12C
PT12B
PT12A
—
PT11D
PT11C
PT11B
PT11A
—
PT10D
PT10C
PT10B
PT10A
PT9D
PT9C
—
PT9B
PT9A
PT8D
PT8C
PT8B
PT8A
PT7D
PT7C
PT7B
PT7A
PT14D
PT14C
PT14B
PT14A
PT13D
PT13C
PT13B
PT13A
PT12D
PT12C
PT12B
PT12A
PT11D
PT11C
PT11B
PT11A
PT10D
PT10C
PT10B
PT10A
PT9D
PT9C
PT9B
PT9A
PT8D
PT8C
PT8B
PT8A
PT16D
PT16C
PT16B
PT16A
PT15D
PT15C
PT15B
PT15A
PT14D
PT13D
PT13C
PT13B
PT13A
PT12D
PT12B
PT12A
PT11D
PT11C
PT11B
PT11A
PT10D
PT10C
PT10B
PT10A
PT9D
PT9C
PT9B
PT9A
PT18D
PT18C
PT18B
PT18A
PT17D
PT17A
PT16D
PT16C
PT16A
PT15D
PT15A
PT14D
PT14A
PT13D
PT13B
PT13A
PT12D
PT12C
PT12B
PT12A
PT11D
PT11C
PT11B
PT11A
PT10D
PT10C
PT10B
PT10A
PT20D
PT20C
PT20A
PT19D
PT19A
PT18A
PT17D
PT17C
PT17A
PT16D
PT16A
PT15D
PT15A
PT14D
PT14B
PT14A
PT13D
PT13C
PT13B
PT13A
PT12D
PT12C
PT12B
PT12A
PT11D
PT11C
PT11B
PT11A
I/O
I/O
I/O
I/O
SE
L
D E
IS C
C T
O D
N E
TI VI
N C
U E
ED S
Pin
I/O-RDY/RCLK
I/O
I/O
I/O
I/O
I/O-D7
I/O
I/O-VDD5
I/O
I/O
I/O-D6
I/O
I/O
I/O
I/O
I/O-D5
I/O
I/O
I/O
I/O-D4
I/O
I/O
I/O
I/O-D3
Notes:
The W3 pin on the 256-pin PBGA package is unconnected for all devices listed in this table.
The OR2C/2T08A do not have bond pads connected to the 256-pin PBGA package pins F2 and Y17.
The pins labeled I/O-VDD5 are user I/Os for the OR2CxxA and OR2TxxB series, but they are connected to VDD5 for the OR2TxxA series.
The pins labeled VSS-ETC are the 4 x 4 array of thermal balls located at the center of the package. The balls can be attached to the ground
plane of the board for enhanced thermal capability (see Table 29), or they can be left unconnected.
98
Lattice Semiconductor
Data Sheet
November 2006
ORCA Series 2 FPGAs
Pin Information (continued)
Table 25. OR2C06A, OR2T08A, OR2C/2T10A, OR2C12A, and OR2C/2T15A/B
256-Pin PBGA Pinout (continued)
2C06A Pad
2T08A Pad
2C/2T10A Pad
2C12A Pad
2C/2T15A/B Pad
Function
B10
C10
D10
A9
B9
C9
D9
A8
B8
C8
A7
B7
A6
C7
B6
A5
D7
C6
B5
A4
C5
B4
A3
D5
C4
B3
B2
A2
C3
A1
D4
D8
D13
D17
H4
H17
N4
N17
U4
PT6D
PT6C
PT6B
PT6A
PT5D
PT5C
PT5B
PT5A
PT4D
PT4C
PT4B
PT4A
PT3D
PT3C
PT3B
PT3A
PT2D
PT2C
PT2B
PT2A
—
PT1D
PT1C
PT1B
—
—
—
PT1A
RD_DATA/TDO
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
PT7D
PT7C
PT7B
PT7A
PT6D
PT6C
PT6B
PT6A
PT5D
PT5C
PT5B
PT5A
PT4D
PT4C
PT4B
PT4A
PT3D
PT3C
PT3B
PT3A
PT2D
PT2C
PT2B
PT2A
PT1D
PT1C
PT1B
PT1A
RD_DATA/TDO
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
PT8D
PT8C
PT8B
PT8A
PT7D
PT7C
PT7B
PT7A
PT6D
PT6C
PT6B
PT6A
PT5D
PT5A
PT4D
PT4A
PT3D
PT3C
PT3B
PT3A
PT2D
PT2C
PT2B
PT2A
PT1D
PT1C
PT1B
PT1A
RD_DATA/TDO
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
PT9D
PT9C
PT9B
PT9A
PT8D
PT8C
PT8B
PT8A
PT7D
PT7C
PT7B
PT7A
PT6D
PT6A
PT5C
PT5A
PT4D
PT4A
PT3D
PT3A
PT2D
PT2C
PT2B
PT2A
PT1D
PT1C
PT1B
PT1A
RD_DATA/TDO
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
PT10D
PT10C
PT10B
PT10A
PT9D
PT9C
PT9B
PT9A
PT8D
PT8C
PT8B
PT8A
PT7D
PT7A
PT6C
PT6A
PT5D
PT5A
PT4D
PT4A
PT3D
PT3A
PT2D
PT2A
PT1D
PT1C
PT1B
PT1A
RD_DATA/TDO
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
I/O
I/O
I/O-VDD5
I/O-D2
I/O-D1
I/O
I/O
I/O-D0/DIN
I/O
I/O
I/O
I/O-DOUT
I/O
I/O
I/O
I/O-TDI
I/O
I/O-VDD5
I/O
I/O-TMS
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O-TCK
RD_DATA/TDO
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
SE
L
D E
IS C
C T
O D
N E
TI VI
N C
U E
ED S
Pin
Notes:
The W3 pin on the 256-pin PBGA package is unconnected for all devices listed in this table.
The OR2C/2T08A do not have bond pads connected to the 256-pin PBGA package pins F2 and Y17.
The pins labeled I/O-VDD5 are user I/Os for the OR2CxxA and OR2TxxB series, but they are connected to VDD5 for the OR2TxxA series.
The pins labeled VSS-ETC are the 4 x 4 array of thermal balls located at the center of the package. The balls can be attached to the ground
plane of the board for enhanced thermal capability (see Table 29), or they can be left unconnected.
Lattice Semiconductor
99
Data Sheet
November 2006
ORCA Series 2 FPGAs
Pin Information (continued)
Table 25. OR2C06A, OR2T08A, OR2C/2T10A, OR2C12A, and OR2C/2T15A/B
256-Pin PBGA Pinout (continued)
2C06A Pad
2T08A Pad
2C/2T10A Pad
2C12A Pad
2C/2T15A/B Pad
Function
U8
U13
U17
B1
D6
D11
D15
F4
F17
K4
L17
R4
R17
U6
U10
U15
W3
J10
J11
J12
J9
K10
K11
K12
K9
L10
L11
L12
L9
M10
M11
M12
M9
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
—
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
—
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
—
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
—
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
—
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
No Connect
VSS—ETC
VSS—ETC
VSS—ETC
VSS—ETC
VSS—ETC
VSS—ETC
VSS—ETC
VSS—ETC
VSS—ETC
VSS—ETC
VSS—ETC
VSS—ETC
VSS—ETC
VSS—ETC
VSS—ETC
VSS—ETC
SE
L
D E
IS C
C T
O D
N E
TI VI
N C
U E
ED S
Pin
Notes:
The W3 pin on the 256-pin PBGA package is unconnected for all devices listed in this table.
The OR2C/2T08A do not have bond pads connected to the 256-pin PBGA package pins F2 and Y17.
The pins labeled I/O-VDD5 are user I/Os for the OR2CxxA and OR2TxxB series, but they are connected to VDD5 for the OR2TxxA series.
The pins labeled VSS-ETC are the 4 x 4 array of thermal balls located at the center of the package. The balls can be attached to the ground
plane of the board for enhanced thermal capability (see Table 29), or they can be left unconnected.
100
Lattice Semiconductor
Data Sheet
November 2006
ORCA Series 2 FPGAs
Pin Information (continued)
Table 26. OR2C12A, OR2C15A, OR2C26A, and OR2C40A 304-Pin SQFP/SQFP2 Pinout
2C12A Pad
VSS
VDD
VSS
PL1D
PL1C
PL1B
PL1A
PL2D
PL2C
PL2B
PL2A
VSS
PL3D
PL3A
PL4D
PL4A
PL5D
PL5C
PL5B
PL5A
PL6D
PL6C
PL6B
PL6A
VDD
PL7D
PL7C
PL7B
PL7A
PL8D
PL8C
PL8B
PL8A
VSS
PL9D
PL9C
PL9B
PL9A
VDD
PL10D
PL10C
PL10B
PL10A
VSS
2C15A Pad
VSS
VDD
VSS
PL1D
PL1C
PL1B
PL1A
PL2D
PL2A
PL3D
PL3A
VSS
PL4D
PL4A
PL5D
PL5A
PL6D
PL6C
PL6B
PL6A
PL7D
PL7C
PL7B
PL7A
VDD
PL8D
PL8C
PL8B
PL8A
PL9D
PL9C
PL9B
PL9A
VSS
PL10D
PL10C
PL10B
PL10A
VDD
PL11D
PL11C
PL11B
PL11A
VSS
2C26A Pad
VSS
VDD
VSS
PL1D
PL1C
PL1B
PL1A
PL2D
PL2A
PL3D
PL3A
VSS
PL4D
PL4A
PL5D
PL5A
PL6D
PL6C
PL6B
PL6A
PL7D
PL7C
PL7B
PL7A
VDD
PL8D
PL8A
PL9D
PL9A
PL10D
PL10A
PL11D
PL11A
VSS
PL12D
PL12C
PL12B
PL12A
VDD
PL13D
PL13C
PL13B
PL13A
VSS
2C40A Pad
VSS
VDD
VSS
PL1D
PL1A
PL2D
PL2A
PL3D
PL3A
PL4D
PL4A
VSS
PL5D
PL6D
PL7D
PL8D
PL9D
PL9C
PL9B
PL9A
PL10D
PL10C
PL10B
PL10A
VDD
PL11D
PL11A
PL12D
PL12A
PL13D
PL13A
PL14D
PL14A
VSS
PL15D
PL15C
PL15B
PL15A
VDD
PL16D
PL16C
PL16B
PL16A
VSS
Function
VSS
VDD
VSS
I/O
I/O
I/O
I/O
I/O-A0
I/O
I/O
I/O
VSS
I/O
I/O
I/O
I/O-A1
I/O
I/O
I/O
I/O-A2
I/O
I/O
I/O
I/O-A3
VDD
I/O
I/O
I/O
I/O-A4
I/O-A5
I/O
I/O
I/O-A6
VSS
I/O
I/O
I/O
I/O-A7
VDD
I/O
I/O
I/O
I/O-A8
VSS
SE
L
D E
IS C
C T
O D
N E
TI VI
N C
U E
ED S
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
Note: The OR2TxxA and OR2TxxB series are not offered in the 304-pin SQFP/SQFP2 packages.
Lattice Semiconductor
101
Data Sheet
November 2006
ORCA Series 2 FPGAs
Pin Information (continued)
Table 26. OR2C12A, OR2C15A, OR2C26A, and OR2C40A 304-Pin SQFP/SQFP2 Pinout (continued)
2C12A Pad
PL11D
PL11C
PL11B
PL11A
PL12D
PL12C
PL12B
PL12A
VDD
PL13D
PL13B
PL13A
PL14D
PL14B
PL14A
PL15D
PL15B
PL15A
PL16D
PL16A
VSS
PL17D
PL17C
PL17B
PL17A
PL18D
PL18C
PL18B
PL18A
VSS
CCLK
VDD
VSS
VDD
VSS
PB1A
PB1B
PB1C
PB1D
PB2A
PB2B
PB2C
PB2D
VSS
PB3A
2C15A Pad
PL12D
PL12C
PL12B
PL12A
PL13D
PL13C
PL13B
PL13A
VDD
PL14D
PL14B
PL14A
PL15D
PL15B
PL15A
PL16D
PL16B
PL16A
PL17D
PL17A
VSS
PL18D
PL18C
PL18A
PL19D
PL19C
PL19A
PL20D
PL20A
VSS
CCLK
VDD
VSS
VDD
VSS
PB1A
PB1C
PB1D
PB2A
PB2D
PB3A
PB3C
PB3D
VSS
PB4A
2C26A Pad
PL14D
PL14A
PL15D
PL15A
PL16D
PL16A
PL17D
PL17A
VDD
PL18D
PL18B
PL18A
PL19D
PL19B
PL19A
PL20D
PL20B
PL20A
PL21D
PL21A
VSS
PL22D
PL22C
PL22A
PL23D
PL23C
PL23A
PL24D
PL24A
VSS
CCLK
VDD
VSS
VDD
VSS
PB1A
PB1C
PB1D
PB2A
PB2D
PB3A
PB3C
PB3D
VSS
PB4A
2C40A Pad
PL17D
PL17A
PL18D
PL18A
PL19D
PL19A
PL20D
PL20A
VDD
PL21D
PL21B
PL21A
PL22D
PL22B
PL22A
PL23D
PL24D
PL25D
PL25A
PL26A
VSS
PL27D
PL27C
PL27A
PL28D
PL28C
PL28A
PL29A
PL30A
VSS
CCLK
VDD
VSS
VDD
VSS
PB1A
PB2A
PB2D
PB3A
PB3D
PB4A
PB4C
PB4D
VSS
PB5A
Function
I/O-A9
I/O
I/O
I/O-A10
I/O
I/O
I/O
I/O-A11
VDD
I/O-A12
I/O
I/O
I/O
I/O-A13
I/O
I/O
I/O
I/O
I/O-A14
I/O
VSS
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O-A15
VSS
CCLK
VDD
VSS
VDD
VSS
I/O-A16
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VSS
I/O
SE
L
D E
IS C
C T
O D
N E
TI VI
N C
U E
ED S
Pin
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
Note: The OR2TxxA and OR2TxxB series are not offered in the 304-pin SQFP/SQFP2 packages.
102
Lattice Semiconductor
Data Sheet
November 2006
ORCA Series 2 FPGAs
Pin Information (continued)
Table 26. OR2C12A, OR2C15A, OR2C26A, and OR2C40A 304-Pin SQFP/SQFP2 Pinout (continued)
2C12A Pad
PB3D
PB4A
PB4D
PB5A
PB5B
PB5C
PB5D
PB6A
PB6B
PB6C
PB6D
VDD
PB7A
PB7B
PB7C
PB7D
PB8A
PB8B
PB8C
PB8D
VSS
PB9A
PB9B
PB9C
PB9D
VSS
PB10A
PB10B
PB10C
PB10D
VSS
PB11A
PB11B
PB11C
PB11D
PB12A
PB12B
PB12C
PB12D
VDD
PB13A
PB13B
PB13C
PB13D
PB14A
2C15A Pad
PB4D
PB5A
PB5D
PB6A
PB6B
PB6C
PB6D
PB7A
PB7B
PB7C
PB7D
VDD
PB8A
PB8B
PB8C
PB8D
PB9A
PB9B
PB9C
PB9D
VSS
PB10A
PB10B
PB10C
PB10D
VSS
PB11A
PB11B
PB11C
PB11D
VSS
PB12A
PB12B
PB12C
PB12D
PB13A
PB13B
PB13C
PB13D
VDD
PB14A
PB14B
PB14C
PB14D
PB15A
2C26A Pad
PB4D
PB5A
PB5D
PB6A
PB6B
PB6C
PB6D
PB7A
PB7B
PB7C
PB7D
VDD
PB8A
PB8D
PB9A
PB9D
PB10A
PB10D
PB11A
PB11D
VSS
PB12A
PB12B
PB12C
PB12D
VSS
PB13A
PB13B
PB13C
PB13D
VSS
PB14A
PB14D
PB15A
PB15D
PB16A
PB16D
PB17A
PB17D
VDD
PB18A
PB18B
PB18C
PB18D
PB19A
2C40A Pad
PB5D
PB6A
PB6D
PB7A
PB7D
PB8A
PB8D
PB9A
PB9D
PB10A
PB10D
VDD
PB11A
PB11D
PB12A
PB12D
PB13A
PB13D
PB14A
PB14D
VSS
PB15A
PB15B
PB15C
PB15D
VSS
PB16A
PB16B
PB16C
PB16D
VSS
PB17A
PB17D
PB18A
PB18D
PB19A
PB19D
PB20A
PB20D
VDD
PB21A
PB21D
PB22A
PB22D
PB23A
Function
I/O-A17
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VDD
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VSS
I/O
I/O
I/O
I/O
VSS
I/O
I/O
I/O
I/O
VSS
I/O
I/O
I/O
I/O
I/O-HDC
I/O
I/O
I/O
VDD
I/O-LDC
I/O
I/O
I/O
I/O
SE
L
D E
IS C
C T
O D
N E
TI VI
N C
U E
ED S
Pin
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
Note: The OR2TxxA and OR2TxxB series are not offered in the 304-pin SQFP/SQFP2 packages.
Lattice Semiconductor
103
Data Sheet
November 2006
ORCA Series 2 FPGAs
Pin Information (continued)
Table 26. OR2C12A, OR2C15A, OR2C26A, and OR2C40A 304-Pin SQFP/SQFP2 Pinout (continued)
2C12A Pad
PB14B
PB14D
PB15A
PB15D
PB16A
PB16D
VSS
PB17A
PB17B
PB17C
PB17D
PB18A
PB18B
PB18C
PB18D
VSS
DONE
VDD
VSS
2C15A Pad
PB15B
PB15D
PB16A
PB16D
PB17A
PB17D
VSS
PB18A
PB18B
PB18D
PB19A
PB19D
PB20A
PB20B
PB20D
VSS
DONE
VDD
VSS
2C26A Pad
PB19B
PB19D
PB20A
PB20D
PB21A
PB21D
VSS
PB22A
PB22B
PB22D
PB23A
PB23D
PB24A
PB24B
PB24D
VSS
DONE
VDD
VSS
2C40A Pad
PB24A
PB24D
PB25A
PB25D
PB26A
PB26D
VSS
PB27A
PB27B
PB27D
PB28A
PB28D
PB29A
PB29D
PB30D
VSS
DONE
VDD
VSS
Function
I/O
I/O
I/O-INIT
I/O
I/O
I/O
VSS
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VSS
DONE
VDD
VSS
RESET
PRGM
RESET
PRGM
RESET
PRGM
RESET
PRGM
RESET
PRGM
PR18A
PR18B
PR18C
PR18D
PR17A
PR17B
PR17C
PR17D
VSS
PR16A
PR16D
PR15A
PR15C
PR15D
PR14A
PR14C
PR14D
PR13A
PR13C
PR13D
VDD
PR12A
PR12B
PR12C
PR20A
PR20C
PR20D
PR19A
PR19D
PR18A
PR18B
PR18D
VSS
PR17A
PR17D
PR16A
PR16C
PR16D
PR15A
PR15C
PR15D
PR14A
PR14C
PR14D
VDD
PR13A
PR13B
PR13C
PR24A
PR24C
PR24D
PR23A
PR23D
PR22A
PR22B
PR22D
VSS
PR21A
PR21D
PR20A
PR20C
PR20D
PR19A
PR19C
PR19D
PR18A
PR18C
PR18D
VDD
PR17A
PR17D
PR16A
PR30A
PR29A
PR29D
PR28A
PR28D
PR27A
PR27B
PR27D
VSS
PR26A
PR25A
PR24A
PR24D
PR23D
PR22A
PR22C
PR22D
PR21A
PR21C
PR21D
VDD
PR20A
PR20D
PR19A
I/O-M0
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VSS
I/O
I/O
I/O
I/O
I/O-M1
I/O
I/O
I/O
I/O
I/O
I/O
VDD
I/O-M2
I/O
I/O
SE
L
D E
IS C
C T
O D
N E
TI VI
N C
U E
ED S
Pin
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
Note: The OR2TxxA and OR2TxxB series are not offered in the 304-pin SQFP/SQFP2 packages.
104
Lattice Semiconductor
Data Sheet
November 2006
ORCA Series 2 FPGAs
Pin Information (continued)
Table 26. OR2C12A, OR2C15A, OR2C26A, and OR2C40A 304-Pin SQFP/SQFP2 Pinout (continued)
2C12A Pad
PR12D
PR11A
PR11B
PR11C
PR11D
VSS
PR10A
PR10B
PR10C
PR10D
VDD
PR9A
PR9B
PR9C
PR9D
VSS
PR8A
PR8B
PR8C
PR8D
PR7A
PR7B
PR7C
PR7D
VDD
PR6A
PR6B
PR6C
PR6D
PR5A
PR5B
PR5C
PR5D
PR4A
PR4B
PR4D
PR3A
VSS
PR2A
PR2B
PR2C
PR2D
PR1A
PR1B
PR1C
2C15A Pad
PR13D
PR12A
PR12B
PR12C
PR12D
VSS
PR11A
PR11B
PR11C
PR11D
VDD
PR10A
PR10B
PR10C
PR10D
VSS
PR9A
PR9B
PR9C
PR9D
PR8A
PR8B
PR8C
PR8D
VDD
PR7A
PR7B
PR7C
PR7D
PR6A
PR6B
PR6C
PR6D
PR5A
PR5B
PR5D
PR4A
VSS
PR3A
PR3B
PR2A
PR2D
PR1A
PR1B
PR1C
2C26A Pad
PR16D
PR15A
PR15D
PR14A
PR14D
VSS
PR13A
PR13B
PR13C
PR13D
VDD
PR12A
PR12B
PR12C
PR12D
VSS
PR11A
PR11D
PR10A
PR10D
PR9A
PR9D
PR8A
PR8D
VDD
PR7A
PR7B
PR7C
PR7D
PR6A
PR6B
PR6C
PR6D
PR5A
PR5B
PR5D
PR4A
VSS
PR3A
PR3B
PR2A
PR2D
PR1A
PR1B
PR1C
2C40A Pad
PR19D
PR18A
PR18D
PR17A
PR17D
VSS
PR16A
PR16B
PR16C
PR16D
VDD
PR15A
PR15B
PR15C
PR15D
VSS
PR14A
PR14D
PR13A
PR13D
PR12A
PR12D
PR11A
PR11D
VDD
PR10A
PR10B
PR10C
PR10D
PR9A
PR9B
PR9C
PR9D
PR8A
PR7A
PR6A
PR5A
VSS
PR4A
PR4B
PR3A
PR3D
PR2A
PR2D
PR1A
Function
I/O
I/O-M3
I/O
I/O
I/O
VSS
I/O
I/O
I/O
I/O
VDD
I/O
I/O
I/O
I/O
VSS
I/O
I/O
I/O
I/O
I/O-CS1
I/O
I/O
I/O
VDD
I/O-CS0
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O-RD
I/O
I/O
I/O
VSS
I/O-WR
I/O
I/O
I/O
I/O
I/O
I/O
SE
L
D E
IS C
C T
O D
N E
TI VI
N C
U E
ED S
Pin
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
Note: The OR2TxxA and OR2TxxB series are not offered in the 304-pin SQFP/SQFP2 packages.
Lattice Semiconductor
105
Data Sheet
November 2006
ORCA Series 2 FPGAs
Pin Information (continued)
Table 26. OR2C12A, OR2C15A, OR2C26A, and OR2C40A 304-Pin SQFP/SQFP2 Pinout (continued)
2C12A Pad
PR1D
VSS
2C15A Pad
PR1D
VSS
2C26A Pad
PR1D
VSS
2C40A Pad
PR1D
VSS
Function
I/O
VSS
SE
L
D E
IS C
C T
O D
N E
TI VI
N C
U E
ED S
Pin
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
RD_CFGN
RD_CFGN
RD_CFGN
RD_CFGN
RD_CFGN
VDD
VSS
VDD
VSS
PT18D
PT18C
PT18B
PT18A
PT17D
PT17C
PT17B
PT17A
VSS
PT16D
PT16C
PT16A
PT15D
PT15A
PT14D
PT14A
PT13D
PT13C
PT13B
PT13A
VDD
PT12D
PT12C
PT12B
PT12A
PT11D
PT11C
PT11B
PT11A
VSS
PT10D
PT10C
PT10B
PT10A
VSS
PT9D
PT9C
PT9B
VDD
VSS
VDD
VSS
PT20D
PT20C
PT20A
PT19D
PT19A
PT18D
PT18C
PT18A
VSS
PT17D
PT17C
PT17A
PT16D
PT16A
PT15D
PT15A
PT14D
PT14C
PT14B
PT14A
VDD
PT13D
PT13C
PT13B
PT13A
PT12D
PT12C
PT12B
PT12A
VSS
PT11D
PT11C
PT11B
PT11A
VSS
PT10D
PT10C
PT10B
VDD
VSS
VDD
VSS
PT24D
PT24C
PT24A
PT23D
PT23A
PT22D
PT22C
PT22A
VSS
PT21D
PT21C
PT21A
PT20D
PT20A
PT19D
PT19A
PT18D
PT18C
PT18B
PT18A
VDD
PT17D
PT17A
PT16D
PT16A
PT15D
PT15A
PT14D
PT14A
VSS
PT13D
PT13C
PT13B
PT13A
VSS
PT12D
PT12C
PT12B
VDD
VSS
VDD
VSS
PT30D
PT30A
PT29A
PT28D
PT28A
PT27D
PT27C
PT27A
VSS
PT26D
PT26C
PT26A
PT25D
PT25A
PT24D
PT23D
PT22D
PT22A
PT21D
PT21A
VDD
PT20D
PT20A
PT19D
PT19A
PT18D
PT18A
PT17D
PT17A
VSS
PT16D
PT16C
PT16B
PT16A
VSS
PT15D
PT15C
PT15B
VDD
VSS
VDD
VSS
I/O
I/O
I/O
I/O
I/O-RDY/RCLK
I/O
I/O
I/O
VSS
I/O
I/O
I/O
I/O-D7
I/O
I/O
I/O
I/O
I/O
I/O-D6
I/O
VDD
I/O
I/O
I/O
I/O-D5
I/O
I/O
I/O
I/O-D4
VSS
I/O
I/O
I/O
I/O-D3
VSS
I/O
I/O
I/O
Note: The OR2TxxA and OR2TxxB series are not offered in the 304-pin SQFP/SQFP2 packages.
106
Lattice Semiconductor
Data Sheet
November 2006
ORCA Series 2 FPGAs
Pin Information (continued)
Table 26. OR2C12A, OR2C15A, OR2C26A, and OR2C40A 304-Pin SQFP/SQFP2 Pinout (continued)
2C12A Pad
PT9A
VSS
PT8D
PT8C
PT8B
PT8A
PT7D
PT7C
PT7B
PT7A
VDD
PT6D
PT6C
PT6B
PT6A
PT5D
PT5C
PT5B
PT5A
PT4D
PT4A
PT3D
PT3A
VSS
PT2D
PT2C
PT2B
PT2A
PT1D
PT1C
PT1B
PT1A
VSS
2C15A Pad
PT10A
VSS
PT9D
PT9C
PT9B
PT9A
PT8D
PT8C
PT8B
PT8A
VDD
PT7D
PT7C
PT7B
PT7A
PT6D
PT6C
PT6B
PT6A
PT5D
PT5A
PT4D
PT4A
VSS
PT3D
PT3A
PT2D
PT2A
PT1D
PT1C
PT1B
PT1A
VSS
2C26A Pad
PT12A
VSS
PT11D
PT11A
PT10D
PT10A
PT9D
PT9A
PT8D
PT8A
VDD
PT7D
PT7C
PT7B
PT7A
PT6D
PT6C
PT6B
PT6A
PT5D
PT5A
PT4D
PT4A
VSS
PT3D
PT3A
PT2D
PT2A
PT1D
PT1C
PT1B
PT1A
VSS
2C40A Pad
PT15A
VSS
PT14D
PT14A
PT13D
PT13A
PT12D
PT12A
PT11D
PT11A
VDD
PT10D
PT10A
PT9D
PT9A
PT8D
PT8A
PT7D
PT7A
PT6D
PT6A
PT5D
PT5A
VSS
PT4D
PT4A
PT3D
PT3A
PT2D
PT2A
PT1D
PT1A
VSS
Function
I/O-D2
VSS
I/O-D1
I/O
I/O
I/O-D0/DIN
I/O
I/O
I/O
I/O-DOUT
VDD
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O-TDI
I/O
I/O
I/O
I/O-TMS
VSS
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O-TCK
VSS
RD_DATA/TDO
RD_DATA/TDO
RD_DATA/TDO
RD_DATA/TDO
RD_DATA/TDO
VDD
VDD
VDD
VDD
VDD
SE
L
D E
IS C
C T
O D
N E
TI VI
N C
U E
ED S
Pin
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
Note: The OR2TxxA and OR2TxxB series are not offered in the 304-pin SQFP/SQFP2 packages.
Lattice Semiconductor
107
Data Sheet
November 2006
ORCA Series 2 FPGAs
Pin Information (continued)
Table 27. OR2C10A, OR2C12A, OR2C/2T15A/B, OR2T26A, and OR2T40A/B 352-Pin PBGA
Pinout
2C10A Pad
2C12A Pad
2C/2T15A/B Pad
2T26A Pad
OR2T40A/B Pad
Function
B1
C2
C1
D2
D3
D1
E2
E4
E3
E1
F2
G4
F3
F1
G2
G1
G3
H2
J4
H1
H3
J2
J1
K2
J3
K1
K4
L2
K3
L1
M2
M1
L3
N2
M4
N1
M3
P2
PL1D
PL1C
PL1B
PL1A
PL2D
PL2C
PL2B
—
PL2A
PL3D
—
PL3C
—
PL3B
—
—
PL3A
PL4D
PL4C
PL4B
PL4A
PL5D
PL5C
PL5B
PL5A
PL6D
PL6C
PL6B
PL6A
PL7D
PL7C
PL7B
PL7A
PL8D
PL8C
PL8B
PL8A
PL9D
PL1D
PL1C
PL1B
PL1A
PL2D
PL2C
PL2B
—
PL2A
PL3D
PL3C
PL3B
PL3A
PL4D
PL4C
PL4B
PL4A
PL5D
PL5C
PL5B
PL5A
PL6D
PL6C
PL6B
PL6A
PL7D
PL7C
PL7B
PL7A
PL8D
PL8C
PL8B
PL8A
PL9D
PL9C
PL9B
PL9A
PL10D
PL1D
PL1C
PL1B
PL1A
PL2D
PL2A
PL3D
PL3B
PL3A
PL4D
PL4C
PL4B
PL4A
PL5D
PL5C
PL5B
PL5A
PL6D
PL6C
PL6B
PL6A
PL7D
PL7C
PL7B
PL7A
PL8D
PL8C
PL8B
PL8A
PL9D
PL9C
PL9B
PL9A
PL10D
PL10C
PL10B
PL10A
PL11D
PL1D
PL1C
PL1B
PL1A
PL2D
PL2A
PL3D
PL3B
PL3A
PL4D
PL4C
PL4B
PL4A
PL5D
PL5C
PL5B
PL5A
PL6D
PL6C
PL6B
PL6A
PL7D
PL7C
PL7B
PL7A
PL8D
PL8A
PL9D
PL9A
PL10D
PL10A
PL11D
PL11A
PL12D
PL12C
PL12B
PL12A
PL13D
PL1D
PL1A
PL2D
PL2A
PL3D
PL3A
PL4D
PL4B
PL4A
VDD5
PL5C
PL5B
PL6D
PL7D
PL7C
PL7B
PL8D
PL9D
PL9C
PL9B
PL9A
PL10D
PL10C
PL10B
PL10A
PL11D
PL11A
PL12D
PL12A
PL13D
PL13A
PL14D
PL14A
PL15D
PL15C
PL15B
PL15A
PL16D
I/O
I/O
I/O
I/O
I/O-A0
I/O
I/O
I/O
I/O
I/O-VDD5
I/O
I/O
I/O
I/O
I/O
I/O
I/O-A1
I/O
I/O
I/O
I/O-A2
I/O
I/O
I/O
I/O-A3
I/O
I/O
I/O
I/O-A4
I/O-A5
I/O
I/O
I/O-A6
I/O
I/O
I/O
I/O-A7
I/O
SE
L
D E
IS C
C T
O D
N E
TI VI
N C
U E
ED S
Pin
Notes:
The pins labeled I/O-VDD5 are user I/Os for the OR2CxxA and OR2TxxB series, but they are connected to VDD5 for the OR2TxxA series.
The pins labeled VSS-ETC are the 6 x 6 array of thermal balls located at the center of the package. The balls can be attached to the ground plane
of the board for enhanced thermal capability (see Table 29), or they can be left unconnected.
108
Lattice Semiconductor
Data Sheet
November 2006
ORCA Series 2 FPGAs
Pin Information (continued)
Table 27. OR2C10A, OR2C12A, OR2C/2T15A/B, OR2T26A, and OR2T40A/B 352-Pin PBGA
Pinout (continued)
2C10A Pad
2C12A Pad
2C/2T15A/B Pad
2T26A Pad
OR2T40A/B Pad
Function
P4
P1
N3
R2
P3
R1
T2
R3
T1
R4
U2
T3
U1
U4
V2
U3
V1
W2
W1
V3
Y2
W4
Y1
W3
AA2
Y4
AA1
Y3
AB2
AB1
AA3
AC2
AB4
AC1
AB3
AD2
AC3
AD1
AF2
PL9C
PL9B
PL9A
PL10D
PL10C
PL10B
PL10A
PL11D
PL11C
PL11B
PL11A
PL12D
—
PL12C
—
PL12B
PL12A
PL13D
PL13C
PL13B
PL13A
PL14D
—
PL14C
PL14B
PL14A
—
PL15D
PL15C
PL15B
PL15A
PL16D
PL16C
PL16B
—
—
PL16A
CCLK
PB1A
PL10C
PL10B
PL10A
PL11D
PL11C
PL11B
PL11A
PL12D
PL12C
PL12B
PL12A
PL13D
PL13C
PL13B
PL13A
PL14D
PL14C
PL14B
PL14A
PL15D
PL15C
PL15B
PL15A
PL16D
PL16C
PL16B
PL16A
PL17D
PL17C
PL17B
PL17A
PL18D
PL18C
PL18B
—
—
PL18A
CCLK
PB1A
PL11C
PL11B
PL11A
PL12D
PL12C
PL12B
PL12A
PL13D
PL13C
PL13B
PL13A
PL14D
PL14C
PL14B
PL14A
PL15D
PL15C
PL15B
PL15A
PL16D
PL16C
PL16B
PL16A
PL17D
PL17C
PL17B
PL17A
PL18D
PL18C
PL18A
PL19D
PL19C
PL19A
PL20D
PL20C
PL20B
PL20A
CCLK
PB1A
PL13C
PL13B
PL13A
PL14D
PL14A
PL15D
PL15A
PL16D
PL16A
PL17D
PL17A
PL18D
PL18C
PL18B
PL18A
PL19D
PL19C
PL19B
PL19A
PL20D
PL20C
PL20B
PL20A
PL21D
PL21C
PL21B
PL21A
PL22D
PL22C
PL22A
PL23D
PL23C
PL23A
PL24D
PL24C
PL24B
PL24A
CCLK
PB1A
VDD5
PL16B
PL16A
PL17D
PL17A
PL18D
PL18A
PL19D
PL19A
PL20D
PL20A
PL21D
PL21C
PL21B
PL21A
PL22D
PL22C
PL22B
PL22A
PL23D
PL23C
PL24D
PL25D
PL25A
PL26C
PL26B
PL26A
VDD5
PL27C
PL27A
PL28D
PL28C
PL28A
PL29A
PL30C
PL30B
PL30A
PCCLK
PB1A
I/O-VDD5
I/O
I/O-A8
I/O-A9
I/O
I/O
I/O-A10
I/O
I/O
I/O
I/O-A11
I/O-A12
I/O
I/O
I/O
I/O
I/O
I/O-A13
I/O
I/O
I/O
I/O
I/O
I/O-A14
I/O
I/O
I/O
I/O-VDD5
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O-A15
CCLK
I/O-A16
SE
L
D E
IS C
C T
O D
N E
TI VI
N C
U E
ED S
Pin
Notes:
The pins labeled I/O-VDD5 are user I/Os for the OR2CxxA and OR2TxxB series, but they are connected to VDD5 for the OR2TxxA series.
The pins labeled VSS-ETC are the 6 x 6 array of thermal balls located at the center of the package. The balls can be attached to the ground plane
of the board for enhanced thermal capability (see Table 29), or they can be left unconnected.
Lattice Semiconductor
109
Data Sheet
November 2006
ORCA Series 2 FPGAs
Pin Information (continued)
Table 27. OR2C10A, OR2C12A, OR2C/2T15A/B, OR2T26A, and OR2T40A/B 352-Pin PBGA
Pinout (continued)
2C10A Pad
2C12A Pad
2C/2T15A/B Pad
2T26A Pad
OR2T40A/B Pad
Function
AE3
AF3
AE4
AD4
AF4
AE5
AC5
AD5
AF5
AE6
AC7
AD6
AF6
AE7
AF7
AD7
AE8
AC9
AF8
AD8
AE9
AF9
AE10
AD9
AF10
AC10
AE11
AD10
AF11
AE12
AF12
AD11
AE13
AC12
AF13
AD12
AE14
AC14
AF14
—
PB1B
PB1C
PB1D
PB2A
—
PB2B
—
PB2C
PB2D
PB3A
PB3B
—
PB3C
—
PB3D
PB4A
PB4B
PB4C
PB4D
PB5A
PB5B
PB5C
PB5D
PB6A
PB6B
PB6C
PB6D
PB7A
PB7B
PB7C
PB7D
PB8A
PB8B
PB8C
PB8D
PB9A
PB9B
PB9C
—
PB1B
PB1C
PB1D
PB2A
PB2B
PB2C
PB2D
PB3A
PB3B
PB3C
PB3D
PB4A
PB4B
PB4C
PB4D
PB5A
PB5B
PB5C
PB5D
PB6A
PB6B
PB6C
PB6D
PB7A
PB7B
PB7C
PB7D
PB8A
PB8B
PB8C
PB8D
PB9A
PB9B
PB9C
PB9D
PB10A
PB10B
PB10C
PB1B
PB1C
PB1D
PB2A
PB2D
PB3A
PB3C
PB3D
PB4A
PB4B
PB4C
PB4D
PB5A
PB5B
PB5C
PB5D
PB6A
PB6B
PB6C
PB6D
PB7A
PB7B
PB7C
PB7D
PB8A
PB8B
PB8C
PB8D
PB9A
PB9B
PB9C
PB9D
PB10A
PB10B
PB10C
PB10D
PB11A
PB11B
PB11C
PB1B
PB1C
PB1D
PB2A
PB2D
PB3A
PB3C
PB3D
PB4A
PB4B
PB4C
PB4D
PB5A
PB5B
PB5C
PB5D
PB6A
PB6B
PB6C
PB6D
PB7A
PB7B
PB7C
PB7D
PB8A
PB8D
PB9A
PB9D
PB10A
PB10D
PB11A
PB11D
PB12A
PB12B
PB12C
PB12D
PB13A
PB13B
PB13C
PB1B
PB2A
PB2D
PB3A
VDD5
PB4A
PB4C
PB4D
PB5A
PB5B
PB5C
PB5D
PB6A
PB6B
PB6C
PB6D
PB7A
PB7D
PB8A
PB8D
PB9A
PB9D
PB10A
PB10D
PB11A
PB11D
PB12A
PB12D
PB13A
PB13D
PB14A
PB14D
PB15A
PB15B
PB15C
PB15D
PB16A
PB16B
PB16C
I/O
I/O
I/O
I/O
I/O-VDD5
I/O
I/O
I/O
I/O
I/O
I/O
I/O-A17
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
SE
L
D E
IS C
C T
O D
N E
TI VI
N C
U E
ED S
Pin
Notes:
The pins labeled I/O-VDD5 are user I/Os for the OR2CxxA and OR2TxxB series, but they are connected to VDD5 for the OR2TxxA series.
The pins labeled VSS-ETC are the 6 x 6 array of thermal balls located at the center of the package. The balls can be attached to the ground plane
of the board for enhanced thermal capability (see Table 29), or they can be left unconnected.
110
Lattice Semiconductor
Data Sheet
November 2006
ORCA Series 2 FPGAs
Pin Information (continued)
Table 27. OR2C10A, OR2C12A, OR2C/2T15A/B, OR2T26A, and OR2T40A/B 352-Pin PBGA
Pinout (continued)
2C10A Pad
2C12A Pad
2C/2T15A/B Pad
2T26A Pad
OR2T40A/B Pad
Function
AD13
AE15
AD14
AF15
AE16
AD15
AF16
AC15
AE17
AD16
AF17
AC17
AE18
AD17
AF18
AE19
AF19
AD18
AE20
AC19
AF20
AD19
AE21
AC20
AF21
AD20
AE22
AF22
AD21
AE23
AC22
AF23
AD22
AE24
AD23
AF24
AE26
AD25
AD26
PB9D
PB10A
PB10B
PB10C
PB10D
PB11A
PB11B
PB11C
PB11D
PB12A
PB12B
PB12C
PB12D
PB13A
PB13B
—
PB13C
PB13D
—
PB14A
—
PB14B
PB14C
PB14D
PB15A
PB15B
PB15C
PB15D
PB16A
—
PB16B
PB16C
PB16D
—
—
DONE
PB10D
PB11A
PB11B
PB11C
PB11D
PB12A
PB12B
PB12C
PB12D
PB13A
PB13B
PB13C
PB13D
PB14A
PB14B
PB14C
PB14D
PB15A
PB15B
PB15C
PB15D
PB16A
PB16B
PB16C
PB16D
PB17A
PB17B
PB17C
PB17D
—
PB18A
PB18B
PB18C
—
PB18D
DONE
PB11D
PB12A
PB12B
PB12C
PB12D
PB13A
PB13B
PB13C
PB13D
PB14A
PB14B
PB14C
PB14D
PB15A
PB15B
PB15C
PB15D
PB16A
PB16B
PB16C
PB16D
PB17A
PB17B
PB17C
PB17D
PB18A
PB18B
PB18D
PB19A
PB19C
PB19D
PB20A
PB20B
PB20C
PB20D
DONE
PB13D
PB14A
PB14D
PB15A
PB15D
PB16A
PB16D
PB17A
PB17D
PB18A
PB18B
PB18C
PB18D
PB19A
PB19B
PB19C
PB19D
PB20A
PB20B
PB20C
PB20D
PB21A
PB21B
PB21C
PB21D
PB22A
PB22B
PB22D
PB23A
PB23B
PB23D
PB24A
PB24B
PB24C
PB24D
DONE
I/O
I/O-VDD5
I/O
I/O
I/O
I/O-HDC
I/O
I/O
I/O
I/O-LDC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O-INIT
I/O
I/O
I/O
I/O-VDD5
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
DONE
RESET
RESET
RESET
RESET
PRGM
PRGM
PR18A
PRGM
PRGM
PR24A
PB16D
VDD5
PB17D
PB18A
PB18D
PB19A
PB19D
PB20A
PB20D
PB21A
PB21D
PB22A
PB22D
PB23A
PB24A
PB24C
PB24D
PB25A
PB25B
PB25C
PB25D
VDD5
PB26B
PB26C
PB26D
PB27A
PB27B
PB27D
PB28A
PB28B
PB28D
PB29A
PB29D
PB30C
PB30D
PDONE
PRESETN
PPRGMN
PR30A
SE
L
D E
IS C
C T
O D
N E
TI VI
N C
U E
ED S
Pin
PR16A
PR20A
RESET
PRGM
I/O-M0
Notes:
The pins labeled I/O-VDD5 are user I/Os for the OR2CxxA and OR2TxxB series, but they are connected to VDD5 for the OR2TxxA series.
The pins labeled VSS-ETC are the 6 x 6 array of thermal balls located at the center of the package. The balls can be attached to the ground plane
of the board for enhanced thermal capability (see Table 29), or they can be left unconnected.
Lattice Semiconductor
111
Data Sheet
November 2006
ORCA Series 2 FPGAs
Pin Information (continued)
Table 27. OR2C10A, OR2C12A, OR2C/2T15A/B, OR2T26A, and OR2T40A/B 352-Pin PBGA
Pinout (continued)
2C10A Pad
2C12A Pad
2C/2T15A/B Pad
2T26A Pad
OR2T40A/B Pad
Function
AC25
AC24
AC26
AB25
AB23
AB24
AB26
AA25
Y23
AA24
AA26
Y25
Y26
Y24
W25
V23
W26
W24
V25
V26
U25
V24
U26
U23
T25
U24
T26
R25
R26
T24
P25
R23
P26
R24
N25
N23
N26
P24
M25
PR16B
PR16C
PR16D
PR15A
PR15B
PR15C
PR15D
PR14A
PR14B
PR14C
—
PR14D
—
PR13A
PR13B
PR13C
—
PR13D
PR12A
PR12B
—
PR12C
PR12D
PR11A
PR11B
PR11C
PR11D
PR10A
PR10B
PR10C
PR10D
PR9A
PR9B
PR9C
PR9D
PR8A
PR8B
PR8C
PR8D
PR18B
PR18C
PR18D
PR17A
PR17B
PR17C
PR17D
PR16A
PR16B
PR16C
PR16D
PR15A
PR15B
PR15C
PR15D
PR14A
PR14B
PR14C
PR14D
PR13A
PR13B
PR13C
PR13D
PR12A
PR12B
PR12C
PR12D
PR11A
PR11B
PR11C
PR11D
PR10A
PR10B
PR10C
PR10D
PR9A
PR9B
PR9C
PR9D
PR20C
PR20D
PR19A
PR19D
PR18A
PR18B
PR18D
PR17A
PR17B
PR17C
PR17D
PR16A
PR16B
PR16C
PR16D
PR15A
PR15B
PR15C
PR15D
PR14A
PR14B
PR14C
PR14D
PR13A
PR13B
PR13C
PR13D
PR12A
PR12B
PR12C
PR12D
PR11A
PR11B
PR11C
PR11D
PR10A
PR10B
PR10C
PR10D
PR24C
PR24D
PR23A
PR23D
PR22A
PR22B
PR22D
PR21A
PR21B
PR21C
PR21D
PR20A
PR20B
PR20C
PR20D
PR19A
PR19B
PR19C
PR19D
PR18A
PR18B
PR18C
PR18D
PR17A
PR17D
PR16A
PR16D
PR15A
PR15D
PR14A
PR14D
PR13A
PR13B
PR13C
PR13D
PR12A
PR12B
PR12C
PR12D
PR29A
PR29D
PR28A
PR28D
PR27A
PR27B
PR27D
PR26A
PR26B
PR26C
PR25A
PR24A
PR24B
PR24D
PR23D
PR22A
PR22B
PR22C
VDD5
PR21A
PR21B
PR21C
PR21D
PR20A
PR20D
PR19A
PR19D
PR18A
PR18D
PR17A
PR17D
PR16A
PR16B
PR16C
PR16D
PR15A
PR15B
PR15C
PR15D
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O-M1
I/O
I/O
I/O
I/O-VDD5
I/O
I/O
I/O
I/O
I/O-M2
I/O
I/O
I/O
I/O-M3
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
SE
L
D E
IS C
C T
O D
N E
TI VI
N C
U E
ED S
Pin
Notes:
The pins labeled I/O-VDD5 are user I/Os for the OR2CxxA and OR2TxxB series, but they are connected to VDD5 for the OR2TxxA series.
The pins labeled VSS-ETC are the 6 x 6 array of thermal balls located at the center of the package. The balls can be attached to the ground plane
of the board for enhanced thermal capability (see Table 29), or they can be left unconnected.
112
Lattice Semiconductor
Data Sheet
November 2006
ORCA Series 2 FPGAs
Pin Information (continued)
Table 27. OR2C10A, OR2C12A, OR2C/2T15A/B, OR2T26A, and OR2T40A/B 352-Pin PBGA
Pinout (continued)
2C10A Pad
2C12A Pad
2C/2T15A/B Pad
2T26A Pad
OR2T40A/B Pad
Function
N24
M26
L25
M24
L26
M23
K25
L24
K26
K23
J25
K24
J26
H25
H26
J24
G25
H23
G26
H24
F25
G23
F26
G24
E25
E26
F24
D25
E23
D26
E24
C25
D24
C26
A25
B24
A24
B23
C23
PR7A
PR7B
PR7C
PR7D
PR6A
PR6B
PR6C
PR6D
PR5A
PR5B
PR5C
PR5D
PR4A
PR4B
PR4C
PR4D
PR3A
PR3B
—
PR3C
PR3D
—
—
—
PR2A
PR2B
—
PR2C
PR2D
PR1A
PR1B
PR1C
PR1D
PR8A
PR8B
PR8C
PR8D
PR7A
PR7B
PR7C
PR7D
PR6A
PR6B
PR6C
PR6D
PR5A
PR5B
PR5C
PR5D
PR4A
PR4B
PR4C
PR4D
PR3A
PR3B
PR3C
PR3D
PR2A
PR2B
—
PR2C
PR2D
PR1A
PR1B
PR1C
PR1D
PR9A
PR9B
PR9C
PR9D
PR8A
PR8B
PR8C
PR8D
PR7A
PR7B
PR7C
PR7D
PR6A
PR6B
PR6C
PR6D
PR5A
PR5B
PR5C
PR5D
PR4A
PR4B
PR4C
PR4D
PR3A
PR3B
PR3D
PR2A
PR2D
PR1A
PR1B
PR1C
PR1D
PR11A
PR11D
PR10A
PR10D
PR9A
PR9D
PR8A
PR8D
PR7A
PR7B
PR7C
PR7D
PR6A
PR6B
PR6C
PR6D
PR5A
PR5B
PR5C
PR5D
PR4A
PR4B
PR4C
PR4D
PR3A
PR3B
PR3D
PR2A
PR2D
PR1A
PR1B
PR1C
PR1D
VDD5
PR14D
PR13A
PR13D
PR12A
PR12D
PR11A
PR11D
PR10A
PR10B
PR10C
PR10D
PR9A
PR9B
PR9C
PR9D
PR8A
PR7A
PR7C
PR6A
VDD5
PR5B
PR5C
PR5D
PR4A
PR4B
PR4D
PR3A
PR3D
PR2A
PR2D
PR1A
PR1D
I/O-VDD5
I/O
I/O
I/O
I/O-CS1
I/O
I/O
I/O
I/O-CS0
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O-RD
I/O
I/O
I/O
I/O-VDD5
I/O
I/O
I/O
I/O-WR
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
RD_CFGN
RD_CFGN
RD_CFGN
RD_CFGN
RD_CFGN
RD_CFGN
PT16D
PT16C
—
PT16B
PT16A
PT18D
PT18C
—
PT18B
PT18A
PT20D
PT20C
PT20B
PT20A
PT19D
PT24D
PT24C
PT24B
PT24A
PT23D
PT30D
PT30A
PT29B
PT29A
PT28D
I/O
I/O
I/O
I/O
I/O
SE
L
D E
IS C
C T
O D
N E
TI VI
N C
U E
ED S
Pin
Notes:
The pins labeled I/O-VDD5 are user I/Os for the OR2CxxA and OR2TxxB series, but they are connected to VDD5 for the OR2TxxA series.
The pins labeled VSS-ETC are the 6 x 6 array of thermal balls located at the center of the package. The balls can be attached to the ground plane
of the board for enhanced thermal capability (see Table 29), or they can be left unconnected.
Lattice Semiconductor
113
Data Sheet
November 2006
ORCA Series 2 FPGAs
Pin Information (continued)
Table 27. OR2C10A, OR2C12A, OR2C/2T15A/B, OR2T26A, and OR2T40A/B 352-Pin PBGA
Pinout (continued)
2C10A Pad
2C12A Pad
2C/2T15A/B Pad
2T26A Pad
OR2T40A/B Pad
Function
A23
PT15D
PT17D
PT19A
PT23A
PT28A
I/O-RDY/
RCLK
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O-D7
I/O
I/O
I/O
I/O-VDD5
I/O
I/O
I/O
I/O
I/O
I/O-D6
I/O
I/O
I/O
I/O
I/O-D5
I/O
I/O
I/O
I/O-D4
I/O
I/O
I/O
I/O-D3
I/O
I/O
I/O-VDD5
I/O-D2
I/O-D1
I/O
SE
L
D E
IS C
C T
O D
N E
TI VI
N C
U E
ED S
Pin
B22
D22
C22
A22
B21
D20
C21
A21
B20
A20
C20
B19
D18
A19
C19
B18
A18
B17
C18
A17
D17
B16
C17
A16
B15
A15
C16
B14
D15
A14
C15
B13
D13
A13
C14
B12
C13
PT15C
PT15B
PT15A
PT14D
PT14C
PT14B
PT14A
PT13D
—
PT13C
—
PT13B
—
PT13A
—
PT12D
PT12C
PT12B
PT12A
PT11D
PT11C
PT11B
PT11A
PT10D
PT10C
PT10B
PT10A
PT9D
PT9C
PT9B
PT9A
PT8D
PT8C
PT8B
PT8A
PT7D
PT7C
PT17C
PT17B
PT17A
PT16D
PT16C
PT16B
PT16A
PT15D
PT15C
PT15B
PT15A
PT14D
PT14C
PT14B
PT14A
PT13D
PT13C
PT13B
PT13A
PT12D
PT12C
PT12B
PT12A
PT11D
PT11C
PT11B
PT11A
PT10D
PT10C
PT10B
PT10A
PT9D
PT9C
PT9B
PT9A
PT8D
PT8C
PT18D
PT18C
PT18A
PT17D
PT17C
PT17B
PT17A
PT16D
PT16C
PT16B
PT16A
PT15D
PT15C
PT15B
PT15A
PT14D
PT14C
PT14B
PT14A
PT13D
PT13C
PT13B
PT13A
PT12D
PT12C
PT12B
PT12A
PT11D
PT11C
PT11B
PT11A
PT10D
PT10C
PT10B
PT10A
PT9D
PT9C
PT22D
PT22C
PT22A
PT21D
PT21C
PT21B
PT21A
PT20D
PT20C
PT20B
PT20A
PT19D
PT19C
PT19B
PT19A
PT18D
PT18C
PT18B
PT18A
PT17D
PT17A
PT16D
PT16A
PT15D
PT15A
PT14D
PT14A
PT13D
PT13C
PT13B
PT13A
PT12D
PT12C
PT12B
PT12A
PT11D
PT11A
PT27D
PT27C
PT27A
PT26D
PT26C
PT26B
PT26A
PT25D
PT25C
PT25B
PT25A
VDD5
PT24C
PT24B
PT23D
PT22D
PT22A
PT21D
PT21A
PT20D
PT20A
PT19D
PT19A
PT18D
PT18A
PT17D
PT17A
PT16D
PT16C
PT16B
PT16A
PT15D
PT15C
VDD5
PT15A
PT14D
PT14A
Notes:
The pins labeled I/O-VDD5 are user I/Os for the OR2CxxA and OR2TxxB series, but they are connected to VDD5 for the OR2TxxA series.
The pins labeled VSS-ETC are the 6 x 6 array of thermal balls located at the center of the package. The balls can be attached to the ground plane
of the board for enhanced thermal capability (see Table 29), or they can be left unconnected.
114
Lattice Semiconductor
Data Sheet
November 2006
ORCA Series 2 FPGAs
Pin Information (continued)
Table 27. OR2C10A, OR2C12A, OR2C/2T15A/B, OR2T26A, and OR2T40A/B 352-Pin PBGA
Pinout (continued)
2C10A Pad
2C12A Pad
2C/2T15A/B Pad
2T26A Pad
OR2T40A/B Pad
Function
A12
B11
C12
A11
D12
B10
C11
A10
D10
B9
C10
A9
B8
A8
C9
B7
D8
A7
C8
B6
D7
A6
C7
B5
A5
C6
B4
D5
A4
C5
B3
C4
A3
PT7B
PT7A
PT6D
PT6C
PT6B
PT6A
PT5D
PT5C
PT5B
PT5A
PT4D
PT4C
PT4B
PT4A
—
PT3D
—
PT3C
—
PT3B
—
PT3A
PT2D
PT2C
PT2B
—
—
PT2A
PT1D
PT1C
PT1B
PT1A
RD_DATA/TDO
PT8B
PT8A
PT7D
PT7C
PT7B
PT7A
PT6D
PT6C
PT6B
PT6A
PT5D
PT5C
PT5B
PT5A
PT4D
PT4C
PT4B
PT4A
PT3D
PT3C
PT3B
PT3A
PT2D
PT2C
PT2B
—
—
PT2A
PT1D
PT1C
PT1B
PT1A
RD_DATA/TDO
PT9B
PT9A
PT8D
PT8C
PT8B
PT8A
PT7D
PT7C
PT7B
PT7A
PT6D
PT6C
PT6B
PT6A
PT5D
PT5C
PT5B
PT5A
PT4D
PT4C
PT4B
PT4A
PT3D
PT3A
PT2D
PT2C
PT2B
PT2A
PT1D
PT1C
PT1B
PT1A
RD_DATA/TDO
PT10D
PT10A
PT9D
PT9A
PT8D
PT8A/
PT7D
PT7C
PT7B
PT7A
PT6D
PT6C
PT6B
PT6A
PT5D
PT5C
PT5B
PT5A
PT4D
PT4C
PT4B
PT4A
PT3D
PT3A
PT2D
PT2C
PT2B
PT2A
PT1D
PT1C
PT1B
PT1A
RD_DATA/TDO
PT13D
PT13A
PT12D
PT12A
PT11D
PT11A
PT10D
PT10A
PT9D
PT9A
PT8D
PT8A
PT7D
PT7A
PT6D
PT6C
PT6B
VDD5
PT5D
PT5C
PT5B
PT5A
PT4D
PT4A
PT3D
PT3C
PT3B
PT3A
PT2D
PT2A
PT1D
PT1A
RD_DATA/TDO
A1
A2
A26
AC13
AC18
AC23
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
I/O
I/O-D0/DIN
I/O
I/O
I/O
I/O-DOUT
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O-TDI
I/O
I/O
I/O
I/O-VDD5
I/O
I/O
I/O
I/O-TMS
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O-TCK
RD_DATA/
TDO
VSS
VSS
VSS
VSS
VSS
VSS
SE
L
D E
IS C
C T
O D
N E
TI VI
N C
U E
ED S
Pin
Notes:
The pins labeled I/O-VDD5 are user I/Os for the OR2CxxA and OR2TxxB series, but they are connected to VDD5 for the OR2TxxA series.
The pins labeled VSS-ETC are the 6 x 6 array of thermal balls located at the center of the package. The balls can be attached to the ground plane
of the board for enhanced thermal capability (see Table 29), or they can be left unconnected.
Lattice Semiconductor
115
Data Sheet
November 2006
ORCA Series 2 FPGAs
Pin Information (continued)
Table 27. OR2C10A, OR2C12A, OR2C/2T15A/B, OR2T26A, and OR2T40A/B 352-Pin PBGA
Pinout (continued)
2C10A Pad
2C12A Pad
2C/2T15A/B Pad
2T26A Pad
OR2T40A/B Pad
Function
AC4
AC8
AD24
AD3
AE1
AE2
AE25
AF1
AF25
AF26
B2
B25
B26
C24
C3
D14
D19
D23
D4
D9
H4
J23
N4
P23
V4
W23
AA23
AA4
AC11
AC16
AC21
AC6
D11
D16
D21
D6
F23
F4
L23
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
SE
L
D E
IS C
C T
O D
N E
TI VI
N C
U E
ED S
Pin
Notes:
The pins labeled I/O-VDD5 are user I/Os for the OR2CxxA and OR2TxxB series, but they are connected to VDD5 for the OR2TxxA series.
The pins labeled VSS-ETC are the 6 x 6 array of thermal balls located at the center of the package. The balls can be attached to the ground plane
of the board for enhanced thermal capability (see Table 29), or they can be left unconnected.
116
Lattice Semiconductor
Data Sheet
November 2006
ORCA Series 2 FPGAs
Pin Information (continued)
Table 27. OR2C10A, OR2C12A, OR2C/2T15A/B, OR2T26A, and OR2T40A/B 352-Pin PBGA
Pinout (continued)
2C10A Pad
2C12A Pad
2C/2T15A/B Pad
2T26A Pad
OR2T40A/B Pad
Function
L4
T23
T4
L11
L12
L13
L14
L15
L16
M11
M12
M13
M14
M15
M16
N11
N12
N13
N14
N15
N16
P11
P12
P13
P14
P15
P16
R11
R12
R13
R14
R15
R16
T11
T12
T13
T14
T15
T16
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VSS—ETC
VSS—ETC
VSS—ETC
VSS—ETC
VSS—ETC
VSS—ETC
VSS—ETC
VSS—ETC
VSS—ETC
VSS—ETC
VSS—ETC
VSS—ETC
VSS—ETC
VSS—ETC
VSS—ETC
VSS—ETC
VSS—ETC
VSS—ETC
VSS—ETC
VSS—ETC
VSS—ETC
VSS—ETC
VSS—ETC
VSS—ETC
VSS—ETC
VSS—ETC
VSS—ETC
VSS—ETC
VSS—ETC
VSS—ETC
VSS—ETC
VSS—ETC
VSS—ETC
VSS—ETC
VSS—ETC
VSS—ETC
SE
L
D E
IS C
C T
O D
N E
TI VI
N C
U E
ED S
Pin
Notes:
The pins labeled I/O-VDD5 are user I/Os for the OR2CxxA and OR2TxxB series, but they are connected to VDD5 for the OR2TxxA series.
The pins labeled VSS-ETC are the 6 x 6 array of thermal balls located at the center of the package. The balls can be attached to the ground plane
of the board for enhanced thermal capability (see Table 29), or they can be left unconnected.
Lattice Semiconductor
117
Data Sheet
November 2006
ORCA Series 2 FPGAs
Pin Information (continued)
Table 28. OR2T15A, OR2T26A, and OR2T40A/B 432-Pin EBGA Pinout
2T15A Pad
PL1D
PL1C
PL1B
PL1A
PL2D
PL2C
PL2B
PL2A
PL3D
PL3C
PL3B
PL3A
PL4D
PL4C
PL4B
PL4A
PL5D
PL5C
PL5B
PL5A
PL6D
PL6C
PL6B
PL6A
PL7D
PL7C
PL7B
PL7A
—
PL8D
PL8C
PL8B
—
PL8A
PL9D
—
PL9C
PL9B
PL9A
PL10D
PL10C
PL10B
PL10A
2T26A Pad
PL1D
PL1C
PL1B
PL1A
PL2D
PL2C
PL2B
PL2A
PL3D
PL3C
PL3B
PL3A
PL4D
PL4C
PL4B
PL4A
PL5D
PL5C
PL5B
PL5A
PL6D
PL6C
PL6B
PL6A
PL7D
PL7C
PL7B
PL7A
PL8D
PL8C
PL8A
PL9D
PL9C
PL9A
PL10D
PL10C
PL10A
PL11D
PL11A
PL12D
PL12C
PL12B
PL12A
2T40A/B Pad
PL1D
PL1A
PL2D
PL2A
PL3D
PL3C
PL3B
PL3A
PL4D
PL4C
PL4B
PL4A
PL5D
PL5C
PL5B
PL6D
PL7D
PL7C
PL7B
PL8D
PL9D
PL9C
PL9B
PL9A
PL10D
PL10C
PL10B
PL10A
PL11D
PL11C
PL11A
PL12D
PL12C
PL12A
PL13D
PL13C
PL13A
PL14D
PL14A
PL15D
PL15C
PL15B
PL15A
Function
I/O
I/O
I/O
I/O
I/O-A0
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O-VDD5
I/O
I/O
I/O
I/O
I/O
I/O
I/O-A1
I/O
I/O
I/O
I/O-A2
I/O
I/O
I/O
I/O-A3
I/O-VDD5
I/O
I/O
I/O
I/O
I/O-A4
I/O-A5
I/O
I/O
I/O
I/O-A6
I/O
I/O
I/O
I/O-A7
SE
L
D E
IS C
C T
O D
N E
TI VI
N C
U E
ED S
Pin
E28
D29
D30
D31
F28
E29
E30
E31
F29
F30
F31
H28
G29
G30
G31
J28
H29
H30
J29
K28
J30
J31
K29
K30
K31
L29
M28
L30
L31
M29
N28
M30
N29
N30
P28
N31
P29
P30
P31
R29
R30
R31
T29
Notes:
The OR2T15A pin AG2 is not connected in the 432-pin EBGA package.
The pins labeled I/O-VDD5 are user I/Os for the OR2CxxA and OR2TxxB series, but they are connected to VDD5 for the OR2TxxA series.
118
Lattice Semiconductor
Data Sheet
November 2006
ORCA Series 2 FPGAs
Pin Information (continued)
Table 28. OR2T15A, OR2T26A, and OR2T40A/B 432-Pin EBGA Pinout (continued)
2T15A Pad
PL11D
PL11C
PL11B
PL11A
PL12D
—
PL12C
PL12B
—
PL12A
PL13D
—
PL13C
PL13B
PL13A
PL14D
PL14C
PL14B
PL14A
PL15D
PL15C
PL15B
PL15A
PL16D
PL16C
PL16B
PL16A
PL17D
PL17C
PL17B
PL17A
PL18D
PL18C
PL18B
PL18A
PL19D
PL19C
PL19B
PL19A
PL20D
PL20C
PL20B
PL20A
CCLK
2T26A Pad
PL13D
PL13C
PL13B
PL13A
PL14D
PL14C
PL14A
PL15D
PL15C
PL15A
PL16D
PL16C
PL16A
PL17D
PL17A
PL18D
PL18C
PL18B
PL18A
PL19D
PL19C
PL19B
PL19A
PL20D
PL20C
PL20B
PL20A
PL21D
PL21C
PL21B
PL21A
PL22D
PL22C
PL22B
PL22A
PL23D
PL23C
PL23B
PL23A
PL24D
PL24C
PL24B
PL24A
CCLK
2T40A/B Pad
PL16D
PL16C
PL16B
PL16A
PL17D
PL17C
PL17A
PL18D
PL18C
PL18A
PL19D
PL19C
PL19A
PL20D
PL20A
PL21D
PL21C
PL21B
PL21A
PL22D
PL22C
PL22B
PL22A
PL23D
PL23C
PL24D
PL25D
PL25A
PL26C
PL26B
PL26A
PL27D
PL27C
PL27B
PL27A
PL28D
PL28C
PL28B
PL28A
PL29A
PL30C
PL30B
PL30A
CCLK
Function
I/O
I/O-VDD5
I/O
I/O-A8
I/O-A9
I/O
I/O
I/O
I/O
I/O-A10
I/O
I/O
I/O
I/O
I/O-A11
I/O-A12
I/O
I/O
I/O
I/O
I/O
I/O-A13
I/O
I/O
I/O
I/O
I/O
I/O-A14
I/O
I/O
I/O
I/O-VDD5
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O-A15
CCLK
SE
L
D E
IS C
C T
O D
N E
TI VI
N C
U E
ED S
Pin
T28
T30
U31
U30
U29
V31
V30
V29
W31
V28
W30
W29
Y30
W28
Y29
AA31
AA30
Y28
AA29
AB31
AB30
AB29
AC31
AC30
AB28
AC29
AD30
AD29
AC28
AE31
AE30
AE29
AD28
AF31
AF30
AF29
AG31
AG30
AG29
AF28
AH31
AH30
AH29
AG28
Notes:
The OR2T15A pin AG2 is not connected in the 432-pin EBGA package.
The pins labeled I/O-VDD5 are user I/Os for the OR2CxxA and OR2TxxB series, but they are connected to VDD5 for the OR2TxxA series.
Lattice Semiconductor
119
Data Sheet
November 2006
ORCA Series 2 FPGAs
Pin Information (continued)
Table 28. OR2T15A, OR2T26A, and OR2T40A/B 432-Pin EBGA Pinout (continued)
2T15A Pad
PB1A
PB1B
PB1C
PB1D
PB2A
PB2B
PB2C
PB2D
PB3A
PB3B
PB3C
PB3D
PB4A
PB4B
PB4C
PB4D
PB5A
PB5B
PB5C
PB5D
PB6A
PB6B
PB6C
PB6D
PB7A
PB7B
PB7C
PB7D
—
PB8A
PB8B
PB8C
—
PB8D
PB9A
PB9B
PB9C
—
PB9D
PB10A
PB10B
PB10C
PB10D
PB11A
2T26A Pad
PB1A
PB1B
PB1C
PB1D
PB2A
PB2B
PB2C
PB2D
PB3A
PB3B
PB3C
PB3D
PB4A
PB4B
PB4C
PB4D
PB5A
PB5B
PB5C
PB5D
PB6A
PB6B
PB6C
PB6D
PB7A
PB7B
PB7C
PB7D
PB8A
PB8B
PB8D
PB9A
PB9B
PB9D
PB10A
PB10D
PB11A
PB11B
PB11D
PB12A
PB12B
PB12C
PB12D
PB13A
2T40A/B Pad
PB1A
PB1B
PB2A
PB2D
PB3A
PB3B
PB3C
PB3D
PB4A
PB4B
PB4C
PB4D
PB5A
PB5B
PB5C
PB5D
PB6A
PB6B
PB6C
PB6D
PB7A
PB7D
PB8A
PB8D
PB9A
PB9D
PB10A
PB10D
PB11A
PB11B
PB11D
PB12A
PB12B
PB12D
PB13A
PB13D
PB14A
PB14B
PB14D
PB15A
PB15B
PB15C
PB15D
PB16A
Function
I/O-A16
I/O
I/O
I/O
I/O
I/O
I/O
I/O-VDD5
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O-A17
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O-VDD5
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
SE
L
D E
IS C
C T
O D
N E
TI VI
N C
U E
ED S
Pin
AH27
AJ28
AK28
AL28
AH26
AJ27
AK27
AL27
AJ26
AK26
AL26
AH24
AJ25
AK25
AL25
AH23
AJ24
AK24
AJ23
AH22
AK23
AL23
AJ22
AK22
AL22
AJ21
AH20
AK21
AL21
AJ20
AH19
AK20
AJ19
AK19
AH18
AL19
AJ18
AK18
AL18
AJ17
AK17
AL17
AJ16
AH16
Notes:
The OR2T15A pin AG2 is not connected in the 432-pin EBGA package.
The pins labeled I/O-VDD5 are user I/Os for the OR2CxxA and OR2TxxB series, but they are connected to VDD5 for the OR2TxxA series.
120
Lattice Semiconductor
Data Sheet
November 2006
ORCA Series 2 FPGAs
Pin Information (continued)
Table 28. OR2T15A, OR2T26A, and OR2T40A/B 432-Pin EBGA Pinout (continued)
2T15A Pad
PB11B
PB11C
PB11D
PB12A
PB12B
PB12C
—
PB12D
PB13A
—
PB13B
PB13C
—
PB13D
PB14A
PB14B
PB14C
PB14D
PB15A
PB15B
PB15C
PB15D
PB16A
PB16B
PB16C
PB16D
PB17A
PB17B
PB17C
PB17D
PB18A
PB18B
PB18C
PB18D
PB19A
PB19B
PB19C
PB19D
PB20A
PB20B
PB20C
PB20D
DONE
2T26A Pad
PB13B
PB13C
PB13D
PB14A
PB14D
PB15A
PB15B
PB15D
PB16A
PB16B
PB16D
PB17A
PB17B
PB17D
PB18A
PB18B
PB18C
PB18D
PB19A
PB19B
PB19C
PB19D
PB20A
PB20B
PB20C
PB20D
PB21A
PB21B
PB21C
PB21D
PB22A
PB22B
PB22C
PB22D
PB23A
PB23B
PB23C
PB23D
PB24A
PB24B
PB24C
PB24D
DONE
2T40A/B Pad
PB16B
PB16C
PB16D
PB17A
PB17D
PB18A
PB18B
PB18D
PB19A
PB19B
PB19D
PB20A
PB20B
PB20D
PB21A
PB21D
PB22A
PB22D
PB23A
PB24A
PB24C
PB24D
PB25A
PB25B
PB25C
PB25D
PB26A
PB26B
PB26C
PB26D
PB27A
PB27B
PB27C
PB27D
PB28A
PB28B
PB28C
PB28D
PB29A
PB29D
PB30C
PB30D
DONE
Function
I/O
I/O
I/O
I/O-VDD5
I/O
I/O
I/O
I/O
I/O-HDC
I/O
I/O
I/O
I/O
I/O
I/O-LDC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O-INIT
I/O
I/O
I/O
I/O-VDD5
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
DONE
RESET
RESET
RESET
RESET
SE
L
D E
IS C
C T
O D
N E
TI VI
N C
U E
ED S
Pin
AK16
AL15
AK15
AJ15
AL14
AK14
AJ14
AL13
AH14
AK13
AJ13
AK12
AH13
AJ12
AL11
AK11
AH12
AJ11
AL10
AK10
AJ10
AL9
AK9
AH10
AJ9
AK8
AJ8
AH9
AL7
AK7
AJ7
AH8
AL6
AK6
AJ6
AL5
AK5
AJ5
AH6
AL4
AK4
AJ4
AH5
AG4
Notes:
The OR2T15A pin AG2 is not connected in the 432-pin EBGA package.
The pins labeled I/O-VDD5 are user I/Os for the OR2CxxA and OR2TxxB series, but they are connected to VDD5 for the OR2TxxA series.
Lattice Semiconductor
121
Data Sheet
November 2006
ORCA Series 2 FPGAs
Pin Information (continued)
Table 28. OR2T15A, OR2T26A, and OR2T40A/B 432-Pin EBGA Pinout (continued)
2T15A Pad
2T26A Pad
2T40A/B Pad
Function
PRGM
PRGM
PRGM
PRGM
PR20A
PR20B
PR20C
PR20D
PR19A
PR19B
PR19C
PR19D
PR18A
PR18B
PR18C
PR18D
PR17A
PR17B
PR17C
PR17D
PR16A
PR16B
PR16C
PR16D
PR15A
PR15B
PR15C
PR15D
PR14A
PR14B
PR14C
PR14D
PR13A
PR13B
PR13C
PR13D
—
PR12A
—
PR12B
PR12C
PR12D
PR11A
PR11B
PR11C
PR11D
PR10A
PR24A
PR24B
PR24C
PR24D
PR23A
PR23B
PR23C
PR23D
PR22A
PR22B
PR22C
PR22D
PR21A
PR21B
PR21C
PR21D
PR20A
PR20B
PR20C
PR20D
PR19A
PR19B
PR19C
PR19D
PR18A
PR18B
PR18C
PR18D
PR17A
PR17D
PR16A
PR16B
PR16D
PR15A
PR15D
PR14A
PR14B
PR14D
PR13A
PR13B
PR13C
PR13D
PR12A
PR30A
PR30B
PR29A
PR29D
PR28A
PR28B
PR28C
PR28D
PR27A
PR27B
PR27C
PR27D
PR26A
PR26B
PR26C
PR25A
PR24A
PR24B
PR24D
PR23D
PR22A
PR22B
PR22C
PR22D
PR21A
PR21B
PR21C
PR21D
PR20A
PR20D
PR19A
PR19B
PR19D
PR18A
PR18D
PR17A
PR17B
PR17D
PR16A
PR16B
PR16C
PR16D
PR15A
I/O-M0
I/O
I/O
I/O
I/O-VDD5
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O-M1
I/O
I/O
I/O
I/O-VDD5
I/O
I/O
I/O
I/O
I/O-M2
I/O
I/O
I/O
I/O
I/O-M3
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
SE
L
D E
IS C
C T
O D
N E
TI VI
N C
U E
ED S
Pin
AH3
AH2
AH1
AF4
AG3
AG2
AG1
AF3
AF2
AF1
AD4
AE3
AE2
AE1
AC4
AD3
AD2
AC3
AB4
AC2
AC1
AB3
AB2
AB1
AA3
Y4
AA2
AA1
Y3
W4
Y2
W3
W2
V4
W1
V3
V2
V1
U3
U2
U1
T3
T4
T2
Notes:
The OR2T15A pin AG2 is not connected in the 432-pin EBGA package.
The pins labeled I/O-VDD5 are user I/Os for the OR2CxxA and OR2TxxB series, but they are connected to VDD5 for the OR2TxxA series.
122
Lattice Semiconductor
Data Sheet
November 2006
ORCA Series 2 FPGAs
Pin Information (continued)
Table 28. OR2T15A, OR2T26A, and OR2T40A/B 432-Pin EBGA Pinout (continued)
2T15A Pad
PR10B
PR10C
PR10D
PR9A
PR9B
PR9C
—
PR9D
—
PR8A
PR8B
PR8C
PR8D
PR7A
PR7B
PR7C
PR7D
PR6A
PR6B
PR6C
PR6D
PR5A
PR5B
PR5C
PR5D
PR4A
PR4B
PR4C
PR4D
PR3A
PR3B
PR3C
PR3D
PR2A
PR2B
PR2C
PR2D
PR1A
PR1B
PR1C
PR1D
2T26A Pad
PR12B
PR12C
PR12D
PR11A
PR11C
PR11D
PR10A
PR10C
PR10D
PR9A
PR9D
PR8A
PR8D
PR7A
PR7B
PR7C
PR7D
PR6A
PR6B
PR6C
PR6D
PR5A
PR5B
PR5C
PR5D
PR4A
PR4B
PR4C
PR4D
PR3A
PR3B
PR3C
PR3D
PR2A
PR2B
PR2C
PR2D
PR1A
PR1B
PR1C
PR1D
2T40A/B Pad
PR15B
PR15C
PR15D
PR14A
PR14C
PR14D
PR13A
PR13C
PR13D
PR12A
PR12D
PR11A
PR11D
PR10A
PR10B
PR10C
PR10D
PR9A
PR9B
PR9C
PR9D
PR8A
PR7A
PR7C
PR6A
PR5A
PR5B
PR5C
PR5D
PR4A
PR4B
PR4C
PR4D
PR3A
PR3B
PR3C
PR3D
PR2A
PR2D
PR1A
PR1D
Function
I/O
I/O
I/O
I/O-VDD5
I/O
I/O
I/O
I/O
I/O
I/O-CS1
I/O
I/O
I/O
I/O-CS0
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O-RD
I/O
I/O
I/O
I/O-VDD5
I/O
I/O
I/O
I/O-WR
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
RD_CFGN
RD_CFGN
RD_CFGN
RD_CFGN
PT20D
PT20C
PT24D
PT24C
PT30D
PT30A
I/O
I/O
SE
L
D E
IS C
C T
O D
N E
TI VI
N C
U E
ED S
Pin
R1
R2
R3
P1
P2
P3
N1
P4
N2
N3
M2
N4
M3
L1
L2
M4
L3
K1
K2
K3
J1
J2
K4
J3
H2
H3
J4
G1
G2
G3
H4
F1
F2
F3
E1
E2
E3
F4
D1
D2
D3
E4
D5
C4
Notes:
The OR2T15A pin AG2 is not connected in the 432-pin EBGA package.
The pins labeled I/O-VDD5 are user I/Os for the OR2CxxA and OR2TxxB series, but they are connected to VDD5 for the OR2TxxA series.
Lattice Semiconductor
123
Data Sheet
November 2006
ORCA Series 2 FPGAs
Pin Information (continued)
Table 28. OR2T15A, OR2T26A, and OR2T40A/B 432-Pin EBGA Pinout (continued)
2T15A Pad
PT20B
PT20A
PT19D
PT19C
PT19B
PT19A
PT18D
PT18C
PT18B
PT18A
PT17D
PT17C
PT17B
PT17A
PT16D
PT16C
PT16B
PT16A
PT15D
PT15C
PT15B
PT15A
PT14D
PT14C
PT14B
PT14A
PT13D
PT13C
—
PT13B
PT13A
PT12D
—
PT12C
PT12B
—
PT12A
PT11D
PT11C
PT11B
PT11A
PT10D
PT10C
PT10B
2T26A Pad
PT24B
PT24A
PT23D
PT23C
PT23B
PT23A
PT22D
PT22C
PT22B
PT22A
PT21D
PT21C
PT21B
PT21A
PT20D
PT20C
PT20B
PT20A
PT19D
PT19C
PT19B
PT19A
PT18D
PT18C
PT18B
PT18A
PT17D
PT17A
PT16D
PT16B
PT16A
PT15D
PT15B
PT15A
PT14D
PT14B
PT14A
PT13D
PT13C
PT13B
PT13A
PT12D
PT12C
PT12B
2T40A/B Pad
PT29B
PT29A
PT28D
PT28C
PT28B
PT28A
PT27D
PT27C
PT27B
PT27A
PT26D
PT26C
PT26B
PT26A
PT25D
PT25C
PT25B
PT25A
PT24D
PT24C
PT24B
PT23D
PT22D
PT22A
PT21D
PT21A
PT20D
PT20A
PT19D
PT19B
PT19A
PT18D
PT18B
PT18A
PT17D
PT17B
PT17A
PT16D
PT16C
PT16B
PT16A
PT15D
PT15C
PT15B
Function
I/O
I/O
I/O
I/O
I/O
I/O-RDY/RCLK
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O-D7
I/O
I/O
I/O
I/O-VDD5
I/O
I/O
I/O
I/O
I/O
I/O-D6
I/O
I/O
I/O
I/O-VDD5
I/O
I/O-D5
I/O
I/O
I/O
I/O
I/O
I/O-D4
I/O
I/O
I/O
I/O-D3
I/O
I/O
I/O-VDD5
SE
L
D E
IS C
C T
O D
N E
TI VI
N C
U E
ED S
Pin
B4
A4
D6
C5
B5
A5
C6
B6
A6
D8
C7
B7
A7
D9
C8
B8
C9
D10
B9
A9
C10
B10
A10
C11
D12
B11
A11
C12
D13
B12
C13
B13
D14
A13
C14
B14
A14
C15
B15
A15
C16
D16
B16
A17
Notes:
The OR2T15A pin AG2 is not connected in the 432-pin EBGA package.
The pins labeled I/O-VDD5 are user I/Os for the OR2CxxA and OR2TxxB series, but they are connected to VDD5 for the OR2TxxA series.
124
Lattice Semiconductor
Data Sheet
November 2006
ORCA Series 2 FPGAs
Pin Information (continued)
Table 28. OR2T15A, OR2T26A, and OR2T40A/B 432-Pin EBGA Pinout (continued)
2T15A Pad
PT10A
PT9D
—
PT9C
PT9B
—
PT9A
PT8D
—
PT8C
PT8B
PT8A
PT7D
PT7C
PT7B
PT7A
PT6D
PT6C
PT6B
PT6A
PT5D
PT5C
PT5B
PT5A
PT4D
PT4C
PT4B
PT4A
PT3D
PT3C
PT3B
PT3A
PT2D
PT2C
PT2B
PT2A
PT1D
PT1C
PT1B
PT1A
RD_DATA/TDO
VSS
VSS
VSS
2T26A Pad
PT12A
PT11D
PT11C
PT11A
PT10D
PT10C
PT10A
PT9D
PT9C
PT9A
PT8D
PT8A
PT7D
PT7C
PT7B
PT7A
PT6D
PT6C
PT6B
PT6A
PT5D
PT5C
PT5B
PT5A
PT4D
PT4C
PT4B
PT4A
PT3D
PT3C
PT3B
PT3A
PT2D
PT2C
PT2B
PT2A
PT1D
PT1C
PT1B
PT1A
RD_DATA/TDO
VSS
VSS
VSS
2T40A/B Pad
PT15A
PT14D
PT14C
PT14A
PT13D
PT13C
PT13A
PT12D
PT12C
PT12A
PT11D
PT11A
PT10D
PT10A
PT9D
PT9A
PT8D
PT8A
PT7D
PT7A
PT6D
PT6C
PT6B
PT6A
PT5D
PT5C
PT5B
PT5A
PT4D
PT4C
PT4B
PT4A
PT3D
PT3C
PT3B
PT3A
PT2D
PT2A
PT1D
PT1A
RD_DATA/TDO
VSS
VSS
VSS
Function
I/O-D2
D1
I/O
I/O
I/O
I/O
I/O-D0/DIN
I/O
I/O
I/O
I/O
I/O-DOUT
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O-TDI
I/O
I/O
I/O
I/O-VDD5
I/O
I/O
I/O
I/O-TMS
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O-TCK
RD_DATA/TDO
VSS
VSS
VSS
SE
L
D E
IS C
C T
O D
N E
TI VI
N C
U E
ED S
Pin
B17
C17
A18
B18
C18
A19
D18
B19
C19
B20
D19
C20
A21
B21
D20
C21
A22
B22
C22
A23
B23
D22
C23
B24
C24
D23
A25
B25
C25
D24
A26
B26
C26
A27
B27
C27
D26
A28
B28
C28
D27
A12
A16
A2
Notes:
The OR2T15A pin AG2 is not connected in the 432-pin EBGA package.
The pins labeled I/O-VDD5 are user I/Os for the OR2CxxA and OR2TxxB series, but they are connected to VDD5 for the OR2TxxA series.
Lattice Semiconductor
125
Data Sheet
November 2006
ORCA Series 2 FPGAs
Pin Information (continued)
Table 28. OR2T15A, OR2T26A, and OR2T40A/B 432-Pin EBGA Pinout (continued)
2T15A Pad
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
2T26A Pad
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
2T40A/B Pad
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
Function
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
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Pin
A20
A24
A29
A3
A30
A8
AD1
AD31
AJ1
AJ2
AJ30
AJ31
AK1
AK29
AK3
AK31
AL12
AL16
AL2
AL20
AL24
AL29
AL3
AL30
AL8
B1
B29
B3
B31
C1
C2
C30
C31
H1
H31
M1
M31
T1
T31
Y1
Y31
A1
A31
Notes:
The OR2T15A pin AG2 is not connected in the 432-pin EBGA package.
The pins labeled I/O-VDD5 are user I/Os for the OR2CxxA and OR2TxxB series, but they are connected to VDD5 for the OR2TxxA series.
126
Lattice Semiconductor
Data Sheet
November 2006
ORCA Series 2 FPGAs
Pin Information (continued)
Table 28. OR2T15A, OR2T26A, and OR2T40A/B 432-Pin EBGA Pinout (continued)
2T15A Pad
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
2T26A Pad
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
2T40A/B Pad
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
Function
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
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Pin
AA28
AA4
AE28
AE4
AH11
AH15
AH17
AH21
AH25
AH28
AH4
AH7
AJ29
AJ3
AK2
AK30
AL1
AL31
B2
B30
C29
C3
D11
D15
D17
D21
D25
D28
D4
D7
G28
G4
L28
L4
R28
R4
U28
U4
Notes:
The OR2T15A pin AG2 is not connected in the 432-pin EBGA package.
The pins labeled I/O-VDD5 are user I/Os for the OR2CxxA and OR2TxxB series, but they are connected to VDD5 for the OR2TxxA series.
Lattice Semiconductor
127
Data Sheet
November 2006
ORCA Series 2 FPGAs
Package Thermal Characteristics
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There are three thermal parameters that are in common use: ΘJA, ψJC, and ΘJC. It should be noted that all
the parameters are affected, to varying degrees, by
package design (including paddle size) and choice of
materials, the amount of copper in the test board or
system board, and system airflow.
where TC is the case temperature at top dead center,
TJ is the junction temperature, and Q is the chip power.
During the ΘJA measurements described above,
besides the other parameters measured, an additional
temperature reading, TC, is made with a thermocouple
attached at top-dead-center of the case. ψJC is also
expressed in units of °C/watt.
Table 29 contains the currently available thermal specifications for FPGA packages mounted on both JEDEC
and non-JEDEC test boards. The thermal values for the
newer package types correspond to those packages
mounted on a JEDEC four-layer board (indicated as
Note 2 in the table). The values for the older packages,
however, correspond to those packages mounted on a
non-JEDEC, single-layer, sparse copper board (see
Note 1). It should also be noted that the values for the
older packages are considered conservative.
ΘJA
This is the thermal resistance from junction to ambient
(a.k.a. theta-JA, R-theta, etc.).
ΘJC
This is the thermal resistance from junction to case. It
is most often used when attaching a heat sink to the
top of the package. It is defined by:
TJ – TC
Θ JC = -------------------Q
The parameters in this equation have been defined
above. However, the measurements is performed with
the case of the part pressed against a water-cooled
heat sink so as to draw most of the heat generated by
the chip out the top of the package. It is this difference
in the measurement process that differentiates ΘJC
from ψJC. ΘJC is a true thermal resistance and is
expressed in units of °C/watt.
TJ – TA
Θ JA = -------------------Q
where TJ is the junction temperature, TA is the ambient
air temperature, and Q is the chip power.
Experimentally, ΘJA is determined when a special thermal test die is assembled into the package of interest,
and the part is mounted on the thermal test board. The
diodes on the test chip are separately calibrated in an
oven. The package/board is placed either in a JEDEC
natural convection box or in the wind tunnel, the latter
for forced convection measurements. A controlled
amount of power (Q) is dissipated in the test chip’s
heater resistor, the chip’s temperature (TJ) is determined by the forward drop on the diodes, and the ambient temperature (TA) is noted. Note that ΘJA is
expressed in units of °C/watt.
ΘJB
This is the thermal resistance from junction to board
(a.k.a., ΘJL). It is defined by:
TJ – TB
Θ JB = -------------------Q
where TB is the temperature of the board adjacent to a
lead measured with a thermocouple. The other parameters on the right-hand side have been defined above.
This is considered a true thermal resistance, and the
measurement is made with a water-cooled heat sink
pressed against the board so as to draw most of the
heat out of the leads. Note that ΘJB is expressed in
units of °C/watt, and that this parameter and the way it
is measured is still in JEDEC committee.
ψJC
This JEDEC designated parameter correlates the junction temperature to the case temperature. It is generally
used to infer the junction temperature while the device
is operating in the system. It is not considered a true
thermal resistance, and it is defined by:
TJ – TC
ψ JC = ------------------Q
128
Lattice Semiconductor
Data Sheet
November 2006
ORCA Series 2 FPGAs
Package Thermal Characteristics (continued)
FPGA Maximum Junction Temperature
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Once the power dissipated by the FPGA has been determined (see the Estimating Power Dissipation section), the
maximum junction temperature of the FPGA can be found. This is needed to determine if speed derating of the
device from the 85 °C junction temperature used in all of the delay tables is needed. Using the maximum ambient
temperature, TAmax, and the power dissipated by the device, Q (expressed in °C), the maximum junction temperature is approximated by:
TJmax = TAmax + (Q • ΘJA)
Table 29 lists the thermal characteristics for all packages used with the Series 2 FPGAs.
Table 29. Series 2 Plastic Package Thermal Guidelines
0 fpm
ΘJA (°C/W)
200 fpm
500 fpm
40.0
30.0—27.0
52.0
24.0
26.5
12.8
25.5
13.0
22.5
26.0
27.5
12.0
19.0
25.5
11.0
35.0
26—23
39.0
21.5
23.0
10.3
22.5
10.0
19.0
22.0
24.0
10.0
16.0
22.0
8.5
—
24.0—21.0
—
20.5
21.0
9.1
21.0
9.0
17.5
20.5
22.5
9.0
15.0
20.5
7.5
Package
84-Pin PLCC1
100-Pin TQFP2
144-Pin TQFP1
160-Pin QFP2
208-Pin SQFP2
208-Pin SQFP22
240-Pin SQFP2
240-Pin SQFP22
256-Pin PBGA2, 3
256-Pin PBGA2, 4
304-Pin SQFP2
304-Pin SQFP22
352-Pin PBGA2, 3
352-Pin PBGA2, 4
432-Pin EBGA2
1.
2.
3.
4.
TA = 70 °C max
TJ = 125 °C max
@ 0 fpm (W)
1.4
1.8—2.0
1.1
2.3
2.1
4.3
2.2
4.2
2.4
2.1
2.0
4.6
2.9
2.1
5.0
Mounted on a sparse copper one-layer test board.
Mounted on four-layer JEDEC standard test board with two power/ground planes.
With thermal balls connected to board ground plane.
Without thermal balls connected to board ground plane.
Note: The ψJC for the packages listed is <1 °C/W. This implies that virtually all of the heat is dissipated through the board on which the package
is mounted.
Package Coplanarity
Package Parasitics
The coplanarity limits of the Series 2 series packages
are as follows:
■ TQFP: 3.15 mils
■ PLCC and QFP: 4.0 mils
■ PBGA: 8.0 mils
■ SQFP: 4.0 mils (240 and 304 only)
3.15 mils (all other sizes)
■ SQFP2: 3.15 mils
■ EBGA: 8.0 mils
The electrical performance of an IC package, such as
signal quality and noise sensitivity, is directly affected
by the package parasitics. Table 30 lists eight parasitics
associated with the ORCA packages. These parasitics
represent the contributions of all components of a
package, which include the bond wires, all internal
package routing, and the external leads.
Lattice Semiconductor
Four inductances in nH are listed: LSW and LSL, the
self-inductance of the lead; and LMW and LML, the
mutual inductance to the nearest neighbor lead.
129
Data Sheet
November 2006
ORCA Series 2 FPGAs
Package Parasitics (continued)
These parameters are important in determining ground bounce noise and inductive crosstalk noise. Three capacitances in pF are listed: CM, the mutual capacitance of the lead to the nearest neighbor lead; and C1 and C2, the
total capacitance of the lead to all other leads (all other leads are assumed to be grounded). These parameters are
important in determining capacitive crosstalk and the capacitive loading effect of the lead.
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The parasitic values in Table 30 are for the circuit model of bond wire and package lead parasitics. If the mutual
capacitance value is not used in the designer’s model, then the value listed as mutual capacitance should be
added to each of the C1 and C2 capacitors.
Table 30. Series 2 Package Parasitics
Package Type
LSW
LMW
RW
C1
C2
CM
LSL
LML
84-Pin PLCC
3
1
140
1
1
0.5
7—11
3—6
100-Pin TQFP
3
1
150
0.5
0.5
0.4
4—6
2—3
144-Pin TQFP
3
1
140
1
1
0.6
4—6
2—2.5
160-Pin QFP
4
1.5
180
1.5
1.5
1
10—13
6—8
208-Pin SQFP
4
2
200
1
1
1
7—10
4—6
208-Pin SQFP2
4
2
200
1
1
1
6—9
4—6
240-Pin SQFP
4
2
200
1
1
1
8—12
5—8
240-Pin SQFP2
4
2
200
1
1
1
7—11
4—7
256-Pin PBGA
5
2
220
1
1
1
5—8
2—4
304-Pin SQFP
5
2
220
1
1
1
12—18
7—12
304-Pin SQFP2
5
2
220
1
1
1
11—17
7—12
352-Pin PBGA
5
2
220
1.5
1.5
1.5
7—12
3—6
432-Pin EBGA
4
1.5
500
1
1
0.3
3—5.5
0.5—1
LW
RW
LL
CIRCUIT
BOARD PAD
PAD N
C1
LMW CM
C2
LML
PAD N + 1
LW
RW
LL
C1
C2
5-3862(F).r2
Figure 53. Package Parasitics
130
Lattice Semiconductor
Data Sheet
November 2006
ORCA Series 2 FPGAs
Absolute Maximum Ratings
Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are absolute stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess of
those given in the operations sections of this data sheet. Exposure to absolute maximum ratings for extended periods
can adversely affect device reliability.
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The ORCA Series FPGAs include circuitry designed to protect the chips from damaging substrate injection currents
and prevent accumulations of static charge. Nevertheless, conventional precautions should be observed during storage, handling, and use to avoid exposure to excessive electrical stress.
Parameter
Symbol
Min
Max
Unit
Storage Temperature
Tstg
–65
150
°C
Supply Voltage with Respect to Ground
VDD
–0.5
7.0
V
VDD5 Supply Voltage with Respect to Ground
(OR2TxxA)
VDD5
VDD
7.0
V
Input Signal with Respect to Ground
OR2TxxA only
—
–0.5
VDD + 0.3
VDD5 + 0.3
V
Signal Applied to High-impedance Output
OR2TxxA only
—
–0.5
VDD + 0.3
VDD5 + 0.3
V
Maximum Soldering Temperature
—
—
260
°C
Recommended Operating Conditions
OR2CxxA
Mode
Commercial
Industrial
OR2TxxA/OR2TxxB
Temperature
Range
(Ambient)
Supply Voltage
(VDD)
Temperature
Range
(Ambient)
Supply Voltage
(VDD)
Supply Voltage*
(VDD5)
0 °C to 70 °C
5 V ± 5%
0 °C to 70 °C
3.0 V to 3.6 V
VDD to 5.25 V
–40 °C to +85 °C
5 V ± 10%
–40 °C to +85 °C
3.0 V to 3.6 V
VDD to 5.25 V
Notes:
During powerup and powerdown sequencing, VDD is allowed to be at a higher voltage level than VDD5 for up to 100 ms.
During powerup sequencing of OR2TxxA devices VDD should reach 1.0 V before voltage applied to VDD5 can be greater than the voltage applied
to VDD.
The maximum recommended junction temperature (TJ) during operation is 125 °C.
* VDD5 not used in OR2TxxB devices.
Lattice Semiconductor
131
Data Sheet
November 2006
ORCA Series 2 FPGAs
Electrical Characteristics
Table 31A. OR2CxxA and OR2TxxA Electrical Characteristics
OR2CxxA Commercial: VDD = 5.0 V ± 5%, 0 °C ≤ TA ≤ 70 °C; OR2CxxA Industrial: VDD = 5.0 V ± 10%, –40 °C ≤ TA ≤ +85 °C.
OR2TxxA Commercial: VDD = 3.0 V to 3.6 V, 0 °C ≤ TA ≤ 70 °C; OR2TxxA Industrial: VDD = 3.0 V to 3.6 V, –40 °C ≤ TA ≤
+85 °C.
Symbol
OR2CxxA
OR2TxxA
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Parameter
Input Voltage:
High
Low
Input Voltage:
High
Low
Output Voltage:
High
Low
Input Leakage Current
Standby Current:
OR2C04A/OR2T04A
OR2C06A/OR2T06A
OR2C08A/OR2T08A
OR2C10A/OR2T10A
OR2C12A
OR2C15A/OR2T15A
OR2C26A/OR2T26A
OR2C40A/OR2T40A
Standby Current:
OR2C04A/OR2T04A
OR2C06A/OR2T06A
OR2C08A/OR2T08A
OR2C10A/OR2T10A
OR2C12A
OR2C15A/OR2T15A
OR2C26A/OR2T26A
OR2C40A/OR2T40A
Data Retention Voltage
Input Capacitance
Output Capacitance
Test Conditions
Min
Max
Min
Max
Unit
Input configured as CMOS
50% VDD VDD + 0.3 50% VDD5 VDD5 + 0.3
GND – 0.5 30% VDD GND – 0.5 30% VDD5
VIH
VIL
VIH
VIL
VOH
VOL
IL
IDDSB
IDDSB
VDR
CIN
COUT
DONE Pull-up Resistor*
M3, M2, M1, and M0
Pull-up Resistors*
I/O Pad Static Pull-up
Current*
RDONE
RM
I/O Pad Static Pull-down
Current
IPD
I/O Pad Pull-up Resistor*
I/O Pad Pull-down
Resistor
RPU
RPD
IPU
Input configured as TTL
(valid for OR2CxxA only)
VDD = min, IOH = 6 mA or 3 mA
VDD = min, IOL = 12 mA or 6 mA
VDD = Max, VIN = VSS or VDD
OR2CxxA (TA = 25 °C, VDD = 5.0 V)
OR2TxxA (TA = 25 °C, VDD = 3.3 V)
internal oscillator running,
no output loads,
inputs at VDD or GND
(after configuration)
OR2CxxA (TA = 25 °C, VDD = 5.0 V)
OR2TxxA (TA = 25 °C, VDD = 3.3 V)
internal oscillator stopped,
no output loads,
inputs at VDD or GND
(after configuration)
TA = 25 °C
OR2CxxA (TA = 25 °C, VDD = 5.0 V)
OR2TxxA (TA = 25 °C, VDD = 3.3 V)
Test frequency = 1 MHz
OR2CxxA (TA = 25 °C, VDD = 5.0 V)
OR2TxxA (TA = 25 °C, VDD = 3.3 V)
Test frequency = 1 MHz
—
—
OR2CxxA (VDD = 5.25 V, VIN = VSS,
TA = 0 °C)
OR2TxxA (VDD = 3.6 V, VIN = VSS,
TA = 0 °C)
OR2CxxA (VDD = 5.25 V, VIN = VSS,
TA = 0 °C)
OR2TxxA (VDD = 3.6 V, VIN = VSS,
TA = 0 °C)
VDD = All, VIN = VSS, TA = 0 °C
VDD = All, VIN = VDD, TA = 0 °C
V
V
2.0
–0.5
VDD + 0.3
—
—
—
0.8
—
V
V
2.4
—
–10
—
0.4
10
2.4
—
–10
—
0.4
10
V
V
µA
—
—
—
—
—
—
—
—
6.5
7.0
7.7
8.4
9.2
10.0
12.2
16.3
—
—
—
—
—
—
—
—
4.0
4.3
4.8
5.3
5.8
6.3
7.8
10.6
mA
mA
mA
mA
mA
mA
mA
mA
—
—
—
—
—
—
—
—
2.3
—
1.5
2.0
2.7
3.4
4.2
5.0
7.2
11.3
—
9
—
—
—
—
—
—
—
—
2.3
—
1.0
1.3
1.8
2.3
2.8
3.3
4.8
7.6
—
9
mA
mA
mA
mA
mA
mA
mA
mA
V
pF
—
9
—
9
pF
100k
100k
—
—
100k
100k
—
—
Ω
Ω
14.4
50.9
14.4
50.9
µA
26
103
26
103
µA
100k
50k
—
—
100k
50k
—
—
Ω
Ω
* On the OR2TxxA devices, the pull-up resistor will externally pull the pin to a level 1.0 V below VDD.
132
Lattice Semiconductor
Data Sheet
November 2006
ORCA Series 2 FPGAs
Electrical Characteristics (continued)
Table 31B. OR2TxxB Electrical Characteristics
OR2TxxB Commercial: VDD = 3.0 V to 3.6 V, 0 °C ≤ TA ≤ 70 °C; OR2TxxB Industrial: VDD = 3.0 V to 3.6 V, –40 °C ≤ TA ≤ +85 °C.
Symbol
OR2TxxB
Test Conditions
Unit
Min
Max
80% VDD
GND – 0.5
VDD + 0.3
15% VDD
V
V
2.4
—
–10
—
0.4
10
V
V
µA
—
—
5.5
8.0
mA
mA
—
—
2.0
4.5
mA
mA
2.3
—
—
8
V
pF
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Parameter
Input Voltage:
High
Low
Output Voltage:
High
Low
Input Leakage Current
Standby Current:
OR2T15B
OR2T40B
Standby Current:
OR2T15B
OR2T40B
Data Retention Voltage
Input Capacitance
Output Capacitance
DONE Pull-up Resistor*
M3, M2, M1, and M0
Pull-up Resistors*
I/O Pad Static Pull-up
Current*
I/O Pad Static Pull-down Current
I/O Pad Pull-up Resistor*
I/O Pad Pull-down
Resistor
Input configured as CMOS
VIH
VIL
VOH
VOL
IL
IDDSB
IDDSB
VDR
CIN
VDD = min, IOH = 6 mA or 3 mA
VDD = min, IOL = 12 mA or 6 mA
VDD = max, VIN = VSS or VDD
OR2TxxB (TA = 25 °C, VDD = 3.3 V)
internal oscillator running,
no output loads,
inputs at VDD or GND
(after configuration)
OR2TxxB (TA = 25 °C, VDD = 3.3 V)
internal oscillator stopped,
no output loads,
inputs at VDD or GND
(after configuration)
TA = 25 °C
OR2TxxB (TA = 25 °C, VDD = 3.3 V)
Test frequency = 1 MHz
OR2TxxB (TA = 25 °C, VDD = 3.3 V)
Test frequency = 1 MHz
—
—
—
8
pF
100k
100k
—
—
Ω
Ω
IPU
VDD = 3.6 V, VIN = VSS, TA = 0 °C
14.4
50.9
µA
IPD
VDD = 3.6 V, VIN = VDD, TA = 0 °C
26
103
µA
RPU
RPD
VDD = all, VIN = VSS, TA = 0 °C
VDD = all, VIN = VDD, TA = 0 °C
100k
50k
—
—
Ω
Ω
COUT
RDONE
RM
* On the OR2TxxB devices, the pull-up resistor will externally pull the pin to a level 1.0 V below VDD.
Lattice Semiconductor
133
Data Sheet
November 2006
ORCA Series 2 FPGAs
Timing Characteristics
Table 32A. OR2CxxA and OR2TxxA Combinatorial PFU Timing Characteristics
OR2CxxA Commercial: VDD = 5.0 V ± 5%, 0 °C ≤ TA ≤ 70 °C; OR2CxxA Industrial: VDD = 5.0 V ± 10%, –40 °C ≤ TA ≤ +85 °C.
OR2TxxA Commercial: VDD = 3.0 V to 3.6 V, 0 °C ≤ TA ≤ 70 °C; OR2TxxA Industrial: VDD = 3.0 V to 3.6 V, –40 °C ≤ TA ≤ +85 °C.
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N C
U E
ED S
Speed
Parameter
Symbol
-3
-4
-5
-6
Unit
-7
Min Max Min Max Min Max Min Max Min Max
Combinatorial Delays
(TJ = +85 °C, VDD = min):
Four Input Variables (A[4:0],
B[4:0] to F[3:0])
Five Input Variables (A[4:0],
B[4:0] to F3, F0)
PFUMUX (A[4:0], B[4:0] to F1)
PFUMUX (C0 to f1)
PFUNAND (A[4:0], B[4:0] to F2)
PFUNAND (C0 to F2)
PFUXOR (A[4:0], B[4:0] to F1)
PFUXOR (C0 to F1)
F4*_DEL
—
2.8
—
2.1
—
1.7
—
1.4
—
1.3
ns
F5*_DEL
—
2.9
—
2.2
—
1.8
—
1.4
—
1.3
ns
MUX_DEL
C0MUX_DEL
ND_DEL
C0ND_DEL
XOR_DEL
C0XOR_DEL
—
—
—
—
—
—
3.8
2.2
4.0
2.2
4.5
2.2
—
—
—
—
—
—
3.2
1.9
3.3
1.8
3.8
2.0
—
—
—
—
—
—
2.6
1.5
2.7
1.5
3.1
1.6
—
—
—
—
—
—
1.9
1.1
1.8
1.0
2.3
1.1
—
—
—
—
—
—
1.8
1.0
1.7
0.8
2.1
1.0
ns
ns
ns
ns
ns
ns
Table 32B. OR2TxxB Combinatorial PFU Timing Characteristics
OR2TxxB Commercial: VDD = 3.0 V to 3.6 V, 0 °C ≤ TA ≤ 70 °C; OR2TxxB Industrial: VDD = 3.0 V to 3.6 V, –40 °C ≤ TA ≤ +85 °C.
Speed
Parameter
Symbol
-7
Unit
-8
Min Max Min Max
Combinatorial Delays
(TJ = +85 °C, VDD = min):
Four Input Variables (A[4:0],
B[4:0] to F[3:0])
Five Input Variables (A[4:0],
B[4:0] to F3, F0)
PFUMUX (A[4:0], B[4:0] to F1)
PFUMUX (C0 to F1)
PFUNAND (A[4:0], B[4:0] to F2)
PFUNAND (C0 to F2)
PFUXOR (A[4:0], B[4:0] to F1)
PFUXOR (C0 to F1)
134
F4*_DEL
—
1.3
—
1.0
ns
F5*_DEL
—
1.3
—
1.0
ns
MUX_DEL
C0MUX_DEL
ND_DEL
C0ND_DEL
XOR_DEL
C0XOR_DEL
—
—
—
—
—
—
2.2
1.4
2.1
1.2
2.5
1.3
—
—
—
—
—
—
1.8
1.0
1.7
0.9
2.0
1.0
ns
ns
ns
ns
ns
ns
Lattice Semiconductor
Data Sheet
November 2006
ORCA Series 2 FPGAs
Timing Characteristics (continued)
XSW LINES
SE
L
D E
IS C
C T
O D
N E
TI VI
N C
U E
ED S
FDBK_DEL
A[4:0], B[4:0]
F4*_DEL
(LUT)
4
F[3:0]
A[4:0], B[4:0]
F5*_DEL
(LUT)
2
F3, F0
MUX_DEL
F1
OMUX_DEL
OUTPUT MUX
PFU
O[4:0]
C
A[4:0], B[4:0]
(LUT)
2
XOR_DEL
ND_DEL
C0
F2
C0MUX_DEL, C0XOR_DEL, C0ND_DEL
5-4633(F).a
C = controlled by configuration RAM.
Notes:
The parameters MUX_DEL, XOR_DEL, and ND_DEL include the delay through the LUT in F5A/F5B modes.
See Table 41 for an explanation of FDBK_DEL and OMUX_DEL.
Figure 54. Combinatorial PFU Timing
Lattice Semiconductor
135
Data Sheet
November 2006
ORCA Series 2 FPGAs
Timing Characteristics (continued)
Table 33A. OR2CxxA and OR2TxxA Sequential PFU Timing Characteristics
OR2CxxA Commercial: VDD = 5.0 V ± 5%, 0 °C ≤ TA ≤ 70 °C; OR2CxxA Industrial: VDD = 5.0 V ± 10%, –40 °C ≤ TA ≤ +85 °C.
OR2TxxA Commercial: VDD = 3.0 V to 3.6 V, 0 °C ≤ TA ≤ 70 °C; OR2TxxA Industrial: VDD = 3.0 V to 3.6 V, –40 °C ≤ TA ≤ +85 °C.
SE
L
D E
IS C
C T
O D
N E
TI VI
N C
U E
ED S
Speed
Parameter
Symbol
-3
-4
-5
-6
Unit
-7
Min Max Min Max Min Max Min Max Min Max
Input Requirements
Clock Low Time
TCL
Clock High Time
TCH
Global S/R Pulse Width (GSRN)
TRW
Local S/R Pulse Width
TPW
Combinatorial Setup Times (TJ = 85 °C,
VDD = min):
Four Input Variables to Clock
F4*_SET
(A[4:0], B[4:0] to CK)
Five Input Variables to Clock
F5*_SET
(A[4:0], B[4:0] to CK)
PFUMUX to Clock (A[4:0], B[4:0] to CK)
MUX_SET
PFUMUX to Clock (C0 to CK)
C0MUX_SET
PFUNAND to Clock (A[4:0], B[4:0] to CK)
ND_SET
PFUNAND to Clock (C0 to CK)
C0ND_SET
PFUXOR to Clock (A[4:0], B[4:0] to CK)
XOR_SET
PFUXOR to Clock (C0 to CK)
C0XOR_SET
Data In to Clock (WD[3:0] to CK)
D*_SET
Clock Enable to Clock (CE to CK)
CKEN_SET
Local Set/Reset (synchronous) (LSR to CK)
LSR_SET
Data Select to Clock (SEL to CK)
SELECT_SET
Pad Direct In
PDIN_SET
Combinatorial Hold Times (TJ = all, VDD = all):
D*_HLD
Data In (WD[3:0] from CK)
CKEN_HLD
Clock Enable (CE from CK)
LSR_HLD
Local Set/Reset (synchronous) (LSR from CK)
SELECT_HLD
Data Select (sel from CK)
PDIN_HLD
Pad Direct In Hold (DIA[3:0], DIB[3:0] to CK)1
All Others
—
Output Characteristics
Sequential Delays (TJ = 85 °C, VDD = min):
Local S/R (async) to PFU Out (LSR to Q[3:0])
LSR_DEL
Global S/R to PFU Out (GSRN to Q[3:0])
GSR_DEL
Clock to PFU Out (CK to Q[3:0])—Register
REG_DEL
Clock to PFU Out (CK to Q[3:0])—Latch
LTCH_DEL
Transparent Latch (WD[3:0] to Q[3:0])
LTCH_DDEL
2.5
2.5
2.5
2.5
—
—
—
—
2.0
2.0
2.0
2.0
—
—
—
—
1.8
1.8
1.8
1.8
—
—
—
—
1.7
1.7
1.7
1.7
—
—
—
—
1.6
1.6
1.6
1.6
—
—
—
—
ns
ns
ns
ns
1.7
—
1.3
—
1.1
—
1.0
—
0.9
—
ns
1.9
—
1.3
—
1.2
—
1.0
—
0.9
—
ns
2.9
1.2
2.9
1.2
3.6
1.2
0.1
1.2
1.4
1.5
0.0
—
—
—
—
—
—
—
—
—
—
—
2.3
0.9
2.2
0.6
3.0
0.9
0.1
1.0
1.3
1.4
0.0
—
—
—
—
—
—
—
—
—
—
—
2.1
0.8
2.0
0.5
2.7
0.8
0.0
0.9
1.2
1.3
0.0
—
—
—
—
—
—
—
—
—
—
—
1.6
0.7
1.7
0.5
2.1
0.7
0.1
0.9
1.1
1.2
0.0
—
—
—
—
—
—
—
—
—
—
—
1.5
0.6
1.6
0.5
2.0
0.6
0.1
0.6
0.8
1.0
0.0
—
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
0.4
0.4
0.0
0.0
1.4
0.0
—
—
—
—
—
—
0.4
0.0
0.0
0.0
1.0
0.0
—
—
—
—
—
—
0.4
0.0
0.0
0.0
0.9
0.0
—
—
—
—
—
—
0.3
0.0
0.0
0.0
0.8
0.0
—
—
—
—
—
—
0.3
0.0
0.0
0.0
0.8
0.0
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
—
—
—
—
—
3.4
2.3
2.0
2.0
2.7
—
—
—
—
—
3.1
2.0
1.9
1.9
2.5
—
—
—
—
—
2.5
1.6
1.5
1.5
2.0
—
—
—
—
—
2.0
1.3
1.3
1.3
2.0
—
—
—
—
—
1.6
1.2
1.0
1.0
1.8
ns
ns
ns
ns
ns
1.The input buffers contain a programmable delay to allow the hold time vs. the external clock pin to be equal to 0.
136
Lattice Semiconductor
Data Sheet
November 2006
ORCA Series 2 FPGAs
Timing Characteristics (continued)
Table 33B. OR2TxxB Sequential PFU Timing Characteristics
OR2TxxB Commercial: VDD = 3.0 V to 3.6 V, 0 °C ≤ TA ≤ 70 °C; OR2TxxB Industrial: VDD = 3.0 V to 3.6 V, –40 °C ≤ TA ≤
+85 °C.
SE
L
D E
IS C
C T
O D
N E
TI VI
N C
U E
ED S
Speed
Parameter
Input Requirements
Clock Low Time
Clock High Time
Global S/R Pulse Width (GSRN)
Local S/R Pulse Width
Combinatorial Setup Times (TJ = 85 °C,
VDD = min):
Four Input Variables to Clock
(A[4:0], B[4:0] to CK)
Five Input Variables to Clock
(A[4:0], B[4:0] to CK)
PFUMUX to Clock (A[4:0], B[4:0] to CK)
PFUMUX to Clock (C0 to CK)
PFUNAND to Clock (A[4:0], B[4:0] to CK)
PFUNAND to Clock (C0 to CK)
PFUXOR to Clock (A[4:0], B[4:0] to CK)
PFUXOR to Clock (C0 to CK)
Data In to Clock (WD[3:0] to CK)
Clock Enable to Clock (CE to CK)
Local Set/Reset (synchronous) (LSR to CK)
Data Select to Clock (SEL to CK)
Pad Direct In
Combinatorial Hold Times (TJ = all, VDD = all):
Data In (WD[3:0] from CK)
Clock Enable (CE from CK)
Local Set/Reset (synchronous) (LSR from CK)
Data Select (SEL from CK)
Pad Direct In Hold (DIA[3:0], DIB[3:0] to CK)1
All Others
Output Characteristics
Sequential Delays (TJ = 85 °C, VDD = min):
Local S/R (async) to PFU Out (LSR to Q[3:0])
Global S/R to PFU Out (GSRN to Q[3:0])
Clock to PFU Out (CK to Q[3:0])—Register
Clock to PFU Out (CK to Q[3:0])—Latch
Transparent Latch (WD[3:0] to Q[3:0])
Symbol
-7
-8
Unit
Min
Max
Min
Max
TCL
TCH
TRW
TPW
1.7
1.7
1.7
1.7
—
—
—
—
1.4
1.4
1.4
1.4
—
—
—
—
ns
ns
ns
ns
F4*_SET
1.0
—
0.8
—
ns
F5*_SET
1.0
—
0.8
—
ns
MUX_SET
C0MUX_SET
ND_SET
C0ND_SET
XOR_SET
C0XOR_SET
D*_SET
CKEN_SET
LSR_SET
SELECT_SET
PDIN_SET
1.3
1.1
1.0
0.8
1.3
1.1
0.2
1.0
1.0
1.0
0.0
—
—
—
—
—
—
—
—
—
—
—
1.3
0.8
0.8
0.7
1.3
0.8
0.1
0.8
0.8
0.8
0.0
—
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
D*_HLD
CKEN_HLD
LSR_HLD
SELECT_HLD
PDIN_HLD
—
0.0
0.0
0.0
0.0
0.1
0.0
—
—
—
—
—
—
0.0
0.0
0.0
0.0
0.1
0.0
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
LSR_DEL
GSR_DEL
REG_DEL
LTCH_DEL
LTCH_DDEL
2.2
1.4
1.0
1.0
1.7
—
—
—
—
—
1.8
1.0
1.0
1.0
1.4
—
—
—
—
—
ns
ns
ns
ns
ns
1.The input buffers contain a programmable delay to allow the hold time vs. the external clock pin to be equal to 0.
Lattice Semiconductor
137
Data Sheet
November 2006
ORCA Series 2 FPGAs
Timing Characteristics (continued)
Table 34A. OR2CxxA and OR2TxxA Ripple Mode PFU Timing Characteristics
OR2CxxA Commercial: VDD = 5.0 V ± 5%, 0 °C ≤ TA ≤ 70 °C; OR2CxxA Industrial: VDD = 5.0 V ± 10%, –40 °C ≤ TA ≤ +85 °C.
OR2TxxA Commercial: VDD = 3.0 V to 3.6 V, 0 °C ≤ TA ≤ 70 °C; OR2TxxA Industrial: VDD = 3.0 V to 3.6 V, –40 °C ≤ TA ≤ +85 °C.
SE
L
D E
IS C
C T
O D
N E
TI VI
N C
U E
ED S
Speed
Parameter
Ripple Setup Times
(TJ = +85 °C, VDD = min):
Operands to Clock (A[3:0], B[3:0] to CK)
Bitwise Operands to Clock
(A[i], B[i] to CK at F[i])
Carry-in from Fast Carry to Clock
(CIN to CK)
Carry-in from General Routing to Clock
(B4 to CK)
Add/Subtract to Clock (A4 to CK)
Ripple Hold Times (TJ = all, VDD = all): All
Ripple Delays (TJ = 85 °C, VDD = min):
Operands to Carry-out (A[3:0], B[3:0]
to COUT)
Operands to Carry-out (A[3:0], B[3:0]
to O4)
Operands to PFU Out (A[3:0], B[3:0]
to F[3:0])
Bitwise Operands to PFU Out (A[i], B[i]
to F[i])
Carry-in from Fast Carry to Carry-out
(CIN to COUT)
Carry-in from Fast Carry to Carry-out
(CIN to O4)
Carry-in from Fast Carry to PFU Out
(CIN to F[3:0])
Carry-in from General Routing to Carryout (B4 to COUT)
Carry-in from General Routing to Carryout (B4 to O4)
Carry-in from General Routing to PFU
Out (B4 to F[3:0])
Add/Subtract to Carry-out (A4 to COUT)
Add/Subtract to Carry-out (A4 to O4)
Add/Subtract to PFU Out (A4 to F[3:0])
Symbol
-3
-4
-5
-6
Unit
-7
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
RIP_SET
FRIP_SET
5.0
1.7
—
—
3.7
1.3
—
—
3.3
1.2
—
—
2.8
1.0
—
—
2.5
0.9
—
—
ns
ns
CIN_SET
3.2
—
1.9
—
1.7
—
1.4
—
1.3
—
ns
B4_SET
3.2
—
1.9
—
1.7
—
1.4
—
1.3
—
ns
AS_SET
5.6
—
4.3
—
3.9
—
3.2
—
3.1
—
ns
TH
0.0
—
0.0
—
0.0
—
0.0
—
0.0
—
ns
RIP_CODEL
—
3.8
—
3.3
—
2.6
—
2.1
—
1.8
ns
RIP_O4DEL
—
4.8
—
4.2
—
3.4
—
2.6
—
2.4
ns
RIP_DEL
—
6.0
—
4.7
—
3.8
—
3.2
—
2.8
ns
FRIP_DEL
—
2.8
—
2.1
—
1.7
—
1.6
—
1.5
ns
CIN_CODEL
—
1.6
—
1.1
—
0.9
—
0.7
—
0.6
ns
CIN_O4DEL
—
2.6
—
2.1
—
1.7
—
1.3
—
1.1
ns
CIN_DEL
—
4.2
—
2.9
—
2.3
—
2.2
—
1.7
ns
B4_CODEL
—
1.6
—
1.1
—
0.9
—
0.7
—
0.6
ns
B4_O4DEL
—
2.6
—
2.1
—
1.7
—
1.3
—
1.1
ns
B4_DEL
—
4.2
—
2.9
—
2.3
—
2.2
—
2.1
ns
AS_CODEL
AS_O4DEL
AS_DEL
—
—
—
4.5
5.6
6.8
—
—
—
3.9
4.9
5.3
—
—
—
3.1
3.9
4.3
—
—
—
2.5
3.1
3.5
—
—
—
2.3
2.8
3.1
ns
ns
ns
Notes:
The new 4 x 1 multiplier and 4-bit comparator submodes use the appropriate ripple mode timing shown above.
138
Lattice Semiconductor
Data Sheet
November 2006
ORCA Series 2 FPGAs
Timing Characteristics (continued)
Table 34B. OR2TxxB Ripple Mode PFU Timing Characteristics
OR2TxxB Commercial: VDD = 3.0 V to 3.6 V, 0 °C ≤ TA ≤ 70 °C; OR2TxxB Industrial: VDD = 3.0 V to 3.6 V, –40 °C ≤ TA ≤
+85 °C.
SE
L
D E
IS C
C T
O D
N E
TI VI
N C
U E
ED S
Speed
Parameter
Ripple Setup Times
(TJ = 85 °C, VDD = min):
Operands to Clock (A[3:0], B[3:0] to CK)
Bitwise Operands to Clock
(A[i], B[i] to CK at F[i])
Carry-in from Fast Carry to Clock
(CIN to CK)
Carry-in from General Routing to Clock
(B4 to CK)
Add/Subtract to Clock (A4 to CK)
Ripple Hold Times (TJ = all, VDD = all): All
Ripple Delays (TJ = 85 °C, VDD = min):
Operands to Carry-out (A[3:0], B[3:0]
to COUT)
Operands to Carry-out (A[3:0], B[3:0]
to O4)
Operands to PFU Out (A[3:0], B[3:0]
to F[3:0])
Bitwise Operands to PFU Out (A[i], B[i]
to F[i])
Carry-in from Fast Carry to Carry-out
(CIN to COUT)
Carry-in from Fast Carry to Carry-out
(CIN to O4)
Carry-in from Fast Carry to PFU Out
(CIN to F[3:0])
Carry-in from General Routing to Carryout (B4 to COUT)
Carry-in from General Routing to Carryout (B4 to O4)
Carry-in from General Routing to PFU
Out (B4 to F[3:0])
Add/Subtract to Carry-out (A4 to COUT)
Add/Subtract to Carry-out (A4 to O4)
Add/Subtract to PFU Out (A4 to F[3:0])
Symbol
-7
-8
Unit
Min
Max
Min
Max
RIP_SET
FRIP_SET
2.4
1.1
—
—
1.9
0.9
—
—
ns
ns
CIN_SET
1.6
—
1.3
—
ns
B4_SET
1.0
—
0.8
—
ns
AS_SET
2.9
—
2.3
—
ns
TH
ns
RIP_CODEL
2.2
—
1.8
—
ns
RIP_O4DEL
3.0
—
2.4
—
ns
RIP_DEL
3.1
—
2.5
—
ns
FRIP_DEL
1.4
—
1.1
—
ns
CIN_CODEL
0.7
—
0.6
—
ns
CIN_O4DEL
1.4
—
1.2
—
ns
CIN_DEL
1.9
—
1.5
—
ns
B4_CODEL
0.7
—
0.6
—
ns
B4_O4DEL
1.4
—
1.2
—
ns
B4_DEL
1.9
—
1.5
—
ns
AS_CODEL
AS_O4DEL
AS_DEL
2.7
3.4
3.6
—
—
—
2.2
2.8
2.9
—
—
—
ns
ns
ns
Notes: The new 4 x 1 multiplier and 4-bit comparator submodes use the appropriate ripple mode timing shown above.
Lattice Semiconductor
139
Data Sheet
November 2006
ORCA Series 2 FPGAs
Timing Characteristics (continued)
Table 35A. OR2CxxA and OR2TxxA Asynchronous Memory Read Characteristics (MA/MB Modes)
OR2CxxA Commercial: VDD = 5.0 V ± 5%, 0 °C ≤ TA ≤ 70 °C; OR2CxxA Industrial: VDD = 5.0 V ± 10%, –40 °C ≤ TA ≤ +85 °C.
OR2TxxA Commercial: VDD = 3.0 V to 3.6 V, 0 °C ≤ TA ≤ 70 °C; OR2TxxA Industrial: VDD = 3.0 V to 3.6 V, –40 °C ≤ TA ≤ +85 °C.
SE
L
D E
IS C
C T
O D
N E
TI VI
N C
U E
ED S
Speed
Parameter
Symbol
-3
-4
-5
-6
Unit
-7
Min Max Min Max Min Max Min Max Min Max
Read Operation (TJ = 85 °C, VDD = min):
Read Cycle Time
Data Valid after Address (A[3:0], B[3:0] to F[3:0])
TRC
3.6
MEM*_ADEL —
—
2.8
2.7
—
—
2.1
2.4
—
—
1.7
2.3
—
—
1.4
2.0
—
—
1.3
ns
ns
Read Operation, Clocking Data into Latch/Flip-flop
(TJ = 85 °C, VDD = min):
Address to Clock Setup Time (A[3:0], B[3:0] to CK)
Clock to PFU Out (CK to Q[3:0])—Register
MEM*_ASET 1.8
REG_DEL
—
—
2.0
1.2
—
—
1.9
1.1
—
—
1.5
1.0
—
—
1.3
1.0
—
—
1.0
ns
ns
Table 35B. OR2TxxB Asynchronous Memory Read Characteristics (MA/MB Modes)
OR2TxxB Commercial: VDD = 3.0 V to 3.6 V, 0 °C ≤ TA ≤ 70 °C; OR2TxxB Industrial: VDD = 3.0 V to 3.6 V, –40 °C ≤ TA ≤ +85 °C.
Speed
Parameter
Symbol
Read Operation (TJ = 85 °C, VDD = min):
Read Cycle Time
Data Valid after Address (A[3:0], B[3:0] to F[3:0])
Read Operation, Clocking Data into Latch/Flip-flop
(TJ = 85 °C, VDD = min):
Address to Clock Setup Time (A[3:0], B[3:0] to CK)
Clock to PFU Out (CK to Q[3:0])—Register
-7
Unit
-8
Min
Max
Min
Max
TRC
MEM*_ADEL
1.9
—
—
1.3
1.8
—
—
1.0
ns
ns
MEM*_ASET
REG_DEL
0.9
—
—
1.0
0.8
—
—
1.0
ns
ns
TRC
A[3:0], B[3:0]
MEM*_ADEL
F[3:0]
5-3226(F).r4
Figure 55. Read Operation—Flip-Flop Bypass
A[3:0], B[3:0]
MEM*_ASET
CK
REG_DEL
Q[3:0]
5-3227(F).r4
Figure 56. Read Operation—LUT Memory Loading Flip-Flops
140
Lattice Semiconductor
Data Sheet
November 2006
ORCA Series 2 FPGAs
Timing Characteristics (continued)
Table 36A. OR2CxxA and OR2TxxA Asynchronous Memory Write Characteristics (MA/MB Modes)
SE
L
D E
IS C
C T
O D
N E
TI VI
N C
U E
ED S
OR2CxxA Commercial: VDD = 5.0 V ± 5%, 0 °C ≤ TA ≤ 70 °C; OR2CxxA Industrial: VDD = 5.0 V ± 10%, –40 °C ≤ TA ≤ +85 °C.
OR2TxxA Commercial: VDD = 3.0 V to 3.6 V, 0 °C ≤ TA ≤ 70 °C; OR2TxxA Industrial: VDD = 3.0 V to 3.6 V, –40 °C ≤ TA ≤
+85 °C.
Speed
Parameter
Symbol
-3
-4
-5
-6
Unit
-7
Min Max Min Max Min Max Min Max Min Max
Write Operation (TJ = 85 °C, VDD = min):
Write Cycle Time
Write Enable (WREN) Pulse Width (A4/B4)
TWC
TPW
7.8
2.5
—
—
6.3
2.0
—
—
5.7
1.8
—
—
5.2
1.7
—
—
5.1
1.6
—
—
ns
ns
Setup Time (TJ = 85 °C, VDD = min):
Address to WREN (A[3:0]/B[3:0] to A4/B4)
Data to WREN (WD[3:0] to A4/B4)
Address to WPE (A[3:0]/B[3:0] to C0)
Data to WPE (WD[3:0] to C0)
WPE to WREN (C0 to A4/B4)
MEM*_AWRSET
MEM*_DWRSET
MEM*_APWRSET
MEM*_DPWRSET
MEM*_WPESET
0.1
0.0
0.0
0.0
2.0
—
—
—
—
—
0.0
0.0
0.0
0.0
1.5
—
—
—
—
—
0.0
0.0
0.0
0.0
1.4
—
—
—
—
—
0.0
0.0
0.0
0.0
1.1
—
—
—
—
—
0.0
0.0
0.0
0.0
1.1
—
—
—
—
—
ns
ns
ns
ns
ns
Hold Time (TJ = all, VDD = all):
Address from WREN (A[3:0]/B[3:0] from A4/B4)
Data from WREN (WD[3:0] from A4/B4)
Address from WPE (A[3:0/B[3:0] to C0)
Data from WPE (WD[3:0] to C0)
WPE from WREN (C0 from A4/B4)
MEM*_WRAHLD
MEM*_WRDHLD
MEM*_PWRAHLD
MEM*_PWRDHLD
MEM*_WPEHLD
1.7
2.0
3.3
3.4
0.0
—
—
—
—
—
1.8
1.9
2.8
2.9
0.0
—
—
—
—
—
1.6
1.5
2.5
2.6
0.0
—
—
—
—
—
1.6
1.6
2.4
2.4
0.0
—
—
—
—
—
1.5
1.6
2.3
2.3
0.0
—
—
—
—
—
ns
ns
ns
ns
ns
Table 36B. OR2TxxB Asynchronous Memory Write Characteristics (MA/MB Modes)
OR2TxxB Commercial: VDD = 3.0 V to 3.6 V, 0 °C ≤ TA ≤ 70 °C; OR2TxxB Industrial: VDD = 3.0 V to 3.6 V, –40 °C ≤ TA ≤
+85 °C.
Speed
Parameter
Symbol
-7
-8
Unit
Min
Max
Min
Max
TWC
TPW
5.1
1.7
—
—
4.2
1.4
—
—
ns
ns
Setup Time (TJ = 85 °C, VDD = min):
Address to WREN (A[3:0]/B[3:0] to A4/B4)
Data to WREN (WD[3:0] to A4/B4)
Address to WPE (A[3:0]/B[3:0] to C0)
Data to WPE (WD[3:0] to C0)
WPE to WREN (C0 to A4/B4)
MEM*_AWRSET
MEM*_DWRSET
MEM*_APWRSET
MEM*_DPWRSET
MEM*_WPESET
0.0
0.0
0.0
0.0
1.0
—
—
—
—
—
0.0
0.0
0.0
0.0
0.8
—
—
—
—
—
ns
ns
ns
ns
ns
Hold Time (TJ = all, VDD = all):
Address from WREN (A[3:0]/B[3:0] from A4/B4)
Data from WREN (WD[3:0] from A4/B4)
Address from WPE (A[3:0/B[3:0] to C0)
Data from WPE (WD[3:0] to C0)
WPE from WREN (C0 from A4/B4)
MEM*_WRAHLD
MEM*_WRDHLD
MEM*_PWRAHLD
MEM*_PWRDHLD
MEM*_WPEHLD
0.9
1.6
2.3
2.3
0.0
—
—
—
—
—
0.7
1.3
1.9
1.9
0.0
—
—
—
—
—
ns
ns
ns
ns
ns
Write Operation (TJ = 85 °C, VDD = min):
Write Cycle Time
Write Enable (WREN) Pulse Width (A4/B4)
Lattice Semiconductor
141
Data Sheet
November 2006
ORCA Series 2 FPGAs
Timing Characteristics (continued)
TWC
A[3:0], B[3:0]
MEM*_PWRAHLD
SE
L
D E
IS C
C T
O D
N E
TI VI
N C
U E
ED S
MEM*_APWRSET
C0 (WPE)
MEM*_WPESET
TPW
MEM*_WPEHLD
A4, B4 (WREN)
MEM*_AWRSET
MEM*_WRAHLD
MEM*_DPWRSET
MEM*_PWRDHLD
MEM*_DWRSET
MEM*_WRDHLD
WD[3:0]
5-3228(F).r6
Figure 57. Write Operation
142
Lattice Semiconductor
Data Sheet
November 2006
ORCA Series 2 FPGAs
Timing Characteristics (continued)
Table 37A. OR2CxxA and OR2TxxA Asynchronous Memory Read During Write Operation (MA/MB Modes)
SE
L
D E
IS C
C T
O D
N E
TI VI
N C
U E
ED S
OR2CxxA Commercial: VDD = 5.0 V ± 5%, 0 °C ≤ TA ≤ 70 °C; OR2CxxA Industrial: VDD = 5.0 V ± 10%, –40 °C ≤ TA ≤ +85 °C.
OR2TxxA Commercial: VDD = 3.0 V to 3.6 V, 0 °C ≤ TA ≤ 70 °C; OR2TxxA Industrial: VDD = 3.0 V to 3.6 V, –40 °C ≤ TA ≤
+85 °C.
Speed
Parameter
Symbol
-3
-4
-5
-6
Unit
-7
Min Max Min Max Min Max Min Max Min Max
Read During Write Operation
(TJ = 85 °C, VDD = min):
Write Enable (WREN) to PFU Output Delay
MEM*_WRDEL
(A4/B4 to F[3:0])
Write-port Enable (WPE) to PFU Output
MEM*_PWRDEL
Delay (C0 to F[3:0])
Data to PFU Output Delay (WD[3:0] to F[3:0]) MEM*_DDEL
—
4.9
—
4.8
—
3.9
—
4.0
—
3.9
ns
—
6.4
—
5.8
—
4.7
—
4.7
—
4.5
ns
—
3.6
—
3.1
—
2.5
—
2.5
—
2.2
ns
Table 37B. OR2TxxB Asynchronous Memory Read During Write Operation (MA/MB Modes)
OR2TxxB Commercial: VDD = 3.0 V to 3.6 V, 0 °C ≤ TA ≤ 70 °C; OR2TxxB Industrial: VDD = 3.0 V to 3.6 V, –40 °C ≤ TA ≤
+85 °C.
Speed
Parameter
Read During Write Operation
(TJ = +85 °C, VDD = min):
Write Enable (WREN) to PFU Output Delay
(A4/B4 to F[3:0])
Write-port Enable (WPE) to PFU Output
Delay (C0 to F[3:0])
Data to PFU Output Delay (WD[3:0] to F[3:0])
Lattice Semiconductor
Symbol
-7
Unit
-8
Min
Max
Min
Max
MEM*_WRDEL
—
4.5
—
3.9
ns
MEM*_PWRDEL
—
4.6
—
4.0
ns
MEM*_DDEL
—
2.7
—
2.4
ns
143
Data Sheet
November 2006
ORCA Series 2 FPGAs
Timing Characteristics (continued)
A[3:0], B[3:0]
SE
L
D E
IS C
C T
O D
N E
TI VI
N C
U E
ED S
CO (WPE)
TPW
A4, B4 (WREN)
DATA STABLE
DURING
WREN AND WPE
WD[3:0]
MEM*_PWRDEL
MEM*_WRDEL
F[3:0]
WD[3:0]
DATA CHANGING
DURING
WREN AND WPE
MEM*_PWRDEL
MEM*_DDEL
MEM*_WRDEL
F[3:0]
5-3229(F).r6
Figure 58. Read During Write
144
Lattice Semiconductor
Data Sheet
November 2006
ORCA Series 2 FPGAs
Timing Characteristics (continued)
Table 38A. OR2CxxA and OR2TxxA Asynchronous Memory Read During Write, Clocking Data into Latch/
Flip-Flop (MA/MB Modes)
SE
L
D E
IS C
C T
O D
N E
TI VI
N C
U E
ED S
OR2CxxA Commercial: VDD = 5.0 V ± 5%, 0 °C ≤ TA ≤ 70 °C; OR2CxxA Industrial: VDD = 5.0 V ± 10%, –40 °C ≤ TA ≤ +85 °C.
OR2TxxA Commercial: VDD = 3.0 V to 3.6 V, 0 °C ≤ TA ≤ 70 °C; OR2TxxA Industrial: VDD = 3.0 V to 3.6 V, –40 °C ≤ TA ≤
+85 °C.
Speed
Parameter
Symbol
-3
-4
-5
-6
Unit
-7
Min Max Min Max Min Max Min Max Min Max
Setup Time (TJ = 85 °C, VDD = min):
Address to Clock (A[3:0], B[3:0] to CK)
Write Enable (WREN) to Clock (A4/B4 to CK)
Write-port Enable (WPE) to Clock (C0 to CK)
Data (WD[3:0] to CK)
MEM*_ASET
MEM*_WRSET
MEM*_PWRSET
MEM*_DSET
1.8
4.4
5.9
2.6
TH
REG_DEL
Hold Time (TJ = All, VDD = All): All
Clock to PFU Out (CK to Q[3:0])—Register
—
—
—
—
1.2
3.8
4.8
2.6
—
—
—
—
1.1
3.4
4.3
2.3
0.0
—
—
2.0
—
—
—
—
1.0
3.1
4.0
2.2
0.0
—
—
1.9
—
—
—
—
1.0
3.0
3.9
2.1
0.0
—
—
1.5
—
—
—
—
ns
ns
ns
ns
0.0
—
—
1.3
0.0
—
ns
—
1.0
ns
Table 38B. OR2TxxB Asynchronous Memory Read During Write, Clocking Data into Latch/Flip-Flop
(MA/MB Modes)
OR2TxxB Commercial: VDD = 3.0 V to 3.6 V, 0 °C ≤ TA ≤ 70 °C; OR2TxxB Industrial: VDD = 3.0 V to 3.6 V, –40 °C ≤ TA ≤
+85 °C.
Speed
Parameter
Setup Time (TJ = 85 °C, VDD = min):
Address to Clock (A[3:0], B[3:0] to CK)
Write Enable (WREN) to Clock (A4/B4 to CK)
Write-port Enable (WPE) to Clock (C0 to CK)
Data (WD[3:0] to CK)
Hold Time (TJ = all, VDD = all): All
Clock to PFU Out (CK to Q[3:0])—Register
Lattice Semiconductor
Symbol
-7
Unit
-8
Min
Max
Min
Max
MEM*_ASET
MEM*_WRSET
MEM*_PWRSET
MEM*_DSET
0.9
2.9
3.7
2.0
—
—
—
—
0.8
2.5
3.2
1.7
—
—
—
—
TH
0.0
—
0.0
—
ns
REG_DEL
—
1.0
—
1.0
ns
ns
ns
ns
ns
145
Data Sheet
November 2006
ORCA Series 2 FPGAs
Timing Characteristics (continued)
A[3:0], B[3:0]
MEM*_ASET
SE
L
D E
IS C
C T
O D
N E
TI VI
N C
U E
ED S
MEM*_PWRSET
C0 (WPE)
TPW
A4, B4 (WREN)
MEM*_WRSET
WD[3:0]
MEM*_DSET
CK
REG_DEL
Q[3:0]
5-3230(F).r6
Figure 59. Read During Write—Clocking Data into Flip-Flop
146
Lattice Semiconductor
Data Sheet
November 2006
ORCA Series 2 FPGAs
Timing Characteristics (continued)
Table 39A. OR2CxxA and OR2TxxA Synchronous Memory Write Characteristics (SSPM and SDPM Modes)
SE
L
D E
IS C
C T
O D
N E
TI VI
N C
U E
ED S
OR2CxxA Commercial: VDD = 5.0 V ± 5%, 0 °C ≤ TA ≤ 70 °C; OR2CxxA Industrial: VDD = 5.0 V ± 10%, –40 °C ≤ TA ≤ +85 °C.
OR2TxxA Commercial: VDD = 3.0 V to 3.6 V, 0 °C ≤ TA ≤ 70 °C; OR2TxxA Industrial: VDD = 3.0 V to 3.6 V, –40 °C ≤ TA ≤
+85 °C.
Speed
Parameter
Symbol
-3
-4
-5
-6
Unit
-7
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
FFSCK
TFSCL
TFSCH
FMEMS_DEL
52.6
9.5
9.5
—
—
—
—
7.4
83.3
6.0
6.0
—
—
—
—
6.2
90.9
5.5
5.5
—
—
—
—
5.0
92.6
5.4
5.4
—
—
—
—
5.3
96.2
5.2
5.2
—
—
—
—
5.2
MHz
ns
ns
ns
FSCK
TSCL
TSCH
MEMS_DEL
33.3
15.0
15.0
—
—
—
—
8.6
52.6
9.5
9.5
—
—
—
—
7.5
58.0
8.5
8.5
—
—
—
—
6.0
58.8
8.5
8.5
—
—
—
—
6.4
59.8
8.4
8.4
—
—
—
—
5.9
MHz
ns
ns
ns
0.0
0.0
0.0
—
—
—
0.0
0.0
0.0
—
—
—
0.0
0.0
0.0
—
—
—
0.0
0.0
0.0
—
—
—
0.0
0.0
0.0
—
—
—
ns
ns
ns
0.0
—
0.0
—
0.0
—
0.0
—
0.0
—
ns
MEMS_AHLD
MEMS_DHLD
MEMS_WRHLD
3.0
3.0
3.0
—
—
—
2.2
2.2
2.2
—
—
—
2.0
2.0
2.0
—
—
—
1.9
1.9
1.9
—
—
—
1.8
1.8
1.8
—
—
—
ns
ns
ns
MEMS_PWRHL
D
2.3
—
1.5
—
1.4
—
1.9
—
1.2
—
ns
1:
Write Operation for Fast-RAM Mode
Maximum Frequency
Clock Low Time
Clock High Time
Clock to Data Valid (CK to F[3:0])2
Write Operation for Normal RAM Mode:
Maximum Frequency
Clock Low Time
Clock High Time
Clock to Data Valid (CK to F[3:0])
Write Operation Setup Time:
Address to Clock (A[3:0]/B[3:0] to CK)
MEMS_ASET
MEMS_DSET
Data to Clock (WD[3:0] to CK)
Write Enable (WREN) to Clock
MEMS_WRSET
(A4 to CK)
Write-port Enable (WPE) to Clock
MEMS_PWRSET
(C0 to CK)
Write Operation Hold Time:
Address to Clock (A[3:0]/B[3:0] to CK)
Data to Clock (WD[3:0] to CK)
Write Enable (WREN) to Clock
(A4 to CK)
Write-port Enable (WPE) to Clock
(C0 to CK)
1. Readback of the configuration bit stream when simultaneously writing to a PFU in either SSPM fast mode or SDPM fast mode is not allowed.
2. Because the setup time of data into the latches/FFs is less than 0 ns, data written into the RAM can be loaded into a latch/FF in the same
PFU on the next opposite clock edge (one-half clock period).
Table 39.B OR2TxxB Synchronous Memory Write Characteristics (SSPM and SDPM Modes)
OR2TxxB Commercial: VDD = 3.0 V to 3.6 V, 0 °C ≤ TA ≤ 70 °C; OR2TxxB Industrial: VDD = 3.0 V to 3.6 V, –40 °C ≤ TA ≤ +85 °C.
Speed
Parameter
Write Operation for Fast-RAM Mode1:
Maximum Frequency
Clock Low Time
Clock High Time
Clock to Data Valid (CK to F[3:0])2
Write Operation for Normal RAM Mode:
Maximum Frequency
Clock Low Time
Clock High Time
Clock to Data Valid (CK to F[3:0])
Lattice Semiconductor
Symbol
-7
Unit
-8
Min
Max
Min
Max
FFSCK
TFSCL
TFSCH
FMEMS_DEL
97.7
5.1
5.1
—
—
—
—
5.1
112.4
4.5
4.5
—
—
—
—
4.5
MHz
ns
ns
ns
FSCK
TSCL
TSCH
MEMS_DEL
60.8
8.2
8.2
—
—
—
—
5.1
69.9
7.2
7.2
—
—
—
—
4.5
MHz
ns
ns
ns
147
Data Sheet
November 2006
ORCA Series 2 FPGAs
Timing Characteristics (continued)
Table 39.B OR2TxxB Synchronous Memory Write Characteristics (SSPM and SDPM Modes) (continued)
OR2TxxB Commercial: VDD = 3.0 V to 3.6 V, 0 °C ≤ TA ≤ 70 °C; OR2TxxB Industrial: VDD = 3.0 V to 3.6 V, –40 °C ≤ TA ≤ +85 °C.
Speed
Symbol
-7
Unit
-8
SE
L
D E
IS C
C T
O D
N E
TI VI
N C
U E
ED S
Parameter
Write Operation Setup Time:
Address to Clock (A[3:0]/B[3:0] to CK)
Data to Clock (WD[3:0] to CK)
Write Enable (WREN) to Clock
(A4 to CK)
Write-port Enable (WPE) to Clock
(C0 to CK)
Write Operation Hold Time:
Address to Clock (A[3:0]/B[3:0] to CK)
Data to Clock (WD[3:0] to CK)
Write Enable (WREN) to Clock
(A4 to CK)
Write-port Enable (WPE) to Clock
(C0 to CK)
Min
Max
Min
Max
MEMS_ASET
MEMS_DSET
MEMS_WRSET
0.0
0.0
0.0
—
—
—
0.0
0.0
0.0
—
—
—
ns
ns
ns
MEMS_PWRSET
0.0
—
0.0
—
ns
MEMS_AHLD
MEMS_DHLD
MEMS_WRHLD
1.0
1.0
1.0
—
—
—
0.8
0.8
0.8
—
—
—
ns
ns
ns
MEMS_PWRHLD
0.7
—
0.6
—
ns
1. Readback of the configuration bit stream when simultaneously writing to a PFU in either SSPM fast mode or SDPM fast mode is not allowed.
2. Because the setup time of data into the latches/FFs is less than 0 ns, data written into the RAM can be loaded into a latch/FF in the same
PFU on the next opposite clock edge (one-half clock period).
MEMS_ASET
MEMS_AHLD
MEMS_DSET
MEMS_DHLD
A[3:0], B[3:0]
WD[3:0]
MEMS_WRSET
MEMS_WRHLD
A4 (WREN)
MEMS_PWRSET
MEMS_PWRHLD
C0 (WPE)
TFSCH/TSCH
TFSCL/TSCL
CK
FMEMS_DEL/MEMS_DEL
F[3:0]
5-4621(F).a
Figure 60. Synchronous Memory Write Characteristics
148
Lattice Semiconductor
Data Sheet
November 2006
ORCA Series 2 FPGAs
Timing Characteristics (continued)
Table 40A. OR2CxxA and OR2TxxA Synchronous Memory Read Characteristics (SSPM and SDPM Modes)
OR2CxxA Commercial: VDD = 5.0 V ± 5%, 0 °C ≤ TA ≤ 70 °C; OR2CxxA Industrial: VDD = 5.0 V ± 10%, –40 °C ≤ TA ≤ +85 °C.
OR2TxxA Commercial: VDD = 3.0 V to 3.6 V, 0 °C ≤ TA ≤ 70 °C; OR2TxxA Industrial: VDD = 3.0 V to 3.6 V, –40 °C ≤ TA ≤
+85 °C.
SE
L
D E
IS C
C T
O D
N E
TI VI
N C
U E
ED S
Speed
Parameter
Read Operation (TJ = 85 °C, VDD = min):
Read Cycle Time
Data Valid After Address
(A[3:0], B[3:0] to F[3:0])
Read Operation, Clocking Data Into
Latch/FF (TJ = 85 °C, VDD = min):
Address to Clock Setup Time
(A[3:0], B[3:0] to CK)
Clock to PFU Output—Register
(CK to Q[3:0])
Symbol
-3
-4
-5
-6
Unit
-7
Min
Max Min Max Min Max Min Max Min Max
TRC
MEMS*_ADEL
3.6
—
—
2.8
2.7
—
—
2.1
2.4
—
—
1.7
2.3
—
—
1.4
2.0
—
—
1.1
ns
ns
MEMS*_ASET
1.8
—
1.2
—
1.1
—
1.0
—
0.9
—
ns
REG_DEL
—
2.0
—
1.9
—
1.5
—
1.3
—
1.0
ns
Table 40B. OR2TxxB Synchronous Memory Read Characteristics (SSPM and SDPM Modes)
OR2TxxB Commercial: VDD = 3.0 V to 3.6 V, 0 °C ≤ TA ≤ 70 °C; OR2TxxB Industrial: VDD = 3.0 V to 3.6 V, –40 °C ≤ TA ≤
+85 °C.
Speed
Parameter
Read Operation (TJ = 85 °C, VDD = min):
Read Cycle Time
Data Valid After Address
(A[3:0], B[3:0] to F[3:0])
Read Operation, Clocking Data into
Latch/FF (TJ = 85 °C, VDD = Min):
Address to Clock Setup Time
(A[3:0], B[3:0] to CK)
Clock to PFU Output—Register
(CK to Q[3:0])
Symbol
-7
-8
Unit
Min
Max
Min
Max
TRC
MEMS*_ADEL
1.9
—
—
1.8
1.8
—
—
1.4
ns
ns
MEMS*_ASET
0.9
—
0.8
—
ns
REG_DEL
—
1.0
—
1.0
ns
A[3:0], B[3:0]
MEM*_ADEL
F[3:0]
MEM*_ASET
CK
REG_DEL
Q[3:0]
5-4622(F).r2.a
Figure 61. Synchronous Memory Read Cycle
Lattice Semiconductor
149
Data Sheet
November 2006
ORCA Series 2 FPGAs
Timing Characteristics (continued)
Table 41A. OR2CxxA and OR2TxxA PFU Output MUX, PLC BIDI, and Direct Routing Timing Characteristics
OR2CxxA Commercial: VDD = 5.0 V ± 5%, 0 °C ≤ TA ≤ 70 °C; OR2CxxA Industrial: VDD = 5.0 V ± 10%, –40 °C ≤ TA ≤ +85 °C.
OR2TxxA Commercial: VDD = 3.0 V to 3.6 V, 0 °C ≤ TA ≤ 70 °C; OR2TxxA Industrial: VDD = 3.0 V to 3.6 V, –40 °C ≤ TA ≤ +85 °C.
SE
L
D E
IS C
C T
O D
N E
TI VI
N C
U E
ED S
Speed
Parameter
Symbol
-3
-4
-5
-6
Unit
-7
Min Max Min Max Min Max Min Max Min Max
PFU Output MUX (TJ = 85 °C, VDD = min)
Output MUX Delay (F[3:0]/Q[3:0] to O[4:0]) OMUX_DEL
PLC 3-Statable BIDIs (TJ = 85 °C, VDD = min)
BIDI Propagation Delay
TRI_DEL
BIDI 3-state Enable/Disable Delay
TRIEN_DEL
Direct Routing (TJ = 85 °C, VDD = min)
PFU to PFU Delay (xSW)
DIR_DEL
PFU Feedback (xSW)
FDBK_DEL
—
0.8
—
0.6
—
0.5
—
0.4
—
0.4
ns
—
—
1.0
1.3
—
—
0.8
1.0
—
—
0.7
0.8
—
—
0.6
0.8
—
—
0.5
0.7
ns
ns
—
—
1.1
0.8
—
—
0.9
0.7
—
—
0.7
0.6
—
—
0.6
0.5
—
—
0.6
0.5
ns
ns
Table 41B. OR2TxxB PFU Output MUX, PLC BIDI, and Direct Routing Timing Characteristics
OR2TxxB Commercial: VDD = 3.0 V to 3.6 V, 0 °C ≤ TA ≤ 70 °C; OR2TxxA Industrial: VDD = 3.0 V to 3.6 V, –40 °C ≤ TA ≤
+85 °C.
Speed
Parameter
PFU Output MUX (TJ = 85 °C, VDD = min)
Output MUX Delay (F[3:0]/Q[3:0] to O[4:0])
PLC 3-Statable BIDIs (TJ = 85 °C, VDD = min)
BIDI Propagation Delay
BIDI 3-state Enable/Disable Delay
Direct Routing (TJ = 85 °C, VDD = min)
PFU to PFU Delay (xSW)
PFU Feedback (xSW)
150
Symbol
-7
Unit
-8
Min
Max
Min
Max
OMUX_DEL
—
0.4
—
0.4
ns
TRI_DEL
TRIEN_DEL
—
—
0.7
1.1
—
—
0.6
0.9
ns
ns
DIR_DEL
FDBK_DEL
—
—
0.6
0.4
—
—
0.5
0.4
ns
ns
Lattice Semiconductor
Data Sheet
November 2006
ORCA Series 2 FPGAs
Timing Characteristics (continued)
Table 42A. OR2CxxA and OR2TxxA Internal Clock Delay
SE
L
D E
IS C
C T
O D
N E
TI VI
N C
U E
ED S
OR2CxxA Commercial: VDD = 5.0 V ± 5%, 0 °C ≤ TA ≤ 70 °C; OR2CxxA Industrial: VDD = 5.0 V ± 10%, –40 °C ≤ TA ≤ +85 °C.
OR2TxxA Commercial: VDD = 3.0 V to 3.6 V, 0 °C ≤ TA ≤ 70 °C; OR2TxxA Industrial: VDD = 3.0 V to 3.6 V, –40 °C ≤ TA ≤
+85 °C.
Speed
Device
(TJ = 85 °C, VDD = min)
Symbol
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
OR2C04A/OR2T04A
CLK_DEL
—
4.4
—
4.3
—
3.6
—
—
—
—
ns
-3
-4
-5
-6
Unit
-7
OR2C06A
CLK_DEL
—
4.5
—
4.4
—
3.7
—
—
—
—
ns
OR2C08A/OR2T08A
CLK_DEL
—
4.6
—
4.5
—
3.8
—
—
—
—
ns
OR2C10A/OR2T10A
CLK_DEL
—
4.7
—
4.6
—
3.9
—
—
—
—
ns
OR2C12A
CLK_DEL
—
4.8
—
4.7
—
4.0
—
—
—
—
ns
OR2C15A/OR2T15A
CLK_DEL
—
4.9
—
4.8
—
4.1
—
3.9
—
3.3
ns
OR2C26A/OR2T26A
CLK_DEL
—
5.1
—
5.0
—
4.2
—
4.0
—
3.4
ns
OR2C40A/OR2T40A
CLK_DEL
—
5.4
—
5.3
—
4.5
—
4.2
—
3.6
ns
Notes:
This clock delay is for a fully routed clock tree that uses the primary clock network. It includes both the input buffer delay and the clock routing
to the PFU CLK input. The delay will be reduced if any of the clock branches are not used.
Table 42B. OR2TxxB Internal Clock Delay
OR2TxxB Commercial: VDD = 3.0 V to 3.6 V, 0 °C ≤ TA ≤ 70 °C; OR2TxxB Industrial: VDD = 3.0 V to 3.6 V, –40 °C ≤ TA ≤
+85 °C.
Speed
Device
(TJ = 85 °C, VDD = min)
Symbol
OR2T15B
OR2T40B
-7
-8
Unit
Min
Max
Min
Max
CLK_DEL
—
3.6
—
3.1
ns
CLK_DEL
—
3.8
—
3.3
ns
Note: This clock delay is for a fully routed clock tree that uses the primary clock network. It includes both the input buffer delay and the clock
routing to the PFU CLK input. The delay will be reduced if any of the clock branches are not used.
Lattice Semiconductor
151
Data Sheet
November 2006
ORCA Series 2 FPGAs
Timing Characteristics (continued)
Table 43A. OR2CxxA and OR2TxxA OR2CxxA/OR2TxxA Global Clock to Output Delay (Pin-to-Pin)—Output
on Same Side of the Device as the Clock Pin
SE
L
D E
IS C
C T
O D
N E
TI VI
N C
U E
ED S
OR2CxxA Commercial: VDD = 5.0 V ± 5%, 0 °C ≤ TA ≤ 70 °C; Industrial: VDD = 5.0 V ± 10%, –40 °C ≤ TA ≤ +85 °C; CL = 50 pF.
OR2TxxA Commercial: VDD = 3.0 V to 3.6 V, 0 °C ≤ TA ≤ 70 °C; Industrial: VDD = 3.0 V to 3.6 V, –40 °C ≤ TA ≤ +85 °C; CL =
50 pF.
Description
(TJ = 85 °C, VDD = min)
Speed
Device
-3
-4
-5
-6
Unit
-7
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
CLK Input Pin → OUTPUT Pin
(Fast)
OR2C/2T04A
OR2C06A
OR2C/2T08A
OR2C/2T10A
OR2C12A
OR2C/2T15A
OR2C/2T26A
OR2C/2T40A
—
—
—
—
—
—
—
—
10.3
10.4
10.5
10.6
10.7
10.8
11.0
11.4
—
—
—
—
—
—
—
—
9.8
9.9
10.0
10.1
10.2
10.3
10.5
10.8
—
—
—
—
—
—
—
—
8.6
8.7
8.8
8.9
9.0
9.1
9.2
9.5
—
—
—
—
—
—
—
—
—
—
—
—
—
8.3
8.4
8.6
—
—
—
—
—
—
—
—
—
—
—
—
—
6.7
6.9
7.0
ns
ns
ns
ns
ns
ns
ns
ns
CLK Input Pin → OUTPUT Pin
(Slewlim)
OR2C/2T04A
OR2C06A
OR2C/2T08A
OR2C/2T10A
OR2C12A
OR2C/2T15A
OR2C/2T26A
OR2C/2T40A
—
—
—
—
—
—
—
—
12.5
12.6
12.7
12.8
12.9
13.0
13.2
13.6
—
—
—
—
—
—
—
—
11.7
11.8
11.9
12.0
12.1
12.2
12.3
12.6
—
—
—
—
—
—
—
—
10.0
10.1
10.2
10.3
10.4
10.5
10.6
10.9
—
—
—
—
—
—
—
—
—
—
—
—
—
9.5
9.6
9.8
—
—
—
—
—
—
—
—
—
—
—
—
—
7.4
7.5
7.7
ns
ns
ns
ns
ns
ns
ns
ns
CLK Input Pin → OUTPUT Pin
(Sinklim)
OR2C/2T04A
OR2C06A
OR2C/2T08A
OR2C/2T10A
OR2C12A
OR2C/2T15A
OR2C/2T26A
OR2C/2T40A
—
—
—
—
—
—
—
—
14.7
14.8
14.9
15.0
15.1
15.2
15.3
15.7
—
—
—
—
—
—
—
—
13.7
13.8
13.9
14.0
14.1
14.2
14.3
14.6
—
—
—
—
—
—
—
—
13.1
13.2
13.3
13.4
13.5
13.6
13.7
14.0
—
—
—
—
—
—
—
—
—
—
—
—
—
12.1
12.2
12.4
—
—
—
—
—
—
—
—
—
—
—
—
—
10.0
10.7
10.9
ns
ns
ns
ns
ns
ns
ns
ns
Notes:
The pin-to-pin timing information from ispLEVER is more accurate than this table. For earlier versions of ORCA
Foundry, the pin-to-pin timing parameters in this table should be used instead of results reported by ORCA Foundry.
This clock delay is for a fully routed clock tree that uses the primary clock network. It includes both the input buffer delay, the clock routing to
the PFU CLK input, the clock→Q of the FF, and the delay through the output buffer. The delay will be reduced if any of the clock branches are
not used. The given timing requires that the input clock pin be located at one of the four center PICs on any side of the device and that the
direct FF→I/O routing be used.
If the clock pin is not located at one of the four center PICs, this delay must be increased by up to the following amounts:
OR2C/2T04A = 1.5%, OR2C06A = 2.0%, OR2C/2T08A = 3.1%, OR2C/2T10A = 3.9%, OR2C12A = 4.9%, OR2C/2T15A = 5.7%,
OR2C/2T26A = 8.1%, OR2C/2T40A = 12.5%.
152
Lattice Semiconductor
Data Sheet
November 2006
ORCA Series 2 FPGAs
Timing Characteristics (continued)
Table 43B. OR2TxxB Global Clock to Output Delay (Pin-to-Pin)—Output on Same Side of the Device as the
Clock Pin
OR2TxxB Commercial: VDD = 3.0 V to 3.6 V, 0 °C ≤ TA ≤ 70 °C;
Industrial: VDD = 3.0 V to 3.6 V, –40 °C ≤ TA ≤ +85 °C; CL = 50 pF.
SE
L
D E
IS C
C T
O D
N E
TI VI
N C
U E
ED S
Speed
Description
(TJ = 85 °C, VDD = min)
Device
CLK Input Pin → OUTPUT Pin
(Fast)
-7
-8
Unit
Min
Max
Min
Max
OR2T15B
OR2T40B
—
—
7.3
7.5
—
—
6.6
6.6
ns
ns
CLK Input Pin → OUTPUT Pin
(Slewlim)
OR2T15B
OR2T40B
—
—
8.2
8.4
—
—
7.4
7.6
ns
ns
CLK Input Pin → OUTPUT Pin
(Sinklim)
OR2T15B
OR2T40B
—
—
12.9
13.1
—
—
12.1
12.3
ns
ns
Notes:
The pin-to-pin timing information from ispLEVER is more accurate than this table. For earlier versions of ORCA Foundry, the pin-to-pin timing
parameters in this table should be used instead of results reported by ORCA Foundry.
This clock delay is for a fully routed clock tree that uses the primary clock network. It includes both the input buffer delay, the clock routing to the
PFU CLK input, the clock→Q of the FF, and the delay through the output buffer. The delay will be reduced if any of the clock branches are not
used. The given timing requires that the input clock pin be located at one of the four center PICs on any side of the device and that the direct
FF→I/O routing be used.
If the clock pin is not located at one of the four center PICs, this delay must be increased by up to the following amounts:
OR2T15B = 5.7%, OR2T40B = 12.5%.
D
Q
OUTPUT (50 pF LOAD)
CLK
5-4846(F)
Figure 62. Global Clock to Output Delay
Lattice Semiconductor
153
Data Sheet
November 2006
ORCA Series 2 FPGAs
Timing Characteristics (continued)
Table 44A. OR2CxxA/OR2TxxA Global Clock to Output Delay (Pin-to-Pin)—Output Not on Same
Side of the Device as the Clock Pin
SE
L
D E
IS C
C T
O D
N E
TI VI
N C
U E
ED S
OR2CxxA Commercial: VDD = 5.0 V ± 5%, 0 °C ≤ TA ≤ 70 °C; Industrial: VDD = 5.0 V ± 10%, –40 °C ≤ TA ≤ +85 °C; CL = 50 pF.
OR2TxxA Commercial: VDD = 3.0 V to 3.6 V, 0 °C ≤ TA ≤ 70 °C;
Industrial: VDD = 3.0 V to 3.6 V, –40 °C ≤ TA ≤ +85 °C; CL = 50 pF.
Description
(TJ = 85 °C, VDD = min)
Speed
Device
-3
-4
-5
-6
Unit
-7
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
CLK Input Pin → OUTPUT Pin
(Fast)
OR2C/2T04A
OR2C06A
OR2C/2T08A
OR2C/2T10A
OR2C12A
OR2C/2T15A
OR2C/2T26A
OR2C/2T40A
—
—
—
—
—
—
—
—
10.5
10.6
10.8
11.0
11.2
11.5
11.9
13.3
—
—
—
—
—
—
—
—
9.9
10.0
10.1
10.3
10.5
10.7
11.1
12.4
—
—
—
—
—
—
—
—
8.8
8.9
9.0
9.2
9.4
9.6
10.0
11.1
—
—
—
—
—
—
—
—
—
—
—
—
—
8.9
9.3
10.5
—
—
—
—
—
—
—
—
—
—
—
—
—
7.3
7.7
8.3
ns
ns
ns
ns
ns
ns
ns
ns
CLK Input Pin → OUTPUT Pin
(Slewlim)
OR2C/2T04A
OR2C06A
OR2C/2T08A
OR2C/2T10A
OR2C12A
OR2C/2T15A
OR2C/2T26A
OR2C/2T40A
—
—
—
—
—
—
—
—
12.7
12.9
13.1
13.3
13.5
13.6
14.1
15.5
—
—
—
—
—
—
—
—
11.8
11.9
12.0
12.2
12.4
12.6
12.9
14.2
—
—
—
—
—
—
—
—
10.3
10.4
10.5
10.6
10.8
11.0
11.4
12.5
—
—
—
—
—
—
—
—
—
—
—
—
—
10.1
10.5
11.7
—
—
—
—
—
—
—
—
—
—
—
—
—
8.0
8.4
9.1
ns
ns
ns
ns
ns
ns
ns
ns
CLK Input Pin → OUTPUT Pin
(Sinklim)
OR2C/2T04A
OR2C06A
OR2C/2T08A
OR2C/2T10A
OR2C12A
OR2C/2T15A
OR2C/2T26A
OR2C/2T40A
—
—
—
—
—
—
—
—
14.8
15.0
15.2
15.4
15.6
15.8
16.2
17.6
—
—
—
—
—
—
—
—
13.8
13.9
14.1
14.2
14.4
14.6
14.9
16.3
—
—
—
—
—
—
—
—
13.4
13.5
13.6
13.7
13.9
14.1
14.4
15.6
—
—
—
—
—
—
—
—
—
—
—
—
—
12.7
13.1
14.3
—
—
—
—
—
—
—
—
—
—
—
—
—
11.2
11.6
12.2
ns
ns
ns
ns
ns
ns
ns
ns
Notes:
The pin-to-pin timing information from ispLEVER is more accurate than this table. For earlier versions of ORCA Foundry, the pin-to-pin timing
parameters in this table should be used instead of results reported by ORCA Foundry.
This clock delay is for a fully routed clock tree that uses the primary clock network. It includes both the input buffer delay, the clock routing to the
PFU CLK input, the clock→Q of the FF, and the delay through the output buffer. The delay will be reduced if any of the clock branches are not
used. The given timing requires that the input clock pin be located at one of the four center PICs on any side of the device and that the direct
FF→I/O routing be used.
If the clock pin is not located at one of the four center PICs, this delay must be increased by up to the following amounts:
OR2C/2T04A = 1.5%, OR2C06A = 2.0%, OR2C/2T08A = 3.1%, OR2C/2T10A = 3.9%, OR2C12A = 4.9%, OR2C/2T15A = 5.7%,
OR2C/2T26A = 8.1%, OR2C/2T40A = 12.5%.
154
Lattice Semiconductor
Data Sheet
November 2006
ORCA Series 2 FPGAs
Timing Characteristics (continued)
.
Table 44B. OR2TxxB Global Clock to Output Delay (Pin-to-Pin)—Output Not on Same Side of the Device as
the Clock Pin
SE
L
D E
IS C
C T
O D
N E
TI VI
N C
U E
ED S
OR2TxxB Commercial: VDD = 3.0 V to 3.6 V, 0 °C ≤ TA ≤ 70 °C;
Industrial: VDD = 3.0 V to 3.6 V, –40 °C ≤ TA ≤ +85 °C; CL = 50 pF.
Speed
Description
(TJ = 85 °C, VDD = min)
Device
CLK Input Pin → OUTPUT Pin
(Fast)
-7
-8
Unit
Min
Max
Min
Max
OR2T15B
OR2T40B
—
—
7.6
8.1
—
—
6.9
7.4
ns
ns
CLK Input Pin → OUTPUT Pin
(Slewlim)
OR2T15B
OR2T40B
—
—
8.4
9.0
—
—
7.7
8.2
ns
ns
CLK Input Pin → OUTPUT Pin
(Sinklim)
OR2T15B
OR2T40B
—
—
13.2
13.7
—
—
12.4
12.8
ns
ns
Notes:
The pin-to-pin timing information from ispLEVER is more accurate than this table. For earlier versions of ORCA Foundry, the pin-to-pin timing
parameters in this table should be used instead of results reported by ORCA Foundry.
This clock delay is for a fully routed clock tree that uses the primary clock network. It includes both the input buffer delay, the clock routing to the
PFU CLK input, the clock→Q of the FF, and the delay through the output buffer. The delay will be reduced if any of the clock branches are not
used. The given timing requires that the input clock pin be located at one of the four center PICs on any side of the device and that the direct
FF→I/O routing be used.
If the clock pin is not located at one of the four center PICs, this delay must be increased by up to the following amounts:
OR2T15B = 5.7%, OR2T40B = 12.5%.
D
Q
OUTPUT (50 pF LOAD)
CLK
5-4846(F)
Figure 63. Global Clock to Output Delay
Lattice Semiconductor
155
Data Sheet
November 2006
ORCA Series 2 FPGAs
Timing Characteristics (continued)
Table 45A. OR2CxxA/OR2TxxA Global Input to Clock Setup/Hold Time (Pin-to-Pin)
OR2CxxA Commercial: VDD = 5.0 V ± 5%, 0 °C ≤ TA ≤ 70 °C; Industrial: VDD = 5.0 V ± 10%, –40 °C ≤ TA ≤ +85 °C.
OR2TxxA Commercial: VDD = 3.0 V to 3.6 V, 0 °C ≤ TA ≤ 70 °C; Industrial: VDD = 3.0 V to 3.6 V, –40 °C ≤ TA ≤ +85 °C.
Speed
-5
Min
Max
0.0
—
0.0
—
0.0
—
0.0
—
0.0
—
0.0
—
0.0
—
0.0
—
4.0
—
3.9
—
3.8
—
3.7
—
3.6
—
3.4
—
5.7
—
5.2
—
3.6
—
3.7
—
3.9
—
4.2
—
4.4
—
4.7
—
5.3
—
6.3
—
0.0
—
0.0
—
0.0
—
0.0
—
0.0
—
0.0
—
0.0
—
0.0
—
SE
L
D E
IS C
C T
O D
N E
TI VI
N C
U E
ED S
Description
(TJ = all, VDD = all)
Input to CLK (TTL/CMOS)
Setup Time (no delay)
Input to CLK (TTL/CMOS)
Setup Time (delayed)
Input to CLK (TTL/CMOS)
Hold Time (no delay)
Input to CLK (TTL/CMOS)
Hold Time (delayed)
Device
OR2C/2T04A
OR2C06A
OR2C/2T08A
OR2C/2T10A
OR2C12A
OR2C/2T15A
OR2C/2T26A
OR2C/2T40A
OR2C/2T04A
OR2C06A
OR2C/2T08A
OR2C/2T10A
OR2C12A
OR2C/2T15A
OR2C/2T26A
OR2C/2T40A
OR2C/2T04A
OR2C06A
OR2C/2T08A
OR2C/2T10A
OR2C12A
OR2C/2T15A
OR2C/2T26A
OR2C/2T40A
OR2C/2T04A
OR2C06A
OR2C/2T08A
OR2C/2T10A
OR2C12A
OR2C/2T15A
OR2C/2T26A
OR2C/2T40A
-3
Min
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
5.5
5.4
5.3
5.0
4.9
4.7
6.9
6.4
4.0
4.1
4.3
4.6
4.8
5.1
5.8
6.8
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
-4
Max
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Min
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
4.2
4.1
4.0
3.9
3.8
3.6
6.0
5.5
3.8
3.9
4.1
4.4
4.6
4.9
5.6
6.6
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
Max
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
-6
Min
—
—
—
—
—
0.0
0.0
0.0
—
—
—
—
—
4.1
6.7
6.5
—
—
—
—
—
4.2
4.6
5.8
—
—
—
—
—
0.0
0.0
0.0
Unit
-7
Max
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Min
—
—
—
—
—
0.0
0.0
0.0
—
—
—
—
—
4.1
6.0
5.8
—
—
—
—
—
3.7
4.1
4.9
—
—
—
—
—
0.0
0.0
0.0
Max
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes:
The pin-to-pin timing parameters in this table should be used instead of results reported by ispLEVER.
This clock delay is for a fully routed clock tree that uses the primary clock network. It includes both the input buffer delay and the clock routing to
the PFU CLK input. The delay will be reduced if any of the clock branches are not used. The given Setup (Delayed and No delay) and Hold
(Delayed) timing allows the input clock pin to be located in any PIC on any side of the device, but direct I/O→FF routing must be used. The Hold
(No delay) timing assumes the clock pin is located at one of the four center PICs and direct I/O→FF routing is used. If it is not located at one of
the four center PICs, this delay must be increased by up to the following amounts: OR2C/2T04A = 5.3%, OR2C06A = 6.4%, OR2C/2T08A =
7.3%, OR2C/2T10A = 9.1%, OR2C12A = 10.8%, OR2C/2T15A = 12.2%, OR2C/2T26A = 16.1%, OR2C/2T40A = 21.2%.
156
Lattice Semiconductor
Data Sheet
November 2006
ORCA Series 2 FPGAs
Timing Characteristics (continued)
Table 45B. OR2TxxB Global Input to Clock Setup/Hold Time (Pin-to-Pin)
OR2TxxB Commercial: VDD = 3.0 V to 3.6 V, 0 °C ≤ TA ≤ 70 °C; Industrial: VDD = 3.0 V to 3.6 V, –40 °C ≤ TA ≤ +85 °C.
Speed
Device
-7
-8
Unit
SE
L
D E
IS C
C T
O D
N E
TI VI
N C
U E
ED S
Description
(TJ = all, VDD = all)
Input to CLK (TTL/CMOS)
Setup Time (no delay)
Input to CLK (TTL/CMOS)
Setup Time (delayed)
Input to CLK (TTL/CMOS)
Hold Time (no delay)
OR2T15B
OR2T40B
OR2T15B
OR2T40B
Input to CLK (TTL/CMOS)
Hold Time (delayed)
OR2T15B
OR2T40B
OR2T15B
OR2T40B
Min
0.0
0.0
4.7
7.7
Max
—
—
—
—
Min
0.0
0.0
4.0
5.5
Max
—
—
—
—
1.6
1.4
0.0
0.0
—
—
—
—
1.4
1.3
0.0
0.0
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
Notes:
The pin-to-pin timing parameters in this table should be used instead of results reported by ispLEVER.
This clock delay is for a fully routed clock tree that uses the primary clock network. It includes both the input buffer delay and the clock routing to
the PFU CLK input. The delay will be reduced if any of the clock branches are not used. The given Setup (delayed and no delay) and Hold
(delayed) timing allows the input clock pin to be located in any PIC on any side of the device, but direct I/O→FF routing must be used. The Hold
(no delay) timing assumes the clock pin is located at one of the four center PICs and direct I/O→FF routing is used. If it is not located at one of
the four center PICs, this delay must be increased by up to the following amounts: OR2T15B = 5.7%, OR2T40B = 12.5%.
INPUT
D
Q
CLK
5-4847(F)
Figure 64. Global Input to Clock Setup/Hold Time
Lattice Semiconductor
157
Data Sheet
November 2006
ORCA Series 2 FPGAs
Timing Characteristics (continued)
Table 46A. OR2CxxA/OR2TxxA Programmable I/O Cell Timing Characteristics
OR2CxxA Commercial: VDD = 5.0 V ± 5%, 0 °C ≤ TA ≤ 70 °C; OR2CxxA Industrial: VDD = 5.0 V ± 10%, –40 °C ≤ TA ≤ +85 °C.
OR2TxxA Commercial: VDD = 3.0 V to 3.6 V, 0 °C ≤ TA ≤ 70 °C; OR2TxxA Industrial: VDD = 3.0 V to 3.6 V, –40 °C ≤ TA ≤ +85 °C.
SE
L
D E
IS C
C T
O D
N E
TI VI
N C
U E
ED S
Speed
Parameter
Symbol
-3
-4
-5
-6
Unit
-7
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Inputs (TJ = 85 °C, VDD = min)
Input Rise Time
TR
—
500
—
500
—
500
—
500
—
500
ns
Input Fall Time
TF
—
500
—
500
—
500
—
500
—
500
ns
Pad to In Delay
PAD_IN_DEL
—
1.5
—
1.3
—
1.2
—
1.2
—
1.1
ns
Pad to Nearest PFU Latch Output
CHIP_LATCH
—
4.7
—
4.1
—
3.5
—
3.1
—
2.9
ns
Delay Added to General Routing
(input buffer in delay mode for
OR2C/2T15A and smaller
devices)
—
—
7.0
—
6.0
—
5.9
—
6.2
—
5.8
ns
Delay Added to General Routing
(input buffer in delay mode for
OR2C/2T26A and OR2C/2T40A)
—
—
9.7
—
8.6
—
8.6
—
9.0
—
8.6
ns
Delay Added to Direct-FF Routing
(input buffer in delay mode for
OR2C/2T15A and smaller
devices)
—
—
6.8
—
5.9
—
6.0
—
6.4
—
6.0
ns
Delay Added to Direct-FF Routing
(input buffer in delay mode for
OR2C/2T26A and OR2C/2T40A)
—
—
10.2
—
8.5
—
8.6
—
9.1
—
7.9
ns
DOUT_DEL(F)
DOUT_DEL(SL)
DOUT_DEL(SI)
—
—
—
6.2
8.4
10.5
—
—
—
5.5
7.4
9.4
—
—
—
5.0
6.4
9.5
—
—
—
4.4
5.6
8.3
—
—
—
3.3
4.1
7.2
ns
ns
ns
OUT_DEL(F)
OUT_DEL(SL)
OUT_DEL(SI)
—
—
—
4.0
6.3
7.2
—
—
—
3.6
5.5
7.5
—
—
—
3.1
4.5
7.6
—
—
—
2.7
3.9
6.5
—
—
—
2.3
3.1
6.2
ns
ns
ns
TS_DEL(F)
TS_DEL(SL)
TS_DEL(SI)
—
—
—
4.7
7.0
7.9
—
—
—
4.0
6.3
8.4
—
—
—
3.5
5.2
9.3
—
—
—
3.1
4.7
8.0
—
—
—
2.5
3.7
7.6
ns
ns
ns
Outputs (TJ = 85 °C, VDD = min, CL = 50 pF)
PFU CK to Pad Delay (DOUT[3:0] to
PAD):
Fast
Slewlim
Sinklim
Output to Pad Delay (OUT[3:0] to
PAD):
Fast
Slewlim
Sinklim
3-state Enable Delay (TS[3:0] to
PAD):
Fast
Slewlim
Sinklim
Notes:
If the input buffer is placed in delay mode, the chip hold time to the nearest PFU latch is guaranteed to be 0 if the clock is routed using the
primary clock network; (TJ = all, VDD = all). It should also be noted that any signals routed on the clock lines or using the TRIDI buffers directly
from the input buffer do not get delayed at any time.
The delays for all input buffers assume an input rise/fall time of ≤1 V/ns.
158
Lattice Semiconductor
Data Sheet
November 2006
ORCA Series 2 FPGAs
Timing Characteristics (continued)
Table 46B. OR2TxxB Programmable I/O Cell Timing Characteristics
OR2TxxA Commercial: VDD = 3.0 V to 3.6 V, 0 °C ≤ TA ≤ 70 °C; OR2TxxA Industrial: VDD = 3.0 V to 3.6 V, –40 °C ≤ TA ≤
+85 °C.
SE
L
D E
IS C
C T
O D
N E
TI VI
N C
U E
ED S
Speed
Parameter
Symbol
-7
-8
Unit
Min
Max
Min
Max
Inputs (TJ = 85 °C, VDD = min)
Input Rise Time
TR
—
500
—
500
ns
Input Fall Time
TF
—
500
—
500
ns
Pad to In Delay
PAD_IN_DEL
—
1.1
—
1.0
ns
Pad to Nearest PFU Latch Output
CHIP_LATCH
—
3.3
—
2.4
ns
Delay Added to General Routing
(input buffer in delay mode for
OR2T15B and smaller devices)
—
—
6.6
—
6.1
ns
Delay Added to General Routing
(input buffer in delay mode for
OR2T40B)
—
—
8.9
—
8.2
ns
Delay Added to Direct-FF Routing
(input buffer in delay mode for
OR2T15B and smaller devices)
—
—
6.4
—
6.0
ns
Delay Added to Direct-FF Routing
(input buffer in delay mode for
OR2T40B)
—
—
8.7
—
8.0
ns
DOUT_DEL(F)
DOUT_DEL(SL)
DOUT_DEL(SI)
—
—
—
2.8
3.6
8.3
—
—
—
2.5
3.3
8.0
ns
ns
ns
OUT_DEL(F)
OUT_DEL(SL)
OUT_DEL(SI)
—
—
—
2.8
3.6
8.3
—
—
—
2.5
3.3
8.0
ns
ns
ns
TS_DEL(F)
TS_DEL(SL)
TS_DEL(SI)
—
—
—
3.0
3.8
9.1
—
—
—
2.7
3.4
8.7
ns
ns
ns
Outputs (TJ = 85 °C, VDD = min, CL = 50 pF)
PFU CK to Pad Delay (DOUT[3:0] to
PAD):
Fast
Slewlim
Sinklim
Output to Pad Delay (OUT[3:0] to
PAD):
Fast
Slewlim
Sinklim
3-state Enable Delay (TS[3:0] to
PAD):
Fast
Slewlim
Sinklim
Notes:
If the input buffer is placed in delay mode, the chip hold time to the nearest PFU latch is guaranteed to be 0 if the clock is routed using the
primary clock network; (TJ = all, VDD = all). It should also be noted that any signals routed on the clock lines or using the TRIDI buffers directly
from the input buffer do not get delayed at any time.
The delays for all input buffers assume an input rise/fall time of ≤1 V/ns.
Lattice Semiconductor
159
Data Sheet
November 2006
ORCA Series 2 FPGAs
Timing Characteristics (continued)
Table 47. Series 2 General Configuration Mode Timing Characteristics
OR2CxxA Commercial: VDD = 5.0 V ± 5%, 0 °C ≤ TA ≤ 70 °C; OR2CxxA Industrial: VDD = 5.0 V ± 10%, –40 °C ≤ TA ≤ +85 °C.
OR2TxxA/B Commercial: VDD = 3.0 V to 3.6 V, 0 °C ≤ TA ≤ 70 °C; OR2TxxA/B Industrial: VDD = 3.0 V to 3.6 V,
–40 °C ≤ TA ≤ +85 °C.
Symbol
Min
Max
Unit
TSMODE
THMODE
TRW
TPGW
50.0
600.0
50.0
50.0
—
—
—
—
ns
ns
ns
ns
TPO
TCCLK
17.30
66.0
528.00
69.47
265.00
2120.00
ms
ns
ns
4.31
34.48
6.00
48.00
7.62
60.96
9.82
78.56
11.86
94.88
14.57
116.56
20.25
162.00
31.29
250.32
17.30*
138.40*
24.08*
192.64*
30.60*
244.80*
39.43*
315.44*
47.62*
380.96*
58.51*
468.08*
81.32*
650.56*
125.62*
1004.96*
ms
ms
ms
ms
ms
ms
ms
ms
ms
ms
ms
ms
ms
ms
ms
ms
4.33
100.00
25.00
17.37
—
—
ms
ns
ns
6.53
9.09
11.55
14.88
17.97
22.08
5.52
30.69
47.40
11.85
—
—
—
—
—
—
—
—
—
—
ms
ms
ms
ms
ms
ms
ms
ms
ms
ms
SE
L
D E
IS C
C T
O D
N E
TI VI
N C
U E
ED S
Parameter
All Configuration Modes
M[3:0] Setup Time to INIT High
M[3:0] Hold Time from INIT High
RESET Pulse Width Low to Start Reconfiguration
PRGM Pulse Width Low to Start Reconfiguration
Master and Asynchronous Peripheral Modes
Power-on Reset Delay
CCLK Period (M3 = 0)
(M3 = 1)
Configuration Latency (noncompressed):
OR2C/2T04A
(M3 = 0)
(M3 = 1)
OR2C/2T06A
(M3 = 0)
(M3 = 1)
OR2C/2T08A
(M3 = 0)
(M3 = 1)
OR2C/2T10A
(M3 = 0)
(M3 = 1)
OR2C12A
(M3 = 0)
(M3 = 1)
OR2C/2T15A/2T15B (M3 = 0)
(M3 = 1)
OR2C/2T26A
(M3 = 0)
(M3 = 1)
OR2C/2T40A/2T40B (M3 = 0)
(M3 = 1)
Slave Serial and Synchronous Peripheral Modes
Power-on Reset Delay
CCLK Period (OR2CxxA/OR2TxxA)
CCLK Period (OR2TxxB)
Configuration Latency (noncompressed):
OR2C/2T04A
OR2C/2T06A
OR2C/2T08A
OR2C/2T10A
OR2C12A
OR2C/2T15A
OR2T15B
OR2C/2T26A
OR2C/2T40A
OR2T40B
TCL
TPO
TCCLK
TCCLK
TCL
* Not applicable to asynchronous peripheral mode.
160
Lattice Semiconductor
Data Sheet
November 2006
ORCA Series 2 FPGAs
Timing Characteristics (continued)
Table 47. Series 2 General Configuration Mode Timing Characteristics (continued)
OR2CxxA Commercial: VDD = 5.0 V ± 5%, 0 °C ≤ TA ≤ 70 °C; OR2CxxA Industrial: VDD = 5.0 V ± 10%, –40 °C ≤ TA ≤ +85 °C.
OR2TxxA/B Commercial: VDD = 3.0 V to 3.6 V, 0 °C ≤ TA ≤ 70 °C; OR2TxxA/B Industrial: VDD = 3.0 V to 3.6 V,
–40 °C ≤ TA ≤ +85 °C.
Symbol
Min
Max
TPO
TCCLK
TCCLK
TCL
4.33
100.00
25.0
17.37
—
—
ms
ns
ns
0.82
1.14
1.44
1.86
2.25
2.76
0.69
3.84
5.93
1.48
—
—
—
—
—
—
—
—
—
—
ms
ms
ms
ms
ms
ms
ms
ms
ms
ms
1.70
2.00
2.20
2.50
2.70
3.00
3.50
4.30
—
—
—
—
—
—
—
—
µs/frame
µs/frame
µs/frame
µs/frame
µs/frame
µs/frame
µs/frame
µs/frame
1.00
1.00
1.00
—
—
—
µs
µs
µs
1.06
0.59
4.51
2.65
µs
µs
5.28
1.12
21.47
4.77
µs
µs
63.36
74.98
86.59
98.21
109.82
121.44
144.67
181.90
254.40
301.04
347.68
394.32
440.96
487.60
580.88
730.34
1.50
—
µs
µs
µs
µs
µs
µs
µs
µs
µs
SE
L
D E
IS C
C T
O D
N E
TI VI
N C
U E
ED S
Parameter
Slave Parallel Mode
Power-on Reset Delay
CCLK Period (OR2CxxA/OR2TxxA)
CCLK Period (OR2TxxB)
Configuration Latency (noncompressed):
OR2C/2T04A
OR2C/2T06A
OR2C/2T08A
OR2C/2T10A
OR2C12A
OR2C/2T15A
OR2T15B
OR2C/2T26A
OR2C/2T40A
OR2T40B
Partial Reconfiguration (noncompressed):
OR2C/2T04A
OR2C/2T06A
OR2C/2T08A
OR2C/2T10A
OR2C12A
OR2C/2T15A/2T15B
OR2C/2T26A
OR2C/2T40A/2T40B
INIT Timing
INIT High to CCLK Delay:
Slave Parallel
Slave Serial
Synchronous Peripheral
Master Serial:
(M3 = 1)
(M3 = 0)
Master Parallel:
(M3 = 1)
(M3 = 0)
Initialization Latency (PRGM high to INIT high):
OR2C/2T04A
OR2C/2T06A
OR2C/2T08A
OR2C/2T10A
OR2C12A
OR2C/2T15A/2T15B
OR2C/2T26A
OR2C/2T40A/2T40B
INIT High to WR, Asynchronous Peripheral
Unit
TPR
TINIT_CLK
TIL
TINIT_WR
Note: TPO is triggered when VDD reaches between 3.0 V to 4.0 V for the OR2CxxA and between 2.7 V and 3.0 V for the OR2TxxA/OR2TxxB.
Lattice Semiconductor
161
Data Sheet
November 2006
ORCA Series 2 FPGAs
Timing Characteristics (continued)
Series 2
VDD
SE
L
D E
IS C
C T
O D
N E
TI VI
N C
U E
ED S
TPO + T IL
PRGM
TPGW
TIL
INIT
TINIT_CLK
TCCLK
CCLK
THMODE
TSMODE
M[3:0]
TCL
DONE
5-4531(F)
Figure 65. General Configuration Mode Timing Diagram
162
Lattice Semiconductor
Data Sheet
November 2006
ORCA Series 2 FPGAs
Timing Characteristics (continued)
Table 48. Series 2 Master Serial Configuration Mode Timing Characteristics
SE
L
D E
IS C
C T
O D
N E
TI VI
N C
U E
ED S
OR2CxxA Commercial: VDD = 5.0 V ± 5%, 0 °C ≤ TA ≤ 70 °C; OR2CxxA Industrial: VDD = 5.0 V ± 10%, –40 °C ≤ TA ≤ +85 °C.
OR2TxxA/B Commercial: VDD = 3.0 V to 3.6 V, 0 °C ≤ TA ≤ 70 °C; OR2TxxA/B Industrial: VDD = 3.0 V to 3.6 V,
–40 °C ≤ TA ≤ +85 °C.
Parameter
DIN Setup Time
DIN Hold Time
CCLK Frequency (M3 = 0)
CCLK Frequency (M3 = 1)
CCLK to DOUT Delay
Symbol
TS
TH
FC
FC
TD
Min
60.0
0
3.8
0.48
—
Nom
—
—
10.0
1.25
—
Max
—
—
15.2
1.9
30
Unit
ns
ns
MHz
MHz
ns
Note: Serial configuration data is transmitted out on DOUT on the falling edge of CCLK after it is input DIN.
CCLK
TS
DIN
TH
BIT N
TD
DOUT
BIT N
5-4532(F)
Figure 66. Master Serial Configuration Mode Timing Diagram
Lattice Semiconductor
163
Data Sheet
November 2006
ORCA Series 2 FPGAs
Timing Characteristics (continued)
Table 49. Series 2 Master Parallel Configuration Mode Timing Characteristics
SE
L
D E
IS C
C T
O D
N E
TI VI
N C
U E
ED S
OR2CxxA Commercial: VDD = 5.0 V ± 5%, 0 °C ≤ TA ≤ 70 °C; OR2CxxA Industrial: VDD = 5.0 V ± 10%, –40 °C ≤ TA ≤ +85 °C.
OR2TxxA/B Commercial: VDD = 3.0 V to 3.6 V, 0 °C ≤ TA ≤ 70 °C; OR2TxxA/B Industrial: VDD = 3.0 V to 3.6 V,
–40 °C ≤ TA ≤ +85 °C.
Parameter
RCLK to Address Valid
D[7:0] Setup Time to RCLK High
D[7:0] Hold Time to RCLK High
RCLK Low Time (M3 = 0)
RCLK High Time (M3 = 0)
RCLK Low Time (M3 = 1)
RCLK High Time (M3 = 1)
CCLK to DOUT
Symbol
TAV
TS
TH
TCL
TCH
TCL
TCH
TD
Min
0
60
0
462
66
3696
528
—
Max
200
—
—
1855
265
14840
2120
30
Unit
ns
ns
ns
ns
ns
ns
ns
ns
Notes:
The RCLK period consists of seven CCLKs for RCLK low and one CCLK for RCLK high.
Serial data is transmitted out on DOUT 1.5 CCLK cycles after the byte is input D[7:0]
A[17:0]
TAV
TCH
TCL
RCLK
TS
D[7:0]
TH
BYTE N + 1
BYTE N
CCLK
DOUT
D0
D1
D2
D3
D4
D5
D6
D7
TD
f.44(F)
Figure 67. Master Parallel Configuration Mode Timing Diagram
164
Lattice Semiconductor
Data Sheet
November 2006
ORCA Series 2 FPGAs
Timing Characteristics (continued)
Table 50. Series 2 Asynchronous Peripheral Configuration Mode Timing Characteristics
SE
L
D E
IS C
C T
O D
N E
TI VI
N C
U E
ED S
OR2CxxA Commercial: VDD = 5.0 V ± 5%, 0 °C ≤ TA ≤ 70 °C; OR2CxxA Industrial: VDD = 5.0 V ± 10%, –40 °C ≤ TA ≤ +85 °C.
OR2TxxA/B Commercial: VDD = 3.0 V to 3.6 V, 0 °C ≤ TA ≤ 70 °C; OR2TxxA/B Industrial: VDD = 3.0 V to 3.6 V,
–40 °C ≤ TA ≤ +85 °C.
Parameter
WR, CS0, and CS1 Pulse Width
D[7:0] Setup Time
D[7:0] Hold Time
RDY Delay
RDY Low
Earliest WR After RDY Goes High*
RD to D7 Enable/Disable
CCLK to DOUT
Symbol
TWR
TS
TH
TRDY
TB
TWR2
TDEN
TD
Min
100
20
0
—
1
0
—
—
Max
—
—
—
60
8
—
60
30
Unit
ns
ns
ns
ns
CCLK Periods
ns
ns
ns
* This parameter is valid whether the end of not RDY is determined from the RDY/RCLK pin or from the D7 pin.
Notes:
Serial data is transmitted out on DOUT on the falling edge of CCLK after the byte is input D[7:0].
D[6:0] timing is the same as the write data port of the D7 waveform because D[6:0] are not enabled.
CS0
CS1
TWR
WR
TS
D7
TH
TWR2
WRITE DATA
TDEN
TDEN
RD
RDY
TB
TRDY
CCLK
TD
DOUT
PREVIOUS BYTE
D7
D0
D1
D2
D3
5-4533.a
Figure 68. Asynchronous Peripheral Configuration Mode Timing Diagram
Lattice Semiconductor
165
Data Sheet
November 2006
ORCA Series 2 FPGAs
Timing Characteristics (continued)
Table 51A. OR2CxxA/OR2TxxA Synchronous Peripheral Configuration Mode Timing Characteristics
OR2CxxA Commercial: VDD = 5.0 V ± 5%, 0 °C ≤ TA ≤ 70 °C; OR2CxxA Industrial: VDD = 5.0 V ± 10%, –40 °C ≤ TA ≤ +85 °C.
OR2TxxA Commercial: VDD = 3.0 V to 3.6 V, 0 °C ≤ TA ≤ 70 °C; OR2TxxA Industrial: VDD = 3.0 V to 3.6 V, –40 °C ≤ TA ≤ +85 °C.
Symbol
TS
TH
TCH
TCL
FC
TD
Min
20
0
50
50
—
—
Max
—
—
—
—
10
30
Unit
ns
ns
ns
ns
MHz
ns
SE
L
D E
IS C
C T
O D
N E
TI VI
N C
U E
ED S
Parameter
D[7:0] Setup Time
D[7:0] Hold Time
CCLK High Time
CCLK Low Time
CCLK Frequency
CCLK to DOUT
Note: Serial data is transmitted out on DOUT 1.5 clock cycles after the byte is input D[7:0].
Table 51B. OR2TxxB Synchronous Peripheral Configuration Mode Timing Characteristics
OR2TxxB Commercial: VDD = 3.0 V to 3.6 V, 0 °C ≤ TA ≤ 70 °C; OR2TxxB Industrial: VDD = 3.0 V to 3.6 V, –40 °C ≤ TA ≤ +85 °C.
Parameter
D[7:0] Setup Time
D[7:0] Hold Time
CCLK High Time
CCLK Low Time
CCLK Frequency
CCLK to DOUT
Symbol
TS
TH
TCH
TCL
FC
TD
Min
15
0
12.5
12.5
—
—
Max
—
—
—
—
40
10
Unit
ns
ns
ns
ns
MHz
ns
Note: Serial data is transmitted out on DOUT 1.5 clock cycles after the byte is input D[7:0].
TCH
CCLK
TINIT_CLK
TCL
INIT
TH
TS
D[7:0]
BYTE 1
BYTE 0
TD
DOUT
0
1
2
3
4
5
6
7
0
RDY
5-4534(F)
Figure 69. Synchronous Peripheral Configuration Mode Timing Diagram
166
Lattice Semiconductor
Data Sheet
November 2006
ORCA Series 2 FPGAs
Timing Characteristics (continued)
Table 52A. OR2CxxA/OR2TxxA Slave Serial Configuration Mode Timing Characteristics
OR2CxxA Commercial: VDD = 5.0 V ± 5%, 0 °C ≤ TA ≤ 70 °C; OR2CxxA Industrial: VDD = 5.0 V ± 10%, –40 °C ≤ TA ≤ +85 °C.
OR2TxxA Commercial: VDD = 3.0 V to 3.6 V, 0 °C ≤ TA ≤ 70 °C; OR2TxxA Industrial: VDD = 3.0 V to 3.6 V, –40 °C ≤ TA ≤ +85 °C
Symbol
TS
TH
TCH
TCL
FC
TD
Min
20
0
50
50
—
—
Max
—
—
—
—
10
30
Unit
ns
ns
ns
ns
MHz
ns
SE
L
D E
IS C
C T
O D
N E
TI VI
N C
U E
ED S
Parameter
DIN Setup Time
DIN Hold Time
CCLK High Time
CCLK Low Time
CCLK Frequency
CCLK to DOUT
Note: Serial configuration data is transmitted out on DOUT on the falling edge of CCLK after it is input on DIN.
Table 52B. OR2TxxB Slave Serial Configuration Mode Timing Characteristics
OR2TxxB Commercial: VDD = 3.0 V to 3.6 V, 0 °C ≤ TA ≤ 70 °C; OR2TxxB Industrial: VDD = 3.0 V to 3.6 V, –40 °C ≤ TA ≤ +85 °C.
Parameter
DIN Setup Time
DIN Hold Time
CCLK High Time
CCLK Low Time
CCLK Frequency
CCLK to DOUT
Symbol
TS
TH
TCH
TCL
FC
TD
Min
15
0
12.5
12.5
—
—
Max
—
—
—
—
40
10
Unit
ns
ns
ns
ns
MHz
ns
Note: Serial configuration data is transmitted out on DOUT on the falling edge of CCLK after it is input on DIN
BIT N
DIN
TS
TH
CCLK
TD
DOUT
TCL
TCH
BIT N
5-4535(F)
Figure 70. Slave Serial Configuration Mode Timing Diagram
Lattice Semiconductor
167
Data Sheet
November 2006
ORCA Series 2 FPGAs
Timing Characteristics (continued)
Table 53A. OR2CxxA/OR2TxxA Slave Parallel Configuration Mode Timing Characteristics
OR2CxxA Commercial: VDD = 5.0 V ± 5%, 0 °C ≤ TA ≤ 70 °C; OR2CxxA Industrial: VDD = 5.0 V ± 10%, –40 °C ≤ TA ≤ +85 °C.
OR2TxxA Commercial: VDD = 3.0 V to 3.6 V, 0 °C ≤ TA ≤ 70 °C; OR2TxxA Industrial: VDD = 3.0 V to 3.6 V, –40 °C ≤ TA ≤ +85 °C.
Symbol
TS1
TH1
TS2
TH2
TCH
TCL
FC
Min
60
20
20
0
50
50
—
Max
—
—
—
—
—
—
10
Unit
ns
ns
ns
ns
ns
ns
MHz
SE
L
D E
IS C
C T
O D
N E
TI VI
N C
U E
ED S
Parameter
CS0, CS1, WR Setup Time
CS0, CS1, WR Hold Time
D[7:0] Setup Time
D[7:0] Hold Time
CCLK High Time
CCLK Low Time
CCLK Frequency
Note: Daisy chaining of FPGAs is not supported in this mode.
Table 53B. OR2TxxB Slave Parallel Configuration Mode Timing Characteristics
OR2TxxB Commercial: VDD = 3.0 V to 3.6 V, 0 °C ≤ TA ≤ 70 °C; OR2TxxB Industrial: VDD = 3.0 V to 3.6 V, –40 °C ≤ TA ≤ +85 °C.
Parameter
CS0, CS1, WR Setup Time
CS0, CS1, WR Hold Time
D[7:0] Setup Time
D[7:0] Hold Time
CCLK High Time
CCLK Low Time
CCLK Frequency
Symbol
TS1
TH1
TS2
TH2
TCH
TCL
FC
Min
—
15
15
0
12.5
12.5
—
Max
—
—
—
—
—
—
40
Unit
—
ns
ns
ns
ns
ns
MHz
Note: Daisy chaining of FPGAs is not supported in this mode.
CS0
CS1
WR
TS1
TH1
CCLK
TS2
TH2
D[7:0]
5-2848(F)
Figure 71. Slave Parallel Configuration Mode Timing Diagram
168
Lattice Semiconductor
Data Sheet
November 2006
ORCA Series 2 FPGAs
Timing Characteristics (continued)
Table 54. Series 2 Readback Timing Characteristics
SE
L
D E
IS C
C T
O D
N E
TI VI
N C
U E
ED S
OR2CxxA Commercial: VDD = 5.0 V ± 5%, 0 °C ≤ TA ≤ 70 °C; OR2CxxA Industrial: VDD = 5.0 V ± 10%, –40 °C ≤ TA ≤ +85 °C.
OR2TxxA/B Commercial: VDD = 3.0 V to 3.6 V, 0 °C ≤ TA ≤ 70 °C; OR2TxxA/B Industrial: VDD = 3.0 V to 3.6 V,
–40 °C ≤ TA ≤ +85 °C.
Parameter
RD_CFGN to CCLK Setup Time
RD_CFGN High Width to Abort Readback
CCLK Low Time
CCLK High Time
CCLK Frequency
CCLK to RD_DATA Delay
Symbol
TS
TRBA
TCL
TCH
FC
TD
Min
50
2
50
50
—
—
Max
—
—
—
—
10
50
Unit
ns
CCLK
ns
ns
MHz
ns
TRBA
RD_CFGN
TCL
TS
CCLK
TCH
TD
RD_DATA
BIT 0
BIT 1
BIT 0
5-4536(F)
Figure 72. Readback Timing Diagram
Lattice Semiconductor
169
Data Sheet
November 2006
ORCA Series 2 FPGAs
Timing Characteristics (continued)
Table 55. Series 2 Boundary-Scan Timing Characteristics
SE
L
D E
IS C
C T
O D
N E
TI VI
N C
U E
ED S
OR2CxxA Commercial: VDD = 5.0 V ± 5%, 0 °C ≤ TA ≤ 70 °C; OR2CxxA Industrial: VDD = 5.0 V ± 10%, –40 °C ≤ TA ≤ +85 °C.
OR2TxxA Commercial: VDD = 3.0 V to 3.6 V, 0 °C ≤ TA ≤ 70 °C; OR2TxxA Industrial: VDD = 3.0 V to 3.6 V, –40 °C ≤ TA ≤ +85 °C.
OR2TxxB Commercial: VDD = 3.0 V to 3.6 V, 0 °C ≤ TA ≤ 70 °C; OR2TxxB Industrial: VDD = 3.0 V to 3.6 V, –40 °C ≤ TA ≤ +85 °C.
Parameter
TDI/TMS to TCK Setup Time
TDI/TMS Hold Time from TCK
TCK Low Time
TCK High Time
TCK to TDO Delay
TCK Frequency
Symbol
TS
TH
TCL
TCH
TD
TTCK
Min
25
0
50
50
—
—
Max
—
—
—
—
20
10
Unit
ns
ns
ns
ns
ns
MHz
TCK
TS
TH
TMS
TDI
TD
TDO
BSTD(F).2c.r3
Figure 73. Boundary-Scan Timing Diagram
170
Lattice Semiconductor
Data Sheet
November 2006
ORCA Series 2 FPGAs
Measurement Conditions
VCC
GND
1 kΩ
TO THE OUTPUT UNDER TEST
SE
L
D E
IS C
C T
O D
N E
TI VI
N C
U E
ED S
50 pF
TO THE OUTPUT UNDER TEST
50 pF
A. Load Used to Measure Propagation Delay
B. Load Used to Measure Rising/Falling Edges
5-3234(F).r1
Figure 74. ac Test Loads
TS[I]
PAD ac TEST LOADS (SHOWN ABOVE)
OUT
OUT[I]
VDD
OUT[I] VDD/2
VSS
PAD 1.5 V
OUT 0.0 V
TPLL
TPHH
5-3233(F).ar4
Figure 75. Output Buffer Delays
PAD
IN
IN[I]
3.0 V
PAD IN 1.5 V
0.0 V
VDD
IN[I] VDD/2
VSS
TPLL
TPHH
5-3235(F).a
Figure 76. Input Buffer Delays
Lattice Semiconductor
171
Data Sheet
November 2006
ORCA Series 2 FPGAs
Output Buffer Characteristics
50
IOL
OUTPUT CURRENT, IO (mA)
OR2CxxA
70
IOL
50
30
SE
L
D E
IS C
C T
O D
N E
TI VI
N C
U E
ED S
OUTPUT CURRENT, IO (mA)
60
40
40
30
20
IOH
10
IOH
20
0
0
1
2
3
4
5
10
OUTPUT VOLTAGE, VO (V)
5-4635(F)
0
0
1
2
3
4
5
Figure 80. Sinklim (TJ = 125 °C, VDD = 4.5 V)
OUTPUT VOLTAGE, VO (V)
150
5-4634(F)
IOL
250
OUTPUT CURRENT, IO (mA)
225
IOL
200
175
150
125
125
OUTPUT CURRENT, IO (mA)
Figure 77. Sinklim (TJ = 25 °C, VDD = 5.0 V)
100
75
50
IOH
25
100
IOH
75
0
0
1
2
3
4
50
OUTPUT VOLTAGE, VO (V)
25
5-4637(F)
0
0
1
2
3
4
Figure 81. Slewlim (TJ = 125 °C, VDD = 4.5 V)
5
OUTPUT VOLTAGE, VO (V)
175
5-4636(F)
250
OUTPUT CURRENT, IO (mA)
225
IOL
200
175
150
125
150
OUTPUT CURRENT, IO (mA)
Figure 78. Slewlim (TJ = 25 °C, VDD = 5.0 V)
IOL
125
100
75
50
IOH
25
100
IOH
75
0
0
50
1
2
3
4
OUTPUT VOLTAGE, VO (V)
5-4639(F)
25
0
0
1
2
3
4
Figure 82. Fast (TJ = 125 °C, VDD = 4.5 V)
5
OUTPUT VOLTAGE, VO (V)
5-4638(F)
Figure 79. Fast (TJ = 25 °C, VDD = 5.0 V)
172
Lattice Semiconductor
Data Sheet
November 2006
ORCA Series 2 FPGAs
Output Buffer Characteristics (continued)
40
OR2TxxA
OUTPUT CURRENT, IO (mA)
35
80
IOL
60
25
IOH
20
SE
L
D E
IS C
C T
O D
N E
TI VI
N C
U E
ED S
OUTPUT CURRENT, IO (mA)
70
IOL
30
50
IOH
40
15
10
30
5
20
0
0.0
10
0.5
1.0
1.5
2.0
2.5
3.0
OUTPUT VOLTAGE, V O (V)
0
0.0 0.5
1.0
1.5
2.0
2.5
Figure 86. Sinklim (TJ = 125 °C, VDD = 3.0 V)
OUTPUT VOLTAGE, VO (V)
70
5-4637(F)
140
IOL
OUTPUT CURRENT, IO (mA)
120
100
80
IOL
60
OUTPUT CURRENT, IO (mA)
Figure 83. Sinklim (TJ = 25 °C, VDD = 3.3 V)
IOH
50
40
IOH
30
20
10
60
0
40
0.0
0.5
1.0
1.5
2.0
2.5
3.0
OUTPUT VOLTAGE, V O (V)
20
0
0.0 0.5
1.0
1.5
2.0
2.5
5-4637(F)
Figure 87. Slewlim (TJ = 125 °C, VDD = 3.0 V)
3.0 3.5
OUTPUT VOLTAGE, VO (V)
70
5-4637(F)
140
IOL
120
100
80
IOH
IOL
60
OUTPUT CURRENT, IO (mA)
Figure 84. Slewlim (TJ = 25 °C, VDD = 3.3 V)
OUTPUT CURRENT, IO (mA)
5-4637(F)
3.0 3.5
50
40
IOH
30
20
10
60
0
40
0.0
0.5
1.0
1.5
2.0
2.5
3.0
OUTPUT VOLTAGE, V O (V)
20
5-4637(F)
0
0.0 0.5
1.0
1.5
2.0
2.5
Figure 88. Fast (TJ = 125 °C, VDD = 3.0 V)
3.0 3.5
OUTPUT VOLTAGE, VO (V)
5-4637(F)
Figure 85. Fast (TJ = 25 °C, VDD = 3.3 V)
Lattice Semiconductor
173
Data Sheet
November 2006
ORCA Series 2 FPGAs
Output Buffer Characteristics (continued)
OUTPUT CURRENT, IO (mA)
OR2TxxB
80
IOL
60
IOL
45
40
35
IOH
30
25
SE
L
D E
IS C
C T
O D
N E
TI VI
N C
U E
ED S
OUTPUT CURRENT, IO (mA)
90
55
50
50
IOH
40
30
20
10
0
15
10
05
0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
OUTPUT VOLTAGE, VO (V)
5-7930(F).r1
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
OUTPUT VOLTAGE, VO (V)
Figure 92. Sinklim (TJ = 125 ¡C, V DD = 3.0 V)
Figure 89. Sinklim (TJ = 25 ¡C, V DD = 3.3 V)
180
160
IOL
140
120
100
80
IOH
OUTPUT CURRENT, IO (mA)
5-7927(F).r1
OUTPUT CURRENT, IO (mA)
20
60
40
110
100
IOL
90
80
70
60
IOH
50
40
30
20
10
0
0.0
20
0
0.5
1.0
1.5
2.0
2.5
3.0
OUTPUT VOLTAGE, VO (V)
5-7931(F).r1
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
Figure 93. Slewlim (TJ = 125 ¡C, V DD = 3.0 V)
OUTPUT VOLTAGE, VO (V)
Figure 90. Slewlim (TJ = 25 ¡C, V DD = 3.3 V)
OUTPUT CURRENT, IO (mA)
180
160
IOL
140
120
100
80
60
IOH
40
110
100
IOL
90
80
70
60
IOH
50
40
30
20
10
0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
OUTPUT VOLTAGE, VO (V)
20
0
OUTPUT CURRENT, IO (mA)
5-7928(F).r1
5-7932(F).r1
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
Figure 94. Fast (TJ = 125 ¡C, V DD = 3.0 V)
OUTPUT VOLTAGE, VO (V)
5-7929(F).r1
Figure 91. Fast (TJ = 25 °C, VDD = 3.3 V)
174
Lattice Semiconductor
Data Sheet
November 2006
ORCA Series 2 FPGAs
Package Outline Drawings
Terms and Definitions
The basic size of a dimension is the size from which the limits for that dimension are derived
by the application of the allowance and the tolerance.
Design Size:
The design size of a dimension is the actual size of the design, including an allowance for fit
and tolerance.
SE
L
D E
IS C
C T
O D
N E
TI VI
N C
U E
ED S
Basic Size (BSC):
Minimum (MIN) or
Maximum (MAX):
Indicates the minimum or maximum allowable size of a dimension.
Reference (REF):
The reference dimension is an untoleranced dimension used for informational purposes only.
It is a repeated dimension or one that can be derived from other values in the drawing.
Typical (TYP):
When specified after a dimension, this indicates the repeated design size if a tolerance is
specified or repeated basic size if a tolerance is not specified.
Lattice Semiconductor
175
Data Sheet
November 2006
ORCA Series 2 FPGAs
Package Outline Drawings (continued)
84-Pin PLCC
Dimensions are in millimeters.
SE
L
D E
IS C
C T
O D
N E
TI VI
N C
U E
ED S
30.353 MAX
29.083 ± 0.076
PIN #1 IDENTIFIER ZONE
11
1
75
12
74
29.083
± 0.076
30.353
MAX
32
54
33
53
5.080
MAX
1.27 TYP
0.330/0.533
0.51 MIN
TYP
SEATING PLANE
0.10
5-2347r.16
176
Lattice Semiconductor
Data Sheet
November 2006
ORCA Series 2 FPGAs
Package Outline Drawings (continued)
100-Pin TQFP
Dimensions are in millimeters.
16.00 ± 0.20
SE
L
D E
IS C
C T
O D
N E
TI VI
N C
U E
ED S
14.00 ± 0.20
PIN #1 IDENTIFIER ZONE
100
76
1
75
14.00
± 0.20
16.00
± 0.20
25
51
26
50
DETAIL A
DETAIL B
1.40 ± 0.05
1.60 MAX
SEATING PLANE
0.08
0.05/0.15
0.50 TYP
1.00 REF
0.106/0.200
0.25
GAGE PLANE
0.19/0.27
SEATING PLANE
0.45/0.75
DETAIL A
0.08
M
DETAIL B
5-2146r.15
Lattice Semiconductor
177
Data Sheet
November 2006
ORCA Series 2 FPGAs
Package Outline Drawings (continued)
144-Pin TQFP
Dimensions are in millimeters.
22.00 ± 0.20
SE
L
D E
IS C
C T
O D
N E
TI VI
N C
U E
ED S
20.00 ± 0.20
PIN #1 IDENTIFIER ZONE
144
109
1
108
20.00
± 0.20
22.00
± 0.20
36
73
37
72
DETAIL A
DETAIL B
1.40 ± 0.05
1.60 MAX
SEATING PLANE
0.08
0.05/0.15
0.50 TYP
1.00 REF
0.25
0.106/0.200
GAGE PLANE
0.19/0.27
SEATING PLANE
0.45/0.75
DETAIL A
0.08
M
DETAIL B
5-3815r.5
178
Lattice Semiconductor
Data Sheet
November 2006
ORCA Series 2 FPGAs
Package Outline Drawings (continued)
160-Pin QFP
Dimensions are in millimeters.
31.20 ± 0.20
SE
L
D E
IS C
C T
O D
N E
TI VI
N C
U E
ED S
28.00 ± 0.20
PIN #1 IDENTIFIER ZONE
160
121
1
120
28.00
± 0.20
31.20
± 0.20
81
40
41
80
DETAIL A
DETAIL B
3.42 ± 0.25
4.07 MAX
SEATING PLANE
0.10
0.25 MIN
0.65 TYP
1.60 REF
0.13/0.23
0.25
GAGE PLANE
0.22/0.38
SEATING PLANE
0.12
M
0.73/1.03
DETAIL A
DETAIL B
5-2132r.12
Lattice Semiconductor
179
Data Sheet
November 2006
ORCA Series 2 FPGAs
Package Outline Drawings (continued)
208-Pin SQFP
Dimensions are in millimeters.
SE
L
D E
IS C
C T
O D
N E
TI VI
N C
U E
ED S
30.60 ± 0.20
28.00 ± 0.20
PIN #1 IDENTIFIER ZONE
208
157
1
156
28.00
± 0.20
30.60
± 0.20
105
52
53
104
DETAIL A
DETAIL B
3.40 ± 0.20
4.10 MAX
SEATING PLANE
0.08
0.50 TYP
0.25 MIN
1.30 REF
0.25
0.090/0.200
GAGE PLANE
SEATING PLANE
0.17/0.27
0.50/0.75
DETAIL A
0.10
M
DETAIL B
5-2196r.13
180
Lattice Semiconductor
Data Sheet
November 2006
ORCA Series 2 FPGAs
Package Outline Drawings (continued)
208-Pin SQFP2
Dimensions are in millimeters.
SE
L
D E
IS C
C T
O D
N E
TI VI
N C
U E
ED S
30.60 ± 0.20
28.00 ± 0.20
21.0 REF
PIN #1 IDENTIFIER ZONE
208
1.30 REF
157
156
0.25
GAGE PLANE
SEATING PLANE
21.0
REF
28.00
± 0.20
0.50/0.75
DETAIL A
30.60
± 0.20
0.090/0.200
0.17/0.2
105
53
0.10
M
DETAIL B
104
EXPOSED HEAT SINK APPEARS ON BOTTOM
SURFACE: CHIP BONDED FACE UP. (SEE DETAIL C.)
DETAIL A
DETAIL B
3.40 ± 0.20
4.10 MAX
SEATING PLANE
0.08
0.50 TYP
5-3828(F)
0.25 MIN
CHIP BONDED FACE UP
CHIP
COPPER HEAT SINK
DETAIL C (SQFP2 CHIP-UP)
Lattice Semiconductor
181
Data Sheet
November 2006
ORCA Series 2 FPGAs
Package Outline Drawings (continued)
240-Pin SQFP
Dimensions are in millimeters.
SE
L
D E
IS C
C T
O D
N E
TI VI
N C
U E
ED S
34.60 ± 0.20
32.00 ± 0.20
PIN #1 IDENTIFIER ZONE
240
181
1
180
32.00
± 0.20
34.60
± 0.20
121
60
61
120
DETAIL A
DETAIL B
3.40 ± 0.20
4.10 MAX
SEATING PLANE
0.08
0.50 TYP
0.25 MIN
1.30 REF
0.25
0.090/0.200
GAGE PLANE
SEATING PLANE
0.17/0.27
0.50/0.75
DETAIL A
0.10
M
DETAIL B
5-2718r.8
182
Lattice Semiconductor
Data Sheet
November 2006
ORCA Series 2 FPGAs
Package Outline Drawings (continued)
240-Pin SQFP2
Dimensions are in millimeters.
SE
L
D E
IS C
C T
O D
N E
TI VI
N C
U E
ED S
34.60 ± 0.20
32.00 ± 0.20
24.2 REF
240
1.30 REF
PIN #1 IDENTIFIER ZONE
181
1
180
0.25
GAGE PLANE
SEATING PLANE
24.2
REF
0.50/0.75
DETAIL A
32.00
± 0.20
34.60
± 0.20
0.090/0.200
0.17/0.27
0.10
M
DETAIL B
60
121
61
120
EXPOSED HEAT SINK APPEARS ON BOTTOM
SURFACE: CHIP BONDED FACE UP. (SEE DETAIL C.)
DETAIL B
DETAIL A
3.40 ± 0.20
4.10 MAX
SEATING PLANE
0.08
0.50 TYP
0.25 MIN
CHIP BONDED FACE UP
CHIP
COPPER HEAT SINK
DETAIL C (SQFP2 CHIP-UP)
Lattice Semiconductor
183
Data Sheet
November 2006
ORCA Series 2 FPGAs
Package Outline Drawings (continued)
256-Pin PBGA
Dimensions are in millimeters.
27.00 ± 0.20
SE
L
D E
IS C
C T
O D
N E
TI VI
N C
U E
ED S
+0.70
24.00 –0.00
A1 BALL
IDENTIFIER ZONE
+0.70
24.00 –0.00
27.00
± 0.20
MOLD
COMPOUND
PWB
1.17 ± 0.05
0.36 ± 0.04
2.13 ± 0.19
SEATING PLANE
0.20
SOLDER BALL
0.60 ± 0.10
19 SPACES @ 1.27 = 24.13
CENTER ARRAY
FOR THERMAL
ENHANCEMENT
A1 BALL
CORNER
Y
W
V
U
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
0.75 ± 0.15
19 SPACES
@ 1.27 = 24.13
1 2 3 4 5 6 7 8 9 10
12
11
14
13
16
15
18
17
20
19
5-4406r.6
184
Lattice Semiconductor
Data Sheet
November 2006
ORCA Series 2 FPGAs
Package Outline Drawings (continued)
304-Pin SQFP
Dimensions are in millimeters.
42.60 ± 0.20
SE
L
D E
IS C
C T
O D
N E
TI VI
N C
U E
ED S
40.00 ± 0.20
PIN #1 IDENTIFIER ZONE
304
229
1
228
40.00
± 0.20
42.60
± 0.20
76
153
77
152
DETAIL A
DETAIL B
3.40 ± 0.20
4.10 MAX
SEATING PLANE
0.08
0.50 TYP
0.25 MIN
1.30 REF
0.090/0.200
0.25
GAGE PLANE
0.17/0.27
SEATING PLANE
0.10
M
0.50/0.75
DETAIL A
DETAIL B
5-3307r.8
Lattice Semiconductor
185
Data Sheet
November 2006
ORCA Series 2 FPGAs
Package Outline Drawings (continued)
304-Pin SQFP2
Dimensions are in millimeters.
42.60 ± 0.20
SE
L
D E
IS C
C T
O D
N E
TI VI
N C
U E
ED S
40.00 ± 0.20
31.2 REF
PIN #1 IDENTIFIER ZONE
304
229
1
228
31.2
REF
40.00
± 0.20
42.60
± 0.20
76
153
77
152
EXPOSED HEAT SINK APPEARS ON
TOP SURFACE IN CHIP FACE-DOWN VERSION OR
BOTTOM SURFACE IN CHIP FACE-UP VERSION
DETAIL A
DETAIL B
3.40 ± 0.20
4.10 MAX
SEATING PLANE
0.08
0.50 TYP
0.25 MIN
1.30 REF
0.25
0.090/0.200
GAGE PLANE
0.17/0.27
SEATING PLANE
0.10
M
0.50/0.75
DETAIL A
DETAIL B
5-3827(F).r8
186
Lattice Semiconductor
Data Sheet
November 2006
ORCA Series 2 FPGAs
Package Outline Drawings (continued)
352-Pin PBGA
Dimensions are in millimeters.
35.00 ± 0.20
SE
L
D E
IS C
C T
O D
N E
TI VI
N C
U E
ED S
+0.70
30.00 –0.00
A1 BALL
IDENTIFIER ZONE
30.00
+0.70
–0.00
35.00
± 0.20
MOLD
COMPOUND
PWB
1.17 ± 0.05
0.56 ± 0.06
2.33 ± 0.21
SEATING PLANE
0.20
0.60 ± 0.10
SOLDER BALL
25 SPACES @ 1.27 = 31.75
CENTER ARRAY
FOR THERMAL
ENHANCEMENT
A1 BALL
CORNER
AF
AE
AD
AC
AB
AA
Y
W
V
U
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
0.75 ± 0.15
25 SPACES
@ 1.27 = 31.75
1 2 3 4 5 6 7 8 9 10
12 14 16 18 20 22 24 26
11 13 15 17 19 21 23 25
5-4407r.4
Lattice Semiconductor
187
Data Sheet
November 2006
ORCA Series 2 FPGAs
Package Outline Drawings (continued)
432-Pin EBGA
Dimensions are in millimeters.
40.00 ± 0.10
SE
L
D E
IS C
C T
O D
N E
TI VI
N C
U E
ED S
A1 BALL
IDENTIFIER ZONE
40.00
± 0.10
0.91 ± 0.06
1.54 ± 0.13
SEATING PLANE
0.20
SOLDER BALL
0.63 ± 0.07
30 SPACES @ 1.27 = 38.10
AL
AK
AJ
AH
AG
AF
AD
AB
Y
AE
0.75 ± 0.15
AC
AA
W
V
U
T
P
M
K
H
F
30 SPACES
@ 1.27 = 38.10
R
N
L
J
G
E
D
C
B
A
A1 BALL
CORNER
1
3
2
5
4
7
6
9
8
11
10
12
13 15 17 19 21 23 25 27 29 31
14 16 18 20 22 24 26 28 30
5-4409r.3
188
Lattice Semiconductor
Data Sheet
November 2006
ORCA Series 2 FPGAs
Ordering Information
OR2XXXX
X XX XXX X
XX
Packing Designator
DB = Dry Packed Tray
D = Dry Packed Tube
SE
L
D E
IS C
C T
O D
N E
TI VI
N C
U E
ED S
Device Family
OR2CXXA
OR2TXXA
OR2TXXB
Speed Grade
Package Type
BA = Plastic Ball Grid Array (PBGA)
BC = Enhanced Ball Grid Array (EBGA)
J = Quad Flat Pack (QFP)
M = Plastic Leaded Chip Carrier (PLCC)
PS = Power Quad Shrink Flat Package (SQFP2)
S = Shrink Quad Flat Package (SQFP)
T = Thin Quad Flat Package (TQFP)
Grade
Blank = Commercial
I = Industrial
Pin/Ball Count
Table 56. Ordering Information
Commercial
Device Family
OR2C04A
OR2C06A
OR2C08A
OR2C10A
Part Number
OR2C04A4M84-D2
OR2C04A4T100-DB2
OR2C04A4T144-DB2
OR2C04A4J160-DB2
OR2C04A4S208-DB2
OR2C06A4T100-DB2
OR2C06A4T144-DB2
OR2C06A4J160-DB2
OR2C06A4S208-DB2
OR2C06A4S240-DB2
OR2C06A4BA256-DB2
OR2C08A4J160-DB2
OR2C08A4S208-DB2
OR2C08A4S240-DB2
OR2C10A4J160-DB2
OR2C10A4S208-DB2
OR2C10A4BA256-DB2
OR2C10A4BA352-DB2
Lattice Semiconductor
Speed
Grade
Package
Type
Pin/Ball
Count
Grade
Packing
Designator
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
PLCC
TQFP
TQFP
QFP
SQFP
TQFP
TQFP
QFP
SQFP
SQFP
PBGA
QFP
SQFP
SQFP
QFP
SQFP
PBGA
PBGA
84
100
144
160
208
100
144
160
208
240
256
160
208
240
160
208
256
352
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
D
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
189
Data Sheet
November 2006
ORCA Series 2 FPGAs
Commercial
Device Family
OR2C12A4M84-D2
OR2C12A4S208-DB2
OR2C12A4S240-DB2
OR2C12A4BA256-DB2
OR2C12A4S304-DB2
OR2C12A4BA352-DB2
OR2C12A3S208-DB2
OR2C12A3S240-DB2
OR2C15A4M84-D2
OR2C15A4PS208-DB2
OR2C15A4S208-DB2
OR2C15A4S240-DB2
OR2C15A4BA256-DB2
OR2C15A4S304-DB2
OR2C15A4BA352-DB2
OR2C26A4PS208-DB2
OR2C26A4PS240-DB2
OR2C26A4PS304-DB2
OR2C40A4PS208-DB2
OR2C40A4PS240-DB2
OR2C40A4PS304-DB2
OR2T04A5T100-DB2
OR2T04A5T144-DB2
OR2T04A5S208-DB2
OR2T04A4T100-DB2
OR2T04A4T144-DB2
OR2T04A4S208-DB2
OR2T08A5J160-DB2
OR2T08A5S208-DB2
OR2T08A5S240-DB2
OR2T08A5BA256-DB2
OR2T08A4J160-DB2
OR2T08A4S208-DB2
OR2T08A4S240-DB2
OR2T08A4BA256-DB2
Speed
Grade
Package
Type
Pin/Ball
Count
Grade
Packing
Designator
4
4
4
4
4
4
3
3
4
4
4
4
4
4
4
4
4
4
4
4
4
5
5
5
4
4
4
5
5
5
5
4
4
4
4
PLCC
SQFP
SQFP
PBGA
SQFP
PLCC
SQFP
SQFP
PLCC
SQFP2
SQFP
SQFP
PBGA
SQFP
EBGA
SQFP2
SQFP2
SQFP2
SQFP2
SQFP2
SQFP2
TQFP
TQFP
SQFP
TQFP
TQFP
SQFP
QFP
SQFP
SQFP
PBGA
QFP
SQFP
SQFP
PBGA
84
208
240
256
304
352
208
240
84
208
208
240
256
304
352
208
240
304
208
240
304
100
144
208
100
144
208
160
208
240
256
160
208
240
256
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
D
DB
DB
DB
DB
DB
DB
DB
D
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
SE
L
D E
IS C
C T
O D
N E
TI VI
N C
U E
ED S
OR2C12A
Part Number
OR2C15A
OR2C26A
OR2C40A
OR2T04A
OR2T08A
190
Lattice Semiconductor
Data Sheet
November 2006
ORCA Series 2 FPGAs
Commercial
Device Family
OR2T10A5J160-DB2
OR2T10A5S208-DB2
OR2T10A5S240-DB2
OR2T10A5BA256-DB2
OR2T10A4J160-DB2
OR2T10A4S208-DB2
OR2T10A4S240-DB2
OR2T10A4BA256-DB2
OR2T15A7S208-DB
OR2T15A7S240-DB
OR2T15A7BA256-DB
OR2T15A7BA352-DB2
OR2T15A6M84-D
OR2T15A6S208-DB
OR2T15A6S240-DB
OR2T15A6BA256-DB
OR2T15A6BA352-DB2
OR2T15B8S208-DB2
OR2T15B8S240-DB2
OR2T15B8BA256-DB2
OR2T15B8BA352-DB2
OR2T15B7S208-DB2
OR2T15B7S240-DB2
OR2T15B7BA256-DB2
OR2T15B7BA352-DB2
OR2T26A7PS208-DB1
OR2T26A7S208-DB
OR2T26A7PS240-DB3
OR2T26A7BA352-DB2
OR2T26A7BC432-DB2
OR2T26A6PS208-DB1
OR2T26A6S208-DB
OR2T26A6PS240-DB3
OR2T26A6BA352-DB2
OR2T26A6BC432-DB2
OR2T40A7PS208-DB3
OR2T40A7PS240-DB3
OR2T40A7BA352-DB2
OR2T40A6PS208-DB3
OR2T40A6PS240-DB3
OR2T40A6BA352-DB2
Speed
Grade
Package
Type
Pin/Ball
Count
Grade
Packing
Designator
5
5
5
5
4
4
4
4
7
7
7
7
6
6
6
6
6
8
8
8
8
7
7
7
7
7
7
7
7
7
6
6
6
6
6
7
7
7
6
6
6
QFP
SQFP
SQFP
PBGA
QFP
SQFP
SQFP
PBGA
SQFP
SQFP
PBGA
PBGA
PLCC
SQFP
SQFP
PBGA
PBGA
SQFP
SQFP
PBGA
PBGA
SQFP
SQFP
PBGA
PBGA
SQFP2
SQFP
SQFP2
PBGA
EBGA
SQFP2
SQFP
SQFP2
PBGA
EBGA
SQFP2
SQFP2
PBGA
SQFP2
SQFP2
PBGA
160
208
240
256
160
208
240
256
208
240
256
352
84
208
240
256
352
208
240
256
352
208
240
256
352
208
208
240
352
432
208
208
240
352
432
208
240
352
208
240
352
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
D
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
SE
L
D E
IS C
C T
O D
N E
TI VI
N C
U E
ED S
OR2T10A
Part Number
OR2T15A
OR2T15B
OR2T26A
OR2T40A
Lattice Semiconductor
191
Data Sheet
November 2006
ORCA Series 2 FPGAs
Commercial
Device Family
OR2T40B8PS208-DB2
OR2T40B8BA352-DB2
OR2T40B8BC432-DB2
OR2T40B7PS208-DB2
OR2T40B7BA352-DB2
OR2T40B7BC432-DB2
Speed
Grade
Package
Type
Pin/Ball
Count
Grade
Packing
Designator
8
8
8
7
7
7
SQFP2
PBGA
EBGA
SQFP2
PBGA
EBGA
208
352
432
208
352
432
C
C
C
C
C
C
DB
DB
DB
DB
DB
DB
Speed
Grade
Package
Type
Pin/Ball
Count
Grade
Packing
Designator
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
TQFP
TQFP
SQFP
TQFP
TQFP
QFP
SQFP
SQFP
PBGA
QFP
SQFP
SQFP
QFP
SQFP
PBGA
QFP
SQFP
SQFP
SQFP
PBGA
SPBGA
PLCC
PLCC
SQFP
SQFP2
SQFP
SQFP2
PBGA
PBGA
100
144
208
100
144
160
208
240
256
160
208
240
160
208
256
352
84
208
240
256
304
352
84
208
208
240
240
256
352
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
D
DB
DB
DB
DB
DB
D
DB
DB
DB
DB
DB
DB
SE
L
D E
IS C
C T
O D
N E
TI VI
N C
U E
ED S
OR2T40B
Part Number
Industrial
Device Family
OR2C04A
OR2C06A
OR2C08A
OR2C10A
OR2C12A
OR2C15A
192
Part Number
OR2C04A3T100I-DB2
OR2C04A3T144I-DB2
OR2C04A3S208I-DB2
OR2C06A3T100I-DB2
OR2C06A3T144I-DB2
OR2C06A3J160I-DB2
OR2C06A3S208I-DB2
OR2C06A3S240I-DB2
OR2C06A3BA256I-DB2
OR2C08A3J160I-DB2
OR2C08A3S208I-DB2
OR2C08A3S240I-DB2
OR2C10A3J160I-DB2
OR2C10A3S208I-DB2
OR2C10A3BA256I-DB2
OR2C10A3BA352I-DB2
OR2C12A3M84I-D2
OR2C12A3S208I-DB2
OR2C12A3S240I-DB2
OR2C12A3BA256I-DB2
OR2C12A3S304I-DB2
OR2C12A3BA352I-DB2
OR2C15A3M84I-D2
OR2C15A3S208I-DB2
OR2C15A3PS208I-DB2
OR2C15A3S240I-DB2
OR2C15A3PS240I-DB2
OR2C15A3BA256I-DB2
OR2C15A3BA352I-DB2
Lattice Semiconductor
Data Sheet
November 2006
ORCA Series 2 FPGAs
Industrial
Device Family
OR2C26A
Part Number
OR2C26A3PS208BI-DB2
OR2C26A3PS208I-DB2
Package
Type
Pin/Ball
Count
Grade
Packing
Designator
3
3
4
3
3
3
4
3
3
4
4
4
4
4
4
4
4
4
4
4
6
6
6
7
7
7
7
6
6
6
6
6
6
6
6
7
7
7
SQFP2
SQFP2
SQFP2
SQFP2
SQFP2
SQFP2
SQFP2
SQFP2
SQFP2
TQFP
TQFP
SQFP
QFP
SQFP
SQFP
PBGA
QFP
SQFP
SQFP
PBGA
SQFP
SQFP
PBGA
SQFP
SQFP
PBGA
PBGA
SQFP2
SQFP
SQFP2
PBGA
EBGA
SQFP2
SQFP2
PBGA
SQFP2
PBGA
EBGA
208
208
208
240
304
208
208
240
304
100
144
208
160
208
240
256
160
208
240
256
208
240
352
208
240
256
352
208
208
240
352
432
208
240
352
208
352
432
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
SE
L
D E
IS C
C T
O D
N E
TI VI
N C
U E
ED S
OR2C26A4PS208I-DB2
OR2C26A3PS240I-DB2
OR2C26A3PS304I-DB2
OR2C40A3PS208I-DB2
OR2C40A4PS208I-DB2
OR2C40A3PS240I-DB2
OR2C40A3PS304I-DB2
OR2T04A4T100I-DB2
OR2T04A4T144I-DB2
OR2T04A4S208I-DB2
OR2T08A4J160I-DB2
OR2T08A4S208I-DB2
OR2T08A4S240I-DB2
OR2T08A4BA256I-DB2
OR2T10A4J160I-DB2
OR2T10A4S208I-DB2
OR2T10A4S240I-DB2
OR2T10A4BA256I-DB2
OR2T15A6S208I-DB
OR2T15A6S240I-DB
OR2T15A6BA352I-DB2
OR2T15B7S208I-DB2
OR2T15B7S240I-DB2
OR2T15B7BA256I-DB2
OR2T15B7BA352I-DB2
OR2T26A6PS208I-DB1
OR2T26A6S208I-DB
OR2T26A6PS240I-DB3
OR2T26A6BA352I-DB2
OR2T26A6BC432I-DB2
OR2T40A6PS208I-DB3
OR2T40A6PS240I-DB3
OR2T40A6BA352I-DB2
OR2T40B7PS208I-DB2
OR2T40B7BA352I-DB2
OR2T40B7BC432I-DB2
Speed
Grade
OR2C40A
OR2T04A
OR2T08A
OR2T10A
OR2T15A
OR2T15B
OR2T26A
OR2T40A
OR2T40B
1. Converted to S208 package device per PCN#11A-06
2. Discontinued per PCN #02-06. Contact Rochester Electronics for available inventory.
3. Discontinued per PCN #06-07. Contact Rochester Electronics for available inventory.
Lattice Semiconductor
193
Data Sheet
November 2006
SE
L
D E
IS C
C T
O D
N E
TI VI
N C
U E
ED S
ORCA Series 2 FPGAs
194
Lattice Semiconductor
ORCA Series 2 FPGAs
SE
L
D E
IS C
C T
O D
N E
TI VI
N C
U E
ED S
Data Sheet
November 2006
Lattice Semiconductor
195
SE
L
D E
IS C
C T
O D
N E
TI VI
N C
U E
ED S
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November 2006
DS99-094FPGA (Replaces DS98-022FPGA)