Product Brief December 2005 ORCA® Series 2 Field-Programmable Gate Arrays Features ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ High-performance, cost-effective, low-power 0.35 μm CMOS technology (OR2CxxA), 0.3 μm CMOS technology (OR2TxxA), and 0.25 μm CMOS technology (OR2TxxB), (four-input look-up table (LUT) delay less than 1.0 ns with -8 speed grade) High density (up to 43,200 usable, logic-only gates; or 99,400 gates including RAM) Up to 480 user I/Os (OR2TxxA and OR2TxxB I/Os are 5 V tolerant to allow interconnection to both 3.3 V and 5 V devices, selectable on a per-pin basis) Four 16-bit look-up tables and four latches/flip-flops per PFU, nibble-oriented for implementing 4-, 8-, 16-, and/or 32-bit (or wider) bus structures Eight 3-state buffers per PFU for on-chip bus structures Fast on-chip user SRAM has features to simplify RAM design and increase RAM speed: — Asynchronous single port: 64 bits/PFU — Synchronous single port: 64 bits/PFU — Synchronous dual port: 32 bits/PFU Improved ability to combine PFUs to create larger RAM structures using write-port enable and 3-state buffers Fast, dense multipliers can be created with the multiplier mode (4 x 1 multiplier/PFU): — 8 x 8 multiplier requires only 16 PFUs — 30% increase in speed Flip-flop/latch options to allow programmable priority of synchronous set/reset vs. clock enable Enhanced cascadable nibble-wide data path capabilities for adders, subtractors, counters, multipliers, and comparators including internal fast-carry operation ■ ■ ■ ■ ■ ■ ■ ■ ■ Innovative, abundant, and hierarchical nibbleoriented routing resources that allow automatic use of internal gates for all device densities without sacrificing performance Upward bit stream compatible from the ORCA ATT2Cxx/ ATT2Txx series of devices Pinout-compatible with new ORCA Series 3 FPGAs TTL or CMOS input levels programmable per pin for the OR2CxxA (5 V) devices Individually programmable drive capability: 12 mA sink/6 mA source or 6 mA sink/3 mA source Built-in boundary scan (IEEE † 1149.1 JTAG) and TS_ALL testability function to 3-state all I/O pins. Multiple configuration options, including simple, low pincount serial ROMs, and peripheral or JTAG modes for insystem programming (ISP) Full PCI bus compliance for all devices Supported by industry-standard CAE tools for design entry, synthesis, and simulation with ORCA Foundry Development System support (for back-end implementation) New added features (OR2TxxB) provide: — More I/O per package than the OR2TxxA family. — No dedicated 5 V supply (VDD5). — Faster configuration speed (40 MHz). — Full PCI bus compliance in both 5 V and 3.3 V PCI systems. Pin selectable I/O clamping diodes provide 5 V or 3.3 V PCI compliance and 5 V tolerance. * IEEE is a registered trademark of The Institute of Electrical and Electronics Engineers, Inc. Table 1. ORCA Series 2 FPGAs Device Usable Gates* LUTs Registers Max User RAM Bits User I/Os Array Size OR2C04A/OR2T04A OR2C06A/OR2T06A OR2C08A/OR2T08A OR2C10A/OR2T10A OR2C12A/OR2T12A OR2C15A/OR2T15B OR2C26A/OR2T26A OR2C40A/OR2T40A/OR2T40B 4,800—11,000 6,900—15,900 9,400—21,600 12,300—28,300 15,600—35,800 19,200—44,200 27,600—63,600 43,200—99,400 400 576 784 1024 1296 1600 2304 3600 400 576 724 1024 1296 1600 2304 3600 6,400 9,216 12,544 16,384 20,736 25,600 36,864 57,600 160 192 224 256 288 320 384 480 10 x 10 12 x 12 14 x 14 16 x 16 18 x 18 20 x 20 24 x 24 30 x 30 * The first number in the usable gates column assumes 48 gates per PFU (12 gates per four-input LUT/FF pair) for logic-only designs. The second number assumes 30% of a design is RAM. PFUs used as RAM are counted at four gates per bit, with each PFU capable of implementing a 16 x 4 RAM (or 256 gates) per PFU. Product Brief December 2005 ORCA Series 2 FPGAs ize any four-, five-, or six-input logic functions. In ripple mode, the high-speed carry logic is used for arithmetic functions, the multiplier function, or the enhanced data path functions. In memory mode, the LUTs can be used as a 16 x 4 read/write or read-only memory (asynchronous mode or synchronous mode) or a 16 x 2 dual-port memory. Description The ORCA Series 2 series of SRAM-based FPGAs are an enhanced version of the ATT2C/2T architecture. The latest ORCA series includes patented architectural enhancements that make functions faster and easier to design while conserving the use of PLCs and routing resources. The PLC architecture provides a balanced mix of logic and routing that allows a higher utilized gate/PFU than alternative architectures. The routing resources carry logic signals between PFUs and I/O pads. The routing in the PLC is symmetrical about the horizontal and vertical axes. This improves routability by allowing a bus of signals to be routed into the PLC from any direction. The Series 2 devices can be used as drop-in replacements for the ATT2Cxx/ATT2Txx series, respectively, and they are also bit stream compatible with each other. The usable gate counts associated with each series are provided in Table 1. All devices are offered in a variety of packages, speed grades, and temperature ranges. Each PIC (shown in Figures 2A and 2B) is comprised of I/O drivers, I/O pads, and routing resources. Each I/O can be programmed to be either an input, output, or bidirectional signal. Other options include variable output slew rates and pull-up or pull-down resistors. ORCA FPGAs consist of two basic elements: programmable logic cells (PLCs) and programmable input/output cells (PICs). An array of PLCs is surrounded by PICs as shown in Figure 1. Each PLC contains a programmable function unit (PFU). The PLCs and PICs also contain routing resources and configuration RAM. All logic is done in the PFU. Each PFU contains four 16-bit look-up tables (LUTs) and four latches/flip-flops (FFs). OR2TxxA and OR2TxxB I/Os are 5 V tolerant to allow interconnection to both 3.3 V and 5 V devices, selectable on a per-pin basis. The LUTs can be programmed to operate in one of three modes: combinatorial, ripple, or memory. In combinatorial mode, the LUTs can be programmed to realCOUT CARRY A4 A4 A3 A2 A3 QLUT3 C A1 F3 WD3 REG3 CARRY A1 A3 A2 A1 A0 Q3 D3 A2 C PFU_NAND QLUT2 SR F2 O4 Q2 D2 A4 A0 O3 REG2 WD2 C CARRY B4 B4 B3 B2 B3 B1 B0 O1 Q1 D1 C SR EN PFU_XOR C F0 Q0 D0 QLUT0 WD0 B4 C T T T T T T T T C C REG0 EN C C0 LSR GSR O0 REG1 WD1 SR CIN O2 EN F1 PFU_MUX QLUT1 CARRY B3 B2 B0 SR B1 B2 B1 EN C WD[3:0] C CK CKEN TRI 5-4573(F) Figure 1. PFU Block Diagram 2 Lattice Semiconductor Product Brief December 2005 ORCA Series 2 FPGAs Description (continued) VDD PULL-UP DELAY dintb, dinlr in TTL/CMOS POLARITY PAD TRI DOUT/OUT SLEW RATE POLARITY PULL-DOWN 5-4591(F) A. Simplified Diagram of OR2CxxA Programmable I/O Cell VDD PULL-UP DELAY dintb, dinlr in PAD POLARITY TRI DOUT/OUT SLEW RATE POLARITY PULL-DOWN 5-4591.T(F) B. Simplified Diagram of OR2TxxA/OR2TxxB Programmable I/O Cell Figure 2. Series 2 Diagrams Lattice Semiconductor 3 Product Brief December 2005 ORCA Series 2 FPGAs Description (continued) The ORCA Foundry Development System is used to process a design from a netlist to a configured FPGA. This system is used to map your design onto the ORCA architecture and then place and route it using ORCA Foundry’s timing-driven tools. The development system also includes interfaces and libraries to popular CAE tools for design entry, synthesis, and simulation. Some examples of the resources required and the performance that can be achieved using these devices are represented in Table 2. The FPGA’s functionalitiy is determined by internal configuration RAM. The FPGA’s internal initialization/configuration circuitry loads the configuration data at powerup or under system control. The RAM is loaded by using one of several configuration modes. The configuration data resides externally in an EEPROM, EPROM, or ROM on the circuit board, or any other storage media. Serial ROMs provide a simple, low pin count method for configuring FPGAs, while the peripheral and JTAG configuration modes allow for easy, in-system programming (ISP). Table 2. ORCA Series 2 System Performance Function 16-bit Loadable Up/Down Counter 16-bit Accumulator 8 x 8 Parallel Multiplier: Multiplier Mode, Unpipelined1 ROM Mode, Unpipelined2 Multiplier Mode, Pipelined3 32 x 16 RAM (synchronous): Single Port (read and write/ cycle)4 Single Port5 Dual Port6 36-bit Parity Check (internal) 32-bit Address Decode (internal) Speed Grade # PFUs -2A -3A -4A -5A -6A -7A -7B -8B 4 4 51.0 51.0 66.7 66.7 87.0 87.0 104.2 104.2 129.9 129.9 144.9 144.9 131.6 131.6 149.3 149.3 MHz MHz 22 9 44 14.2 41.5 50.5 19.3 55.6 69.0 25.1 71.9 82.0 31.0 87.7 103.1 36.0 107.5 125.0 40.3 122.0 142.9 37.7 103.1 123.5 44.8 120.5 142.9 MHz MHz MHz 9 9 16 21.8 38.2 38.2 28.6 52.6 52.6 36.2 69.0 83.3 45.5 86.2 90.9 53.8 92.6 92.6 62.5 96.2 96.2 57.5 97.7 97.7 69.4 112.4 112.4 MHz MHz MHz 4 3.25 13.9 12.3 11.0 9.5 9.1 7.5 7.4 6.1 5.6 4.6 5.2 4.3 6.1 4.8 5.1 4.0 ns ns Unit 1. 2. 3. 4. Implemented using 4 x 1 multiplier mode (unpipelined), register-to-register, two 8-bit inputs, one 16-bit output. Implemented using two 16 x 12 ROMs and one 12-bit adder, one 8-bit input, one fixed operand, one 16-bit output. Implemented using 4 x 1 multiplier mode (fully pipelined), two 8-bit inputs, one 16-bit output (28 of 44 PFUs contain only pipelining registers). Implemented using 16 x 4 synchronous single-port RAM mode allowing both read and write per clock cycle, including write/read address multiplexer. 5. Implemented using 16 x 4 synchronous single-port RAM mode allowing either read or write per clock cycle, including write/read address multiplexer. 6. Implemented using 16 x 2 synchronous dual-port RAM mode. 7. OR2TxxB available in -7 and -8 speeds only. 4 Lattice Semiconductor Product Brief December 2005 ORCA Series 2 FPGAs Ordering Information Example: OR2C12A-4 S 240 TEMPERATURE RANGE DEVICE TYPE SPEED GRADE NUMBER OF PINS PACKAGE TYPE OR2C12A, -4 speed grade, 240-pin shrink quad flat pack, commercial temperature. Table 3. FPGA Voltage Options Device OR2CxxA OR2TxxA OR2TxxB Table 5. FPGA Package Options Voltage 5.0 V 3.3 V 3.3 V Table 4. FPGA Temperature Options Symbol (Blank) I Description Commercial Industrial Lattice Semiconductor Temperature 0 °C to 70 °C –40 °C to +85 °C Symbol BA BC J M PS S T Description Plastic Ball Grid Array (PBGA) Enhanced Ball Grid Array (EBGA) Quad Flat Package (QFP) Plastic Leaded Chip Carrier (PLCC) Power Quad Shrink Flat Package (SQFP2) Shrink Quad Flat Package (SQFP) Thin Quad Flat Package (TQFP) 5 Product Brief December 2005 ORCA Series 2 FPGAs Ordering Information (continued) Table 6. ORCA OR2CxxA/OR2TxxA Series Package Matrix Packages OR2C/2T04A OR2C/2T06A OR2C/2T08A OR2C/2T10A OR2C/2T12A OR2C15A OR2C/2T26A OR2C/2T40A 84-Pin PLCC 100-Pin TQFP 144-Pin TQFP 160-Pin QFP M84 CI CI CI CI CI CI — — T100 CI CI — — — — — — T144 CI CI — — — — — — J160 CI CI CI CI — — — — 208-Pin EIAJ SQFP/ SQFP2 S208/ PS208 CI CI CI CI CI CI CI CI 240-Pin EIAJ SQFP/ SQFP2 S240/ PS240 — CI CI CI CI CI CI CI 208-Pin EIAJ SQFP/ SQFP2 S208/ PS208 CI CI 240-Pin EIAJ SQFP/ SQFP2 S240/ PS240 CI CI 256-Pin PBGA BA256 — CI CI CI CI CI — — 304-Pin EIAJ SQFP/ SQFP2 S304/ PS304 — — — — CI CI CI CI 352-Pin PBGA 432-Pin EBGA BA352 — — — CI CI CI CI CI BC432 — — — — — CI CI CI 352-Pin PBGA 432-Pin EBGA BA352 CI CI BC432 — CI Key: C = commercial, I = industrial. Table 7. ORCA OR2TxxB Series Package Matrix Packages OR2T15B OR2T40B 84-Pin PLCC 100-Pin TQFP 144-Pin TQFP 160-Pin QFP M84 — — T100 — — T144 — — J160 — — 256-Pin PBGA BA256 CI — 304-Pin EIAJ SQFP/ SQFP2 S304/ PS304 — — Key: C = commercial, I = industrial. Notes: The package options with the SQFP/SQFP2 designation in the table above use the SQFP package for all densities up to and including the OR2C/T15B, while the OR2C/T26A and the OR2C/2T40A/B use the SQFP2. The OR2TxxA and OR2TxxB series is not offered in the 304-pin SQFP/SQFP2 packages. The OR2C40A is not offered in a 352-pin PBGA. www.latticesemi.com Copyright © 2005 Lattice Semiconductor All Rights Reserved December 2005 PN99-072FPGA_A