ispPAC20 Brochure - Lattice Semiconductor

IN-SYSTEM PROGRAMMABLE MIXED SIGNAL CIRCUIT
ispPAC20
Introduction to ispPAC20
A P P L I C AT I O N S
Ease of design and flexibility? You can have both, together,
while implementing your mixed signal circuit on a single
chip. If you want to change parameters, just reprogram the
chip. No hassle of discrete components, no layout issues.
Your analog circuit is instantaneously manufacturable.
That’s what you get with the revolutionary ispPAC®20.
Fast P-I Loop – Laser Bias Control
Multiple Voltage Monitoring
Programmable VCO, PWM
Data Acquisition
Industrial Automation and Control
Signal Amplification, Summation,
Filtering, Subtraction, Integration
Sensor Signal Conditioning
IA
OA
IA
CP
Automated Test and Measurement
IA
OA
IA
Medical and Scientific Analyzers
CP
Key Features and Benefits
■
Analog Routing Pool
E2CMOS Mem
Reference
Auto-Cal
ISP Control
In-System Programmable/Reprogrammable
• Easily Adapts to Design Changes
• Adjust Analog System Tolerances at Final Test
DAC
• Field Upgrade of Functionality/Parametrics via Software
• No External Components Needed for Configuration
ispPAC20 Block Diagram
Programmable
Analog
• Dynamic Setpoint for Control Loops and Voltage
Monitoring
How to Implement Circuits in ispPAC20
The ispPAC20 has four programmable-gain instrumentation
amplifiers, two continuous-time capacitor arrays with 128
values, two differential output amplifiers, two comparators,
an 8-bit DAC and an analog routing pool to implement
your circuit. PAC-Designer® is an intuitive point-and-click
software program with powerful utilities for creating,
simulating and in-system programming your circuit into the
on-chip E2 memory of the ispPAC20 device.
■
Two PACblocks, Two Comparators, 8-Bit DAC
• Programmable Gain from 0 to 40dB
• Precision 2nd Order, Continuous-Time Filters up to
100kHz
• Summing and Subtracting Analog Signals
• Precision Voltage References and Trip Points
• On-Chip Offset Calibration
• Programmable Integration Time Constant
• Window Comparator
Easy-to-Use PAC-Designer Software Offers a Fully-Integrated
Design and Simulation Environment for ispPAC Device Design
■
Non Volatile E2CMOS®
■
IEEE 1149.1 JTAG Serial Programming
■
SPI Interface for Dynamic DAC Updates
■
44-Pin TQFP and PLCC Packages
■
Single Supply 5V Operation
ispPAC20 Key Specifications
TA = 25°C; VS = 5.0V; Signal Path = VIN to VOUT of one PACblock™; 1V ≤ VOUT ≤ 4V; Gain = 1. Feedback enabled; Auto-Cal initiated prior
(unless otherwise specified).
SYMBOL
PARAMETER
CONDITION
MIN.
TYP.
MAX.
UNITS
20
0.2
4
100
1
V
µV
mV
4.9
V
20
4
dB
%
±0.5
LSB
Analog Input
VIN±
VOS
Input Voltage Range
Differential Offset Voltage (Input Referred)
1
G = 10
G=1
Analog Output
VOUT±
Voltage Output Range (Feedback Open)
Present at either VOUT+ or VOUT-
0.1
Each Individual PACblock
RL = 300Ω Differential
0
Static Performance
G
Programmable Gain Range
Gain Error
1.5
Digital-to-Analog Converter
INL
Integral Non-linearity Error
8-bit DAC
Comparator
tp
Propagation Delay
Overdrive = 10mV
Overdrive = 100mV
ns
ns
Small Signal BW vs. Gain
Filter FC Accuracy
21
50
2000 Units
PDIP Pkg
Fc = 46.46kHz
G = 10
15
G=5
9
40
30
Gain (dB)
Percentage of Devices (%)
750
150
20
3
G=2
-3
G=1
-9
-15
-21
10
-27
-33
0
-4
-3
-2
-1
0
1
2
3
4
Frequency Variation (%)
Also Available
ispPAC10 Device – In-System Programmable Analog Circuit
ispPAC80 Device – Programmable Analog 5th-Order Filter
PAC-Designer Software
ispPAC Evaluation Boards
PAC System Design Kits
-39
1k
10k
100k
1M
10M
Frequency (Hz)
For More Information
www.latticesemi.com
Applications Support
1-800-LATTICE (528-8423)
(503) 268-8000
[email protected]
Copyright © 2001 Lattice Semiconductor Corporation. Lattice Semiconductor, L (stylized) Lattice Semiconductor Corp., and Lattice (design), ISP, ispPAC,
PAC-Designer, PACblock, PACell and E2CMOS are either registered trademarks or trademarks of Lattice Semiconductor Corporation in the United States and/or
other countries. Other product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
June 2001
Order #: I0126