Data Sheet Revision History ispPAC-CLK5510/5520 Date Version June, 2004 Aug 13/2004 Aug 13/2004 Aug 13/2004 -02 -04 -04 -04 Aug 13/2004 -04 Aug 13/2004 Aug 13/2004 Aug 13/2004 Aug 13/2004 Aug 13/2004 Aug 13/2004 Aug 13/2004 Aug 13/2004 Aug 13/2004 Oct 1,2004 Oct 1,2004 Oct 1,2004 Oct 1,2004 Oct 1,2004 Oct 1,2004 Oct 1,2004 Oct 1,2004 Oct 1,2004 Feb 4,2005 Feb 4,2005 Feb 22,2005 Mar 11,2005 -04 -04 -04 -04 -04 -04 -04 -04 -04 -05 -05 -05 -05 -05 -05 -05 -05 -05 -06 -06 -06.1 -06.2 Page Change Summary Original Prelim Release to Web Final Datasheet release to Web Max current added for 5510 100 Ohm/5pF load notation added for LVDS 5 5 5,8,9,22, ~20 Ohm notation replaces <40 Ohm setting for output termination 23 10 Altered Max Period Jitter Spec 15,16 NxV Max value extended from 32 to 64 19 Added differential SSTL receiver configuration graphic 24 Altered 5510 Temperature Derating Curves for single ended operation 24 Added Temperature Derating Curves for LVDS operation 27 Added Skew Matching Accuracy section 29 Added Reset and power up functional description 30 Edited Eval Board part number 36,42 Pin Names changed for 5510 6 Input Capacitance Spec broken out for Reference inputs versus control inputs 7 Rise/Fall time values updated 8 Output Test loads clarified, Figs 3,4,5 updated 9 Input/Output Termination resistance table updated 15 Additional Explanation of Lock Detector Behavior 16 Added graph of PLL loop bandwidth versus feedback multiplication factor 18 Output duty cycle tables restructured 19-20 New Section on Output timing relationships 24 Reference to Differential HSTL output capability clarified 9 Output Impedance table modified 14-15 Jitter Performance Vs VCO Freq graphs added 10 Typical Phase Jitter & Static phase offset parameters added 36, 39 Figure 30 Changed data register from 90 to 89, JTAG ID Code for ispPAC-CLK5510 corrected Signed