The Next Generation of FPGAs ispXPGA TM Non-Volatile Infinitely Reconfigurable Instant-on FPGAs You know Lattice as a supplier of the world’s biggest, Non-volatile and infinitely reconfigurable. It’s both! fastest, widest, and lowest-power ispMACH™ Welcome to the eXpanded Field Programmable CPLDs, the revolutionary ispXPLD™ family, Gate Array — the Instant-On ispXPGA! the unique ispGDX® crosspoint switch ispXPGA devices offer a unique set of and ispPAC® programmable analog advantages: families, and ispGAL® SPLDs. Now • Non-Volatile/Reprogrammable in E2 we’re adding a line of unique FPGAs in • Infinitely Reconfigurable in SRAM order to support you with the widest range of programmable ICs on the market. • Self-Configures in Microseconds at Power-Up for “Instant-On” Availability More programmability means quicker time-to- • Secure — No External Bitstream market for you. ispXPGA Family Family Member System Gates PFUs LUT-4 Logic FFs Block RAM Distributed sysHSI™* User RAM Channels I/O ispXPGA 125/E 139K 484 1936 3.8K 92K 30K 4 160 176 1.8, 2.5, 3.3V 256 fpBGA 17x17mm 516 fpBGA** 31x31mm ispXPGA 200/E 210K 676 2704 5.4K 111K 43K 8 160 208 1.8, 2.5, 3.3V 256 fpBGA 17x17mm 516 fpBGA** 31x31mm ispXPGA 500/E 476K 1764 7056 14.1K 184K 112K 12 336 336 1.8, 2.5, 3.3V 516 fpBGA** 31x31mm 900 fpBGA 31x31mm ispXPGA 1200/E 1.25M 3844 15376 30.8K 414K 246K 20 496 496 1.8, 2.5, 3.3V 680 fpSBGA** 40x40mm 900 fpBGA 31x31mm Vcc Packaging Body Size * “E” series does not support sysHSI. ** Thermally enhanced ispXPGA Programming and Configuration The ispXPGA family of devices takes a unique approach to FPGA configuration memory. ispXPGA devices contain two types of memory, Static RAM and non-volatile E2CMOS® cells. The static RAM is used to control the functionality of the device during normal operation and the E2CMOS memory cells are used to load the SRAM. The SRAM is configured either from the E2CMOS memory or from an external source. We call this concept ispXP™, for eXpanded Programmability. The ispXPGA family is available in two options. The standard device supports sysHSI capability for ultra fast serial communications and the “E” series, a high performance, low cost device with no sysHSI functionality. E2 Nonvolatility + SRAM Reconfigurability = ■ Logic available to system power-up sequence in 200 µs ■ High security - no external bitstream for configuration ispXPGA Configuration Modes Port Mode ISP 1149.1 JTAG TAP ISP Background sysCONFIG™ Peripheral Port sysCONFIG P1532 Configuration in Milliseconds Memory Space ■ ■ E2PROM Memory Space Programming in Seconds Power Up Refresh Download in Microseconds SRAM Memory Space Single-chip solution for reduced inventory, handling, and manufacturing costs No external SPROM noise, reliability, or board-space concerns ispXPGA Architecture ispXPGA Block Diagram sysMEM Blocks • Up to 414Kb of Dedicated Memory per ispXPGA • Configurable as Single- or Dual-Port, FIFO, or ROM • 512x9 Bits or 256x18 Bits • Cascadable Width and Depth Programmable Function Units • Up to 3,844 High Speed Logic Blocks • Four LUT-4 per PFU • Dual Flip-Flops per LUT-4 for Extensive Pipelining • Dedicated Logic for Adders Multipliers, Multiplexers, and Counters • Distributed Memory sysCLOCK PLL • 8 Phase Locked Loops • 10MHz to 320MHz • Clock Mutiplication and Division • Phase Adjustment • Shift Clocks in 325ps Steps sysIO High Speed I/Os sysHSI Blocks* • • • • Ultra Fast SERDES Up to 800Mbps Performance Clock Data Recovery Up to 20 Channels per Device • Up to 496 I/Os • High Speed Memory Support: SSTL and HSTL • Bus Support: PCI, PCI-X, GTL+, LVDS and LVPECL • Standard Logic Support: LVTTL, LVCMOS 3.3, 2.5 and 1.8 *Not available with “E” series. Programmable I/O Cells Programmable Function Unit The Programmable Function Unit (PFU) is the basic building block of the ispXPGA architecture. Each PFU consists of four Configurable Logic Elements (CLEs), four Configurable Sequential Elements (CSEs), and a Wide Logic Generator (WLG). By utilizing these components, the PFU can implement a variety of functions. Programmable Function Unit Block Diagram 12 Control Logic COUT(r,c) From 5 Routing CLE 0 Carry LUT-4 Logic From 5 Routing CLE 1 Carry LUT-4 Logic From 5 Routing CLE 2 Carry LUT-4 Logic 5 From 5 Routing CLE 3 Carry LUT-4 Logic 5 5 2 CSE 0 FF 2 FF 5 Wide Logic Generator From Routing 2 CSE 1 FF 2 FF 2 CSE 2 FF 2 FF 2 CSE 3 FF FF To Routing To Routing To Routing PFU Features ■ Input Switch Matrix signals from global, general, direct-connect, and feedback routing paths – Up to 24 go to PFU ■ Multiplexer Mode uses PFU as four 2:1 muxes, two 4:1 muxes, or one 8:1 mux, cascadable for 16:1 mux ■ LUT/Carry can also be 8-bit shift register, up to 32-bits in a PFU, cascadable ■ PFU’s four LUT-4s configurable as two LUT-5s or one LUT-6, cascadable to LUT-7s – Partial functions up to 20 inputs achievable ■ Wide-gating via carry chain offers 16-input OR, AND, NOR, and NAND functions, or 2-bit comparators. ■ Arithmetic Mode for 4-bit adder/subtractor, magnitude comparator, or up/down pre-loadable counter ■ 2 Flip-Flops per LUT for efficient pipelining and register retiming by synthesis tools ■ Output Switch Matrix optimally connects PFU outputs to ispXPGA routing resources ■ Memory Mode configurations – Single-port 64 bits – Dual-port 32 bits 2 To Routing ■ Set and Reset signals common to PFU’s 8 FFs ■ Clocks from up to 12 sources with polarity control Memory Routing Resources The ispXPGA architecture provides a large amount of resources for memory intensive applications. Embedded Block RAMs (EBRs) are available to complement the Distributed Memory that is configured in the PFUs. Each memory element can be configured as RAM or ROM. Additionally, the internal logic of the device can be used to configure the memory elements as FIFO and other storage types. These EBRs are referred to as sysMEM™ blocks. The ispXPGA architecture contains a highly flexible routing technology to connect the PFUs, PICs, and EBRs in the device. The ispXPGA’s superior routing resources are optimized for fittability and performance and allow signals to be routed to any element in the device with the optimal delay. DECA (40) Double (32) Long (8) Global Lines (5) Direct + Feedback (14 + 4) PFU sysMEM Embedded Block RAM (EBR) ■ ■ Configure using ispLEVER™ software’s Memory Compiler 4K-bit blocks usable as Single-Port, Dual-Port, FIFO, or ROM ■ Byte or Word organization plus parity bit per byte ■ Cascade for more depth or width SB B Access times under 3 ns ■ sysMEM Modes of Operation - Single-Port Synchronous Read/Write - Single-Port Synchronous Write/Asynchronous Read - Single-Port Synchronous Write/Synchronous Read - Dual-Port Synchronous Read/Write - Dual-Port Synchronous Write/Asynchronous Read - Dual-Port Synchronous Write/Synchronous Read SB SB Input p t M Mu Mux PFU SB B Input p Mu Mux SB B Input p Mu Mux Input p t M Mu Mux SB B Input p Mu Mux SB B Input p t M Mu Mux PFU SB B Input p t M Mu Mux Input p Mu Mux PFU SB B Input p Mu Mux PFU SB B Input p t M Mu Mux Direct Long (8) Double (32) DECA (40) Inp putt p Mu ux PFU SB B Input p t M Mu Mux SB SB Input p t M Mu Mux PFU SB B PFU PFU PFU PFU SB B SB SB Input p t M Mu Mux PFU PFU SB B ■ Input p t Mu Mux PFU PFU PFU SB B Input p Mu Mux PFU Interconnect Options sysMEM Dual Port SRAM Port A Read/Write Address 8-9 RWCLKENA RWCLKA Read/ Write Port Logic Dual-Port SRAM • 4.5K bits • 256 x 18 • 512 x 9 Reg Read/ Write Port Logic Reg Port B 8-9 Read/Write Address 9 or 18 Read/Write Data RWCLKENB RWCLKB 9 or 18 Read/Write Data Distributed Memory ■ ■ ■ ■ From a starting PFU, one can reach a cluster of 8 surrounding PFUs (up, down, left, right, diagonal) using Direct Connects /WENB OEB /WENA OEA Configuration Single-port Dual-port Shift Register Feed back signals within a PFU without using any external routing resources 8x1 16x1 16x2 32x1 32x2 64x1 – 4 2 2 1 1 – 2 1 1 – – 4 2 – 1 – – Distributed Memory Mode of PFU’s LUT PFU inputs become Address, Data, Write Enable and Clock Single-Port Synchronous Write/Synchronous Read Up to 64 SRAM bits per PFU - Single-port or Dual-port RAM - 8-bit shift register per LUT; 32-bit per PFU Long Connects (not shown here) traverse the whole chip horizontally and vertically From a starting PFU Double Connects reach up to 2 PFUs away From a starting PFU Deca Connects reach up to 10 PFUs away Programmable I/O Cells sysIO™ High Speed I/O The Programmable Input/Output Cell (PIC) is an essential part of the symmetrical architecture of the ispXPGA Family. The PICs interface the PFUs and EBRs to the sysIO and sysHSI blocks of the device. Each PIC contains two Programmable Input/Outputs (PIOs) with a total of 21 inputs and 10 outputs. Four outputs of the PIC connect to routing and two outputs are available as Output Enables for the tristatable Long Lines. The remaining four outputs feed the sysIO buffers directly (one output enable and one output to each). Each PIC associated with a sysHSI block has four additional inputs and six additional outputs to support the sysHSI blocks. ispXPGA devices offer up to eight sysIO banks. Each sysIO bank is capable of supporting multiple I/O standards and has its own I/O supply voltage (VCCO) and reference voltage (VREF) resources allowing each bank complete independence from the others. Each I/O is individually configurable based on the bank’s VCCO and VREF settings. In addition, each I/O has configurable drive strength, weak pull-up, weak pull-down, or a bus-keeper latch Programmable I/O Features ■ ■ ■ ■ Separate Input, Output and OE Registers Flexible Set, Reset, Clock Enable and Polarity Input Register Offers Delay Option for Zero tHOLD Programmable Output Slew Rate Chip to Memory Chip to Chip Chip to Backplane SSTL2 I and II SSTL3 I and II HSTL I HSTL III HSTL IV CTT ↓ SDRAM DDR SRAM QDR SRAM ZBT SRAM LVTTL LVCMOS 3.3 LVCMOS 2.5 LVCMOS 1.8 Prog. Impedance PCI33_3 PCI66_3 PCI-X GTL+ AGP Bus-LVDS LVDS LVPECL sysIO Features Programmable I/O Block Diagram ■ Up to 8 independent sysIO banks – Each supports multiple I/O standards – Each has own I/O supply voltage (VCCO) – Each has own reference voltage (VREF) – Each bank configurable based on VCCO and VREF ■ Configurable drive strength on each I/O ■ Pull-up, pull-down, or Bus-Keeper latch capabilities for bus maintenance on each I/O Programmable I/O Cell (PIC) sysIO Input Routing Pool sysIO Programmable I/O (PIO) 0 Programmable I/O (PIO) 1 OE0 Output Routing Pool OE1 ispXPGA devices include three classes of I/O interface standards Programmable I/O From sysHSI block From sysHSI block Only for Programmable I/Os (PIOs) associated with sysHSI Blocks Feed-through (FT) From sysIO Input Clock (CLK) Input Clock Enable (ICEN) D Q Un-terminated, single-ended – 3.3V LVTTL and 1.8V, 2.5V, and 3.3V LVCMOS – PCI, PCI-X, and AGP-1X ■ Terminated, single-ended – SSTL and HSTL – CTT and GTL+ ■ Differential – LVDS and LVPECL To Routing OUT0 Delay ■ OUT1 CLK/LE CE SR Input Set/Reset (ISR) Global Set/Reset(GSR) PIO Input (IN) Q D SR Q To sysIO Output Enable CLK/LE Output Clock Enable (OCEN) CE Output Set/Reset (OSR) PIO Output Enable(OEN) D To sysIO Output To sysHSI block Only for PIOs Associated with sysHSI Blocks To sysHSI block CLK/LE CE PIO Input Enable (IEN) SR OE sysCLOCK™ ispXPGA devices provide up to eight sysCLOCK PhaseLocked Loops (PLLs). Lattice’s advanced sysCLOCK PLL circuitry consists of PLLs plus the various dividers, reset, and feedback signals associated with PLLs. The sysCLOCK feature provides the ability to synthesize clock frequencies and generate multiple clock signals for routing within the device. Furthermore, sysCLOCK circuitry can generate clock signals that are aligned either at the board-level or the device-level. sysCLOCK PLL Block Diagram Clock_Net CLK_IN 10:320MHz Programmable Post-scalar Input Clock +Delay (M) Divider 10-320 10-320 100-400 (V) Divider ÷1, 2, 4, 8, ÷1-32 MHz MHz MHz PLL 16, 32, 64 PLL_RST Programmable –Delay 0 to ±2.8ns in 325ps Steps Lattice’s High Speed Serial Interface (sysHSI) allows highspeed serial data transfer over a pair of LVDS I/O at up to 800Mbs. The ispXPGA devices have multiple sysHSI blocks. Each sysHSI block has two SERDES blocks which contain two main sub-blocks, Transmitter (with a serializer) and Receiver (with a deserializer) including Clock/Data Recovery Circuit (CDR). Each SERDES can be used as a full duplex channel. The two SERDES in each sysHSI block share a common clock and must operate at the same nominal frequency. sysHSI Block Diagram PLL_LOCK sysHSI Block sysIO SOUT_A Secondary Clock (K) Divider ÷2, 4, 8, 16, 32 Feedback Divider (N) ÷1-32 PLL_FBK CLK_OUT 10-320MHz sysHSI High-Speed Serial Interface Clock_Net SIN_A SEC_OUT Clock Recovery sysCLOCK PLL Features ■ Eight PLLs per Device - Plus 8 Global Clocks - Plus 8 Low-Skew Clock Nets ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ PIC RECCLK_A PIC PIC SS_CLKOUT ■ PIC TXD_A RXD_A SERDES LVDS PLL SS_CLKIN SIN_B Clock Frequency Synthesis Multiple Clock Signal Generation Device or Board Clock Alignment 10 - 320MHz, tLOCK 25 µs Jitter: Cycle-to-Cycle ±100ps; Period ±150ps; Input Jitter Tolerance ±300ps Four Dividers per PLL – M Divider for Clock Division – N Divider for Clock Multiplication – V Divider for VCO Operation at Higher Frequencies – K Divider for Secondary Clock Division Programmable Delay for Advancing or Delaying Clock – 325ps Increments from 0 to ±2.8ns – Inserts Delay on PLL Input or Feedback Lines PLL Input Clock from Associated Global Clock Pin Output Routed to Associated Global Clock Net Secondary Clock Divided from Primary Clock Output PLL Reset, Feedback, and Lock Control Signals PIC Clock Recovery RECCLK_B RXD_B TXD_B SERDES SOUT_B Routing Pool REFCLK PIC PIC PIC sysHSI Features ■ sysHSI Block Performs – Clock data recovery (CDR) – Serialization – De-serialization ■ Two Options Available – High performance sysHSI (standard part number) – Low-cost, no sysHSI (“E” series) ■ Low Voltage Differential Signals (LVDS) ■ Clock Signal Encoded into Serial Data Stream ■ CDR used to Cancel Channel-to-Channel Skew and Data-to-Clock Skew ■ Dedicated PLL per sysHSI Circuit sysHSI High-Speed Operation Modes Data Code Serial Data Rate (Mbps) Pay Load Data Rate (Mbps) Parallel Data/Clk (MHz) SERDES without Encoding/Decoding 8B/10B 400 to 800 320 to 680 40 to 85 SERDES with Encoding/Decoding 10B/12B 400 to 800 333 to 708 N/A 400 to 800 n x (400 to 800) Mode Source-Synchronous (n channels) Serial/ Parallel Ratio Symbol Alignment Pattern CDR Support 10b Encoded 10 K28.5 +/- CDR 33.3 to 70.8 10b Raw Data 12 SyncPat CDR 100 133 200 n x 8b n x 6b n x 4b 8 6 4 Synch to LS Clock De-skew (optional) Parallel Data Width ispLEVER Design Software ispXPGA Select Performance Lattice’s ispLEVER is a new generation of PLD design tool equipped to provide a complete system for FPSC, FPGA, ispXPLD, CPLD, ispGDX and SPLD design. ispLEVER includes a fully integrated, push-button design environment and advanced features for interactive design optimization and debug. TA = 25º C; VCC = 1.8V Function 4-Input LUT Delay Features ■ Fully Integrated Synthesis and RTL and Timing Simulation Tools ■ Complete Design Flow for All In-System Programmable (ISP™) Lattice Device Families ■ Advanced Timing-Driven Placement and Routing ■ IP Manager and Module Generator ■ Fast, Efficient Run Times and Competitive Device Performance and Utilization ■ ■ Speed Supported by Libraries from Leading CAE Vendors • Aldec, Cadence, Innoveda, Mentor Graphics, Synopsys, Synplicity 440ps Synchronous Counter 8-bit 334MHz Loadable Up/Dn Carry-Ripple Counter 64-bit 156MHz Carry-Ripple Adder 64-bit 232MHz Multiplexer 64:1 237MHz De-Multiplexer 1:64 371MHz Shift Reg Up/Dn, Circular Shift 64-bit 315MHz Barrel Shifter 64-bit 184MHz PLL Frequency Min Max 10 MHz 320 MHz LVDS with Clock Recovery Max 850Mbit Windows® and UNIX® Solutions ispLEVER Design Software Flow Chart Lattice’s ispLEVER Core program offers a wide variety of IP cores from Lattice and third-party partners. Lattice EDA Partner HDL Capture and Simulation Floor Planner Design Synthesis Design Database Packing Logic Simulation and Timing Analysis Function Compilers and IP Timing-Driven Place and Route Library Delay File Lattice OEM EDA Partners: • Mentor Graphics® Leonardo SpectrumTM • Mentor Graphics ModelSim® • Synplicity® Synplify® IP Cores Timing Analyzer ■ Custom Macro Generation -- Reuse Your Own Earlier Work ■ High Quality Lattice-developed IP Cores – Busses, Communications, Memory, DSP functions – Richly parameterized – Free trial versions on Lattice website ■ Broad Offering from Lattice IP Partners Lattice’s ispLEVER Core Program Saves Time POS-PHY ispVM™ System FIR Filter PCI-X Lattice Cores Utopia PCI DMA Customer Cores DDR Reed-Solomon POS-PHY ispLEVER CORE Design Database TM 3rd Party Cores Lattice Semiconductor Corporation 5555 Northeast Moore Court Hillsboro, Oregon 97124 U.S.A. Telephone: (503) 268-8000 • FAX: (503) 268-8556 Applications & Literature Hotline: 1-800-LATTICE www.latticesemi.com Copyright © 2002 Lattice Semiconductor Corporation. Lattice Semiconductor, L (stylized) Lattice Semiconductor Corp., and Lattice (design), E2CMOS, ISP, ispGAL, ispGDX, ispLEVER, ispMACH, ispPAC, ispVM, ispXP, ispXPGA, ispXPLD, sysCLOCK, sysCONFIG, sysHSI, sysIO and sysMEM are either registered trademarks or trademarks of Lattice Semiconductor Corporation in the United States and/or other countries. Other product names used in this publication are for identification purposes only and may be trademarks of their respective companies. July 2004 Order #: I0141A