ECP5 sysIO Usage Guide March 2014 Technical Note TN1262 Introduction The sysIO buffers in the ECP5TM device give the designer the ability to easily interface with other devices using advanced system I/O standards. This technical note describes the sysIO standards available and how to implement them using Lattice Diamond® design software. sysIO Buffer Overview The ECP5 sysIO interface contains multiple Programmable I/O Cell (PIC) blocks. The primary building block is a quad or pair of GPIO depending on the side of the I/O. The GPIO functions are available on every PIO of all devices. The quad is built of four GPIOs (PIOA, PIOB, PIOC and PIOD) or two GPIOs (PIOA, PIOB). Two adjacent PIOs can be joined to provide a differential I/O pair (labeled as ‘T’ and ‘C’). PIOA and PIOB comprise a differential pair and PIOC and PIOD comprise another pair. One true LVDS driver is connected only to the A/B pair. Each PIO includes a sysIO buffer and I/O logic (IOLOGIC). The ECP5 sysIO buffers support a variety of single-ended and differential signaling standards. The sysIO buffer also supports the DQS strobe signal that is required for interfacing with the DDR memory. The DQS signal from the bus is used to strobe the DDR data from the memory into input register blocks. The top and bottom sides are grouped into eight IOs with the pitch matches to nine PLC from the core. These IOs will support hot socket with IO standards from 3.3 V to 1.2 V and mainly used for 3.3 V domain IOs. The left and right sides are grouped into 16 IOs that support one DQS group and pitch matches to 12PLC + EBR/DSP from the core. The left/right side IOs will support IO standard from 3.3 V to 1.2 V with no hot socket capability. The left/right side also have one LVDS output driver per four IOs and one differential termination resistor per two IOs. For more information on the architecture of the sysIO buffer, refer to DS1044, ECP5 Family Data Sheet. The IOLOGIC includes input, output and tri-state registers that implement both single data rate (SDR) and double data rate (DDR) applications along with the necessary clock and data selection logic. Programmable delay lines and dedicated logic within the IOLOGIC are used to provide the required shift to incoming clock and data signals and the delay required by DQS inputs in DDR memory. The DDR implementation in the IOLOGIC and the DDR memory interface support are discussed in more detail in TN1265, ECP5 High-Speed I/O Interface. Supported sysIO Standards The ECP5 sysIO buffer supports both single-ended and differential standards. Single-ended standards can be further subdivided into internally ratioed standards such as LVCMOS, LVTTL; and externally referenced standards such as HSUL and SSTL. The buffers support the LVTTL, LVCMOS 1.2 V, 1.5 V, 1.8 V, 2.5 V and 3.3 V standards. In LVCMOS and LVTTL modes, the buffer has individually-configurable options for drive strength, bus maintenance (weak pull-up, weak pull-down). Differential standards supported include LVDS, BLVDS, LVPECL, MLVDS, SLVS (Rx only), differential LVCMOS, differential SSTL and differential HSUL. For better support of video standards, subLVDS and MIPI (Rx only) are also supported. Table 10-1 and Table 10-2 list the sysIO standards supported in ECP5 devices. © 2014 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. www.latticesemi.com 10-1 tn1262_01.0 ECP5 sysIO Usage Guide Table 10-1. Single-Ended I/O Standards Standard LVTTL33 VREF VCCIO — Input Output Bi-Directional 3.3 2 Yes Yes Yes LVCMOS33 — 3.3 2 Yes Yes Yes LVCMOS25 — 2.5 2 Yes Yes Yes LVCMOS18 — 1.8 Yes Yes Yes LVCMOS15 — 1.5 Yes Yes Yes LVCMOS12 — 1.22 Yes Yes Yes 1 Yes Yes1 SSTL18 Class I, II 0.9 — Yes SSTL15 Class I, II 0.75 — Yes1 Yes Yes1 SSTL135 Class I, II 0.675 — Yes1 Yes Yes1 0.6 — Yes1 Yes Yes1 HSUL12 1. Left and right side I/O only. 2. Required for output only. Table 10-2. Differential I/O Standards Standard SSTL18D I, II VREF Input Output Bi-Directional Yes A/B pair Yes — SSTL135D I, II — SSTL15D I, II — HSUL12D — LVTTL33D — LVCMOS33D — LVCMOS25D — LVCMOS18D — LVDS — LVDS25E — No Yes No BLVDS25 — Yes No No BLVDS25E — No Yes Yes MLVDS25 — Yes No No MLVDS25E — No Yes Yes LVPECL33 — Yes No No LVPECL33E — No Yes No SLVS — Yes No No SUBLVDS — Yes No No MIPI D-PHY HS Mode — C/D Pair No No sysIO Banking Scheme ECP5 devices have general-purpose programmable sysIO banks and a configuration bank. Each of the generalpurpose sysIO banks has a VCCIO supply voltage and one reference voltage, VREF1. Every device has two banks on the left, right and top side. The bottom side implements SERDES channels and only the biggest device 85K has one sysIO bank. Every ECP5 device has a TAP controller interface bank in the lower left corner of the device. This Bank 8 has four signal pins (TCK, TMS, TDI and TDO) and is powered by VCCIO8, located on the lower left side of the device, has shared I/O for configuration. 10-2 ECP5 sysIO Usage Guide Figure 10-1. ECP5 sysIO Banking TOP VREF1(1) VCCIO1 GND VREF1(0) VCCIO0 GND Bank 0 Bank 1 GND VCCIO2 VREF1(2) RIGHT LEFT Bank 7 Bank 2 VREF1(7) VCCIO7 GND Bank 6 Bank 3 VREF1(6) VCCIO6 GND Bank 41 Bank 8 CONFIG BANK GND VCCIO3 VREF1(3) SERDES GND VCCIO4 VCCIO8 GND BOTTOM 1. Only 85K device has this bank. VCC (1.1 V) The core power supply, VCC, is used to power the device internally before data is captured by the I/O buffers. VCC is also used to power the 1.2V (LVCMOS12) ratioed buffers so these can be captured independently of VCCIO. VCCIO (1.2 V/1.35 V/1.5 V/1.8 V/2.5 V/3.3 V) Each bank has a separate VCCIO supply that powers the single-ended output drivers in a bank. The bank VCCIO is also used to power ratioed input buffers such as LVCMOS15 and LVCMOS18, as well as extended threshold ratioed buffers. For unused banks, it is recommended to set VCCIO to 0V to minimize power and hold the bank in hot socket. VCCAUX (2.5V) In addition the VCCIO supply, every bank also has an auxiliary global supply called VCCAUX. The bank VCCAUX supply is used to power the differential and referenced (SSTL) input buffer. Bank VCCAUX is also used to power the push-pull output pre-driver sections. 10-3 ECP5 sysIO Usage Guide VCCIO8 (1.2 V/1.5 V/1.8 V/2.5 V/3.3 V) The JTAG pins share power supply of Bank 8 VCCIO supplies. VCCIO8 determines the electrical characteristics of the LVCMOS JTAG pins, both the output high level and the input threshold. Table 10-3 contains a summary of the required power supplies. Table 10-3. Power Supplies Power Supply Value1 Description VCC Core power supply 1.1 V VCCIO Power supply for the I/O banks 1.2 V/1.35 V/1.8 V/2.5 V/3.3 V VCCAUX Auxiliary power supply 2.5 V VCCIO8 Power supply for JTAG pins and configuration bank I/O 1.2 V/1.5 V/1.8 V/2.5 V/3.3 V 1. Refer to DS1044, ECP5 Family Data Sheet for recommended minimum and maximum values. VREF1 Each bank can support one separate VREF input voltage, VREF1, which is used to set the threshold for the referenced input buffers. A dedicated I/O in each bank can be used to drive the VREF1 bank reference voltage. An I/O used as a VREF1 input is also called a VREF1_DRIVER. A conceptual block diagram is shown in Figure 10-2. Figure 10-2. Bank VREF from One Specific Pad PAD BANK VREF To assign a VREF driver, use IO_TYPE=VREF1_DRIVER. To assign a VREF to a buffer, use VREF=VREF1_LOAD. Hot Socketing Support The I/Os located on the top and bottom sides are fully hot socketable See DS1044, ECP5 Family Data Sheet for hot socketing (IDK) requirements. Standby Using the Standby modes is a way to dynamically power-down the bank. It disables the differential/reference receiver, true differential driver, current mirrors and bias circuits. In Standby mode, differential drivers and differential input buffers can be powered down to save power. The Standby modes are enabled on a bank-by-bank basis. Each bank has user-routed input signals to enable the Standby (dynamic power-down) modes. Refer to TN1266, Power Consumption and Management for ECP5 Devices for detailed information. LVDS sysIO Buffer Pairs (A/B and C/D on Left and Right Sides) The GPIO are grouped as a quad building block, GPIOA, GPIOB, GPIOC and GPIOD. Each pair consists of two single-ended output drivers and two sets of single-ended input buffers (both ratioed and referenced). One referenced input buffer, per pair, can also be configured as a differential input. In addition to these buffers and drivers, each I/O has a weak pull-up and weak pull-down resistor. The programmability for these ‘weak’ features is limited to ON and OFF programmability on each I/O independently. The pull modes are always disabled in output mode. Left and right side GPIO has clamp always on. The two pads in the pair are described as ‘true’ and ‘comp’, where the true pad is associated with the positive side of the differential I/O, and the comp (complementary) pad is asso10-4 ECP5 sysIO Usage Guide ciated with the negative side of the differential I/O. The sysIO buffers pairs are grouped as A/B pad pairs or C/D pad pairs. Each sysIO pad pair will support programmable on/off differential input termination of 100 ohms. There is an added LVDS output driver in the A/B pad pairs of all arrays. The C/D pad pairs do not have the true LVDS differential output driver. The LVDS output driver does support tri-state. LVDS can be BIDI. Figure 10-5 describes the detail of the sysIO Buffer Pairs on left and right sides. sysIO Buffer Pair (A/B Pair on Top and Bottom Sides) The GPIO are grouped as a pair building block, GPIOA and GPIOB. Each pair consists of two single-ended output drivers and two sets of single-ended input buffers (ratioed only). In addition to these buffers and drivers, each I/O has a weak pull-up and weak pull-down resistor. The programmability for these ‘weak’ features is limited to ON and OFF programmability on each I/O independently. The pull modes are always disabled in output mode. All GPIO on top and bottom side support a clamp that is programmable on or off. Figure 10-5 describes the detail of the sysIO Buffer Pair on the top and bottom sides. Figure 10-3. sysIO Buffer Pair for Left and Right Sides TRUE Pad TRUE Pad The PAD C and PAD D pio pair have the same configuration logic as PAD A and PAD B, with the exception, they do not have a true differential output driver. B VCCIO Clamp ON Weak Pulldown (default) GND GND Weak Pullup Weak Pullup Weak Pulldown (default) VCCIO A Clamp ON Programmable (on, off) 100 ohm differential input termination Complementary circuitry located in IO logic bocks 10-5 + Ratioed Ref/diff Ratioed VCCAUX - VCC VCCIO VCCAUX TSB OUTB TSA OUTA INA Programmable static/dynamic Thevenin termination 50/60/70 ohm to VCCIO/2 INB VCCIO Programmable static/dynamic Thevenin termination 50/60/70 ohm to VCCIO/2 SE Driver Diff Driver on AB pairs VCCIO SE Driver VCCAUX VCCIO Ratioed Ref/diff + - VCC True differential drivers only on AB pins Ratioed VCCIO VCCAUX Bank VREF ECP5 sysIO Usage Guide Figure 10-4. SysIO Buffer Pair for Top and Bottom Sides A Clamp Off, on The PAD C and PAD D pio pair have the same configuration logic as PAD A and PAD B. B Ratioed INA OUTB TOB TOA OUTA INA Programmable static/dynamic Thevenin termination 50/50/75 ohm to VCCIO/2 Ratioed Programmable static/dynamic Thevenin termination 50/50/75 ohm to VCCIO/2 VCC GND VCCIO VCCIO Ratioed VCCIO VCCAUX GND Weak Pullup Weak Pullup VCC Ratioed VCCIO VCCAUX Weak Pulldown (default) VCCIO Clamp Off, on TRUE Pad Weak Pulldown (default) VCCIO TRUE Pad Complementary circuitry located in IO logic blocks Mixed Voltage Support in a Bank ECP5 devices support mixed mode inputs in a given bank on all sides of the device. All differential and referenced inputs are supported independent of VCCIO. When output is configured as an open drain it can be placed independent of VCCIO. Some of the ratioed buffers are powered by VCCAUX and VCC and can therefore be placed independently of VCCIO. ECP5 devices support numerous mixed input voltage combinations by using a combination of three ratio receivers. The first receiver is powered by VCCIO and uses overdrive/underdrive threshold adjustments to support 1.8 V and 1.5 V signaling. The second is a fixed threshold 1.2 V ratio receiver powered by VCC that supports 1.2 V signaling. The third is powered with VCCAUX (2.5 V), supports hysteresis, and is used for 3.3 V and 2.5 V signaling. Table 10-4 lists the ratioed sysIO standards that can be mixed in the same bank. 10-6 ECP5 sysIO Usage Guide Table 10-4. Mixed Voltage I/O Support For TOP/BOTTOM BANKS Input SysIO Standards VCCIO (V) 1.2 V 1.5 V 1.8 V Output SysIO Standards 2.5 V 3.3 V 1.2 V ✓ 1.2 V ✓ ✓ ✓ 1.35 V ✓ ✓ ✓ 1.5 V ✓ 1.8 V ✓ 2.5 V 3.3 V ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ 1.5 V 1.8 V 2.5 V 3.3 V ✓ ✓ ✓ ✓ For LEFT/RIGHT BANKS Input Signal VCCIO (V) 1.2 V 1.5 V 1.8 V Output SysIO Standards 2.5 V 1.2 V ✓ 1.35 V ✓ 1.5 V ✓ 1.8 V ✓ 2.5 V ✓ ✓ 3.3 V ✓ ✓ 3.3 V 1.2 V 1.5 V 1.8 V 2.5 V 3.3 V ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ sysIO Buffer Configurations This section describes the various sysIO features available on the ECP5 FPGA. Programmable Drive Strength The single-ended driver has programmable drive strength. The LVCMOS/LVTTL drive strength available at each value of VCCIO is shown in Table 10-5. The ECP5 single-ended driver is a process, voltage and temperature compensating driver. Therefore, there will be a good tolerance of drive strength. For LVCMOS and LVTTL I/O standards, guaranteed minimum drive strength is listed. The user must consider the maximum allowable current per bank and the package thermal limit current when selecting the drive strength. Table 10-5 shows the available drive settings for each of the output standards. Table 10-5. Programmable Drive Values for LVCMOS/LVTTL 1.2 V 1.5 V 1.8 V 2.5 V 3.3 V IOLmin IOHmin IOLmin IOHmin IOLmin IOHmin IOLmin IOHmin IOLmin IOHmin Units 4 -4 4 -4 4 -4 4 -4 4 -4 mA 8 8 8 -8 8 -8 8 -8 8 -8 mA 121 -121 121 -121 121 -121 mA 161 -161 mA 1. Automotive device may not support drive setting. The SSTL and HSUL nominal drive strengths are optimized for the performance and signal integrity of the I/O interface. 10-7 ECP5 sysIO Usage Guide Programmable Slew Rate The single-ended output buffer for each device I/O pin has programmable output slew rate control that can be configured for either low-noise (SLEWRATE=SLOW) or high-speed (SLEWRATE=FAST) performance. Each I/O pin has an individual slew rate control that allows designers to specify slew rate control on a pin-by-pin basis. Slew rate control affects both the rising and falling edges. Slew rates vary as a function of drive and PVT conditions. Slow slew rate reduces SSO noise. The software default for slew rate is SLEWRATE=SLOW. Differential standards are not impacted by slew rate settings. However, slew rate settings have some impact on emulated differential standards, as they use single-ended output buffers and complementary outputs. Tri-state Control On the output side, each single-ended driver has a separate tri-state control. The differential driver has tri-state control as well. Open Drain Control In addition to tri-state control, single-ended drivers also support open drain operation on each I/O independently. Unlike non-open drain outputs that consist of both source and sink components, an open drain output is composed of only the sink section of the output driver. All LVCMOS and LVTTL output buffers can be configured to function as open drain outputs. The user can implement an open drain output by turning on the OPENDRAIN attribute in the software. Complementary Outputs The single-ended driver associated with the complementary pad can optionally be driven by the complement of the data that drives the single-ended driver associated with the true pad. ECP5 devices use pads A and C as true pads and pads B and D as complement pads. This allows a pair of single-ended drivers to be used to drive complementary outputs. Pads A and B from a PIO pair and pads C and D from another PIO pair. This is used for driving complementary SSTL signals (as required by the differential SSTL clock inputs on synchronous DRAM and synchronous SRAM devices, respectively). It can also be used in conjunction with off-chip resistors to emulate LVPECL33, MLVDS, LVDS25E and BLVDS output drivers. When this option is selected, the tri-state control for the driver associated with the complement pad is driven by the same signal as the tri-state control for the driver associated with the true pad. Differential I/O Supported Differential inputs LVDS, SUBLVDS, MLVDS25, BLVDS, SLVS, MIPI are supported with differential receivers on both A/B pair and C/D pair PIOs and on left and right sides only. 50% of the sysIO buffer pairs on the left and right sides only are true differential outputs. LVDS is supported with a dedicated differential output driver on the A/B PIO pair. The C/D pair pins do not support true differential outputs. LVDS25E, LVPECL33E, MLVDS25E, and BLVDS25E outputs can be implemented via emulation on all A/B and C/D pin output pairs. These emulated differential outputs require external resistors. Refer to DS1044, ECP5 Family Data Sheet for detailed information. Complementary SSTL Output Support Differential SSTL outputs do not use external resistors, they use the complementary mux contained within each pair of single-ended output drivers. 10-8 ECP5 sysIO Usage Guide Differential Input Termination The ECP5 device supports on-chip 100 ohm input differential termination between all pairs of all banks on left and right sides. The only value supported is 100 ohm. It is programmable as on and off. When it is on and the I/O type is MIPI or a BIDI, it is dynamic. Figure 10-5 shows the discrete off-chip and on-chip solutions for dedicated, differential input termination. The differential termination is implemented using parallel legs that turn on and off to compensate for PVT variation. The termination also applies to input termination and is dynamic (enabled when output buffer is put in tri-state) or static (always on) to support MIPI and BIDI applications. Figure 10-5. Differential Input Termination Zo = 50 Ohms Zo = 50 Ohms 100 Ohms 100 Ohms Zo = 50 Ohms Zo = 50 Ohms Off-Chip Solution On-Chip Solution Single-Ended Input Termination ECP5 devices support single-ended input parallel termination to VCCIO/2. This is done by using output driver legs to emulate termination between the pad and VCCIO as well as between the pad and VSS. Both static and dynamic termination are supported. Dynamic termination is used to support the DDR2 and DDR3 interface standards. Values of termination are 50 ohms, 75 ohms and 150 ohms. All input parallel terminations use a Thevenin termination scheme. As an example, 50ohms to VCCIO/2 is created by the Thevenin combination of 100 ohms between the pad and VCCIO and 100 ohms between the pad and VSS. Figure 10-6 shows the various off-chip, single-ended input termination schemes. Figure 10-6. Single-Ended Input Termination Off-Chip Solution Termination Type On-Chip Solution VCCIO/2 VCCIO/2 Parallel to VCCIO/2 at Receiving end. Thevenin Zo Zo Zo Zo VREF VREF VCCIO/2 Tri-state Parallel to VCCIO/2 at Receiving end with Bidirectional Enable/Disable for DDR2 and DDR3 N/A Zo Zo VREF 10-9 ECP5 sysIO Usage Guide Programmable CLAMP The buffers on top and bottom sysIO have optional clamp diodes that may optionally be specified in the Lattice Diamond design software. The programmable CLAMP can be turned ON or OFF. Differential SSTL and HSUL The single-ended driver associated with the complementary pad can optionally be driven by the complement of the data that drives the single-ended driver associated with the true pad. This allows a pair of single-ended drivers to be used to drive complementary outputs with the lowest possible skew between the signals. This is used for driving complementary SSTL and HSUL signals (as required by the differential SSTL and HSUL clock inputs on synchronous DRAM and synchronous SRAM devices, respectively). Refer to the DS1044, ECP5 Family Data Sheet for a detailed description of the differential HSUL and SSTL implementations. MIPI D-PHY Interface The MIPI D-PHY Interface is used only in input mode and only on the C/D pad pair. The differential C/D pad pair high-speed and pad C single-ended low-power inputs are handled through the pad C I/O logic. The pad D singleended low-power inputs are handled through the pad D I/O logic. • HS mode: 100 ohm differential termination is enabled with a differential receiver • LP mode: HS mode is disabled and ratio receiver is enabled on pad C The primitive shown in Figure 10-7 should be used when implementing the MIPI interface. Figure 10-7. MIPI Primitive IMIPI Pad C A Pad D AN High-Speed Select OHSLS HSSEL OLS High/Low-Speed Output Low-Speed Output Table 10-6. IMIPI Port List Port I/O A I Pad C input Description AN I Pad D input High-speed select signal. This is shared with the tri-state input of the buffer. HSSEL I HSSEL=1: High-speed mode, 100 ohm differential termination is on. Pad C logic select differential signal to IOL for gearing. HSSEL=0: Low-speed mode, 100 ohm termination is turned off. OHSLS selected as ratioed LVCMOS input buffer from the I input (pad C), OLS selected as LVCMOS input from the IN input (pad D). OHSLS O High-speed or low-speed output, depending on HSSEL OLS O Low-speed output MIPI is supported via the IMIPI primitive instead of IO_TYPE in the front-end RTL and simulation. 10-10 ECP5 sysIO Usage Guide Software sysIO Attributes sysIO attributes can be specified in the HDL, using the Preference Editor GUI or in the ASCII Preference file (.prf) directly. The appendices of this document provide examples of how these can be assigned using each of the methods described above. This section describes each of the attributes in detail. IO_TYPE The IO_TYPE is used to set the sysIO standard for an I/O. The VCCIO required to set these I/O standards are embedded in the attribute names. The BANK VCCIO attribute is used to specify allowed VCCIO combinations for each IO_TYPE. Default: LVCMOS25 Table 10-7. IO_TYPE Attribute Values sysIO Signaling Standard IO_TYPE DEFAULT LVCMOS25 LVDS 2.5 V LVDS Emulated LVDS 2.5 V LVDS25E Bus LVDS 2.5 V BLVDS25 Emulated Bus LVDS 2.5 V BLVDS25E LVPECL 3.3 V LVPECL33 Emulated LVPECL 3.3 V LVPECL33E MLVDS MLVDS Emulated MLVDS MLVDS25E SLVS SLVS Sub_LVDS SUBLVDS HSUL 1.2 V HSUL12 Differential HSUL HSUL12D SSTL15 Class I and II SSTL15_I, SSTL15_II Differential SSTL15 Class I and II SSTL15D_I, SSTL15D_II SSTL135 Class I and II SSTL135_I, SSTL135_II Differential SSTL135 Class I and II SSTL135D_I, SSTL135D_II SSTL18 Class I and II SSTL18_I, SSTL18_II Differential SSTL18 Class I and II SSTL18D_I, SSTL18D_II Differential LVTTL LVTTL33D LVTTL LVTTL33 LVCMOS 3.3 V LVCMOS33 LVCMOS 2.5 V LVCMOS25 LVCMOS 1.8 V LVCMOS18 LVCMOS 1.5 V LVCMOS15 LVCMOS 1.2 V LVCMOS12 Differential LVCMOS 3.3 V LVCMOS33D Differential LVCMOS 2.5 V LVCMOS25D Differential LVCMOS 1.8 V LVCMOS18D 10-11 ECP5 sysIO Usage Guide OPENDRAIN An I/O can be assigned independently to be an open drain when this attribute is turned on. Values: ON, OFF Default: OFF DRIVE The drive strength attribute is available for output standards that support programmable drive strength. The default depends on the I/O standard used. Table 10-8. Programmable Output Drive Output Standard DRIVE Single-Ended Interfaces LVTTL33 4 mA, 8 mA, 12 mA, 16 mA LVCMOS33 4 mA, 8 mA, 12 mA, 16 mA LVCMOS25 4 mA, 8 mA, 12 mA LVCMOS18 4 mA, 8 mA, 12 mA LVCMOS15 4 mA, 8 mA LVCMOS12 4 mA, 8 mA LVTTL33 (open drain) 4 mA, 8 mA, 12 mA, 16 mA LVCMOS33 (open drain) 4 mA, 8 mA, 12 mA, 16 mA LVCMOS25 (open drain) 4 mA, 8 mA, 12 mA, 16 mA LVCMOS18 (open drain) 4 mA, 8 mA, 12 mA, 16 mA LVCMOS15 (open drain) 4 mA, 8 mA, 12 mA1, 16 mA LVCMOS12 (open drain) 4 mA, 8 mA, 12 mA1, 16 mA HSUL12 4 mA, 8 mA SSTL135 I 8 mA SSTL135 II 10 mA SSTL18 I 8 mA SSTL18 II 16 mA SSTL15 I 8 mA SSTL15 II 10 mA Differential Interfaces LVTTL33D 4 mA, 8 mA, 12 mA, 16 mA LVCMOS33D 4 mA, 8 mA, 12 mA, 16 mA LVCMOS25D 4 mA, 8 mA, 12 mA SSTL1.35D I 8 mA SSTL1.35D II 10 mA SSTL18D I 8 mA SSTL18D II 16 mA SSTL15D I 8 mA SSTL15D II 10 mA HSUL12D 4 mA, 8 mA LVDS — LVDS25E1 8 mA BLVDS25E1 16 mA MLVDS25E1 16 mA LVPECL33E1 16 mA 1. Emulated with LVCMOS drivers and external resistors. 2. Independent of VCCIO. 10-12 DIFFDRIVE VCCIO — — — — — — — — — — — — — — — — — — — 3.3 3.3 2.5 1.8 1.5 1.2 Note2 Note2 Note2 Note2 Note2 Note2 1.2 1.35 1.35 1.8 1.8 1.5 1.5 — — — — — — — — — — 3.5 — — — — 3.3 3.3 2.5 1.35 1.35 1.8 1.8 1.5 1.5 1.2 2.5 2.5 2.5 2.5 3.3 ECP5 sysIO Usage Guide DIFFDRIVE DIFFDRIVE attribute is available for the LVDS output standard. The default value is set to 3.5 mA. Values: 3.5 mA Default: 3.5 mA TERMINATION This attribute sets the on-chip input parallel termination to VCCIO/2. Parallel termination is achieved using a Thevenin termination scheme. This programmable option can be set for each I/O individually. Both static and dynamic terminations are available. Values: OFF, 50, 75, 150 Default: OFF DIFFRESISTOR This attribute is used to provide differential termination (dynamic differential). It is available only for differential IO_TYPES. Values: OFF, 100 Default: OFF CLAMP The CLAMP options can be enabled for each I/O independently. CLAMP is available on only top and bottom sysIO banks. CLAMP is not available when an output is set to open drain. Values: ON, OFF Default: OFF PULLMODE The PULLMODE options can be enabled for each I/O pin independently. The PULLMODE settings are not available when I/O pins are programmed output-only. It is available for I/O pins in Input mode and Bidi mode. Values: UP, DOWN, NONE Default: DOWN SLEWRATE Each I/O pin has an individual slew rate control. This allows designers to specify slew rate control on a pin-by-pin basis. This is not a valid attribute for inputs. Values: FAST, SLOW, NA Default: SLOW Note: LVTTL and LVCMOS support fast and slow slew rates. 10-13 ECP5 sysIO Usage Guide HYSTERESIS The ratioed input buffers have an input hysteresis option. The HYSTERESIS option can be used to change the amount of hysteresis for the LVTTL33, LVCMOS33 and LVCMOS25 input and bi-directional I/O standards. The HYSTERESIS option for each of the input pins can be set independently. Values: ON, OFF Default: Default for LVCMOS33, LVCMOS25 and LVTTL33 is ON. Default for all other IO_TYPES is OFF. VREF The VREF option must be enabled for referenced input buffers (HSUL and SSTL). The VREF can be specified in the HDL or in the Design Planner GUI. Values: OFF, VREF1_LOAD Default: VREF1_LOAD (software assigns the dedicated pin to be VREF). DIN/DOUT This attribute can be used when an I/O register needs to be assigned. Using DIN asserts an input register and using DOUT asserts an output register in the design. By default, the software will attempt to assign the I/O registers if applicable. Users can turn this OFF by using a synthesis attribute or the Preference Editor. These attributes can only be applied on registers. LOC This attribute can be used to make pin assignments to the I/O ports in the design. This attribute is used only when the pin assignments are made in HDL source code. Pins can also be assigned directly using the GUI in the Preference Editor. See the appendices of this document for further information. 10-14 ECP5 sysIO Usage Guide Technical Support Assistance e-mail: [email protected] Internet: www.latticesemi.com Revision History Date Version August 2013 01.0 Change Summary Initial release 10-15 ECP5 sysIO Usage Guide Appendix A. sysIO Primitive Symbols and Instance Examples Primitive Symbols IB: Input Buffer OBCO: Output Complementary Buffer I O BBPD: Bi-directional Buffer with Pull-down T OT I I IB OC INPUT: I OUTPUT: O OBCO OB INPUT: I OUTPUTS: OT, OC BBPD INPUTS: I, T OUTPUT: O INOUT: B IBPD: Input Buffer with Pull-down I O OBZ: Output Buffer with Tristate BBPU: Bi-directional Buffer with Pull-up T T O I I IBPD OBZ VSS OB INPUTS: I, T OUTPUT: O INPUT: I OUTPUT: O BBPU INPUTS: I, T OUTPUT: O INOUT: B IBPU: Input Buffer with Pull-up VDD I O OBZPU: Output Buffer with Tristate and Pull-up BBW: Bi-directional Buffer with Keeper Mode T T I O I OBZPU IBPU OB INPUTS: I, T OUTPUT: O INPUT: I OUTPUT: O BBW INPUTS: I, T OUTPUT: O INOUT: B OB: Output Buffer I O MIPI BB: Bi-directional Buffer T A I OB INPUT: I OUTPUT: O OHSLS AN HSSEL OLS IMIPI OB INPUTS: A, AN, HSSEL OUTPUTS: OHSLS, OLS BB INPUTS: I, T OUTPUT: O INOUT: B 10-16 ECP5 sysIO Usage Guide Instance Examples Input Buffer (IB) VHDL: component IB port (I: in end component; std_logic; O: out std_logic); Inst_IB: IB port map (I=>clk, O=>buf_clk); Verilog: IB IB_inst (.I(Data[7]), .O(buf_Data7)); Output Buffer (OB) VHDL: component OB port (I: in std_logic; O: out std_logic); Inst_OB0: OB port map (I=>buf_qo0, O=>q(0)); Verilog: IB IB_inst (.I(Data[7]), .O(buf_Data7)); Bi-directional Buffer (BB) VHDL: component BB port (I: in std_logic; T: in std_logic; O: out std_logic; B: inout std_logic); end component; buf7: BB port map (I=>Q_out7, T=>Q_tri7, O=>buf_Data7, B=>Data(7)); Verilog: BB buf7 (.I(Q_out7), .T(Q_tri7), .O(buf_Data7), .B(Data[7])); 10-17 ECP5 sysIO Usage Guide Appendix B. sysIO Attribute Examples IO_TYPE VHDL: ATTRIBUTE ATTRIBUTE ATTRIBUTE ATTRIBUTE ATTRIBUTE IO_TYPE: string; IO_TYPE OF portA: IO_TYPE OF portB: IO_TYPE OF portC: IO_TYPE OF portD: SIGNAL SIGNAL SIGNAL SIGNAL IS IS IS IS "LVCMOS18"; "LVCMOS33"; "SSTL33_II"; "LVCMOS25"; Verilog output [4:0] portA /* synthesis IO_TYPE="LVTTL33" DRIVE="16" PULLMODE="UP" SLEWRATE="FAST"*/; OPENDRAIN VHDL: ATTRIBUTE OPENDRAIN: string; ATTRIBUTE OPENDRAIN OF q_lvttl33_17: SIGNAL IS "ON"; Verilog: output [4:0] portA /* synthesis attribute OPENDRAIN of q_lvttl33_17 is ON */; DRIVE VHDL: ATTRIBUTE DRIVE: string; ATTRIBUTE DRIVE OF portD: SIGNAL IS "8"; Verilog: output [4:0] portA /* synthesis DRIVE = "8" */; DIFFDRIVE VHDL: ATTRIBUTE DIFFDRIVE: string; ATTRIBUTE DIFFDRIVE OF portF: SIGNAL IS "3.5"; Verilog: output [4:0] portF/* synthesis IO_TYPE="LVDS" DIFFDRIVE="3.5" */; TERMINATION VHDL: ATTRIBUTE TERMINATION: string; ATTRIBUTE TERMINATION OF portF: SIGNAL IS "50"; Verilog: output [4:0] portA /* synthesis IO_TYPE="SSTL18_I" TERMINATION = "50"*/; 10-18 ECP5 sysIO Usage Guide DIFFRESISTOR VHDL: ATTRIBUTE DIFFRESISTOR: string; ATTRIBUTE DIFFERESISTOR OF portF: SIGNAL IS "100"; Verilog: output [4:0] portA /* synthesis IO_TYPE="LVDS" DIFFRESISTOR = "100"*/; PULLMODE VHDL: ATTRIBUTE PULLMODE: string; ATTRIBUTE PULLMODE OF portF: SIGNAL IS "PULLUP"; Verilog: output [4:0] portA /* synthesis IO_TYPE="LVCMOS33" PULLMODE = "PULLUP"*/; SLEWRATE VHDL: ATTRIBUTE SLEWRATE: string; ATTRIBUTE SLEWRATE OF portF: SIGNAL IS "FAST"; Verilog: output [4:0] portA /* synthesis IO_TYPE="LVCMOS33" SLEWRATE = "FAST"*/; CLAMP VHDL: ATTRIBUTE CLAMP: string; ATTRIBUTE CLAMP OF portF: SIGNAL IS "ON"; Verilog: output [4:0] portA /* synthesis IO_TYPE="LVCMOS33" CLAMP = "ON"*/; HYSTERESIS VHDL: ATTRIBUTE HYSTERESIS: string; ATTRIBUTE HYSTERESIS OF portF: SIGNAL IS "ON"; Verilog: output [4:0] portA /* synthesis IO_TYPE="LVCMOS25" 10-19 HYSTERESIS = "ON"*/; ECP5 sysIO Usage Guide Appendix C. sysIO Buffer Design Rules 1. Only one VCCIO level is allowed in a given bank. a. If VCCIO for any bank is set to 2.5 V, it is recommended that it be connected to the same power supply as VCCAUX, thus minimizing leakage. The software will issue a message in the .pad file to the user about this if the VCCIO of a bank is set to 2.5 V. 2. When an output is configured as an OPENDRAIN, the PULLMODE is set to NONE and the CLAMP setting is set to OFF. a. When an output is configured as an OPENDRAIN, it can be placed independent of VCCIO. 3. When a ratioed input buffer is placed in a bank with a different VCCIO (mixed mode), the Pull mode options of Up are no longer available 4. Left and right banks can support LVDS input buffers. True LVDS outputs are supported on 50% of the sysIO pins of left and right banks. True LVDS outputs are available only on the A and B pairs of the I/O pairs of left and right banks. Emulated differential outputs are available on every output pair. Pad information can be found in the data sheet of the pad file. a. The IO_TYPE attribute for a differential buffer can only be assigned to the TRUE pad. The Lattice Diamond design tool will automatically assign the other I/O of the differential pair to the complementary pad. 5. DIFFRESISTOR termination is available on all sysIO pairs of left and right banks. 6. If none of the pins is used for a given bank, the VCCIO of the bank should be grounded except the JTAG bank. 10-20 ECP5 sysIO Usage Guide Appendix D. sysIO Attributes Using the Diamond Spreadsheet View User Interface sysIO buffer attributes can be assigned using the Spreadsheet View in Lattice Diamond design software. The Port Assignments Sheet lists all the ports in a design and all the available sysIO attributes in multiple columns. Click on each of these cells for a list of all the valid I/O preferences for that port. Each column takes precedence over the next. Therefore, when you choose a particular IO_TYPE, the columns for the PULLMODE, DRIVE, SLEWRATE and other attributes will only list the valid entries for that IO_TYPE. Pin locations can be locked using the Pin column of the Port Assignments Sheet or using the Pin Assignments Sheet. You can right-click on a cell and go to Assign Pins to see a list of available pins. In Spreadsheet View, go to Design > Preference PIO DRC to look for incorrect pin assignments. You can enter the DIN/DOUT preferences using the Cell Mapping tab. All the preferences assigned using the Spreadsheet view are written into the logical preference file (.lpf). Figure 10-8 shows the Port Assignments Sheet of the Spreadsheet View. For further information on how to use the Spreadsheet View, refer to the Diamond Help documentation, available in the Help menu option of the software. Figure 10-8. Port Attributes Tab of Spreadsheet View 10-21