Lattice USB Type-C Solution Data Sheet Preliminary DS1052 Version 1.3, August 2015 Lattice USB Type-C Solution Data Sheet Introduction August 2015 Preliminary Data Sheet DS1052 General Description The USB Type-C receptacle, plug and cable provide a smaller, thinner and more robust alternative to existing USB interconnects. The Lattice USB Type-C solution targets its use in a variety of platforms ranging from notebooks, PCs, Monitors, down to tablets and smart phones. These solutions are also implemented in Docking Stations, USB chargers and cables where cable detect (CD) electronic intelligence and power delivery (PD) protocols are implemented. The Lattice solution is designed to support USB Type-C cable and Connector and USB Power Delivery specifications with programmable flexibility to support the new and evolving specifications as well as the various levels of complexities required by the end system in a cost effective manner. Features Four solutions cover majority of USB Type-C Power Delivery (PD) and Cable Detect (CD) Applications: • • • • CD/PD for Charger CD/PD-Phy for hosts/devices CD/PD for hosts/devices CD/PD for Docks/Dockable Devices Logic Based PHY Provides Fast Deterministic Response and Low Power • Typical Solution Power 7 mW Standby Power less than 100 uW Flexible 8-bit uC Policy Engine Enables Easy Modifications Supports Fast Development Wide Range of Packages to Match PCB Technology • • • • 36 WLCSP 48 QFN 36 ucBGA 81 ucBGA Ultra-Small Form Factor • As small as 2.078 mm x 2.078 mm USB Type-C PHY USB Type-C Cable Detect (CD) support per USB Cable and Connector Specification v1.0 USB Power Delivery (PD) support per Power Delivery Specification v2.0 • IO capability to drive LED indicator • Industry Proven Solutions Reduce Design Risk • Schematics and BOMS available to minimize system design effort Table 1-1. USB Type-C Device Table Solution Package, Ball Pitch, Dimension Typical End Equipment OPN CD/PD for Charger 48 QFN, 0.50 mm, 7.00 mm x 7.00 mm Charger LIF-UC110-SG48I CD/PD Phy for Hosts/Devices 36 WLCSP, 0.35 mm, 2.078 mm x 2.078 mm Smartphone, Tablet LIF-UC120-SWG36I 36 ucBGA, 0.40 mm, 2.50 mm x 2.50 mm Smartphone, Tablet LIF-UC120-CM36I 81 ucBGA, 0.40 mm, 4.00 mm x 4.00 mm Tablet LIF-UC140-CM81I CD/PD for Hosts/Devices © 2015 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. www.latticesemi.com 1-1 DS1052 Introduction_01.2 Lattice USB Type-C Solution Data Sheet Architecture August 2015 Preliminary Data Sheet DS1052 Architecture Overview Figure 2-1. High-level Functional Block for USB Type-C Physical Layer and Power Detect Protocol CPU/ I2C/SPI AC/ /Other EC Policy Management Layer Policy Engine Layer Protocol Layer Capabilities Register Set Soft Reset Handler Construct Message Policy Manager VDM Engine I2C Slave Controller Policy Engine VBUS Current Sense Timer Interface Timer Block CD Interface Protocol Layer Message TX REGISTER Set Cable and Orientation Detect Protocol Layer Message RX Hard Reset Management SS Select Switch Select CC PHY 4B5B Encoder PHY Interface BMC TX BMC Encoder CRC REGISTER Set BIST Engine VBUS_EN VBUS Discharge Voltage Select 4B5B Decoder Stop/Start Detect BMC Decoder BMC RX CRC © 2015 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. www.latticesemi.com 2-1 DS1052 Architecture_01.3 Architecture Lattice USB Type-C Solution Data Sheet USB CD/PD Charger Solution (Captive Cable) Block Diagram Figure 2-2. USB CD/PD Charger Solution (Captive Cable) Block Diagram CD/PD Manager CD/PD PHY CC VBUS VBUS Power Control CD = Cable Detect PD = Power Delivery Features Supported in Schematics • Downstream Facing Port (DFP) • USB Power Delivery Communication between Port partners • Takes advantage of captive cable to minimize component count 2-2 Type C Connector LIF-UC110 2-3 A B C D 0 0V 0 1 0 0 100nF 10V 47 46 34 13 40 14 17 15 16 19 18 4K7 4K7 R17 CDONE 7 CRESET_B 8 Refer Note 5 VSEL1 VSEL2 VSEL3 VSEL4 VBUS_PG SPI_MISO SPI_MOSI SPI_SCK SPI_SS_B 20 10uF 10V CDONE CRESET_B IOB_2a IOB_0a IOT_44b IOB_24a RGB1 IOB_32a_SO IOB_33b_SI IOB_34a_SCK IOB_35b_CSN IOB_29b IOB_31b IOB_25b_G3 VCCPLL VCC VCC VPP2V5_Top VCCIO0 SPI_VCCIO1 VCCIO2 U1 VBUS_DSICHARGE_EN VBUS_DET_PWM R4 QFN48 DEVICE 5 4 RGB0 IOT_41a IOT_42b IOB_6a IOB_9b IOT_38b IOT_36b IOT_46b_G0 IOT_51a IOT_39a IOT_43a IOB_20a IOB_18a IOT_50b IOT_49a IOT_45a_G1 IOT_37a IOB_8a IOB_16a IOB_13b IOT_48b VBUS_DET 1K C1 0.047uF VBUS Sense All VSEL* lines are programmable, they can ben changed based on customer requirement. VSEL4 can be used to select another output voltage 0 1 0 0 0 12V 19.6V 0 1 30 5 29 100R VCCPLL C11 C12 CLK_IN R16 3V3 33 22 1 2VPP_2V5 24 CDBU0520 1 D1 VSEL1 VSEL2 VSEL3 5V VBUS OUTPUT VOLTAGE SELECT LINES Config / Optional PMIC control via I2C R11 1V2 100nF 100nF 10V 10V 10uF 10V C7 C8 C6 1V2 100nF 100nF 100nF 10V 10V 10V 10uF 10V C5 C3 C2 C4 3V3 4 VBUS_REF Preliminary Schematics VBUS_SOURCE_EN 21 IOB_23b 12 IOB_22a 39 RGB2 TH_PAD 49 44 IOB_3b_G6 45 IOB_5b 48 IOB_4a 41 28 31 2 3 27 25 35 42 26 32 11 10 38 43 37 23 4 9 CC1_TX R8 R6 100R R9 4K7 42R2 DNI CC1_DET_PWM CC1_DET_REF CC1_RX_REF R18 R13 R12 1K 510K 3 3.3nF 10V C9 1K R15 1V2 510K Refer Note 6 CC1_RX CC1_DET CC1_TX_EN Q2 VBUS_SOURCE_EN 510K R2 N-Channel Q1 P-Channel 10m Current Monitor R1 C10 330pF 16V Q3 N-Channel 1W 100R R3 C13 0.047uF 10V CC1 GND CC1 VBUS 2 Date: Size B Monday,30-Mar-15 Project CD_PD_Charger_Captive Title CD_PD_Charger_Captive 1 Sheet (Preliminary Schematics) Lattice Semiconductor Applications Email: [email protected] Phone (503) 268-8001 -or- (800) LATTICE Board Rev 1 of 2 A Schematic Rev 1.6 Notes:1) In case VBUS Current sensing is required, customer can contact Lattice tech support for current sense implementation. 2) CC1_RP resistor value is dependent on current rating. It should be 36KOhm for standard device, 12KOhm for 1.5A device and 4.7KOhm for 3A device. 3)These values are as per Lattice LAB tests. Might need fine-tuning by customer to meet the Eye requirements 4)During configration Lattice device pins are weak pulled-up for time duration of 40ms. 5)RGB0, RGB1 and RGB2 are open drain pins, they required external pull-up. 6)BMC RX reference can be generated with internal PWM, To do that mount R18 component, R12 as DNI and replace R13 with 47nF capacitor. Capacitor C10 is required to meet minimum reciever capacitance 3V3 Q6 N-Channel Q6 is for Device protection CC1_INT 1 not included in BOM Count VBUS VBUS_DSICHARGE_EN VBUS Control section Components are 2 VBUS Power Control scheme shown is logical implmentation, for actual implementation please contact Lattice tech support. Refer Note 3 CC1_RP 36 6 75K R7 510K R5 VBUS VBUS SOURCE 5 to 20V 3 ISENSE 5 A B C D Architecture Lattice USB Type-C Solution Data Sheet Schematics Figure 2-3. USB CD/PD Charger Solution (Captive Cable) Schematic Diagram Architecture Lattice USB Type-C Solution Data Sheet Table 2-1. USB CD/PD Mobile System Solution (Captive Cable) BOM Item Quantity Reference Part 1 2 C1, C13 2 3 C2, C6, C12 10 uF CAP CER 10 uf 10 V 10% X5R 0805 3 6 C4, C5, C7, C3, C8, C11 100 nF CAP CER 100 nf 10 V 10% X5R 0402 4 1 C9 3.3 nF CAP CER 3300 pF 10 V 5% U2J 0402 5 1 C10 330 pF CAP CER 330 pF 16 V 10% X7R 0402 6 1 D1 CDBU0520 DIODE SCHOTTKY 20 V 500 MA 0603 7 1 Q1 P-Channel MOSFET P-CH 20 V 6 A SOT-23 8 1 Q3 N-Channel MOSFET N-CH 20 V 6.3 A SOT-23 0.047 uF DESCRIPTION CAP CER 0.047 uf 10 V 10% X5R 0402 9 2 Q2, Q6 N-Channel 10 2 R4, R15 1K MOSFET N-CH 30 V 0.85 A SOT23 11 4 R2, R5, R12, R13 510K RES 510 kOhm 1/16 W 5% 0402 12 1 R8 100R RES SMD 100 Ohm 1% 1/16 W 0402 RES 1 kOhm 1/16 W 5% 0402 13 3 R6, R16, R17 4K7 RES 150 Ohm 1/16 W 1% 0402 SMD 14 1 R11 100R RES 100 Ohm 1/16 W 5% 0402 15 1 R9 42.2R RES SMD 42.2 Ohm 1% 1/16 W 0402 16 1 R3 100R RES SMD 100 Ohm 1% 1 W 2512 17 1 R7 75K RES SMD 75 kOhm 5% 1/16 W 0402 18 1 R1 10m RES 0.01 Ohm 1/2 W 1% 1206 19 1 U1 LIF-UC LIF-UC 48-Pin Device Table 2-2. USB CD/PD Mobile System Solution (Captive Cable) BOM Count1, 2 Item Component Count 1 Cap 13 2 FET 1 3 Resistor 12 4 Lattice LIF-UC 1 1. VBUS control section components are not Included in the BOM count. 2. Diode D1 is not included in the BOM count. It is required only during onboard NVCM programming. 2-4 Architecture Lattice USB Type-C Solution Data Sheet USB CD/PD Charger Solution (Non-Captive Cable) Block Diagram Figure 2-4. USB CD/PD Charger Solution (Non-Captive Cable) Block Diagram CD/PD Manager CD/PD PHY CC VBUS VBUS Power Control CD = Cable Detect PD = Power Delivery Features Supported in Schematics • DFP • USB Power Delivery Communication between Port partners • Provides cable flip support needed in chargers with receptacles 2-5 Type C Connector LIF-UC110 A B C D 0 0 0 0 19.6V 0V 0 1 0 30 5 24 100nF 10V 47 46 34 13 40 14 17 15 16 19 18 4K7 7 4K7 CDONE CRESET_B 8 R22 Refer Note 5 VSEL1 VSEL2 VSEL3 VSEL4 VBUS_PG SPI_MISO SPI_MOSI SPI_SCK SPI_SS_B 20 10uF 10V 29 100R VCCPLL C11 C12 CLK_IN R18 3V3 0 VPP_2V5 33 22 1 CDONE CRESET_B IOB_2a IOB_0a IOT_44b IOB_24a RGB1 IOB_32a_SO IOB_33b_SI IOB_34a_SCK IOB_35b_CSN IOB_29b IOB_31b IOB_25b_G3 VCCPLL VCC VCC VPP2V5_Top VCCIO0 SPI_VCCIO1 VCCIO2 U1 VBUS_DSICHARGE_EN R4 5 4 1K C1 0.047uF RGB0 IOT_41a IOT_42b IOB_6a IOB_9b IOT_38b IOT_36b IOT_46b_G0 IOT_51a IOT_39a IOT_43a IOB_20a IOB_18a IOT_50b IOT_49a IOT_45a_G1 IOT_37a IOB_8a IOB_16a IOB_13b IOT_48b VBUS_DET QFN48 DEVICE All VSEL* lines are programmable, they can be changed based on customer requirement. VSEL4 can be used to select another output voltage. 1 0 12V 0 1 2 CDBU0520 1 D1 VSEL1 VSEL2 VSEL3 5V VBUS OUTPUT VOLTAGE SELECT LINES Config / Optional PMIC control via I2C R11 1V2 100nF 100nF 10V 10V 10uF 10V C7 C8 C6 1V2 100nF 100nF 100nF 10V 10V 10V C5 10uF 10V C4 C3 C2 3V3 VBUS Sense VBUS_REF 41 28 31 2 3 27 25 35 42 26 32 11 10 38 43 37 23 4 4K7 100R R9 R13 R12 CC2_DET_PWM CC2_DET_REF CC1_DET_PWM CC1_DET_REF CC_RX_REF CC2_VCONN_EN DNI 1K R21 CC2_RX CC2_DET CC2_TX_EN 42R2 100R R14 4K7 N-Channel Q1 R1 10m Current Monitor 3V3 CC1_INT Q6 N-Channel 3.3nF 10V C17 R20 R19 0.047uF 10V C16 510K 1K 1V2 510K VBUS_DSICHARGE_EN VBUS Q3 N-Channel 1W 100R R3 C15 0.047uF 10V 3 4K7 R23 4K7 R24 5 7 4 2 9 1 IN2 NC2 NO2 NO1 NC1 IN1 TS5A23159RSER VCONN_5V VCONN_5V VCONN_5V VCONN SPDT Switch U2 COM2 COM1 330pF 330pF 16V 16V C14 CC2 6 C10 CC1 10 GND CC2 TYPE C CC1 VBUS 2 Date: Size B Monday,25-May-15 1 Sheet Project CD_PD_Charger_Non_Captive (Preliminary Schematics) Title CD_PD_Charger_Non_Captive Lattice Semiconductor Applications Email: [email protected] Phone (503) 268-8001 -or- (800) LATTICE Board Rev 1 of 1 A Schematic Rev 1.7 Notes:1) In case VBUS Current sensing is required, customer can contact Lattice tech support for current sense implementation. 2) CC1_RP and CC2_RP resistor value is dependent on current rating. It should be 36KOhm for standard device, 12KOhm for 1.5A device and 4.7KOhm for 3A device. 3)These values are as per Lattice LAB tests. Might need fine-tuning by customer to meet the Eye requirements 4)During configration Lattice device pins are weak pulled-up for time duration of 40ms. 5)RGB0, RGB1 and RGB2 are open drain pins, they required external pull-up. 6)BMC RX reference can be generated with internal PWM, To do that mount R21 component, R16 as DNI and replace R17 with 47nF capacitor. Q7 N-Channel Sch Rev 1.7 Changes :1.Added VCONN SPDT switch for SOP' support. 1K R17 R16 3V3 CC2_INT 1 are not included in BOM Count Capacitor C10 and C14 are required to meet minimum reciever capacitance Q7 is for Device protection Q6 is for Device protection 3.3nF 10V C9 Refer Note 6 42R2 Refer Note 3 CC2_TX CC2_RP CC1_VCONN_EN Q2 VBUS_SOURCE_EN 510K R2 P-Channel 2 VBUS Power Control scheme shown is logical implmentation, for actual implementation please contact Lattice tech support. Refer Note 3 CC1_DET CC1_RX SOURCE 5 to 20 V R8 R6 CC1_TX_EN CC1_TX 9 CC1_RP 36 6 75K R7 510K R5 VBUS 3 VBUS Control section Components ISENSE Preliminary Schematics VBUS_SOURCE_EN 21 IOB_23b 12 IOB_22a VBUS_DET_PWM 44 IOB_3b_G6 45 IOB_5b 48 IOB_4a 4 V+ 8 GND 39 RGB2 TH_PAD 49 2-6 3 5 A B C D Architecture Lattice USB Type-C Solution Data Sheet Schematics Figure 2-5. USB CD/PD Charger Solution (Non-Captive Cable) Schematic Diagram Architecture Lattice USB Type-C Solution Data Sheet BOM Table 2-3. USB CD/PD Charger Solution (Non-Captive Cable) BOM Item Quantity 1 3 C1, C15, C16 Reference Part 2 3 C2, C6, C12 10 uF CAP CER 10 uf 10 V 10% X5R 0805 3 6 C4, C5, C7, C3, C8, C11 100 nF CAP CER 100 nf 10 V 10% X5R 0402 4 2 C9, C17 3.3 nF CAP CER 3300 pF 10.V 5% U2J 0402 5 2 C10, C14 330 pF CAP CER 330 pF 16 V 10% X7R 0402 6 1 D1 CDBU0520 DIODE SCHOTTKY 20 V 500 MA 7 1 Q1 P-Channel MOSFET P-CH 20 V 6 A SOT-23 0.047 uF DESCRIPTION CAP CER 0.047 uf 10 V 10% X5R 0402 8 1 Q3 N-Channel MOSFET N-CH 20 V 6.3 A SOT-23 9 3 Q2, Q6, Q7 N-Channel MOSFET N-CH 30 V 0.85 A SOT23 10 3 R4, R19, R20 11 4 R2, R5, R16, R17 12 6 R6, R12, R18, R22, R23, R24 13 2 R8, R13 100R 1K 510K 4K7 RES 1K Ohm 1/16 W 5% 0402 RES 510K Ohm 1/16 W 5% 0402 RES 4.7K Ohm 1/16 W 5% 0402 RES SMD 100 Ohm 1% 1/16 W 0402 14 2 R9, R14 42.2R RES SMD 42.2 Ohm 1% 1/16 W 0402 15 1 R11 100R RES 100 Ohm 1/16 W 5% 0402 16 1 R3 100R RES SMD 100 Ohm 1% 1 W 2512 17 1 R7 75K 18 1 R1 10m 19 1 U1 LIF-UC 20 1 U2 TS5A23159RSER RES SMD 75 kOhm 5% 1/16 W 0402 RES 0.01 Ohm 1/2 W 1% 1206 LIF-UC 48-Pin Device Switch Dual SPDT BOM Count Table 2-4. USB CD/PD Charger Solution (Non-Captive Cable) BOM Count1, 2 Item Component Count 1 Cap 16 2 FET 2 3 Resistor 18 4 Lattice LIF-UC 1 5 Dual SPDT 1 1. VBUS control section components are not Included in the BOM count. 2. Diode D1 is not included in the BOM count. It is required only during onboard NVCM programming. 2-7 Architecture Lattice USB Type-C Solution Data Sheet CD/PD PHY for Host/Devices Block Diagram Figure 2-6. CD/PD PHY for Host/Devices Block Diagram Tx1/Rx1 Tx/Rx SS Switch SS Sel Tx2/Rx2 Type-C Connector USB Chipset LIF-UC120 AP SPI CD/PD PHY+ IRPT PD Manager VBUS Power Control CC VBUS Power Control VBUS CD = Cable Detect PD = Power Delivery Features Supported in Schematics • Dual Role Port (DRP) • USB Power Delivery Communication between Port partners • Dead Battery Support • SPI Config interface is reused as SPI interface post configuration. SPI is used to interface PD to AP/Controller/Processor. Note: VCONN supports up to 1 W power at 5 V supply. 2-8 A B C D Switch SS IOB_31B IOB_30A IOB_29B IOB_25B_G3 IOB_20A IOB_16A RGB2 RGB1 CDONE IOB_26A IOB_27B IOB_11B_G5 IOB_10A IOB_6A/TRUE_of_IOB_7B IOB_7B/COMP_of_IOB_11B IOB_5B/COMP_of_IOB_4A IOB_2A/TRUE_of_IOB_3B IOB_3B_G6/COMP_of_IOB_2a IOB_4A/TRUE_of_IOB_5B CRESET_B RGB0 IRLED IOT_46B_G0 IOB_32A_SPI_SO/TRUE_of_IOB_33B IOB_33B_SPI_SI/COMP_of_IOB_32A IOB_34A_SPI_SCK/TRU_of_IOB_35B IOB_35B_SPI_CSN/COMP_of_IOB_34A VCCIO_0 SPI_VCCIO1 VCCIO_2 VCC VCCPLL VPP_2V5 U1 B2 C1 E2 C2 E3 F3 A6 B6 E4 B1 D2 F4 B4 F5 E5 D5 F6 E6 D6 1V2 R2 C17 0.047uF 10V C18 0.047uF 10V 10uF 10V C1 36K 5K1 36K 5K1 100nF 10V C2 VCC_PLL 3.3nF 10V 100R 42R2 C13 510K1V2 100R CC_TX_RX_EN CC1_RP R10 CC1_RD R11 CC2_RP R12 CC2_RD R13 CC_SEL CC1_VCONN_EN_n CC2_VCONN_EN_n DB_DISABLE 510K R52 CC_RX CC_RX_REF CC_TX R22 CC_TX_EN R23 R51 1K R43 1K R42 Refer Note 7 CC2_DET_PWM CC2_DET CC2_DET_REF CC1_DET_PWM CC1_DET CC1_DET_REF 10uF 10V C3 5 4 7 9 2 1 U4 COM2 COM1 3V3 100nF 10V C4 1V2 10uF 10V C5 TS5A23159RSER IN2 NO2 NC2 NC1 NO1 IN1 U11 CC Select Mux 3 6 10 100nF 10V C6 3V3 Q14 Q13 3V3 R20 R21 100nF 10V C7 100K 100K 100K R19 3V3 N-Channel 3V3 Control VBUS Power & Discharge 9 2 1 5 4 7 U4 COM2 COM1 TS5A23159RSER IN2 NO2 NC2 NC1 NO1 IN1 U10 VCONN_5V 2 1 A NC 4 SN74LV1T34DCKR Y U5 VCONN_5V VCONN Power Control VCONN_5V VCONN_5V 1 VBUS Q15 P-Channel 510K R53 5K1 R55 C22 510K Q16 5K1 R56 Batttery P-Channel DNI 330pF 16V R54 Dead CC2 6 C23 DNI 330pF 16V CC1 10 Capacitor C22 and C23 are required to meet minimum reciever capacitance are for device protection Refer note 6 N-Channel Q13 and Q14 EC/AP 2 5 4 3 2 Date: Size B Monday,30-Mar-15 Project CD_PD_PHY_Hosts_Devices Title CD_PD_PHY_Hosts_Devices 1 Sheet (Preliminary Schematics) 1) CC1_RP and CC2_RP resistor value is dependent on current rating. It should be 36KOhm for standard device, 12KOhm for 1.5A device and 4.7Kohm for 3A device. 2)All VBUS control (enable/disable/discharge) is done by AP/EC and the data is provided back to PD by SPI in order to detect the presence of external source. 3)SS or HS switch control is done by AP/EC. The orientation info can be provided over SPI register interface by Lattice PD. 4) Discrete FET based logic can also be used instead of SPDT switch (U10)Contact Lattice tech support for details 5)RGB0 and IRLED are open drain pins, they required external pull-up. 6)VCONN_5V should be sequenced, It should come after Lattice device is configured. Lattice Semiconductor Applications 7)These values are as per Lattice LAB tests. Might need fine-tuning by customer to meet the Eye requirements. Email: [email protected] 8)During configration Lattice device pins are weak pulled-up for time duration of 40ms. Phone (503) 268-8001 -or- (800) LATTICE Notes:- From EC/AP CONFIG & EC/AP 5K1 R16 A4 C3 C4 A5 B3 D4 CRESET_B D3 EC_INT C6 EC_CS A2 CLK_IN B5 SPI_MISO F2 SPI_MOSI D1 SPI_SCK E1 SPI_SS_B F1 3V3 2VPP_2V5 CDBU0520 1 D1 VCC_PLL1V2 Refer Note 5 3V3 4 V+ 8 GND Preliminary Schematics GND A3 GND C5 GND_LED A1 5 V G 2-9 3 3 V+ 8 GND 3 5 Board Rev 1 of 1 A Schematic Rev 1.3 GND CC2 TYPE C CC1 VBUS A B C D Architecture Lattice USB Type-C Solution Data Sheet Schematics Figure 2-7. CD/PD Phy for Hosts/Devices Schematic Diagram Architecture Lattice USB Type-C Solution Data Sheet BOM Table 2-5. CD/PD Phy for Hosts/Devices BOM Item Quantity 1 3 C1, C3, C5 Reference 10 uF Part CAP CER 10 uf 10 V 10% X5R 0805 Description BOM_Note 2 4 C2, C4, C6, C7 100 nF CAP CER 100 nf 10 V 10% X5R 0402 3 1 C13 3.3 nF CAP CER 3300 pF 10 V 5% U2J 0402 4 2 C17, C18 0.047 uF CAP CER 0.047 uf 10 V 10% X5R 0402 5 2 C22, C23 330 pF CAP CER 330 pF 16 V 10% X7R 0402 6 1 D1 CDBU0520 DIODE SCHOTTKY 20 V 500 mA 0603 7 2 Q13, Q14 N-Channel MOSFET N-CH 30 V 0.85 A SOT23 8 2 Q15, Q16 P-Channel MOSFET P-CH 20 V 760 mA SOT-416 9 1 R2 100R RES 100 Ohm 1/16 W 5% 0402 10 2 R10, R12 36K RES 36K Ohm 1/16 W 5% 0402 11 5 R11, R13, R16, R55, 5K1 R56 RES 5.1K Ohm 1/16 W 5% 0402 12 3 R19, R20, R21 100K RES 100K Ohm 1/16 W 5% 0402 13 1 R22 100R RES SMD 100 Ohm 1% 1/16 W 0402 14 1 R23 42R2 RES SMD 42.2 Ohm 1% 1/16 W 0402 15 2 R42, R43 1K RES 1 kOhm 1/16 W 5% 0402 16 4 R51, R52, R53, R54 510K RES 510 kOhm 1/16 W 5% 0402 17 1 U1 LIF UC LIF UC 36 Pin device 18 1 U5 SN74LV1T34DCKR IC BUFFER GATE SGL CMOS SC70-5 19 2 U10, U11 TS5A23159RSER SWITCH DUAL SPDT BOM Count Table 2-6. CD/PD Phy for Hosts/Devices BOM Count1 Item Component Count 1 Cap 12 2 FET 4 3 Resistor 19 4 Dual SPDT 2 5 Level Translator 1 6 Lattice LIF-UC 1 1. Diode D1 is not included in the BOM count. It is required only during onboard NVCM programming. 2-10 DNI Architecture Lattice USB Type-C Solution Data Sheet CD/PD for Hosts/Devices Block Diagram Figure 2-8. CD/PD for Hosts/Devices Block Diagram Tx1/Rx1 USB Chipset SS Switch Tx/Rx Tx2/Rx2 Type-C Connector Video LIF-UC140 SPI IRPT AP/ CPU/ EC CD/PD Manager CD/PD PHY VBUS Power Control CC VBUS Power Control VBUS CD = Cable Detect PD = Power Delivery Features Supported in Schematics • Dual Role Port (DRP) • USB Power Delivery Communication between Port partners • SS/HS switch control • VBUS Source/Sink and Discharge Control signals • Alternate mode support • SPI Config interface is reused as SPI interface post configuration. SPI is used to interface PD to AP/Controller/Processor. Note: VCONN supports up to 1 W power at 5 V supply. 2-11 A B C A5 H8 CLK D8 E8 5 CM81 IOR_109 IOR_110 IOR_111 IOR_112 IOR_113 IOR_114 IOR_115 IOR_116 IOR_117 IOR_118 IOR_119 IOR_120 IOR_148 TP1 100nF C18 G6 H7 G7 F7 i/o's 100nF C20 AP/EC Optional CONFIGS & 4 D3 E3 100nF C10 H3 J8 J9 H9 G9 F8 G8 D6 A9 D7 E7 D9 B9 C9 CC2_RP CC2_RD CC1_RP CC1_RD SS_SEL1 SS_SEL2 SS_SEL3 Notes:- 36K 5K1 36K 5K1 DB_DISABLE CM81 3V3 IOL_13B_GBIN7 IOL_14A_GBIN6 BANK3 VCCIO_3 100K R37 IOL_2B IOL_2A IOL_3A IOL_3B IOL_7A IOL_7B IOL_10B IOL_10A IOL_13A IOL_14B IOL_22B IOL_22A IOL_24A IOL_24B IOL_26B IOL_26A IOB_82_GBIN4 IOB_81_GBIN5 IOB_103_CBSEL0 IOB_104_CBSEL1 CDONE CRESET_B BANK2 B2 C2 B1 C1 D2 C3 E1 D1 E2 E4 F3 F1 G3 G1 H2 G2 IOB_54 IOB_55 IOB_56 IOB_57 IOB_70 VBUS_DET_PWM VBUS_IN 3.3nF 10V C5 510K C19 CC2_RX_REF CC1_RX_REF 100nF U3 R22 R21 510K 510K COMP_2CH 3V3 R12 510K 510K R13 3V3 510K R26 510K R23 1V2 510K 510K R20 R18 4 3 2 1 510K R6 Q4 P-Channel Q1 P-Channel N-Channel Q2 P-Channel 3V3 3V3 Q7 R15 VBUS N-Channel 100R VBUS DISCHARGE Q8 N-Channel 2 1 A NC 4 2 IN2 NC2 NO2 NO1 NC1 IN1 Dead Q10 Size B Date: U2 COM2 COM1 C11 C12 510K R36 P-Channel 5K1 CC2 6 Q11 5K1 R42 CC1 R41 330pF 330pF 10 Lattice Semiconductor Applications Email: [email protected] Phone (503) 268-8001 -or- (800) LATTICE Batttery P-Channel 510K R35 TS5A23159RSER 5 7 4 2 9 1 VCONN_5V Wednesday,20-May-15 1 Sheet Project CD_PD_Hosts_Devices (Preliminary schematics) Title CD_PD_Hosts_Devices 5K1 5K1 R39 R38 VCONN_5V CC2_VCONN_EN CC1_VCONN_EN VCONN_5V SN74LV1T04DCKR Y U5 VCONN_5V Q9 N-Channel CC1_INT 510K R7 VBUS Control section Components are not included in BOM Count Q6 N-Channel VBUS_SINK_EN Q3 P-Channel Q5 VBUS_SOURCE_EN SOURCE SINK GND Board Rev 1 of 1 A Schematic Rev 1.6 TYPE C GND CC2 CC1 VBUS VBUS Power Control scheme shown is logical implmentation, for actual implementation please contact Lattice tech support. Capacitor C11 and C12 are required to meet minimum reciever capacitance VBUS Q8 and Q9 are for DNI DNI Device protection Refer note 3 510K 510K R19 R17 VBUS CC2_INT 3V3 Refer Note 5 R16 R14 510K VBUS_DET 3V3 Refer Note 7 510K 510K R9 VBUS_SOURCE_EN VBUS_SINK_EN BMC RX Comparators 1nF C13 1nF C9 1nF C7 R11 R10 510K 510K R8 CC2_INT Refer Note 4 CC1_INT VBUS SENSING 100R 42R2 3.3nF 10V 100R 42R2 R4 R5 C4 R1 R3 Refer Note 4 VBUS_REF CC2_TX CC2_TX_EN CC1_TX CC1_TX_EN CC1_DET_REF CC1_DET CC1_DET_PWM VBUS_DISCHARGE_EN CC2_DET_REF CC2_DET CC2_DET_PWM H1 J1 J2 J3 J4 3 1) CC1_RP and CC2_RP resistor value is dependent on current rating. It should be 36Kohms for standard device, 12Kohms for 1.5A device and 4.7KOhms for 3A device. 2) Discrete FET based logic can also be used instead of SPDT switch (U2)Contact Lattice tech support for details 3) VCONN_5V should be sequenced, It should come after Lattice device is configured. 4) These values are as per Lattice LAB tests. Might need fine-tuning by customer to meet the Eye requirements. 5)Regressive LAB tests ongoing for Sigma Delta ADC 6)During configration Lattice device pins are weak pulled-up for time duration of 40ms. 7)Incase VBUS is greater than 5V, Adjust R19 to map the voltage across R19 is not greter than to 3.3V. R31 R32 R33 R34 SS SEL U1C VCCIO_2 CM81 U1D H4 G4 EC_INT EC_CS 3V3 G5 H5 E6 H6 CDONE CRESET_B 5K1 J5 100nF R40 C1 3V3 SS Switch selection signals HPD 100nF C17 B8 A8 A7 B7 B6 A6 B5 A4 B4 D5 E5 A3 B3 A2 A1 3V3 CDBU0520 D1 VPP_2V5 2 1 VPP_FAST 1V2 IOB_105_SDO IOB_106_SDI IOB_107_SCK IOB_108_SS IOR_141_GBIN2 IOR_140_GBIN3 BANK1 VCCIO_1 100nF C16 IOT_170 IOT_174 IOT_177 IOT_180 IOT_183 IOT_185 IOT_188 IOT_208 IOT_211 IOT_212 IOT_214 IOT_217 IOT_218 IOT_221 IOT_224 CM81 SPI VCC_SPI U1E U1B 10uF C6 C15 1uF C14 F2 D4 E9 C8 C7 Configuration IOT_198_GBIN0 IOT_197_GBIN1 BANK0 CM81 CLK_IN 100nF C21 POWER GNDPLL0 GND GND GND GND CM81 VCCIO_0 U1A 1V2 C4 C5 100nF C8 3V3 100nF C6 3V3 3V3 C3 10uF100nF J6 10V 10V GNDPLL0 F9 F4 F5 F6 C2 VCC VCC VCC VPP_2V5 VPP_FAST 1 VCCPLL0 SPI_MISO U1F SPI_MOSI J7 100R VCCPLL0 SPI_SCK D R2 SPI_SS_B 5 CC_RX_REF Preliminary Schematics 5 V G 3 V+ 8 GND 2-12 3 1V2 A B C D Architecture Lattice USB Type-C Solution Data Sheet Schematics Figure 2-9. CD/PD for Hosts/Devices Schematic Diagram Architecture Lattice USB Type-C Solution Data Sheet BOM Table 2-7. CD/PD for Hosts/Devices BOM Item Quantity 1 11 C1, C3, C6, C8, C10, C16, 100 nF C17, C18, C19, C20, C21 Reference Part CAP CER 100 nf 10V 10% X5R 0402 DESCRIPTION 2 2 C2, C14 10 uF CAP CER 10 uf 10 V 10% X5R 0805 3 2 C4, C5 3.3 nF CAP CER 3300 PF 10 V 5% U2J 0402 4 3 C7, C9, C13 1 nF CAP CER 1000 PF 10 V 10% X5R 0402 5 2 C11, C12 330 pF CAP CER 330 PF 16 V 10% X7R 0402 6 1 C15 1 uF CAP CER 1 uf 10V 10% X5R 0402 7 1 D1 CDBU0520 DIODE SCHOTTKY 20 V 500 MA 0603 8 4 Q1, Q2, Q3, Q4 P-Channel MOSFET P-CH 20 V 6 A SOT-23 9 4 Q5, Q6, Q8, Q9 N-Channel MOSFET N-CH 30 V 0.85 A SOT23 10 1 Q7 N-Channel MOSFET N-CH 20 V 6.3 A SOT-23 11 2 Q10, Q11 P-Channel MOSFET P-CH 20 V 760 MA SOT-416 12 2 R1, R4 100R RES SMD 100 Ohm 1% 1/16 W 0402 13 1 R2 100R RES 100 OHM 1/16 W 5% 0402 14 2 R3, R5 42R2 RES SMD 42.2 Ohm 1% 1/16 W 0402 15 20 R6, R7, R8, R9, R10, R11, 510K R12, R13, R14, R16, R17, R18, R19, R20, R21, R22, R23, R26, R35, R36 16 1 R15 100R RES SMD 100 Ohm 1% 1 W 2512 17 2 R31, R33 36K RES 36K Ohm 1/16 W 5% 0402 18 7 R32, R34, R38, R39, R40, 5K1 R41, R42 RES 5.1K Ohm 1/16 W 5% 0402 19 1 R37 100K RES 100K Ohm M 1/16 W 5% 0402 20 1 U1 LIF-UC LIF-UC 81 Pin Device RES 510K Ohm 1/16 W 5% 0402 21 1 U2 TS5A23159RSER SWITCH DUAL SPDT 22 1 U3 COMP_2CH IC COMPARATR P-P NANOPWR SOT23-8 23 1 U5 SN74LV1T04DCKR IC BUFFER GATE SGL CMOS SC70-5 BOM Count Table 2-8. CD/PD for Hosts/Devices BOM Count1, 2 Item Component Count 1 CAP 21 2 FET 4 3 Resistor 33 4 Dual SPDT 1 5 Level Translator 1 6 Comparator 1 6 Lattice LIF-UC 1 1. VBUS control section components are not Included in the BOM count. 2. Diode D1 is not included in the BOM count. It is required only during onboard NVCM programming. 2-13 Lattice USB Type-C Solution Data Sheet DC and Switching Characteristics March 2015 Preliminary Data Sheet DS1052 Absolute Maximum Ratings1, 2, 3 Supply Voltage VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 1.42 V Output Supply Voltage VCCIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 3.60 V NVCM Supply Voltage VPP_2V5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 3.60 V PLL Supply Voltage VCCPLL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 1.42 V I/O Tri-state Voltage Applied. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 3.60 V Dedicated Input Voltage Applied . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 3.60 V Storage Temperature (Ambient). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65 °C to 150 °C Junction Temperature (TJ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65 °C to 125 °C 1. Stress above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. 2. Compliance with the Lattice Thermal Management document is required. 3. All voltages referenced to GND. Recommended Operating Conditions1 Symbol VCC1 VPP_2V5 VCCIO Parameter Min. Max. Units Core Supply Voltage 1.14 1.26 V Slave SPI Configuration 1.71 3.46 V Master SPI Configuration 2.30 3.46 V VPP_2V5 NVCM Programming and Operating Supply Voltage 1, 2, 3 I/O Driver Supply Voltage VCCPLL Configuration from NVCM 2.30 3.46 V NVCM Programming 2.30 3.00 V VCCIO_0, SPI_VCCIO1, VCCIO_2 1.71 3.46 V 1.14 1.26 V PLL Supply Voltage tJCOM Junction Temperature Commercial Operation 0 85 °C tJIND Junction Temperature Industrial Operation –40 100 °C tPROG Junction Temperature NVCM Programming 10.00 30.00 °C 1. Like power supplies must be tied together if they are at the same supply voltage and they meet the power up sequence requirement. Please refer to Power-up Sequence section. VCC and VCCPLL are not recommended to be tied together. Please refer to TN1252, iCE40 Hardware Checklist. 2. See recommended voltages by I/O standard in subsequent table. 3. VCCIO pins of unused I/O banks should be connected to the VCC power supply on boards. Power Supply Ramp Rates1, 2 Symbol tRAMP Parameter Power supply ramp rates for all power supplies. Min. Max. Units 0.6 10 V/ms 1. Assumes monotonic ramp rates. 2. Power up sequence must be followed. Please refer to Power-up Sequence section. © 2015 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. www.latticesemi.com 3-1 DS1052 Architecture_01.1 DC and Switching Characteristics Lattice USB Type-C Solution Data Sheet Power-up Sequence For all LIF-UC devices, it is required to have the VPP_2V5 to be powered up last among the supplies that are monitored by POR circuitry (VCC, SPI_VCCIO1, and VPP_2V5). All supply voltages need to be powered up during configuration. For the 36-pin WLCSP package (SWG36), the Power Up sequence is: VCC and VCCPLL, SPI_VCCIO1, VPP_2V5, VCCIO0 and VCCIO2. Each supply has to wait until the previous supplies in the sequence have reached 0.5 V or higher. There is no power down sequence required. However, when partial power supplies are powered down, it is required the above sequence to be followed when these supplies are re-powered up again. Power-On-Reset Voltage Levels1 Symbol VPORUP VPORDN Parameter Power-On-Reset ramp-up trip point (circuit monitoring VCC, SPI_VCCIO1, VPP_2V5) Power-On-Reset ramp-down trip point (circuit monitoring VCC, SPI_VCCIO1, VPP_2V5) Min. Max. Units VCC 0.62 0.92 V SPI_VCCIO1 0.87 1.50 V VPP_2V5 0.90 1.53 V VCC — 0.79 V SPI_VCCIO1 — 1.50 V VPP_2V5 — 1.53 V 1. These POR trip points are only provided for guidance. Device operation is only characterized for power supply voltages specified under recommended operating conditions. ESD Performance Please contact Lattice Semiconductor for additional information. DC Electrical Characteristics Over Recommended Operating Conditions Symbol 1, 3, 4 Parameter Condition Min. Typ. Max. Units Input or I/O Leakage 0V < VIN < VCCIO + 0.2 V — — +/–10 µA C1 I/O Capacitance, excluding LED Drivers2 VCCIO = 3.3 V, 2.5 V, 1.8 V VCC = Typ., VIO = 0 to VCCIO + 0.2 V — 6 — pf C2 Global Input Buffer Capacitance2 VCCIO = 3.3 V, 2.5 V, 1.8 V VCC = Typ., VIO = 0 to VCCIO + 0.2 V — 6 — pf C3 RGB Pin Capacitance2 VCC = Typ., VIO = 0 to 3.5 V — 15 — pf VCC = Typ., VIO = 0 to 3.5 V — 53 — pf VCCIO = 1.8 V, 2.5 V, 3.3 V — 200 — mV –3 –8 –11 — –31 –72 –128 µA IIL, IIH C4 IRLED Pin Capacitance VHYST Input Hysteresis IPU Internal PIO Pull-up Current 2 VCCIO = 1.8 V, 0=<VIN<=0.65 VCCIO VCCIO = 2.5 V, 0=<VIN<=0.65 VCCIO VCCIO = 3.3 V, 0=<VIN<=0.65 VCCIO — — µA µA 1. Input or I/O leakage current is measured with the pin configured as an input or as an I/O with the output driver tri-stated. It is not measured with the output driver active. Internal pull-up resistors are disabled. 2. TJ 25 °C, f = 1.0 MHz. 3. Please refer to VIL and VIH in the sysIO Single-Ended DC Electrical Characteristics table of this document. 4. Some products are clamped to a diode when VIN is larger than VCCIO. 3-2 DC and Switching Characteristics Lattice USB Type-C Solution Data Sheet Supply Current 1, 2, 3, 4 Symbol Parameter Typ. VCC = 1.2 V4 Units ICCSTDBY Core Power Supply Static Current 71 µA IPP2V5STDBY VCC_V2P5 Power Supply Static Current 0.55 µA ISPI_VCCIO1STDBY SPI_VCCIO1 Power Supply Static Current 0.5 µA ICCIOSTDBY VCCIO Power Supply Static Current 0.5 µA ICCPEAK Core Power Supply Startup Peak Current 8.0 mA IPP_2V5PEAK VPP_2V5 Power Supply Startup Peak Current 7.0 mA ISPI_VCCIO1PEAK SPI_VCCIO1 Power Supply Startup Peak Current 9.0 mA ICCIOPEAK VCCIO Power Supply Startup Peak Current 7.5 mA 1. Assumes blank pattern with the following characteristics: all outputs are tri-stated, all inputs are configured as LVCMOS and held at VCCIO or GND, on-chip PLL is off. For more detail with your specific design, use the Power Calculator tool. Power specified with master SPI configuration mode. Other modes may be up to 25% higher. 2. Frequency = 0 MHz. 3. TJ = 25 °C, power supplies at nominal voltage, on devices processed in nominal process conditions. 4. Does not include pull-up. User I2C Specifications Parameter Symbol spec (STD Mode) Parameter Description spec (FAST Mode) Min Typ Max Min Typ Max Units fSCL Maximum SCL clock frequency — — 100 — — 400 kHz tHI SCL clock HIGH Time 4 — — 0.6 — — µs tLO SCL clock LOW Time 4.7 — — 1.3 — — µs tSU,DAT Setup time (DATA) 250 — — 100 — — ns tHD,DAT Hold time (DATA) 0 — — 0 — — ns tSU,STA Setup time (START condition) 4.7 — — 0.6 — — µs tHD,STA Hold time (START condition) 4 — — 0.6 — — µs tSU,STO Setup time (STOP condition) 4 — — 0.6 — — µs tBUF Bus free time between STOP and START 4.7 — — 1.3 — — µs tCO,DAT SCL LOW to DATAOUT valid — — 3.4 — — 0.9 µs User SPI Specifications Parameter Symbol Parameter Description Typ Max Units — — 45 MHz 9 — — ns LOW period of SCK clock 9 — — ns Setup time (master mode) 2 — — ns tHOLDmaster Hold time (master mode) 5 — — ns tSUslave Setup time (slave mode) 2 — — ns tHOLDslave Hold time (slave mode) 5 — — ns tSCK2OUT SCK to out (slave mode) — — 13.5 ns fMAX Maximum SCK clock frequency tHI HIGH period of SCK clock tLO tSUmaster Min 3-3 DC and Switching Characteristics Lattice USB Type-C Solution Data Sheet Internal Oscillators (HFOSC, LFOSC)1 Parameter Symbol fCLKHF Parameter Description Spec/Recommended Conditions Units Min Typ –10% 48 10% MHz 48 20.00% MHz Commercial Temp HFOSC clock frequency (tJ = 0 oC–85 oC) Industrial Temp HFOSC clock frequency (tJ = –40 oC–100 oC) –20.00% Max fCLKLF LFOSC CLKK clock frequency –10% 10 10% kHz DCHCLKHF HFOSC Duty Cycle (Clock High Period) 45 50 55 % DCHCLKLF LFOSC Duty Cycle (Clock High Period) 45 50 55 % Tsync_on Oscillator output synchronizer delay — — 5 Cycles Tsync_off Oscillator output disable delay — — 5 Cycles 1. Glitchless enabling and disabling OSC clock outputs. sysIO Recommended Operating Conditions VCCIO (V) Min. Typ. Max. LVCMOS 3.3 3.14 3.3 3.46 LVCMOS 2.5 2.37 2.5 2.62 LVCMOS 1.8 1.71 1.8 1.89 Standard sysIO Single-Ended DC Electrical Characteristics Input/ Output Standard VIH1 VIL Min. (V) Max. (V) Min. (V) Max. (V) LVCMOS 3.3 –0.3 0.8 2.0 VCCIO + 0.2V LVCMOS 2.5 –0.3 0.7 1.7 VCCIO + 0.2V LVCMOS 1.8 –0.3 0.35VCCIO 0.65VCCIO VCCIO + 0.2V VOL Max. (V) VOH Min. (V) IOL Max. (mA) IOH Max. (mA) 0.4 VCCIO – 0.5 8 0.2 VCCIO – 0.2 0.1 0.4 VCCIO – 0.5 6 0.2 VCCIO – 0.2 0.1 0.4 VCCIO – 0.4 4 0.2 VCCIO – 0.2 0.1 –8 –0.1 –6 –0.1 –4 –0.1 1. Some products are clamped to a diode when VIN is larger than VCCIO. Differential Comparator Electrical Characteristics Parameter Symbol Parameter Description VINP, VINM Input Voltage VTHD Differential Input Threshold VCM Input Common Mode Voltage IIN Input Current Test Conditions 1 VCCIO = 2.5 Min. 1. Typical. 3-4 Max. Units 0 — 2.5 V 250 350 450 mV ±10 µA VCCIO1 = 2.5 Power on Typ. VCCIO/2 — — V Lattice USB Type-C Solution Data Sheet Pinout Information March 2015 Preliminary Data Sheet DS1052 Signal Descriptions Signal Name Function I/O Description VCC Power Core Power Supply VCCIO_0, SPI_VCCIO1, VCCIO_2 Power — — VPP_2V5 Power Power GROUND — — — Power for NVCM programming and operations VCCPLL CRESETB Configuration I CDONE Configuration I/O Configuration Done. Includes a weak pull-up resistor to VCCIO_1 General I/O I/O In user mode, after configuration, this pin can be programmed as general I/O in user function Configuration I/O This pin is shared with device configuration. During configuration: In Master SPI mode, this pint outputs the clock to external SPI memory. In Slave SPI mode, this pin inputs the clock from external processor. General I/O I/O In user mode, after configuration, this pin can be programmed as general I/O in user function Configuration Output This pin is shared with device configuration. During configuration: In Master SPI mode, this pint outputs the command data to external SPI memory. In Slave SPI mode, this pin connects to the MISO pin of the external processor. General I/O I/O In user mode, after configuration, this pin can be programmed as general I/O in user function Configuration Input This pin is shared with device configuration. During configuration: In Master SPI mode, this pint receives data from external SPI memory. In Slave SPI mode, this pin connects to the MOSI pin of the external processor. General I/O I/O In user mode, after configuration, this pin can be programmed as general I/O in user function Power Supplies GND Power for I/Os in Bank 0, 1, and 2. Power for PLL. Ground Configuration Configuration Reset, active LOW. No internal pull-up resistor. Either actively driven externally or connect an 10 k-Ohm pullup to VCCIO_1 Config SPI SPI_SCK SPI_SDO SPI_SI © 2015 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. www.latticesemi.com 4-1 DS1052 Pinout Information_01.1 Pinout Information Lattice USB Type-C Solution Data Sheet SPI_CSN CC1_RP Configuration I/O This pin is shared with device configuration. During configuration: In Master SPI mode, this pint outputs to the external SPI memory. In Slave SPI mode, this pin inputs CSN from the external processor. General I/O I/O In user mode, after configuration, this pin can be programmed as general I/O in user function O Enable signal to Connect RP to CC1 line 1:RP connected to CC1 line Z:RP not connected to CC1 line CC1_TX O Configuration channel TX for CC1 line CC1_TX_EN O Enable signal for CC1_TX 0:CC1_TX connected to CC1 line Z:CC1_TX not connected to CC1 line CC1_DET I Cable detection on CC1 line CC1_RX I Configuration channel RX for CC1 line CC1_RD O Enable signal to Connect RD to CC1 line 0:RD connected to CC1 line Z:RD not connected to CC1 line CC1_VCONN_EN O VCONN Enable 1:VCONN enabled on CC1 line 0:VCONN disabled on CC1 line CC1_VCONN_EN_n O VCONN Enable 1:VCONN disabled on CC1 line 0:VCONN enabled on CC1 line CC2_RP O Enable signal to Connect RP to CC2 line 1:RP connected to CC2 line Z:RP not connected to CC2 line CC2_TX O Configuration channel TX for CC2 line CC2_TX_EN O Enable signal for CC2_TX 0:CC2_TX connected to CC2 line Z:CC2_TX not connected to CC2 line CC2_DET I Cable detection on CC2 line CC2_RX I Configuration channel RX for CC2 line CC2_RD O Enable signal to Connect RD to CC2 line 0:RD connected to CC2 line Z:RD not connected to CC2 line CC2_VCONN_EN O VCONN Enable 1:VCONN enabled on CC2 line 0:VCONN disabled on CC2 line CC2_VCONN_EN_n O VCONN Enable 1:VCONN disabled on CC2 line 0:VCONN enabled on CC2 line CC_RX_REF I Reference Signal for CC1_RX and CC2_RX CC1_DET_REF I Reference Signal for CC1_DET CC1_DET_PWM O PWM signal to generate CC1_DET_REF CC2_DET_REF I Reference Signal for CC2_DET 4-2 Pinout Information Lattice USB Type-C Solution Data Sheet CC2_DET_PWM O PWM signal to generate CC2_DET_REF DB_DISABLE O Disable signal to disable Dead battery MOSFET's 1:Dead Battery MOSFE's disabled 0:Dead Battery MOSFE's enabled VBUS_SOURCE_EN O Enable Signal for VBUS Source VBUS_SINK_EN O Enable Signal for VBUS Sink VBUS_DSICHARGE_EN O Enable Signal for VBUS Discharge 1:VBUS Discharge enabled 0:VBUS Discharge disabled VBUS_DET I VBUS detect and monitor signal VBUS_REF I Reference signal for VBUS_DET VBUS_DET_PWM PWM signal to generate VBUS_REF SS_SEL1, SS_SEL2, SS_SEL3 O SS/HS Switch Control Signal CLK_IN I 4.8 MHz Clock or Even Multiples of 4.8 MHz such as 9.6 MHz or 19.2 MHz etc. LIF-UC110 and LIF-UC120 devices have an internal oscillator. It can also be used if the customer prefers not to use external clock source. SPI_MISO I/O This pin is shared with device configuration and EC.After configuration. This pin is used SPI_MISO for EC. SPI_MOSI I/O This pin is shared with device configuration and EC.After configuration. This pin is used SPI_MOSI for EC. SPI_SCK I/O This pin is shared with device configuration and EC.After configuration. This pin is used SPI_SCK for EC. SPI_SS_B I EC_INT O Interrupt signal from FPGA to EC EC_CS I Chip select signal from EC to FPGA CDONE I/O CRESETB VSEL1,VSEL2,VSEL3,VSEL4 I Chip select signal for Device configuration Configuration Done. Includes a weak pull-up resistor to VCCIO_1 Configuration Reset, active LOW. No internal pull-up resistor. Either actively driven externally or connect an 10K-ohm pull-up to VCCIO_1 I/O Voltage selection line 1 for selecting output voltage VBUS_PG O VBUS power good signal HPD I/O Hot Plug detect. CC1_RX_REF I CC1 RX From external comparator CC2_RX_REF I CC2 RX From external comparator VBUS_IN I VBUS sense Input from the Connector CC1_DET I CC1 input from the for cable detection CC2_DET I CC2 input from the for cable detection 4-3 Lattice USB Type-C Solution Data Sheet Ordering Information August 2015 Preliminary Data Sheet DS1052 Ordering Part Numbers Supply Voltage Package Pins Temp. LIF-UC110-SG48I Part Number CD/PD for Charger Functional Description 1.2 V QFN 48 IND LIF-UC120-SWG36I CD/PD Phy for Hosts/Devices 1.2 V WLCSP 36 IND LIF-UC140-CM81I CD/PD for Docks 1.2 V CBGA 81 IND © 2015 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. www.latticesemi.com 5-1 DS1052 Order Info_01.2 Lattice USB Type-C Solution Data Sheet Revision History August 2015 Preliminary Data Sheet DS1052 Date Version Section Change Summary August 2015 1.3 Introduction Updated the Features section. — Removed 81 caBGA under Wide Range of Packages to Match PCB Technology feature. — Updated Table 1-1, USB Type-C Device Table. Revised heading to Package, Ball Pitch, Dimension and updated data. Removed the 81 BGA, 0.8 mm, 8 mm x 8 mm package. Architecture Updated the Architecture Overview section. Revised Figure 2-1, Highlevel Functional Block for USB Type-C Physical Layer and Power Detect Protocol. Updated the USB CD/PD Charger Solution (Captive Cable) section. Revised Figure 2-2, USB CD/PD Charger Solution (Captive Cable) Block Diagram. Updated the USB CD/PD Charger Solution (Non-Captive Cable). Revised Figure 2-4, USB CD/PD Charger Solution (Non-Captive Cable) Block Diagram Updated the CD/PD PHY for Host/Devices. Revised Figure 2-6, CD/ PD PHY for Host/Devices Block Diagram. Updated the CD/PD for Hosts/Devices. Revised Figure 2-8, CD/PD for Host/Devices Block Diagram. June 2015 1.2 Ordering Information Updated Ordering Part Numbers section. Removed LIF-UC140-BG81I part number. Architecture Updated the USB CD/PD Charger Solution (Non-Captive Cable) section. — Modified Figure 2-5, USB CD/PD Charger Solution (Non-Captive Cable) Schematic Diagram. Added VCONN switch for SOP support. — Updated Table 2-3, CD/PD for Hosts/Devices BOM. USB CD/PD Charger Solution (Non-Captive Cable) BOM. Revised Item 12. Added Item 20. — Updated Table 2-4, USB CD/PD Charger Solution (Non-Captive Cable) BOM Count. Revised Item 3. Added Item 5. Updated the CD/PD PHY for Host/Devices section. Added note in supported features in schematics. Updated the CD/PD for Hosts/Devices section. — Added note in supported features in schematics. — Modified Figure 2-9, CD/PD for Hosts/Devices Schematic Diagram. Changed R38 and R39 resistor values to 5.1 kOhm. — Updated Table 2-7, CD/PD for Hosts/Devices BOM. Revised Items 15 and 18. March 2015 1.1 Architecture Updated the USB CD/PD Charger Solution (Captive Cable) section. Modified Figure 2-3, USB CD/PD Charger Solution (Captive Cable) Schematic Diagram. — Updated BMX TX resistor values. — Added RC Circuit provision for BMC reference voltage. — Added pull-up resistors for CDONE. Updated Table 2-1, USB CD/PD Mobile System Solution (Captive Cable) BOM and Table 2-2, USB CD/PD Mobile System Solution (Captive Cable) BOM Count. © 2015 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. www.latticesemi.com 6-1 DS1052 Revision History Revision History Lattice USB Type-C Solution Data Sheet Date Version Section Change Summary Updated the USB CD/PD Charger Solution (Non-Captive Cable) section. Modified Figure 2-5, USB CD/PD Charger Solution (Non-Captive Cable) Schematic Diagram. — Updated BMX TX resistor values. — Added RC Circuit provision for BMC reference voltage. — Added pull-up resistors for CDONE. Updated Table 2-3, USB CD/PD Charger Solution (Non-Captive Cable) BOM and Table 2-4, USB CD/PD Charger Solution (Non-Captive Cable) BOM Count. Updated the CD/PD PHY for Host/Devices section. Modified Figure 2-6, CD/PD Phy for Host/Devices Block Diagram. Removed items in Features Supported in Schematics. Modified Figure 2-7, CD/PD Phy for Hosts/Devices Schematic Diagram. — Updated BMX TX resistor values. Updated Table 2-5, CD/PD Phy for Hosts/Devices BOM and Table 2-6, CD/PD Phy for Hosts/Devices BOM Count. Updated the CD/PD for Hosts/Devices section. Modified Figure 2-9, CD/PD for Hosts/Devices Schematic Diagram. — Updated BMX TX resistor values. — Added dead battery circuit. — Moved DB-Disable signal to CDONE pin. — Changed Rx Comparator Power supply voltage to 3.3 V. Added Table 2-7, CD/PD for Hosts/Devices BOM and Table 2-8, CD/PD for Hosts/Devices BOM Count. Pinout Information February 2015 1.0 All Updated Signal Descriptions section. Initial release. 6-2