MAX153 General Description The MAX153 high-speed, microprocessor (µP)-compatible, 8-bit analog-to-digital converter (ADC) uses a half-flash technique to achieve a 660ns conversion time, and digitizes at a rate of 1M samples per second (Msps). It operates with single +5V or dual ±5V supplies and accepts either unipolar or bipolar inputs. A POWERDN (power-down) pin reduces current consumption to a typical value of 1µA (with 5V supply). The part returns from power-down to normal operating mode in less than 200ns, providing large reductions in supply current in applications with burstmode input signals. The MAX153 is DC and dynamically tested. Its µP interface appears as a memory location or input/output port that requires no external interface logic. The data outputs use latched, three-state buffered circuitry for direct connection to a µP data bus or system input port. The ADC’s input/ reference arrangement enables ratiometric operation. Applications ● ● ● ● ● ● ● Cellular Telephones Portable Radios Battery-Powered Systems Burst-Mode Data Acquisition Digital-Signal Processing Telecommunications High-Speed Servo Loops 1Msps, µP-Compatible, 8-Bit ADC with 1µA Power-Down Features ● 660ns Conversion Time ● Power-Up/Power-Down in 200ns ● Internal Track/Hold ● 1Msps Throughput ● Low Power 40mW (Operating Mode) 5µW (Power-Down Mode) ● 1MHz Full-Power Bandwidth ● 20-Pin Narrow DIP, SO, and SSOP Packages ● No External Clock Required ● Unipolar/Bipolar Inputs ● Single +5V or Dual ±5V Supplies ● Ratiometric Reference Inputs Functional Diagram VDD 20 VREF+ 12 18 4-BIT FLASH ADC VREF- 11 VIN 1 THREESTATE DRIVERS 4-BIT DAC VREF+ Ordering Information appears at end of data sheet. 16 For related parts and recommended products to use with this part, refer to www.maximintegrated.com/MAX153.related. 4-BIT FLASH ADC (4 LSB) MAX153 TIMING AND CONTROL CIRCUITRY 10 7 6 3 GND MODE WR/RDY CS 19-4740; Rev 2; 1/12 7 RD 7 19 INT VSS PWRDN D0–D7 DATA OUT PINS 2–5, 14–17 MAX153 1Msps, µP-Compatible, 8-Bit ADC with 1µA Power-Down Absolute Maximum Ratings (All voltages referenced to GND.) VDD...........................................................................-0.3V to +7V VSS...........................................................................+0.3V to -7V Digital Input Voltage................................ +0.3V to (VDD + 0.3V) Digital Output Voltage.............................. -0.3V to (VDD + 0.3V) VREF+, VREF+, VIN......................... (VSS - 0.3V) to (VDD + 0.3V) Continuous Power Dissipation (TA = +70°C) PDIP (derate 11.11mW/°C above + 70°C)...................889mW SO(W) (derate 10.00mW/°C above +70°C..................800mW SSOP (derate 8.00mW/°C above +70°C)....................640mW Operating Temperature Ranges MAX153C....................................................................0 to +70°C MAX153E............................................................ -40°C to +85°C Storage Temperature Range............................. -65°C to +150°C Lead Temperature (soldering, 10s).................................. +300°C Soldering Temperature (reflow)........................................+260°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Electrical Characteristics (VDD = +5V ±5%, VGND = 0V; Unipolar Input Range: VSS = GND, VREF+ = 5V, VREF- = GND; Bipolar Input Range: VSS = -5V ±5%, VREF+ = 2.5V, VREF- = -2.5V; 100% production tested, specifications are given for RD Mode (MODE = GND), TA = TMIN to TMAX, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS ACCURACY Resolution N 8 Bits Total Unadjusted Error TUE Unipolar range ±1 LSB Differential Nonlinearity DNL No missing codes guaranteed ±1 LSB Zero-Code Error Bipolar input range ±1 LSB Full-Scale Error Bipolar input range ±1 LSB DYNAMIC SPECIFICATIONS (Note 1) Signal-to-Noise Plus Distortion Noise Total Harmonic Distortion SINAD fSAMPLE = 1MHz, fIN = 195.8kHz THD fSAMPLE = 1MHz, fIN = 195.8kHz -50 dB fSAMPLE = 1MHz, fIN = 195.8kHz -50 dB TA = +25°C, tRD < tINTL, CL = 20pF 660 ns TA = +25°C 700 TA = TMIN to TMAX 875 Peak Harmonic or Spurious Noise Conversion Time (WR-RD Mode) (Note 2) tCWR Conversion Time (RD Mode) tCRD Full-Power Bandwidth 45 VIN = 5VP-P Input Slew Rate 3.14 dB ns 1 MHz 15 V/µs ANALOG INPUT Input Voltage Range VIN Input Leakage Current IIN Input Capacitance CIN VREF-5V ≤ VIN ≤ +5V VREF+ V ±3 µA 22 pF REFERENCE INPUT Reference Resistance RREF 1 2 4 kΩ VREF+ Input Voltage Range VREF- VDD V VREF- Input Voltage Range VSS VREF+ V www.maximintegrated.com Maxim Integrated │ 2 MAX153 1Msps, µP-Compatible, 8-Bit ADC with 1µA Power-Down Electrical Characteristics (continued) (VDD = +5V ±5%, VGND = 0V; Unipolar Input Range: VSS = GND, VREF+ = 5V, VREF- = GND; Bipolar Input Range: VSS = -5V ±5%, VREF+ = 2.5V, VREF- = -2.5V; 100% production tested, specifications are given for RD Mode (MODE = GND), TA = TMIN to TMAX, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS LOGIC INPUTS Input High Voltage VINH Input Low Voltage VINL Input High Current IINH CS, WR, RD, PWRDN 2.4 MODE 3.5 V CS, WR, RD, PWRDN 0.8 MODE 1.5 CS, RD, PWRDN 1 WR 3 MODE 50 Input Low Current IINL CS, WR, RD, PWRDN Input Capacitance (Note 3) CIN CS, WR, RD, PWRDN, MODE 5 V µA 200 ±1 µA 8 pF LOGIC OUTPUTS Output Low Voltage VOL ISINK = 1.6mA, INT, D0–D7 0.4 RDY, ISINK = 2.6mA 0.4 4 V Output High Voltage VOH ISOURCE = 360µA, INT, D0–D7 Floating State Current ILKG D0–D7, RDY V Floating Capacitance (Note 3) COUT D7–D0, RDY 5 ±5% for specified accuracy 5 V GND V -5 V ±3 µA 8 pF POWER REQUIREMENTS Positive Supply Voltage VDD Negative Supply Voltage (Unipolar Operation) VSS Negative Supply Voltage (Bipolar Operation) VSS ±5% for specified accuracy VDD Supply Current IDD VCS = VRD = 0V, VPWRDN = 5V MAX153C 8 15 MAX153E 8 20 VCS = VRD = 5V, VPWRDN = 0V (Note 4) 1 100 µA VCS = VRD = 0V, VPWRDN = 5V 25 100 µA Power-Down VSS Current VCS = VRD = 5V, VPWRDN = 0V 12 100 µA Power-Supply Rejection VDD = 4.75V to 5.25V, VREF+ = 4.75V (max), unipolar mode ±1/16 ±1/4 LSB Power-Down VDD Current VSS Supply Current Note Note Note Note ISS PSR mA 1: Bipolar input range, VIN = ±2.5VP-P. WR-RD mode. 2: See Figure 1 for load circuit. Parameter defined as the time required for the output to cross +0.8V or +2.4V. 3: Guaranteed by design. 4: Tested with CS, RD, PWRDN at CMOS logic levels. Power-down current increases to several hundred) µA at TTL levels. www.maximintegrated.com Maxim Integrated │ 3 MAX153 1Msps, µP-Compatible, 8-Bit ADC with 1µA Power-Down TIMING CHARACTERISTICS (Note 5) (VDD = +5V ±5%, VSS = 0V for Unipolar Input Range, VSS = -5V ±5% for Bipolar Input Range, 100% production tested, TA = +25°C, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS CS TO RD/WR Setup Time tCSS 0 ns CS to RD/WR Hold Time tCSH 0 ns CS to RDY Delay (Note 6) tRDY Data-Access Time (RD Mode) (Note 2) RD to INT Delay (RD Mode) Data-Hold Time (Note 7) Delay Time Between Conversions (Acquisition Time) tACC0 tINTH tDH tP Write Pulse Width tWR Delay Time Between WR and RD Pulses tRD RD Pulse Width (WR-RD Mode) Determined by tACC1 Data-Access Time (WR-RD Mode (Note 2) tRD < tINL tREAD1 tACC1 RD to INT Delay tRI WR to INT Delay tINTL RD Pulse Width (WR-RD Mode) Determinted by tACC2 tRD > tINTL Data-Access Time (WR-RD Mode) (Note 2) tRD > tINTL www.maximintegrated.com tREAD2 tACC2 CL = 50pF 70 TA = TMIN to TMAX, CL = 50pF 85 CL = 20pF tCRD + 25 TA = TMIN to TMAX, CL = 20pF tCRD + 30 CL = 100pF tCRD + 50 TA = TMIN to TMAX, CL = 100pF tCRD + 65 CL = 50pF 50 TA = TMIN to TMAX, CL = 50pF 80 85 60 TA = TMIN to TMAX 70 160 TA = TMIN to TMAX TA = TMIN to TMAX 0.250 10 0.280 10 250 350 Figure 6 160 TA = TMIN to TMAX, Figure 6 205 160 205 CL = 100pF, Figure 6 185 TA = TMIN to TMAX, CL = 100pF, Figure 6 235 150 TA = TMIN to TMAX 185 380 500 610 Figure 5 65 TA = TMIN to TMAX, Figure 5 75 ns µs ns TA = TMIN to TMAX, CL = 20pF, Figure 6 TA = TMIN to TMAX, CL = 50pF ns ns CL = 20pF, Figure 6 CL = 50pF ns ns 185 TA = TMIN to TMAX ns ns ns ns ns CL = 20pF, Figure 5 65 TA = TMIN to TMAX, CL = 20pF, Figure 5 75 CL = 100pF, Figure 5 90 TA = TMIN to TMAX, CL = 100pF, Figure 5 110 ns Maxim Integrated │ 4 MAX153 1Msps, µP-Compatible, 8-Bit ADC with 1µA Power-Down TIMING CHARACTERISTICS (Note 5) (continued) (VDD = +5V ±5%, VSS = 0V for Unipolar Input Range, VSS = -5V ±5% for Bipolar Input Range, 100% production tested, TA = +25°C, unless otherwise noted.) PARAMETER SYMBOL WR to INT Delay (Pipelined Mode) CONDITIONS tIHWR Data-Access Time After INT (Note 2) tID MIN TYP MAX CL = 50pF 80 TA = TMIN to TMAX, CL = 50pF 100 CL = 20pF 30 TA = TMIN to TMAX, CL = 20pF 35 CL = 100pF 45 TA = TMIN to TMAX, CL = 100pF 60 UNITS ns ns Note 5: Input control signals are specified with tr = tt = 5ns, 10% to 90% of +5V and timed from a 1.6V voltage level. Note 6: RL = 5.1kΩ pullup resistor. Note 7: See Figure 2 for load circuit. Parameter defined as the time required for data lines to change 0.5V. +5V +5V 3kΩ 3kΩ DN DN DN 3kΩ CL CL DGND A. HIGH-Z TO VOH DGND B. HIGH-Z TO VOL Figure 1. Load Circuits for Data-Access Time Test www.maximintegrated.com DN 3kΩ 10pF 10pF DGND A. VOH TO HIGH-Z DGND B. VOL TO HIGH-Z Figure 2. Load Circuits for Data-Hold Time Test Maxim Integrated │ 5 MAX153 1Msps, µP-Compatible, 8-Bit ADC with 1µA Power-Down 1.5 1.4 1.3 8.0 7.5 HOT +125°C EFFECTIVE BITS 7.0 1.2 VDD = +4.75V 1.1 1.0 VDD = +5.25V 0.9 VDD = +5V 0.7 -60 -40 -20 0 COLD -55°C ROOM 6.5 6.0 5.5 5.0 0.8 0.6 EFFECTIVE BITS vs. INPUT FREQUENCY, WR-RD MODE ISAMPLE = 1MHz VIN = ±2.5V 4.5 4.0 20 40 60 80 100 120 140 10 TEMPERATURE (°C) INPUT FREQUENCY = 195.8ksps (±2.5V) SAMPLE FREQUENCY = 1MHz SNR = 49.1dB -40 -60 -80 -80 -100 -100 100 200 300 FREQUENCY (kHz) www.maximintegrated.com 400 TA = +25°C -20 -60 0 MAX153 toc04 0 RATIO (dB) RATIO (dB) -40 1k INTERMODULATION DISTORTION MAX153 toc03 TA = +25°C -20 100 FREQUENCY (kHz) SIGNAL-TO-NOISE RATIO 0 MAX153 toc02 CONVERSION TIME vs. AMBIENT TEMPERATURE MAX153 toc01 tCRD (NORMALIZED TO VALUE AT +25°C) Typical Operating Characteristics 500 0 50 INPUT FREQUENCY = 94.97kHz = 84.72kHz (±2.5V) SAMPLE FREQUENCY = 500kHz IMD: 2ND-ORDER TERMS = -66.2dB 3RD-OREDER TERMS = -60.0dB 100 150 200 250 FREQUENCY (kHz) Maxim Integrated │ 6 MAX153 1Msps, µP-Compatible, 8-Bit ADC with 1µA Power-Down Pin Configuration TOP VIEW + VIN 1 20 VDD D0 (LSB) 2 19 VSS D1 3 18 PWRDN D2 4 D3 5 WR/RDY 6 15 D5 MODE 7 14 D4 RD 8 13 CS INT 9 12 VREF+ GND 10 11 VREF- MAX153 17 D7 (MSB) 16 D6 PDIP/SO(W)/SSOP Pin Description PIN NAME 1 VIN Analog Input. Range is VREF- > VIN < VREF+. FUNCTION Three-State Data Output (LSB) 2 D0 3–5 D1–D3 6 WR/RDY 7 MODE 8 RD READ Input. Must be low to access data*. 9 INT INTERRUPT Output goes low to indicate end of conversion*. Three-State Data Outputs WRITE Control Input/READY Status Output* MODE Selection Input. Internally pulled low with a 50µA current source. MODE = 0 activates read mode. MODE = 1 actives write-read mode* 10 GND Ground 11 VREF- Lower Limit of Reference Span. Sets the zero-code voltage. Range is VSS < VREF- < VREF+. 12 VREF+ Upper Limit to Reference Span. Sets the full-scale input voltage. Range is VREF- < VREF+ < VDD. 13 CS 14–16 D4–D6 17 D7 18 PWRDN CHIP SELECT Input. Must be low for the device to recognize WR or RD inputs. Three-State Data Outputs Three-State Data Output (MSB) POWERDOWN Input. Reduces supply current when low. CS must be high during power-down. 19 VSS Negative Supply. Unipolar: VSS = 0V, Bipolar: VSS = -5V. 20 VDD Positive Supply, +5V *See the Digital Interface section. www.maximintegrated.com Maxim Integrated │ 7 MAX153 Detailed Description Converter Operation The MAX153 uses a half-flash conversion technique (see the Functional Diagram) in which two 4-bit flash ADC sections achieve an 8-bit result. Using 15 comparators, the flash ADC compares the unknown input voltage to the reference ladder and provides the upper 4 data bits. An internal digital-to-analog converter (DAC) uses the 4 most significant bits (MSBs) to generate the analog result from the first flash conversion and a residue voltage that is the difference between the unknown input and the DAC voltage. The residue is then compared again with the flash comparators to obtain the lower 4 data bits (LSBs). Power-Down Mode In burst-mode or low sample-rate applications, the MAX153 can be shut down between conversions, reducing supply current to microamp levels. A TTL/CMOS logic-low on the PWRDN pin shuts the device down, reducing supply current to typically 1µA when powered from a single 5V supply. CS must be high when power-down is used. A logic-high on PWRDN wakes up the MAX153. A new conversion can be started (WR asserted low) within 360ns of the PWRDN pin being driven high 200ns to power up plus 160ns for track/hold acquisition). If powerdown mode is not required, connect PWRDN to VDD. Once the MAX153 is in power-down mode, lowest supply current is drawn with MODE low (RD mode) due to an internal 50µA pulldown resistor at this pin. CS must remain high during shutdown because the MAX153 may attempt to start a conversion that it cannot complete. In addition, for minimum current consumption, other digital inputs should remain stable in power-down. RDY, an open-drain output (in RD mode), will then fall and remain low throughout. Power-down, sinking additional supply current unless CS remains high. See the Reference section for information on reducing reference current during power-down. Digital Interface The MAX153 has two basic interface modes set by the status of the MODE input pin. When MODE is low, the converter is in the RD mode; when MODE is high, the converter is set up for the WR-RD mode. www.maximintegrated.com 1Msps, µP-Compatible, 8-Bit ADC with 1µA Power-Down Read Mode (MODE = 0) In RD mode, conversion control and data access are controlled by the RD input (Figure 3). The comparator inputs track the analog input voltage for the duration of tP. A minimum of 160ns is required for the input to be acquired. A conversion is initiated by driving RD low. With µPs that can be forced into a wait state, hold RD low until output data appears. The µP starts the conversion, waits, and then reads data with a single read instruction. WR/RDY is configured as a status output (RDY) in RD mode, where it can drive the ready or wait input of a µP. RDY is an open-collector output (with no internal pullup) that goes low after the falling edge of CS and goes high at the end of the conversion. If not used, the WR/RDY pin can be left unconnected. The INT output goes low at the end of the conversion and returns high on the rising edge of CS or RD. Write-Read Mode (MODE = 1) Figures 4 and 5 show the operating sequence for the write-read (WR-RD) mode. The comparator inputs track the analog input voltage for the duration of tP. A minimum of 160ns is required for the input voltage to be acquired. The conversion is initiated by a falling edge of WR. When WR returns high, the 4 MSBs flash result is latched into the output buffers and the 4 LSBs conversion begins. INT goes low about 380ns later, indicating conversion end, and the lower 4 data bits are latched into the output buffers. The data is then accessible 65ns to 130ns after RD goes low (see the Timing Characteristics). If an externally controlled conversion time is required, drive RD low 250ns after WR goes high. This latches the lower 4 data bits and outputs the conversion result on D0–07. A minimum 160ns delay is required from INT going low to the start of another conversion (WR going low). Options for reading data from the converter include the following: Using Internal Delay The µP waits for the INT output to go low before reading the data (Figure 4). INT typically goes low 380ns after the rising edge of WR, indicating the conversion is complete, and the result is available in the output latch. With CS low, data outputs D0–D7 can be accessed by pulling RD low. INT is then reset by the rising edge of CS or RD. Maxim Integrated │ 8 MAX153 1Msps, µP-Compatible, 8-Bit ADC with 1µA Power-Down CS CS RD tWR tCSH WR tCSS tRI tINTH INT tCRD D0–D7 VALID DATA tACC0 tP tREAD1 RD WITH EXTERNAL PULLUP tRDY tRD tCSS tP RDY INT tCSH tINTH DATA VALID D0–D7 tACC1 tCWR tDH Figure 3. RD Mode Timing (MODE = 0) tDH Figure 5. WR-RD Mode Timing (tRD > tINTL), Fastest Operating Mode (MODE = 1) CS tWR WR tCSS RD INT tWR tP tCSH RD, WR tREAD2 tRD tIHWR tINTH tINTL INT D0–D7 D0–D7 tINTL OLD DATA tP tID NEW DATA VALID DATA tACC2 tDH Figure 4. WR-RD Mode Timing (tRD > tINTL) (MODE = 1) Figure 6. Pipelined Mode Timing (WR = RD) (MODE = 1) Pipelined Operation Fastest Conversion: Reading Before Delay An external method of controlling the conversion time is shown in Figure 5. The internally generated delay tINTL varies slightly with temperature and supply voltage, and can be overridden with RD to achieve the fastest conversion time. INT is ignored, and RD is brought low typically 250ns after the rising edge of WR. This completes the conversion and enables the output buffers (D0–D7) that contain the conversion result. INT also goes low after the falling edge of RD and is reset on the rising edge of RD or CS. The total conversion time is therefore: tCWR = tWR (250ns) + tCSH (0ns) to tRD (250ns) + tACC1 (160ns) = 660ns. www.maximintegrated.com Besides the two standard WR-RD mode options, pipelined operation can be achieved by connecting WR and RD together (Figure 6). With CS low, driving WR and RD low initiates a conversion and reads the result of the previous conversion concurrently. Analog Considerations Reference Figures 7a–7c show some reference connections. VREF+ and VREF- inputs set the full-scale and zero-input voltages of the ADC. The voltage at VREF- defines the input that produces an output code of all zeros, and the voltage at VREF+ defines the input that produces an output code of all ones. Maxim Integrated │ 9 MAX153 1Msps, µP-Compatible, 8-Bit ADC with 1µA Power-Down The internal resistances from VREF+ and VREF- may be as low as 1kΩ. Since current is still drawn by the reference inputs during power-down, reference supply current can be reduced during shutdown by using the circuit shown in Figure 7d. A logic-level n-channel MOSFET, connected between VREF- and ground, disconnects the reference load when the ADC enters power-down. (PWRDN = low). The FET should have no more than 0.5Ω of on-resistance to maintain accuracy. Bypassing A 4.7µF electrolytic in parallel with a 0.1µF ceramic capacitor should be used to bypass VDD to GND. These capacitors should have minimal lead length. Input Current Figure 8 shows the equivalent circuit of the converter input. When the conversion starts and WR is low, VIN is connected to 16 0.6pF capacitors. During this acquisition phase, the input capacitors charge to the input voltage through the resistance of the internal analog switches (about 2kΩ). In addition, about 12pF of stray capacitance must be charged. The input can be modeled as an equivalent RC network (Figure 9). As source impedance increases, the capacitors take longer to charge. The typical 22pF input capacitance allows source resistance as high as 2.2kΩ without setup problems. For larger resistances, the acquisition time (tP) must be increased The reference inputs should be bypassed with 0.1µF capacitors, as shown in Figures 7a–7c. VIN+ VIN+ VIN- 1 10 20 +5V 0.1µF 4.7µF 12 11 VIN GND MAX153 VDD 10 20 +5V 0.1µF 1 4.7µF VREF+ 12 VIN- +2.5V 11 * 0.1µF VREF- 0.1µF VIN GND MAX153 VDD VREF+ VREF- *CURRENT PATH MUST STILL EXIST FROM VIN- TO GND Figure 7a. Power Supply as Reference VIN+ VIN- 1 10 20 +5V 0.1µF Figure 7c. Input Not Referenced to GND 4.7µF MAX584 +2.5V 0.1µF 12 11 Figure 7b. External Reference, +2.5V Full Scale www.maximintegrated.com 20 VIN+ 0.1µF VIN GND MAX584 MAX153 0.1µF VDD VREF+ VREF- 12 11 18 PWRDN N-FET VDD MAX153 VREF+ VREFPWRDN 0.1µF Figure 7d. An n-Channel MOSFET Switches Off the Reference Load During Power-Down Maxim Integrated │ 10 MAX153 1Msps, µP-Compatible, 8-Bit ADC with 1µA Power-Down MAX153 MAX153 VIN RIN RON 1 VIN VIN R 1 VIN 2kΩ 12pF C 10pF Figure 8. Equivalent Input Circuit Figure 9. RC Network Equivalent Input Model Conversion Rate The effective resolution, or effective number of bits, the ADC provides can be measured by transposing the equation that converts resolution to SNR: N = (SNR 1.76)/6.02. The maximum sampling rate (fMAX) for the MAX153 is achieved in the WR-RD mode (tRD < tINTL) and is calculated as follows: f MAX = f MAX = 1 t WR + t RD + t RI + t P 1 250ns + 250ns + 150ns + 165ns f MAX = 1.23MHz where tWR = Write pulse width tRD = Delay between WR and RD pulses tRI = RD to INT delay tP = Delay time between conversions Signal-to-Noise Ratio and Effective Number of Bits Signal-to-noise ratio (SNR) is the ratio of the RMS amplitude of the fundamental input frequency to the RMS amplitude of all other analog-to-digital output values. The output band is limited to one-half the A/D sample (conversion) rate. This ratio usually includes distortion as well as noise components. For this reason, the ratio is sometimes referred to as signal-to-noise plus distortion. The theoretical minimum A/D noise is caused by quantization error and results directly from the ADC’s resolution: SNR = (6.02N + 1.76)dB, where N is the number of bits of resolution. Therefore, a perfect 8-bit ADC can do no better than 50dB. The FFT plot (Typical Operating Characteristics) shows the result of sampling a pure 200kHz sinusoid at a 1MHz rate. This FFT plot of the output shows the output level in various spectral bands. www.maximintegrated.com Total Harmonic Distortion Total harmonic distortion (THD) is the ratio of the RMS sum of all harmonics of the input signal (in the frequency band above DC and below one-half the sample rate) to the fundamental itself. This is expressed as: (V 2 2 + V3 2 +V 4 2 + ... +VN 2 ) THD = 20 log V1 where V1 is the fundamental RMS amplitude, and V2 to VN are the amplitudes of the 2nd through Nth harmonics. Peak Harmonic or Spurious Noise Peak harmonic or spurious noise is the ratio of the fundamental RMS amplitude to the amplitude of the next largest spectral component (in the frequency band above DC and below one-half the sample rate). Usually this peak occurs at some harmonic of the input frequency, but if the ADC is exceptionally linear, it may occur only at a random peak in the ADC’s noise floor. Intermodulation Distortion An FFT plot of intermodulation distortion (IMD) is generated by sampling an analog input applied to the ADC. This input consists of very low distortion sine waves at two frequencies. A 2048 point plot for IMD of the MAX153 is shown in the Typical Operating Characteristics. Maxim Integrated │ 11 MAX153 1Msps, µP-Compatible, 8-Bit ADC with 1µA Power-Down Ordering Information PART TEMP RANGE Package Information PIN-PACKAGE MAX153CAP+ 0°C to +70°C 20 SSOP** MAX153CPP+ 0°C to +70°C 20 PDIP MAX153CWP+ 0°C to +70°C 20 SO(W) MAX153C/D 0°C to +70°C Dice* MAX153EAP+ -40°C to +85°C MAX153EPP+ -40°C to +85°C MAX153EWP+ -40°C to +85°C 20 SSOP** 20 PDIP 20 Wide SO +Denotes a lead(Pb)-free/RoHS-compliant package. For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE PACKAGE CODE OUTLINE NO. LAND PATTERN NO. 20 PDIP P20+3 21-0043 — 20 SO(W) W20+2 21-0042 90-0108 20 SSOP A20+1 21-0056 90-0094 *Contact factory for dice specifications. **Contact factory for availability of SSOP packages Chip Information PROCESS: BiCMOS www.maximintegrated.com Maxim Integrated │ 12 MAX153 1Msps, µP-Compatible, 8-Bit ADC with 1µA Power-Down Revision History REVISION NUMBER REVISION DATE 0 7/92 Initial release — 1 10/93 Corrected die topography 11 2 1/12 Removed military packages DESCRIPTION PAGES CHANGED 1–5 For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com. Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance. Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc. © 2012 Maxim Integrated Products, Inc. │ 13