HFRD-29.11

Reference Design:
HFRD-29.11
Rev 0; 6/09
REFERENCE DESIGN
Dual-Rate (1.25Gbps/10.3125Gbps) VCSEL
Small Form-Factor Pluggable (SFP+) Transceiver
Functional Diagrams
Pin Configurations appear at end of data sheet.
Functional Diagrams continued at end of data sheet.
UCSP is a trademark of Maxim Integrated Products, Inc.
LE
AVAILAB
Dual-Rate (1.25Gbps/10.3125Gbps) VCSEL SFP+ Transceiver
Table of Contents
1 Overview
2 Obtaining Additional Information
3 Reference-Design Details
4 Transmitter Performance Data
5 Receiver Performance Data
6 Applications Information
7 Getting Started
8 SFP+ Evaluation Software
9 Signal Definitions
10 Component List
11 Schematic
12 Board Layout
13 Layer Profile
2
2
3
5
9
14
15
16
22
23
24
25
27
The HFRD-29.11 transceiver reduces design time
for SFP+ and other optical transmitters by
providing the schematics, PC-board layout,
Gerber files, and bill of materials. The module is
provided with some basic firmware and a
graphical user interface (GUI) to demonstrate the
operation of the MAX3799. Test data and typical
performance from an assembled board also aid in
evaluating this reference design.
1.1
Features
•
•
•
1 Overview
High-Frequency Reference Design (HFRD-29.11)
is a complete optical transceiver targeted for the
small form-factor pluggable (SFP+) Multisource
Agreement (MSA) market and other high-speed
optical-transceiver applications.
This
design
showcases
the
MAX3799
combination differential VCSEL driver and
limiting amplifier. The MAX3799 limiting
amplifier is optimized to provide standardscompliant sensitivity at data rates of either
1.25Gbps or 10.3125Gbps. The reference design
is available with a variety of VCSEL (TOSAs)
and receivers (ROSAs). Control of the MAX3799
is provided by an ATMEGA88 microprocessor.
The microprocessor interfaces to the MAX3799
with a 3-wire digital interface, and is used to
regulate optical power, monitor functions, and
control other settings within the MAX3799.
Communication with the SFP+ module is
accomplished through the standard MSA I2C
interface.
The MAX3799 is a cost-effective solution for an
SFP+ dual-rate transceiver. Combining the
VCSEL driver and limiting amplifier into a single,
5mm x 5mm package reduces cost without
compromising performance. Mask margins in
excess of 40% at 10.3125Gbps are achievable.
Reference Design HFRD-29.11 (Rev. 0, 6/09)
•
•
•
•
•
Schematics and Bill of Materials provided
Gerber plot files available
Dual-rate compliant
(1.25Gbps or 10.3125Gbps)
Single +3.3V power supply
SFP+ multisource footprint
Digital diagnostic monitors
850nm wavelength LC VCSEL (TOSA)
and receiver (ROSA) provided
Basic F/W and GUI provided with sample
2 Obtaining Additional
Information
Limited quantities of the HFRD-29.11 SFP+
transmitter board and HFRD-30.1 SFP host board
(see section 6.5) are available. For more
information about this reference design or to
obtain an SFP+ transmitter or host board, please
access
our
customer
support
at:
https://support.maxim-ic.com
Maxim Integrated
Page 2 of 27
3 Reference-Design Details
3.1
Components
3.1.1
MAX3799 Laser Driver/Limiting Amp
The MAX3799 is a combination VCSEL driver
and limiting amplifier with a 3-wire digitalcontrol interface.
The laser driver portion has many registers and
features, including:
1.
2.
3.
4.
5.
6.
7.
8.
Waveform peaking
Pulse-width fine adjustment
Control of bias and modulation
Soft and hard limits on bias and
modulation
Driver back termination
Full differential drive
Up to 12mA modulation
Fault detection capability
The limiting amplifier features:
1.
2.
3.
4.
5.
6.
7.
Adjustable-output CML level
Adjustable-output slew rate
Input-bandwidth select feature
Output pre-emphasis enable
5mV input sensitivity
LOS polarity/squelch
Programmable LOS level
For additional information, see the MAX3799
data sheet, available on the web at: www.maximic.com/MAX3799.
3.1.2
Microcontroller
Basic firmware is provided in the microcontroller
to demonstrate the capability of the MAX3799.
However, it is the designer’s responsibility to
complete a production version of the firmware. A
GUI is also provided.
3.1.3
VCSEL (TOSA)
HFRD-29.11 is available with one of three
VCSEL brands:
JDSU™
PL-FLD-00-S40-C5 www.jdsu.com
EMCORE®: 8585-3760
Finisar®:
HFE 6192-261
www.emcore.com
www.finisar.com
All VCSELs are provided with flex circuit
interconnect and packaged in LC headers.
3.1.4
Receive Optical Subassemblies (ROSA)
HFRD-29.11 can be provided to the customer
with either of these ROSA brands:
Finisar:
HFD 6180-418 or 6180-419
JDSU:
PL-FLR-00-S43-C6
3.2
Functional Block Diagram
The functional block diagram is shown in Figure
1. The 20-pin SFP+ electrical interface is shown
on the left portion of the diagram. The TOSA and
ROSA are located to the right of the MAX3799. A
simple, but effective, RC equalizer is included on
the Tx data input lines to help compensate for the
jitter added by the edge connector. The
TX_DISABLE and TX_FAULT functions are
controlled through the microcontroller.
The microcontroller contains all of the firmware
and input/output connections to control and
monitor the MAX3799 functions. In this reference
design an ATMEGA88 is employed, although
other brands of microcontrollers can be used.
The microcontroller performs the following tasks:
1.
2.
3.
4.
5.
6.
I2C interface to host board
3-wire digital interface to the MAX3799
Monitor and control of VCSEL power
Diagnostic monitoring functions
Control of all MAX3799 registers
Fault monitoring
Reference Design HFRD-29.11 (Rev. 0, 6/09)
Maxim Integrated
Page 3 of 27
VCC_Micro
VCC_TX
VCC_RX
MD
TEMP
SENSOR
ROSA
RSSI
TX_FAULT
TX_FAULT
SDA
Filter
VCC_RX
VCC_RX
BIAS_MONITOR
SCL
ATMEGA88
TX_DISABLE
VCC_TX
TX_DISABLE
CS
IN+
S_DATA
INOUT+
S_CLOCK
*
PAD
TOSA
OUT-
MSel
RS0
MAX3799
BIAS
LOS
MD
VCC_TX
RX_OUT+
RX_OUT+
RX_OUT-
RX_OUT-
TX_IN+ TX_IN-
TX_IN+
EQUALIZER
TX_INBIAS_MAX
VCC_TX
VCCT
VCCR
FILTERS
*
24
430
430
VCC_RX
24
VCC_Micro
Resistive pad may be installed to improve
matching between TOSA and MAX3799.
Figure 1. Functional diagram.
Reference Design HFRD-29.11 (Rev. 0, 6/09)
Maxim Integrated
Page 4 of 27
4 Transmitter Performance Data
4.1
Filtered Transmit Eye Diagrams at 10.3125Gbps, PRBS 231-1 (JDSU VCSEL shown)
2.95V
Mask margin: 46%
Mask margin: 33%
Peaking adjustment: none (0)
Modulation level: manually adjusted
at each temperature to maintain
relatively constant extinction ratio.
3.3V
APC loop: operational, bias
automatically adjusts to maintain
constant power; bias limit set to 9mA.
Pad: 0dB (see Figure 1)
Mask margin: 44%
Mask margin: 46%
3.65V
Mask margin: 46%
0°C
Reference Design HFRD-29.11 (Rev. 0, 6/09)
Mask margin: 33%
+25°C
+50°C
+85°C
Maxim Integrated
Page 5 of 27
4.2
Filtered Transmit Eye Diagrams at 10.3125Gbps vs. Temperature (Finisar and EMCORE VCSELs shown)
Finisar VCSEL
Mask margin: 26%
Mask margin: 44%
0ºC
Peaking adjustment: none (0)
+25ºC
Pad: 4dB
Mask margin: 44%
Mask margin: 39%
+50ºC
+85ºC
Modulation level: manually adjusted to maintain relatively constant extinction ratio
EMCORE VCSEL
Mask margin: 39%
Mask margin: 37%
0ºC
Peaking adjustment: none (0)
+25ºC
Mask margin: 39%
Mask margin: 34%
+50ºC
+85ºC
Pad: 4dB Modulation level: manually adjusted to maintain relatively constant extinction ratio
Reference Design HFRD-29.11 (Rev. 0, 6/09)
Maxim Integrated
Page 6 of 27
4.3
Filtered Transmit Eye Diagrams at 1.25Gbps, PRBS 27-1 (JDSU VCSEL shown)
2.95V
Mask margin: 44%
Mask margin: 4%
Peaking adjustment: none (0)
Modulation level: manually adjusted
at each temperature to maintain
relatively constant extinction ratio.
3.3V
APC loop: operational, bias
automatically adjusts to maintain
constant power; bias limit set to 9mA.
Pad: 4dB (see Figure 1)
Mask margin: 44%
Mask margin: 46%
3.65V
Mask margin: 44%
0°C
Reference Design HFRD-29.11 (Rev. 0, 6/09)
Mask margin: 41%
+25°C
+50°C
+85°C
Maxim Integrated
Page 7 of 27
Additional Transmitter Data at 10.3125Gbps (Finisar VCSEL shown)
Average Power and Extinction Ratio
Bias Current and Monitor Level
150
100
5
4
3
2
Bias current limit set to 9mA
50
Bias Current
1
0
Average Power [dBm]
8
7
6
Monitor Level
-20
0
20
40
60
80
10
-1
Monitor Level
Bias Current [mA]
0
200
10
9
0
100
-2
8
-3
7
-4
6
-5
5
-6
4
-7
3
-8
Average Power
2
-9
Extinction Ratio
1
-10
-20
0
Temperature [ C]
0
20
40
60
80
0
100
0
Temperature [ C]
Transceiver Current Draw
(RX CML OUT = MAX)
Modulation Register Setting
(Pad = 4dB)
250
120
200
100
Register Setting
ICC [mA]
9
Bias current limit set to 9mA
Extinction Ratio [dB]
4.4
150
100
Includes ROSA
50
80
60
40
20
0
0
-20
0
20
40
60
80
Temperature [ºC]
Reference Design HFRD-29.11 (Rev. 0, 6/09)
100
-20
0
20
40
60
80
100
0
Temperature [ C]
Maxim Integrated
Page 8 of 27
5 Receiver Performance Data
5.1
Receiver Output Eye Diagrams at 10.3125Gbps, 231-1 PRBS, -10dBm Input OMA, Nonstressed Source
(Finisar ROSA shown)
2.95V
RS0: high bandwidth (1)
Output D-emphasis: ON
CML Level: 150
Output eyes include jitter from:
•
•
•
•
•
Reference transmitter
15 feet of 50μm fiber
Host-board edge connector
3 feet of coax cables
BERT SCOPE
3.3V
(Finisar ROSA shown)
3.65V
0 °C
Reference Design HFRD-29.11 (Rev. 0, 6/09)
+30 °C
+50 °C
+85°C
Maxim Integrated
Page 9 of 27
5.2
Receiver Output Eye Diagrams at 1.25Gbps, 27-1 PRBS, -15dBm Input OMA, Nonstressed Source
(Finisar ROSA shown)
2.95V
RS0: low bandwidth (0)
Output De-emphasis: OFF
CML level: 150
Output eyes include jitter from:
•
•
•
•
•
Reference transmitter
15 feet of 50μm fiber
Host-board edge connector
3 feet of coax cables
BERT SCOPE
3.3V
(Finisar ROSA shown)
3.65V
0 °C
Reference Design HFRD-29.11 (Rev. 0, 6/09)
+30 °C
+50 °C
+85°C
Maxim Integrated
Page 10 of 27
5.3
Receiver Sensitivity, 10.3125Gbps, 231-1 PRBS (Finisar ROSA shown)
0
0
Non-Stressed Sensitivity 30 C, 10.3125 Gbps
1.0E-03
Non-Stressed Sensitivity 50 C, 10.3125 Gbps
1.0E-03
1.0E-04
1.0E-04
1.0E-05
1.0E-05
1.0E-06
1.0E-06
1.0E-07
1.0E-07
1.0E-08
1.0E-08
1.0E-09
1.0E-09
1.0E-10
1.0E-10
1.0E-11
1.0E-11
1.0E-12
1.0E-12
-20 -19 -18 -17 -16 -15 -14 -13 -12 -11 -10
-20 -19 -18 -17 -16 -15 -14 -13 -12 -11 -10
OMA [dBm]
OMA [dBm]
Non-Stressed Sensitivity 70 C, 10.3125 Gbps
1.0E-03
Non-Stressed Sensitivity 850C, 10.3125 Gbps
1.0E-03
1.0E-04
1.0E-04
1.0E-05
1.0E-05
1.0E-06
1.0E-06
1.0E-07
1.0E-07
1.0E-08
1.0E-08
1.0E-09
1.0E-09
1.0E-10
1.0E-10
1.0E-11
1.0E-11
0
1.0E-12
1.0E-12
-20 -19 -18 -17 -16 -15 -14 -13 -12 -11 -10
-20 -19 -18 -17 -16 -15 -14 -13 -12 -11 -10
OMA [dBm]
OMA [dBm]
Specification (informative): -11.1dBm[1]
[1]
IEEE(S) Std 802.3-2005, page 318, Table 52-9
Reference Design HFRD-29.11 (Rev. 0, 6/09)
Maxim Integrated
Page 11 of 27
5.4
Receiver Sensitivity, 1.25Gbps, 27-1 PRBS (Finisar ROSA shown)
0
Non-Stressed Sensitivity 300C, 1.25 Gbps
1.0E-03
Non-Stressed Sensitivity 50 C, 1.25 Gbps
1.0E-03
1.0E-04
1.0E-04
1.0E-05
1.0E-05
1.0E-06
1.0E-06
1.0E-07
1.0E-07
1.0E-08
1.0E-08
1.0E-09
1.0E-09
1.0E-10
1.0E-10
1.0E-11
1.0E-11
1.0E-12
1.0E-12
-25 -24 -23 -22 -21 -20 -19 -18 -17 -16 -15
-25 -24 -23 -22 -21 -20 -19 -18 -17 -16 -15
OMA [dBm]
OMA [dBm]
0
0
Non-Stressed Sensitivity 70 C, 1.25 Gbps
1.0E-03
Non-Stressed Sensitivity 85 C, 1.25 Gbps
1.0E-03
1.0E-04
1.0E-04
1.0E-05
1.0E-05
1.0E-06
1.0E-06
1.0E-07
1.0E-07
1.0E-08
1.0E-08
1.0E-09
1.0E-09
1.0E-10
1.0E-10
1.0E-11
1.0E-11
1.0E-12
-25 -24 -23 -22 -21 -20 -19 -18 -17 -16 -15
1.0E-12
-25 -24 -23 -22 -21 -20 -19 -18 -17 -16 -15
OMA [dBm]
OMA [dBm]
Specification (informative): -15.1dBm[2]
[2]
IEEE Std 802.3-2005, page 108, Table 38-4 (Average Power converted to OMA)
Reference Design HFRD-29.11 (Rev. 0, 6/09)
Maxim Integrated
Page 12 of 27
5.5
Receiver LOS and RSSI, 10.3125Gbps (Finisar ROSA)
LOS Hysteresis vs Temperature
LOS vs Temperature
-10
Activation OMA [dBm]
Hysteresis OMA [dBm]
5
4
3
2
1
-11
LOS ON
-12
LOS OFF
-13
-14
-15
-16
-17
-18
-19
0
-20
0
20
40
60
80
100
Temperature [0C]
-20
-20
0
20
40
60
80
0
Temperature [ C]
LOS level: 63 (Decimal); VCC: 3.3V
RSSI Level vs Input
400
350
Relative level
300
-15C, 2.95V
250
-15 C, 3.65 V
0C, 2.95 V
200
0C, 3.65 V
150
25 C, 3.3 V
50 C, 3.3 V
100
70 C, 2.95V
70 C, 3.64 V
50
85 C, 2.95 V
85 C 3.65 V
0
0
200
400
600
800
Average Power [mW]
Reference Design HFRD-29.11 (Rev. 0, 6/09)
Maxim Integrated
Page 13 of 27
100
6 Applications Information
6.1
Small Form-Factor Pluggable
Transceivers
The HFRD-29.11 transceiver design was
specifically engineered to meet the requirements
of the small form-factor pluggable (SFP+)
transceiver Multisource Agreement (MSA). This
MSA sets guidelines for the package outline, pin
function, and other aspects of the module design.
By complying with the standard, modules are
mechanically and functionally interchangeable.
6.2
Monitor Functions
HFRD-29.11 provides monitor outputs for RSSI,
bias current, temperature, VCC, and VCSEL
monitor diode power level. The uncalibrated data
is displayed in the Maxim-supplied GUI discussed
below. To convert to an internally-calibrated
format, the user can write additional
microcontroller code to perform this function.
6.3
Microcontroller Firmware
This reference design is provided with basic
microcontroller firmware. The firmware contains
the following functions:
•
•
•
•
•
•
•
Automatic power control (APC)
Tx disable
Tx fault indicator
LOS indicator
Uncalibrated monitor outputs
I2C connection to host
3-wire interface to MAX3799
Additional code will be required to make the unit
fully MSA compliant. It is the responsibility of the
module designer to ensure that the code has been
thoroughly reviewed. Maxim can provide a copy
of the basic firmware used in the design to serve
as a general guideline for implementing the APC
control function and 3-wire interface.
Reference Design HFRD-29.11 (Rev. 0, 6/09)
6.4
Layout Considerations
Differential and single-ended transmission lines
are designed on the HFRD-29.11 PC board.
Changing the PCB layer profile can affect the
impedance of these transmission lines and the
performance of the reference design. If the layer
profile is changed, the transmission line
dimensions should be recalculated. Additional
details are provided in sections 12 and 13.
6.5
Host-Board Requirements
To fully evaluate the HFRD-29.11, a Maxim Host
Board, HFRD-30.1, is recommended. The
HFRD-30.1 provides: the controlled impedance
interface between the reference design and user’s
high-speed test equipment, such as the
oscilloscope; and the bit error ratio tester (BERT).
In addition, the host board enables the user to run
the Maxim-provided GUI software through a
standard USB connection. More details on this are
provided in section 7 titled, “Getting Started.”
6.6
Operating Data Rates
The HFRD-29.11 provides compliant sensitivity at
data rates of either 1.25Gbps (8B10B coding) or
10.3125Gbps (64/66 coding). The required output
power and extinction ratio for the optical signal
are also dependent on the data rate selected. When
a module sample is shipped to a customer, it is
configured for the 10.3125Gbps data rate. The
extinction ratio is set in the range of 4.5dB to 5dB.
Optical power is set in the range of -1dBm to 3dBm. The customer can test the part at 1.25Gbps,
but will need to adjust the modulation and APC
levels for the desired extinction ratio and output
power.
6.7
Operating Temperature
The operating temperature range of the MAX3799
is from -40oC to +85oC. The recommended
operating temperature of the TOSAs and ROSAs
varies from one manufacturer to the next.
Maximum VCSEL case temperature is generally
specified as +85°C. Minimum VCSEL case
temperature varies from -40°C to 0°C. The
suggested operating temperature range for the
HFRD-29.11 is 0°C to +85°C.
Maxim Integrated
Page 14 of 27
6.8
Gerber Files
7 Getting Started
The Gerber files for this reference design are
available by contacting Maxim support at 1-800988-9872 between 8 a.m. and 5 p.m. Pacific Time,
or by accessing our customer support through the
website at: https://support.maxim-ic.com/. While
Gerber files can be provided, it is still the module
designer’s responsibility to ensure that the layout
meets all of their mechanical and thermal
requirements.
6.9
The HFRD-29.11 can be evaluated on any host
board; however, to utilize the added benefit of the
Maxim-supplied GUI, Maxim’s host board,
HFRD-30.1, is recommended. (Please refer to
Reference Design HFRD-30.1 for complete details
on
the host
board:
http://www.maximic.com/products/optical/reference_designs/ )
Figure 2 shows the host board and associated
connections. Precautions must be taken to ensure
safe operation when using a device with a laser
diode. Laser-light emissions can be harmful and
may cause eye damage. Maxim assumes no
responsibility for harm or injury as a result of the
use of this reference design. The safe operation of
this design is the sole responsibility of the user.
TOSA and ROSA Options
At the time of this publication, there are three
TOSA options and two ROSA options for
HFRD-29.11. These options are outlined in
sections 3.1.3 and 3.1.4. When making a sample
request, the customer should indicate which
TOSA and ROSA are required. At special request,
Maxim may also install a customer’s custom
TOSA or ROSA, provided that they meet the
correct mechanical and electrical specifications.
SFP+ TEST SETUP
BLOCK DIAGRAM
Multimeter /
LED
Indicators
Computer
USB Interface
Pattern
Generator /
BERT,
Serializer
Deserializer
or FPGA
Low-Speed Digital I/O
Fiber
SMA
Received Data
SMA
SMA
Transmitt Data
SMA
20Pin
SFP
SFP+ Host Board
(HFRD-30.1)
Optical
Test
Equipment
HFRD29.11
Fiber
Power Supply
Figure 2. HFRD-29.11 with HFRD-30.1 host PCB.
Reference Design HFRD-29.11 (Rev. 0, 6/09)
Maxim Integrated
Page 15 of 27
1) Start with the host board. Attach a differential
source such as a pattern generator to the Tx data
inputs using equal lengths of high-speed SMA
coax cable. The output level of the pattern
generator should be set to a nominal level of 1V
differential.
10) Connect the other end of the fiber to a highspeed 850nm optical source through an optical
attenuator.
2) Connect the Rx data SMA outputs on the host
PCB to either an oscilloscope or BERT which is
triggered by the pattern generator.
12) The transceiver registers are preset to permit
operation without running the GUI. To enable the
optical output without running the GUI, connect
the Tx disable test point on the host board to
ground. The optical transmit eye should be
observable on the scope.
3) Connect a computer to the USB port on the host
PCB. The GUI software provided with this
reference design should be installed in this
computer.
4) Connect a power supply to the 3.3V terminal on
the host board. Set the power-supply current limit
to 250mA. Do not apply power.
5) Insert the HFRD-29.11 into the host board.
6) Carefully insert an LC multimode fiber-optic
cable into the TOSA barrel; take care not to strain
the TOSA flex. The optical cable should be
secured to prevent damage to the TOSA if the
fiber is accidentally moved.
7) Connect the other end of the fiber-optic cable to
a high-speed oscilloscope through an optical-toelectrical converter or an optical plug-in module.
The optical-to-electrical conversion should have a
bandwidth sufficiently large for the operating bit
rate and should be able to detect 850nm
wavelengths.
Note: The laser supplied with the reference
design may be capable of delivering more than
1mW of power. Attenuation may be required if
the optical power exceeds the optical-toelectrical device’s input power rating.
11) Apply power to the host board. Current draw
should be less than 200mA.
13) The receiver output and LOS will also be
operational. If an external reference transmitter is
used as an optical source to test the receiver, the
output electrical eye will be active. The RS0 is
pulled high on the host board (wide bandwidth,
low gain).
8 SFP+ Evaluation Software
Running the GUI allows the user to access and
modify the settings within the MAX3799. The
GUI also displays several monitor functions:
•
•
•
•
•
Temperature
VCC
VCSEL monitor level
Bias current
RSSI level
In the firmware provided with this reference
design, all functions except the bias current (mA)
are displayed in the GUI in an uncalibrated
format.
8) To view the receiver output, attach equal length
high-speed SMA coaxial cables to the differential
outputs from the host board to the oscilloscope.
9) Connect a multimode fiber with an LC-type
ferrule to the ROSA. Follow the same precautions
outlined in step 6 above.
Reference Design HFRD-29.11 (Rev. 0, 6/09)
Maxim Integrated
Page 16 of 27
8.1
Running the GUI
Activate the GUI. The screen shown below
should appear.
1
1. USB Connect. Pressing this button initializes
the test communication. This button resets the
GUI interface, and initializes a test sequence to
determine if the HFRD-30.1 is connected to the
computer. The software then scans the I2C bus to
determine if any I2C-addressable modules are
connected to the HFRD-30.1 host board.
Reference Design HFRD-29.11 (Rev. 0, 6/09)
Maxim Integrated
Page 17 of 27
1
2
1
3
4
1. Status LEDs and Controls. Pressing TX
Enabled or TX Disabled enables or disables the
transmitter. Pressing RS0 or RS1 will toggle the
output high or low. Transmit status indicators are
also displayed.
2. Supply Monitoring. This section displays the
voltage and current for the SFP+ module. The
transmitter and receiver VCC are connected
together inside the SFP+ module. The SFP+ host
board splits the current-draw reading, so the total
current draw for the module is the sum of the
transmit and receiver current.
Reference Design HFRD-29.11 (Rev. 0, 6/09)
3. Transmitter Controls. The majority of
transmitter control registers are handled here.
Toggle settings are provided for bias current and
modulation current registers, as well as pulsewidth selection and de-emphasis. When the APC
loop is in operation, the bias current is
automatically controlled and set by the
microprocessor.
4. Receiver Controls/Indicator. The receiver
control functions are handled in this section.
Output level and LOS threshold are adjustable. An
Rx LOS indicator replicates the indicator located
on the host board. Note: To allow the option of
selecting the low-bandwidth high-gain setting
(8GHz is unchecked), the RS0 test point on the
host board must be connected to ground.
Otherwise the bandwidth will remain in the high
condition.
Maxim Integrated
Page 18 of 27
2
1
3
4
1. APC Loop. The APC loop function is enabled
or disabled depending upon the setting selected.
2. Monitor Diode Current. This function selects
the level of monitor diode current (arbitrary units)
that is maintained by the APC loop. If the APC
loop is disabled, then this setting has no effect.
3. Modulation Current Settings. This is a
duplicate function also provided in the
“Transmitter Controls” section above.
4. Bias Current Settings. These settings control
the initial value and initial step size used by the
APC algorithm when the TX Enabled is activated.
A larger initial starting value and step size reduce
the APC loop convergence time. If too large an
initial value is entered for bias, then the optical
output can overshoot during TX Enabled. The
Max Value is a duplicate entry, also provided in
the “Transmitter Controls” section.
Reference Design HFRD-29.11 (Rev. 0, 6/09)
Maxim Integrated
Page 19 of 27
2
1
1. Digital Monitors. All values displayed are
uncalibrated except for bias current.
2. Controller Memory. This section allows the
user to read and write to the controller memory.
Reference Design HFRD-29.11 (Rev. 0, 6/09)
Maxim Integrated
Page 20 of 27
1
2
1. Individual Registers. This section provides an
alternate way to set specific control bits. Select the
desired register from the pulldown, toggle the
desired bits in the New Value section, and press
Write. The newly written values should appear in
the Current Value section.
2. Set Defaults. Prior to removing power from the
module, press the Set Defaults button to save the
latest changes to transmitter and receiver settings.
Otherwise, upon activation of power the previous
default values will be loaded.
Reference Design HFRD-29.11 (Rev. 0, 6/09)
Maxim Integrated
Page 21 of 27
9 Signal Definitions
Connector
Pin
I/O Type
1, 17, 20
Name
VEET
Definition
Module transmitter ground (Note 4)
2
LVTTL
OUTPUT
TX_FAULT
3
LVTTL
INPUT
TX_DISABLE
Transmitter disable input; the transmitter is disabled when TX_DISABLE is
asserted.
4
LVTTL
INPUT /
OUTPUT
MOD-DEF2
2-wire serial interface, bidirectional data line (Note 1)
5
LVTTL
INPUT
MOD-DEF1
2-wire serial interface clock line (Note 1)
6
LVTTL
OUTPUT
MOD-DEF0
Pin is pulled low by the SFP+ module to indicate to the host controller that a
module is present (Note 1).
7
LVTTL
INPUT
RATE SEL1
Optional bandwidth selection input (not used in HFRD-29.11)
8
LVTTL
OUTPUT
LOS
Receiver loss-of-signal output (Note 1); output is high when receiver input
signal is below the set threshold (Note 2).
9
LVTTL
INPUT
RS0
Sets receiver input mode (0 = low BW; 1 = high BW).
VEER
Module receiver ground (Note 4)
10, 11, 14
Transmitter fault output (Note 1); the transmitter is disabled when TX_FAULT
is asserted.
12
OUTPUT
RD-
Inverted received data output, AC-coupled inside the SFP+ module
13
OUTPUT
RD+
Noninverted received data output, AC-coupled inside the SFP+ module
15
VCCR
+3.3V receiver power-supply connection; may be internally connected to
VCCT inside the SFP+ module (Note: 3).
16
VCCT
+3.3V transmitter power-supply connection; may be internally connected to
VCCR inside the SFP+ module (Note: 3).
18
INPUT
TD+
Inverted transmit data input, AC-coupled inside the SFP+ module
19
INPUT
TD-
Noninverted transmit data input, AC-coupled inside the SFP+ module
Note 1: Open collector output. These pins must be pulled high (+2.95V to +3.65V) on the host board through
a 4.7kΩ to 10kΩ resistor.
Note 2: LOS function can be inverted, if desired, in the HFRD-29.11.
Note 3: VCCR and VCCT are connected together inside HFRD-29.11.
Note 4: VEER and VEET are connected together inside HFRD-29.11
Reference Design HFRD-29.11 (Rev. 0, 6/09)
Maxim Integrated
Page 22 of 27
10 Component List
Reference
Qty
Value
5
2
1
4
6
0.1µF
0.001µF
680pF
1.0µF
0.01µF
CAPACITOR (0201)
CAPACITOR (0402)
CAPACITOR (0201)
CAPACITOR (0402)
CAPACITOR (0201)
12
3
2
0.01µF
680pF
20pF
CAPACITOR (0402)
CAPACITOR (0402)
CAPACITOR (0201)
7
1
1
3
0.1µF
L12-13
L4 L10
L5 L8
L7 L9 L6 L3
R10
R11-12 R14 R20 R22
R1-3 R7 R15 R17
R16
R18
R4, R19
R23 R26
R24-25
R27-28
R29-30
R5
R6 R13
R8 R21
R9
2
2
2
4
1
5
6
1
1
2
2
2
2
2
1
2
2
1
47µH
U1
U2
U3
U4
U5
1
1
1
1
1
U6
U7
1
1
CAPACITOR (0402)
DIODE, ROHM RB521CS-30
SOLDER JUMPER (0201)
BEAD, MURATA BLM15BD601SN1
INDUCTOR (0603) TAIYO YUDEN
LBMF1608T470K
BEAD, MURATA BLM15HB121SN1
BEAD, MURATA BLM18GG601SN1
BEAD, MURATA BLM15HG102SN1
RESISTOR (0402)
RESISTOR (0402)
RESISTOR (0402)
RESISTOR (0402)
RESISTOR (0402)
RESISTOR (0402)
RESISTOR (0402) Note 1
RESISTOR (0402) Note 1
RESISTOR (0201) Note 2
RESISTOR (0201) Note 2
RESISTOR (0402)
RESISTOR (0201)
RESISTOR (0402)
RESISTOR (0402)
ATMEL ATMEGA88V-10MU
MICROCONTROLLER
MAX3799
TOSA w FLEX
ROSA w FLEX
PMOS TRANSISTOR FAIRCHILD FDN302P
LM20BIM71NOPB, NATIONAL TEMP
SENSOR
MAX4073TAXK-T IN SC70-5
U8
1
NC7WZ07P6X, BUFFER IC NON-INVERTING
C1 C3 C8 C11-12
C10 C37
C13
C15 C19 C31 C36
C16 C30 C34 C40-42
C2 C14 C17 C22-23 C25
C27-29 C33 C35 C38
C4 C20-21
C5-6
C7 C9 C18 C24 C26 C32
C39
D1
JU1
L1-2 L11
4.99K
8.06K
10.0K
49.9
4.75K
0
DNI
0
DNI
0
6.81K
30.1
1.0K
20.0K
Description
Note 1: For ground reference RSSI operation: R26 = 1kΩ, R23 = 0Ω, R24-R25 = DNI, U7 = DNI. Jumper
pin 1 to pin 4 at U7 location.
Note 2: To increase buffer attenuator from 0dB to 4dB: R29 to R30 = 24Ω, R27 to R28 = 440Ω.
Reference Design HFRD-29.11 (Rev. 0, 6/09)
Maxim Integrated
Page 23 of 27
11 Schematic
Figure 3. HFRD-29.11 schematic.
Reference Design HFRD-29.11 (Rev. 0, 6/09)
Maxim Integrated
Page 24 of 27
12 Board Layout
Figure 4. Board layout, component side—Layer 1
Figure 5. Board layout, ground plane—Layer 2.
Figure 6: Board layout, miscellaneous routing and VCC—Layer 3.
Reference Design HFRD-29.11 (Rev. 0, 6/09)
Maxim Integrated
Page 25 of 27
Figure 7. Board layout, miscellaneous routing—Layer 4.
Figure 8. Board layout, VCC plane—Layer 5.
Figure 9. Board layout bottom side—Layer 6.
Reference Design HFRD-29.11 (Rev. 0, 6/09)
Maxim Integrated
Page 26 of 27
13 Layer Profile
The HFRD-29.11 includes controlled-impedance
transmission lines. The layer profile is shown in
Figure 10. The controlled-impedance transmission
line connecting the output of the MAX3799 to the
TOSA flex is between layer 1 and layer 3. A
dielectric constant of 4.3 is assumed.
6 mil 6 mil 6mil
pre-preg
5mil
0.5 oz
Layer 2
Core
4mil
Controlled impedance
from the MAX3799
output and TOSA flex
connection is between
layer 1 and layer 3.
0.5 oz
Layer 3
pre-preg
as needed
0.5 oz
Layer 4
Core
4 mil
0.5 oz
Layer 5
pre-preg
Layer 6
12 mil 8mil 12 mil
0.5 oz
Layer 1
5 mil
0.5 oz
Figure 10. Layer profile for HFRD-29.11
EMCORE is a registered trademark of EMCORE Corp.
Finisar is a registered trademark of Finisar Corp.
JDSU is a trademark of JDS Uniphase Corporation.
IEEE is a registered service mark of the Institute of Electrical and Electronics Engineers.
Reference Design HFRD-29.11 (Rev. 0, 6/09)
Maxim Integrated
Page 27 of 27