SM3320AGA Optical Sensor IC OVERVIEW The SM3320AGA is an image sensor IC with a built-in single picture element (pixel) photodiode of 1mm2 and programmable signal conditioning circuit. The IC has an optical filter on chip with target condition 585nm±30nm, and it integrates all the elements required for optical sensor into an ultra-miniature package. The signal condition circuit has a programmable gain amplifier with dark current compensation circuit, so that it can operate in wider temperature range. With 3 addressing bits, up to 8 SM3320AGA can be paralleled. PACKAGE DIMENSIONS 12 pin HCOB 5.5 ±0.1 0.6 ±0.1 A 0.35 1.15 ±0.2 3.2 ±0.1 0.5 0.25 ±0.05 Photodiode detector dimensions(Origin:Package center) A B X -1.15 1.15 Package type : 12pin HCOB Package size : 3.2mm×5.5mm Photodiode detector size : 2.3mm×0.6mm (1.0mm2 photo detector surface area) Y -0.7 -0.1 TYPICAL APPLICATION CIRCUIT DATA OE CLK SE VDD SM3320AGA X SM3320AGA IC1 SM3320AGA IC2 SM3320AGA IC3 VSS REF A0 A1 A2 OUT Package B Photodiode detector DATA OE CLK SE VDD Device Y VSS REF A0 A1 A2 OUT ORDERING INFORMATION (Unit: mm) DATA OE CLK SE VDD ▪ Optical filter on chip with target condition: 585nm±30nm ▪ Dark current compensation circuit built-in for stable signal output ▪ Gain setting and output control function using serial interface (DATA, SE, CLK, OE) ▪ Connection up to 8 devices in parallel according to 3-bit address setting ▪ Transimpedance range: 500kΩ to 240MΩ ▪ Photodiode detector size: 2.3mm×0.6mm (1.0mm2 photodetector surface area) ▪Anti-reflection film coating with little sensitivity changing by wavelength ▪ Supply voltage range: 2.7 to 5.5V (single supply) ▪ Current consumption: 1.5mA (typ)@VDD=5V, no load ▪ Operating temperature range: -40 to +85°C ▪ Package: 12 pin HCOB VSS REF A0 A1 A2 OUT FEATURES ADC ADC CPU SEIKO NPC CORPORATION - 1 SM3320AGA PINOUT NC DATA OE CLK SE VDD 12 11 10 9 8 7 1 2 3 4 5 6 VSS REF A0 A1 A2 OUT (Top view) PIN DESCRIPTION No. Name I/O 1 VSS S Ground 2 REF O Reference voltage 3 A0 I Address setting input 0 4 A1 I Address setting input 1 5 6 A2 OUT I O Address setting input 2 Analog output 7 VDD S Supply voltage 8 SE I Serial I/F enable input 9 CLK I Serial I/F clock input 10 OE I Output enable control 11 12 DATA NC I/O - *. I/O: Input/Output pin I: Input pin O: Output pin Description Serial I/F data input/output Leave open-circuit for normal use S: Supply pin BLOCK DIAGRAM Pre Amplifier Photodiode ＋ － Sample & Hold Offset Cancel Post Amplifier Buffer OUT Dark Current Compensation Timing Generator VDD VSS OE SE DATA A2 CLK A1 Serial Interface A0 REF Reference Voltage Source SEIKO NPC CORPORATION - 2 SM3320AGA SPECIFICATIONS Absolute Maximum Ratings VSS=0V Parameter Supply voltage*1 *1*2 Input voltage Output voltage*1*2 Symbol Storage temperature Rating Unit -0.3 to +7.0 V VDD VDD pin VIN DATA, CLK, SE, OE, A0, A1, A2 pins -0.3 to VDD+0.3 V OUT, REF pins -0.3 to VDD+0.3 V -55 to +90 °C VOUT *3 Conditions TSTG *1. These ratings must not be exceeded, not even momentarily. If a rating is exceeded, there is a risk of IC failure, deterioration in characteristics, and decrease in reliability. *2. VDD is a VDD value of recommended operating conditions. *3. When stored in nitrogen or vacuum atmosphere applied to IC itself only (excluding packaging materials). Recommended Operating Conditions The recommended operating conditions are the conditions for which the electrical characteristics are guaranteed. VSS=0V Parameter Supply voltage Symbol VDD Conditions MIN TYP MAX Unit 2.7 5.0 5.5 V OUT output load*1 - - 100 pF REF output load*1 - - 100 pF -40 - 85 °C Operating temperature Ta *1. The output load of the OUT and REF outputs presumes capacitive load only. For current load, an error in the output voltage occurs, so the outputs must be used under high-impedance conditions. Note. Since it may influence the reliability if it is used out of range of recommended operating conditions, this product should be used within this range. SEIKO NPC CORPORATION - 3 SM3320AGA Electrical Characteristics DC Characteristics Recommended operating conditions using reference circuit, unless otherwise noted Parameter Current consumption Logic input voltage 1 Logic input voltage 2 Logic input current 1 Logic input current 2 Logic output impedance REF output voltage OUT maximum output voltage Output impedance Symbol Conditions IDD OE=0V, No output load VIH1 DATA,CLK,SE,A0,A1,A2 pins VIL1 VIH2 VIL2 IIH1 IIL1 IIH2 IIL2 ZDATA VREF VOUTH ZO OE pin, VDD=5.0V MAX Unit mA - 1.5 3.0 - - - - 0.2VDD 0.8VDD - - VIH=VDD - - 0.2VDD 1 VIL=0V -1 - - VIH=VDD - 10 20 VIL=0V -20 -10 - - - 400 Ω 0.08VDD 0.65VDD 0.10VDD 0.70VDD 0.12VDD - V V - 400 1000 Ω DATA pin, read mode *1 Load capacitance < 100pF OUT pin*2 TYP 0.8VDD OE pin DATA,CLK,SE, A0,A1,A2,pins MIN V V μA μA *1. If a large load capacitance is connected to REF, the REF voltage may begin to oscillate. Accordingly, the load capacitance connected to the REF output should be 100pF or lower. *2. The output impedance ZO is given by the following equation, where V10 is the output voltage for 10kΩ load resistance and V0 is the output voltage with no load. ZO = (V0/V10 - 1)*10 [kΩ] SEIKO NPC CORPORATION - 4 SM3320AGA Photodiode Characteristics Recommended operating conditions using reference circuit, unless otherwise noted. *1 Parameter Symbol Conditions MIN TYP MAX Unit *1 S1/S4 470nm - - 20 % *1 S2/S4 525nm - - 30 % *1 S3/S4 545nm - - 60 % Photodetector sensitivity 1 Photodetector sensitivity 2 Photodetector sensitivity 3 *1 Photodetector sensitivity 4 S4 590nm 0.23 0.33 - A/W Photodetector sensitivity 5*1 Photodetector sensitivity 6*1 S5/S4 S6/S4 630nm 870nm - - 60 30 % % *1. Typical characteristics determined on standalone device. Photodiode spectral responsivity charactreistic (typ) Responsivity [A/W] 0.5 0.4 0.3 0.2 0.1 0 300 400 500 600 700 800 900 1000 1100 1200 Wavelength [nm] Photodiode spectral responsivity Photodiode spectral responsivity charactreistic (typ) Responsivity [A/W] 0.5 0.4 0.3 0.2 0.1 0 500 520 540 560 580 600 620 640 660 Wavelength [nm] Photodiode spectral responsivity (500nm~680nm) SEIKO NPC CORPORATION - 5 SM3320AGA Analog Electrical Characteristics Recommended operating conditions using reference circuit, unless otherwise noted. Parameter Symbol Conditions MIN TYP MAX Unit - 0.5 - MΩ - 1.0 2.0 - MΩ MΩ CS[11] - 4.0 - MΩ CS[00] - 1.5 - MΩ 3.0 - MΩ - 6.0 - MΩ - 12.0 3.5 - MΩ MΩ - 7.0 - MΩ CS[00] CS[01] CS[10] TS[00] CS[01] TS[01] CS[10] CS[11] CS[00] Preamplifier transimpedance*1 CS[01] TS[10] CS[10] - 14.0 - MΩ CS[11] - 28.0 - MΩ CS[00] - 7.5 - MΩ - 15.0 30.0 - MΩ MΩ - 60.0 - MΩ TS[00] - 20 30 μs TS[01] - 40 60 μs TS[10] - 80 120 μs TS[11] - 160 - 240 ±1 μs dB REF reference, [01111111] below -40 - 40 mV REF reference, [11111111] below -40 - 40 mV CS[01] CS[10] TS[11] CS[11] Preamplifier conversion time Postamplifier gain error Dark voltage *1. Design value: Preamplifier transimpedance is determined by specifying the preamplifier feedback capacitance (CS[1:0]) and preamplifier conversion time (TS[1:0]). This is a virtual impedance called the preamplifier transimpedance. The preamplifier transimpedance (Rti) is calculated using the following equation. Rti = ( Preamplifi er conversion time − 10 μ sec) Preamplifi er feedback capacitanc e The sample and hold circuit is synchronized to the preamplifier conversion time. To determine the output voltage, the sample and hold circuit must complete one full cycle after photoirradiation. The photoirradiation time should be set to a value equal to or greater than the detection time (double the maximum preamplifier conversion time) + analog output capture time. If photoirradiation ends before analog output capture, the output voltage may drop or fall to zero. Photoirradiation should be continuous until analog output capture is completed. . Photoirradiation time Light Source Serial Interface Gain setting time Analog output load Output control time Detection time Analog output capture time Preamplifier conversion time TS[00] TS[01] TS[10] TS[11] Detection time ≥60μs ≥120μs ≥240μs ≥480μs Output voltage = VREF + (Rti × Photodiode photocurrent × Postamplifier gain) SEIKO NPC CORPORATION - 6 SM3320AGA AC Characteristics Data Write Mode Recommended operating conditions using reference circuit, unless otherwise noted. Parameter Symbol Conditions MIN TYP MAX Unit Write clock LOW-level pulse width twlw CLK pin 40 - - ns Write clock HIGH-level pulse width twhw CLK pin 40 - - ns Data setup time 1 tsu1 Between SE-CLK 40 - - ns Data setup time 2 Data hold time 1 tsu2 th1 Between DATA-CLK Between SE-CLK 40 140 - - ns ns Data hold time 2 th2 Between DATA-CLK 40 - - ns - - 10 MHz - - 2 μs - 0.1 - Write clock frequency fclkw tz OUT pin, 100pF load, 1V output amplitude variation, time to reach 95% level OUT pin Input capacitance CI SE,OE,CLK,DATA pins - 5 - μs pF Output capacitance*2 CO OUT pin - 5 - pF Interface wait time tsi 100 - - ns Settling time tst Output disable time*1 *2 *1. Design value: Provided as a measure for the output control time. *2. Design value: Indicates the terminal capacitance per pin. Provided as a guide for when designing the circuit board. LOW/HIGH-level switch timing measured with respect to 0.5VDD reference level, unless otherwise noted. OE tsi SE R/W DATA tsu2 A2 A1 GS1 CLK 1 2 GS0 th2 twhw twlw 3 15 th1 16 1/fclkw tsu1 tst tz OUT 95% 100% Data Read Mode Recommended operating conditions using reference circuit, unless otherwise noted. Parameter Symbol Conditions MIN TYP MAX Unit Read clock LOW-level pulse width twlr CLK pin 500 - - ns Read clock HIGH-level pulse width twhr CLK pin 500 - - ns Read clock frequency fclkr - - 1 MHz 500 - - ns - - 400 ns SE hold time tse Between SE-CLK Read-out data delay time tRD DATA pin, load capacitance=100pF LOW/HIGH-level switch timing measured with respect to 0.5VDD reference level, unless otherwise noted. "L" or open OE SE DATA R/W A2 A1 - CS1 tZZ CLK 1 2 3 7 8 tRD CS0 GS1 GS0 twhr 9 twlr 15 tse 16 1/fclkr SEIKO NPC CORPORATION - 7 SM3320AGA FUNCTIONAL DESCRIPTION Basic Function The SM3320AGA detects the current generated from a photodiode and outputs a voltage signal. The transimpedance of the preamplifier can be adjusted for coarse adjustment of the responsivity. The transimpedance adjustment range is 0.5 to 60MΩ, set using 4 adjustment bits. Also, a dark current compensation circuit is used to compensate photodiode output under dark lighting conditions for output voltage stability with low temperature variation. The gain of the postamplifier can be adjusted for fine adjustment of the responsivity. The gain adjustment range is 1 to 4 times, set using 4 adjustment bits. Also, a built-in offset cancel circuit is used to provide low offset voltage at the output. The output voltage when there is no photoirradiation, called the dark voltage, is 0.1VDD. The maximum output voltage with photoirradiation is 0.7VDD. The device can be addressed using address pin control. This function allows the transimpedance and gain settings to be adjusted for each device independently when multiple devices are connected in parallel. An output enable control (OE) is used for output control. [Address and A[2:0] setting] Address A2 setting A1 setting A0 setting [000] [001] [010] [011] [100] [101] [110] [111] VSS VSS VSS VSS VDD VDD VDD VDD VSS VSS VDD VDD VSS VSS VDD VDD VSS VDD VSS VDD VSS VDD VSS VDD Serial Interface The SM3320AGA use a 3-wire serial interface (SE, CLK, DATA) to access the device and to set an internal register to control device operation. Note that extraneous signal input on the serial interface pins must be avoided when not reading/writing data to the device to prevent incorrect operation. Internal Register Structure The device read/write mode, address, operating mode, preamplifier transimpedance, and postamplifier gain are set in an internal register. The device can be accessed for writing data to or reading data from the register when the A[2:0] address write data bits match the setting of the address control inputs (A2 to A0). Note that register data must be configured before using the device. Address RW R/W A2 A1 Data A0 D11 D10 D9 D8 - - - D6 D5 D4 D3 Preamplifier transimpedance Feedback Conversion capacitance time Don’t care address D7 - CS1 CS0 TS1 TS0 D2 D1 D0 Postamplifier gain GS3 GS2 GS1 GS0 (1) RW Read/Write mode set bit. Set to “1” for read mode, and to “0” for write mode. (2) Address A[2:0] (A2 to A0) Address bits. (3) Preamplifier transimpedance CS[1:0] (D7 to D6) and TS[1:0] (D5 to D4) Preamplifier transimpedance setting bits (4) Postamplifier gain GS[3:0] (D3 to D0) Postamplifier gain setting bits SEIKO NPC CORPORATION - 8 SM3320AGA [Adjustment bit assignment] CS[1:0] Preamplifier feedback capacitance CS1 CS0 0 0 0 1 1 0 1 1 TS[1:0] Preamplifier conversion time TS1 TS0 0 0 0 1 1 0 1 1 Capacitance (pF) 20.0 10.0 5.0 2.5 GS[3:0] Time (µs) 20 40 80 160 GS3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Postamplifier gain GS2 GS1 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 GS0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Gain (times） 1.00 1.08 1.17 1.27 1.38 1.50 1.63 1.78 1.94 2.13 2.33 2.57 2.85 3.17 3.55 4.00 OUT pin Control The OUT pin is controlled by the level of the OE control pin. OE pin OUT pin Conditions ≥ 0.8VDD Output enable Normal operation output when A[2:0] write data matches the setting of the address control inputs. Open Output enable Normal operation output ≤ 0.2VDD Output disable SEIKO NPC CORPORATION - 9 SM3320AGA Gain Setting (register write mode, OE = LOW or open-circuit) If OE is LOW or open circuit, serial interface operation starts when SE goes HIGH. Write data comprises 1 read/write mode bit (write mode = 0), 3 address bits, and 12 write data bits transferred in sequence. If the address data bits match the address control pin settings (meaning the device is addressed), the write data is loaded into the register, and the write data becomes valid and serial interface operation ends when SE goes LOW. Note that data will be corrupted if there are less than or more than 16 clock pulses received during serial data transfer. Register write (when OE is LOW) "L" OE SE DATA R/W A2 A1 A0 - - - - CS1 CS0 TS1 TS0 GS3 GS2 GS1 GS0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 CLK Register write (when OE is open-circuit) OE (OPEN) "L" SE DATA R/W A2 A1 A0 - - - - CS1 CS0 TS1 TS0 GS3 GS2 GS1 GS0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 CLK OUT (Hi-Z) Analog Output Control (register write mode, OE = HIGH) If OE is HIGH, serial interface operation starts when SE goes HIGH. Write data comprises 1 read/write mode bit (write mode = 0), 3 address bits, and 4 dummy data bits transferred in sequence. The address data becomes valid and serial interface operation ends when SE goes LOW. If the address data bits match the address control pin settings (meaning the device is addressed), the output is enabled. If the output was already enabled and the address data does not match the address pin settings, the output is disabled. Note that if there are less than or more than 8 clock pulses received during serial data transfer, an address mismatch occurs and the output is disabled. In addition, sequential write cycles to the register are permitted while OE is HIGH. Register write (when OE is HIGH) OE SE DATA R/W A2 A1 A0 - - - - 1 2 3 4 5 6 7 8 CLK OUT (Hi-Z) SEIKO NPC CORPORATION - 10 SM3320AGA Reading Data from the Register (OE = LOW or open-circuit) Serial interface operation starts when SE goes HIGH. Read data comprises 1 read/write mode bit (read mode = 1), 3 address bits, and 4 dummy data bits transferred in sequence when OE is open-circuit or goes LOW. The address control pin setting is compared with the address register setting on the falling edge of the 8th CLK pulse. If the settings match (meaning the device is addressed), the data in the 8-bit analog adjustment code register is read out in sequence. On the serial interface, the GS0 data bit is transferred on the 15th falling edge of CLK, and then any data bits transferred between the 16th falling edge of CLK and the falling edge on SE are undefined data. Serial interface operation ends when SE goes LOW, and the DATA terminal reverts to an input. Make sure there are not less than nor more than 16 input pulses on the CLK clock. If the number of clock pulses is incorrect, incorrect data may be written to the register or read from the register. Register read SE DATA R/W A2 A1 A0 - - - - CS1 CS0 TS1 TS0 GS3 GS2 GS1 GS0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 - CLK SEIKO NPC CORPORATION - 11 SM3320AGA REFERENCE CIRCUIT 10μF VSS REF A0 A1 A2 OUT SM3320AGA ADC DATA OE CLK SE VDD CPU Device with [000] address setting Connect a laminated ceramic capacitor of 10μF or larger as close as possible to the supply voltage terminals. The nominal value rating for each electrical characteristics parameter is measured using the reference circuit. SEIKO NPC CORPORATION - 12 SM3320AGA TYPICAL APPLICATION CIRCUITS The typical application circuits are provided for reference only, and do not represent a guarantee of circuit operation. We accept no liability for any damage resulting from the use of these circuits. Always use devices after sufficient evaluation under actual operating conditions. DATA OE CLK SE VDD DATA OE CLK SE VDD DATA OE CLK SE VDD SM3320AGA IC1 SM3320AGA IC2 SM3320AGA IC3 VSS REF A0 A1 A2 OUT VSS REF A0 A1 A2 OUT VSS REF A0 A1 A2 OUT Circuit 1 ADC ADC CPU Timing Diagram OE SE IC1 IC2 IC3 IC1 IC2 IC3 DATA CLK （光照射） (Optical irradiation) (OFF) (ON) Rti OUT(IC1) (Hi-Z) OUT(IC2) (Hi-Z) OUT(IC3) (Hi-Z) OUT(ALL) OUT合成 (Hi-Z) SEIKO NPC CORPORATION - 13 SM3320AGA Circuit 2 VSS REF A0 A1 A2 OUT DATA OE CLK SE VDD VSS REF A0 A1 A2 OUT SM3320AGA IC A8 DATA OE CLK SE VDD VSS REF A0 A1 A2 OUT SM3320AGA IC A2 DATA OE CLK SE VDD SM3320AGA IC A1 DATA OE CLK SE VDD DATA OE CLK SE VDD DATA OE CLK SE VDD SM3320AGA IC B1 SM3320AGA IC B2 SM3320AGA IC B8 VSS REF A0 A1 A2 OUT VSS REF A0 A1 A2 OUT VSS REF A0 A1 A2 OUT CPU ADC ADC Example with 9 or more devices connected in parallel Timing Diagram OE(A) OE(B) SE(A) SE(B) IC A1 IC A8 IC B1 IC B8 IC A1 DATA IC A2 IC A3 IC A1 IC A2 IC A3 CLK (Optical（光照射） irradiation) (OFF) (ON) Rti OUT(IC A1) (Hi-Z) OUT(IC A2) (Hi-Z) OUT(IC B1) (Hi-Z) OUT(IC B2) (Hi-Z) SEIKO NPC CORPORATION - 14 SM3320AGA Please pay your attention to the following points at time of using the products shown in this document. 1. The products shown in this document (hereinafter ”Products”) are designed and manufactured to the generally accepted standards of reliability as expected for use in general electronic and electrical equipment, such as personal equipment, machine tools and measurement equipment. The Products are not designed and manufactured to be used in any other special equipment requiring extremely high level of reliability and safety, such as aerospace equipment, nuclear power control equipment, medical equipment, transportation equipment, disaster prevention equipment, security equipment. The Products are not designed and manufactured to be used for the apparatus that exerts harmful influence on the human lives due to the defects, failure or malfunction of the Products. If you wish to use the Products in that apparatus, please contact our sales section in advance. In the event that the Products are used in such apparatus without our prior approval, we assume no responsibility whatsoever for any damages resulting from the use of that apparatus. 2. NPC reserves the right to change the specifications of the Products in order to improve the characteristics or reliability thereof. 3. The information described in this document is presented only as a guide for using the Products. No responsibility is assumed by us for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any patents or other rights of the third parties. Then, we assume no responsibility whatsoever for any damages resulting from that infringements. 4. The constant of each circuit shown in this document is described as an example, and it is not guaranteed about its value of the mass production products. 5. In the case of that the Products in this document falls under the foreign exchange and foreign trade control law or other applicable laws and regulations, approval of the export to be based on those laws and regulations are necessary. Customers are requested appropriately take steps to obtain required permissions or approvals from appropriate government agencies. SEIKO NPC CORPORATION 1-9-9, Hatchobori, Chuo-ku, Tokyo 104-0032, Japan Telephone: +81-3-5541-6501 Facsimile: +81-3-5541-6510 http://www.npc.co.jp/ Email:[email protected] ND14018-E-00 2014.11 SEIKO NPC CORPORATION - 15