DS3100DK Stratum 3/3E Timing Card IC Demo Kit www.maxim-ic.com GENERAL DESCRIPTION FEATURES The DS3100DK is an easy-to-use demo and evaluation kit for the DS3100 Stratum 3/3E timing card IC. A surface-mounted DS3100 and careful layout provide maximum signal integrity. An on-board Maxim 8051-compatible microcontroller and included software give point-and-click access to configuration and status registers from a personal computer. LEDs on the board indicate interrupt, power-supply function, and GPIO status. The board provides BNC and bantam connectors for the composite clock and BITS interfaces. Single-ended and LVDS clocks are accessed via SMB connectors. All LEDs and connectors are clearly labeled with silkscreening to identify associated signals. Soldered DS3100 for Best Signal Integrity SMB Connectors, BNC, Bantam, Transformers, and Termination Ease Connectivity Careful Layout for Analog Signal Paths On-Board Stratum 3 Oscillator with Footprints for Stratum 3E Oscillators DS3100 Configured for CPU Bus Operation for Complete Control Over the Device On-Board Maxim Microcontroller and Included Software Provide Point-and-Click Access to the DS3100 Register Set LEDs for Interrupt, Power Supplies, and GPIO Included International Power Supply Banana Jack VDD and GND Connectors Support Use of Lab Power Supplies Easy-to-Read Silkscreen Labels Identify the Signals Associated with All Connectors, Jumpers, and LEDs Header Provided for Master/Slave Connection to a Second DS3100DK Software Provides GUI Fields for Most Commonly Used Features Plus Full Read/Write Access to the Entire Register Set Software Support for Creating and Running Configuration Scripts Saves Time During Evaluation DEMO KIT CONTENTS DS3100DK PCB CD-ROM Includes: DS3100 Software DS3100 Initialization File DS3100DK Data Sheet DS3100 Data Sheet DS3100 Rev A2 Errata Sheet MINIMUM SYSTEM REQUIREMENTS PC Running Windows® XP or Windows 2000 Display with 1024 x 768 Resolution or Higher Available USB Port or Serial (COM) Port USB Cable or DB-9 Serial Cable ORDERING INFORMATION PART DS3100DK DESCRIPTION Demo kit for DS3100 Windows is a registered trademark of Microsoft Corp. For software revision 1.0. 1 of 38 REV: 071807 DS3100DK TABLE OF CONTENTS 1. BOARD FLOORPLAN........................................................................................................4 1.1 1.2 1.3 1.4 1.5 1.6 2. INPUT AND OUTPUT CLOCKS ............................................................................................................5 JUMPERS, HEADERS, AND SWITCH SETTINGS ..................................................................................5 COMPOSITE CLOCK INTERFACE .......................................................................................................5 BITS INTERFACES ...........................................................................................................................5 MICROCONTROLLER ........................................................................................................................5 POWER-SUPPLY CONNECTORS........................................................................................................5 BASIC HARDWARE SETUP..............................................................................................6 2.1 3. USB DRIVER INSTALLATION .............................................................................................................6 INSTALLING AND RUNNING THE SOFTWARE...............................................................7 3.1 4. COMMAND LINE OPTIONS ................................................................................................................7 OVERVIEW OF THE SOFTWARE INTERFACE................................................................8 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9 GLOBAL CONFIGURATION ................................................................................................................8 INPUT CLOCK MONITOR, DIVIDER, AND SELECTOR ...........................................................................8 T0 DPLL ...................................................................................................................................... 10 T4 DPLL ...................................................................................................................................... 12 T0 APLL....................................................................................................................................... 13 T4 APLL....................................................................................................................................... 13 OUTPUT CLOCKS...........................................................................................................................14 DPLL FREQUENCY LIMITS, PHASE DETECTORS, DPLL LOCK CRITERIA ..........................................15 BITS RECEIVERS AND BITS TRANSMITTERS ..................................................................................15 4.9.1 4.10 4.11 4.12 4.13 4.13.1 4.13.2 5. Note About Working with the BITS Receivers and Transmitters ......................................................... 15 COMPOSITE CLOCK RECEIVERS .................................................................................................19 REFCLK CALIBRATION ..............................................................................................................19 REGISTER VIEW WINDOW ...........................................................................................................20 CONFIGURATION SCRIPTS AND LOG FILE ....................................................................................21 Configuration Log File .......................................................................................................................... 21 Configuration Scripts............................................................................................................................ 21 ADDITIONAL INFORMATION AND RESOURCES .........................................................21 5.1 5.2 5.3 DS3100 INFORMATION ..................................................................................................................21 DS3100DK INFORMATION .............................................................................................................21 TECHNICAL SUPPORT ....................................................................................................................21 6. APPENDIX 1: HARDWARE COMPONENTS...................................................................22 7. APPENDIX 2: BITS MODE WRITE SEQUENCES...........................................................25 8. SCHEMATICS ..................................................................................................................25 9. DOCUMENT REVISION HISTORY ..................................................................................25 2 of 38 DS3100DK LIST OF FIGURES Figure 1-1. Board Floorplan......................................................................................................................................... 4 Figure 4-1. Software Main Screen ............................................................................................................................... 8 Figure 4-2. Software Input Clock Window ................................................................................................................... 9 Figure 4-3. Software T0 DPLL Window ..................................................................................................................... 11 Figure 4-4. Software T4 DPLL Window ..................................................................................................................... 12 Figure 4-5. Software BITS Receiver Window (DS1 Mode) ....................................................................................... 16 Figure 4-6. Software BITS Receiver Window (E1 Mode) .......................................................................................... 16 Figure 4-7. Software BITS Transmitter Window (DS1 Mode and E1 Mode .............................................................. 16 Figure 4-8. Software CC Receiver Window............................................................................................................... 19 Figure 4-9. Software Register View Window ............................................................................................................. 20 LIST OF TABLES Table 4-1. Mapping Between Input Clock Software Fields and DS3100 Register Fields ........................................... 9 Table 4-2. Mapping Between T0 DPLL Software Fields and DS3100 Register Fields ............................................. 11 Table 4-3. Mapping Between T4 DPLL Software Fields and DS3100 Register Fields ............................................. 13 Table 4-4. Mapping Between T0 APLL Software Fields and DS3100 Register Fields ............................................. 13 Table 4-5. Mapping Between T4 APLL Software Fields and DS3100 Register Fields ............................................. 13 Table 4-6. Mapping Between Output Clock Software Fields and DS3100 Register Fields ...................................... 14 Table 4-7. Mapping Between DPLL Software Fields and DS3100 Register Fields .................................................. 15 Table 4-8. Mapping Between BITS Software Fields and DS3100 Register Fields ................................................... 17 Table 4-9. Mapping Between CC Software Fields and DS3100 Register Fields ...................................................... 19 Table 4-10. Mapping Between REFCLK Software Fields and DS3100 Register Fields ........................................... 19 3 of 38 DS3100DK 1. BOARD FLOORPLAN Figure 1-1 shows the floorplan of the DS3100DK. The DS3100 is in the center of the board, input clock SMB connectors are along the top edge of the board, and output clock connectors are on the bottom edge. Between the input clock connectors and the DS3100, land patterns are provided for several different types of local oscillators, ranging from tiny, inexpensive TCXOs to larger, high-performance OCXOs. The right edge contains, from top to bottom, power-supply connectors, DC-DC converters and power-indicator LEDs, reset pushbutton, serial connector, and USB connector. An on-board DS87C520 microcontroller is located near the USB connector. The left edge of the board is occupied by connectors and transformers for the DS3100’s built-in BITS (DS1/E1/2048kHz) and composite clock (64kHz) receivers and transmitters. Between the BITS and composite clock connectors are a JTAG header and three switches to control the DS3100’s MASTSLV, SONSDH, and SRCSW pins. See APPENDIX 1: HARDWARE COMPONENTS for a complete component list. Complete board schematics follow Appendix 2. Figure 1-1. Board Floorplan Power Option LVDS Input Clocks 5V Banana Jack Single-ended Input Clocks GND Banana Jack Oscillator Circuitry Power Supply Circuitry GPIO Circuitry BITS Interfaces Reset DS3100 RS232 9-Pin Connector Switches Single-ended Output Clocks M\S Hdr Composite Clock Output LVDS Output Clocks USB Connector Composite Clock Input Microprocessor ` JTAG Header 4 of 38 DS3100DK 1.1 Input and Output Clocks There are 13 SMB connectors at the top of the board labeled IC1–IC4, IC7–IC14, and SYNC2K that provide a single-ended clock input to the DS3100. All single-ended clock inputs are connected to the DS3100 with a 50Ω characteristic impedance trace and terminated with 50Ω at the device. Four additional SMB connectors labeled IC5P, IC5N, IC6P, and IC6N provide differential clock inputs to the DS3100. These differential inputs have 50Ω trace impedance and 50Ω termination at the device (i.e., 100Ω differential). On the other end of the PCB are eight SMB clock output connectors labeled OC1–OC5 and OC9, OC10, and OC11. All single-ended clock outputs are buffered at the DS3100 and connected to the SMB connector via a 50Ω characteristic impedance trace. Four additional SMB connectors labeled OC6P, OC6N, OC7P, and OC7N provide connections to the differential outputs from the DS3100. 1.2 Jumpers, Headers, and Switch Settings Jumpers JMP1 to JMP4 (upper right of board) provide input settings to the four DS3100 GPIO pins. If a jumper is installed the corresponding GPIO input is high. With no jumper the GPIO pin defaults low. LEDs DS5–DS8 indicate the logic level of the GPIO pins (LED lit means GPIO pin is high). Switches SW7 to SW9 set the SONSDH, SRCSW, and MASTSLV pins, respectively, high or low as indicated by the silkscreen. Headers J1 and J2 provide access to BITS1 and BITS2 framer signals, respectively. Header J51 provides access to the JTAG port of the DS3100. Header J15 provides interface to a master or slave board depending on position of switch SW6. 1.3 Composite Clock Interface Bantam jacks J89 and J90 provide access to composite clock inputs IC1A and IC2A through a 2:1 transformer. Jumpers JMP7 and JMP6 configure termination for IC1A and IC2A, respectively. Silkscreen text indicates which jumper is necessary to set the interface at 110Ω, 120Ω, or 133Ω. Bantam jack J117 provides an interface through a 1:1 transformer to the OC8 composite clock output. Jumpers JMP8, JMP9, and JMP10 provide different attenuation configurations that are represented in silkscreen (Rs = 91Ω with no jumper installed). See the schematics for additional details on the composite clock termination circuitry. 1.4 BITS Interfaces The BITS1 DS1/E1 LIU uses bantam connectors J85 and J55 or BNC connectors J83 and J57 for transmit and receive interfaces, respectively. The BITS2 LIU uses bantam connectors J86 and J56 or BNC connectors J84 and J58 for transmit and receive, respectively. There is a dual transformer package for each BITS transceiver (component T1 for BITS1 and T2 for BITS2). See the schematics for additional details on the BITS termination circuitry. 1.5 Microcontroller The DS87C520 microcontroller has factory-installed firmware in on-chip nonvolatile memory. This firmware translates memory access requests from the RS-232 serial port or USB port into register accesses on the DS3100. When the microcontroller starts up it turns on DS16 to indicate that the controller is working correctly. A pushbutton switch labeled RESET (SW5) at the right middle of the board resets the microcontroller as well as the DS3100. 1.6 Power-Supply Connectors The included international power supply can be connected to jack J3 to power the board or a 5V lab power supply can be connected across the red (J13) and black (J19) banana jacks. The 5V input is then regulated to 3.3V and 1.8V and distributed to board components. 5 of 38 DS3100DK 2. BASIC HARDWARE SETUP The following steps provide a quick start to using the DS3100DK. 1) Ensure switch SW6 (near the OC1 and OC2 connectors) is in the “MAS” position. 2) Set switch SW9 (MASTSLV) in the “1” (master) position. 3) Set switch SW8 (SRCSW) in the “0” (normal operation) position. 4) Set switch SW7 (SONSDH) to “1.” 5) To communicate with the board using a USB cable: a) Configure the board for USB communication by placing jumpers to connect the middle and right pins of JMP62 and JMP63 (i.e., place the jumpers toward the “USB” silkscreen). b) Connect a USB cable between the USB connector on the DS3100DK and an available USB port on the host computer. 6) To communicate with the board using a serial (RS-232) cable: a) Configure the board for serial communication by placing jumpers to connect the left and middle pins of JMP62 and JMP63 (i.e., place the jumpers toward the “RS232” silkscreen). b) Connect a standard DB-9 serial cable between the serial port connector on the DS3100DK and an available serial port on the host computer. (Be sure the cable is a standard straight-through cable rather than a null-modem cable. Null-modem cables prevent proper operation.) 7) Attach the appropriate AC power supply prongs to the included international power supply. 8) Plug the power supply into an AC power outlet and connect the DC output of the supply to connector J3 (PWR in Figure 1-1). At this point the power indicator LEDs DS1–DS4 should be lit green. Microcontroller status LED DS16 (to the right of the USB connector) should also be lit green. SRFAIL LED DS9 should be lit red. 2.1 USB Driver Installation When the DS3100DK is first connected to the PC using a USB cable, an on-board USB-to-serial converter IC is automatically detected by Windows and the Found New Hardware Wizard is automatically started. Follow these steps to install the driver: 1) In the first screen of this wizard, select “Install from a list or specific location” and click “Next.” 2) In the second screen, select “Search for the best driver in these locations,” check “Include this location in the search,” and browse to the “USB” directory in the DS3100DK CD-ROM or downloaded ZIP file. Click “Next.” 3) Click “Finished.” 4) Repeats steps 1 to 3 the second time the Found New Hardware Wizard starts. After the drivers are installed, whenever the DS3100DK board is connected to a USB port on the PC the Windows operating system will see the USB-to-serial converter IC as an additional COM port. The DS3100DK software will automatically list the additional COM port in the PORT selection combo box in the upper-left corner of the main window. 6 of 38 DS3100DK 3. INSTALLING AND RUNNING THE SOFTWARE At this time the DS3100 demo kit software only runs on Windows 2000 or Windows XP operating systems. To install the demo kit software, run SETUP.EXE from the disk included in the DS3100DK box or from the zip file available on our website at www.maxim-ic.com/DS3100DK. After software installation is complete, set up the hardware as described above and run the software by doubleclicking the DS3100 Demo Kit icon on the Windows desktop or by selecting Start→Programs→Maxim→DS3100 Demo Kit. When the main window appears, select the correct serial COM port in the box in the upper-left corner. (Note that when talking to the DS3100DK over USB cable, the USB-to-serial converter on the board is a virtual COM port.) When communication has been properly established between the software and the hardware, the ID field in the upper-left corner should indicate 3100 rev x, where x = 0 for a revision A1 device, and x = 1 for a revision A2 device. The demo kit software always starts in demo mode (with the DEMO MODE checkbox in the upper-left corner checked) to allow a user to look at the software without having the DK hardware connected to the PC. To connect the software with the demo kit hardware, uncheck the DEMO MODE box. The software optionally initializes the DS3100 device and then reads the state of the device to get ready for use. 3.1 Command Line Options The demo kit software has these command line options: -l <filepath> -p[port#] specifies an alternate log file sets the serial (COM) port number example: “DS3100DK.exe –l mylog.mfg example: “DS3100DK.exe –p2” sets COM2 To add command line options to the DS3100 demo kit shortcut that the installer adds to the desktop, right click on the shortcut and select Properties. In the Shortcut tab, at the end of the text in the Target text box, add a space followed by the command line option. 7 of 38 DS3100DK 4. OVERVIEW OF THE SOFTWARE INTERFACE Figure 4-1. Software Main Screen 4.1 Global Configuration In the upper-left corner of the main window are several global status and configuration fields. The ID field displays the device part number and revision. The M/S field shows the status of the device MASTSLV pin (MCR3:MASTSLV). The PORT field shows the COM port to which the DK board is connected. The DEMO MODE checkbox, which is checked by default, must be unchecked to enable the software to communicate with the DK board. The ENABLE POLLING checkbox, also checked by default, controls software polling of the device. Finally, the SDH and SONET radio buttons (which control device register field MCR3:SONSDH) specify whether 1.544MHz (SON) or 2.048MHz (SDH) is an available frequency option for input clocks 1 to 14 and output clock OC9. 4.2 Input Clock Monitor, Divider, and Selector This box occupying the left-center section of the main window contains the most frequently used configuration and status associated with input clocks IC1–IC14. At the far left, inputs IC1 and IC2 can be configured for either composite clock (on the IC1A and IC2A pins, respectively) or CMOS (on the IC1 and IC2 pins, respectively). Similarly, IC5 and IC6 can be configured for LVDS or PECL operation. Just to the right of the input clock numbers 1–14 are software LEDs that indicate the state of each input as reported by its input monitor. These LEDs are red in the absence of any other condition. When a clock of the correct frequency is applied to an input, the associated LED turns yellow when activity is detected and, about 10 seconds later, it turns green if the input clock frequency is within range. If an input is disqualified by one of the DPLLs because the DPLL could not lock to it, the LED turns magenta. 8 of 38 DS3100DK In the middle of the box, the FREQ and LK MODE fields configure the frequency and lock mode (direct-lock, DIVN, or LOCK8K) for each input clock. At the bottom is a field to configure the DIVN divider used for inputs configured for DIVN mode. All the fields in the box containing the PRIORITY fields display information about either the T0 DPLL or the T4 DPLL, depending on which of two radio buttons is selected at the top of the box. The PRIORITY fields configure the input clock priorities for the selected DPLL. The SEL REF field shows the selected reference for the DPLL, while the REF 1, REF 2, and REF 3 fields display the three highest priority valid inputs for the DPLL. The FREQ and PHASE fields show the real-time frequency and phase reported by the DPLL. Clicking the More button opens another window (Figure 4-2) with additional input clock configuration and status fields. See Table 4-1 for details. Figure 4-2. Software Input Clock Window Table 4-1. Mapping Between Input Clock Software Fields and DS3100 Register Fields SOFTWARE FIELD MAIN WINDOW IC1 Signal Format (CMOS or CC) IC2 Signal Format (CMOS or CC) IC5 Signal Format (LVDS or PECL) IC6 Signal Format (LVDS or PECL) Input Clock Status LEDs 1 to 14 FREQ 1 to 14 LK MODE 1 to 14 PRIORITY 1 to 14 SEL REF REF 1 REF 2 DS3100 REGISTER FIELDS MCR5:IC1SF MCR5:IC2SF MCR5:IC5SF MCR5:IC6SF ISR1–ISR7 registers LED red when ACT = 1, HARD = 1 LED yellow when ACT = 0, HARD = 1 LED green when ACT = 0, HARD = 0, LOCK = 0 LED magenta when ACT = 0, HARD = 0, LOCK = 1 ICR1 to ICR14:FREQ[3:0] ICR1 to ICR14:LOCK8K, and DIVN IPR1 to IPR7 PTAB1:SELREF PTAB1:REF1 PTAB2:REF2 9 of 38 DS3100DK SOFTWARE FIELD REF 3 FREQ (ppm) PHASE (deg) SUBWINDOW Soft 1 to 14 Hard 1 to 14 Act 1 to 14 Lock 1 to 14 Valid 1 to 14 Enable 1 to 14 Bucket 1 to 14 PHLKTO and PHLKTOM Lock Alarm Timeout External Switching Ultra-Fast Switching Soft Alarm Enable Hard Alarm Enable Freq Measurement Input Freq Measurement Freq Freq Measurement Reference Leaky Bucket Settings Freq Monitor Limits, Input Clock Freq Monitor Limits, Selected Ref 4.3 DS3100 REGISTER FIELDS PTAB3:REF3 FREQ1, FREQ2, and FREQ3 registers concatenated PHASE1 and PHASE2 registers concatenated ISR1 to ISR7:SOFT ISR1 to ISR7:HARD ISR1 to ISR7:ACT ISR1 to ISR7:LOCK VALSR1, VALSR2 VALCR1, VALCR2 ICR1 to ICR14:BUCKET PHLKTO MCR3:LKATO MCR10:EXTSW MCR10:UFSW MCR10:SOFTEN MCR10:HARDEN MCR11:FMEASIN FMEAS MCR10:FMONCLK LBxU, LBxL, BLxS, LBxD (x = 1 to 4) ILIMIT SRLIMIT T0 DPLL The state of the T0 DPLL (free-run, locked, holdover, etc.) is shown in the STATE field. The STATE, SRFAIL, and PHMON fields are buttons that represent latched status bits in the device. When the button is red, the corresponding latched status bit has been set in the DS3100. Pressing the button clears the latched status bit and changes the color of the button back to green. STATE indicates that the state of the T0 DPLL has changed since the last time the button was pressed. SRFAIL indicates the selected reference has failed since the last time the button was pressed. PHMON indicates the phase monitor limit (set by PMLIM) has been exceeded. The state of the T0 DPLL can be forced using the combo box to the left of the STATE field, and the selected reference can be forced using the CLK SEL field. Below the CLK SEL field is a field that configures the T0 DPLL for revertive or nonrevertive input reference switching. The frequency of the T0 DPLL is displayed in the FREQ field (fixed at 77.76MHz for the DS3100 T0 DPLL). The acquisition and locked bandwidths are set by the ABW and LBW fields, respectively, and the damping factor is set by the DAMP field. The acquisition bandwidth is only used if AUTOBW is checked. If the frequency of the T0 DPLL’s selected reference exceeds the SOFT LIMIT setting (in the DPLL FREQUENCY LIMITS box at the top of the window), the SOFTLIM LED turns red. The PALARM status LED and the PHASE MONITOR and BUILDOUT fields are advanced topics. See Table 4-2 and the DS3100 data sheet for more details. Clicking the More button opens another window (Figure 4-3) with additional T0 DPLL configuration and status fields. 10 of 38 DS3100DK Figure 4-3. Software T0 DPLL Window Table 4-2. Mapping Between T0 DPLL Software Fields and DS3100 Register Fields SOFTWARE FIELD MAIN WINDOW STATE combo box STATE status box CLK SEL Revertive/Nonrevertive FREQ ABW LBW DAMP STATE latched status SRFAIL PHMON PALARM SOFTLIM AUTOBW LIMINT PMLIM PMEN, PMPBEN PBOEN, PBOFRZ RECAL MANUAL PBO SUBWINDOW Fast Ready, Slow Ready Manual Holdover Holdover Type Mini HO Type HO Freq RDAVG FSMON AEFSEN, EFSEN INDEP OCN PHASE MONLIM DS3100 REGISTER FIELDS MCR1:T0STATE OPSTATE:T0STATE MCR2:T0FORCE MCR3:REVERT Fixed by T0 DPLL architecture T0ABW T0LBW T0CR2:DAMP MSR2:STATE MSR2:SRFAIL MSR3:PHMON TEST1:PALARM OPSTATE:T0SOFT MCR9:AUTOBW MCR9:LIMINT PHMON:PMLIM PHMON:PMEN, PMPBEN MCR10:PBOEN, PBOFRZ FSCR3:RECAL OFFSET1 and OFFSET2 MSR4:FHORDY, SHORDY MCR3:MANHO HOCR3:AVG, FAST HOCR3:MINIHO HOCR1, HOCR2, HOCR3[2:0] HOCR3:RDAVG OPSTATE:FSMON MCR3:AEFSEN, EFSEN FSCR2:INDEP FSCR2:OCN FSCR2:PHASE FSCR3:MONLIM 11 of 38 DS3100DK SOFTWARE FIELD SOURCE PD2 ENABLE PD2GA, PD2GD PD2GA8K APBO OFFSET 4.4 DS3100 REGISTER FIELDS FSCR3:SOURCE T0CR3:PD2EN T0CR3:PD2GA, PD2GD T0CR2:PD2GA8K PBOFF T4 DPLL The state of the T4 DPLL (locked or not locked) is shown in the STATE field. The LOCK and NO INPUT fields are buttons that represent latched status bits in the device. When the button is red, the corresponding latched status bit has been set in the DS3100. Pressing the button clears the latched status bit and changes the color of the button back to green. LOCK indicates the state of the T4 DPLL has changed since the last time the button was pressed. NO INPUT means the T4 DPLL has no valid inputs available. The selected reference for the T4 DPLL can be forced using the CLK SEL field. The frequency of the T4 DPLL is displayed in the FREQ field. When the FREQ field is changed, the frequency of the T4 option listed in the T4 APLL combo box automatically changes to match. If the T4 option in the T4 APLL box is currently selected, the frequencies of all the T4 options in the OC1–OC7 output clock combo boxes automatically change to frequencies derived from the new T4 APLL frequency. These changes match what happens inside the DS3100 device. The bandwidth of the T4 DPLL is set by the BW field, while the damping factor is set by the DAMP field. If the frequency of the T4 DPLL’s selected reference exceeds the SOFT LIMIT setting (in the DPLL FREQUENCY LIMITS box at the top of the window), the SOFTLIM LED turns red. Digital feedback (vs. analog feedback through the T4 APLL) can be selected using the DIGFB checkbox. The LKT4T0 and T4MT0 fields are advanced topics. See Table 4-3 and the DS3100 data sheet for more details. Clicking the More button opens another window (Figure 4-4) with additional T4 DPLL configuration and status fields. Figure 4-4. Software T4 DPLL Window 12 of 38 DS3100DK Table 4-3. Mapping Between T4 DPLL Software Fields and DS3100 Register Fields SOFTWARE FIELD MAIN WINDOW STATE CLK SEL FREQ BW DAMP LOCK NO INPUT SOFTLIM DIGFB LKT4T0 T4MT0 SUBWINDOW PD2 Enable PD2GA, PD2GD PD2GA8K 4.5 DS3100 REGISTER FIELDS OPSTATE:T4LOCK MCR4:T4FORCE T4CR1:T4FREQ T4BW T4CR2:DAMP MSR3:T4LOCK MSR3:T4NOIN OPSTATE:T4SOFT MCR4:T4DFB MCR4:LKT4T0 T0CR1:T4MT0 T4CR3:PD2EN T4CR3:PD2GA, PD2GD T4CR2:PD2GA8K T0 APLL The T0 APLL can be connected to the output of the T0 Output DFS or to the T0 Low-Frequency DFS (see the DS3100 data sheet for details). The non-77.76 options in the Input Freq field are all frequencies from the T0 LowFrequency DFS. The difference between the “77.76 Analog” and “77.76 Digital” options is whether the feedback path of the T0 DPLL includes the T0 feedback APLL. The APLL output frequency is always four times the input frequency. When the Input Freq field is changed, the Output Freq field changes to match, and all the T0 options in the OC1–OC7 output clock combo boxes also change to frequencies derived from the new T0 APLL frequency. These changes match what happens in the DS3104 device. Table 4-4. Mapping Between T0 APLL Software Fields and DS3100 Register Fields SOFTWARE FIELD DS3100 REGISTER FIELDS Input Freq T0CR1:T0FREQ Output Freq Derived by software from Input Freq 4.6 T4 APLL The T4 APLL can be connected to the output of the T4 DPLL or to the output of the T0 DPLL (specifically the T0 low-frequency DFS; see the DS3100 data sheet for details) as specified by the SRC DPLL field. When SRC DPLL is set to T4, the Input Freq field follows the T4 DPLL FREQ field. When SRC DPLL is set to T0, several frequency options from the T0 Low-Frequency DFS are available in the Input Freq field. When the FREQ field is changed in the T4 DPLL box, the frequency of the T4 option listed in the T4 APLL combo box automatically changes to match. If the T4 option in the T4 APLL box is currently selected, the frequencies of all the T4 options in the OC1–OC7 output clock combo boxes automatically change to frequencies derived from the new T4 APLL frequency. These changes match what happens in the DS3100 device. Similarly, if the T4 APLL option is changed, the frequencies of all the T4 options in the OC1–OC7 output clock combo boxes automatically change to frequencies derived from the new T4 APLL frequency. Table 4-5. Mapping Between T4 APLL Software Fields and DS3100 Register Fields SOFTWARE FIELD SRC DPLL Input Freq Output Freq DS3100 REGISTER FIELDS T0CR1:T4APT0 T0CR1:T0FT4 Derived by software from Input Freq 13 of 38 DS3100DK 4.7 Output Clocks The fields in this box configure the DS3100’s 11 output clocks. The 2K8K field specifies the source (T0 path or T4 path) for the 2kHz and 8kHz clock options for output clocks OC1–OC7. Similarly the DIG1 and DIG2 fields configure the Digital1 and Digital2 frequency options for OC1–OC7 (see the DS3100 data sheet for details). The OC1–OC7 fields specify the output frequencies for outputs OC1–OC7. Note that when the T0 APLL setting is changed, the frequencies of all the T0 options in the OC1–OC7 fields automatically change to frequencies derived from the new T0 APLL frequency. Similarly, when the T4 APLL setting is changed, the frequencies of all the T4 options in the OC1–OC7 fields automatically change to frequencies derived from the new T4 APLL frequency. These changes match what happens in the DS3100 device. The OC89 field specifies whether the T0 path or the T4 path is the source for output clocks OC8 and OC9. OC8 is the 64kHz composite clock output. The OC8 field configures the OC8 output clock for 50% or 5/8 duty cycle, and also for whether or not the output signal has 8kHz BPVs and optionally 400Hz absence-of-BPVs per ITU-T G.703 Appendix II options a) and b). The “8K” options in the list enable the 8kHz BPVs but not the 400Hz absence-ofBPVs. The “400” options enable both the 8kHz BPVs and the 400Hz absence-of-BPVs. OC9 is a dedicated 1.544MHz or 2.048MHz output. When OC89 specifies that OC8 and OC9 are sourced from the T4 path, the Auto Squelch checkbox specifies whether or not OC8 and OC9 are automatically squelched when T4 has no valid input references. When OC89 indicates T0 path, Auto Squelch is not available. OC10 is an 8kHz output that can be configured as a 50% duty cycle clock or a frame pulse and can optionally be inverted. OC11 is a 2kHz output that can be similarly configured. Table 4-6. Mapping Between Output Clock Software Fields and DS3100 Register Fields SOFTWARE FIELD 2K8K DIG1 DIG2 OC1–OC7 OC89 Auto Squelch OC8 OC9 OC10 OC11 DS3100 REGISTER FIELDS FSCR1:2K8KSRC MCR6:DIG1SS, MCR7:DIG1F MCR6:DIG2SS, MCR7:DIG2F, MCR7:DIG2AF OCR1–OCR4 MCR4:OC89 T4CR1:ASQUEL OCR4:OC8EN, T4CR1:OC8DUTY MCR8:OC8NO8, MCR8:OC8400 OCR4:OC9EN, T4CR1:OC9SON OCR4:OC10EN, FSCR1:8KPUL, FSCR1:8KINV OCR4:OC11EN, FSCR1:2KPUL, FSCR1:2KINV 14 of 38 DS3100DK 4.8 DPLL Frequency Limits, Phase Detectors, DPLL Lock Criteria The DPLL frequency limits specify the hard and soft limits of the DPLL frequency range. When the selected reference for a DPLL exceeds the soft limit, the SOFTLIM LED for that DPLL turns red but the selected reference is not disqualified. If the FLLOL (frequency limit loss of lock) box is checked in the DPLL Lock Criteria box, when the selected reference for a DPLL exceeds the hard limit the DPLL will lose lock (T4 transitions to Not Locked state, and T0 transitions to LOL state). The remaining fields are advanced topics. See Table 4-7 and the DS3100 data sheet for more details. Table 4-7. Mapping Between DPLL Software Fields and DS3100 Register Fields SOFTWARE FIELD MCPDEN USEMCPD D180 COURSELIM FINELIM FLEN CLEN FLLOL NALOL HARD LIMIT SOFT LIMIT 4.9 DS3100 REGISTER FIELDS PHLIM2:MCPDEN PHLIM2:USEMCPD TEST1:D180 PHLIM2:COARSELIM PHLIM1:FINELIM PHLIM1:FLEN PHLIM2:CLEN DLIMIT3:FLLOL PHLIM1:NALOL HARDLIM[9:0] in DLIMIT1 and DLIMIT2 DLIMIT3:SOFTLIM BITS Receivers and BITS Transmitters The Mode fields in these boxes set the basic line mode for each port: DS1 ESF, DS1 SF, E1, 2048kHz, and—for receivers only—6312kHz. The termination fields specify the line termination for the receiver or transmitter port. The DS3100 supports either internal termination (inside the device) or external termination (resistors on the board). As shipped from the factory the demo kit board does not have external termination resistors populated, and therefore only the internal termination options should be selected in the software. The input clock (IC1–IC14) to which each BITS receiver should be connected is specified in the Clock Dest fields. The output clock to which each BITS transmitter should be connected is specified in the Clock Source fields. In the BITS Transmitters box, when a transmitter is in DS1 ESF or E1 mode, the SSM value to be transmitted can be specified in the SSM fields below the TX1 and TX2 headings. In E1 mode, the Sa bit channel in which to transmit SSMs can be specified (for both transmitters) in the small combo box next to the SSM label. In the BITS Receivers box, when a receiver is in DS1 ESF or E1 mode, the received SSM values are displayed in the SSM fields below the RX1 and RX2 headings. In E1 mode, the Sa channel in which to look for incoming SSMs can be specified (for both receivers) in the small combo box next to the SSM label. The headings RX1, RX2, TX1, and TX2 are buttons that open secondary windows (Figure 4-5, Figure 4-6, and Figure 4-7) with additional configuration and status fields. 4.9.1 Note About Working with the BITS Receivers and Transmitters 1) When switching BITS transmitter or receiver modes, the termination should be changed to match: internal 100Ω for DS1, internal 75Ω or 120Ω for E1 and 2048kHz, internal 75Ω for 6312kHz. 2) When switching BITS transmitter modes between DS1 and E1/2048kHz modes, the rate of the transmit clock source (typically OC9) must be changed to match: 1.544MHz for DS1 and 2.048MHz for E1/2048kHz. 3) Enabling analog loopback between BITS transmitter 1 and BITS receiver 1 and between BITS transmitter 2 and BITS receiver 2 can be useful in evaluating the DS3100. During device initialization the DS3100DK software enables analog loopback for both BITS transmitter/receiver pairs by setting ALB = 1 (registers B1BLCR4 (address 93h) and B2BLCR4 (address 113h)). 15 of 38 DS3100DK Figure 4-5. Software BITS Receiver Window (DS1 Mode) Figure 4-6. Software BITS Receiver Window (E1 Mode) Figure 4-7. Software BITS Transmitter Window (DS1 Mode and E1 Mode) 16 of 38 DS3100DK Table 4-8. Mapping Between BITS Software Fields and DS3100 Register Fields SOFTWARE FIELD BITS RECEIVERS, MAIN WINDOW DS3100 REGISTER FIELDS BMCR:RMODE, BCCR3:MCLKFC, BRMMR, BRCR1:RB8ZS, BRCR1:RFM, BRCR3:RHDB3, BRCR3:RCRC4. See Mode APPENDIX 2: BITS MODE WRITE SEQUENCES for exact write sequences for each mode. Termination BLCR3:RION, BLCR3:RIMP Clock Dest BCCR2:RCLKD Left-Hand SSM Combo (E1 Only) BRMCR:SSMCH DS1 ESF: BTBOC:TBOC SSM Text Boxes E1: BRMSR, BRSSM:SSM ALB BLCR4:ALB ALOS BLIR1:LOS OOF, AIS, RAI BRIR1:OOF, AIS, RAI BITS RECEIVERS, DS1 AND E1 WINDOWS MCLK Source BCCR3:MCLKS RCLK Pin BCCR3:RCEN, RCINV ROUT Pin BCCR3:ROEN, ROINV, ROUTS RSER Pin BCCR3:RSEN FSync Dest BCCR2:RSYNCD Invalidate on X Zeros BCCR5:ZEROS Increment on BPVs BCCR5:BPV Invalidate on LOS BCCR5:LOS Invalidate on OOF BCCR5:OOF Invalidate on AIS BCCR5:AIS Reset Button BLCR1:LIRST LOS Criteria BLCR1:LCS Internal Termination BLCR3:RION Turns Ratio BLCR3:RTR Monitor Mode BLCR3:RMONEN Sensitivity (dB) BLCR3:RSMS Short Circuit BLIR1:SC ALOS BLIR1:LOS Over Equalized BLIR1:OEQ Under Equalized BLIR1:UEQ Signal Level (dB) BLIR2:RL BITS RECEIVERS, DS1 WINDOW ONLY B8ZS BRCR1:RB8ZS Japanese CRC-6 BRCR1:RJC Japanese RAI BRCR2:RSFRAI RAI Integration BRCR2:RAIIE Sync Time BRCR1:SYNCT Sync Criteria BRCR1:SYNCC Auto Resync BRCR1:ARC, SYNCD OOF Criteria BRCR2:OOFC Resync Now BRCR1:RESYNC BOC Rx Reset BRBCR:RBR BOC Filter BRBCR:RBF BOC Disint. BRBCR:RBD LOS BRSR1:LOS OOF BRSR1:OOF COFA BRSR2:COFA AIS BRSR1:AIS RAI BRSR1:RAI 17 of 38 DS3100DK SOFTWARE FIELD DS3100 REGISTER FIELDS PDV BRSR2:RPDV 8 Zeros Detected BRSR2:8ZD 16 Zeros Detected BRSR2:16ZD SEFE BRSR2:SEFE B8ZS Detected BRSR2:B8ZS Frame Bit Error BRSR2:FBE BITS RECEIVERS, E1 WINDOW ONLY HDB3 BRCR3:RHDB3 CRC-4 BRCR3:RCRC4 LOS Criteria BRCR4:RLOSC MF Sync BRCR5:RMFS Sync Criteria BRCR3:FRC Auto Resync BRCR3:SYNCD Resync Now BRCR3:RESYNC FAS OOF BRIR2:FASSA (LED), BRSR3:FASRC (latched status button) CAS OOF BRIR2:CASSA (LED), BRSR3:CASRC (latched status button) BRIR2:CRC4SA (LED), BRSR3:CRCRC (latched status CRC4 OOF button) SSM Filter BRMCR:SSMF SSM SaX Latched Status Button BRMSR:SaX SSM SaX Value BRSX4 BITS TRANSMITTERS, MAIN WINDOW BMCR:TMODE, BTMMR, BTCR1:TB8ZS, BTCR3:TFM, Mode BTCR4:THDB3, BTCR4:TCRC4, 60, 61. See APPENDIX 2: BITS MODE WRITE SEQUENCES for exact write sequences. Termination BLCR2:TION, BLCR2:TIMP Clock Source BCCR1:TCLKS Left-and SSM Combo (E1 Only) Indicates which of BTSa4–BTSa8 to use DS1 ESF: BRBOC:RBOC Main SSM Combos E1: BTSa4–BTSa8 BITS TRANSMITTERS, DS1 AND E1 WINDOWS TIN Pin BCCR4:TIINV TCLK Pin BCCR4:TCEN, TCINV TOUT Pin BCCR4:TOEN, TOINV, TOUTS MFS Source BCCR4:TMFS FSync Source BCCR1:TSYNCS Transmit AIS BLCR4:TAIS Line Build-Out BLCR2:LBO Open-Circuit BLIR1:OC Short-Circuit BLIR1:SC BITS TRANSMITTERS, DS1 WINDOW ONLY B8ZS BTCR1:TB8ZS Transmit RAI BTCR1:TRAI Japanese CRC-6 BTCR1:TJC Japanese RAI BTCR2:TSFRAI F-Bit Pass-Through BTCR1:TFPT CRC6 Pass-Through BTCR1:TCPT Pulse Density Enforce BTCR2:TPDE F-Bit Corruption 1 BTCR2:FBCT1 F-Bit Corruption 2 BTCR2:FBCT2 Insert BPV BTCR3:IBPV Loss of Tx Clock BTSR1:LOTC Pulse Density BTSR1:TPDV 18 of 38 DS3100DK SOFTWARE FIELD DS3100 REGISTER FIELDS BITS TRANSMITTERS, E1 WINDOW ONLY HDB3 BTCR4:THDB3 CRC-4 BTCR4:TCRC4 TS0 Pass-Through BTCR4:TFPT Si Pass-Through BTCR4:TSiS Insert BPV BTCR3:IBPV SiAF – Sa8 Checkbox BTOCR:SiAF – Sa8 SiAF – Sa8 Text Box BTSiAF – BTSa8 Loss of Tx Clock BTSR1:LOTC 4.10 Composite Clock Receivers The AMI and LOS fields are buttons that represent latched status bits in the device. When the button is red, the corresponding latched status bit has been set in the DS3100. Pressing the button clears the latched status bit and chnages the color of the button back to green. The AMI buttons indicate that a deviation from the expected oneBPV-in-eight pattern has occurred since that button was last pressed. The LOS buttons indicate no pulses were detected in the input signal in a 32μs period (i.e., after two missing pulses). Clicking the More button opens another window (Figure 4-8) with additional composite clock configuration and status fields. See Table 4-9 and the DS3100 data sheet for more details. Figure 4-8. Software CC Receiver Window Table 4-9. Mapping Between CC Software Fields and DS3100 Register Fields SOFTWARE FIELD MAIN WINDOW AMI LOS SUBWINDOW No 8kHz No 400Hz CCEDGE Increment on Bit Error Invalidate on AMI Invalidate on LOS 4.11 DS3100 REGISTER FIELDS MSR3:AMI1, AMI2 MSR3:LOS1, LOS2 MSR4:IC1NO8, IC2NO8 MSR4:IC1NO4, IC2NO4 MCR5:CCEDGE MCR5:BITERR MCR5:AMI MCR5:LOS REFCLK Calibration Any known frequency error in the local oscillator can be calibrated out inside the DS3100 by setting the ppm value in the REFCLK box. Also the significant edge of the REFCLK signal can be selected in XOEDGE field. Table 4-10. Mapping Between REFCLK Software Fields and DS3100 Register Fields SOFTWARE FIELD REFCLK slider/text box XOEDGE DS3100 REGISTER FIELDS MCLKFREQ[15:0] in MCLK1 and MCLK2 MCR3:XOEDGE 19 of 38 DS3100DK 4.12 Register View Window When the Register View button in the upper-right corner of the main window is pressed, the Register View window appears (Figure 4-9). In this window the DS3100’s entire register set can be viewed and manually written as needed. The large grid that takes up most of the window displays the DS3100 register map. For each register, its hexadecimal address in square brackets is followed by its register name and its contents in 2-digit hex format. The DS3100’s core register space is 00h to 7Fh, its BITS transceiver 1 register space is 80h to FFh, and its BITS transceiver 2 register space is 100h to 17Fh. To distinguish between BITS1 and BITS2 registers, all BITS1 register names start with “B1” and all BITS2 register names start with “B2.” When a register is clicked in the main register grid, its register description and fields are displayed at the bottom of the window. Due to the limited speed of the serial port, the demo kit software does not continually poll every register and does not make real-time updates to the data displayed on the Register View screen. Registers can be manually read as described below. The Register View window supports the following actions: • Read a register. Select the register in the register map. • Read a register field. Select the register in the map or the register field at the bottom of the window. • Read all registers. Press the Read All button. • Write a register. Double-click the register name in the register map and enter the value to be written. • Write a register field. Select the register, double-click the field, and enter the value to be written. • Write a multiregister field. Double-click one of the register names and enter the value for the field. Figure 4-9. Software Register View Window 20 of 38 DS3100DK 4.13 Configuration Scripts and Log File 4.13.1 Configuration Log File Every write command issued by the software to the DS3100DK board is logged in file DS3100DKLog.mfg located in the same directory as the software executable. This file can be viewed in Notepad by pressing the Log File button in the upper-right corner of the main window. Command line option "-l <filepath>" can be used to cause the software to write to a file other than DS3100DKLog.mfg. 4.13.2 Configuration Scripts All or part of the text in the Configuration Log File can be copied to a text file with a .mfg file extension for use as a configuration script. Configuration scripts are useful for quickly configuring the DS3100 without having to remember all the required settings. Two types of configuration scripts are possible: full and partial. A full configuration script can start with the DS3100 in its power-on default state and configure every aspect of the device to bring it to a desired state. To make a full configuration script, run the software, uncheck the Demo Mode checkbox, configure the device using the DK software fields, press the Log File button, and use File → Save As in Notepad to save a copy of the entire log file to a different file name. A partial configuration file only affects a subset of the DS3100 device settings. To make a partial configuration script, press the Log File button to view the Log File, press Ctrl-End to jump to the end of the file, and add to the end of the file a carriage return or comment line (starting with a semicolon) to delimit the start of the configuration. Save and exit the Log File. Next, configure the device using the DK software fields (including Register View writes as needed). Finally, view the log file again, jump to the end, and copy everything from the delimiter you made earlier to the end of the file into a new .mfg file. To run a configuration script, press the Config Script button in the upper-right corner of the main window. In the script window, type the path to the file or press the Browse button to navigate to the file. Note that the browser window does not display the files and folders on the Desktop other than My Documents and My Computer. These files and folders can be found under My Computer under c:\Documents and Settings\<username>\Desktop. Note that when the Demo Mode checkbox is unchecked, during the "Initializing the DS3100" step, the software runs configuration script startup.mfg located in the same directory as the software executable. Startup.mfg can be edited or replaced as needed to change the initial configuration of the device. 5. ADDITIONAL INFORMATION AND RESOURCES 5.1 DS3100 Information For more information about the DS3100, refer to the DS3100 data sheet at www.maxim-ic.com/DS3100. 5.2 DS3100DK Information For more information about the DS3100DK including software downloads, refer to the DS3100DK Quick View page at www.maxim-ic.com/DS3100DK. 5.3 Technical Support For additional technical support, go to www.maxim-ic.com/support. 21 of 38 DS3100DK 6. APPENDIX 1: HARDWARE COMPONENTS DESIGNATION QTY DESCRIPTION C1, C2, C3, C8, C42, C59–C138, C140, C142, C143, C145, C147, C149, C151, C155, C163–C166, C168, C169 99 0.1μF ±20%, 16V X7R ceramic capacitors (0603) AVX 0603YC104MAT C4, C5, C6, C27 4 Ceramic capacitors (0805) DO NOT POPULATE — — C6 1 470pF ±5%, 50V CGO ceramic capacitor (0805) AVX 08055A471JAT C7 1 68μF ±20%, 16V tantalum capacitor (D case) Panasonic ECS-T1CD686R C13, C14, C16, C41 4 4.7μF ±10%, 25V X5R ceramic capacitors (1206) Panasonic ECJ-3YB1E475K C17, C18, C20 3 6.8μF ±10%, 6.3V X5R ceramic capacitors (1206) Panasonic ECJ-3YB0J685K C28, C29 2 560pF ±5%, 50V NPO ceramic capacitor (0805) Panasonic ECJ-2VC1H561K C34–C38, C51–C58, C139, C141, C153, C154 17 10μF ±20%, 10V ceramic capacitors (1206) Panasonic ECJ-3YB1A106M C39, C40 2 22pF ±10%, 100V ceramic capacitors (1206) AVX Corp. 12061A220KAT2A C43 1 1μF ±10%, 16V ceramic capacitor (1206) Panasonic ECJ-3YB1C105K C48, C49 2 0.47μF ±10%, 16V ceramic capacitors (0805) Panasonic ECJ-2YB1C474K D1 1 1A, 50V general-purpose silicon diode D7 1 1A, 40V Schottky diode DS1–DS4 4 Green LEDs (SMD) Panasonic LN1351C DS5–DS10 6 Red LEDs (SMD) Panasonic LN1251C DS16 1 Green LED (SMD) Panasonic LN1351C J1, J2 2 6-pin socket strip (single row, vertical) Samtec SS-106-TT-2-N J3 1 2.1mm/5.5mm closed frame power jack, high current (right angle PCB, 24VDC at 5A) CUI Inc. PJ-002AH J6–J12, J20–J41 29 5-pin vertical SMB connectors (50Ω) AMP 413990-1 J13 1 Red socket (banana plug, horizontal) Mouser 164-6219 J14 1 5-pin vertical SMB connector (50Ω) DO NOT POPULATE AMP 413990-1 J15 1 10-pin terminal strip (dual row, vertical) Samtec TSW-105-07-T-D J19 1 Black horizontal banana plug socket Mouser 164-6218 J50 1 DB9 right-angle connector (long case) AMP 747459-1 J51 1 10-pin terminal strip (dual row, vertical) — — J54 1 USB Type B black connector (right angle) Molex 67068-0000 J55, J56, J85, J86, J89, J90, J117 7 Bantam jack connectors (right angle) Switchcraft RTT34B02 J57, J58, J83, J84 4 5-pin BNC connectors (50Ω, right angle) Trompeter CBJR220 22 of 38 SUPPLIER Vishay General Semiconductor International Rectifier PART 1N4001 10BQ040 DS3100DK DESIGNATION QTY JMP1–JMP5, JMP8, JMP9, JMP11, JMP12, JMP36, JMP37 11 2-pin vertical headers, 0.100" centers Samtec TSW-102-07-T-S JMP6, JMP7, JMP10, JMP62, JMP63 5 3-pin vertical headers, 0.100" centers Samtec TSW-103-07-T-S R1 1 10kΩ ±5%, 1/10W resistor (0805) Panasonic ERJ-6GEYJ103V 9 Resistors (0603) DO NOT POPULATE — — 25 10kΩ ±5%, 1/16W resistors (0603) Panasonic ERJ-3GEYJ103V 18 0Ω ±1%, 1/16W resistors (0603) AVX CJ10-000F 4 1.0kΩ ±5%, 1/16W resistors (0603) Panasonic ERJ-3GEYJ102V 5 470Ω ±5%, 1/16W resistors (0603) Panasonic ERJ-3GEYJ471V 1 33.2Ω ±1%, 1/16W resistors (0603) Panasonic ERJ-3EKF33R2V R2, R3, R6, R7, R9, R11, R16-R18 R4, R5, R8, R10, R12R14, R20, R25, R42, R46, R84, R91, R92, R95-R97, R110, R113, R115, R116, R120R123 R15, R22, R23, R24, R41, R43, R45, R47,R49, R51, R53, R55, R80, R81, R111, R112, R117, R118 R19, R21, R40, R44 R26, R27, R48, R50, R52 R28 DESCRIPTION SUPPLIER PART R29–R35, R59–R68 17 51.1Ω ±1%, 1/16W resistors (0603) Panasonic ERJ-3EKF51R1V R36–R39, R94, R108 6 330Ω ±5%, 1/16W resistors (0603) Panasonic ERJ-3GEYJ331V R54, R56, R57, R58, R74, R77, R89, R90 8 0Ω ±5%, 1/8W resistors (1206) Panasonic ERJ-8GEYJ0R00V R69, R72 R70, R93 R71, R73 R75, R76 R78 R79 R82, R83 2 2 2 2 1 1 2 Panasonic Panasonic Panasonic Panasonic Panasonic Panasonic Panasonic ERJ-6ENF1100V ERJ-6ENF10R0V ERJ-6ENF13R0V ERJ-6ENF90R9V ERJ-6ENF3570V ERJ-6ENF3010V ERJ-6GEY0R00V R85–R88 4 — — SW5 1 110Ω ±1%, 1/10W resistors (0805) 10.0Ω ±1%, 1/10W resistors (0805) 13.0Ω ±1%, 1/10W resistors (0805) 90.9Ω ±1%, 1/10W resistors (0805) 357Ω ±1%, 1/10W resistor (0805) 301Ω ±1%, 1/10W resistor (0805) 0.0Ω ±5%, 1/10W resistors (0805) Resistors (0805) DO NOT POPULATE 4-pin single-pole switch Panasonic EVQPAE04M SW6 SW7, SW8, SW9 1 3 2 T3 1 T4 1 Tyco Tyco Pulse Engineering Pulse Engineering Pulse Engineering SSA22 SSA12 T1, T2 6-pin, through-hole, DPDT slide switch 3-pin, through-hole, SPDT slide switches 16-pin SMT T1 transformers (1CT:1CT and 1CT:2CT, 1500V) 12-pin dual SMT transformer (64kbps, 1CT:2CT, 1500V) 64kbps interface transformer (1CT:1CT, 1500V, 6-pin DIP) TP1–TP10, TP18– TP42, TP49–TP61, TP65–TP84 68 1 plated hole test points DO NOT STUFF — — U1 1 High-frequency, surface-mount socket (1mm, 256-pin BGA) Ironwood Electronics SG-BGA-6017 U2, U3, U5, U7, U9–U26 22 TinyLogic ultra-high-speed 2-input OR gates (5-pin SOT23) Fairchild Semiconductor NC7SZ32M5 23 of 38 PE-68678 T7015 PE-65540 DS3100DK DESIGNATION QTY DESCRIPTION U4, U6 2 3.3V linear regulator (16-pin TSSOP-EP) Maxim MAX1793EUE-33 U8 1 1.8V linear regulator (16-pin TSSOP-EP) Maxim MAX1793EUE-18 U27 1 3-line to 8-line decoder/demultiplexer (16-pin SO ) Texas Instruments SN74HC138NSR U41 1 Dual RS-232 transmitter/receiver (16-pin, 300-mil SO) Maxim DS232AS U42 1 High-speed microcontroller (44-pin TQFP, 0°C to +70°C) Maxim DS87C520-ECL U44 1 Microprocessor voltage monitor (3.08V reset threshold) (4-pin SOT143) Maxim MAX811TEUS-T U45 1 Microprocessor voltage monitor (4.38V reset threshold) (4-pin SOT143) Maxim MAX812MEUS-T U46 1 Single-chip USB to UART bridge (28-pin QFN) Silicon Laboratories CP2101 Y1 1 3.3V, 12.8MHz OCXO (5-pin) through-hole DO NOT POPULATE Vectron MC853X4-035W Y2 1 Vectron C2260A1-0028 Y3 1 3.3V, 12.8MHz TCXO (4-pin SMD) 3.3V, 12.8MHz OCXO (4-pin SMD) DO NOT POPULATE Vectron C4400A1-0044 Y7 1 Low-profile 11.0592MHz crystal Pletronics LP49-33-11.0592M 24 of 38 SUPPLIER PART DS3100DK 7. APPENDIX 2: BITS MODE WRITE SEQUENCES BITS Transmitter BITS Receiver DS1 ESF address 04h, set TMODE[1:0]=00 address 21h, write 02h address 21h, write 00h address 27h, write 0Ch address 29h, write 00h address 21h, write 80h address 21h, write C0h DS1 ESF address 04h, set RMODE[1:0]=00 address 0Ah, write 40h address 20h, write 02h address 20h, write 00h address 22h, write 40h address 20h, write 80h address 20h, write C0h DS1 SF/D4 address 04h, set TMODE[1:0]=00 address 21h, write 02h address 21h, write 00h address 27h, write 0Ch address 29h, write 04h address 21h, write 80h address 21h, write C0h DS1 SF/D4 address 04h, set RMODE[1:0]=00 address 0Ah, write 40h address 20h, write 02h address 20h, write 00h address 22h, write 60h address 20h, write 80h address 20h, write C0h E1 address 04h, set TMODE[1:0]=01 address 21h, write 02h address 21h, write 00h address 29h, write 00h address 2Ah, write 05h address 21h, write 81h address 21h, write C1h address 60h, write 1Bh address 61h, write 40h E1 address 04h, set RMODE[1:0]=01 address 20h, write 02h address 20h, write 00h address 24h, write 68h address 20h, write 81h address 20h, write C1h 2048 kHz address 04h, set RMODE[1:0]=10 address 20h, write 02h address 20h, write 00h 2048kHz address 04h, set TMODE[1:0]=10 address 21h, write 02h address 21h, write 00h 8. 6312 kHz address 04h, set RMODE[1:0]=11 address 20h, write 02h address 20h, write 00h SCHEMATICS The DS3100DK schematics are featured in the following 13 pages. 9. DOCUMENT REVISION HISTORY REVISION DATE 091806 110206 040507 052307 071807 DESCRIPTION Initial DS3100DK data sheet release. Updated document to describe software v0.7 features: (page 1) Features section; (page 6) Section 3.1; (page 14) Section 4.12; (page 15) added Section 4.13, 4.13.1, 4.13.2; updated table captions. Updated document for sentence clarification (pages 6, 7, 13, and 14). Updated document to describe changes and new features of software revision 0.8; added USB support. Added screen shots of the software windows and updated document to describe new features of software revision 1.0. 25 of 38 Maxim/Dallas Semiconductor cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim/Dallas Semiconductor product. No circuit patent licenses are implied. Maxim/Dallas Semiconductor reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2007 Maxim Integrated Products The Maxim logo is a registered trademark of Maxim Integrated Products, Inc. The Dallas logo is a registered trademark of Dallas Semiconductor Corporation. R82 R8 2 R10 10K 1 A INTEL MUX VCC 2 1 DNP B R7 8 1 7 A<3> A<4> A<5> A<6> H14 G15 F16 G14 A<8> A<2> G16 A<7> A<1> H15 F15 A<0> H16 A8 E16 2 SYNC2K SYNC2K B14 R99 0.0 IC14 IC13 IC12 IC11 IC10 IC9 IC8 IC7 IC6NEG IC6POS IC5NEG IC5POS IC4 IC3 IC2A IC2 JTCLK JTDI RST* JTRST* REFCLK IC1A JTDO IFSEL<0> IC1 GPIO1 IFSEL<1> RESREF JTRST JTCLK JTDI JTMS JTDO IC1 A10 IC1A P6 IC2 B10 IC2A P7 IC3 C10 IC4 A11 IC5POS B5 IC5NEG A5 IC6POS B4 IC6NEG A4 IC7 B11 IC8 C11 IC9 A12 IC10B12 IC11 A13 IC12C12 IC13B13 IC14A14 TP28 GPIO2 IFSEL<2> RESREF 2 6 U1 NA CONTROL DS3100_U1 SONSDH 10K GPIO3 MASTSLV 0.0 R80 SRCSW 1 TST_RB1 WR_RW* GPIO1 GPIO2 GPIO3 GPIO4 GPIO4 TP29 TP32 TP36 TP38 TP40 TP42 TP31 TP34 TP37 TP39 TP41 TP61 TST_RB2 RD_DS* R1 TM1 SRFAIL 5 TST_RC1 RDY* 6 5 TST_TA1 7 TST_TA2 NC1 R13 1 TM1 2 R81 0.0 T15 1 TM2 2 TM2 WDT C 2 1 TST_TB1 NC2 D 8 R9 DNP IFSEL0 2 1 R12 IFSEL11 10K 2 R83 DNP IFSEL2 2 1 AD6 1 DNP AD7 1 DNP 2 2 2 2 1 R84 10K R91 DNP R92 DNP 1 C8 B8 A9 B9 C9 OC8POS OC8NEG OC9 OC10 OC11 D14 C14 AD<7>_CPOL TP1 TP2 TP3 TP4 TP5 E14 AD<5> AD<6>_CPHA C15 C1 OC7NEG D15 C2 OC7POS AD<4> A3 OC6NEG AD<3> B3 OC6POS C16 A8 OC5 AD<2>_SCLK C7 OC4 AD<1>_SDI B7 OC3 D16 A7 OC2 E15 C6 OC1 4 4 AD<0>_SDO TST_TC1 T7 T8 R8 R9 T9 P9 JTMS HIZ* REFCLKH1 PORNOTB6 HIZ 1 R14 TST_RA1 ALE TST_TC2 E2 F3 H2 J1 IFSEL0 N1 IFSEL1N2 IFSEL2 P1 TST_RA2 CS* AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 OC1 OC2 OC3 OC4 OC5 OC6POS OC6NEG OC7POS OC7NEG OC8POS OC8NEG OC9 OC10 OC11 1 2 R98 DNP 3 3 ENGINEER: TITLE: JML 2 VCC DS10 RED 2 DS3100DK01C0 MASTSLV SRCSW SONSDH R94 INTREQ 2 1 1 R6 1 L14 1 T6 1 K16 1 R7 1 K15 1 TST_RC2 INTREQ MASTSLV R11 SONSDHM3 SRCSW M2 SRFAILJ2 WDT C5 ALE K14 CS_3100 J16 WR J15 RD J14 RDY 1 B15 INTREQ 1 A15 TST_TB2 NC3 2 2 2 3 3 3 VCC 1 PAGE: DATE: 1 1 OF 13 110705 Mon Jul 16 11:12:10 2007 SPDT SW9 1 SPDT SW8 1 SPDT SW7 1 WDT R97 C8 P2 1 R15 1 N3 1 P13 1 P3 1 P14 1 NC1 1 P12 NC2 1 C13 NC3 1 F14 10K R96 2 10K R95 330 2 2 1 1 10K .1UF 2 1 1 2 A B C D A B C I30 TP10 8 I31 TP18 R12 RSER RSER2T11 TSER P11 TIN T13 T12 TOUT ROUT T14 P16 TRINGB THZE P15 TRINGA N16 N15 TCLK 7 TTIPA TTIPB RCLK MCLK RRING RRING2 L15 PORT L3 MCLK2T10 RCLK2R10 ROUT2P10 RTIP RTIP2L16 DS3100_U1 U1 NA L1 TIN TSER RSER RSER1 J3 L2 M1 TOUT ROUT K3 TCLK RCLK T2 THZE R2 TRINGB T3 TRINGA R3 TTIPA TTIPB MCLK RRING RRING1 R5 PORT DS3100_U1 MCLK1 F2 RCLK1 K1 ROUT1 K2 RTIP RTIP1 T5 U1 1 TTIPA1 TTIPA1 TRINGA1 TRINGA1 TP6 THZE1 TP8 TCLK1 TOUT1 TIN1 TSER1 6 TTIPA2 TTIPA2 TRINGA2 TRINGA2 I14 THZE2 TP7 I15 TP9 TCLK2 TOUT2 TIN2 TSER2 RCLK2 TIN2 ROUT2 RSER2 TSER2 RCLK1 TIN1 ROUT1 RSER1 TSER1 6 5 4 3 2 1 J1 6 5 4 3 2 1 J2 5 CONN_6P_U 6 5 4 3 2 1 NA CONN_6P_U 6 5 4 3 2 1 B16 D7 D10 E7 E8 E9 E10 G4 G5 G12 G13 H5 H12 J5 J12 K4 K5 K12 K13 M7 M8 M9 M10 N7 N10 R1 R16 DUT33 B1 VDDIO1 VDDIO2 VDDIO3 VDDIO4 VDDIO5 VDDIO6 VDDIO7 VDDIO8 VDDIO9 VDDIO10 VDDIO11 VDDIO12 VDDIO13 VDDIO14 VDDIO15 VDDIO16 VDDIO17 VDDIO18 VDDIO19 VDDIO20 VDDIO21 VDDIO22 VDDIO23 VDDIO24 VDDIO25 VDDIO26 VDDIO27 VDDIO28 4 DUT18 RVSS_P1 RVSS_P2 TVSS_P1 TVSS_P2 NA 4 VSS_ICDIFF VSS_OC6 VSS_OC7 D 5 DVSS 3 DUT33 2 PWR & GND U1 DS3100_U1 NA VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 3 ENGINEER: TITLE: JML 2 DS3100DK01C0 GND PAGE: DATE: 1 2 OF 13 110705 Mon Jul 16 11:14:08 2007 A1 A16 D4 D5 D12 D13 E4 E5 E12 E13 F6 F7 F8 F9 F10 F11 G6 G7 G8 G9 G10 G11 H6 H7 H8 H9 H10 H11 1 1 2 6 DVDD 1 2 7 R13 R14 AVDD_PLL1 AVDD_PLL2 AVDD_PLL3 AVDD_PLL4 C163.1UF 1 8 2 1 2 1 1 1 1 1 R15 VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8 VDD9 VDD10 VDD11 VDD12 VDD13 VDD14 VDD15 VDD16 VDD17 VDD18 VDD19 VDD20 VDD21 VDD22 VDD23 VDD24 AVSS_PLL1 AVSS_PLL2 AVSS_PLL3 AVSS_PLL4 10K 1 10K RVDD_P1 RVDD_P2 TVDD_P1 TVDD_P2 C164.1UF 1 2 AVDD_PLL1 AVDD_PLL2 AVDD_PLL3 AVDD_PLL4 0.0 0.0 0.0 0.0 1 R22 1 R23 1 R24 1 D6 D8 D9 D11 E6 E11 F4 F5 F12 F13 H4 H13 J4 J13 L4 L5 L12 L13 M6 M11 N6 N8 N9 N11 D1 E1 F1 G1 H3 T4 M15 R4 M16 A6 B2 C3 VDD_ICDIFF VDD_OC6 VDD_OC7 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52 VSS53 VSS54 VSS55 VSS56 D2 E3 G2 G3 P5 M14 P4 N14 C4 A2 D3 P8 J6 J7 J8 J9 J10 J11 K6 K7 K8 K9 K10 K11 L6 L7 L8 L9 L10 L11 M4 M5 M12 M13 N4 N5 N12 N13 T1 T16 C165.1UF AVDD_PLL1 AVDD_PLL2 AVDD_PLL3 AVDD_PLL4 C166.1UF 2 A B C D A B C D 8 INPUT CLOCKS DNP R101 DNP 1R100 OSC331 2 2 VCCD VOSC VCC VREF FOUT 7 J14 DS4026_U GNDD GNDOSC GND SCL SDA U29 GNDA 14 RF_OUT 12.8MHZ GND VCC OSC_OCXO EFC 3 4 8 14 1 16 4 3 2 15 1 1 1 1 OSC33 12.8MHZ_3.3V RF_OUT Y3 GND VS OSC_TCXO VC 1 5 12.8MHZ_3.3V Y2 1 5 RF_OUT OSC_MC853X4 GND 11 13 12 7 1 2 1 2 SUPPLY_V .1UF Y1 DNP DNP R18 R102 DNP R11 33.2 R28 DNP R17 ALL SIGNAL TRACKS ARE 50 OHM WITH RESPECT TO PLANE 12.8MHZ_3.3V 7 1 2 1 2 2 6 2 2 2 6 REFCLK 5 5 J12 J11 J10 J9 J8 J7 J6 4 1 1 1 1 1 1 1 4 3 3 ENGINEER: TITLE: JML 2 DS3100DK01C0 2 51.1 51.1 8 1 C1 C2 C3 R16 2 1 .1UF .1UF 1 1 2 2 1 1 C12DNP 2 C11DNP 2 DNP 1 C15DNP 2 1 C19DNP 2 C21DNP 2 R29 R30 R31 R32 R33 R34 R35 2 1 2 1 2 1 2 1 2 1 51.1 51.1 51.1 51.1 51.1 2 1 2 1 PAGE: DATE: 1 3 OF 13 110705 Wed May 10 13:21:45 2006 IC9 IC8 IC7 IC4 IC3 IC2 IC1 1 A B C D A B C D 7 8 INPUT CLOCKS J33 J32 J31 J30 J29 J28 1 1 1 1 1 1 7 ALL SIGNAL TRACKS ARE 50 OHM WITH RESPECT TO PLANE 8 6 6 GND 51.1 51.1 2 1 2 1 R59 R60 R61 R62 R63 R64 5 SYNC2K IC14 IC13 IC12 IC11 IC10 5 4 J37 J36 J35 J34 4 TP49 1 3 ENGINEER: JML 2 DS3100DK01C0 TP55 TP56 TITLE: PLACE TESTPOINTS ON 100 MIL CENTER TP53 TP54 2 TP51 TP52 1 1 1 PLACE TESTPOINTS ON 100 MIL CENTER 3 1 1 2 1 2 1 51.1 51.1 51.1 51.1 2 1 2 1 TP50 1 1 1 1 1 1 R65 R66 R67 R68 2 2 1 1 1 51.1 51.1 1 51.1 NA IC6POS IC6NEG 2 JMP37 NA IC5NEG 2 JMP36 IC5POS 1 PAGE: DATE: 1 4 OF 13 110705 Mon Jul 16 11:05:37 2007 51.1 2 2 1 1 A B C D A B C D 1 1 1 1 1 1 8 OUTPUT CLOCKS OC9 OC5 OC4 OC3 OC2 OC1 8 0.0 R51 0.0 R49 0.0 R47 0.0 R45 0.0 R43 0.0 R41 B A NA NA C U9 4 B A NA C B A NA C U11 4 4 B A NA C B A NA C 4 U13 4 B A NA C B A NA C 4 U15 4 B A NA C B A NA C 4 U17 4 B A NA C B A NA C 4 U19 4 B A C NC7SZ32 2 1 4 NC7SZ32 U20 2 2 1 NC7SZ32 2 1 NC7SZ32 U18 2 2 1 NC7SZ32 2 1 NC7SZ32 U16 2 2 1 NC7SZ32 2 1 NC7SZ32 U14 2 2 1 NC7SZ32 2 1 NC7SZ32 U12 2 2 1 NC7SZ32 2 1 NC7SZ32 U10 2 2 1 7 7 6 6 1 1 1 1 1 1 J25 J24 J23 J22 J21 J20 5 50 OHM VERT 50 OHM VERT 50 OHM VERT 50 OHM VERT 50 OHM VERT 50 OHM VERT 5 1 1 0.0 R55 0.0 R53 I114 TP60 I113 TP59 I116 TP58 I115 TP57 B A C NA NA C 4 B A C NA C NC7SZ32 2 1 B A 4 U23 4 4 NC7SZ32 U24 2 2 1 NC7SZ32 2 1 B A NA U21 NC7SZ32 U22 2 2 1 3 4 3 ENGINEER: TITLE: 2 JML 2 DS3100DK01C0 PLACE TESTPOINTS ON 100 MIL CENTER OC7NEG OC7POS OC6NEG OC6POS OC11 OC10 4 1 1 1 1 1 1 1 1 1 1 50 OHM VERT 50 OHM VERT PAGE: DATE: 1 5 OF 13 092205 Thu Oct 13 10:14:03 2005 I111 J39 I109 J38 I107 J41 I105 J40 J27 J26 1 A B C D A B C GPIO 8 7 7 2 R19 R20 GPIO1 JMP1 I20 11 I36 R21 2 2 1 GPIO2 VCC 1.0K 2 1 B A C I19 U3 6 VCC B A I35 C U7 6 NC7SZ32 2 1 NC7SZ32 10K 1.0K 10K 2 11 JMP2 R25 4 4 R26470 R27470 2 2 1 2 11 2 2 11 2 DS6 I31 RED DS5 I15 RED 5 5 2 R40 I8 GPIO3 2 2 1 D 8 GPIO4 I24 VCC B A C I9 U2 VCC B A 4 I25 C 4 U25 NC7SZ32 2 1 NC7SZ32 2 1 4 DS8 I27 RED DS7 I11 RED 4 3 I5 JMP5 2 1 3 2 1 B A C I1 ENGINEER: 4 U26 DS9 I4 RED 2 JML 2 DS3100DK01C0 NC7SZ32 TITLE: SRFAIL R52470 11 JMP3 R42 R44 1.0K 10K 1.0K 10K 2 JMP4 R46 R48470 R50470 11 2 2 1 2 11 2 2 11 2 2 11 2 PAGE: DATE: 1 6 OF 13 092205 Thu Oct 13 10:14:03 2005 1 A B C D A B C D 8 BITS TRANSCEIVER 8 2 5 T R 2 5 T R 7 1 CONN_BANTAM J58 J56 1 CONN_BANTAM J57 J55 7 2 2 6 3 1:1 14 1 2 15 16 T2 3 1:1 14 1 2 15 16 T1 6 R85 R86 R87 R88 2 2 1 1 2 2 2 DNP C26 DNP DNP C27 DNP DNP DNP 1 2 1 RRING2 1 RTIP2 RRING1 1 RTIP1 5 5 4 1 1 TRINGA2 TTIPA2 TRINGA1 TTIPA1 4 0.0 R90 0.0 R89 2 2 3 3 ENGINEER: TITLE: R 5 JML J85 R 5 J86 2 1 1 PAGE: DATE: 1 7 OF 13 110705 Mon Jul 16 11:06:10 2007 CONN_BANTAM J84 T 2 1 CONN_BANTAM J83 T 2 DS3100DK01C0 9 8 11 10 1:2 T2 7 6 9 8 11 10 1:2 T1 7 6 2 2 2 1 2 1 JMP11 2 1 JMP12 2 1 560PF 2 C28 C29 560PF A B C D A B C 5 R J90 2 5 R C9 330PF T NA CONN_BANTAM COMPOSITE CLOCK 8 2 T C10 330PF CONN_BANTAM J89 7 10 11 12 7 8 9 NA 2:1 T3 NA 2:1 T3 3 1 6 4 1 1 1 0.0 R56 0.0 R54 0.0 R58 0.0 2 2 2 24 6 2 2 1 1 IC1A NA JMP6 3 1 IC2A JMP7 3 .47UF C49 1 NA .47UF C48 5 OC8POS C4 OC8NEG C5 2 4 4 1 1 1 1 R770.0 R76 90.9 90.9 R75 0.0 R74 2 2 2 2 R78 R57 5 DNP DNP NA 1 6 1 2 7 2 1 1 1 1 3 R79 3 301 ENGINEER: TITLE: 2 JMP9 NA JMP103 NA 2 JMP8 NA 357 D 8 1 2 1 2 R72 R93 R73 R69 R70 R71 2 21 2 1 1 2 2.4 4.7 24 2.4 4.7 21 2 1 1 2 2 2 1 2 1 2 2 1 .01UF C6 1 1:1 4 6 JML 2 DS3100DK01C0 3 2 1:1 T4 2 R 5 J117 PAGE: DATE: 1 8 OF 13 110705 Wed May 10 13:21:43 2006 CONN_BANTAM T 2 NA 1 A B C D A B C 8 1 T2IN T1IN R2IN R1IN C1NEG TXD0 J H G F E D C B A J50 10UF C38 1 TX232 5 4 TX232 3 RX232 2 1 7 CONN_DB9P 9 8 7 6 7 14 9 12 5 4 2 15 16 V5_0 RXD0 JMP633 USB_RXD 1 T2OUT T1OUT R2OUT R1OUT C2NEG C2POS GND VNEG C1POS VCC VPOS U41 DS232A JMP62 USB_TXD 3 10 11 8 13 3 1 1 10UF RX232 2 C37 10UF 12 10UF 2 C36 16 2 C35 2 1 C34 2 RS232 2 D 6 6 SCS AD2 AD1 C 14 330 AD3 AD4 P2_1 P2_0 P1_3 P1_4 P1_5 P1_6 P1_7 RST P3_0 P3_1 P3_2 P3_3 P3_4 P3_5 P3_6 P3_7 XTAL1 XTAL2 GND<2-0> 44 1 2 3 4 5 7 8 9 10 11 12 13 14 11.0592MHZ 15 1 Y7 2 WR RD RXD0 TXD0 INTREQ 5 18 19 20 21 22 23 24 25 26 27 29 30 31 32 33 34 35 36 37 38 4 DS87C520_TQFP P2_2 P2_3 P2_4 P2_5 P2_6 P2_7 PSEN ALE EA AD7 AD6 AD5 AD2 AD1 AD0 P1_2 VCC 43 POR 1 DS16 2 42 2 GREEN P1_1 U42 NC7SZ32 B A R108 41 0.0 2 0.0 2 0.0 2 1 2 NA U5 4 P1_0 1R2 1R3 1R4 5 40 22PF 7 1 C39 2 1 2 8 22PF C40 A8 A12 ALE AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 V5_0 VCC 2 1 10UF R110 10K 3 3 ENGINEER: TITLE: 5 SLAVE CS_3100 5 2 4 6 3 2 A12 1 V5_0 2 R5 DNP 2 R6 0.0 JML 6 5 9 10 8 4 3 7 2 1 NA J15 10 8 6 4 2 SW6 DPDT NA Y7* Y6* Y5* Y4* Y3* Y2* Y1* Y0* 4 6 3 1 CSS CSM CSM SLAVE CSS 7 9 10 11 12 13 14 15 1 PAGE: DATE: 1 9 OF 13 092205 Thu Oct 13 10:14:03 2005 74AHC138 G2A* G1 C B A G2B* U27 CONN_10P 2 DS3100DK01C0 SCS 1 GND 1 9 7 (SCLK) AD2 1 (SDIO) AD1 3 SLAVE 5 2 A B C D A B 8 4 3 1 2 I42 SW5 3 1 9 7 5 3 1 8 MR* GND 7 10 8 6 4 2 CONN_10P 10 7 9 6 4 3 5 2 1 RESET* VCC U44 MAX811_U I40 3.08V JTCLK JTDO JTMS JTRST JTDI 2 4 1 0.0 R111 VCC 2 3 GND MR* 6 PORNOT 1 RESET VCC U45 MAX812_U I37 4.38V 2 4 1 5 0.0 R112 V5_0 2 POR VDD DATDAT+ GND SH J54 USB C 1 2 3 4 1 C41 10K 2 2 1 4 .1UF C43 NA 5 J51 1 2 10K VCC 12 11 7 9 8 4 5 SUSPEND_HIGH ENGINEER: TITLE: 3 U46 NA CP2101_U1 SUSPEND_LOW* REGIN RST* VBUS USBDP USBDM 21 22 NC11 18 NC7 NC10 21 RI* 19 11 DCD* 20 2 27 1 DSR* NC9 2 28 1 DTR* NC8 2 23 1 CTS* JML 2 2 24 1 RTS* 2 25 1 RXD R117 0.0 2 R118 0.0 26 1 TXD 2 DS3100DK01C0 GND 2 10K 3 NC1 3 2 1 4 NC2 R113 5 2 1 6 VDD NC3 1 6 NC4 7 NC5 D 8 NC6 10 13 14 15 16 17 TP84 TP83 NA R121 10K R122 10K R123 10K R120 10K USB_RXD USB_TXD 1 PAGE: DATE: 1 10 OF 13 092205 Thu Oct 13 10:14:03 2005 NA 1UF R116 4.7UF C42 R115 A B C D A B C 8 7 7 B A 1 2 B A C 41 U28 NA DUT331 OSC331 1 6 330 R39 330 R38 330 R37 330 R36 V5_0 1 2 1 DS4 2 1 DS3 2 1 DS2 2 1 DS1 V5_0 1 2 CONN_BANANA_2P J19 1 2 2.1MM/5.5MM J3 NC7SZ32 2 DUT18 1 B A CONN_BANANA_2P J13 1 V5_0 2 2 2 2 C7 2 68UF 2 5 5 4 4 1 2 6 V5_0 V5_0 V5_0 IN2 IN3 IN4 SHDN* 3 4 5 7 10 GND IN2 IN3 IN4 SHDN* 3 4 5 7 11 10 SET GND 15 6 RST* 14 13 12 OUT4 OUT3 OUT2 OUT1 IN2 IN3 IN4 3 4 5 GND SET RST* OUT4 OUT3 OUT2 OUT1 10 11 6 15 14 13 12 3 ENGINEER: TITLE: MAX1793_U2 SHDN* IN1 2 MAX1793_U2 U8 IN1 2 7 11 6 RST* SET 15 14 13 12 OUT4 OUT3 OUT2 OUT1 MAX1793_U2 U6 IN1 2 U4 3 1 2 D 8 C13 C14 C16 4.7UF 4.7UF 4.7UF 1 2 1 2 C17 C18 C20 1 1 1 2 DUT33 VCC 2 DUT18 JML 2 DS3100DK01C0 2 JMP15 NA 1 AMP D7 JMP14 OSC33 2 NA JMP13 6.8UF 6.8UF 6.8UF 1 2 1 2 1 2 D1 PAGE: DATE: 1 11 OF 13 110705 Wed May 10 13:21:47 2006 1 A B C D A B C52 C51 8 1 2 VCC VCC 1 10UF C60 1 GND DUT18 2 10UF C56 2 2 2 1 2 I112I111 I113 TP65 2 1 .1UF C71 1 2 1 2 1 7 7 I96 I97 I92 I91 I99 I98 TP68TP69 .1UF C79 2 1 .1UF C83 1 2 1 .1UF C87 1 2 1 .1UF C91 1 2 1 .1UF C95 1 2 1 .1UF C99 1 2 1 6 2 1 6 I79 I78 I77 I76 I90 TP74 .1UF C103 1 .1UF C107 1 2 1 .1UF C111 1 2 1 C115 .1UF 1 2 1 .1UF C119 1 2 1 2 1 .1UF C127 1 2 1 .1UF C131 1 2 5 5 I69 I70 I60 I71 TP79 .1UF C123 1 1 .1UF 1 .1UF C67 1 1 .1UF C75 1 1 1 1 1 1 1 1 2 1 10UF C59 .1UF C63 1 1 .1UF C72 2 1 .1UF C80 1 .1UF C84 2 1 .1UF C92 2 1 .1UF C100 1 .1UF C104 2 1 .1UF C112 2 1 .1UF C120 1 .1UF C124 2 1 .1UF C132 2 1 .1UF 1 10UF C55 2 2 .1UF C64 1 2 1 2 2 1 2 1 2 2 1 2 1 2 2 1 2 1 .1UF C136 C137 .1UF VCC DUT33 1 1 10UF C61 1 .1UF C65 2 .1UF C68 1 .1UF C73 2 .1UF C76 1 .1UF C81 1 .1UF C85 2 .1UF C88 1 .1UF C93 2 .1UF C96 1 .1UF C101 1 .1UF C105 2 .1UF C108 1 .1UF C113 2 .1UF C116 1 .1UF C121 1 .1UF C125 2 .1UF C128 1 2 C C53 2 10UF C57 2 2 1 2 1 2 2 1 2 1 2 2 1 2 1 2 2 1 2 .1UF C133 1 2 .1UF 8 1 1 10UF C62 1 .1UF C66 .1UF C69 1 .1UF C74 .1UF C77 1 .1UF C82 1 .1UF C86 .1UF C89 1 .1UF C94 .1UF C97 1 .1UF C102 1 .1UF C106 .1UF C109 1 .1UF C114 .1UF C117 1 .1UF C122 1 .1UF C126 .1UF C129 1 .1UF C134 2 C138 .1UF D C54 2 10UF C58 2 2 2 .1UF C70 2 2 .1UF C78 2 2 2 .1UF C90 2 2 .1UF C98 2 2 2 .1UF C110 2 2 .1UF C118 2 2 2 .1UF C130 2 1 2 TP67TP66 TP73TP72TP71TP70 TP78TP77TP76TP75 TP82TP81TP80 1 .1UF C135 1 2 1 .1UF 4 4 C153 2 C139 1 2 1 OSC33 10UF C141 2 1 V5_0 1 V5_0 10UF C154 2 10UF C155 2 10UF C143 1 2 .1UF C168 2 1 .1UF C145 1 2 1 .1UF C147 3 ENGINEER: TITLE: 1 3 .1UF C169 2 2 .1UF 1 .1UF C149 2 1 .1UF C151 2 1 JML 1 1 .1UF 2 2 DS3100DK01C0 .1UF C140 2 .1UF C142 2 PAGE: DATE: 1 12 OF 13 092205 Thu Oct 13 10:14:03 2005 1 A B C D A B C D 8 8 7 - 03 04 05 A0 B0 - - 02 C0 - 01 071607 050206 012106 011306 010406 112105 111905 110705 REVISION HISTORY - 7 - - - - - - - - 6 6 4 3 2 5 4 FIXED RXD,TXD CONNECTION TO CP2101 GENERAL CLEAN-UP ADDED BUFFER TO 1.8V LED ADDED 0 OHM RESISTORS AT SDIO,SCLK,SCS ADDED INTEL BUS CONNECTIONS MADE INTEL MUX MODE DEFAULT ADDED 330PF CAPS AT COMPOSITE CLOCK INPUT FIXED COMPOSITE CLOCK TERMINATION RES CHANGED 138 TO AHC FROM HC MOVED UP OK LED TO P1.1 AND REVERSED LOGIC CHANGED CAP ON COMPOSITE CLOCK TX TO .01UF ADDED SHORTED JUMPERS AT REGULATORS FOR ACCESS MOVED CSM TO 1000 AND CSS TO 0 ADDED DS4026 TCXO AND SUPPORTING COMPONENTS RELEASE TO FAB 3 ENGINEER: TITLE: JML 2 DS3100DK01C0 REMOVED 5V CAPS, LEDS AND SWITCHES FROM MICRO, LOW Z TP FROM ICN CHANGED REF DESIGNATORS TO MATCH EE MOVED MEMORY MAP,OTHER MISCELLANEOUS FIX TRANSFORMER ISSUES,ADDED POWER JACK,FIXED CSM/CSS LOGIC,ADDED TPS RELEASE FOR REVIEW 5 PAGE: DATE: 1 13 OF 13 092205 Thu Oct 13 10:14:03 2005 1 A B C D