ZL40213 Precision 1:2 LVDS Fanout Buffer with On-Chip Input Termination Data Sheet November 2012 Ordering Information Features ZL40213LDG1 ZL40213LDF1 Inputs/Outputs • Accepts differential or single-ended input • LVPECL, LVDS, CML, HCSL, LVCMOS • On-chip input termination resistors and biasing for AC coupled inputs • Two precision LVDS outputs • Operating frequency up to 750 MHz 16 Pin QFN 16 Pin QFN Trays Tape and Reel Matte Tin Package size: 3 x 3 mm -40oC to +85oC Applications • General purpose clock distribution Power • Low jitter clock trees • Options for 2.5 V or 3.3 V power supply • Logic translation • Current consumption of 44 mA • Clock and data signal restoration • On-chip Low Drop Out (LDO) Regulator for superior power supply rejection • Wired communications: OTN, SONET/SDH, GE, 10 GE, FC and 10G FC • Wireless communications • High performance micro-processor clock distribution Performance • Ultra low additive jitter of 78 fs RMS ctrl vt out0_p out0_n Termination and Bias Buffer clk_p clk_n out1_p out1_n Figure 1 - Functional Block Diagram 1 Microsemi Corporation Copyright 2012, Microsemi Corporation. All Rights Reserved. ZL40213 Data Sheet Table of Contents Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Inputs/Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.0 Package Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.0 Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3.0 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3.1 Clock Inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3.2 Clock Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.3 Device Additive Jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.4 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.4.1 Sensitivity to power supply noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.4.2 Power supply filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.4.3 PCB layout considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.0 AC and DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.0 Performance Characterization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6.0 Typical Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 7.0 Package Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 8.0 Mechanical Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2 Microsemi Corporation ZL40213 Data Sheet List of Figures Figure 1 - Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Figure 2 - Pin Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Figure 3 - Simplified Diagram of input stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Figure 4 - Clock Input - LVPECL - DC Coupled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 5 - Clock Input - LVPECL - AC Coupled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 6 - Clock Input - LVDS - DC Coupled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 7 - Clock Input - LVDS - AC Coupled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 8 - Clock Input - CML- AC Coupled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 9 - Clock Input - HCSL- AC Coupled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 10 - Clock Input - AC-coupled Single-Ended . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 11 - Clock Input - DC-coupled 3.3V CMOS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 12 - Simplified LVDS Output Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 13 - LVDS DC Coupled Termination (Internal Receiver Termination) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 14 - LVDS DC Coupled Termination (External Receiver Termination) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 15 - LVDS AC Coupled Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 16 - LVDS AC Output Termination for CML Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 17 - Additive Jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 18 - Decoupling Connections for Power Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 19 - Differential Voltage Parameter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 20 - Input To Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3 Microsemi Corporation ZL40213 1.0 Data Sheet Package Description 12 out1_n out1_p out0_n out0_p The device is packaged in a 16 pin QFN 10 8 vdd NC NC 14 6 NC gnd vdd NC gnd 16 4 clk_n ctrl vt clk_p 2 Figure 2 - Pin Connections 2.0 Pin Description Pin # Name 1, 4 clk_p, clk_n, Description Differential Input (Analog Input). Differential (or singled ended) input signals. For all input signal configuration see“Clock Inputs” on page 5 12, 11, out0_p, out0_n Differential Output (Analog Output). Differential outputs. 10, 9, out1_p, out1_n 8, 13 vdd Positive Supply Voltage. 2.5 VDC or 3.3 VDC nominal. 5, 16 gnd Ground. 0 V. 2 vt On-Chip Input Termination Node (Analog). Center tap between internal 50 Ohm termination resistors. See “Clock Inputs” on page 5 for more information. 3 ctrl Digital Control for On-Chip Input Termination (Input). Selects differential input mode; 0: DC coupled modes 1: AC coupled differential modes These pins are internally pulled down to GND. See “Clock Inputs” on page 5 for more information. 6, 7, 14, 15 NC No connection. Leave unconnected. 4 Microsemi Corporation ZL40213 3.0 Data Sheet Functional Description he ZL40213 is an LVDS clock fanout buffer with two identical output clock drivers capable of operating at frequencies up to 750MHz. The ZL40213 provides an internal input termination network for DC and AC coupled inputs; optional input biasing for AC coupled inputs is also provided. The ZL40213 can accept DC or AC coupled LVPECL and LVDS input signals, AC coupled CML or HCSL input signals, and single ended signals. A pin compatible device with external termination is also available. The ZL40213 is designed to fan out low-jitter reference clocks for wired or optical communications applications while adding minimal jitter to the clock signal. An internal linear power supply regulator and bulk capacitors minimize additive jitter due to power supply noise. The device operates from 2.5V+/-5% or 3.3V+/-5% supply. Its operation is guaranteed over the industrial temperature range -40°C to +85°C. The device block diagram is shown in Figure 1; its operation is described in the following sections. 3.1 Clock Inputs The device has a differential input equipped with two on-chip 50 Ohm termination resistors arranged in series with a center tap. The input can accept many differential and single-ended signals with AC or DC coupling as appropriate. A control pin is available to enable internal biasing for AC coupled inputs. A block diagram of the input stage is in Figure 3. clk_p 50 Receiver 50 clk_n Vt Bias ctrl Figure 3 - Simplified Diagram of input stage This following figures give the components values and configuration for the various circuits compatible with the input stage and the use of the Vt and ctrl pins in each case. In the following diagrams were the ctrl pin is "1" and the Vt pin is not connected, the Vt pin can be instead connected to VDD with a capacitor.The same capacitor can also help in Figure 4 between Vt and VDD. This capacitor will minimize the noise at the point between the two internal termination resistors and improve the overall performance of the device. 5 Microsemi Corporation ZL40213 Data Sheet VDD_driver VDD 22 Ohms Zo = 50 Ohms clk_p clk_p LVPECL Driver clk_n clk_n Zo = 50 Ohms Vt Vt 22 Ohms R “0” Ctrl Ctrl For 3.3 V: R= 50 Ohms For 2.5 V: R= 22 Ohms Figure 4 - Clock Input - LVPECL - DC Coupled VDD_driver VDD 22 Ohms LVPECL Driver Zo = 50 Ohms clk_p clk_n 22 Ohms Zo = 50 Ohms R NC R “1” For 3.3 V: R= 150 Ohms For 2.5 V: R= 85 Ohms Figure 5 - Clock Input - LVPECL - AC Coupled 6 Microsemi Corporation Vt Ctrl ZL40213 Data Sheet VDD_driver VDD Zo = 50 Ohms clk_p LVDS Driver clk_n Zo = 50 Ohms NC “0” Vt Ctrl Figure 6 - Clock Input - LVDS - DC Coupled VDD_driver VDD Note: R is only needed to provide a DC path for the LVDS driver. See driver data sheet for more information. Zo = 50 Ohms clk_p LVDS Driver R clk_n Zo = 50 Ohms NC “1” For VDD_driver = 3.3 V: R= 900 Ohms For VDD_driver = 2.5 V: R = 680 Ohms Figure 7 - Clock Input - LVDS - AC Coupled 7 Microsemi Corporation Vt Ctrl ZL40213 Data Sheet VDD_driver R VDD R Zo = 50 Ohms clk_p CML Driver clk_n Zo = 50 Ohms NC “1” Vt Ctrl R= 50 Ohms Figure 8 - Clock Input - CML- AC Coupled VDD_driver VDD Zo = 50 Ohms clk_p HCSL Driver clk_n Zo = 50 Ohms R NC R “1” R= 50 Ohms Figure 9 - Clock Input - HCSL- AC Coupled 8 Microsemi Corporation Vt Ctrl ZL40213 Data Sheet VDD_driver VDD CMOS Driver Zo = 50 Ohms clk_p clk_n Vt “1” Ctrl Figure 10 - Clock Input - AC-coupled Single-Ended VDD_driver VDD CMOS Driver Zo = 50 Ohms clk_p clk_n NC “1” Figure 11 - Clock Input - DC-coupled 3.3V CMOS 9 Microsemi Corporation Vt Ctrl ZL40213 3.2 Data Sheet Clock Outputs LVDS has lower signal swing than LVPECL which results in a low power consumption. A simplified diagram for the LVDS output stage is shown in Figure 12. VDD 3 mA - + Output + - Figure 12 - Simplified LVDS Output Driver The methods to terminate the ZL40213 drivers are shown in the following figures. VDD_Rx VDD ZL40213 clk_p clk_n Z o = 50 Ohms LVDS Receiver Z o = 50 Ohms Figure 13 - LVDS DC Coupled Termination (Internal Receiver Termination) 10 Microsemi Corporation ZL40213 Data Sheet VDD_Rx VDD ZL40213 clk_p Zo = 50 Ohms 100 Ohms clk_n LVDS Receiver Zo = 50 Ohms Figure 14 - LVDS DC Coupled Termination (External Receiver Termination) VDD VDD_Rx R1 ZL40213 clk_p R1 Zo = 50 Ohms LVDS Receiver 100 Ohms clk_n Zo = 50 Ohms R2 R2 Note: R1 and R2 values and need for external termination depend on the specification of the LVDS receiver Figure 15 - LVDS AC Coupled Termination 11 Microsemi Corporation VDD_Rx ZL40213 VDD ZL40213 clk_p clk_n Data Sheet VDD_Rx 50 Ohms Zo = 50 Ohms 50 Ohms CML Receiver Zo = 50 Ohms Figure 16 - LVDS AC Output Termination for CML Inputs 12 Microsemi Corporation ZL40213 3.3 Data Sheet Device Additive Jitter The ZL40213 clock fanout buffer is not intended to filter clock jitter. The jitter performance of this type of device is characterized by its additive jitter. Additive jitter is the jitter the device would add to a hypothetical jitter-free clock as it passes through the device. The additive jitter of the ZL40213 is random and as such it is not correlated to the jitter of the input clock signal. The square of the resultant random RMS jitter at the output of the ZL40213 is equal to the sum of the squares of the various random RMS jitter sources including: input clock jitter; additive jitter of the buffer; and additive jitter due to power supply noise. There may be additional deterministic jitter sources, but they are not shown in Figure 17. Jadd2 Jin2 Jps2 + Jin Jadd Jps Jout + = Random input clock jitter (RMS) = Additive jitter due to the device (RMS) = Additive jitter due to power supply noise (RMS) = Resultant random output clock jitter (RMS) Figure 17 - Additive Jitter 13 Microsemi Corporation Jout2= Jin2+Jadd2+Jps2 ZL40213 3.4 Data Sheet Power Supply This device operates with either a 2.5V supply or 3.3V supply. 3.4.1 Sensitivity to power supply noise Power supply noise from sources such as switching power supplies and high-power digital components such as FPGAs can induce additive jitter on clock buffer outputs. The ZL40213 is equipped with a low drop out (LDO) power regulator and on-chip bulk capacitors to minimize additive jitter due to power supply noise. The LDO regulator on the ZL40213 allows this device to have superior performance even in the presence of external noise sources. The on-chip measures in combination with the simple recommended power supply filtering and PCB layout minimize the additive jitter from power supply noise. The performance of these clock buffers in the presence of power supply noise is detailed in ZLAN-403, “Power Supply Rejection in Clock Buffers” which is available from Applications Engineering. 3.4.2 Power supply filtering For optimal jitter performance, the device should be isolated from the power planes connected to its power supply pins as shown in Figure 18. • • • • 10 µF capacitors should be size 0603 or size 0805 X5R or X7R ceramic, 6.3 V minimum rating 0.1 µF capacitors should be size 0402 X5R ceramic, 6.3 V minimum rating Capacitors should be placed next to the connected device power pins a 0.3 ohm resistor is recommended for the filter shown in Figure 18 VDD 0.3 Ohm s 0.1 µF 8 ZL40213 10 µF 13 Figure 18 - Decoupling Connections for Power Pins 3.4.3 PCB layout considerations The power nets in Figure 18 can be implemented either as a plane island or routed power topology without changing the overall jitter performance of the device. 14 Microsemi Corporation ZL40213 4.0 Data Sheet AC and DC Electrical Characteristics Absolute Maximum Ratings* Parameter Sym. Min. Max. Units VDD_R -0.5 4.6 V VPIN -0.5 VDD V 260 °C 125 °C 1 Supply voltage 2 Voltage on any digital pin 3 Soldering temperature 4 Storage temperature TST 5 Junction temperature Tj 125 °C 6 Voltage on input pin Vinput VDD V 7 Input capacitance each pin Cp 500 * Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied. * Voltages are with respect to ground (GND) unless otherwise stated fF T -55 Recommended Operating Conditions* Characteristics Sym. Min. Typ. Max. Units 1 Supply voltage 2.5 V mode VDD25 2.375 2.5 2.625 V 2 Supply voltage 3.3 V mode VDD33 3.135 3.3 3.465 V 3 Operating temperature TA -40 25 85 °C * Voltages are with respect to ground (GND) unless otherwise stated DC Electrical Characteristics - Current Consumption Characteristics 1 Supply current LVDS drivers loaded (all outputs are active) Sym. - Min. Typ. Idd_load Max. 44 Units Notes mA DC Electrical Characteristics - Inputs and outputs - for 2.5/3.3 V supply Characteristics Sym. Min. 1 CMOS control logic high-level input VCIH 0.7*VDD 2 CMOS control logic low-level input VCIL 3 CMOS control logic Input leakage current IIL 4 Differential input common mode supply voltage VICM 1.1 5 Differential input common mode supply voltage VICM 6 LVDS Differential input voltage 7 Differential input resistance Typ. Max. Units Notes V 0.3*VDD 1 V µA VI = VDD or 0 V 1.6 V For VDD = 2.5 1.1 2.0 V For VDD = 3.3 VID 0.25 1 V VIR 80 120 ohm 15 Microsemi Corporation 100 ZL40213 Data Sheet DC Electrical Characteristics - Inputs and outputs - for 2.5/3.3 V supply Characteristics Sym. Min. Typ. Max. Units 8 LVDS output differential voltage* VOD 0.25 0.30 0.40 V 9 LVDS output common mode voltage VCM 1.1 1.25 1.375 V Notes * The VOD parameter was measured from 125 MHz to 750 MHz. VOD 2*VOD Figure 19 - Differential Voltage Parameter AC Electrical Characteristics* - Inputs and Outputs (see Figure 20) - for 2.5/3.3 V supply. Characteristics Sym. Min. Typ. Max. Units 750 MHz 1 2 ns 1 Maximum Operating Frequency 1/tp 2 input to output clock propagation delay tpd 3 output to output skew tout2out 50 100 ps 4 part to part output skew tpart2part 80 300 ps 5 Output clock Duty Cycle degradation 0 5 % 6 LVDS Output slew rate 0 tPWH/ tPWL -5 rsl 0.55 * Supply voltage and operating temperature are as per Recommended Operating Conditions tP tREFW tREFW Input tpd Output Figure 20 - Input To Output Timing 16 Microsemi Corporation V/ns Notes ZL40213 5.0 Data Sheet Performance Characterization Additive Jitter at 2.5 V* Output Frequency (MHz) Jitter Measurement Filter Typical (fs) 1 125 12 kHz - 20 MHz 120 2 212.5 12 kHz - 20 MHz 102 3 311.04 12 kHz - 20 MHz 88 4 425 12 kHz - 20 MHz 91 5 500 12 kHz - 20 MHz 77 6 622.08 12 kHz - 20 MHz 78 7 750 12 kHz - 20 MHz 78 Notes *The values in this table were taken with a slew rate of approximately 0.8 V/ns. Additive Jitter at 3.3 V* Output Frequency (MHz) Jitter Measurement Filter Typical (fs) 1 125 12 kHz - 20 MHz 123 2 212.5 12 kHz - 20 MHz 104 3 311.04 12 kHz - 20 MHz 92 4 425 12 kHz - 20 MHz 94 5 500 12 kHz - 20 MHz 78 6 622.08 12 kHz - 20 MHz 79 7 750 12 kHz - 20 MHz 80 Notes *The values in this table were taken with a slew rate of approximately 0.8 V/ns. Additive jitter in the presence of power supply noise* Carrier frequency Parameter Typical Units 125 25 mV at 100 kHz 38 fs RMS 750 25 mV at 100 kHz 50 fs RMS Notes * The values in this table are the additive periodic jitter caused by an interfering tone typically caused by a switching power supply. For this test, measurements were taken over the full temperature and voltage range for VDD = 3.3 V. The magnitude of the interfering tone is measured at the DUT. 17 Microsemi Corporation ZL40213 6.0 Data Sheet Typical Behavior 0.33 0.2 0.15 0.325 0.1 Voltage Voltage 0.05 0 -0.05 0.32 0.315 -0.1 0.31 -0.15 -0.2 0 5 10 15 0.305 20 0 100 200 Time (ns) 400 500 600 700 800 Frequency (MHz) Typical Waveform at 155.52 MHz VOD versus Frequency -60 125 MHz -55 212.5 MHz 425 MHz -65 -60 750 MHz -65 PSRR (dBc) -70 PSRR (dBc) 300 -75 -80 -70 -75 -80 -85 125 MHz 212.5 MHz -85 425 MHz 750 MHz -90 -90 100 150 200 250 300 350 400 450 20 500 Power Supply Tone Frequency versus PSRR Propagation Delay (ns) 0.55 0.5 0.45 0.4 0.35 -40 -20 0 20 40 60 40 50 60 70 80 90 Power Supply Tone Magnitude versus PSRR 0.6 0.3 30 Power Supply Tone magnitude (mV) at 100 kHz Power Supply Tone Frequency with 25 mV (kHz) 80 100 Temperature (°C) Propagation Delay versus Temperature Note: This is for a single device. For more details see the characterization section. 18 Microsemi Corporation 100 ZL40213 7.0 Data Sheet Package Thermal Characteristics Thermal Data Parameter Symbol Test Condition Value Junction to Ambient Thermal Resistance ΘJA Still Air 1 m/s 2 m/s 67.9 61.6 58.1 o Junction to Case Thermal Resistance ΘJC Still Air 44.1 o 23.2 o Junction to Board Thermal Resistance Maximum Junction Temperature* ΘJB Still Air Tjmax Maximum Ambient Temperature TA * Proper thermal management must be practiced to ensure that Tjmax is not exceeded. 19 Microsemi Corporation Unit C/W C/W C/W 125 o 85 o C C ZL40213 8.0 Mechanical Drawing 20 Microsemi Corporation Data Sheet For more information about all Microsemi products visit our Web Site at www.microsemi.com Information relating to products and services furnished herein by Microsemi Corporation or its subsidiaries (collectively “Microsemi”) is believed to be reliable. However, Microsemi assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use. Neither the supply of such information or purchase of product or service conveys any license, either express or implied, under patents or other intellectual property rights owned by Microsemi or licensed from third parties by Microsemi, whatsoever. Purchasers of products are also hereby notified that the use of product in certain ways or in combination with Microsemi, or non-Microsemi furnished goods or services may infringe patents or other intellectual property rights owned by Microsemi. This publication is issued to provide information only and (unless agreed by Microsemi in writing) may not be used, applied or reproduced for any purpose nor form part of any order or contract nor to be regarded as a representation relating to the products or services concerned. The products, their specifications, services and other information appearing in this publication are subject to change by Microsemi without notice. No warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or service. Information concerning possible methods of use is provided as a guide only and does not constitute any guarantee that such methods of use will be satisfactory in a specific piece of equipment. It is the user’s responsibility to fully determine the performance and suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. Manufacturing does not necessarily include testing of all functions or parameters. These products are not suitable for use in any medical and other products whose failure to perform may result in significant injury or death to the user. All products and materials are sold and services provided subject to Microsemi’s conditions of sale which are available on request. Purchase of Microsemi’s I2C components conveys a license under the Philips I2C Patent rights to use these components in an I2C System, provided that the system conforms to the I2C Standard Specification as defined by Philips. Microsemi, ZL, and combinations thereof, VoiceEdge, VoicePort, SLAC, ISLIC, ISLAC and VoicePath are trademarks of Microsemi Corporation. TECHNICAL DOCUMENTATION - NOT FOR RESALE