ZL40217 Precision 1:6 LVDS Fanout Buffer with On-Chip Input Termination Data Sheet November 2012 Features Ordering Information ZL40217LDG1 ZL40217LDF1 Inputs/Outputs • Accepts differential or single-ended input • LVPECL, LVDS, CML, HCSL, LVCMOS • On-chip input termination and biasing for AC coupled inputs • Six precision LVDS outputs • Operating frequency up to 750 MHz 32 Pin QFN 32 Pin QFN Trays Tape and Reel Matte Tin Package size: 5 x 5 mm -40oC to +85oC Applications • General purpose clock distribution Power • Low jitter clock trees • Option for 2.5 V or 3.3 V power supply • Logic translation • Current consumption of 97 mA • Clock and data signal restoration • On-chip Low Drop Out (LDO) Regulator for superior power supply noise rejection • Wired communications: OTN, SONET/SDH, GE, 10 GE, FC and 10G FC Performance • Wireless communications • • High performance micro-processor clock distribution Ultra low additive jitter of 135 fs RMS out0_p out0_n out1_p out1_n ctrl vt Termination and Bias Buffer clk_p clk_n out2_p out2_n out3_p out3_n out4_p out4_n out5_p out5_n Figure 1 - Functional Block Diagram 1 Microsemi Corporation Copyright 2012, Microsemi Corporation. All Rights Reserved. ZL40217 Data Sheet Table of Contents Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Inputs/Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.0 Package Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.0 Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3.0 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3.1 Clock Inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3.2 Clock Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.3 Device Additive Jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.4 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.4.1 Sensitivity to power supply noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.4.2 Power supply filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.4.3 PCB layout considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.0 AC and DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.0 Performance Characterization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.0 Typical Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 7.0 Package Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 8.0 Mechanical Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2 Microsemi Corporation ZL40217 Data Sheet List of Figures Figure 1 - Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Figure 2 - Pin Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Figure 3 - Simplified Diagram of input stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 4 - Clock Input - LVPECL - DC Coupled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 5 - Clock Input - LVPECL - AC Coupled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 6 - Clock Input - LVDS - DC Coupled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 7 - Clock Input - LVDS - AC Coupled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 8 - Clock Input - CML- AC Coupled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 9 - Clock Input - HCSL- AC Coupled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 10 - Clock Input - AC-coupled Single-Ended . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 11 - Clock Input - DC-coupled 3.3V CMOS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 12 - Simplified LVDS Output Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 13 - LVDS DC Coupled Termination (Internal Receiver Termination) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 14 - LVDS DC Coupled Termination (External Receiver Termination) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 15 - LVDS AC Coupled Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 16 - LVDS AC Output Termination for CML Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 17 - Additive Jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 18 - Decoupling Connections for Power Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 19 - Differential Voltage Parameter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 20 - Input To Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3 Microsemi Corporation ZL40217 1.0 Data Sheet Package Description 24 22 20 out3_n 18 out1_n out1_p out3_p vdd gnd gnd vdd out2_n out2_p The device is packaged in a 32 pin QFN 16 out4_n 26 out0_n 14 28 NC 12 gnd (E-pad) NC 10 32 NC vdd VDD_core 8 gnd clk_n 6 ctrl 4 clk_p gnd 2 VDD_core vdd NC NC 30 vt NC out5_p out5_n vt out0_p out4_p Figure 2 - Pin Connections 4 Microsemi Corporation ZL40217 2.0 Data Sheet Pin Description Pin # Name 3, 6 clk_p, clk_n, 28, 27, 26, 25, 24, 23, 18, 17, 16, 15, 14, 13 Description Differential Input (Analog Input). Differential (or single ended) input signals. For all input configurations see “Clock Inputs” on page 6 out0_p, out0_n Differential Output (Analog Output). Differential outputs. out1_p, out1_n out2_p, out2_n out3_p, out3_n out4_p, out4_n out5_p, out5_n 9, 19, 22, 32 vdd Positive Supply Voltage. 2.5 VDC or 3.3 VDC nominal. 1, 8 vdd_core Positive Supply Voltage. 2.5 VDC or 3.3 VDC nominal. 2, 7, 20, 21 gnd 4 vt On-Chip Input Termination Node (Analog). Center tap between internal 50 Ohm termination resistors. The use of this pin is detailed in section 3.1, “Clock Inputs“, for various input signal types. 5 ctrl Digital Control for On-Chip Input Termination (Input). Selects differential input mode; 0: DC coupled LVPECL or LVDS modes 1: AC coupled differential modes This pin are internally pulled down to GND. The use of this pin is detailed in section 3.1, “Clock Inputs“, for various input signal types. 10, 11, 12, 29, 30, 31 NC No Connection. Leave unconnected. Ground. 0 V. 5 Microsemi Corporation ZL40217 3.0 Data Sheet Functional Description he ZL40217 is an LVDS clock fanout buffer with six output clock drivers capable of operating at frequencies up to 750MHz. The ZL40217 provides an internal input termination network for DC and AC coupled inputs; optional input biasing for AC coupled inputs is also provided. The ZL40217 can accept DC or AC coupled LVPECL and LVDS input signals, AC coupled CML or HCSL input signals, and single ended signals. A pin compatible device with external termination is also available. The ZL40217 is designed to fan out low-jitter reference clocks for wired or optical communications applications while adding minimal jitter to the clock signal. An internal linear power supply regulator and bulk capacitors minimize additive jitter due to power supply noise. The device operates from 2.5V+/-5% or 3.3V+/-5% supply. Its operation is guaranteed over the industrial temperature range -40°C to +85°C. The device block diagram is shown in Figure 1; its operation is described in the following sections. 3.1 Clock Inputs The device has a differential input equipped with two on-chip 50 Ohm termination resistors arranged in series with a center tap. The input can accept many differential and single-ended signals with AC or DC coupling as appropriate. A control pin is available to enable internal biasing for AC coupled inputs. A block diagram of the input stage is in Figure 3. clk_p 50 Receiver 50 clk_n Vt Bias ctrl Figure 3 - Simplified Diagram of input stage This following figures give the components values and configuration for the various circuits compatible with the input stage and the use of the Vt and ctrl pins in each case. In the following diagrams were the ctrl pin is "1" and the Vt pin is not connected, the Vt pin can be instead connected to VDD with a capacitor. A capacitor can also help in Figure 4 between Vt and VDD. This capacitor will minimize the noise at the point between the two internal termination resistors and improve the overall performance of the device. 6 Microsemi Corporation ZL40217 Data Sheet VDD_driver VDD 22 Ohms Zo = 50 Ohms clk_p clk_p LVPECL Driver clk_n clk_n Zo = 50 Ohms Vt Vt 22 Ohms R “0” Ctrl Ctrl For 3.3 V: R= 50 Ohms For 2.5 V: R= 22 Ohms Figure 4 - Clock Input - LVPECL - DC Coupled VDD_driver VDD 22 Ohms LVPECL Driver Zo = 50 Ohms clk_p clk_n 22 Ohms Zo = 50 Ohms R NC R “1” For 3.3 V: R= 150 Ohms For 2.5 V: R= 85 Ohms Figure 5 - Clock Input - LVPECL - AC Coupled 7 Microsemi Corporation Vt Ctrl ZL40217 Data Sheet VDD_driver VDD Zo = 50 Ohms clk_p LVDS Driver clk_n Zo = 50 Ohms NC “0” Vt Ctrl Figure 6 - Clock Input - LVDS - DC Coupled VDD_driver VDD Zo = 50 Ohms clk_p LVDS Driver R clk_n Zo = 50 Ohms NC “1” For VDD_driver = 3.3 V: R= 900 Ohms For VDD_driver = 2.5 V: R = 680 Ohms Figure 7 - Clock Input - LVDS - AC Coupled 8 Microsemi Corporation Vt Ctrl ZL40217 Data Sheet VDD_driver R VDD R Zo = 50 Ohms clk_p CML Driver clk_n Zo = 50 Ohms NC “1” Vt Ctrl R= 50 Ohms Figure 8 - Clock Input - CML- AC Coupled VDD_driver VDD Zo = 50 Ohms clk_p HCSL Driver clk_n Zo = 50 Ohms R NC R “1” R= 50 Ohms Figure 9 - Clock Input - HCSL- AC Coupled 9 Microsemi Corporation Vt Ctrl ZL40217 Data Sheet VDD_driver VDD CMOS Driver Zo = 50 Ohms clk_p clk_n Vt “1” Ctrl Figure 10 - Clock Input - AC-coupled Single-Ended VDD_driver VDD CMOS Driver Zo = 50 Ohms clk_p clk_n NC “1” Figure 11 - Clock Input - DC-coupled 3.3V CMOS 10 Microsemi Corporation Vt Ctrl ZL40217 3.2 Data Sheet Clock Outputs LVDS has lower signal swing than LVPECL which results in a low power consumption. A simplified diagram for the LVDS output stage is shown in Figure 12. VDD 3 mA - + Output + - Figure 12 - Simplified LVDS Output Driver The methods to terminate the ZL40217 drivers are shown in the following figures. VDD_Rx VDD ZL40217 clk_p clk_n Zo = 50 Ohms LVDS Receiver Zo = 50 Ohms Figure 13 - LVDS DC Coupled Termination (Internal Receiver Termination) 11 Microsemi Corporation ZL40217 Data Sheet VDD_Rx VDD ZL40217 clk_p Zo = 50 Ohms 100 Ohms clk_n LVDS Receiver Zo = 50 Ohms Figure 14 - LVDS DC Coupled Termination (External Receiver Termination) VDD_Rx VDD R1 ZL40217 clk_p R1 Zo = 50 Ohms LVDS Receiver 100 Ohms clk_n Zo = 50 Ohms R2 R2 Note: R1 and R2 values and need for external termination depend on the specification of the LVDS receiver Figure 15 - LVDS AC Coupled Termination 12 Microsemi Corporation VDD_Rx ZL40217 Data Sheet VDD_Rx VDD ZL40217 clk_p clk_n 50 Ohms Zo = 50 Ohms 50 Ohms CML Receiver Zo = 50 Ohms Figure 16 - LVDS AC Output Termination for CML Inputs 13 Microsemi Corporation ZL40217 3.3 Data Sheet Device Additive Jitter The ZL40217 clock fanout buffer is not intended to filter clock jitter. The jitter performance of this type of device is characterized by its additive jitter. Additive jitter is the jitter the device would add to a hypothetical jitter-free clock as it passes through the device. The additive jitter of the ZL40217 is random and as such it is not correlated to the jitter of the input clock signal. The square of the resultant random RMS jitter at the output of the ZL40217 is equal to the sum of the squares of the various random RMS jitter sources including: input clock jitter; additive jitter of the buffer; and additive jitter due to power supply noise. There may be additional deterministic jitter sources, but they are not shown in Figure 17. Jadd2 Jin2 Jps2 + Jin Jadd Jps Jout + = Random input clock jitter (RMS) = Additive jitter due to the device (RMS) = Additive jitter due to power supply noise (RMS) = Resultant random output clock jitter (RMS) Figure 17 - Additive Jitter 14 Microsemi Corporation Jout2= Jin2+Jadd2+Jps2 ZL40217 3.4 Data Sheet Power Supply This device operates employing either a 2.5V supply or 3.3V supply. 3.4.1 Sensitivity to power supply noise Power supply noise from sources such as switching power supplies and high-power digital components such as FPGAs can induce additive jitter on clock buffer outputs. The ZL40217 is equipped with a low drop out (LDO) linear power regulator and on-chip bulk capacitors to minimize additive jitter due to power supply noise. The on-chip measures in combination with the simple recommended power supply filtering and PCB layout minimize additive jitter from power supply noise. 3.4.2 Power supply filtering Jitter levels may increase when noise is present on the power pins. For optimal jitter performance, the device should be isolated from the power planes connected to its power supply pins as shown in Figure •. • • • • 10 µF capacitors should be size 0603 or size 0805 X5R or X7R ceramic, 6.3 V minimum rating 0.1 µF capacitors should be size 0402 X5R ceramic, 6.3 V minimum rating Capacitors should be placed next to the connected device power pins A 0.3 ohm resistor is recommended vdd_core 0.1 µF 0.1 µF 1 8 0.15 Ω vdd 9 10 µF 0.1 µF 0.1 µF ZL40217 19 22 32 10 µF Figure 18 - Decoupling Connections for Power Pins 3.4.3 PCB layout considerations The power nets in Figure 18 can be implemented either as a plane island or routed power topology without changing the overall jitter performance of the device. 15 Microsemi Corporation ZL40217 4.0 Data Sheet AC and DC Electrical Characteristics Absolute Maximum Ratings* Parameter Sym. Min. Max. Units VDD_R -0.5 4.6 V VPIN -0.5 VDD V 260 °C 125 °C 1 Supply voltage 2 Voltage on any digital pin 3 Soldering temperature 4 Storage temperature TST 5 Junction temperature Tj 125 °C 6 Voltage on input pin Vinput VDD V 7 Input capacitance each pin Cp 500 * Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied. * Voltages are with respect to ground (GND) unless otherwise stated fF T -55 Recommended Operating Conditions* Characteristics Sym. Min. Typ. Max. Units 1 Supply voltage 2.5 V mode VDD25 2.375 2.5 2.625 V 2 Supply voltage 3.3 V mode VDD33 3.135 3.3 3.465 V 3 Operating temperature TA -40 25 85 °C * Voltages are with respect to ground (GND) unless otherwise stated DC Electrical Characteristics - Current Consumption Characteristics 1 Supply current LVDS drivers loaded (all outputs are active) Sym. - Min. Typ. Idd_load Max. 97 Units Notes mA DC Electrical Characteristics - Inputs and outputs - for 2.5/3.3 V supply Characteristics Sym. Min. 1 CMOS control logic high-level input VCIH 0.7*VDD 2 CMOS control logic low-level input VCIL 3 CMOS control logic Input leakage current IIL 4 Differential common mode voltage VICM 1.1 5 Differential common mode voltage VICM 6 Differential input voltage difference 7 Typ. Max. Units Notes V 0.3*VDD 1 V µA VI = VDD or 0 V 1.6 V for 2.5 V 1.1 2.0 V for 3.3 V VID 0.25 1 V Differential input resistance VIR 80 100 120 ohm 8 LVDS output differential voltage* VOD 0.25 0.30 0.40 V 9 LVDS Common Mode voltage VCM 1.1 1.25 1.375 V 16 Microsemi Corporation ZL40217 Data Sheet * The VOD parameter was measured between 125 and 750 MHz VOD 2*VOD Figure 19 - Differential Voltage Parameter AC Electrical Characteristics* - Inputs and Outputs (see Figure 20) - for 2.5/3.3 V supply. Characteristics Sym. Min. Typ. Max. Units 750 MHz 1 2 ns 1 Maximum Operating Frequency 1/tp 2 input to output clock propagation delay tpd 3 output to output skew tout2out 80 150 ps 4 part to part output skew tpart2part 120 300 ps 5 Output clock Duty Cycle degradation 0 5 % 6 LVDS Output slew rate 0 tPWH/ tPWL -5 rSL 0.55 * Supply voltage and operating temperature are as per Recommended Operating Conditions tP tREFW tREFW Input tpd Output Figure 20 - Input To Output Timing 17 Microsemi Corporation V/ns Notes ZL40217 5.0 Data Sheet Performance Characterization Additive Jitter at 2.5 V* Output Frequency (MHz) Jitter Measurement Filter Typical RMS (fs) 1 125 12 kHz - 20 MHz 184 2 212.5 12 kHz - 20 MHz 174 3 311.04 12 kHz - 20 MHz 157 4 425 12 kHz - 20 MHz 152 5 500 12 kHz - 20 MHz 139 6 622.08 12 kHz - 20 MHz 138 7 750 12 kHz - 20 MHz 135 Notes *The values in this table were taken with an approximate slew rate of 0.8 V/ns. Additive Jitter at 3.3 V* Output Frequency (MHz) Jitter Measurement Filter Typical RMS (fs) 1 125 12 kHz - 20 MHz 187 2 212.5 12 kHz - 20 MHz 176 3 311.04 12 kHz - 20 MHz 156 4 425 12 kHz - 20 MHz 153 5 500 12 kHz - 20 MHz 140 6 622.08 12 kHz - 20 MHz 139 7 750 12 kHz - 20 MHz 137 Notes *The values in this table were taken with an approximate slew rate of 0.8 V/ns. Additive jitter from a power supply tone* Carrier frequency Parameter Typical Units 125 25 mV at 100 kHz 33 fs RMS 750 25 mV at 100 kHz 33 fs RMS Notes * The values in this table are the additive periodic jitter caused by an interfering tone typically caused by a switching power supply. For this test, measurements were taken over the full temperature and voltage range for VDD = 3.3 V. The magnitude of the interfering tone is measured at the DUT. 18 Microsemi Corporation ZL40217 6.0 Data Sheet Typical Behavior 0.35 0.2 0.15 0.34 0.1 0.33 VOD Voltage 0.05 0 0.32 -0.05 -0.1 0.31 -0.15 -0.2 0 5 10 15 0.3 20 0 Time (ns) 200 300 400 500 600 -50 125 MHz -55 212.5 MHz -65 -60 425 MHz 750 MHz -65 PSRR (dBc) -70 -75 -80 -70 -75 -80 125 MHz -85 212.5 MHz -90 -85 425 MHz -95 750 MHz -100 100 150 200 250 300 350 400 450 20 500 Power Supply Tone Frequency versus PSRR 0.85 0.8 0.75 0.7 0.65 -40 -20 0 20 40 40 50 60 70 80 Power Supply Tone Magnitude versus PSRR 0.9 0.6 30 Tone Magnitude (mV) Tone Frequency (kHz) Delay (ns) 800 VOD vs Frequency -60 -90 700 Frequency (MHz) Typical Waveform at 155.52 MHz PSRR (dBc) 100 60 80 100 Temperature ( C) Propogation Delay versus Temperature Note: This is for a single device. For more details, see the characterization section. 19 Microsemi Corporation 90 100 ZL40217 7.0 Data Sheet Package Characteristics Thermal Data Parameter Symbol Test Condition Value Junction to Ambient Thermal Resistance ΘJA Still Air 1 m/s 2 m/s 37.4 33.1 31.5 o Junction to Case Thermal Resistance ΘJC 24.4 oC/W Junction to Board Thermal Resistance ΘJB 19.5 oC/W Maximum Junction Temperature* Tjmax 125 oC Maximum Ambient Temperature TA 85 oC 20 Microsemi Corporation Unit C/W ZL40217 8.0 Mechanical Drawing 21 Microsemi Corporation Data Sheet For more information about all Microsemi productsvisit our Web Site at www.microsemi.com Information relating to products and services furnished herein by Microsemi Corporation or its subsidiaries (collectively “Microsemi”) is believed to be reliable. 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