HD74HC670 4-by-4 Register File (with 3-state outputs) REJ03D0639-0200 (Previous ADE-205-521) Rev.2.00 Mar 30, 2006 Description The HD74HC670, 16-bit register file is organized as 4 words of 4 bits each and separate on-chip decoding is provided for addressing the four word locations to either write-in or retrieve data. This permits simultaneous writing into one location and reading from another word location. Four data inputs are available which are used to supply the 4-bit word to be stored. Location of the word is determined by the write-address inputs A and B in conjunction with a write-enable signal. Data applied at the inputs should be in its true form. That is, if a high-level signal is desired from the output, a high-level is applied at the data input for that particular bit location. The latch inputs are arranged so that new data will be accepted only if both internal address gate inputs are high. When this condition exists, data at the D input is transferred to the latch output. When the write-enable input, (GW) is high, the data inputs are inhibited and their levels can cause no change in the information stored in the internal latches. When the read-enable input, (GR) is high, the data outputs are inhibited and go into the high-impedance state. The individual address lines permit direct acquisition of data stored in any four of the latches. Four individual decoding gates are used to complete the address for reading a word. When the read address is made in conjunction with the read-enable signal, the word appears at the four outputs. Features • High Speed Operation: tpd (Read Select to Q) = 21 ns typ (CL = 50 pF) • High Output Current: Fanout of 15 LSTTL Loads • Wide Operating Voltage: VCC = 2 to 6 V • Low Input Current: 1 µA max • Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C) • Ordering Information Part Name Package Type HD74HC670P DILP-16 pin HD74HC670FPEL SOP-16 pin (JEITA) Package Code (Previous Code) PRDP0016AE-B (DP-16FV) PRSP0016DH-B (FP-16DAV) Note: Please consult the sales office for the above package availability. Rev.2.00 Mar 30, 2006 page 1 of 8 Package Abbreviation Taping Abbreviation (Quantity) P — FP EL (2,000 pcs/reel) HD74HC670 Function Table Write Inputs Word WB L WA L GW L 0 Q=D 1 Q0 2 Q0 3 Q0 L H H L L L Q0 Q0 Q=D Q0 Q0 Q=D Q0 Q0 H X H X L H Q0 Q0 Q0 Q0 Q0 Q0 Q=D Q0 RB Read Inputs RA GR Q1 Q2 Q3 Q4 L L L H L L W0 B1 W1 B1 W0 B2 W1 B2 W0 B3 W1 B3 W0 B4 W1 B4 H H L H L L W2 B1 W3 B1 W2 B2 W3 B2 W2 B3 W3 B3 W2 B4 W3 B4 Outputs X X H Z Z Z Z H : high level L : low level X : irrelevant Z : high impedance (off) (Q = D): The four selected internal flip-flop outputs will assume the states applied to the four external data inputs. Q0 : The level of Q before the indicated input conditions were established. W0 B1 : The first bit of word 0, etc. Pin Arrangement D2 1 D3 2 D3 D4 3 RB 16 VCC D1 15 Data D1 D4 WA 14 WA 4 RB WB 13 WB RA 5 RA CW 12 Write Q4 6 Q4 CR 11 Read Q3 7 Q3 Q1 10 Q1 GND 8 9 Q2 Data Read select D2 Write select Enable Outputs Q2 (Top view) Rev.2.00 Mar 30, 2006 page 2 of 8 Outputs HD74HC670 Logic Diagram To other three bits D G VCC Q D G Q D G Q D G Q Q Data WA RA WB GR GW RB Absolute Maximum Ratings Item Symbol Ratings Unit Supply voltage range Input / Output voltage VCC VIN, VOUT –0.5 to 7.0 –0.5 to VCC +0.5 V V IIK, IOK IOUT ±20 ±35 mA mA ICC or IGND PT ±75 500 mA mW Tstg –65 to +150 °C Input / Output diode current Output current VCC, GND current Power dissipation Storage temperature Note: The absolute maximum ratings are values, which must not individually be exceeded, and furthermore, no two of which may be realized at the same time. Recommended Operating Conditions Item Supply voltage Symbol VCC Ratings 2 to 6 Unit V Input / Output voltage Operating temperature VIN, VOUT Ta 0 to VCC –40 to 85 V °C tr , tf 0 to 1000 0 to 500 Input rise / fall time *1 0 to 400 Note: 1. This item guarantees maximum limit when one input switches. Waveform: Refer to test circuit of switching characteristics. Rev.2.00 Mar 30, 2006 page 3 of 8 ns Conditions VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V HD74HC670 Electrical Characteristics Ta = 25°C Item Input voltage Symbol VCC (V) VIH VIL Output voltage VOH VOL Ta = –40 to+85°C 2.0 Min 1.5 Typ — Max — Min 1.5 Max — 4.5 6.0 3.15 4.2 — — — — 3.15 4.2 — — 2.0 4.5 — — — — 0.5 1.35 — — 0.5 1.35 6.0 2.0 — 1.9 — 2.0 1.8 — — 1.9 1.8 — 4.5 6.0 4.4 5.9 4.5 6.0 — — 4.4 5.9 — — 4.5 6.0 4.18 5.68 — — — — 4.13 5.63 — — 2.0 4.5 — — 0.0 0.0 0.1 0.1 — — 0.1 0.1 6.0 4.5 — — 0.0 — 0.1 0.26 — — 0.1 0.33 Unit Test Conditions V V V Vin = VIH or VIL IOH = –20 µA IOH = –6 mA IOH = –7.8 mA V Vin = VIH or VIL IOL = 20 µA IOL = 6 mA Off-state output current IOZ 6.0 6.0 — — — — 0.26 ±0.5 — — 0.33 ±5.0 IOL = 7.8 mA µA Vin = VIN or VIL, Vout = VCC or GND Input current Quiescent supply current Iin ICC 6.0 6.0 — — — — ±0.1 4.0 — — ±1.0 40 µA Vin = VCC or GND µA Vin = VCC or GND, Iout = 0 µA Rev.2.00 Mar 30, 2006 page 4 of 8 HD74HC670 Switching Characteristics (CL = 50 pF, Input tr = tf = 6 ns) Ta = 25°C Item Propagation delay time Symbol VCC (V) tPLH tPHL 2.0 Min — Typ — Max 160 Min — Max 200 4.5 6.0 — — 21 — 32 27 — — 40 34 tPLH tPHL 2.0 4.5 — — — 24 200 40 — — 250 50 6.0 2.0 — — — — 34 150 — — 43 190 4.5 6.0 — — 18 — 30 26 — — 38 33 2.0 4.5 — — — 18 150 30 — — 190 38 6.0 2.0 — — — — 26 150 — — 33 190 4.5 6.0 — — 17 — 30 26 — — 38 33 2.0 4.5 80 16 — — — — 100 20 — — 6.0 2.0 14 60 — — — — 17 75 — — 4.5 6.0 12 10 4 — — — 15 13 — — 2.0 4.5 60 12 — — — — 75 15 — — 6.0 2.0 10 50 — — — — 13 63 — — 4.5 6.0 10 9 6 — — — 13 11 — — 2.0 4.5 50 10 — — — — 63 13 — — 6.0 2.5 9 100 — — — — 11 125 — — 4.5 6.0 20 17 — — — — 25 21 — — tPLH tPHL Output enable time tZH tZL Output disable time tHZ tLZ Pulse width tw Setup time tsu Hold time Ta = –40 to +85°C th Latch time for new data tlatch Output rise/fall time tTLH tTHL 2.0 4.5 — — — 5 75 15 — — 95 19 Cin 6.0 — — — — 5 13 10 — — 16 10 Input capacitance Rev.2.00 Mar 30, 2006 page 5 of 8 Unit Test Conditions ns Read select to Q ns Write enable to Q ns Data to Q ns ns ns ns Data to Write enable ns Write select to Write enable ns Write enable to Data ns Write enable to Write select ns ns pF HD74HC670 Test Circuit VCC VCC Output GR See Function Table Input Pulse Generator Zout = 50 Ω Input Pulse Generator Zout = 50 Ω GW 1 kΩ OPEN S1 Q1 to Q4 GND CL = 50 pF RA VCC RB WA WB TEST t PLH / t PHL S1 OPEN t ZH/ t HZ t ZL / t LZ GND VCC D1 to D4 Note : 1. CL includes probe and jig capacitance. Waveforms • Waveform – 1 tf tr 90 % 50 % WA or WB VCC 90 % 50 % 10 % 10 % t su tf tr 90 % Data D1 to D4 VCC 90 % 50 % 10 % 50 % 10 % t su 0V th tf GW 0V th tr VCC 90 % 50 % 90 % 50 % 10 % 10 % 0V tw tr t latch tf 90 % 50 % RA or RB VCC 90 % 50 % 10 % 10 % t PHL 0V t PLH 90 % Q1 to Q4 50 % 50 % 10 % 10 % t THL t TLH Note : 1. Input waveform : PRR ≤ 1 MHz, duty cycle 50%, tr ≤ 6 ns, tf ≤ 6 ns Rev.2.00 Mar 30, 2006 page 6 of 8 VOH VOL HD74HC670 • Waveform – 2 tr tf VCC Data D1 to D4 50% 0V VCC GW 50% 0V tPLH tPHL VOH 50% 50% Q1 to Q4 VOL VCC 50% Data D1 to D4 0V VCC 50% GW 0V tPHL tPLH 90% 50% Q1 to Q4 VOH 90% 50% 10% VOL tTHL tTLH Note : 1. Input waveform : PRR ≤ 1 MHz, duty cycle 50%, tr ≤ 6 ns, tf ≤ 6 ns • Waveform – 3 tf Read Enable tr 90 % 50 % VCC 90 % 50 % 10 % 10 % t ZL 0V t LZ VOH Waveform - A 50 % t ZH Waveform - B 50 % 10 % VOL t HZ 90 % VOH VOL Notes : 1. Input waveform : PRR ≤ 1 MHz, duty cycle 50%, tr ≤ 6 ns, tf ≤ 6 ns 2. Waveform - A is for an output with internal conditions such that the output is low except when disabled by the output control. 3. Waveform - B is for an output with internal conditions such that the output is high except when disabled by the output control. 4. The output are measured one at a time with one transition per measurement. Rev.2.00 Mar 30, 2006 page 7 of 8 HD74HC670 Package Dimensions JEITA Package Code P-DIP16-6.3x19.2-2.54 RENESAS Code PRDP0016AE-B Previous Code DP-16FV MASS[Typ.] 1.05g D 9 E 16 1 8 b3 0.89 A1 A Z L Reference Symbol θ bp e e1 D E A A1 bp b3 c θ e Z L c e1 ( Ni/Pd/Au plating ) JEITA Package Code P-SOP16-5.5x10.06-1.27 RENESAS Code PRSP0016DH-B *1 Previous Code FP-16DAV Dimension in Millimeters Min Nom Max 7.62 19.2 20.32 6.3 7.4 5.06 0.51 0.40 0.48 0.56 1.30 0.19 0.25 0.31 0° 15° 2.29 2.54 2.79 1.12 2.54 MASS[Typ.] 0.24g D F 16 NOTE) 1. DIMENSIONS"*1 (Nom)"AND"*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET. 9 c HE *2 E bp Index mark Terminal cross section ( Ni/Pd/Au plating ) 1 Z 8 e *3 bp x Reference Symbol M A L1 A1 θ y L Detail F Rev.2.00 Mar 30, 2006 page 8 of 8 D E A2 A1 A bp b1 c c1 θ HE e x y Z L L1 Dimension in Millimeters Min Nom Max 10.06 10.5 5.50 0.00 0.10 0.20 2.20 0.34 0.40 0.46 0.15 0.20 0.25 0° 8° 7.50 7.80 8.00 1.27 0.12 0.15 0.80 0.50 0.70 0.90 1.15 Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party. 2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Renesas Technology Corp. without notice due to product improvements or other reasons. It is therefore recommended that customers contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Renesas Technology Corp. by various means, including the Renesas Technology Corp. Semiconductor home page (http://www.renesas.com). 4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corp. assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in whole or in part these materials. 7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. 8. Please contact Renesas Technology Corp. for further details on these materials or the products contained therein. http://www.renesas.com RENESAS SALES OFFICES Refer to "http://www.renesas.com/en/network" for the latest and detailed information. Renesas Technology America, Inc. 450 Holger Way, San Jose, CA 95134-1368, U.S.A Tel: <1> (408) 382-7500, Fax: <1> (408) 382-7501 Renesas Technology Europe Limited Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K. Tel: <44> (1628) 585-100, Fax: <44> (1628) 585-900 Renesas Technology (Shanghai) Co., Ltd. Unit 204, 205, AZIACenter, No.1233 Lujiazui Ring Rd, Pudong District, Shanghai, China 200120 Tel: <86> (21) 5877-1818, Fax: <86> (21) 6887-7898 Renesas Technology Hong Kong Ltd. 7th Floor, North Tower, World Finance Centre, Harbour City, 1 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel: <852> 2265-6688, Fax: <852> 2730-6071 Renesas Technology Taiwan Co., Ltd. 10th Floor, No.99, Fushing North Road, Taipei, Taiwan Tel: <886> (2) 2715-2888, Fax: <886> (2) 2713-2999 Renesas Technology Singapore Pte. Ltd. 1 Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632 Tel: <65> 6213-0200, Fax: <65> 6278-8001 Renesas Technology Korea Co., Ltd. Kukje Center Bldg. 18th Fl., 191, 2-ka, Hangang-ro, Yongsan-ku, Seoul 140-702, Korea Tel: <82> (2) 796-3115, Fax: <82> (2) 796-2145 Renesas Technology Malaysia Sdn. Bhd Unit 906, Block B, Menara Amcorp, Amcorp Trade Centre, No.18, Jalan Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, Malaysia Tel: <603> 7955-9390, Fax: <603> 7955-9510 © 2006. Renesas Technology Corp., All rights reserved. Printed in Japan. Colophon .6.0