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HN58X24128FPIAG HN58X24256FPIAG Two-wire serial interface 128k EEPROM (16-kword × 8-bit) 256k EEPROM (32-kword × 8-bit) ADE-203-1266A (Z) Rev. 1.0 Apr. 20, 2001 Description HN58X24xxxFPIAG series are two-wire serial interface EEPROM (Electrically Erasable and Programmable ROM). They realize high speed, low power consumption and a high level of reliability by employing advanced MNOS memory technology and CMOS process and low voltage circuitry technology. They also have a 64-byte page programming function to make their write operation faster. Features • • • • • • • • Single supply: 1.8 V to 5.5 V Two-wire serial interface (I2CTM serial bus* 1) Clock frequency: 400 kHz Power dissipation: Standby: 3 µA (max) Active (Read): 1 mA (max) Active (Write): 5 mA (max) Automatic page write: 64-byte/page Write cycle time: 10 ms (2.7 V to 5.5 V)/15 ms (1.8 V to 2.7 V) Endurance: 10 5 Cycles (Page write mode) Data retention: 10 Years HN58X24128FPIAG/HN58X24256FPIAG • Small size packages: SOP-8pin • Shipping tape and reel: 2,500 IC/reel • Temperature range: –40 to +85°C Note: 1. I2C is a trademark of Philips Corporation. Ordering Information Type No. Internal organization Operating voltage Frequency HN58X24128FPIAG 128k bit (16384 × 8-bit) 1.8 V to 5.5 V 400 kHz HN58X24256FPIAG 256k bit (32768 × 8-bit) Pin Arrangement 8-pin SOP A0 1 8 VCC A1 2 7 WP A2 3 6 SCL VSS 4 5 SDA (Top view) Pin Description Pin name Function A0 to A2 Device address SCL Serial clock input SDA Serial data input/output WP Write protect VCC Power supply VSS Ground NC No connection 2 Package 150 mil 8-pin plastic SOP (FP-8DB) HN58X24128FPIAG/HN58X24256FPIAG Block Diagram High voltage generator Control logic A0, A1, A2 SCL X decoder WP Address generator VSS Memory array Y decoder VCC Y-select & Sense amp. SDA Serial-parallel converter Absolute Maximum Ratings Parameter Symbol Value Supply voltage relative to VSS VCC –0.6 to +7.0 Vin 2 –0.5* to +7.0* Topr –40 to +85 ˚C Tstg –65 to +125 ˚C Input voltage relative to V SS Operating temperature range* 1 Storage temperature range Unit V 3 V Notes: 1. Including electrical characteristics and data retention. 2. Vin (min): –3.0 V for pulse width ≤ 50 ns. 3. Should not exceed VCC + 1.0 V. DC Operating Conditions Parameter Symbol Min Typ Max Unit Supply voltage VCC 1.8 — 5.5 V VSS 0 0 0 V VIH VCC × 0.7 — VCC + 1.0 V Input high voltage Input low voltage VIL –0.3* — VCC × 0.3 V Operating temperature Topr –40 — 85 ˚C 1 Notes: 1. VIL (min): –1.0 V for pulse width ≤ 50 ns. 3 HN58X24128FPIAG/HN58X24256FPIAG DC Characteristics (Ta = –40 to +85˚C, VCC = 1.8 V to 5.5 V) Parameter Symbol Min Typ Max Unit Test conditions Input leakage current I LI — — 2.0 µA VCC = 5.5 V, Vin = 0 to 5.5 V Output leakage current I LO — — 2.0 µA VCC = 5.5 V, Vout = 0 to 5.5 V Standby V CC current I SB — 1.0 3.0 µA Vin = VSS or VCC Read VCC current I CC1 — — 1.0 mA VCC = 5.5 V, Read at 400 kHz Write VCC current I CC2 — — 5.0 mA VCC = 5.5 V, Write at 400 kHz Output low voltage VOL2 — — 0.4 V VCC = 4.5 to 5.5 V, IOL = 1.6 mA VCC = 2.7 to 4.5 V, IOL = 0.8 mA VCC = 1.8 to 2.7 V, IOL = 0.4 mA VOL1 — — 0.2 V VCC = 1.8 to 2.7 V, IOL = 0.2 mA Capacitance (Ta = 25˚C, f = 1 MHz) Min Typ Max Unit Test conditions Input capacitance (A0 to A2, SCL, WP) Cin*1 — — 6.0 pF Vin = 0 V 1 — — 6.0 pF Vout = 0 V Parameter Output capacitance (SDA) Note: 4 Symbol CI/O* 1. This parameter is sampled and not 100% tested. HN58X24128FPIAG/HN58X24256FPIAG AC Characteristics (Ta = –40 to +85˚C, VCC = 1.8 to 5.5 V) Test Conditions • Input pules levels: VIL = 0.2 × VCC VIH = 0.8 × VCC • Input rise and fall time: ≤ 20 ns • Input and output timing reference levels: 0.5 × VCC • Output load: TTL Gate + 100 pF Parameter Symbol Min Typ Max Unit Clock frequency f SCL — — 400 kHz Clock pulse width low t LOW 1200 — — ns Clock pulse width high t HIGH 600 — — ns Noise suppression time tI — — 50 ns Access time t AA 100 — 900 ns Bus free time for next mode t BUF 1200 — — ns Start hold time t HD.STA 600 — — ns Start setup time t SU.STA 600 — — ns Data in hold time t HD.DAT 0 — — ns Data in setup time t SU.DAT 100 — — ns Input rise time tR — — 300 ns 1 Input fall time tF — — 300 ns 1 Stop setup time t SU.STO 600 — — ns Data out hold time t DH 50 — — ns VCC = 2.7 V to 5.5 V t WC — — 10 ms 2 VCC = 1.8 V to 2.7 V t WC — — 15 ms 2 Write cycle time Notes 1 Notes: 1. This parameter is sampled and not 100% tested. 2. t WC is the time from a stop condition to the end of internally controlled write cycle. 5 HN58X24128FPIAG/HN58X24256FPIAG Timing Waveforms Bus Timing tF tHIGH 1/fSCL tLOW tR SCL tSU.STA tHD.DAT tSU.DAT tHD.STA tSU.STO SDA (in) tBUF tAA tDH SDA (out) Write Cycle Timing Stop condition Start condition SCL SDA D0 in Write data (Address (n)) 6 ACK tWC (Internally controlled) HN58X24128FPIAG/HN58X24256FPIAG Pin Function Serial Clock (SCL) The SCL pin is used to control serial input/output data timing. The SCL input is used to positive edge clock data into EEPROM device and negative edge clock data out of each device. Maximum clock rate is 400 kHz. Serial Input/Output Data (SDA) The SDA pin is bidirectional for serial data transfer. The SDA pin needs to be pulled up by resistor as that pin is open-drain driven structure. Use proper resistor value for your system by considering VOL, IOL and the SDA pin capacitance. Except for a start condition and a stop condition which will be discussed later, the SDA transition needs to be completed during SCL low period. Data Validity (SDA data change timing waveform) SCL SDA Data change Note: Data change High-to-low and low-to-high change of SDA should be done during SCL low periods. 7 HN58X24128FPIAG/HN58X24256FPIAG Device Address (A0, A1, A2) Eight devices can be wired for one common data bus line as maximum. Device address pins are used to distinguish each device and device address pins should be connected to V CC or V SS . When device address code provided from SDA pin matches corresponding hard-wired device address pins A0 to A2, that one device can be activated. Pin Connections for A0 to A2 Pin connection Max connect Memory size number 128k bit 256k bit Note: A2 A1 1 A0 8 VCC/V SS * VCC/V SS VCC/V SS 8 VCC/V SS VCC/V SS VCC/V SS Note 1. “VCC/V SS ” means that device address pin should be connected to V CC or VSS. Write Protect (WP) When the Write Protect pin (WP) is high, the write protection feature is enabled and operates as shown in the following table. When the WP is low, write operation for all memory arrays are allowed. The read operation is always activated irrespective of the WP pin status. WP should be fixed high or low during operations since WP does not provide a latch function. Write Protect Area Write protect area WP pin status 128k bit 256k bit VIH Upper 1/8 (16k bit) Upper 1/8 (32k bit) VIL Normal read/write operation 8 HN58X24128FPIAG/HN58X24256FPIAG Functional Description Start Condition A high-to-low transition of the SDA with the SCL high is needed in order to start read, write operation. (See start condition and stop condition) Stop Condition A low-to-high transition of the SDA with the SCL high is a stop condition. The stand-by operation starts after a read sequence by a stop condition. In the case of write operation, a stop condition terminates the write data inputs and place the device in a internally-timed write cycle to the memories. After the internally-timed write cycle which is specified as tWC, the device enters a standby mode. (See write cycle timing) Start Condition and Stop Condition SCL SDA (in) Start condition Stop condition 9 HN58X24128FPIAG/HN58X24256FPIAG Acknowledge All addresses and data words are serially transmitted to and from in 8-bit words. The receiver sends a zero to acknowledge that it has received each word. This happens during ninth clock cycle. The transmitter keeps bus open to receive acknowledgment from the receiver at the ninth clock. In the write operation, EEPROM sends a zero to acknowledge after receiving every 8-bit words. In the read operation, EEPROM sends a zero to acknowledge after receiving the device address word. After sending read data, the EEPROM waits acknowledgment by keeping bus open. If the EEPROM receives zero as an acknowledge, it sends read data of next address. If the EEPROM receives acknowledgment "1" (no acknowledgment) and a following stop condition, it stops the read operation and enters a stand-by mode. If the EEPROM receives neither acknowledgment "0" nor a stop condition, the EEPROM keeps bus open without sending read data. Acknowledge Timing Waveform SCL SDA IN SDA OUT 10 1 2 8 9 Acknowledge out HN58X24128FPIAG/HN58X24256FPIAG Device Addressing The EEPROM device requires an 8-bit device address word following a start condition to enable the chip for a read or a write operation. The device address word consists of 4-bit device code, 3-bit device address code and 1-bit read/write(R/W) code. The most significant 4-bit of the device address word are used to distinguish device type and this EEPROM uses “1010” fixed code. The device address word is followed by the 3-bit device address code in the order of A2, A1, A0. The device address code selects one device out of all devices which are connected to the bus. This means that the device is selected if the inputted 3-bit device address code is equal to the corresponding hard-wired A2-A0 pin status. The eighth bit of the device address word is the read/write(R/W) bit. A write operation is initiated if this bit is low and a read operation is initiated if this bit is high. Upon a compare of the device address word, the EEPROM enters the read or write operation after outputting the zero as an acknowledge. The EEPROM turns to a stand-by state if the device code is not “1010” or device address code doesn’t coincide with status of the correspond hard-wired device address pins A0 to A2. Device Address Word Device address word (8-bit) Device code (fixed) 128k, 256k Note: 1 0 R/W code*1 Device address code 1 0 A2 A1 A0 R/W 1. R/W=“1” is read and R/W = “0” is write. 11 HN58X24128FPIAG/HN58X24256FPIAG Write Operations Byte Write: A write operation requires an 8-bit device address word with R/W = “0”. Then the EEPROM sends acknowledgment "0" at the ninth clock cycle. After these, the 128kbit and 256kbit EEPROMs receive 2 sequence 8-bit memory address words. Upon receipt of this memory address, the EEPROM outputs acknowledgment "0" and receives a following 8-bit write data. After receipt of write data, the EEPROM outputs acknowledgment "0". If the EEPROM receives a stop condition, the EEPROM enters an internally-timed write cycle and terminates receipt of SCL, SDA inputs until completion of the write cycle. The EEPROM returns to a standby mode after completion of the write cycle. Start 1010 W 2nd Memory address (n) Write data (n) D7 D6 D5 D4 D3 D2 D1 D0 128k to 256k 1st Memory address (n) a7 a6 a5 a4 a3 a2 a1 a0 Device address *1 a14 *2 a13 a12 a11 a10 a9 a8 Byte Write Operation ACK R/W Notes: 1. Don't care bits for 128k and 256k. 2. Don't care bit for 128k. 12 ACK ACK Stop HN58X24128FPIAG/HN58X24256FPIAG Page Write: The EEPROM is capable of the page write operation which allows any number of bytes up to 64 bytes to be written in a single write cycle. The page write is the same sequence as the byte write except for inputting the more write data. The page write is initiated by a start condition, device address word, memory address(n) and write data (Dn) with every ninth bit acknowledgment. The EEPROM enters the page write operation if the EEPROM receives more write data (Dn+1) instead of receiving a stop condition. The a0 to a5 address bits are automatically incremented upon receiving write data (Dn+1). The EEPROM can continue to receive write data up to 64 bytes. If the a0 to a5 address bits reaches the last address of the page, the a0 to a5 address bits will roll over to the first address of the same page and previous write data will be overwritten. Upon receiving a stop condition, the EEPROM stops receiving write data and enters internally-timed write cycle. Page Write Operation ACK R/W ACK ACK Write data (n+m) D5 D4 D3 D2 D1 D0 W Write data (n) D7 D6 D5 D4 D3 D2 D1 D0 Start 1010 2nd Memory address (n) a7 a6 a5 a4 a3 a2 a1 a0 128k to 256k 1st Memory address (n) *1 a14 *2 a13 a12 a11 a10 a9 a8 Device address ACK ACK Stop Notes: 1. Don't care bits for 128k and 256k. 2. Don't care bit for 128k. 13 HN58X24128FPIAG/HN58X24256FPIAG Acknowledge Polling: Acknowledge polling feature is used to show if the EEPROM is in a internally-timed write cycle or not. This features is initiated by the stop condition after inputting write data. This requires the 8-bit device address word following the start condition during a internally-timed write cycle. Acknowledge polling will operate R/W code = “0”. Acknowledgment “1” (no acknowledgment) shows the EEPROM is in a internally-timed write cycle and acknowledgment “0” shows that the internally-timed write cycle has completed. See Write Cycle Polling using ACK. Write Cycle Polling Using ACK Send write command Send stop condition to initiate write cycle Send start condition Send device address word with R/W = 0 ACK returned No Yes Next operation is addressing the memory No Yes Proceed write operation 14 Send memory address Send start condition Proceed random address read operation Send stop condition Send stop condition HN58X24128FPIAG/HN58X24256FPIAG Read Operation There are three read operations: current address read, random read, and sequential read. Read operations are initiated the same way as write operations with the exception of R/W = “1”. Current Address Read: The internal address counter maintains the last address accessed during the last read or write operation, with incremented by one. Current address read accesses the address kept by the internal address counter. After receiving a start condition and the device address word (R/W is “1”), the EEPROM outputs the 8-bit current address data from the most significant bit following acknowledgment “0” If the EEPROM receives acknowledgment “1” (no acknowledgment) and a following stop condition, the EEPROM stops the read operation and is turned to a standby state. In case the EEPROM have accessed the last address of the last page at previous read operation, the current address will roll over and returns to zero address. In case the EEPROM have accessed the last address of the page at previous write operation, the current address will roll over within page addressing and returns to the first address in the same page. The current address is valid while power is on. The current address after power on will be indefinite. The random read operation described below is necessary to define the memory address. Current Address Read Operation Device address Start 1010 R D7 D6 D5 D4 D3 D2 D1 D0 128k to 256k Read data (n+1) ACK R/W No ACK Stop 15 HN58X24128FPIAG/HN58X24256FPIAG Random Read: This is a read operation with defined read address. A random read requires a dummy write to set read address. The EEPROM receives a start condition, device address word (R/W=0) and memory address 2 × 8-bit sequentially. The EEPROM outputs acknowledgment “0” after receiving memory address then enters a current address read with receiving a start condition. The EEPROM outputs the read data of the address which was defined in the dummy write operation. After receiving acknowledgment “1”(no acknowledgment) and a following stop condition, the EEPROM stops the random read operation and returns to a standby state. Random Read Operation Start W ACK R/W ACK Device address 1010 Start ACK Dummy write Notes: 1. Don't care bits for 128k and 256k. 2. Don't care bit for 128k. 3. 2nd device address code (#) should be same as 1st (@). 16 Read data (n) # # # R R/W ACK D7 D6 D5 D4 D3 D2 D1 D0 1010 @@@ 2nd Memory address (n) a7 a6 a5 a4 a3 a2 a1 a0 128k to 256k 1st Memory address (n) *1 a14 *2 a13 a12 a11 a10 a9 a8 Device address No ACK Stop Currect address read HN58X24128FPIAG/HN58X24256FPIAG Sequential Read: Sequential reads are initiated by either a current address read or a random read. If the EEPROM receives acknowledgment “0” after 8-bit read data, the read address is incremented and the next 8-bit read data are coming out. This operation can be continued as long as the EEPROM receives acknowledgment “0”. The address will roll over and returns address zero if it reaches the last address of the last page. The sequential read can be continued after roll over. The sequential read is terminated if the EEPROM receives acknowledgment “1” (no acknowledgment) and a following stop condition. Sequential Read Operation ACK R/W ACK ACK ACK D5 D4 D3 D2 D1 D0 R Read data (n+1) Read data (n+2) Read data (n+m) D7 D6 D5 D4 D3 D2 D1 D0 Start 1010 Read data (n) D7 D6 D5 D4 D3 D2 D1 D0 128k to 256k D7 D6 D5 D4 D3 D2 D1 D0 Device address No ACK Stop 17 HN58X24128FPIAG/HN58X24256FPIAG Notes Data Protection at VCC On/Off When VCC is turned on or off, noise on the SCL and SDA inputs generated by external circuits (CPU, etc) may act as a trigger and turn the EEPROM to unintentional program mode. To prevent this unintentional programming, this EEPROM have a power on reset function. Be careful of the notices described below in order for the power on reset function to operate correctly. • SCL and SDA should be fixed to VCC or VSS during VCC on/off. Low to high or high to low transition during VCC on/off may cause the trigger for the unintentional programming. • VCC should be turned off after the EEPROM is placed in a standby state. • VCC should be turned on from the ground level(VSS ) in order for the EEPROM not to enter the unintentional programming mode. • VCC turn on speed should be longer than 10 us. Write/Erase Endurance and Data Retention Time The endurance is 10 5 cycles in case of page programming and 104 cycles in case of byte programming (1% cumulative failure rate). The data retention time is more than 10 years when a device is page-programmed less than 104 cycles. Noise Suppression Time This EEPROM have a noise suppression function at SCL and SDA inputs, that cut noise of width less than 50 ns. Be careful not to allow noise of width more than 50 ns. 18 HN58X24128FPIAG/HN58X24256FPIAG Package Dimensions HN58X24128FPIAG/HN58X24256FPIAG (FP-8DB) Unit: mm 3.90 4.89 5.15 Max 5 8 0.69 Max 0.034 *0.22 +– 0.017 0.20 ± 0.03 4 1.73 Max 1 6.02 ± 0.18 1.06 *0.42 +0.063 –0.064 0.40 ± 0.06 0.114 0.14 +– 0.038 0° – 8° 1.27 0.289 0.60 +– 0.194 0.10 0.25 M *Dimension including the plating thickness Base material dimension Hitachi Code JEDEC EIAJ Mass (reference value) FP-8DB — — 0.08 g 19 HN58X24128FPIAG/HN58X24256FPIAG Cautions 1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party’s rights, including intellectual property rights, in connection with use of the information contained in this document. 2. Products and product specifications may be subject to change without notice. Confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However, contact Hitachi’s sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as failsafes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the Hitachi product. 5. This product is not designed to be radiation resistant. 6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from Hitachi. 7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi semiconductor products. Hitachi, Ltd. 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(Taipei Branch Office) 4/F, No. 167, Tun Hwa North Road Hung-Kuo Building Taipei (105), Taiwan Tel : <886>-(2)-2718-3666 Fax : <886>-(2)-2718-8180 Telex : 23222 HAS-TP URL : http://www.hitachi.com.tw Hitachi Asia (Hong Kong) Ltd. Group III (Electronic Components) 7/F., North Tower World Finance Centre, Harbour City, Canton Road Tsim Sha Tsui, Kowloon Hong Kong Tel : <852>-(2)-735-9218 Fax : <852>-(2)-730-0281 URL : http://semiconductor.hitachi.com.hk Copyright © Hitachi, Ltd., 2001. All rights reserved. Printed in Japan. Colophon 4.0 20