RENESAS R1EX24512BTAS0A

Preliminary Datasheet
R1EX24512BSAS0A
R1EX24512BTAS0A
Two-wire serial interface
512k EEPROM (64-kword × 8-bit)
R10DS0025EJ0001
Rev.0.01
Sep, 01, 2010
Description
R1EX24xxx series are two-wire serial interface EEPROM (Electrically Erasable and Programmable ROM). They
realize high speed, low power consumption and a high level of reliability by employing advanced MONOS memory
technology and CMOS process and low voltage circuitry technology. They also have a 128-byte page programming
function to make their write operation faster.
Note: Renesas Electronics’ serial EEPROM are authorized for using consumer applications such as cellular phone,
camcorders, audio equipment. Therefore, please contact Renesas Electronics’ sales office before using
industrial applications such as automotive systems, embedded controllers, and meters.
Features
•
•
•
•
•
•
•
•
•
•
•
•
Single supply: 1.8 V to 5.5 V
Two-wire serial interface (I2C serial bus)
Clock frequency: 1 MHz (2.5 V to 5.5 V) / 400 kHz (1.8 V to 5.5 V)
Power dissipation:
 Standby: 2 µA (max)
 Active (Read): 1 mA (max)
 Active (Write): 5 mA (max)
Automatic page write: 128-byte/page
Write cycle time: 5 ms
Endurance: 1,000k Cycles @25°C
Data retention: 100 Years @25°C
Small size packages: SOP-8pin , TSSOP 8-pin
Shipping tape and reel
 SOP 8-pin: 2,500 IC/reel
 TSSOP 8-pin: 3,000 IC/reel
Temperature range: −40 to +85°C
Lead free products.
Preliminary: The specifications of this device are subject to change without notice. Please contact your nearest
Renesas Electronics’ Sales Dept. regarding specifications.
R10DS0025EJ0001 Rev.0.01
Sep, 01, 2010
Page 1 of 17
R1EX24512BSAS0A/R1EX24512BTAS0A
Ordering Information
Type No.
Internal organization Operating voltage
Frequency
R1EX24512BSAS0A 512k bit
1.8 V to 5.5 V
400 kHz
(65536 × 8-bit)
2.5 V to 5.5 V
1 MHz
R1EX24512BTAS0A 512k bit
(65536 × 8-bit)
1.8 V to 5.5 V
400 kHz
2.5 V to 5.5 V
1 MHz
Package
150 mil 8-pin plastic SOP
PRSP0008DF-B(FP-8DBV)
Lead free
8-pin plastic TSSOP
PTSP0008JC-B(TTP-8DAV)
Lead free
Pin Arrangement
8-pin SOP /8-pin TSSOP
A0
1
8
VCC
A1
2
7
WP
A2
3
6
SCL
VSS
4
5
SDA
(Top view)
Pin Description
Pin name
Function
A0 to A2
Device address
SCL
Serial clock input
SDA
Serial data input/output
WP
Write protect
VCC
Power supply
VSS
Ground
Block Diagram
High voltage generator
A0, A1, A2
SCL
Control
logic
X decoder
WP
Address generator
VSS
Memory array
Y decoder
VCC
Y-select & Sense amp.
SDA
Serial-parallel converter
R10DS0025EJ0001 Rev.0.01
Sep, 01, 2010
Page 2 of 17
R1EX24512BSAS0A/R1EX24512BTAS0A
Absolute Maximum Ratings
Symbol
Value
Unit
Supply voltage relative to VSS
Parameter
VCC
−0.6 to +7.0
V
Input voltage relative to VSS
Vin
−0.3 to VCC +0.3
V
Topr
−40 to +85
°C
Tstg
−55 to +125
°C
Operating temperature range*
1
Storage temperature range
Notes: 1. Including electrical characteristics and data retention.
DC Operating Conditions
Parameter
Supply voltage
Input high voltage
Input low voltage
Operating temperature
Symbol
Min
Typ
Max
Unit
VCC
1.8

5.5
V
VSS
0
0
0
V
VIH
VCC × 0.7

VCC + 0.3
V
VIL
−0.3

VCC × 0.3
V
Topr
−40

+85
°C
DC Characteristics
(Ta = −40 to +85°C, VCC = 1.8 V to 5.5 V)
Parameter
Input leakage current
Output leakage current
Standby VCC current
Read VCC current
Write VCC current
Output low voltage
Symbol
Min
Typ
Max
Unit
ILI
ILO
ISB
ICC1
ICC2
VOL2
VOL1









1.0




2.0
2.0
2.0
1.0
5.0
0.4
0.2
µA
µA
µA
mA
mA
V
V
Test conditions
VCC = 5.5 V, Vin = 0 to 5.5 V
VCC = 5.5 V, Vout = 0 to 5.5 V
Vin = VSS or VCC
VCC = 5.5 V, Read at 400 kHz
VCC = 5.5 V, Write at 400 kHz
VCC = 2.7 to 5.5 V, IOL = 3.0 mA
VCC = 1.8 to 2.7 V, IOL = 1.5 mA
Capacitance
(Ta = +25°C, f = 1 MHz)
Test conditions
Parameter
Symbol
Min
Typ
Max
Unit
Input capacitance (A0 to A2, SCL, WP)
Cin*1


6.0
pF
Vin = 0 V
Output capacitance (SDA)
CI/O*1


6.0
pF
Vout = 0 V
Note: 1. Not 100% tested.
Memory cell characteristics
(VCC = 1.8 V to 5.5 V)
Ta=25°C
Ta=85°C
Notes
Endurance
1,000k Cycles min.
100k Cycles min
1
Data retention
100 Years min.
10 Years min.
1
Notes: 1. Not 100% tested.
R10DS0025EJ0001 Rev.0.01
Sep, 01, 2010
Page 3 of 17
R1EX24512BSAS0A/R1EX24512BTAS0A
AC Characteristics
(Ta = −40 to +85°C, VCC = 1.8 to 5.5 V)
Test Conditions
• Input pules levels:
 VIL = 0.2 × VCC
 VIH = 0.8 × VCC
• Input rise and fall time: ≤ 20 ns
• Input and output timing reference levels: 0.5 × VCC
• Output load: TTL Gate + 100 pF
Parameter
Clock frequency
Clock pulse width low
Clock pulse width high
Noise suppression time
Access time
Bus free time for next mode
Start hold time
Start setup time
Data in hold time
Data in setup time
Input rise time
Input fall time
Stop setup time
Data out hold time
Write protect hold time
Write protect setup time
Write cycle time
Symbol
fSCL
tLOW
tHIGH
tI
tAA
tBUF
tHD.STA
tSU.STA
tHD.DAT
tSU.DAT
tR
tF
tSU.STO
tDH
tHD.WP
tSU.WP
tWC
VCC = 1.8 V to 5.5 V
Min
Typ
Max


400
1200


600




50
100

900
1200


600


600


0
100


600
50
1200
0












300
300




5
VCC = 2.5 V to 5.5 V
Min
Typ
Max


1000
600


400




50
100

550
500


250


250


Unit
kHz
ns
ns
ns
ns
ns
ns
ns









ns
ns
ns
ns
ns
ns
ns
ns
ms
0
100


250
50
600
0



300
100




5
Notes
1
1
1
2
Notes: 1. Not 100% tested.
2. tWC is the time from a stop condition to the end of internally controlled write cycle.
R10DS0025EJ0001 Rev.0.01
Sep, 01, 2010
Page 4 of 17
R1EX24512BSAS0A/R1EX24512BTAS0A
Timing Waveforms
Bus Timing
tF
tHIGH
1/fSCL
tLOW
tR
SCL
tSU.STA
tHD.DAT
tSU.DAT
tHD.STA
tSU.STO
SDA
(in)
tBUF
tAA
tDH
SDA
(out)
tSU.WP
tHD.WP
WP
Write Cycle Timing
Stop condition
Start condition
SCL
D0 in
SDA
Write data
(Address (n))
R10DS0025EJ0001 Rev.0.01
Sep, 01, 2010
ACK
tWC
(Internally controlled)
Page 5 of 17
R1EX24512BSAS0A/R1EX24512BTAS0A
Pin Function
Serial Clock (SCL)
The SCL pin is used to control serial input/output data timing. The SCL input is used to positive edge clock data into
EEPROM device and negative edge clock data out of each device. Maximum clock rate is 1 MHz.
Serial Input/Output Data (SDA)
The SDA pin is bidirectional for serial data transfer. The SDA pin needs to be pulled up by resistor as that pin is opendrain driven structure. Use proper resistor value for your system by considering VOL, IOL and the SDA pin capacitance.
Except for a start condition and a stop condition which will be discussed later, the SDA transition needs to be completed
during the SCL low period.
Data Validity (SDA data change timing waveform)
SCL
SDA
Data
change
Note:
Data
change
High-to-low and low-to-high change of SDA should be done during the SCL low period.
R10DS0025EJ0001 Rev.0.01
Sep, 01, 2010
Page 6 of 17
R1EX24512BSAS0A/R1EX24512BTAS0A
Device Address (A0, A1, A2)
Eight devices can be wired for one common data bus line as maximum. Device address pins are used to distinguish
each device and device address pins should be connected to VCC or VSS. When device address code provided from SDA
pin matches corresponding hard-wired device address pins A0 to A2, that one device can be activated.
Pin Connections for A0 to A2
Pin connection
Memory size Max connect number
512k bit
Note:
8
A2
A1
A0
VCC/VSS *1
VCC/VSS *1
VCC/VSS *1
Note
1. During floating, "VCC/VSS" are fixed to VSS.
Write Protect (WP)
When the Write Protect pin (WP) is high, the write protection feature is enabled and operates as shown in the following
table. Also, acknowledgment "0" is outputted after inputting device address and memory address. After inputting write
data, acknowledgment "1"(NO ACK) is outputted.
When the WP is low, write operation for all memory arrays are allowed. The read operation is always activated
irrespective of the WP pin status.
Write Protect Area
Write protect area
WP pin status
512k bit
VIH
Full (512k bit)
VIL
Normal read/write operation
R10DS0025EJ0001 Rev.0.01
Sep, 01, 2010
Page 7 of 17
R1EX24512BSAS0A/R1EX24512BTAS0A
Functional Description
Start Condition
A high-to-low transition of the SDA with the SCL high is needed in order to start read, write operation (See start
condition and stop condition).
Stop Condition
A low-to-high transition of the SDA with the SCL high is a stop condition. The stand-by operation starts after a read
sequence by a stop condition. In the case of write operation, a stop condition terminates the write data inputs and place
the device in a internally-timed write cycle to the memories. After the internally-timed write cycle which is specified as
tWC, the device enters a standby mode (See write cycle timing).
Start Condition and Stop Condition
SCL
SDA
(in)
Start condition
Stop condition
Acknowledge
All addresses and data words are serially transmitted to and from in 8-bit words. The receiver sends a zero to
acknowledge that it has received each word. This happens during ninth clock cycle. The transmitter keeps bus open to
receive acknowledgment from the receiver at the ninth clock. In the write operation, EEPROM sends a zero to
acknowledge after receiving every 8-bit words. In the read operation, EEPROM sends a zero to acknowledge after
receiving the device address word. After sending read data, the EEPROM waits acknowledgment by keeping bus open.
If the EEPROM receives zero as an acknowledge, it sends read data of next address. If the EEPROM receives
acknowledgment "1" (no acknowledgment) and a following stop condition, it stops the read operation and enters a
stand-by mode. If the EEPROM receives neither acknowledgment "0" nor a stop condition, the EEPROM keeps bus
open without sending read data.
Acknowledge Timing Waveform
SCL
SDA IN
1
2
8
9
Acknowledge
out
SDA OUT
R10DS0025EJ0001 Rev.0.01
Sep, 01, 2010
Page 8 of 17
R1EX24512BSAS0A/R1EX24512BTAS0A
Device Addressing
The EEPROM device requires an 8-bit device address word following a start condition to enable the chip for a read or a
write operation. The device address word consists of 4-bit device code, 3-bit device address code and 1-bit
read/write(R/W) code. The most significant 4-bit of the device address word are used to distinguish device type and
this EEPROM uses “1010” fixed code. The device code is followed by the 3-bit device address code. The device
address code selects one device out of all devices which are connected to the bus. This means that the device is selected
if the inputted 3-bit device address code is equal to the corresponding hard-wired A2-A0 pin status. The eighth bit of
the device address word is the read/write(R/W) bit. A write operation is initiated if this bit is low and a read operation
is initiated if this bit is high. Upon a compare of the device address word, the EEPROM enters the read or write
operation after outputting the zero as an acknowledge. The EEPROM turns to a stand-by state if the device code is not
“1010” or device address code doesn’t coincide with status of the correspond hard-wired device address pins A0 to A2.
Device Address Word
Device address word (8-bit)
Device code (fixed)
512k
1
0
1
R/W code*1
Device address code
0
A2
A1
A0
R/W
Notes: 1. R/W=“1” is read and R/W = “0” is write.
R10DS0025EJ0001 Rev.0.01
Sep, 01, 2010
Page 9 of 17
R1EX24512BSAS0A/R1EX24512BTAS0A
Write Operations(WP=Low)
Byte Write: (Write operation during WP=Low status)
A write operation requires an 8-bit device address word with R/W = “0”. Then the EEPROM sends acknowledgment
"0" at the ninth clock cycle. After these, the EEPROMs receive 2 sequence 8-bit memory address words. Upon receipt
of this memory address, the EEPROM outputs acknowledgment "0" and receives a following 8-bit write data. After
receipt of write data, the EEPROM outputs acknowledgment "0". If the EEPROM receives a stop condition, the
EEPROM enters an internally-timed write cycle and terminates receipt of SCL, SDA inputs until completion of the
write cycle. The EEPROM returns to a standby mode after completion of the write cycle.
Byte Write Operation
1010
W
2nd Memory
address (n)
Write data (n)
D7
D6
D5
D4
D3
D2
D1
D0
512k
1st Memory
address (n)
a7
a6
a5
a4
a3
a2
a1
a0
Device
address
a15
a14
a13
a12
a11
a10
a9
a8
WP
ACK
ACK
R/W
Start
ACK
ACK
Stop
Page Write:
The EEPROM is capable of the page write operation which allows any number of bytes up to 128 bytes to be written in
a single write cycle. The page write is the same sequence as the byte write except for inputting the more write data.
The page write is initiated by a start condition, device address word, memory address(n) and write data (Dn) with every
ninth bit acknowledgment. The EEPROM enters the page write operation if the EEPROM receives more write data
(Dn+1) instead of receiving a stop condition. The a0 to a6 address bits are automatically incremented upon receiving
write data (Dn+1). The EEPROM can continue to receive write data up to 128 bytes. If the a0 to a6 address bits
reaches the last address of the page, the a0 to a6 address bits will roll over to the first address of the same page and
previous write data will be overwritten. Upon receiving a stop condition, the EEPROM stops receiving write data and
enters internally-timed write cycle.
Page Write Operation
WP
Start
R10DS0025EJ0001 Rev.0.01
Sep, 01, 2010
ACK
R/W
ACK
ACK
Write data (n+m)
D5
D4
D3
D2
D1
D0
W
Write data (n)
D7
D6
D5
D4
D3
D2
D1
D0
1010
2nd Memory
address (n)
a7
a6
a5
a4
a3
a2
a1
a0
512k
1st Memory
address (n)
a15
a14
a13
a12
a11
a10
a9
a8
Device
address
ACK
ACK
Stop
Page 10 of 17
R1EX24512BSAS0A/R1EX24512BTAS0A
Write Operations(WP=High)
Byte Write: (Write operation during WP=High status)
A write operation requires an 8-bit device address word with R/W = “0”. Then the EEPROM sends acknowledgment
"0" at the ninth clock cycle. After these, the 512kbit EEPROM receives 2 sequence 8-bit memory address words.
Upon receipt of this memory address, the EEPROM outputs acknowledgment "0". After receipt of 8-bit write data, the
EEPROM outputs acknowledgment "1"(NO ACK). Then the EEPROM write operations are not allowed.
Byte Write Operation
1010
W
2nd Memory
address (n)
Write data (n)
D7
D6
D5
D4
D3
D2
D1
D0
512k
1st Memory
address (n)
a7
a6
a5
a4
a3
a2
a1
a0
Device
address
a15
a14
a13
a12
a11
a10
a9
a8
WP
ACK
ACK
R/W
Start
ACK
No ACK
Stop
Page Write:
The page write is the same sequence as the byte write. The page write is initiated by a start condition, device address
word and memory address(n) with every ninth bit acknowledgment"0". But after inputting write data(Dn) , the
EEPROM outputs acknowledgment "1"(NO ACK). Then the EEPROM write operations are not allowed.
Page Write Operation
WP
Start
R10DS0025EJ0001 Rev.0.01
Sep, 01, 2010
ACK
R/W
ACK
ACK
No ACK
No ACK
Write data (n+m)
D5
D4
D3
D2
D1
D0
W
Write data (n)
D7
D6
D5
D4
D3
D2
D1
D0
1010
2nd Memory
address (n)
a7
a6
a5
a4
a3
a2
a1
a0
512k
1st Memory
address (n)
a15
a14
a13
a12
a11
a10
a9
a8
Device
address
Stop
Page 11 of 17
R1EX24512BSAS0A/R1EX24512BTAS0A
Acknowledge Polling:
Acknowledge polling feature is used to show if the EEPROM is in a internally-timed write cycle or not. This feature is
initiated by the stop condition after inputting write data. This requires the 8-bit device address word following the start
condition during a internally-timed write cycle. Acknowledge polling will operate when the R/W code = “0”.
Acknowledgment “1” (no acknowledgment) shows the EEPROM is in a internally-timed write cycle and
acknowledgment “0” shows that the internally-timed write cycle has completed. See Write Cycle Polling using ACK.
Write Cycle Polling Using ACK
Send
write command
Send
stop condition
to initiate write cycle
Send
start condition
Send
device address word
with R/W = 0
ACK
returned
No
Yes
Next operation is
addressing the memory
No
Yes
Proceed write operation
R10DS0025EJ0001 Rev.0.01
Sep, 01, 2010
Send
memory address
Send
start condition
Proceed random address
read operation
Send
stop condition
Send
stop condition
Page 12 of 17
R1EX24512BSAS0A/R1EX24512BTAS0A
Read Operation
There are three read operations: current address read, random read, and sequential read. Read operations are initiated
the same way as write operations with the exception of R/W = “1”.
Current Address Read:
The internal address counter maintains the last address accessed during the last read or write operation, with
incremented by one. Current address read accesses the address kept by the internal address counter. After receiving a
start condition and the device address word (R/W is “1”), the EEPROM outputs the 8-bit current address data from the
most significant bit following acknowledgment “0”. If the EEPROM receives acknowledgment “1” (no
acknowledgment) and a following stop condition, the EEPROM stops the read operation and is turned to a standby state.
In case the EEPROM has accessed the last address of the last page at previous read operation, the current address will
roll over and returns to zero address. In case the EEPROM has accessed the last address of the page at previous write
operation, the current address will roll over within page addressing and returns to the first address in the same page.
The current address is valid while power is on. The current address after power on will be indefinite. The random read
operation described below is necessary to define the memory address.
Current Address Read Operation
Device
address
Start
R10DS0025EJ0001 Rev.0.01
Sep, 01, 2010
1010
Read data (n+1)
R
D7
D6
D5
D4
D3
D2
D1
D0
512k
ACK
R/W
No ACK
Stop
Page 13 of 17
R1EX24512BSAS0A/R1EX24512BTAS0A
Random Read:
This is a read operation with defined read address. A random read requires a dummy write to set read address. The
EEPROM receives a start condition, device address word (R/W=0) and memory address 2 × 8-bit sequentially. The
EEPROM outputs acknowledgment “0” after receiving memory address then enters a current address read with
receiving a start condition. The EEPROM outputs the read data of the address which was defined in the dummy write
operation. After receiving acknowledgment “1”(no acknowledgment) and a following stop condition, the EEPROM
stops the random read operation and returns to a standby state.
Random Read Operation
W
ACK
R/W
Start
ACK
Device
address
1010
Start
ACK
Dummy write
Read data (n)
# # #
R
R/W
ACK
D7
D6
D5
D4
D3
D2
D1
D0
1010
@@@
2nd Memory
address (n)
a7
a6
a5
a4
a3
a2
a1
a0
512k
1st Memory
address (n)
a15
a14
a13
a12
a11
a10
a9
a8
Device
address
No ACK
Stop
Current address read
Notes: 1. 2nd device address code (#) should be same as 1st (@).
Sequential Read:
Sequential reads are initiated by either a current address read or a random read. If the EEPROM receives
acknowledgment “0” after 8-bit read data, the read address is incremented and the next 8-bit read data are coming out.
This operation can be continued as long as the EEPROM receives acknowledgment “0”. The address will roll over and
returns address zero if it reaches the last address of the last page. The sequential read can be continued after roll over.
The sequential read is terminated if the EEPROM receives acknowledgment “1” (no acknowledgment) and a following
stop condition.
Sequential Read Operation
Start
R10DS0025EJ0001 Rev.0.01
Sep, 01, 2010
ACK
R/W
ACK
ACK
ACK
D5
D4
D3
D2
D1
D0
R
Read data (n+1) Read data (n+2) Read data (n+m)
D7
D6
D5
D4
D3
D2
D1
D0
1010
D7
D6
D5
D4
D3
D2
D1
D0
512k
Read data (n)
D7
D6
D5
D4
D3
D2
D1
D0
Device
address
No ACK
Stop
Page 14 of 17
R1EX24512BSAS0A/R1EX24512BTAS0A
Notes
Data Protection at VCC On/Off
When VCC is turned on or off, noise on the SCL and SDA inputs generated by external circuits (CPU, etc) may act as a
trigger and turn the EEPROM to unintentional program mode. To prevent this unintentional programming, this
EEPROM has a power on reset function. Be careful of the notices described below in order for the power on reset
function to operate correctly.
• SCL and SDA should be fixed to VCC or VSS during VCC on/off. Low to high or high to low transition during VCC
on/off may cause the trigger for the unintentional programming.
• VCC should be turned off after the EEPROM is placed in a standby state.
• VCC should be turned on from the ground level(VSS) in order for the EEPROM not to enter the unintentional
programming mode.
• VCC turn on rate should be slower than 2 µs/V.
Noise Suppression Time
This EEPROM have a noise suppression function at SCL and SDA inputs, that cut noise of width less than 50 ns. Be
careful not to allow noise of width more than 50 ns.
R10DS0025EJ0001 Rev.0.01
Sep, 01, 2010
Page 15 of 17
R1EX24512BSAS0A/R1EX24512BTAS0A
Package Dimensions
R1EX24512BSAS0A (PRSP0008DF-B / Previous Code: FP-8DBV)
JEITA Package Code
P-SOP8-3.9x4.89-1.27
RENESAS Code
PRSP0008DF-B
*1
Previous Code
FP-8DBV
MASS[Typ.]
0.08g
D
8
F
NOTE)
1. DIMENSIONS"*1 (Nom)"AND"*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION"*3"DOES NOT
INCLUDE TRIM OFFSET.
5
*2
c
E
HE
bp
Index mark
Terminal cross section
( Ni/Pd/Au plating )
Reference Dimension in Millimeters
Symbol
4
1
Z
e
*3
bp
x
M
A
L1
A1
θ
L
y
Detail F
R10DS0025EJ0001 Rev.0.01
Sep, 01, 2010
D
E
A2
A1
A
bp
b1
c
c1
θ
HE
e
x
y
Z
L
L1
Min Nom Max
4.89 5.15
3.90
0.102 0.14 0.254
1.73
0.35 0.40 0.45
0.15 0.20 0.25
0°
8°
5.84 6.02 6.20
1.27
0.25
0.10
0.69
0.406 0.60 0.889
1.06
Page 16 of 17
R1EX24512BSAS0A/R1EX24512BTAS0A
R1EX24512BTAS0A (PTSP0008JC-B / Previous Code: TTP-8DAV)
JEITA Package Code
P-TSSOP8-4.4x3-0.65
RENESAS Code
PTSP0008JC-B
*1
Previous Code
TTP-8DAV
MASS[Typ.]
0.034g
D
8
F
5
NOTE)
1. DIMENSIONS"*1 (Nom)"AND"*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION"*3"DOES NOT
INCLUDE TRIM OFFSET.
c
*2
E
HE
bp
Terminal cross section
( Ni/Pd/Au plating )
Reference Dimension in Millimeters
Symbol
Index mark
L1
1
*3
bp
x
M
θ
A1
A
Z
4
e
L
Detail F
y
R10DS0025EJ0001 Rev.0.01
Sep, 01, 2010
D
E
A2
A1
A
bp
b1
c
c1
θ
HE
e
x
y
Z
L
L1
Min Nom Max
3.00 3.30
4.40
0.03 0.07 0.10
1.10
0.15 0.20 0.25
0.10 0.15 0.20
0°
8°
6.20 6.40 6.60
0.65
0.13
0.10
0.805
0.40 0.50 0.60
1.00
Page 17 of 17
Revision History
Rev.
0.01
Date
Sep, 01. 2010
R1EX24512BSAS0A/R1EX24512BTAS0A Data Sheet
Description
Summary
Page
Initial issue
All trademarks and registered trademarks are the property of their respective owners.
C-1
Notice
1.
All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas
Electronics products listed herein, please confirm the latest product information with a Renesas Electronics sales office. Also, please pay regular and careful attention to additional and different information to
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(Note 1)
"Renesas Electronics" as used in this document means Renesas Electronics Corporation and also includes its majority-owned subsidiaries.
(Note 2)
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Refer to "http://www.renesas.com/" for the latest and detailed information.
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