Preliminary Datasheet LP6342 1.5MHz, 2A Step-down Converter Features General Description The LP6342 is a 1.5MHz constant frequency current mode PWM step-down converter. It is ideal for portable equipment requiring very high current up to 2A from single-cell Lithium-ion batteries while still achieving over 90% efficiency during peak load conditions. The LP6342 also can run at 100% duty cycle for low dropout operation, extending battery life in portable systems while light load operation provides very low output ripple for noise sensitive applications. The LP6342 can supply up to 2A output load current from a 2.5V to 5.5V input voltage and the output voltage can be regulated as low as 0.6V. The high switching frequency minimizes the size of external components while keeping switching losses low. The internal slope compensation setting allows the device to operate with smaller inductor values to optimize size and provide efficient operation. The LP6342 is available with adjustable (0.6V to VIN) output voltage. The device is available in a Pb-free, 3mm x 3mm 10-lead TDFN or MSOP-10,SOP8(EP) package and is rated over the-40°C to +85°C temperature range. Applications Order Information LP6342 Input Voltage Range: 2.5V to 5.5V Output Voltage Range: 0.6V to VIN 2A Output Current Low R(DSON) Internal Switches:130mΩ High Efficiency :Up to 95% 100% Duty Cycle in Dropout Low Shutdown Current: < 1 u A 1.5MHz Switching Frequency Soft star Function Short Circuit Protection Thermal Fault Protection 3 m m × 3 m m TDFN-10 or MSOP-10,SOP8(EP) Package RoHS Compliant and 100% Lead (Pb)-Free Portable Instruments DSP Core Supplies Cellular Phone and Smart mobile phone PDA GPS Applications Marking Information □ □ □ Please see website:www.lowpowersemi.com. F: Pb-Free Package Type QV: TDFN-10 MS: MSOP-10 SP:SOP8(EP) Typical Application Circuit 2 1 Vin Vin EN LP6342-03 Version 1.3 Datasheet SW SW 6 4 9 10 C1 10uF 3 LP6342 GND PGOOD GND GND VIN Oct.-2011 FB 7 8 L1 Vout_2A 2.2uH R1 5 C2 22uF Vout=(R1/R2+1)*VFB R2 www.lowpowersemi.com 1 / 15 Preliminary Datasheet LP6342 Functional Pin Description TOP VIEW VIN 2 VIN 3 LP6342 11 GND 10 GND EN 1 9 GND VIN 2 8 SW VIN 3 LPS 1 LP6342 EN 10 GND 9 GND 8 SW PGOOD 4 7 SW PGOOD 4 7 SW FB 5 6 GND FB 5 6 GND EN 1 VIN 2 VIN 3 FB 4 8 GND LP6342 7 GND 9 PGND 6 SW 5 GND ESOP8 MSOP10 TDFN-10 Pi n Desc ript ion Pin NO PIN TDFN-10 MSOP10 ESOP8 1 1 2, 3 2, 3 4 9,10 4 9,10 5 5 6 6 7, 8 7, 8 11 11 1 2,3 5,7,8 4 DESCRIPTION EN Enable pin. Active high. In shutdown, all functions are disabled drawing <1μA supply current. Do not leave EN floating. Vin Supply Input. Power supply input pin. Must be closely decoupled to AGND with a 10μF or greater ceramic capacitor. Power good output. PGOOD GND/PGND FB GND Feedback Input. Connect FB to the center point of the external resistor divider. Normal voltage for this pin is 0.6V. Ground. SW Switch Mode Connection to Inductor. This pin connects to the drains of the internal main and synchronous power MOSFET switches. PAD Ground pad. 6 9 Ground. Function Block Diagram LP6342-03 Version 1.3 Datasheet Oct.-2011 www.lowpowersemi.com 2 / 15 Preliminary Datasheet LP6342 Absolute Maximum Ratings Input Voltage to GND ----------------------------------------------------------------------------------------- SW to GND (VSW) -------------------------------------------------------------------------- -0.3V to VIN +0.3V FB to GND (VFB) ---------------------------------------------------------------------------- -0.3V to VIN +0.3V EN to GND (VEN) ------------------------------------------------------------------------------------ -0.3V to 6V Operating Temperature Range (TA) --------------------------------------------------------------- Storage Temperature Range (TJ) ----------------------------------------------------------------- Maximum Soldering Temperature (at leads, 10sec) ------------------------------------------------------ 260℃ ESD Susceptibility HBN(Human Body Mode) ----------------------------------------------------- 2KV MM(Machine Mode) ------------------------------------------------------------ 200V 6V -40℃ to 85℃ -65℃ to 150℃ Electrical Characteristics (VIN =VEN, Typical values are TA=25℃ ) Symbol Parameter Conditions Input Voltage VIN Min. 2.5 LP6342 Typ. Max. 5.5 Unit V ΔVLINEREG/ΔVIN Line Regulation VIN = 2.5V to 5.5V, IOUT = 10mA 0.15 %/v ΔVLOADREG/ΔIOUT Load Regulation Output Voltage Range VOUT Iout=10mA to 2000mA 0.25 %/A 0.6 IQ Quiescent Current VFB=0V,VIN=4.2V ISHDN ILIM Shutdown Current EN = GND RDS(ON)H RDS(ON)L ISWLEAK VFB VIN 70 V µA 1 µA P-Channel Current Limit 3.5 High-Side Switch On Resistance 130 m Low-Side Switch On Resistance 100 m SW Leakage Current VEN=0V, VSW=0 or 5V, VIN=5V Feedback Threshold Voltage Accuracy VIN=2.5to5.5V, IOUT = 10 to 2000mA 0.585 0.6 A 1 µA 0.615 V FB Leakage Current VOUT = 1 .0V 30 nA Oscillator Frequency VFB=0.6V 1.5 MHz TS Startup Time From Enable to Output Regulation 120 µs TSD Over-Temperature Shutdown Threshold 150 ℃ VEN(L) Enable Threshold Low VEN(H) Enable Threshold High IFB FOSC IEN Note: 0.3 Input Low Current VIN = VEN = 5.0V Output Voltage: Vout = 0.6 x (1+R2/R1) Volts; LP6342-03 Version 1.3 Datasheet Oct.-2011 1.0 -1 www.lowpowersemi.com 0.4 V 1.5 V 1 µA 3 / 15 Preliminary Datasheet LP6342 Typical Operating Characteristics LP6342-03 Version 1.3 Datasheet Oct.-2011 www.lowpowersemi.com 4 / 15 Preliminary Datasheet LP6342-03 Version 1.3 Datasheet Oct.-2011 www.lowpowersemi.com LP6342 5 / 15 Preliminary Datasheet LP6342-03 Version 1.3 Datasheet Oct.-2011 www.lowpowersemi.com LP6342 6 / 15 Preliminary Datasheet LP6342-03 Version 1.3 Datasheet Oct.-2011 www.lowpowersemi.com LP6342 7 / 15 Preliminary Datasheet LP6342-03 Version 1.3 Datasheet Oct.-2011 www.lowpowersemi.com LP6342 8 / 15 Preliminary Datasheet LP6342 Functional Description Soft Start / Enable The LP6342 is a high output current monolithic switch-mode step-down DC-DC converter. The device operates at a fixed 1.5MHz switching frequency, and uses a slope compensated current mode architecture. This step-down DC-DC converter can supply up to 2A output current at VIN = 3V and has an input voltage range from 2.5V to 5.5V. It minimizes external component size and optimizes efficiency at the heavy load range. The slope compensation allows the device to remain stable over a wider range of inductor values so that smaller values (1μH to 4.7μH) with lower DCR can be used to achieve higher efficiency. Apart from the small bypass input capacitor, only a small L-C filter is required at the output. The device can be programmed with external feedback to any voltage, ranging from 0.6V to near the input volt-age. It uses internal MOSFETs to achieve high efficiency and can generate very low output voltages by using an internal reference of 0.6V. At dropout, the converter duty cycle increases to 100% and the output voltage tracks the input voltage minus the low RDS(ON) drop of the P-channel high-side MOSFET and the inductor DCR. The internal error amplifier and compensation provides excellent transient response, load and line regulation. Internal soft start eliminates any output voltage over-shoot when the enable or the input voltage is applied. Soft start limits the current surge seen at the input and eliminates output voltage overshoot. The enable pin is active high. When pulled low, the enable input (EN) forces the LP6342 into a low-power, non-switching state. The total input current during shutdown is less than 1μA. Current Mode PWM Control Slope compensated current mode PWM control provides stable switching and cycle-by-cycle current limit for excellent load and line response with protection of the internal main switch (P-channel MOSFET) and synchronous rectifier (N-channel MOSFET). During normal operation, the internal P-channel MOSFET is turned on for a specified time to ramp the inductor current at each rising edge of the internal oscillator, and switched off when the peak inductor current is above the error volt-age. The current comparator, ICOMP, limits the peak inductor current. When the main switch is off, the synchronous rectifier turns on immediately and stays on until either the inductor current starts to reverse, as indicated by the current reversal comparator, IZERO, or the beginning of the next clock cycle. Control Loop The LP6342 is a peak current mode step-down converter. The current through the P-channel MOSFET (high side) is sensed for current loop control, as well as short circuit and overload protection. A slope compensation signal is added to the sensed current to maintain stability for duty cycles greater than 50%. The peak current mode loop appears as a voltage-programmed current source in parallel with the output capacitor. The output of the voltage error amplifier programs the current mode loop for the necessary peak switch current to force a constant output voltage for all load and line conditions. Internal loop compensation terminates the trans conductance voltage error amplifier output. The error amplifier reference is fixed at 0.6V. LP6342-03 Version 1.3 Datasheet Oct.-2011 Current Limit and Over-Temperature Protection For overload conditions, the peak input current is limited to 3.5A. To minimize power dissipation and stresses under current limit and short-circuit conditions, switching is terminated after entering current limit for a series of pulses. The termination lasts for seven consecutive clock cycles after a current limit has been sensed during a series of four consecutive clock cycles. Thermal protection completely disables switching when internal dissipation becomes excessive. The junction over-temperature threshold is 170°C with 10°C of hysteresis. Once an over-temperature or over-current fault conditions is removed, the output voltage automatically recovers. Dropout Operation When the battery input voltage decreases near the value of the output voltage, the LP6342 allows the main switch to remain on for more than one switching cycle and increases the duty cycle until it reaches 100%. The duty cycle D of a step-down converter is defined as: Where TON is the main switch on time and FOSC is the oscillator frequency. The output voltage then is the input voltage minus the voltage drop across the main switch and the inductor. At low input supply voltage, the RDS(ON) of the P-channel MOSFET increases, and the efficiency of the converter decreases. Caution must be exercised to ensure the heat dissipated does not exceed the maxi-mum junction temperature of the IC. Maximum Load Current The LP6342 will operate with an input supply voltage as low as 2.5V, however, the maximum load current decreases at lower input voltages due to a large IR drop on the main switch and synchronous rectifier. The slope compensation signal reduces the peak inductor current as a function of the duty cycle to prevent sub-harmonic oscillations at duty cycles greater than 50%. Conversely, the current limit increases as the duty cycle decreases. Setting the Output Voltage Figure 1 shows the basic application circuit for the LP6342. The LP6342 can be externally programmed. Resistors R1 and R2 in Figure 1 program the output to regulate at a voltage higher than 0.6V. To limit the bias current required www.lowpowersemi.com 9 / 15 Preliminary Datasheet for the external feedback resistor string while maintaining good noise immunity, the minimum suggested value for R2 is 59kΩ. Although a larger value will further reduce quiescent current, it will also increase the impedance of the feedback node, making it more sensitive to external noise and interference. Table 1 summarizes the resistor values for various output volt-ages with R2 set to either 59kΩ for good noise immunity or 316kΩ for reduced no load input current. The LP6342, combined with an external feed forward capacitor (C3 in Figure 1), delivers enhanced transient response for extreme pulsed load applications. The addition of the feed forward capacitor typically requires a larger output capacitor C2 for stability. The external resistor sets the output voltage according to the following equation: Vout=0.6V x(1+R1/R2) R1=(Vout/0.6V-1)xR2 Table1 shows the resistor selection for different output voltage settings. Vout(V) R2=59K, R2=316K, R1=(K) R1=(K) 0.8 19.6 105 0.9 29.4 158 1.0 39.2 210 1.1 49.9 261 1.2 59 316 1.3 68.1 365 1.4 78.7 422 1.5 88.7 475 1.8 118 634 1.85 124 655 2.0 137 732 2.5 187 1000 3.3 267 1430 Table1: Resistor Selections for Different Output Voltage Settings (Standard 1% Resistors Substituted For Calculated Values). LP6342 For output voltages above 2.0V, when light-load efficiency is important, the minimum recommended inductor is 2.2μH. Manufacturer’s specifications list both the inductor DC current rating, which is a thermal limitation, and the peak current rating, which is determined by the saturation characteristics. The inductor should not show any appreciable saturation under normal load conditions. Some inductors may meet the peak and average current ratings yet result in excessive losses due to a high DCR. Always consider the losses associated with the DCR and its effect on the total converter efficiency when selecting an inductor. For optimum voltage-positioning load transients, choose an inductor with DC series resistance in the 20mΩ to 100mΩ range. For higher efficiency at heavy loads (above 200mA), or minimal load regulation (but some transient overshoot), the resistance should be kept below 100mΩ. The DC current rating of the inductor should be at least equal to the maximum load current plus half the ripple current to prevent core saturation (2A + 600mA). Table 2 lists some typical surface mount inductors that meet target applications for the LP6342. Slope Compensation The LP6342 step-down converter uses peak current mode control with slope compensation for stability when duty cycles are greater than 50%. The slope compensation is set to maintain stability with lower value inductors which provide better overall efficiency. The output inductor value must be selected so the inductor current down slope meets the internal slope compensation requirements. As an example, the value of the slope compensation is set to 1A/μs which is large enough to guarantee stability when using a 2.2μH inductor for all output volt-age levels from 0.6V to 3.3V. The worst case external current slope (m) using the 2.2μH inductor is when VOUT = 3.3V and is: To keep the power supply stable when the duty cycle is above 50%, the internal slope compensation (mA) should be: Inductor Selection For most designs, the LP6342 operates with inductor values of 1μH to 4.7μH. Low inductance values are physically smaller but require faster switching, which results in some efficiency loss. The inductor value can be derived from the following equation: Therefore, to guarantee current loop stability, the slope of the compensation ramp must be greater than one-half of the down slope of the current waveform. So the internal slope compensated value of 1A/μs will guarantee stability using a 2.2μH inductor value for all output volt-ages from 0.6V to 3.3V. Where ΔIL is inductor ripple current. Large value inductors lower ripple current and small value inductors result in high ripple currents. Choose inductor ripple current approximately 30% of the maximum load current 2A, or LP6342-03 Version 1.3 Datasheet Oct.-2011 www.lowpowersemi.com 10 / 15 Preliminary Datasheet A low ESR input capacitor sized for maximum RMS cur-rent must be used. Ceramic capacitors with X5R or X7R dielectrics are highly recommended because of their low ESR and small temperature coefficients. A 22μF ceramic capacitor for most applications is sufficient. A large value may be used for improved input voltage filtering. The maximum input capacitor RMS current is: The input capacitor RMS ripple current varies with the input and output voltage and will always be less than or equal to half of the total DC load current. To minimize stray inductance, the capacitor should be placed as closely as possible to the IC. This keeps the high frequency content of the input current localized, minimizing EMI and input voltage ripple. The proper placement of the input capacitor (C1) can be seen in the evaluation board layout in Figures 2. A laboratory test set-up typically consists of two long wires running from the bench power supply to the evaluation board input voltage pins. The inductance of these wires, along with the low-ESR ceramic input capacitor, can create a high Q network that may affect converter performance. This problem often becomes apparent in the form of excessive ringing in the output voltage during load transients. Errors in the loop phase and gain measurements can also result. Since the inductance of a short PCB trace feeding the input voltage is significantly lower than the power leads from the bench power supply, most applications do not exhibit this problem. In applications where the input power source lead inductance cannot be reduced to a level that does not affect the converter performance, a high ESR tantalum or aluminum electrolytic should be placed in parallel with the low ESR, ESL bypass ceramic. This dampens the high Q network and stabilizes the system. Output Capacitor Selection The function of output capacitance is to store energy to attempt to maintain a constant voltage. The energy is stored in the capacitor’s electric field due to the voltage applied. The value of output capacitance is generally selected to limit output voltage ripple to the level required by the specification. Since the ripple current in the output inductor is usually determined by L, VOUT and VIN, the series impedance of the capacitor primarily determines the out-put voltage ripple. The three elements of the capacitor that contribute to its impedance (and output voltage ripple) are equivalent series resistance (ESR), equivalent series inductance (ESL), and capacitance (C). The output voltage droop due to a load transient is dominated by the capacitance of the ceramic output capacitor. During a step increase in load current, the ceramic output capacitor alone supplies the load current until the loop responds. Within three switching cycles, the loop responds and the inductor LP6342-03 Version 1.3 Datasheet Oct.-2011 LP6342 current increases to match the load current demand. The relationship of the output voltage droop during the three switching cycles to the output capacitance can be estimated by: In many practical designs, to get the required ESR, a capacitor with much more capacitance than is needed must be selected. For both continuous or discontinuous inductor current mode operation, the ESR of the COUT needed to limit the ripple to ∆VO, V peak-to-peak is: Ripple current flowing through a capacitor’s ESR causes power dissipation in the capacitor. This power dissipation causes a temperature increase internal to the capacitor. Excessive temperature can seriously shorten the expect-ed life of a capacitor. Capacitors have ripple current rat-ings that are dependent on ambient temperature and should not be exceeded. The output capacitor ripple cur-rent is the inductor current, IL, minus the output current, IO. The RMS value of the ripple current flowing in the output capacitance (continuous inductor current mode operation) is given by: ESL can be a problem by causing ringing in the low megahertz region but can be controlled by choosing low ESL capacitors, limiting lead length (PCB and capacitor), and replacing one large device with several smaller ones connected in parallel. In conclusion, in order to meet the requirement of out-put voltage ripple small and regulation loop stability, ceramic capacitors with X5R or X7R dielectrics are recommended due to their low ESR and high ripple current ratings. The output ripple VOUT is determined by: A 22μF ceramic capacitor can satisfy most applications. Thermal Calculations There are three types of losses associated with the LP6342 step-down converter: switching losses, conduction losses, and quiescent current losses. Conduction losses are associated with the RDS(ON) characteristics of the power output switching devices. Switching losses are dominated by the gate charge of the power output switching devices. At full load, assuming continuous conduction mode (CCM), a simplified form of the losses is given by: IQ is the step-down converter quiescent current. The term Tsw is used to estimate the full load step-down converter switching losses. www.lowpowersemi.com 11 / 15 Preliminary Datasheet For the condition where the step-down converter is in dropout at 100% duty cycle, the total device dissipation reduces to: Since RDS(ON), quiescent current, and switching losses all vary with input voltage, the total losses should be investigated over the complete input voltage range. Given the total losses, the maximum junction temperature can be derived from the θJA for the DFN-10 package which is 45°C/W. VIN 2.2uH C1 10uF 3 LP6342 Vin EN SW SW FB LP6342-03 Vout_2A 7 8 22pF R1 5 Vout=(R1/R2+1)*VFB 6 4 9 10 1 Vin GND PGOOD GND GND 2 Version 1.3 Datasheet R2 Oct.-2011 C2 22uF LP6342 Layout Guidance When laying out the PC board, the following layout guideline should be followed to ensure proper operation of the LP6342: 1. The exposed pad (EP) must be reliably soldered to the GND plane. A PGND pad below EP is strongly recommended. 2. The power traces, including the GND trace, the SW trace and the IN trace should be kept short, direct and wide to allow large current flow. The L1 connection to the SW pins should be as short as possible. Use several VIA pads when routing between layers. 3. The input capacitor (C1) should connect as closely as possible to IN (Pin 2) and AGND (Pins 6) to get good power filtering. 4. Keep the switching node, SW (Pins 7 and 8) away from the sensitive FB/OUT node. 5. The feedback trace or OUT pinshould be separate from any power trace and connect as closely as possible to the load point. Sensing along a high-current load trace will degrade DC load regulation. If external feedback resistors are used, they should be placed as closely as possible to the FB pin (Pin 5) to minimize the length of the high impedance feedback trace. 6. The output capacitor C2 and L1 should be connected as closely as possible. The connection of L1 to the SW pin should be as short as possible and there should not be any signal lines under the inductor. 7. The resistance of the trace from the load return to PGND should be kept to a minimum. This will help to minimize any error in DC regulation due to differences in the potential of the internal signal ground and the power ground. www.lowpowersemi.com 12 / 15 Preliminary Datasheet LP6342 Packaging Information LP6342-03 Version 1.3 Datasheet Oct.-2011 www.lowpowersemi.com 13 / 15 Preliminary Datasheet LP6342-03 Version 1.3 Datasheet Oct.-2011 www.lowpowersemi.com LP6342 14 / 15 Preliminary Datasheet LP6342 SOP8(EP) LP6342-03 Version 1.3 Datasheet Oct.-2011 www.lowpowersemi.com 15 / 15