RENESAS 116

R32C/116 Group Datasheet
Datasheet
R32C/116 Group
RENESAS MCU
1.
REJ03B0253-0110
Rev.1.10
Jun 23, 2010
Overview
1.1
Features
The M16C Family offers a robust platform of 32-/16-bit CISC microcomputers (MCUs) featuring high ROM
code efficiency, extensive EMI/EMS noise immunity, ultra-low power consumption, high-speed processing
in actual applications, and numerous and varied integrated peripherals. Extensive device scalability from
low- to high-end, featuring a single architecture as well as compatible pin assignments and peripheral
functions, provides support for a vast range of application fields.
The R32C/100 Series is a high-end microcontroller series in the M16C Family. With a 4-Gbyte memory
space, it achieves maximum code efficiency and high-speed processing with 32-bit CISC architecture,
multiplier, multiply-accumulate unit, and floating point unit. The selection from the broadest choice of onchip peripheral devices — UART, CRC, DMAC, A/D and D/A converters, timers, I2C, and WDT enables to
minimize external components.
The R32C/100 Series, in particular, provides the R32C/116 Group as a standard product. This product,
provided as a 100/144-pin plastic molded LQFP package, configures nine channels of serial interface and
one channel of multi-master I2C-bus interface.
1.1.1
Applications
Car audio, audio, cameras, television, home appliance, printer, office/industrial equipment,
communication/portable devices etc.
REJ03B0253-0110
Jun 23, 2010
Rev.1.10
Page 1 of 95
R32C/116 Group
1.1.2
1. Overview
Performance Overview
Table 1.1 to Table 1.4 show the performance overview of the R32C/116 Group.
Table 1.1
R32C/116 Group Performance for the 144 pin-Package (1/2)
Unit
CPU
Function
Central
processing unit
Memory
Performance
R32C/100 Series CPU Core
• Basic instructions: 108
• Minimum instruction execution time: 15.625 ns (f(CPU) = 64 MHz)
• Multiplier: 32-bit × 32-bit 64-bit
• Multiply-accumulate unit: 32-bit × 32-bit + 64-bit 64-bit
• IEEE-754 floating point standard: Single precision
• 32-bit barrel shifter
• Operating mode: Single-chip mode, memory expansion mode,
microprocessor mode (optional (1))
Flash memory: 384 Kbytes to 1 Mbyte
RAM: 40 K/48 K/63 Kbytes
Data flash: 4 Kbytes × 2 blocks
Refer to Table 1.5 for memory size of each product group
Voltage
Detector
Low voltage
detector
Optional (1)
Low voltage detection interrupt
Clock
Clock generator
• 4 circuits (main clock, sub clock, PLL, on-chip oscillator)
• Oscillation stop detector: Main clock oscillator stop/re-oscillation
detection
• Frequency divide circuit: Divide-by-2 to divide-by-24 selectable
• Low power modes: Wait mode, stop mode
External Bus
Expansion
Bus and memory
expansion
• Address space: 4 Gbytes (of which up to 64 Mbytes is user
accessible)
• External bus Interface: Support for wait-state insertion, 4 chip select
outputs
• Bus format: Separate bus/Multiplexed bus selectable, data bus width
selectable (8/16/32 bits)
Interrupts
Interrupt vectors: 261
External interrupt inputs: NMI, INT × 9, key input × 4
Interrupt priority levels: 7 levels
Watchdog Timer
15 bits × 1 (selectable input frequency from prescaler output)
DMA
DMAC
4 channels
• Cycle-steal transfer mode
• Request sources: 57
• 2 transfer modes: Single transfer, repeat transfer
DMAC II
• Can be activated by any peripheral interrupt source
• 3 transfer functions: Immediate data transfer, calculation transfer,
chained transfer
Programmable
I/O ports
• 2 input-only ports
• 120 CMOS inputs/outputs
• 32 ports are 5 V tolerant
• A pull-up resistor is selectable for every 4 input ports (except 5 V
tolerant inputs)
I/O Ports
Note:
1. Please contact a Renesas Electronics sales office to use the optional feature.
REJ03B0253-0110
Jun 23, 2010
Rev.1.10
Page 2 of 95
R32C/116 Group
Table 1.2
1. Overview
R32C/116 Group Performance for the 144-pin Package (2/2)
Unit
Timer
Serial
Interface
Function
Performance
Timer A
16-bit timer × 5
Timer mode, event counter mode, one-shot timer mode, pulse-width
modulation (PWM) mode
Two-phase pulse signal processing in event counter mode (twophase encoder input) × 3
Timer B
16-bit timer × 6
Timer mode, event counter mode, pulse frequency measurement
mode, pulse-width measurement mode
Three-phase
motor control
timer
Three-phase motor control timer × 1 (timers A1, A2, A4, and B2 used)
8-bit programmable dead time timer
UART0 to UART8 Asynchronous/synchronous serial interface × 9 channels
• I2C-bus (UART0 to UART6)
• Special mode 2 (UART0 to UART6)
• IEBus (optional (1)) (UART0 to UART6)
A/D Converter
10-bit resolution × 34 channels
Sample and hold functionality integrated
D/A Converter
8-bit resolution × 2
CRC Calculator
CRC-CCITT (X16 + X12 + X5 + 1)
X-Y Converter
16 bits × 16 bits
Intelligent I/O
Time measurement (input capture): 16 bits × 16
Waveform generation (output compare): 16 bits × 24
Serial interface: Variable-length synchronous serial I/O mode, IEBus
mode (optional (1))
Multi-master I2C-bus Interface
1 channel
Flash Memory
Programming and erasure supply voltage: VCC = 3.0 to 5.5 V
Minimum endurance: 1,000 program/erase cycles
Security protection: ROM code protect, ID code protect
Debugging: On-chip debug, on-board flash programming
Operating Frequency/Supply
Voltage
64 MHz (high speed version)/VCC = 3.0 to 5.5 V
50 MHz (normal speed version)/VCC = 3.0 to 5.5 V
Operating Temperature
-20°C to 85°C (version N)
-40°C to 85°C (version D)
-40°C to 85°C (version P)
Current Consumption
45 mA (VCC = 5.0 V, f(CPU) = 64 MHz)
35 mA (VCC = 5.0 V, f(CPU) = 50 MHz)
8 µA (VCC = 3.3 V, f(XCIN) = 32.768 kHz, in wait mode)
Package
144-pin plastic molded LQFP (PLQP0144KA-A)
Note:
1. Please contact a Renesas Electronics sales office to use the optional feature.
REJ03B0253-0110
Jun 23, 2010
Rev.1.10
Page 3 of 95
R32C/116 Group
Table 1.3
1. Overview
R32C/116 Group Performance for the 100-pin Package (1/2)
Unit
CPU
Function
Central
processing unit
Memory
Performance
R32C/100 Series CPU Core
• Basic instructions: 108
• Minimum instruction execution time: 15.625 ns (f(CPU) = 64 MHz)
• Multiplier: 32-bit × 32-bit 64-bit
• Multiply-accumulate unit: 32-bit × 32-bit + 64-bit 64-bit
• IEEE-754 floating point standard: Single precision
• 32-bit barrel shifter
• Operating mode: Single-chip mode, memory expansion mode,
microprocessor mode (optional (1))
Flash memory: 384 Kbytes to 1 Mbyte
RAM: 40 K/48 K/63 Kbytes
Data flash: 4 Kbytes × 2 blocks
Refer to Table 1.5 for memory size of each product group
Voltage
Detector
Low voltage
detector
Optional (1)
Low voltage detection interrupt
Clock
Clock generator
• 4 circuits (main clock, sub clock, PLL, on-chip oscillator)
• Oscillation stop detector: Main clock oscillator stop/re-oscillation
detection
• Frequency divide circuit: Divide-by-2 to divide-by-24 selectable
• Low power modes: Wait mode, stop mode
External Bus
Expansion
Bus and memory
expansion
• Address space: 4 Gbytes (of which up to 64 Mbytes is user
accessible)
• External bus Interface: Support for wait-state insertion, 4 chip select
outputs
• Bus format: Separate bus/Multiplexed bus selectable, data bus width
selectable (8/16 bits)
Interrupts
Interrupt vectors: 261
External interrupt inputs: NMI, INT × 6, key input × 4
Interrupt priority levels: 7 levels
Watchdog Timer
15 bits × 1 (selectable input frequency from prescaler output)
DMA
DMAC
4 channels
• Cycle-steal transfer mode
• Request sources: 51
• 2 transfer modes: Single transfer, repeat transfer
DMAC II
• Can be activated by any peripheral interrupt source
• 3 transfer functions: Immediate data transfer, calculation transfer,
chained transfer
Programmable
I/O ports
• 2 input-only ports
• 84 CMOS inputs/outputs
• 32 ports are 5 V tolerant
• A pull-up resistor is selectable for every 4 input ports (except 5 V
tolerant inputs)
I/O Ports
Note:
1. Please contact a Renesas Electronics sales office to use the optional feature.
REJ03B0253-0110
Jun 23, 2010
Rev.1.10
Page 4 of 95
R32C/116 Group
Table 1.4
1. Overview
R32C/116 Group Performance for the 100-pin Package (2/2)
Unit
Timer
Serial
Interface
Function
Performance
Timer A
16-bit timer × 5
Timer mode, event counter mode, one-shot timer mode, pulse-width
modulation (PWM) mode
Two-phase pulse signal processing in event counter mode (twophase encoder input) × 3
Timer B
16-bit timer × 6
Timer mode, event counter mode, pulse frequency measurement
mode, pulse-width measurement mode
Three-phase
motor control
timer
Three-phase motor control timer × 1 (timers A1, A2, A4, and B2 used)
8-bit programmable dead time timer
UART0 to UART8 Asynchronous/synchronous serial interface × 9 channels
• I2C-bus (UART0 to UART6)
• Special mode 2 (UART0 to UART6)
• IEBus (optional (1)) (UART0 to UART6)
A/D Converter
10-bit resolution × 26 channels
Sample and hold functionality integrated
D/A Converter
8-bit resolution × 2
CRC Calculator
CRC-CCITT (X16 + X12 + X5 + 1)
X-Y Converter
16 bits × 16 bits
Intelligent I/O
Time measurement (input capture): 16 bits × 16
Waveform generation (output compare): 16 bits × 19
Serial interface: Variable-length synchronous serial I/O mode, IEBus
mode (optional (1))
Multi-master I2C-bus Interface
1 channel
Flash Memory
Programming and erasure supply voltage: VCC = 3.0 to 5.5 V
Minimum endurance: 1,000 program/erase cycles
Security protection: ROM code protect, ID code protect
Debugging: On-chip debug, on-board flash programming
Operating Frequency/Supply
Voltage
64 MHz (high speed version)/VCC = 3.0 to 5.5 V
50 MHz (normal speed version)/VCC = 3.0 to 5.5 V
Operating Temperature
-20°C to 85°C (version N)
-40°C to 85°C (version D)
-40°C to 85°C (version P)
Current Consumption
45 mA (VCC = 5.0 V, f(CPU) = 64 MHz)
35 mA (VCC = 5.0 V, f(CPU) = 50 MHz)
8 µA (VCC = 3.3 V, f(XCIN) = 32.768 kHz, in wait mode)
Package
100-pin plastic molded LQFP (PLQP0100KB-A)
Note:
1. Please contact a Renesas Electronics sales office to use the optional feature.
REJ03B0253-0110
Jun 23, 2010
Rev.1.10
Page 5 of 95
R32C/116 Group
1.2
1. Overview
Product Information
Table 1.5 and Table 1.6 list the product information and Figure 1.1 shows the details of the part number.
Table 1.5
R32C/116 Group Product List for Normal Speed Version (1/2)
Package Code (1)
Part Number
R5F64165NFD
PLQP0144KA-A
-40°C to 85°C (version D)
-20°C to 85°C (version N)
PLQP0100KB-A
-40°C to 85°C (version D)
R5F64165PFB
40 Kbytes
(P)
R5F64166DFD
PLQP0144KA-A
R5F64166PFD
R5F64166NFB
-40°C to 85°C (version P)
384 Kbytes
+ 8 Kbytes
(P)
R5F64165DFB
-20°C to 85°C (version N)
PLQP0100KB-A
-40°C to 85°C (version D)
-40°C to 85°C (version P)
(P)
R5F64167DFD
-20°C to 85°C (version N)
PLQP0144KA-A
R5F64167PFD
R5F64167NFB
-40°C to 85°C (version D)
640 Kbytes
+ 8 Kbytes
(P)
R5F64167DFB
48 Kbytes
PLQP0100KB-A
-20°C to 85°C (version N)
(P)
-40°C to 85°C (version D)
PLQP0144KA-A
R5F64168PFD
-40°C to 85°C (version D)
63 Kbytes
(P)
PLQP0144KA-A
R5F64169DFD
R5F64169PFD
R5F64169DFB
-20°C to 85°C (version N)
PLQP0100KB-A
R5F64168PFB
R5F64169NFB
-40°C to 85°C (version P)
768 Kbytes
+ 8 Kbytes
(P)
R5F64168DFB
R5F64169NFD
-20°C to 85°C (version N)
-40°C to 85°C (version P)
R5F64168DFD
R5F64168NFB
-40°C to 85°C (version P)
-40°C to 85°C (version D)
R5F64167PFB
R5F64168NFD
-20°C to 85°C (version N)
-40°C to 85°C (version P)
R5F64166PFB
R5F64167NFD
-40°C to 85°C (version P)
-40°C to 85°C (version D)
512 Kbytes
+ 8 Kbytes
(P)
R5F64166DFB
Remarks
-20°C to 85°C (version N)
R5F64165PFD
R5F64166NFD
RAM Capacity
(P)
R5F64165DFD
R5F64165NFB
ROM Capacity (2)
As of June, 2010
-40°C to 85°C (version D)
1 Mbyte
+ 8 Kbytes
(P)
PLQP0100KB-A
R5F64169PFB
-40°C to 85°C (version P)
-20°C to 85°C (version N)
-40°C to 85°C (version P)
-20°C to 85°C (version N)
-40°C to 85°C (version D)
-40°C to 85°C (version P)
(D): Under development (P): On planning phase
Notes:
1. The old package codes are as follows:PLQP0100KB-A: 100P6Q-A, PLQP0144KA-A: 144P6Q-A
2. Data flash memory provides an additional 8 Kbytes of ROM capacity.
REJ03B0253-0110
Jun 23, 2010
Rev.1.10
Page 6 of 95
R32C/116 Group
Table 1.6
1. Overview
R32C/116 Group Product List for High Speed Version (2/2)
Package Code (1)
Part Number
R5F64165HNFD
(P)
R5F64165HDFD
(D)
R5F64165HPFD
(D)
R5F64165HNFB
(P)
R5F64165HDFB
(D)
R5F64165HPFB
(D)
R5F64166HNFD
(P)
R5F64166HDFD
(D)
R5F64166HPFD
(D)
R5F64166HNFB
(P)
R5F64166HDFB
(D)
R5F64166HPFB
(D)
R5F64167HNFD
(P)
R5F64167HDFD
(D)
R5F64167HPFD
(D)
R5F64167HNFB
(P)
ROM Capacity (2)
RAM Capacity
As of June, 2010
Remarks
-20°C to 85°C (version N)
PLQP0144KA-A
-40°C to 85°C (version D)
-40°C to 85°C (version P)
384 Kbytes
+ 8 Kbytes
-20°C to 85°C (version N)
PLQP0100KB-A
-40°C to 85°C (version D)
40 Kbytes
PLQP0144KA-A
-40°C to 85°C (version P)
-20°C to 85°C (version N)
-40°C to 85°C (version D)
-40°C to 85°C (version P)
512 Kbytes
+ 8 Kbytes
-20°C to 85°C (version N)
PLQP0100KB-A
-40°C to 85°C (version D)
-40°C to 85°C (version P)
-20°C to 85°C (version N)
PLQP0144KA-A
-40°C to 85°C (version D)
640 Kbytes
+ 8 Kbytes
48 Kbytes
-20°C to 85°C (version N)
R5F64167HDFB
(D)
R5F64167HPFB
(D)
-40°C to 85°C (version P)
R5F64168HNFD
(P)
-20°C to 85°C (version N)
R5F64168HDFD
(D)
R5F64168HPFD
(D)
R5F64168HNFB
(P)
R5F64168HDFB
(D)
R5F64168HPFB
(D)
R5F64169HNFD
(P)
R5F64169HDFD
(D)
R5F64169HPFD
(D)
R5F64169HNFB
(P)
R5F64169HDFB
(D)
R5F64169HPFB
(D)
PLQP0100KB-A
-40°C to 85°C (version P)
-40°C to 85°C (version D)
-40°C to 85°C (version D)
PLQP0144KA-A
-40°C to 85°C (version P)
768 Kbytes
+ 8 Kbytes
-20°C to 85°C (version N)
PLQP0100KB-A
-40°C to 85°C (version D)
63 Kbytes
PLQP0144KA-A
-20°C to 85°C (version N)
-40°C to 85°C (version D)
1 Mbyte
+ 8 Kbytes
PLQP0100KB-A
-40°C to 85°C (version P)
-40°C to 85°C (version P)
-20°C to 85°C (version N)
-40°C to 85°C (version D)
-40°C to 85°C (version P)
(D): Under development (P): On planning phase
Notes:
1. The old package codes are as follows:PLQP0100KB-A: 100P6Q-A, PLQP0144KA-A: 144P6Q-A
2. Data flash memory provides an additional 8 Kbytes of ROM capacity.
REJ03B0253-0110
Jun 23, 2010
Rev.1.10
Page 7 of 95
R32C/116 Group
1. Overview
Part Number
R5 F 64 16 9 H P XXX FD
Package Code
FB : PLQP0100KB-A
FD : PLQP0144KA-A
ROM Number
Omitted in the flash memory version
Temperature Code
N : -20°C to 85°C
D : -40°C to 85°C
P : -40°C to 85°C
Rated Operating Frequency
H : 64MHz (High speed version)
None : 50MHz (Normal speed version)
ROM/RAM Capacity
5 : 384 KB/40 KB
6 : 512 KB/40 KB
7 : 640 KB/48 KB
8 : 768 KB/63 KB
9 : 1 MB/63 KB
R32C/116 Group
R32C/100 Series
Memory Type
F : Flash memory version
Figure 1.1
Part Numbering
REJ03B0253-0110
Jun 23, 2010
Rev.1.10
Page 8 of 95
R32C/116 Group
1.3
1. Overview
Block Diagram
Figure 1.2 shows a block diagram of the R32C/116 Group.
8
8
8
8
8
8
8
Port P0
Port P1
Port P2
Port P3
Port P4
Port P5
Port P6
D/A converter:
8 bits × 2 channels
Serial interface:
9 channels
Watchdog timer:
15 bits
X-Y converter:
16 bits × 16 bits
DMAC
CRC calculator (CCITT)
DMAC II
X16 + X12 + X5 + 1
1 channel
Memory
R32C/100 Series CPU Core
8
4
Port P14_1
Multiplier
8
Port P14
RAM
8 (3)
Port P15
ROM
FLG
INTB
ISP
USP
PC
SVF
SVP
VCT
Port P10
R2R0
R2R0
R3R1
R3R1
R6R4
R6R4
R7R5
R7R5
A0
A0
A1
A1
A2
A2
A3
A3
FB
FB
SB
SB
Port P9
Intelligent I/O
Time Measurement: 16
Wave generation: 24 (2)
Serial interface:
- Variable-length
synchronous serial I/O
- IEBus
P8_5
Multi-master I2C-bus
interface:
7
Three-phase motor
controller
8
16 bits × 5 timers
16 bits × 6 timers
4 circuits
- XIN-XOUT
- XCIN-XCOUT
- On-chip oscillator
- PLL frequency synthesizer
Port P8
Timer:
Timer A
Timer B
Clock generator:
A/D converter:
10 bits × 1 circuit
Standard: 10 inputs
Maximum: 34 inputs (1)
Port P7
Peripheral functions
Floating-point unit
Port P13
Port P12
Port P11
8
8
5
(Note 4)
Notes:
1. 34 inputs are available in the 144-pin package. In the 100-pin package, up to 26 inputs are provided.
2. 24 outputs are available in the 144-pin package. In the 100-pin package, 19 outputs are provided.
3. Eight ports are available in the 144-pin package. In the 100-pin package, five I/O ports and one inputonly port (P9_1) are provided.
4. Ports P11 to P15 are available in the 144-pin package only.
Figure 1.2
R32C/116 Group Block Diagram
REJ03B0253-0110
Jun 23, 2010
Rev.1.10
Page 9 of 95
R32C/116 Group
1.4
1. Overview
Pin Assignments
P1_1 / D9 / IIO0_1 / IIO1_1
P1_2 / D10 / IIO0_2 / IIO1_2
P1_3 / D11 / IIO0_3 / IIO1_3
P1_4 / D12 / IIO0_4 / IIO1_4
P1_5 / D13 / INT3 / IIO0_5 / IIO1_5
P1_6 / D14 / INT4 / IIO0_6 / IIO1_6
P1_7 / D15 / INT5 / IIO0_7 / IIO1_7
P2_0 / A0 / [A0/D0] / BC0 / [BC0/D0] / AN2_0
P2_1 / A1 / [A1/D1] / BC2 / [BC2/D1] / AN2_1
P2_2 / A2 / [A2/D2] / AN2_2
P2_3 / A3 / [A3/D3] / AN2_3
P2_4 / A4 / [A4/D4] / AN2_4
P2_5 / A5 / [A5/D5] / AN2_5
P2_6 / A6 / [A6/D6] / AN2_6
P2_7 / A7 / [A7/D7] / AN2_7
VSS
P3_0 / A8 / [A8/D8] / TA0OUT / UD0A / UD1A
VCC
P12_0 / D16 / TXD6 / SDA6 / SRXD6
P12_1 / D17 / CLK6
P12_2 / D18 / RXD6 / SCL6 / STXD6
P12_3 / D19 / CTS6 / RTS6 / SS6
P12_4 / D20
P3_1 / A9 / [A9/D9] / TA3OUT / UD0B / UD1B
P3_2 / A10 / [A10/D10] / TA1OUT / V
P3_3 / A11 / [A11/D11] / TA1IN / V
P3_4 / A12 / [A12/D12] / TA2OUT / W
P3_5 / A13 / [A13/D13] / TA2IN / W
P3_6 / A14 / [A14/D14] / TA4OUT / U
P3_7 / A15 / [A15/D15] / TA4IN / U
P4_0 / A16 / CTS3 / RTS3 / SS3
P4_1 / A17 / CLK3
VSS
P4_2 / A18 / RXD3 / SCL3 / STXD3 / ISRXD2 / IEIN
VCC
P4_3 / A19 / TXD3 / SDA3 / SRXD3 / OUTC2_0 / ISTXD2 / IEOUT
Figure 1.3 and Figure 1.4 show the pin assignments (top view) and Table 1.7 to Table 1.13 show the pin
characteristics.
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
109
72
110
71
111
70
112
69
113
68
114
67
115
66
116
65
117
64
118
63
119
62
120
61
121
60
R32C/116 GROUP
122
123
124
59
58
57
125
56
PLQP0144KA-A
(144P6Q-A)
(Top view)
126
127
128
129
130
131
55
54
53
52
51
50
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
P4_4 / CS3 / A20 / CTS6 / RTS6 / SS6
P4_5 / CS2 / A21 / CLK6
P4_6 / CS1 / A22 / RXD6 / SCL6 / STXD6
P4_7 / CS0 / A23 / TXD6 / SDA6 / SRXD6
P12_5 / D21
P12_6 / D22
P12_7 / D23
P5_0 / WR0 / WR
P5_1 / WR1 / BC1
P5_2 / RD
P5_3 / CLKOUT / BCLK
P13_0 / D24 / OUTC2_4
P13_1 / D25 / OUTC2_5
VCC
(Note 2)
P13_2 / D26 / OUTC2_6
VSS
P13_3 / D27 / OUTC2_3
P5_4 / HLDA / CS1 / TXD7
P5_5 / HOLD / CLK7
P5_6 / ALE / CS2 / RXD7
P5_7 / RDY / CS3 / CTS7 / RTS7
P13_4 / D28 / OUTC2_0 / ISTXD2 / IEOUT
P13_5 / D29 / OUTC2_2 / ISRXD2 / IEIN
P13_6 / D30 / OUTC2_1 / ISCLK2
P13_7 / D31 / OUTC2_7
P6_0 / TB0IN / CTS0 / RTS0 / SS0
P6_1 / TB1IN / CLK0
P6_2 / TB2IN / RXD0 / SCL0 / STXD0
P6_3 / TXD0 / SDA0 / SRXD0
P6_4 / CTS1 / RTS1 / SS1 / OUTC2_1 / ISCLK2
P6_5 / CLK1
VSS
P6_6 / RXD1 / SCL1 / STXD1
VCC
P6_7 / TXD1 / SDA1 / SRXD1
P7_0 / TA0OUT / TXD2 / SDA2 / SRXD2 / IIO1_6 / OUTC2_0 / ISTXD2 / IEOUT / MSDA
SRXD4 / SDA4 / TXD4 / ANEX1 / P9_6
CLK4 / ANEX0 / P9_5
SS4 / RTS4 / CTS4 / TB4IN / DA1 / P9_4
SS3 / RTS3 / CTS3 / TB3IN / DA0 / P9_3
IEOUT / ISTXD2 / OUTC2_0 / SRXD3 / SDA3 / TXD3 / TB2IN / P9_2
IEIN / ISRXD2 / STXD3 / SCL3 / RXD3 / TB1IN / P9_1
CLK3 / TB0IN / P9_0
INT8 / P14_6
INT7 / P14_5
INT6 / P14_4
P14_3
VDC0
P14_1
VDC1
NSD
CNVSS
XCIN / P8_7
XCOUT / P8_6
RESET
XOUT
VSS
XIN
VCC
NMI / P8_5
INT2 / P8_4
INT1 / P8_3
INT0 / P8_2
UD0B / UD1B / IIO1_5 / RTS5 / CTS5 / SS5 / U / TA4IN / P8_1
UD0A / UD1A / RXD5 / SCL5 / STXD5 / U / TA4OUT / P8_0
UD0B / UD1B / IIO1_4 / CLK5 / TA3IN / P7_7
UD0A / UD1A / IIO1_3 / RTS8 / CTS8 / TXD5 / SDA5 / SRXD5 / TA3OUT / P7_6
IIO1_2 / RXD8 / W / TA2IN / P7_5
IIO1_1 / CLK8 / W / TA2OUT / P7_4
IIO1_0 / TXD8 / SS2 / RTS2 / CTS2 / V / TA1IN / P7_3
CLK2 / V / TA1OUT / P7_2
MSCL / IEIN / ISRXD2 / OUTC2_2 / IIO1_7 / STXD2 / SCL2 / RXD2 / TA0IN / TB5IN / P7_1
15
37
(Note 3)
14
38
144
13
39
143
12
40
142
11
41
141
10
42
140
9
43
139
8
44
138
7
45
137
6
46
136
5
47
135
4
48
134
3
49
133
2
132
1
IIO0_0 / IIO1_0 / D8 / P1_0
AN0_7 / D7 / P0_7
AN0_6 / D6 / P0_6
AN0_5 / D5 / P0_5
AN0_4 / D4 / P0_4
WR3 / BC3 / P11_4
IIO1_3 / RTS8 / CTS8 / WR2 / CS3 / P11_3
IIO1_2 / RXD8 / CS2 / P11_2
IIO1_1 / CLK8 / CS1 / P11_1
IIO1_0 / TXD8 / CS0 / P11_0
AN0_3 / D3 / P0_3
AN0_2 / D2 / P0_2
AN0_1 / D1 / P0_1
AN0_0 / D0 / P0_0
IIO0_7 / RTS6 / CTS6 / SS6 / AN15_7 / P15_7
IIO0_6 / CLK6 / AN15_6 / P15_6
IIO0_5 / RXD6 / SCL6 / STXD6 / AN15_5 / P15_5
IIO0_4 / TXD6 / SDA6 / SRXD6 / AN15_4 / P15_4
IIO0_3 / RTS7 / CTS7 / AN15_3 / P15_3
IIO0_2 / RXD7 / AN15_2 / P15_2
IIO0_1 / CLK7 / AN15_1 / P15_1
VSS
IIO0_0 / TXD7 / AN15_0 / P15_0
VCC
KI3 / AN_7 / P10_7
KI2 / AN_6 / P10_6
KI1 / AN_5 / P10_5
KI0 / AN_4 / P10_4
AN_3 / P10_3
AN_2 / P10_2
AN_1 / P10_1
AVSS
AN_0 / P10_0
VREF
AVCC
STXD4 / SCL4 / RXD4 / ADTRG / P9_7
107
108
(Note 1)
Notes:
1. Pin names in brackets [ ] represent a functional signal as a whole and should not be considered as two separate pins.
2. The following pins are 5 V tolerant inputs: P4_0 to P4_7, P5_4 to P5_7, P6_0 to P6_7, P7_0 to P7_7, and P8_0 to P8_3.
3. The position of pin number 1 varies by product. Refer to the index mark in attached “Package Dimensions”.
Figure 1.3
Pin Assignment for the 144-pin Package (top view)
REJ03B0253-0110
Jun 23, 2010
Rev.1.10
Page 10 of 95
R32C/116 Group
Table 1.7
Pin
No.
1. Overview
Pin Characteristics for the 144-pin Package (1/4)
Control
Pin
Port
Interrupt
Pin
Timer Pin
UART Pin
Intelligent I/O Pin
Analog
Pin
1
P9_6
TXD4/SDA4/SRXD4
ANEX1
2
P9_5
CLK4
ANEX0
3
P9_4
CTS4/RTS4/SS4
DA1
TB4IN
4
P9_3
TB3IN
CTS3/RTS3/SS3
5
P9_2
TB2IN
TXD3/SDA3/SRXD3
OUTC2_0/ISTXD2/
IEOUT
6
P9_1
TB1IN
RXD3/SCL3/STXD3
ISRXD2/IEIN
7
P9_0
TB0IN
CLK3
8
P14_6 INT8
9
P14_5 INT7
10
P14_4 INT6
11
P14_3
CTS5/RTS5/SS5
12
Bus Control
Pin
DA0
VDC0
13
P14_1
14
VDC1
15
NSD
16
CNVSS
17
XCIN
18
XCOUT P8_6
19
RESET
20
XOUT
21
VSS
22
XIN
23
VCC
P8_7
24
P8_5
NMI
25
P8_4
INT2
26
P8_3
INT1
27
P8_2
INT0
28
P8_1
TA4IN/U
29
P8_0
TA4OUT/U RXD5/SCL5/STXD5
UD0A/UD1A
30
P7_7
TA3IN
CLK5
IIO1_4/UD0B/UD1B
31
P7_6
TA3OUT
TXD5/SDA5/SRXD5/
CTS8/RTS8
IIO1_3/UD0A/UD1A
32
P7_5
TA2IN/W
RXD8
IIO1_2
33
P7_4
TA2OUT/W CLK8
IIO1_1
34
P7_3
TA1IN/V
35
P7_2
TA1OUT/V CLK2
36
P7_1
TB5IN/
TA0IN
REJ03B0253-0110
Jun 23, 2010
Rev.1.10
IIO1_5/UD0B/UD1B
CTS2/RTS2/SS2/TXD8 IIO1_0
RXD2/SCL2/STXD2/
MSCL
IIO1_7/OUTC2_2/
ISRXD2/IEIN
Page 11 of 95
R32C/116 Group
Table 1.8
Pin
No.
1. Overview
Pin Characteristics for the 144-pin Package (2/4)
Control
Pin
Port
Interrupt
Pin
Timer Pin
37
P7_0
38
P6_7
TXD1/SDA1/SRXD1
P6_6
RXD1/SCL1/STXD1
42
P6_5
CLK1
43
P6_4
CTS1/RTS1/SS1
39
TXD2/SDA2/SRXD2/
MSDA
Intelligent I/O Pin
Analog
Pin
Bus Control
Pin
IIO1_6/OUTC2_0/
ISTXD2/IEOUT
VCC
40
41
TA0OUT
UART Pin
VSS
44
P6_3
45
P6_2
TB2IN
RXD0/SCL0/STXD0
46
P6_1
TB1IN
CLK0
47
P6_0
TB0IN
CTS0/RTS0/SS0
OUTC2_1/ISCLK2
TXD0/SDA0/SRXD0
48
P13_7
OUTC2_7
D31
49
P13_6
OUTC2_1/ISCLK2
D30
50
P13_5
OUTC2_2/ISRXD2/
IEIN
D29
51
P13_4
OUTC2_0/ISTXD2/
IEOUT
D28
52
P5_7
CTS7/RTS7
RDY/CS3
53
P5_6
RXD7
ALE/CS2
54
P5_5
CLK7
HOLD
55
P5_4
TXD7
HLDA/CS1
56
P13_3
OUTC2_3
D27
P13_2
OUTC2_6
D26
60
P13_1
OUTC2_5
D25
61
P13_0
OUTC2_4
D24
62
P5_3
CLKOUT/
BCLK
63
P5_2
RD
64
P5_1
WR1/BC1
57
VSS
58
59
VCC
65
P5_0
WR0/WR
66
P12_7
D23
67
P12_6
D22
68
P12_5
D21
69
P4_7
TXD6/SDA6/SRXD6
CS0/A23
70
P4_6
RXD6/SCL6/STXD6
CS1/A22
71
P4_5
CLK6
CS2/A21
72
P4_4
CTS6/RTS6/SS6
CS3/A20
73
P4_3
TXD3/SDA3/SRXD3
74
OUTC2_0/ISTXD2/
IEOUT
A19
VCC
REJ03B0253-0110
Jun 23, 2010
Rev.1.10
Page 12 of 95
R32C/116 Group
Table 1.9
Pin
No.
Pin Characteristics for the 144-pin Package (3/4)
Control
Pin
75
76
1. Overview
Port
Interrupt
Pin
Timer Pin
UART Pin
Intelligent I/O Pin
Analog
Pin
ISRXD2/IEIN
Bus Control
Pin
P4_2
RXD3/SCL3/STXD3
A18
P4_1
CLK3
A17
CTS3/RTS3/SS3
A16
VSS
77
78
P4_0
79
P3_7
TA4IN/U
A15(/D15)
80
P3_6
TA4OUT/U
A14(/D14)
81
P3_5
TA2IN/W
A13(/D13)
82
P3_4
TA2OUT/W
A12(/D12)
83
P3_3
TA1IN/V
A11(/D11)
84
P3_2
TA1OUT/V
A10(/D10)
85
P3_1
TA3OUT
86
P12_4
87
P12_3
CTS6/RTS6/SS6
D19
88
P12_2
RXD6/SCL6/STXD6
D18
89
P12_1
CLK6
D17
P12_0
TXD6/SDA6/SRXD6
D16
90
91
A9(/D9)
D20
VCC
92
93
UD0B/UD1B
P3_0
TA0OUT
UD0A/UD1A
A8(/D8)
VSS
94
P2_7
AN2_7
A7(/D7)
95
P2_6
AN2_6
A6(/D6)
96
P2_5
AN2_5
A5(/D5)
97
P2_4
AN2_4
A4(/D4)
98
P2_3
AN2_3
A3(/D3)
99
P2_2
AN2_2
A2(/D2)
100
P2_1
AN2_1
A1(/D1)/
BC2(/D1)
101
P2_0
AN2_0
A0(/D0)/
BC0(/D0)
102
P1_7
INT5
IIO0_7/IIO1_7
D15
103
P1_6
INT4
IIO0_6/IIO1_6
D14
INT3
104
P1_5
IIO0_5/IIO1_5
D13
105
P1_4
IIO0_4/IIO1_4
D12
106
P1_3
IIO0_3/IIO1_3
D11
107
P1_2
IIO0_2/IIO1_2
D10
108
P1_1
IIO0_1/IIO1_1
D9
109
P1_0
IIO0_0/IIO1_0
D8
110
P0_7
AN0_7
D7
111
P0_6
AN0_6
D6
112
P0_5
AN0_5
D5
113
P0_4
AN0_4
D4
114
P11_4
REJ03B0253-0110
Jun 23, 2010
Rev.1.10
BC3/WR3
Page 13 of 95
R32C/116 Group
Table 1.10
Pin
No.
1. Overview
Pin Characteristics for the 144-pin Package (4/4)
Control
Pin
Port
Interrupt
Pin
Timer Pin
UART Pin
Intelligent I/O Pin
Analog
Pin
Bus Control
Pin
115
P11_3
CTS8/RTS8
IIO1_3
CS3/WR2
116
P11_2
RXD8
IIO1_2
CS2
117
P11_1
CLK8
IIO1_1
CS1
118
P11_0
TXD8
IIO1_0
119
P0_3
AN0_3
D3
120
P0_2
AN0_2
D2
121
P0_1
AN0_1
D1
122
P0_0
AN0_0
D0
123
P15_7
CTS6/RTS6/SS6
IIO0_7
AN15_7
124
P15_6
CLK6
IIO0_6
AN15_6
125
P15_5
RXD6/SCL6/STXD6
IIO0_5
AN15_5
126
P15_4
TXD6/SDA6/SRXD6
IIO0_4
AN15_4
127
P15_3
CTS7/RTS7
IIO0_3
AN15_3
128
P15_2
RXD7
IIO0_2
AN15_2
129
P15_1
CLK7
IIO0_1
AN15_1
P15_0
TXD7
IIO0_0
AN15_0
130
VSS
131
132
CS0
VCC
P10_7 KI3
133
AN_7
134
P10_6 KI2
AN_6
135
P10_5 KI1
AN_5
136
P10_4 KI0
AN_4
137
P10_3
AN_3
138
P10_2
AN_2
139
P10_1
AN_1
P10_0
AN_0
140
AVSS
141
142
VREF
143
AVCC
144
P9_7
REJ03B0253-0110
Jun 23, 2010
Rev.1.10
RXD4/SCL4/STXD4
ADTRG
Page 14 of 95
R32C/116 Group
1. Overview
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
76
50
77
49
78
48
79
47
80
46
81
45
82
44
83
43
84
42
R32C/116 GROUP
85
86
41
40
87
39
88
38
PLQP0100KB-A
(100P6Q-A)
(Top view)
89
90
91
92
93
37
36
35
34
33
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
P4_2 / A18 / RXD3 / SCL3 / STXD3 / ISRXD2 / IEIN
P4_3 / A19 / TXD3 / SDA3 / SRXD3 / OUTC2_0 / ISTXD2 / IEOUT
P4_4 / CS3 / A20 / CTS6 / RTS6 / SS6
P4_5 / CS2 / A21 / CLK6
P4_6 / CS1 / A22 / RXD6 / SCL6 / STXD6
P4_7 / CS0 / A23 / TXD6 / SDA6 / SRXD6
P5_0 / WR0 / WR
P5_1 / WR1 / BC1
P5_2 / RD
P5_3 / CLKOUT / BCLK
(Note 2)
P5_4 / HLDA / CS1 / TXD7
P5_5 / HOLD / CLK7
P5_6 / ALE / CS2 / RXD7
P5_7 / RDY / CS3 / CTS7 / RTS7
P6_0 / TB0IN / CTS0 / RTS0 / SS0
P6_1 / TB1IN / CLK0
P6_2 / TB2IN / RXD0 / SCL0 / STXD0
P6_3 / TXD0 / SDA0 / SRXD0
P6_4 / CTS1 / RTS1 / SS1 / OUTC2_1 / ISCLK2
P6_5 / CLK1
P6_6 / RXD1 / SCL1 / STXD1
P6_7 / TXD1 / SDA1 / SRXD1
P7_0 / TA0OUT / TXD2 / SDA2 / SRXD2 / IIO1_6 / OUTC2_0 / ISTXD2 / IEOUT / MSDA
P7_1 / TB5IN / TA0IN / RXD2 / SCL2 / STXD2 / IIO1_7 / OUTC2_2 / ISRXD2 / IEIN / MSCL
P7_2 / TA1OUT / V / CLK2
SS4 / RTS4 / CTS4 / TB4IN / DA1 / P9_4
TB3IN / DA0 / P9_3
VDC0
P9_1
VDC1
NSD
CNVSS
XCIN / P8_7
XCOUT / P8_6
RESET
XOUT
VSS
XIN
VCC
NMI / P8_5
INT2 / P8_4
INT1 / P8_3
INT0 / P8_2
UD0B / UD1B / IIO1_5 / RTS5 / CTS5 / SS5 / U / TA4IN / P8_1
UD0A / UD1A / RXD5 / SCL5 / STXD5 / U / TA4OUT / P8_0
UD0B / UD1B / IIO1_4 / CLK5 / TA3IN / P7_7
UD0A / UD1A / IIO1_3 / RTS8 / CTS8 / TXD5 / SDA5 / SRXD5 / TA3OUT / P7_6
IIO1_2 / RXD8 / W / TA2IN / P7_5
IIO1_1 / CLK8 / W / TA2OUT / P7_4
IIO1_0 / TXD8 / SS2 / RTS2 / CTS2 / V / TA1IN / P7_3
9
26
(Note 3)
8
27
100
7
28
99
6
29
98
5
30
97
4
31
96
3
32
95
2
94
1
IIO0_2 / IIO1_2 / D10 / P1_2
IIO0_1 / IIO1_1 / D9 / P1_1
IIO0_0 / IIO1_0 / D8 / P1_0
AN0_7 / D7 / P0_7
AN0_6 / D6 / P0_6
AN0_5 / D5 / P0_5
AN0_4 / D4 / P0_4
AN0_3 / D3 / P0_3
AN0_2 / D2 / P0_2
AN0_1 / D1 / P0_1
AN0_0 / D0 / P0_0
KI3 / AN_7 / P10_7
KI2 / AN_6 / P10_6
KI1 / AN_5 / P10_5
KI0 / AN_4 / P10_4
AN_3 / P10_3
AN_2 / P10_2
AN_1 / P10_1
AVSS
AN_0 / P10_0
VREF
AVCC
STXD4 / SCL4 / RXD4 / ADTRG / P9_7
SRXD4 / SDA4 / TXD4 / ANEX1 / P9_6
CLK4 / ANEX0 / P9_5
74
75
P1_3 / D11 / IIO0_3 / IIO1_3
P1_4 / D12 / IIO0_4 / IIO1_4
P1_5 / D13 / INT3 / IIO0_5 / IIO1_5
P1_6 / D14 / INT4 / IIO0_6 / IIO1_6
P1_7 / D15 / INT5 / IIO0_7 / IIO1_7
P2_0 / A0 / [A0/D0] / BC0 / [BC0/D0] / AN2_0
P2_1 / A1 / [A1/D1] / AN2_1
P2_2 / A2 / [A2/D2] / AN2_2
P2_3 / A3 / [A3/D3] / AN2_3
P2_4 / A4 / [A4/D4] / AN2_4
P2_5 / A5 / [A5/D5] / AN2_5
P2_6 / A6 / [A6/D6] / AN2_6
P2_7 / A7 / [A7/D7] / AN2_7
VSS
P3_0 / A8 / [A8/D8] / TA0OUT / UD0A / UD1A
VCC
P3_1 / A9 / [A9/D9] / TA3OUT / UD0B / UD1B
P3_2 / A10 / [A10/D10] / TA1OUT / V
P3_3 / A11 / [A11/D11] / TA1IN / V
P3_4 / A12 / [A12/D12] / TA2OUT / W
P3_5 / A13 / [A13/D13] / TA2IN / W
P3_6 / A14 / [A14/D14] / TA4OUT / U
P3_7 / A15 / [A15/D15] / TA4IN / U
P4_0 / A16 / CTS3 / RTS3 / SS3
P4_1 / A17 / CLK3
(Note 1)
Notes:
1. Pin names in brackets [ ] represent a functional signal as a whole and should not be considered as two separate pins.
2. The following pins are 5 V tolerant inputs: P4_0 to P4_7, P5_4 to P5_7, P6_0 to P6_7, P7_0 to P7_7, and P8_0 to P8_3.
3. The position of pin number 1 varies by product. Refer to the index mark in attached “Package Dimensions”.
Figure 1.4
Pin Assignment for the 100-pin Package (top view)
REJ03B0253-0110
Jun 23, 2010
Rev.1.10
Page 15 of 95
R32C/116 Group
Table 1.11
Pin
No.
1. Overview
Pin Characteristics for the 100-pin Package (1/3)
Control
Pin
Port
Interrupt
Pin
Timer Pin
1
P9_4
TB4IN
2
P9_3
TB3IN
3
UART Pin
Intelligent I/O Pin
CTS4/RTS4/SS4
Analog
Pin
Bus Control
Pin
DA1
DA0
VDC0
4
P9_1
5
VDC1
6
NSD
7
CNVSS
8
XCIN
9
XCOUT P8_6
10
RESET
11
XOUT
12
VSS
13
XIN
14
VCC
P8_7
15
P8_5
NMI
16
P8_4
INT2
17
P8_3
INT1
18
P8_2
INT0
19
P8_1
TA4IN/U
CTS5/RTS5/SS5
IIO1_5/UD0B/UD1B
20
P8_0
TA4OUT/U RXD5/SCL5/STXD5
UD0A/UD1A
21
P7_7
TA3IN
CLK5
IIO1_4/UD0B/UD1B
22
P7_6
TA3OUT
TXD5/SDA5/SRXD5/
CTS8/RTS8
IIO1_3/UD0A/UD1A
23
P7_5
TA2IN/W
RXD8
IIO1_2
24
P7_4
TA2OUT/W CLK8
IIO1_1
25
P7_3
TA1IN/V
26
P7_2
TA1OUT/V CLK2
27
P7_1
TB5IN/
TA0IN
RXD2/SCL2/STXD2/
MSCL
IIO1_7/OUTC2_2/
ISRXD2/IEIN
28
P7_0
TA0OUT
TXD2/SDA2/SRXD2/
MSDA
IIO1_6/OUTC2_0/
ISTXD2/IEOUT
29
P6_7
TXD1/SDA1/SRXD1
30
P6_6
RXD1/SCL1/STXD1
31
P6_5
CLK1
32
P6_4
CTS1/RTS1/SS1
CTS2/RTS2/SS2/TXD8 IIO1_0
33
P6_3
34
P6_2
TB2IN
RXD0/SCL0/STXD0
35
P6_1
TB1IN
CLK0
36
P6_0
TB0IN
CTS0/RTS0/SS0
OUTC2_1/ISCLK2
TXD0/SDA0/SRXD0
37
P5_7
CTS7/RTS7
RDY/CS3
38
P5_6
RXD7
ALE/CS2
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Table 1.12
Pin
No.
1. Overview
Pin Characteristics for the 100-pin Package (2/3)
Control
Pin
Port
Interrupt
Pin
Timer Pin
UART Pin
Intelligent I/O Pin
Analog
Pin
Bus Control
Pin
39
P5_5
CLK7
HOLD
40
P5_4
TXD7
HLDA/CS1
41
P5_3
CLKOUT/
BCLK
42
P5_2
RD
43
P5_1
WR1/BC1
44
P5_0
WR0/WR
45
P4_7
TXD6/SDA6/SRXD6
CS0/A23
46
P4_6
RXD6/SCL6/STXD6
CS1/A22
47
P4_5
CLK6
CS2/A21
48
P4_4
CTS6/RTS6/SS6
CS3/A20
49
P4_3
TXD3/SDA3/SRXD3
OUTC2_0/ISTXD2/
IEOUT
A19
50
P4_2
RXD3/SCL3/STXD3
ISRXD2/IEIN
A18
51
P4_1
CLK3
A17
CTS3/RTS3/SS3
A16
52
P4_0
53
P3_7
TA4IN/U
A15(/D15)
54
P3_6
TA4OUT/U
A14(/D14)
55
P3_5
TA2IN/W
A13(/D13)
56
P3_4
TA2OUT/W
A12(/D12)
57
P3_3
TA1IN/V
A11(/D11)
58
P3_2
TA1OUT/V
A10(/D10)
59
P3_1
TA3OUT
UD0B/UD1B
A9(/D9)
P3_0
TA0OUT
UD0A/UD1A
A8(/D8)
60
VCC
61
62
VSS
63
P2_7
AN2_7
A7(/D7)
64
P2_6
AN2_6
A6(/D6)
65
P2_5
AN2_5
A5(/D5)
66
P2_4
AN2_4
A4(/D4)
67
P2_3
AN2_3
A3(/D3)
68
P2_2
AN2_2
A2(/D2)
69
P2_1
AN2_1
A1(/D1)
70
P2_0
AN2_0
A0(/D0)/
BC0(/D0)
71
P1_7
INT5
IIO0_7/IIO1_7
D15
72
P1_6
INT4
IIO0_6/IIO1_6
D14
73
P1_5
INT3
IIO0_5/IIO1_5
D13
74
P1_4
IIO0_4/IIO1_4
D12
75
P1_3
IIO0_3/IIO1_3
D11
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Table 1.13
Pin
No.
1. Overview
Pin Characteristics for the 100-pin Package (3/3)
Control
Pin
Port
Interrupt
Pin
Timer Pin
UART Pin
Intelligent I/O Pin
Analog
Pin
Bus Control
Pin
76
P1_2
IIO0_2/IIO1_2
D10
77
P1_1
IIO0_1/IIO1_1
D9
78
P1_0
IIO0_0/IIO1_0
D8
79
P0_7
AN0_7
D7
80
P0_6
AN0_6
D6
81
P0_5
AN0_5
D5
82
P0_4
AN0_4
D4
83
P0_3
AN0_3
D3
84
P0_2
AN0_2
D2
85
P0_1
AN0_1
D1
86
P0_0
AN0_0
D0
87
P10_7 KI3
AN_7
88
P10_6 KI2
AN_6
89
P10_5 KI1
AN_5
90
P10_4 KI0
AN_4
91
P10_3
AN_3
92
P10_2
AN_2
93
P10_1
AN_1
P10_0
AN_0
94
AVSS
95
96
VREF
97
AVCC
ADTRG
98
P9_7
RXD4/SCL4/STXD4
99
P9_6
TXD4/SDA4/SRXD4
ANEX1
100
P9_5
CLK4
ANEX0
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1.5
1. Overview
Pin Definitions and Functions
Table 1.14 to Table 1.18 show the pin definitions and functions.
Table 1.14
Pin Definitions and Functions (1/4)
Function
Symbol
Power supply
VCC, VSS
Connecting pins
for decoupling
capacitor
VDC0, VDC1
Analog power
supply
AVCC, AVSS
Reset input
I/O
Description
I
Applicable as follows: VCC = 3.0 to 5.5 V, VSS = 0 V
—
A decoupling capacitor for internal voltage should be
connected between VDC0 and VDC1
I
Power supply for the A/D converter. AVCC and AVSS
should be connected to VCC and VSS, respectively
RESET
I
The MCU is reset when this pin is driven low
CNVSS
CNVSS
I
This pin should be connected to VSS via a resistor
Debug port
NSD
Main clock input
XIN
Main clock output XOUT
Sub clock input
XCIN
Sub clock output
XCOUT
BCLK output
BCLK
Clock output
CLKOUT
External interrupt INT0 to INT8 (1)
input
I/O
I
O
This pin is to communicate with a debugger. It should be
connected to VCC via a resistor of 1 to 4.7 kΩ
Input/output for the main clock oscillator. A crystal, or a
ceramic resonator should be connected between pins XIN
and XOUT. An external clock should be input at the XIN
while leaving the XOUT open
O
Input/output for the sub clock oscillator. A crystal oscillator
should be connected between pins XCIN and XCOUT. An
external clock should be input at the XCIN while leaving the
XCOUT open
O
BCLK output
O
Output of the clock with the same frequency as low speed
clocks, f8, or f32
I
I
Input for external interrupts
P8_5/NMI
I
Input for NMI
Key input interrupt KI0 to KI3
I
Input for the key input interrupt
NMI input
Bus control pins
D0 to D7
D8 to D15
D16 to D31 (2)
A0 to A23
I/O
Input/output of data (D0 to D7) while accessing an external
memory space with a separate bus
I/O
Input/output of data (D8 to D15) while accessing an
external memory space with 16-bit or 32-bit separate bus
I/O
Input/output of data (D16 to D31) while accessing an
external memory space with 32-bit separate bus
O
Output of address bits A0 to A23
I/O
Output of address bits (A0 to A7) and input/output of data
(D0 to D7) by time-division while accessing an external
memory space with multiplexed bus
I/O
Output of address bits (A8 to A15) and input/output of data
(D8 to D15) by time-division while accessing an external
memory space with 16-bit or 32-bit multiplexed bus
A0/D0 to A7/D7
A8/D8 to
A15/D15
Notes:
1. Pins INT6 to INT8 are available in the 144-pin package only.
2. Pins D16 to D31 are available in the 144-pin package only.
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Table 1.15
1. Overview
Pin Definitions and Functions (2/4)
Function
Bus control pins
Symbol
I/O
BC0/D0, BC2/D1
(1)
CS0 to CS3
Description
I/O
Output of byte control (BC0 and BC2) and input/output of
data (D0 and D1) by time-division while accessing an
external memory space with multiplexed bus
O
Chip select output
WR0/WR1/WR2/
WR3
WR/BC0/BC1/
BC2/BC3
RD (1)
Output of write, byte control, and read signals. Either WRx
or WR and BCx can be selected by a program.
Data is read when RD is low.
O
• When WR0, WR1, WR2, WR3, and RD are selected,
data is written to the following address:
4n+0, when WR0 is low
4n+1, when WR1 is low
4n+2, when WR2 is low
4n+3, when WR3 is low
on 32-bit external data bus
or
an even address, when WR0 is low
an odd address, when WR1 is low
on 16-bit external data bus
• When WR, BC0, BC1, BC2, BC3, and RD are selected,
data is written, when WR is low
and
the following address is accessed:
4n+0, when BC0 is low
4n+1, when BC1 is low
4n+2, when BC2 is low
4n+3, when BC3 is low
on 32-bit external data bus
or
an even address, when BC0 is low
an odd address, when BC1 is low
on 16-bit external data bus
ALE
O
Latch enable signal in multiplexed bus format
HOLD
I
The MCU is in a hold state while this pin is held low
HLDA
O
This pin is driven low while the MCU is held in a hold state
I
Bus cycle is extended by the CPU if this pin is low on the
falling edge of the BCLK
RDY
Note:
1. Pins BC2/D1, WR2, WR3, BC2, and BC3 are available in the 144-pin package only.
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Table 1.16
1. Overview
Pin Definitions and Functions (3/4)
Function
I/O port (1, 2)
Input port (2)
Timer A
Symbol
P0_0 to P0_7,
P1_0 to P1_7,
P2_0 to P2_7,
P3_0 to P3_7,
P4_0 to P4_7,
P5_0 to P5_7,
P6_0 to P6_7,
P7_0 to P7_7,
P8_0 to P8_4,
P8_6, P8_7,
P9_0 to P9_7,
P10_0 to P10_7,
P11_0 to P11_4,
P12_0 to P12_7,
P13_0 to P13_7,
P14_3 to P14_6,
P15_0 to P15_7
P9_1 (for 100-pin
package)
P14_1 (for 144pin package)
TA0OUT to
TA4OUT
I/O
Description
I/O ports in CMOS. Each port can be programmed to input
or output under the control of the direction register.
Some ports are 5 V tolerant inputs.
Pull-up resistors and N-channel open drain setting can be
enabled on some ports. Refer to Table 1.18 “Pin
Specifications” for details
I/O
I
I/O
Input port in CMOS
Pull-up resistor is selectable.
Refer to Table 1.18 “Pin Specifications” for details
Timers A0 to A4 input/output
TA0IN to TA4IN
I
Timers A0 to A4 input
Timer B
TB0IN to TB5IN
I
Timers B0 to B5 input
Three-phase
motor control
timer output
U,U,V,V,W,W
Serial interface
CTS0 to CTS8
I
Handshake input
RTS0 to RTS8
O
Handshake output
CLK0 to CLK8
I/O
Transmit/receive clock input/output
RXD0 to RXD8
I
Serial data input
TXD0 to TXD8
O
Serial data output
I2C bus
(simplified)
SDA0 to SDA6
I/O
Serial data input/output
SCL0 to SCL6
I/O
Transmit/receive clock input/output
Serial interface
special functions
STXD0 to
STXD6
O
SRXD0 to
SRXD6
I
SS0 to SS6
I
Three-phase motor control timer output
O
Serial data output in slave mode
Serial data input in slave mode
Input to control serial interface special functions
Notes:
1. Port P9_1 in the 100-pin package is an input-only port.
2. Ports P9_0, P9_2, and P11 to P15 are available in the 144-pin package only.
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Table 1.17
1. Overview
Pin Definitions and Functions (4/4)
Function
A/D converter
Symbol
I
ADTRG
I
I/O
External trigger input for the A/D converter
Expanded analog input for the A/D converter and output in
external op-amp connection mode
ANEX1
I
Expanded analog input for the A/D converter
DA0, DA1
O
Output for the D/A converter
I
Reference voltage input for the A/D converter and D/A
converter
I/O
Input/output for the Intelligent I/O group 0. Either input
capture or output compare is selectable
I/O
Input/output for the Intelligent I/O group 1. Either input
capture or output compare is selectable
Reference voltage VREF
input
Intelligent I/O
Description
Analog input for the A/D converter
AN_0 to AN_7,
AN0_0 to AN0_7,
AN2_0 to AN2_7,
AN15_0 to
AN15_7 (1)
ANEX0
D/A converter
I/O
IIO0_0 to IIO0_7
IIO1_0 to IIO1_7
Input for the two-phase encoder
UD0A, UD0B,
UD1A, UD1B
I
OUTC2_0 to
OUTC2_7 (2)
O
Output for OC (output compare) of the Intelligent I/O group
2
ISCLK2
I/O
Clock input/output for the serial interface
ISRXD2
I
Receive data input for the serial interface
ISTXD2
O
Transmit data output for the serial interface
IEIN
I
Receive data input for the serial interface
IEOUT
O
Transmit data output for the serial interface
Multi-master I2C- MSDA
bus
MSCL
I/O
Serial data input/output
I/O
Transmit/receive clock input/output
Notes:
1. Pins AN15_0 to AN15_7 are available in the 144-pin package only.
2. Pins OUTC2_3 to OUTC2_7 are available in the 144-pin package only.
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Table 1.18
1. Overview
Pin Specifications
Package
Selectable Functions
N-channel
open drain (2)
5 V tolerant input (3)
3
3
3
3
3
3
3
3
3
P7_0 to P7_7
3
3
3
3
P8_0 to P8_3
3
3
3
3
P8_4, P8_6, P8_7
3
3
P9_0 to P9_3 (144-pin)
3
Pin names
144pin
100pin
Pull-up resistor (1)
P0_0 to P0_7
3
3
3
P1_0 to P1_7
3
3
3
P2_0 to P2_7
3
3
3
P3_0 to P3_7
3
3
3
P4_0 to P4_7
3
3
P5_0 to P5_3
3
3
P5_4 to P5_7
3
P6_0 to P6_7
P9_1, P9_3 (100-pin)
3
3
3
3
3
P9_4 to P9_7
3
3
3
P10_0 to P10_7
3
3
3
P11_0 to P11_3
3
3
P11_4
3
3
P12_0 to P12_3
3
3
P12_4 to P12_7
3
3
P13_0 to P13_7
3
3
P14_1, P14_3
3
3
P14_4 to P14_6
3
3
P15_0 to P15_7
3
3
3
3
3
3
3
Notes:
1. Pull-up resistors are selected in 4-pin units, but are only enabled for those pins set as input ports.
2. N-channel open drain output can be enabled on the applicable pins on a discrete pin basis.
3. 5 V tolerant input is enabled when an applicable pin is set as an input port. When it is set as an I/O
port, to enable 5 V tolerant input, this pin should be set as N-channel open drain output.
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2.
2. Central Processing Unit (CPU)
Central Processing Unit (CPU)
The CPU contains registers as shown below. There are two register banks each consisting of registers
R2R0, R3R1, R6R4, R7R5, A0 to A3, SB, and FB.
General purpose
registers
b31
R2R0
R2H
R3R1
R3H
b23
R6R4
R6
R7R5
R7
b15
b7
R2L
R0H
R3L
R1H
b0
R0L
R1L
Data registers (1)
R4
R5
A0
A1
Address registers (1)
A2
A3
SB
Static base register (1)
FB
Frame base register (1)
USP
User stack pointer
ISP
Interrupt stack pointer
Interrupt vector table base register
INTB
b31
PC
Program counter
FLG
Flag register
b24 b23
b16 b15
RND
b8 b7
IPL
DP
FU
FO
b31
Fast interrupt
registers
DMAC-associated
registers (2)
b31
b0
U I O B S Z D C
Blank fields represent reserved.
b0
SVF
Save flag register
SVP
Save PC register
VCT
Vector register
b0
b23
DMD0
DMD0
DMD0
DMD0
DCT0
DCT0
DCT0
DCT0
DCR0
DCR0
DCR0
DCR0
DSA0
DSA0
DSA0
DSA0
DSR0
DSR0
DSR0
DSR0
DDA0
DDA0
DDA0
DDA0
DDR0
DDR0
DDR0
DDR0
DMA mode register
DMA terminal count register
DMA terminal count reload register
DMA source address register
DMA source address reload register
DMA destination address register
DMA destination address reload register
Notes:
1. There are two banks of these registers.
2. There are four identical sets of DMAC-associated registers.
Figure 2.1
CPU Registers
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2.1
2. Central Processing Unit (CPU)
General Purpose Registers
2.1.1
Data Registers (R2R0, R3R1, R6R4, and R7R5)
These 32-bit registers are primarily used for transfers and arithmetic/logic operations.
Each of the registers can be divided into upper and lower 16-bit registers, e.g. R2R0 can be divided into
R2 and R0, R3R0 can be divided into R3 and R1, etc.
Moreover, data registers R2R0 and R3R1 can be divided into four 8-bit data registers: upper (R2H and
R3H), mid-upper (R2L and R3L), mid-lower (R0H and R1H), and lower (R0L and R1L).
2.1.2
Address Registers (A0, A1, A2, and A3)
These 32-bit registers have functions similar to data registers. They are also used for address register
indirect addressing and address register relative addressing.
2.1.3
Static Base Register (SB)
This 32-bit register is used for SB relative addressing.
2.1.4
Frame Base Register (FB)
This 32-bit register is used for FB relative addressing.
2.1.5
Program Counter (PC)
This 32-bit counter indicates the address of the instruction to be executed next.
2.1.6
Interrupt Vector Table Base Register (INTB)
This 32-bit register indicates the start address of a relocatable vector table.
2.1.7
User Stack Pointer (USP) and Interrupt Stack Pointer (ISP)
Two types of 32-bit stack pointers (SPs) are provided: user stack pointer (USP) and interrupt stack
pointer (ISP).
Use the stack pointer select flag (U flag) to select either the user stack pointer (USP) or the interrupt
stack pointer (ISP). The U flag is bit 7 in the flag register (FLG). Refer to 2.1.8 “Flag Register (FLG)” for
details.
To minimize the overhead of interrupt sequence due to less memory access, set the user stack pointer
(USP) or the interrupt stack pointer (ISP) to a multiple of 4.
2.1.8
Flag Register (FLG)
This 32-bit register indicates the CPU status.
2.1.8.1
Carry Flag (C flag)
This flag becomes 1 when any of the carry, borrow, shifted-out bit, etc. is generated in the arithmetic
logic unit (ALU).
2.1.8.2
Debug Flag (D flag)
This flag is only for debugging. Only set this bit to 0.
2.1.8.3
Zero Flag (Z flag)
This flag becomes 1 when the result of an operation is 0; otherwise it is 0.
2.1.8.4
Sign Flag (S flag)
This flag becomes 1 when the result of an operation is a negative value; otherwise it is 0.
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2.1.8.5
2. Central Processing Unit (CPU)
Register Bank Select Flag (B flag)
This flag selects a register bank. It indicates 0 when the register bank 0 is selected, and 1 when the
register bank 1 is selected.
2.1.8.6
Overflow Flag (O flag)
This flag becomes 1 if an overflow occurs in an operation; otherwise it is 0.
2.1.8.7
Interrupt Enable Flag (I flag)
This flag enables maskable interrupts. To disable maskable interrupts, set this flag to 0. To enable
them, set this flag to 1. When an interrupt is accepted, the flag becomes 0.
2.1.8.8
Stack Pointer Select Flag (U flag)
To select the interrupt stack pointer (ISP), set this flag to 0. To select the user stack pointer (USP), set
this flag to 1.
It becomes 0 when a hardware interrupts is accepted or when an INT instruction designated by a
software interrupt number from 0 to 127 is executed.
2.1.8.9
Floating-point Underflow Flag (FU flag)
This flag becomes 1 when an underflow occurs in a floating-point operation; otherwise it is 0. It also
becomes 1 when the operand has invalid numbers (subnormal numbers).
2.1.8.10
Floating-point Overflow Flag (FO flag)
This flag becomes 1 when an overflow occurs in a floating-point operation; otherwise it is 0. It also
becomes 1 when the operand has invalid numbers (subnormal numbers).
2.1.8.11
Processor Interrupt Priority Level (IPL)
The processor interrupt priority level (IPL), consisting of three bits, selects a processor interrupt priority
level from level 0 to 7. An interrupt is acceptable when the interrupt request level is higher than the
selected IPL.
When the processor interrupt priority level (IPL) is set to 111b (level 7), all interrupts are disabled.
2.1.8.12
Fixed-point Radix Point Designation Bit (DP bit)
This bit designates the radix point. It also specifies which portion of the fixed-point multiplication result
to take. It is used in the MULX instruction.
2.1.8.13
Floating-point Rounding Mode (RND)
The 2-bit floating-point rounding mode selects a rounding mode for floating-point calculation results.
2.1.8.14
Reserved
Only set this bit to 0. The read value is undefined.
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2.2
2. Central Processing Unit (CPU)
Fast Interrupt Registers
The following three registers are provided to minimize the overhead of interrupt sequence.
2.2.1
Save Flag Register (SVF)
This 32-bit register is used to save the flag register when a fast interrupt is generated.
2.2.2
Save PC Register (SVP)
This 32-bit register is used to save the program counter when a fast interrupt is generated.
2.2.3
Vector Register (VCT)
This 32-bit register is used to indicate a jump address when a fast interrupt is generated.
2.3
DMAC-associated Registers
There are seven types of DMAC-associated registers.
2.3.1
DMA Mode Registers (DMD0, DMD1, DMD2, and DMD3)
These 32-bit registers are used to set DMA transfer mode, bit rate etc.
2.3.2
DMA Terminal Count Registers (DCT0, DCT1, DCT2, and DCT3)
These 24-bit registers are used to set DMA transfer counting.
2.3.3
DMA Terminal Count Reload Registers (DCR0, DCR1, DCR2, and DCR3)
These 24-bit registers are used to set the reloaded values for DMA terminal count registers.
2.3.4
DMA Source Address Registers (DSA0, DSA1, DSA2, and DSA3)
These 32-bit registers are used to set DMA source addresses.
2.3.5
DMA Source Address Reload Registers (DSR0, DSR1, DSR2, and DSR3)
These 32-bit registers are used to set the reloaded value for DMA source address register.
2.3.6
DMA Destination Address Registers (DDA0, DDA1, DDA2, and DDA3)
These 32-bit registers are used to set DMA destination address.
2.3.7
DMA Destination Address Reload Registers (DDR0, DDR1, DDR2, and
DDR3)
These 32-bit registers are used to set reloaded values for DMA destination address registers.
REJ03B0253-0110
Jun 23, 2010
Rev.1.10
Page 27 of 95
R32C/116 Group
3.
3. Memory
Memory
Figure 3.1 shows the memory map of the R32C/116 Group.
The R32C/116 Group provides a 4-Gbyte address space from 00000000h to FFFFFFFFh.
The internal ROM is mapped to the end of the memory map with the ending address fixed at FFFFFFFFh.
Therefore, the 1-Mbyte internal ROM is mapped from FFF00000h to FFFFFFFFh.
The fixed interrupt vector table which contains each start address of interrupt handlers is mapped from
FFFFFFDCh to FFFFFFFFh.
The internal RAM is mapped to the beginning of the memory map with the starting address fixed at
00000400h. Therefore, the 63-Kbyte internal RAM is mapped from 00000400h to 0000FFFFh. Besides
being used for data storage, the internal RAM functions as a stack(s) for subroutines and/or interrupt
handlers.
Special Function Registers (SFRs), which are control registers for peripheral functions, are mapped from
00000000h to 000003FFh, and from 00040000h to 0004FFFFh. Unoccupied SFR locations are reserved.
No access is allowed.
In memory expansion mode or microprocessor mode, some spaces are reserved for internal use and should
not be accessed.
00000000h
SFR1
00000400h
Internal RAM
Internal RAM
Capacity
XXXXXXXXh
40 Kbytes
0000A400h
48 Kbytes
0000C400h
63 Kbytes
00010000h
XXXXXXXXh
Reserved
00040000h
SFR2
00050000h
Reserved
00060000h
Internal ROM
Capacity
YYYYYYYYh
384 Kbytes
FFFA0000h
512 Kbytes
FFF80000h
640 Kbytes
FFF60000h
768 Kbytes
FFF40000h
1 Mbyte
FFF00000h
Internal ROM
(Data space) (1)
00062000h
Reserved
00080000h
External space (2)
FFE00000h
Reserved (3)
YYYYYYYYh
Internal ROM (4)
FFFFFFFFh
FFFFFFDCh Undefined instruction
Overflow
BRK instruction
Reserved
Reserved
Watchdog timer (5)
Reserved
NMI
Reset
FFFFFFFFh
Notes:
1. Additional two 4-Kbyte spaces (blocks A and B) for storing data are provided in the flash memory version.
2. This space can be used in memory expansion mode or microprocessor mode. Addresses from 02000000h
to FDFFFFFFh are inaccessible.
3. This space is reserved in memory expansion mode. It can be external space in microprocessor mode.
4. This space can be used in single-chip mode or memory expansion mode. It can be external space in
microprocessor mode.
5. The watchdog timer interrupt shares the vector table with the oscillator stop detection interrupt and low
voltage detection interrupt.
Figure 3.1
Memory Map
REJ03B0253-0110
Jun 23, 2010
Rev.1.10
Page 28 of 95
R32C/116 Group
4.
4. Special Function Registers (SFRs)
Special Function Registers (SFRs)
SFRs are memory-mapped peripheral registers that control the operation of peripherals. Table 4.1 SFR List
(1) to Table 4.25 SFR List (25) list the SFR details.
Table 4.1
SFR List (1)
Address
Register
000000h
000001h
000002h
000003h
000004h Clock Control Register
000005h
000006h Flash Memory Control Register
000007h Protect Release Register
000008h
000009h
00000Ah
00000Bh
00000Ch
00000Dh
00000Eh
00000Fh
000010h External Bus Control Register 3/Flash Memory Rewrite Bus
000011h Control Register 3
000012h Chip Selects 2 and 3 Boundary Setting Register
000013h
000014h External Bus Control Register 2
000015h
000016h Chip Selects 1 and 2 Boundary Setting Register
000017h
000018h External Bus Control Register 1
000019h
00001Ah Chip selects 0 and 1 Boundary Setting Register
00001Bh
00001Ch External Bus Control Register 0/Flash Memory Rewrite Bus
00001Dh Control Register 0
00001Eh Peripheral Bus Control Register
00001Fh
000020h to
00005Fh
X: Undefined
Blanks are reserved. No access is allowed.
REJ03B0253-0110
Jun 23, 2010
Rev.1.10
Symbol
Reset Value
CCR
0001 1000b
FMCR
PRR
0000 0001b
00h
EBC3/FEBC3
0000h
CB23
00h
EBC2
0000h
CB12
00h
EBC1
0000h
CB01
00h
EBC0/FEBC0
0000h
PBC
0504h
Page 29 of 95
R32C/116 Group
Table 4.2
4. Special Function Registers (SFRs)
SFR List (2)
Address
Register
000060h
000061h Timer B5 Interrupt Control Register
000062h UART5 Transmit/NACK Interrupt Control Register
000063h UART2 Receive/ACK Interrupt Control Register/I2C Bus Line
Interrupt Control Register
000064h UART6 Transmit/NACK Interrupt Control Register
000065h UART3 Receive/ACK Interrupt Control Register
000066h UART5/6 Bus Collision, Start Condition/Stop Condition
Detection Interrupt Control Register
000067h UART4 Receive/ACK Interrupt Control Register
000068h DMA0 Transfer Complete Interrupt Control Register
000069h UART0/3 Bus Collision, Start Condition/Stop Condition
Detection Interrupt Control Register
00006Ah DMA2 Transfer Complete Interrupt Control Register
00006Bh A/D Converter 0 Convert Completion Interrupt Control Register
00006Ch Timer A0 Interrupt Control Register
00006Dh Intelligent I/O Interrupt Control Register 0
00006Eh Timer A2 Interrupt Control Register
00006Fh Intelligent I/O Interrupt Control Register 2
000070h Timer A4 Interrupt Control Register
000071h Intelligent I/O Interrupt Control Register 4
000072h UART0 Receive/ACK Interrupt Control Register
000073h Intelligent I/O Interrupt Control Register 6
000074h UART1 Receive/ACK Interrupt Control Register
000075h Intelligent I/O Interrupt Control Register 8
000076h Timer B1 Interrupt Control Register
000077h Intelligent I/O Interrupt Control Register 10
000078h Timer B3 Interrupt Control Register
000079h
00007Ah INT5 Interrupt Control Register
00007Bh
00007Ch INT3 Interrupt Control Register
00007Dh
00007Eh INT1 Interrupt Control Register
00007Fh
000080h
000081h UART2 Transmit/NACK Interrupt Control Register/I2C-Bus
Interrupt Control Register
000082h UART5 Receive/ACK Interrupt Control Register
000083h UART3 Transmit/NACK Interrupt Control Register
000084h UART6 Receive/ACK Interrupt Control Register
000085h UART4 Transmit/NACK Interrupt Control Register
000086h
000087h UART2 Bus Collision, Start Condition/Stop Condition Detection
Interrupt Control Register
X: Undefined
Blanks are reserved. No access is allowed.
REJ03B0253-0110
Jun 23, 2010
Rev.1.10
Symbol
Reset Value
TB5IC
S5TIC
S2RIC/I2CLIC
XXXX X000b
XXXX X000b
XXXX X000b
S6TIC
S3RIC
BCN5IC/BCN6IC
XXXX X000b
XXXX X000b
XXXX X000b
S4RIC
DM0IC
BCN0IC/BCN3IC
XXXX X000b
XXXX X000b
XXXX X000b
DM2IC
AD0IC
TA0IC
IIO0IC
TA2IC
IIO2IC
TA4IC
IIO4IC
S0RIC
IIO6IC
S1RIC
IIO8IC
TB1IC
IIO10IC
TB3IC
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
INT5IC
XX00 X000b
INT3IC
XX00 X000b
INT1IC
XX00 X000b
S2TIC/I2CIC
XXXX X000b
S5RIC
S3TIC
S6RIC
S4TIC
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
BCN2IC
XXXX X000b
Page 30 of 95
R32C/116 Group
Table 4.3
4. Special Function Registers (SFRs)
SFR List (3)
Address
Register
000088h DMA1 Transfer Complete Interrupt Control Register
000089h UART1/4 Bus Collision, Start Condition/Stop Condition
Detection Interrupt Control Register
00008Ah DMA3 Transfer Complete Interrupt Control Register
00008Bh Key Input Interrupt Control Register
00008Ch Timer A1 Interrupt Control Register
00008Dh Intelligent I/O Interrupt Control Register 1
00008Eh Timer A3 Interrupt Control Register
00008Fh Intelligent I/O Interrupt Control Register 3
000090h UART0 Transmit/NACK Interrupt Control Register
000091h Intelligent I/O Interrupt Control Register 5
000092h UART1 Transmit/NACK Interrupt Control Register
000093h Intelligent I/O Interrupt Control Register 7
000094h Timer B0 Interrupt Control Register
000095h Intelligent I/O Interrupt Control Register 9
000096h Timer B2 Interrupt Control Register
000097h Intelligent I/O Interrupt Control Register 11
000098h Timer B4 Interrupt Control Register
000099h
00009Ah INT4 Interrupt Control Register
00009Bh
00009Ch INT2 Interrupt Control Register
00009Dh
00009Eh INT0 Interrupt Control Register
00009Fh
0000A0h Intelligent I/O Interrupt Request Register 0
0000A1h Intelligent I/O Interrupt Request Register 1
0000A2h Intelligent I/O Interrupt Request Register 2
0000A3h Intelligent I/O Interrupt Request Register 3
0000A4h Intelligent I/O Interrupt Request Register 4
0000A5h Intelligent I/O Interrupt Request Register 5
0000A6h Intelligent I/O Interrupt Request Register 6
0000A7h Intelligent I/O Interrupt Request Register 7
0000A8h Intelligent I/O Interrupt Request Register 8
0000A9h Intelligent I/O Interrupt Request Register 9
0000AAh Intelligent I/O Interrupt Request Register 10
0000ABh Intelligent I/O Interrupt Request Register 11
0000ACh
0000ADh
0000AEh
0000AFh
X: Undefined
Blanks are reserved. No access is allowed.
REJ03B0253-0110
Jun 23, 2010
Rev.1.10
Symbol
DM1IC
BCN1IC/BCN4IC
Reset Value
XXXX X000b
XXXX X000b
DM3IC
KUPIC
TA1IC
IIO1IC
TA3IC
IIO3IC
S0TIC
IIO5IC
S1TIC
IIO7IC
TB0IC
IIO9IC
TB2IC
IIO11IC
TB4IC
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
INT4IC
XX00 X000b
INT2IC
XX00 X000b
INT0IC
XX00 X000b
IIO0IR
IIO1IR
IIO2IR
IIO3IR
IIO4IR
IIO5IR
IIO6IR
IIO7IR
IIO8IR
IIO9IR
IIO10IR
IIO11IR
0000 0XX1b
0000 0XX1b
0000 0X01b
0000 XXX1b
000X 0XX1b
000X 0XX1b
000X 0XX1b
X00X 0XX1b
XX0X 0XX1b
0X00 0XX1b
0X00 0XX1b
0X00 0XX1b
Page 31 of 95
R32C/116 Group
Table 4.4
4. Special Function Registers (SFRs)
SFR List (4)
Address
Register
0000B0h Intelligent I/O Interrupt Enable Register 0
0000B1h Intelligent I/O Interrupt Enable Register 1
0000B2h Intelligent I/O Interrupt Enable Register 2
0000B3h Intelligent I/O Interrupt Enable Register 3
0000B4h Intelligent I/O Interrupt Enable Register 4
0000B5h Intelligent I/O Interrupt Enable Register 5
0000B6h Intelligent I/O Interrupt Enable Register 6
0000B7h Intelligent I/O Interrupt Enable Register 7
0000B8h Intelligent I/O Interrupt Enable Register 8
0000B9h Intelligent I/O Interrupt Enable Register 9
0000BAh Intelligent I/O Interrupt Enable Register 10
0000BBh Intelligent I/O Interrupt Enable Register 11
0000BCh
0000BDh
0000BEh
0000BFh
0000C0h
0000C1h
0000C2h
0000C3h
0000C4h
0000C5h
0000C6h
0000C7h
0000C8h
0000C9h
0000CAh
0000CBh
0000CCh
0000CDh
0000CEh
0000CFh
0000D0h
0000D1h
0000D2h
0000D3h
0000D4h
0000D5h
0000D6h
0000D7h
0000D8h
0000D9h
0000DAh
0000DBh
0000DCh
0000DDh UART7 Transmit Interrupt Control Register
0000DEh INT7 Interrupt Control Register
0000DFh UART8 Transmit Interrupt Control Register
X: Undefined
Blanks are reserved. No access is allowed.
REJ03B0253-0110
Jun 23, 2010
Rev.1.10
Symbol
IIO0IE
IIO1IE
IIO2IE
IIO3IE
IIO4IE
IIO5IE
IIO6IE
IIO7IE
IIO8IE
IIO9IE
IIO10IE
IIO11IE
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
Reset Value
S7TIC
INT7IC
S8TIC
XXXX X000b
XX00 X000b
XXXX X000b
Page 32 of 95
R32C/116 Group
Table 4.5
4. Special Function Registers (SFRs)
SFR List (5)
Address
Register
0000E0h
0000E1h
0000E2h
0000E3h
0000E4h
0000E5h
0000E6h
0000E7h
0000E8h
0000E9h
0000EAh
0000EBh
0000ECh
0000EDh
0000EEh
0000EFh
0000F0h
0000F1h
0000F2h
0000F3h
0000F4h
0000F5h
0000F6h
0000F7h
0000F8h
0000F9h
0000FAh
0000FBh
0000FCh INT8 Interrupt Control Register
0000FDh UART7 Receive Interrupt Control Register
0000FEh INT6 Interrupt Control Register
0000FFh UART8 Receive Interrupt Control Register
000100h Group 1 Time Measurement/Waveform Generation Register 0
000101h
000102h Group 1 Time Measurement/Waveform Generation Register 1
000103h
000104h Group 1 Time Measurement/Waveform Generation Register 2
000105h
000106h Group 1 Time Measurement/Waveform Generation Register 3
000107h
X: Undefined
Blanks are reserved. No access is allowed.
REJ03B0253-0110
Jun 23, 2010
Rev.1.10
Symbol
Reset Value
INT8IC
S7RIC
INT6IC
S8RIC
G1TM0/G1PO0
XX00 X000b
XXXX X000b
XX00 X000b
XXXX X000b
XXXXh
G1TM1/G1PO1
XXXXh
G1TM2/G1PO2
XXXXh
G1TM3/G1PO3
XXXXh
Page 33 of 95
R32C/116 Group
Table 4.6
4. Special Function Registers (SFRs)
SFR List (6)
Address
Register
000108h Group 1 Time Measurement/Waveform Generation Register 4
000109h
00010Ah Group 1 Time Measurement/Waveform Generation Register 5
00010Bh
00010Ch Group 1 Time Measurement/Waveform Generation Register 6
00010Dh
00010Eh Group 1 Time Measurement/Waveform Generation Register 7
00010Fh
000110h Group 1 Waveform Generation Control Register 0
000111h Group 1 Waveform Generation Control Register 1
000112h Group 1 Waveform Generation Control Register 2
000113h Group 1 Waveform Generation Control Register 3
000114h Group 1 Waveform Generation Control Register 4
000115h Group 1 Waveform Generation Control Register 5
000116h Group 1 Waveform Generation Control Register 6
000117h Group 1 Waveform Generation Control Register 7
000118h Group 1 Time Measurement Control Register 0
000119h Group 1 Time Measurement Control Register 1
00011Ah Group 1 Time Measurement Control Register 2
00011Bh Group 1 Time Measurement Control Register 3
00011Ch Group 1 Time Measurement Control Register 4
00011Dh Group 1 Time Measurement Control Register 5
00011Eh Group 1 Time Measurement Control Register 6
00011Fh Group 1 Time Measurement Control Register 7
000120h Group 1 Base Timer Register
000121h
000122h Group 1 Base Timer Control Register 0
000123h Group 1 Base Timer Control Register 1
000124h Group 1 Time Measurement Prescaler Register 6
000125h Group 1 Time Measurement Prescaler Register 7
000126h Group 1 Function Enable Register
000127h Group 1 Function Select Register
000128h
000129h
00012Ah
00012Bh
00012Ch
00012Dh
00012Eh
00012Fh
000130h to
00013Fh
X: Undefined
Blanks are reserved. No access is allowed.
REJ03B0253-0110
Jun 23, 2010
Rev.1.10
Symbol
G1TM4/G1PO4
Reset Value
XXXXh
G1TM5/G1PO5
XXXXh
G1TM6/G1PO6
XXXXh
G1TM7/G1PO7
XXXXh
G1POCR0
G1POCR1
G1POCR2
G1POCR3
G1POCR4
G1POCR5
G1POCR6
G1POCR7
G1TMCR0
G1TMCR1
G1TMCR2
G1TMCR3
G1TMCR4
G1TMCR5
G1TMCR6
G1TMCR7
G1BT
0000 X000b
0X00 X000b
0X00 X000b
0X00 X000b
0X00 X000b
0X00 X000b
0X00 X000b
0X00 X000b
00h
00h
00h
00h
00h
00h
00h
00h
XXXXh
G1BCR0
G1BCR1
G1TPR6
G1TPR7
G1FE
G1FS
00h
0000 0000b
00h
00h
00h
00h
Page 34 of 95
R32C/116 Group
Table 4.7
4. Special Function Registers (SFRs)
SFR List (7)
Address
Register
000140h Group 2 Waveform Generation Register 0
000141h
000142h Group 2 Waveform Generation Register 1
000143h
000144h Group 2 Waveform Generation Register 2
000145h
000146h Group 2 Waveform Generation Register 3
000147h
000148h Group 2 Waveform Generation Register 4
000149h
00014Ah Group 2 Waveform Generation Register 5
00014Bh
00014Ch Group 2 Waveform Generation Register 6
00014Dh
00014Eh Group 2 Waveform Generation Register 7
00014Fh
000150h Group 2 Waveform Generation Control Register 0
000151h Group 2 Waveform Generation Control Register 1
000152h Group 2 Waveform Generation Control Register 2
000153h Group 2 Waveform Generation Control Register 3
000154h Group 2 Waveform Generation Control Register 4
000155h Group 2 Waveform Generation Control Register 5
000156h Group 2 Waveform Generation Control Register 6
000157h Group 2 Waveform Generation Control Register 7
000158h
000159h
00015Ah
00015Bh
00015Ch
00015Dh
00015Eh
00015Fh
000160h Group 2 Base Timer Register
000161h
000162h Group 2 Base Timer Control Register 0
000163h Group 2 Base Timer Control Register 1
000164h Base Timer Start Register
000165h
000166h Group 2 Function Enable Register
000167h Group 2 RTP Output Buffer Register
000168h
000169h
00016Ah Group 2 Serial Interface Mode Register
00016Bh Group 2 Serial Interface Control Register
00016Ch Group 2 SI/O Transmit Buffer Register
00016Dh
00016Eh Group 2 SI/O Receive Buffer Register
00016Fh
X: Undefined
Blanks are reserved. No access is allowed.
REJ03B0253-0110
Jun 23, 2010
Rev.1.10
Symbol
G2PO0
Reset Value
XXXXh
G2PO1
XXXXh
G2PO2
XXXXh
G2PO3
XXXXh
G2PO4
XXXXh
G2PO5
XXXXh
G2PO6
XXXXh
G2PO7
XXXXh
G2POCR0
G2POCR1
G2POCR2
G2POCR3
G2POCR4
G2POCR5
G2POCR6
G2POCR7
0000 0000b
0000 0000b
0000 0000b
0000 0000b
0000 0000b
0000 0000b
0000 0000b
0000 0000b
G2BT
XXXXh
G2BCR0
G2BCR1
BTSR
00h
0000 0000b
XXXX 0000b
G2FE
G2RTP
00h
00h
G2MR
G2CR
G2TB
00XX X000b
0000 X110b
XXXXh
G2RB
XXXXh
Page 35 of 95
R32C/116 Group
Table 4.8
4. Special Function Registers (SFRs)
SFR List (8)
Address
Register
000170h Group 2 IEBus Address Register
000171h
000172h Group 2 IEBus Control Register
000173h Group 2 IEBus Transmit Interrupt Source Detect Register
000174h Group 2 IEBus Receive Interrupt Source Detect Register
000175h
000176h
000177h
000178h
000179h
00017Ah
00017Bh
00017Ch
00017Dh
00017Eh
00017Fh
000180h Group 0 Time Measurement/Waveform Generation Register 0
000181h
000182h Group 0 Time Measurement/Waveform Generation Register 1
000183h
000184h Group 0 Time Measurement/Waveform Generation Register 2
000185h
000186h Group 0 Time Measurement/Waveform Generation Register 3
000187h
000188h Group 0 Time Measurement/Waveform Generation Register 4
000189h
00018Ah Group 0 Time Measurement/Waveform Generation Register 5
00018Bh
00018Ch Group 0 Time Measurement/Waveform Generation Register 6
00018Dh
00018Eh Group 0 Time Measurement/Waveform Generation Register 7
00018Fh
000190h Group 0 Waveform Generation Control Register 0
000191h Group 0 Waveform Generation Control Register 1
000192h Group 0 Waveform Generation Control Register 2
000193h Group 0 Waveform Generation Control Register 3
000194h Group 0 Waveform Generation Control Register 4
000195h Group 0 Waveform Generation Control Register 5
000196h Group 0 Waveform Generation Control Register 6
000197h Group 0 Waveform Generation Control Register 7
000198h Group 0 Time Measurement Control Register 0
000199h Group 0 Time Measurement Control Register 1
00019Ah Group 0 Time Measurement Control Register 2
00019Bh Group 0 Time Measurement Control Register 3
00019Ch Group 0 Time Measurement Control Register 4
00019Dh Group 0 Time Measurement Control Register 5
00019Eh Group 0 Time Measurement Control Register 6
00019Fh Group 0 Time Measurement Control Register 7
X: Undefined
Blanks are reserved. No access is allowed.
REJ03B0253-0110
Jun 23, 2010
Rev.1.10
IEAR
Symbol
Reset Value
XXXXh
IECR
IETIF
IERIF
00XX X000b
XXX0 0000b
XXX0 0000b
G0TM0/G0PO0
XXXXh
G0TM1/G0PO1
XXXXh
G0TM2/G0PO2
XXXXh
G0TM3/G0PO3
XXXXh
G0TM4/G0PO4
XXXXh
G0TM5/G0PO5
XXXXh
G0TM6/G0PO6
XXXXh
G0TM7/G0PO7
XXXXh
G0POCR0
G0POCR1
G0POCR2
G0POCR3
G0POCR4
G0POCR5
G0POCR6
G0POCR7
G0TMCR0
G0TMCR1
G0TMCR2
G0TMCR3
G0TMCR4
G0TMCR5
G0TMCR6
G0TMCR7
0000 X000b
0X00 X000b
0X00 X000b
0X00 X000b
0X00 X000b
0X00 X000b
0X00 X000b
0X00 X000b
00h
00h
00h
00h
00h
00h
00h
00h
Page 36 of 95
R32C/116 Group
Table 4.9
4. Special Function Registers (SFRs)
SFR List (9)
Address
Register
0001A0h Group 0 Base Timer Register
0001A1h
0001A2h Group 0 Base Timer Control Register 0
0001A3h Group 0 Base Timer Control Register 1
0001A4h Group 0 Time Measurement Prescaler Register 6
0001A5h Group 0 Time Measurement Prescaler Register 7
0001A6h Group 0 Function Enable Register
0001A7h Group 0 Function Select Register
0001A8h
0001A9h
0001AAh
0001ABh
0001ACh
0001ADh
0001AEh
0001AFh
0001B0h
0001B1h
0001B2h
0001B3h
0001B4h
0001B5h
0001B6h
0001B7h
0001B8h
0001B9h
0001BAh
0001BBh
0001BCh
0001BDh
0001BEh
0001BFh
0001C0h
0001C1h
0001C2h
0001C3h
0001C4h UART5 Special Mode Register 4
0001C5h UART5 Special Mode Register 3
0001C6h UART5 Special Mode Register 2
0001C7h UART5 Special Mode Register
0001C8h UART5 Transmit/Receive Mode Register
0001C9h UART5 Bit Rate Register
0001CAh UART5 Transmit Buffer Register
0001CBh
0001CCh UART5 Transmit/Receive Control Register 0
0001CDh UART5 Transmit/Receive Control Register 1
0001CEh UART5 Receive Buffer Register
0001CFh
X: Undefined
Blanks are reserved. No access is allowed.
REJ03B0253-0110
Jun 23, 2010
Rev.1.10
G0BT
Symbol
Reset Value
XXXXh
G0BCR0
G0BCR1
G0TPR6
G0TPR7
G0FE
G0FS
00h
0000 0000b
00h
00h
00h
00h
U5SMR4
U5SMR3
U5SMR2
U5SMR
U5MR
U5BRG
U5TB
00h
00h
00h
00h
00h
XXh
XXXXh
U5C0
U5C1
U5RB
0000 1000b
0000 0010b
XXXXh
Page 37 of 95
R32C/116 Group
Table 4.10
4. Special Function Registers (SFRs)
SFR List (10)
Address
Register
0001D0h
0001D1h
0001D2h
0001D3h
0001D4h UART6 Special Mode Register 4
0001D5h UART6 Special Mode Register 3
0001D6h UART6 Special Mode Register 2
0001D7h UART6 Special Mode Register
0001D8h UART6 Transmit/Receive Mode Register
0001D9h UART6 Bit Rate Register
0001DAh UART6 Transmit Buffer Register
0001DBh
0001DCh UART6 Transmit/Receive Control Register 0
0001DDh UART6 Transmit/Receive Control Register 1
0001DEh UART6 Receive Buffer Register
0001DFh
0001E0h UART7 Transmit/Receive Mode Register
0001E1h UART7 Bit Rate Register
0001E2h UART7 Transmit Buffer Register
0001E3h
0001E4h UART7 Transmit/Receive Control Register 0
0001E5h UART7 Transmit/Receive Control Register 1
0001E6h UART7 Receive Buffer Register
0001E7h
0001E8h UART8 Transmit/Receive Mode Register
0001E9h UART8 Bit Rate Register
0001EAh UART8 Transmit Buffer Register
0001EBh
0001ECh UART8 Transmit/Receive Control Register 0
0001EDh UART8 Transmit/Receive Control Register 1
0001EEh UART8 Receive Buffer Register
0001EFh
0001F0h UART7, UART8 Transmit/Receive Control Register 2
0001F1h
0001F2h
0001F3h
0001F4h
0001F5h
0001F6h
0001F7h
0001F8h
0001F9h
0001FAh
0001FBh
0001FCh
0001FDh
0001FEh
0001FFh
X: Undefined
Blanks are reserved. No access is allowed.
REJ03B0253-0110
Jun 23, 2010
Rev.1.10
Symbol
Reset Value
U6SMR4
U6SMR3
U6SMR2
U6SMR
U6MR
U6BRG
U6TB
00h
00h
00h
00h
00h
XXh
XXXXh
U6C0
U6C1
U6RB
0000 1000b
0000 0010b
XXXXh
U7MR
U7BRG
U7TB
00h
XXh
XXXXh
U7C0
U7C1
U7RB
00X0 1000b
XXXX 0010b
XXXXh
U8MR
U8BRG
U8TB
00h
XXh
XXXXh
U8C0
U8C1
U8RB
00X0 1000b
XXXX 0010b
XXXXh
U78CON
X000 0000b
Page 38 of 95
R32C/116 Group
Table 4.11
4. Special Function Registers (SFRs)
SFR List (11)
Address
Register
000200h to
0002BFh
0002C0h X0 Register/Y0 Register
0002C1h
0002C2h X1 Register/Y1 Register
0002C3h
0002C4h X2 Register/Y2 Register
0002C5h
0002C6h X3 Register/Y3 Register
0002C7h
0002C8h X4 Register/Y4 Register
0002C9h
0002CAh X5 Register/Y5 Register
0002CBh
0002CCh X6 Register/Y6 Register
0002CDh
0002CEh X7 Register/Y7 Register
0002CFh
0002D0h X8 Register/Y8 Register
0002D1h
0002D2h X9 Register/Y9 Register
0002D3h
0002D4h X10 Register/Y10 Register
0002D5h
0002D6h X11 Register/Y11 Register
0002D7h
0002D8h X12 Register/Y12 Register
0002D9h
0002DAh X13 Register/Y13 Register
0002DBh
0002DCh X14 Register/Y14 Register
0002DDh
0002DEh X15 Register/Y15 Register
0002DFh
0002E0h X-Y Control Register
0002E1h
0002E2h
0002E3h
0002E4h UART1 Special Mode Register 4
0002E5h UART1 Special Mode Register 3
0002E6h UART1 Special Mode Register 2
0002E7h UART1 Special Mode Register
0002E8h UART1 Transmit/Receive Mode Register
0002E9h UART1 Bit Rate Register
0002EAh UART1 Transmit Buffer Register
0002EBh
0002ECh UART1 Transmit/Receive Control Register 0
0002EDh UART1 Transmit/Receive Control Register 1
0002EEh UART1 Receive Buffer Register
0002EFh
X: Undefined
Blanks are reserved. No access is allowed.
REJ03B0253-0110
Jun 23, 2010
Rev.1.10
Symbol
Reset Value
X0R/Y0R
XXXXh
X1R/Y1R
XXXXh
X2R/Y2R
XXXXh
X3R/Y3R
XXXXh
X4R/Y4R
XXXXh
X5R/Y5R
XXXXh
X6R/Y6R
XXXXh
X7R/Y7R
XXXXh
X8R/Y8R
XXXXh
X9R/Y9R
XXXXh
X10R/Y10R
XXXXh
X11R/Y11R
XXXXh
X12R/Y12R
XXXXh
X13R/Y13R
XXXXh
X14R/Y14R
XXXXh
X15R/Y15R
XXXXh
XYC
XXXX XX00b
U1SMR4
U1SMR3
U1SMR2
U1SMR
U1MR
U1BRG
U1TB
00h
00h
00h
00h
00h
XXh
XXXXh
U1C0
U1C1
U1RB
0000 1000b
0000 0010b
XXXXh
Page 39 of 95
R32C/116 Group
Table 4.12
4. Special Function Registers (SFRs)
SFR List (12)
Address
Register
0002F0h
0002F1h
0002F2h
0002F3h
0002F4h UART4 Special Mode Register 4
0002F5h UART4 Special Mode Register 3
0002F6h UART4 Special Mode Register 2
0002F7h UART4 Special Mode Register
0002F8h UART4 Transmit/Receive Mode Register
0002F9h UART4 Bit Rate Register
0002FAh UART4 Transmit Buffer Register
0002FBh
0002FCh UART4 Transmit/Receive Control Register 0
0002FDh UART4 Transmit/Receive Control Register 1
0002FEh UART4 Receive Buffer Register
0002FFh
000300h Count Start Register for Timers B3, B4, and B5
000301h
000302h Timer A1-1 Register
000303h
000304h Timer A2-1 Register
000305h
000306h Timer A4-1 Register
000307h
000308h Three-phase PWM Control Register 0
000309h Three-phase PWM Control Register 1
00030Ah Three-phase Output Buffer Register 0
00030Bh Three-phase Output Buffer Register 1
00030Ch Dead Time Timer
00030Dh Timer B2 Interrupt Generating Frequency Set Counter
00030Eh
00030Fh
000310h Timer B3 Register
000311h
000312h Timer B4 Register
000313h
000314h Timer B5 Register
000315h
000316h
000317h
000318h
000319h
00031Ah
00031Bh Timer B3 Mode Register
00031Ch Timer B4 Mode Register
00031Dh Timer B5 Mode Register
00031Eh
00031Fh
X: Undefined
Blanks are reserved. No access is allowed.
REJ03B0253-0110
Jun 23, 2010
Rev.1.10
Symbol
Reset Value
U4SMR4
U4SMR3
U4SMR2
U4SMR
U4MR
U4BRG
U4TB
00h
00h
00h
00h
00h
XXh
XXXXh
U4C0
U4C1
U4RB
0000 1000b
0000 0010b
XXXXh
TBSR
000X XXXXb
TA11
XXXXh
TA21
XXXXh
TA41
XXXXh
INVC0
INVC1
IDB0
IDB1
DTT
ICTB2
00h
00h
XX11 1111b
XX11 1111b
XXh
XXh
TB3
XXXXh
TB4
XXXXh
TB5
XXXXh
TB3MR
TB4MR
TB5MR
00XX 0000b
00XX 0000b
00XX 0000b
Page 40 of 95
R32C/116 Group
Table 4.13
4. Special Function Registers (SFRs)
SFR List (13)
Address
Register
000320h
000321h
000322h
000323h
000324h UART3 Special Mode Register 4
000325h UART3 Special Mode Register 3
000326h UART3 Special Mode Register 2
000327h UART3 Special Mode Register
000328h UART3 Transmit/Receive Mode Register
000329h UART3 Bit Rate Register
00032Ah UART3 Transmit Buffer Register
00032Bh
00032Ch UART3 Transmit/Receive Control Register 0
00032Dh UART3 Transmit/Receive Control Register 1
00032Eh UART3 Receive Buffer Register
00032Fh
000330h
000331h
000332h
000333h
000334h UART2 Special Mode Register 4
000335h UART2 Special Mode Register 3
000336h UART2 Special Mode Register 2
000337h UART2 Special Mode Register
000338h UART2 Transmit/Receive Mode Register
000339h UART2 Bit Rate Register
00033Ah UART2 Transmit Buffer Register
00033Bh
00033Ch UART2 Transmit/Receive Control Register 0
00033Dh UART2 Transmit/Receive Control Register 1
00033Eh UART2 Receive Buffer Register
00033Fh
000340h Count Start Register
000341h Clock Prescaler Reset Register
000342h One-shot Start Register
000343h Trigger Select Register
000344h Increment/Decrement Counting Select Register
000345h
000346h Timer A0 Register
000347h
000348h Timer A1 Register
000349h
00034Ah Timer A2 Register
00034Bh
00034Ch Timer A3 Register
00034Dh
00034Eh Timer A4 Register
00034Fh
X: Undefined
Blanks are reserved. No access is allowed.
REJ03B0253-0110
Jun 23, 2010
Rev.1.10
Symbol
Reset Value
U3SMR4
U3SMR3
U3SMR2
U3SMR
U3MR
U3BRG
U3TB
00h
00h
00h
00h
00h
XXh
XXXXh
U3C0
U3C1
U3RB
0000 1000b
0000 0010b
XXXXh
U2SMR4
U2SMR3
U2SMR2
U2SMR
U2MR
U2BRG
U2TB
00h
00h
00h
00h
00h
XXh
XXXXh
U2C0
U2C1
U2RB
0000 1000b
0000 0010b
XXXXh
TABSR
CPSRF
ONSF
TRGSR
UDF
0000 0000b
0XXX XXXXb
0000 0000b
0000 0000b
0000 0000b
TA0
XXXXh
TA1
XXXXh
TA2
XXXXh
TA3
XXXXh
TA4
XXXXh
Page 41 of 95
R32C/116 Group
Table 4.14
4. Special Function Registers (SFRs)
SFR List (14)
Address
Register
000350h Timer B0 Register
000351h
000352h Timer B1 Register
000353h
000354h Timer B2 Register
000355h
000356h Timer A0 Mode Register
000357h Timer A1 Mode Register
000358h Timer A2 Mode Register
000359h Timer A3 Mode Register
00035Ah Timer A4 Mode Register
00035Bh Timer B0 Mode Register
00035Ch Timer B1 Mode Register
00035Dh Timer B2 Mode Register
00035Eh Timer B2 Special Mode Register
00035Fh Count Source Prescaler Register
000360h
000361h
000362h
000363h
000364h UART0 Special Mode Register 4
000365h UART0 Special Mode Register 3
000366h UART0 Special Mode Register 2
000367h UART0 Special Mode Register
000368h UART0 Transmit/Receive Mode Register
000369h UART0 Bit Rate Register
00036Ah UART0 Transmit Buffer Register
00036Bh
00036Ch UART0 Transmit/Receive Control Register 0
00036Dh UART0 Transmit/Receive Control Register 1
00036Eh UART0 Receive Buffer Register
00036Fh
000370h
000371h
000372h
000373h
000374h
000375h
000376h
000377h
000378h
000379h
00037Ah
00037Bh
00037Ch CRC Data Register
00037Dh
00037Eh CRC Input Register
00037Fh
X: Undefined
Blanks are reserved. No access is allowed.
REJ03B0253-0110
Jun 23, 2010
Rev.1.10
TB0
Symbol
Reset Value
XXXXh
TB1
XXXXh
TB2
XXXXh
TA0MR
TA1MR
TA2MR
TA3MR
TA4MR
TB0MR
TB1MR
TB2MR
TB2SC
TCSPR
0000 0000b
0000 0000b
0000 0000b
0000 0000b
0000 0000b
00XX 0000b
00XX 0000b
00XX 0000b
XXXX XXX0b
0000 0000b
U0SMR4
U0SMR3
U0SMR2
U0SMR
U0MR
U0BRG
U0TB
00h
00h
00h
00h
00h
XXh
XXXXh
U0C0
U0C1
U0RB
0000 1000b
0000 0010b
XXXXh
CRCD
XXXXh
CRCIN
XXh
Page 42 of 95
R32C/116 Group
Table 4.15
4. Special Function Registers (SFRs)
SFR List (15)
Address
Register
000380h A/D0 Register 0
000381h
000382h A/D0 Register 1
000383h
000384h A/D0 Register 2
000385h
000386h A/D0 Register 3
000387h
000388h A/D0 Register 4
000389h
00038Ah A/D0 Register 5
00038Bh
00038Ch A/D0 Register 6
00038Dh
00038Eh A/D0 Register 7
00038Fh
000390h
000391h
000392h A/D0 Control Register 4
000393h
000394h A/D0 Control Register 2
000395h A/D0 Control Register 3
000396h A/D0 Control Register 0
000397h A/D0 Control Register 1
000398h D/A Register 0
000399h
00039Ah D/A Register 1
00039Bh
00039Ch D/A Control Register
00039Dh
00039Eh
00039Fh
0003A0h
0003A1h
0003A2h
0003A3h
0003A4h
0003A5h
0003A6h
0003A7h
0003A8h
0003A9h
0003AAh
0003ABh
0003ACh
0003ADh
0003AEh
0003AFh
X: Undefined
Blanks are reserved. No access is allowed.
REJ03B0253-0110
Jun 23, 2010
Rev.1.10
AD00
Symbol
Reset Value
00XXh
AD01
00XXh
AD02
00XXh
AD03
00XXh
AD04
00XXh
AD05
00XXh
AD06
00XXh
AD07
00XXh
AD0CON4
XXXX 00XXb
AD0CON2
AD0CON3
AD0CON0
AD0CON1
DA0
X00X X000b
XXXX X000b
00h
00h
XXh
DA1
XXh
DACON
XXXX XX00b
Page 43 of 95
R32C/116 Group
Table 4.16
4. Special Function Registers (SFRs)
SFR List (16)
Address
Register
0003B0h
0003B1h
0003B2h
0003B3h
0003B4h
0003B5h
0003B6h
0003B7h
0003B8h
0003B9h
0003BAh
0003BBh
0003BCh
0003BDh
0003BEh
0003BFh
0003C0h Port P0 Register
0003C1h Port P1 Register
0003C2h Port P0 Direction Register
0003C3h Port P1 Direction Register
0003C4h Port P2 Register
0003C5h Port P3 Register
0003C6h Port P2 Direction Register
0003C7h Port P3 Direction Register
0003C8h Port P4 Register
0003C9h Port P5 Register
0003CAh Port P4 Direction Register
0003CBh Port P5 Direction Register
0003CCh Port P6 Register
0003CDh Port P7 Register
0003CEh Port P6 Direction Register
0003CFh Port P7 Direction Register
0003D0h Port P8 Register
0003D1h Port P9 Register
0003D2h Port P8 Direction Register
0003D3h Port P9 Direction Register
0003D4h Port P10 Register
0003D5h Port P11 Register
0003D6h Port P10 Direction Register
0003D7h Port P11 Direction Register
0003D8h Port P12 Register
0003D9h Port P13 Register
0003DAh Port P12 Direction Register
0003DBh Port P13 Direction Register
0003DCh Port P14 Register
0003DDh Port P15 Register
0003DEh Port P14 Direction Register
0003DFh Port P15 Direction Register
X: Undefined
Blanks are reserved. No access is allowed.
REJ03B0253-0110
Jun 23, 2010
Rev.1.10
Symbol
P0
P1
PD0
PD1
P2
P3
PD2
PD3
P4
P5
PD4
PD5
P6
P7
PD6
PD7
P8
P9
PD8
PD9
P10
P11
PD10
PD11
P12
P13
PD12
PD13
P14
P15
PD14
PD15
Reset Value
XXh
XXh
0000 0000b
0000 0000b
XXh
XXh
0000 0000b
0000 0000b
XXh
XXh
0000 0000b
0000 0000b
XXh
XXh
0000 0000b
0000 0000b
XXh
XXh
00X0 0000b
0000 0000b
XXh
XXh
0000 0000b
XXX0 0000b
XXh
XXh
0000 0000b
0000 0000b
XXh
XXh
X000 0000b
0000 0000b
Page 44 of 95
R32C/116 Group
Table 4.17
4. Special Function Registers (SFRs)
SFR List (17)
Address
Register
0003E0h
0003E1h
0003E2h
0003E3h
0003E4h
0003E5h
0003E6h
0003E7h
0003E8h
0003E9h
0003EAh
0003EBh
0003ECh
0003EDh
0003EEh
0003EFh
0003F0h Pull-up Control Register 0
0003F1h Pull-up Control Register 1
0003F2h Pull-up Control Register 2
0003F3h Pull-up Control Register 3
0003F4h Pull-up Control Register 4
0003F5h
0003F6h
0003F7h
0003F8h
0003F9h
0003FAh
0003FBh
0003FCh
0003FDh
0003FEh
0003FFh Port Control Register
X: Undefined
Blanks are reserved. No access is allowed.
REJ03B0253-0110
Jun 23, 2010
Rev.1.10
Symbol
Reset Value
PUR0
PUR1
PUR2
PUR3
PUR4
0000 0000b
XXXX X0XXb
000X XXXXb
0000 0000b
XXXX 0000b
PCR
0XXX XXX0b
Page 45 of 95
R32C/116 Group
Table 4.18
4. Special Function Registers (SFRs)
SFR List (18)
Address
Register
040000h Flash Memory Control Register 0
040001h Flash Memory Status Register 0
040002h
040003h
040004h
040005h
040006h
040007h
040008h Flash Register Protection Unlock Register 0
040009h Flash Memory Control Register 1
04000Ah Block Protect Bit Monitor Register 0
04000Bh Block Protect Bit Monitor Register 1
04000Ch
04000Dh
04000Eh
04000Fh
040010h
040011h Block Protect Bit Monitor Register 2
040012h
040013h
040014h
040015h
040016h
040017h
040018h
040019h
04001Ah
04001Bh
04001Ch
04001Dh
04001Eh
04001Fh
040020h PLL Control Register 0
040021h PLL Control Register 1
040022h
040023h
040024h
040025h
040026h
040027h
040028h
040029h
04002Ah
04002Bh
04002Ch
04002Dh
04002Eh
04002Fh
X: Undefined
Blanks are reserved. No access is allowed.
Symbol
FMR0
FMSR0
Reset Value
0X01 XX00b
1000 0000b
FPR0
FMR1
FBPM0
FBPM1
00h
0000 0010b
??X? ????b (1)
XXX? ????b (1)
FBPM2
???? ????b (1)
PLC0
PLC1
0000 0001b
0001 1111b
Note:
1. The status of protect bit of each block in flash memory is reflected.
REJ03B0253-0110
Jun 23, 2010
Rev.1.10
Page 46 of 95
R32C/116 Group
Table 4.19
4. Special Function Registers (SFRs)
SFR List (19)
Address
Register
040030h to
04003Fh
040040h
040041h
040042h
040043h
040044h Processor Mode Register 0 (1)
040045h
040046h System Clock Control Register 0
040047h System Clock Control Register 1
040048h Processor Mode Register 3
040049h
04004Ah Protect Register
04004Bh
04004Ch Protect Register 3
04004Dh Oscillator Stop Detection Register
04004Eh
04004Fh
040050h
040051h
040052h
040053h Processor Mode Register 2
040054h Chip Select Output Pin Setting Register 0
040055h Chip Select Output Pin Setting Register 1
040056h Chip Select Output Pin Setting Register 2
040057h
040058h
040059h
04005Ah Low Speed Mode Clock Control Register
04005Bh
04005Ch
04005Dh
04005Eh
04005Fh
040060h Voltage Regulator Control Register
040061h
040062h Low Voltage Detector Control Register
040063h
040064h Detection Voltage Configuration Register
040065h
040066h
040067h
040068h to
040093h
X: Undefined
Blanks are reserved. No access is allowed.
Symbol
Reset Value
PM0
1000 0000b
(CNVSS pin = Low)
0000 0011b
(CNVSS pin = High)
CM0
CM1
PM3
0000 1000b
0010 0000b
00h
PRCR
XXXX X000b
PRCR3
CM2
0000 0000b
00h
PM2
CSOP0
CSOP1
CSOP2
00h
1000 XXXXb
01X0 XXXXb
XXXX 0000b
CM3
XXXX XX00b
VRCR
0000 0000b
LVDC
0000 XX00b
DVCR
0000 XXXXb
Note:
1. The value in the PM0 register remains unchanged even after a software reset or watchdog timer reset.
REJ03B0253-0110
Jun 23, 2010
Rev.1.10
Page 47 of 95
R32C/116 Group
Table 4.20
4. Special Function Registers (SFRs)
SFR List (20)
Address
Register
040094h
040095h
040096h
040097h Three-phase Output Buffer Control Register
040098h Input Function Select Register 0
040099h
04009Ah Input Function Select Register 2
04009Bh Input Function Select Register 3
04009Ch
04009Dh
04009Eh
04009Fh
0400A0h Port P0_0 Function Select Register
0400A1h Port P1_0 Function Select Register
0400A2h Port P0_1 Function Select Register
0400A3h Port P1_1 Function Select Register
0400A4h Port P0_2 Function Select Register
0400A5h Port P1_2 Function Select Register
0400A6h Port P0_3 Function Select Register
0400A7h Port P1_3 Function Select Register
0400A8h Port P0_4 Function Select Register
0400A9h Port P1_4 Function Select Register
0400AAh Port P0_5 Function Select Register
0400ABh Port P1_5 Function Select Register
0400ACh Port P0_6 Function Select Register
0400ADh Port P1_6 Function Select Register
0400AEh Port P0_7 Function Select Register
0400AFh Port P1_7 Function Select Register
0400B0h Port P2_0 Function Select Register
0400B1h Port P3_0 Function Select Register
0400B2h Port P2_1 Function Select Register
0400B3h Port P3_1 Function Select Register
0400B4h Port P2_2 Function Select Register
0400B5h Port P3_2 Function Select Register
0400B6h Port P2_3 Function Select Register
0400B7h Port P3_3 Function Select Register
0400B8h Port P2_4 Function Select Register
0400B9h Port P3_4 Function Select Register
0400BAh Port P2_5 Function Select Register
0400BBh Port P3_5 Function Select Register
0400BCh Port P2_6 Function Select Register
0400BDh Port P3_6 Function Select Register
0400BEh Port P2_7 Function Select Register
0400BFh Port P3_7 Function Select Register
X: Undefined
Blanks are reserved. No access is allowed.
REJ03B0253-0110
Jun 23, 2010
Rev.1.10
Symbol
Reset Value
IOBC
IFS0
0XXX XXXXb
X000 0000b
IFS2
IFS3
0000 00X0b
XXXX XX00b
P0_0S
P1_0S
P0_1S
P1_1S
P0_2S
P1_2S
P0_3S
P1_3S
P0_4S
P1_4S
P0_5S
P1_5S
P0_6S
P1_6S
P0_7S
P1_7S
P2_0S
P3_0S
P2_1S
P3_1S
P2_2S
P3_2S
P2_3S
P3_3S
P2_4S
P3_4S
P2_5S
P3_5S
P2_6S
P3_6S
P2_7S
P3_7S
0XXX X000b
XXXX X000b
0XXX X000b
XXXX X000b
0XXX X000b
XXXX X000b
0XXX X000b
XXXX X000b
0XXX X000b
XXXX X000b
0XXX X000b
XXXX X000b
0XXX X000b
XXXX X000b
0XXX X000b
XXXX X000b
0XXX X000b
XXXX X000b
0XXX X000b
XXXX X000b
0XXX X000b
XXXX X000b
0XXX X000b
XXXX X000b
0XXX X000b
XXXX X000b
0XXX X000b
XXXX X000b
0XXX X000b
XXXX X000b
0XXX X000b
XXXX X000b
Page 48 of 95
R32C/116 Group
Table 4.21
4. Special Function Registers (SFRs)
SFR List (21)
Address
Register
0400C0h Port P4_0 Function Select Register
0400C1h Port P5_0 Function Select Register
0400C2h Port P4_1 Function Select Register
0400C3h Port P5_1 Function Select Register
0400C4h Port P4_2 Function Select Register
0400C5h Port P5_2 Function Select Register
0400C6h Port P4_3 Function Select Register
0400C7h Port P5_3 Function Select Register
0400C8h Port P4_4 Function Select Register
0400C9h Port P5_4 Function Select Register
0400CAh Port P4_5 Function Select Register
0400CBh Port P5_5 Function Select Register
0400CCh Port P4_6 Function Select Register
0400CDh Port P5_6 Function Select Register
0400CEh Port P4_7 Function Select Register
0400CFh Port P5_7 Function Select Register
0400D0h Port P6_0 Function Select Register
0400D1h Port P7_0 Function Select Register
0400D2h Port P6_1 Function Select Register
0400D3h Port P7_1 Function Select Register
0400D4h Port P6_2 Function Select Register
0400D5h Port P7_2 Function Select Register
0400D6h Port P6_3 Function Select Register
0400D7h Port P7_3 Function Select Register
0400D8h Port P6_4 Function Select Register
0400D9h Port P7_4 Function Select Register
0400DAh Port P6_5 Function Select Register
0400DBh Port P7_5 Function Select Register
0400DCh Port P6_6 Function Select Register
0400DDh Port P7_6 Function Select Register
0400DEh Port P6_7 Function Select Register
0400DFh Port P7_7 Function Select Register
0400E0h Port P8_0 Function Select Register
0400E1h Port P9_0 Function Select Register
0400E2h Port P8_1 Function Select Register
0400E3h Port P9_1 Function Select Register
0400E4h Port P8_2 Function Select Register
0400E5h Port P9_2 Function Select Register
0400E6h Port P8_3 Function Select Register
0400E7h Port P9_3 Function Select Register
0400E8h Port P8_4 Function Select Register
0400E9h Port P9_4 Function Select Register
0400EAh
0400EBh Port P9_5 Function Select Register
0400ECh Port P8_6 Function Select Register
0400EDh Port P9_6 Function Select Register
0400EEh Port P8_7 Function Select Register
0400EFh Port P9_7 Function Select Register
X: Undefined
Blanks are reserved. No access is allowed.
REJ03B0253-0110
Jun 23, 2010
Rev.1.10
Symbol
P4_0S
P5_0S
P4_1S
P5_1S
P4_2S
P5_2S
P4_3S
P5_3S
P4_4S
P5_4S
P4_5S
P5_5S
P4_6S
P5_6S
P4_7S
P5_7S
P6_0S
P7_0S
P6_1S
P7_1S
P6_2S
P7_2S
P6_3S
P7_3S
P6_4S
P7_4S
P6_5S
P7_5S
P6_6S
P7_6S
P6_7S
P7_7S
P8_0S
P9_0S
P8_1S
P9_1S
P8_2S
P9_2S
P8_3S
P9_3S
P8_4S
P9_4S
Reset Value
X0XX X000b
XXXX X000b
X0XX X000b
XXXX X000b
X0XX X000b
XXXX X000b
X0XX X000b
XXXX X000b
X0XX X000b
X0XX X000b
X0XX X000b
X0XX X000b
X0XX X000b
X0XX X000b
X0XX X000b
X0XX X000b
X0XX X000b
X0XX X000b
X0XX X000b
X0XX X000b
X0XX X000b
X0XX X000b
X0XX X000b
X0XX X000b
X0XX X000b
X0XX X000b
X0XX X000b
X0XX X000b
X0XX X000b
X0XX X000b
X0XX X000b
X0XX X000b
X0XX X000b
X0XX X000b
X0XX X000b
X0XX X000b
X0XX X000b
X0XX X000b
X0XX X000b
00XX X000b
XXXX X000b
00XX X000b
P9_5S
P8_6S
P9_6S
P8_7S
P9_7S
00XX X000b
XXXX X000b
00XX X000b
XXXX X000b
X0XX X000b
Page 49 of 95
R32C/116 Group
Table 4.22
4. Special Function Registers (SFRs)
SFR List (22)
Address
Register
0400F0h Port P10_0 Function Select Register
0400F1h Port P11_0 Function Select Register
0400F2h Port P10_1 Function Select Register
0400F3h Port P11_1 Function Select Register
0400F4h Port P10_2 Function Select Register
0400F5h Port P11_2 Function Select Register
0400F6h Port P10_3 Function Select Register
0400F7h Port P11_3 Function Select Register
0400F8h Port P10_4 Function Select Register
0400F9h Port P11_4 Function Select Register
0400FAh Port P10_5 Function Select Register
0400FBh
0400FCh Port P10_6 Function Select Register
0400FDh
0400FEh Port P10_7 Function Select Register
0400FFh
040100h Port P12_0 Function Select Register
040101h Port P13_0 Function Select Register
040102h Port P12_1 Function Select Register
040103h Port P13_1 Function Select Register
040104h Port P12_2 Function Select Register
040105h Port P13_2 Function Select Register
040106h Port P12_3 Function Select Register
040107h Port P13_3 Function Select Register
040108h Port P12_4 Function Select Register
040109h Port P13_4 Function Select Register
04010Ah Port P12_5 Function Select Register
04010Bh Port P13_5 Function Select Register
04010Ch Port P12_6 Function Select Register
04010Dh Port P13_6 Function Select Register
04010Eh Port P12_7 Function Select Register
04010Fh Port P13_7 Function Select Register
040110h
040111h Port P15_0 Function Select Register
040112h
040113h Port P15_1 Function Select Register
040114h
040115h Port P15_2 Function Select Register
040116h Port P14_3 Function Select Register
040117h Port P15_3 Function Select Register
040118h Port P14_4 Function Select Register
040119h Port P15_4 Function Select Register
04011Ah Port P14_5 Function Select Register
04011Bh Port P15_5 Function Select Register
04011Ch Port P14_6 Function Select Register
04011Dh Port P15_6 Function Select Register
04011Eh
04011Fh Port P15_7 Function Select Register
X: Undefined
Blanks are reserved. No access is allowed.
REJ03B0253-0110
Jun 23, 2010
Rev.1.10
Symbol
P10_0S
P11_0S
P10_1S
P11_1S
P10_2S
P11_2S
P10_3S
P11_3S
P10_4S
P11_4S
P10_5S
Reset Value
0XXX X000b
X0XX X000b
0XXX X000b
X0XX X000b
0XXX X000b
X0XX X000b
0XXX X000b
X0XX X000b
0XXX X000b
XXXX X000b
0XXX X000b
P10_6S
0XXX X000b
P10_7S
0XXX X000b
P12_0S
P13_0S
P12_1S
P13_1S
P12_2S
P13_2S
P12_3S
P13_3S
P12_4S
P13_4S
P12_5S
P13_5S
P12_6S
P13_6S
P12_7S
P13_7S
X0XX X000b
XXXX X000b
X0XX X000b
XXXX X000b
X0XX X000b
XXXX X000b
X0XX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
P15_0S
00XX X000b
P15_1S
00XX X000b
P15_2S
P14_3S
P15_3S
P14_4S
P15_4S
P14_5S
P15_5S
P14_6S
P15_6S
00XX X000b
XXXX X000b
00XX X000b
XXXX X000b
00XX X000b
XXXX X000b
00XX X000b
XXXX X000b
00XX X000b
P15_7S
00XX X000b
Page 50 of 95
R32C/116 Group
Table 4.23
4. Special Function Registers (SFRs)
SFR List (23)
Address
Register
040120h to
04403Fh
044040h
044041h
044042h
044043h
044044h
044045h
044046h
044047h
044048h
044049h
04404Ah
04404Bh
04404Ch
04404Dh
04404Eh Watchdog Timer Start Register
04404Fh Watchdog Timer Control Register
044050h
044051h
044052h
044053h
044054h
044055h
044056h
044057h
044058h
044059h
04405Ah
04405Bh
04405Ch
04405Dh
04405Eh
04405Fh Protect Register 2
X: Undefined
Blanks are reserved. No access is allowed.
REJ03B0253-0110
Jun 23, 2010
Rev.1.10
Symbol
Reset Value
WDTS
WDC
XXXX XXXXb
000X XXXXb
PRCR2
0XXX XXXXb
Page 51 of 95
R32C/116 Group
Table 4.24
4. Special Function Registers (SFRs)
SFR List (24)
Address
Register
044060h
044061h
044062h
044063h
044064h
044065h
044066h
044067h
044068h
044069h
04406Ah
04406Bh
04406Ch
04406Dh External Interrupt Request Source Select Register 1
04406Eh
04406Fh External Interrupt Request Source Select Register 0
044070h DMA0 Request Source Select Register 2
044071h DMA1 Request Source Select Register 2
044072h DMA2 Request Source Select Register 2
044073h DMA3 Request Source Select Register 2
044074h
044075h
044076h
044077h
044078h DMA0 Request Source Select Register
044079h DMA1 Request Source Select Register
04407Ah DMA2 Request Source Select Register
04407Bh DMA3 Request Source Select Register
04407Ch
04407Dh Wake-up IPL Setting Register 2
04407Eh
04407Fh Wake-up IPL Setting Register 1
044080h
044081h
044082h
044083h
044084h
044085h
044086h
044087h
044088h
044089h
04408Ah
04408Bh
04408Ch
04408Dh
04408Eh
04408Fh
X: Undefined
Blanks are reserved. No access is allowed.
REJ03B0253-0110
Jun 23, 2010
Rev.1.10
Symbol
Reset Value
IFSR1
X0XX X000b
IFSR0
DM0SL2
DM1SL2
DM2SL2
DM3SL2
0000 0000b
XX00 0000b
XX00 0000b
XX00 0000b
XX00 0000b
DM0SL
DM1SL
DM2SL
DM3SL
XXX0 0000b
XXX0 0000b
XXX0 0000b
XXX0 0000b
RIPL2
XX0X 0000b
RIPL1
XX0X 0000b
Page 52 of 95
R32C/116 Group
Table 4.25
Address
044090h to
0443FFh
044400h
044401h
044402h
044403h
044404h
044405h
4. Special Function Registers (SFRs)
SFR List (25)
Register
I2C Bus Transmit/Receive Shift Register
I2C Bus Slave Address Register
I2C Bus Control Register 0
I2C Bus Clock Control Register
I2C Bus START Condition/STOP Condition Control
Register
044406h I2C Bus Control Register 1
044407h I2C Bus Control Register 2
044408h I2C Bus Status Register
044409h
04440Ah
04440Bh
04440Ch
04440Dh
04440Eh
04440Fh
044410h I2C Bus Mode Register
044411h
044412h
044413h
044414h
044415h
044416h
044417h
044418h
044419h
04441Ah
04441Bh
04441Ch
04441Dh
04441Eh
04441Fh
044420h to
04FFFFh
X: Undefined
Blanks are reserved. No access is allowed.
REJ03B0253-0110
Jun 23, 2010
Rev.1.10
Symbol
Reset Value
I2CTRSR
XXh
I2CSAR
I2CCR0
I2CCCR
I2CSSCR
00h
0000 0000b
0000 0000b
0000 0000b
I2CCR1
I2CCR2
I2CSR
0000 0000b
0000 0000b
0000 0000b
I2CMR
0000 0000b
Page 53 of 95
R32C/116 Group
5.
5. Electrical Characteristics
Electrical Characteristics
Table 5.1
Absolute Maximum Ratings (1)
Symbol
Characteristic
Condition
Value
Unit
VCC
Supply voltage
VCC = AVCC
-0.3 to 6.0
V
AVCC
Analog supply voltage
VCC = AVCC
-0.3 to 6.0
V
VI
Input voltage
-0.3 to VCC + 0.3
V
-0.3 to 6.0
V
-0.3 to VCC + 0.3
V
500
mW
Operating temperature range
-40 to 85
°C
Storage temperature range
-65 to 150
°C
XIN, RESET, CNVSS, NSD, VREF,
P0_0 to P0_7, P1_0 to P1_7,
P2_0 to P2_7, P3_0 to P3_7,
P5_0 to P5_3, P8_4 to P8_7,
P9_0 to P9_7, P10_0 to P10_7,
P11_0 to P11_4, P12_0 to P12_7,
P13_0 to P13_7, P14_1,
P14_3 to P14_6, P15_0 to P15_7 (2)
P4_0 to P4_7, P5_4 to P5_7,
P6_0 to P6_7, P7_0 to P7_7,
P8_0 to P8_3
VO
Output
voltage
Power consumption
Pd
—
Tstg
XOUT, P0_0 to P0_7, P1_0 to P1_7,
P2_0 to P2_7, P3_0 to P3_7,
P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0 to P7_7,
P8_0 to P8_4, P8_6, P8_7,
P9_0 to P9_7, P10_0 to P10_7,
P11_0 to P11_4, P12_0 to P12_7,
P13_0 to P13_7, P14_3 to P14_6,
P15_0 to P15_7 (2)
Ta = 25°C
Notes:
1. Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to
the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
2. Ports P9_0, P9_2, and P11 to P15 are available in the 144-pin package only. Port P9_1 is designated
as input pin in the 100-pin package.
REJ03B0253-0110
Jun 23, 2010
Rev.1.10
Page 54 of 95
R32C/116 Group
Table 5.2
5. Electrical Characteristics
Operating Conditions (1/5) (1)
Symbol
Characteristic
Value
Min.
Typ.
Max.
3.0
5.0
5.5
Unit
VCC
Digital supply voltage
AVCC
Analog supply voltage
VREF
Reference voltage
VSS
Digital ground voltage
0
V
AVSS
Analog ground voltage
0
V
dVCC/dt VCC ramp up rate (VCC < 2.0 V)
VIH
High level
input
voltage
VCC
V
VCC
3.0
V
0.05
V
V/ms
XIN, RESET, CNVSS, NSD, P2_0 to P2_7,
P3_0 to P3_7, P5_0 to P5_3, P8_4 to P8_7 (2),
0.8 × VCC
P9_0 to P9_7, P10_0 to P10_7,
P11_0 to P11_4, P14_1, P14_3 to P14_6,
P15_0 to P15_7 (3)
VCC
V
P4_0 to P4_7, P5_4 to P5_7, P6_0 to P6_7,
P7_0 to P7_7, P8_0 to P8_3
0.8 × VCC
6.0
V
0.8 × VCC
VCC
V
0.5 × VCC
VCC
V
0
0.2 × VCC
V
0
0.2 × VCC
V
0
0.16 × VCC
V
-20
85
°C
-40
85
°C
-40
85
°C
P0_0 to P0_7,
in single-chip mode
P1_0 to P1_7,
P12_0 to P12_7, in memory expansion mode
P13_0 to P13_7 or microprocessor mode
(3)
VIL
Low level
input
voltage
XIN, RESET, CNVSS, NSD, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7 (2),
P9_0 to P9_7, P10_0 to P10_7,
P11_0 to P11_4, P14_1, P14_3 to P14_6,
P15_0 to P15_7 (3)
in single-chip mode
P0_0 to P0_7,
P1_0 to P1_7,
in memory expansion mode
P12_0 to P12_7,
or microprocessor mode
P13_0 to P13_7
(3)
Topr
Operating
Version N
temperature Version D
range
Version P
Notes:
1. The device is operationally guaranteed under these operating conditions.
2. VIH and VIL for P8_7 are specified for P8_7 as a programmable port. These values are not applicable
to P8_7 as XCIN.
3. Ports P9_0, P9_2, and P11 to P15 are available in the 144-pin package only. Port P9_1 is designated
as input pin in the 100-pin package.
REJ03B0253-0110
Jun 23, 2010
Rev.1.10
Page 55 of 95
R32C/116 Group
Table 5.3
5. Electrical Characteristics
Operating Conditions (2/5)
(VCC = 3.0 to 5.5 V, VSS = 0 V, and Ta = Topr, unless otherwise noted) (1)
Symbol
CVDC
Value (2)
Characteristic
Decoupling capacitance for voltage
regulator
Min. Typ. Max.
Inter-pin voltage: 1.5 V
2.4
10.0
Unit
µF
Notes:
1. The device is operationally guaranteed under these operating conditions.
2. This value should be satisfied with due consideration of every condition as follows: operating
temperature, DC bias, aging, etc.
REJ03B0253-0110
Jun 23, 2010
Rev.1.10
Page 56 of 95
R32C/116 Group
Table 5.4
5. Electrical Characteristics
Operating Conditions (3/5)
(VCC = 3.0 to 5.5 V, VSS = 0 V, and Ta = Topr, unless otherwise noted) (1)
Symbol
Characteristic
Value
Min.
Typ.
Max.
Unit
IOH(peak) High level
peak
output
current (2)
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4, P8_6,
P8_7, P9_0 to P9_7, P10_0 to P10_7,
P11_0 to P11_4, P12_0 to P12_7, P13_0 to P13_7,
P14_3 to P14_6, P15_0 to P15_7 (3)
-10.0
mA
IOH(avg)
High level
average
output
current (4)
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4, P8_6,
P8_7, P9_0 to P9_7, P10_0 to P10_7,
P11_0 to P11_4, P12_0 to P12_7, P13_0 to P13_7,
P14_3 to P14_6, P15_0 to P15_7 (3)
-5.0
mA
IOL(peak) Low level
peak
output
current (2)
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4, P8_6,
P8_7, P9_0 to P9_7, P10_0 to P10_7,
P11_0 to P11_4, P12_0 to P12_7, P13_0 to P13_7,
P14_3 to P14_6, P15_0 to P15_7 (3)
10.0
mA
IOL(avg)
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4, P8_6,
P8_7, P9_0 to P9_7, P10_0 to P10_7,
P11_0 to P11_4, P12_0 to P12_7, P13_0 to P13_7,
P14_3 to P14_6, P15_0 to P15_7 (3)
5.0
mA
Low level
average
output
current (4)
Notes:
1. The device is operationally guaranteed under these operating conditions.
2. The following conditions should be satisfied:
• The sum of IOL(peak) of ports P0, P1, P2, P8_6, P8_7, P9, P10, P11, P14, and P15 is 80 mA or less.
• The sum of IOL(peak) of ports P3, P4, P5, P6, P7, P8_0 to P8_4, P12, and P13 is 80 mA or less.
• The sum of IOH(peak) of ports P0, P1, P2, and P11 is -40 mA or less.
• The sum of IOH(peak) of ports P8_6, P8_7, P9, P10, P14, and P15 is -40 mA or less.
• The sum of IOH(peak) of ports P3, P4, P5, P12, and P13 is -40 mA or less.
• The sum of IOH(peak) of ports P6, P7, and P8_0 to P8_4 is -40 mA or less.
3. Ports P9_0, P9_2, and P11 to P15 are available in the 144-pin package only. Port P9_1 is designated
as input pin in the 100-pin package.
4. Average value within 100 ms.
REJ03B0253-0110
Jun 23, 2010
Rev.1.10
Page 57 of 95
R32C/116 Group
Table 5.5
5. Electrical Characteristics
Operating Conditions (4/5)
(VCC = 3.0 to 5.5 V, VSS = 0 V, and Ta = Topr, unless otherwise noted) (1)
Symbol
Value
Characteristic
Min.
Typ.
Max.
Unit
f(XIN)
Main clock oscillator frequency
4
16
MHz
f(XRef)
Reference clock frequency
2
4
MHz
f(PLL)
PLL clock oscillator frequency
96
128
MHz
f(Base)
Base clock frequency
High speed
64
MHz
Normal speed
50
MHz
tc(Base)
Base clock cycle time
High speed
Normal speed
f(CPU)
CPU operating frequency
CPU clock cycle time
tc(CPU)
ns
20
ns
High speed
64
MHz
Normal speed
50
MHz
High speed
Normal speed
f(BCLK)
15.625
15.625
ns
20
ns
Peripheral bus clock operating frequency High speed
Normal speed
tc(BCLK)
Peripheral bus clock cycle time
High speed
Normal speed
f(PER)
Peripheral clock source frequency
f(XCIN)
Sub clock oscillator frequency
32
MHz
25
MHz
31.25
ns
40
ns
32.768
32
MHz
62.5
kHz
Note:
1. The device is operationally guaranteed under these operating conditions.
t c(Base)
Base clock
(Internal signal)
t c(CPU)
CPU clock
(Internal signal)
t c(BCLK)
Peripheral bus clock
(Internal signal)
Figure 5.1
Clock Cycle Time
REJ03B0253-0110
Jun 23, 2010
Rev.1.10
Page 58 of 95
R32C/116 Group
Table 5.6
5. Electrical Characteristics
Operating Conditions (5/5)
(VCC = 3.0 to 5.5 V, VSS = 0 V, and Ta = Topr, unless otherwise noted) (1)
Symbol
Vr(VCC)
Allowable ripple voltage
dVr(VCC)/dt Ripple voltage gradient
fr(VCC)
Value
Characteristic
Min.
Typ.
Max.
Unit
VCC = 5.0 V
0.5
Vp-p
VCC = 3.0 V
0.3
Vp-p
VCC = 5.0 V
±0.3
V/ms
VCC = 3.0 V
±0.3
V/ms
10
kHz
Allowable ripple frequency
Note:
1. The device is operationally guaranteed under these operating conditions.
1 / f r(VCC)
VCC
Figure 5.2
V r(VCC)
Ripple Waveform
REJ03B0253-0110
Jun 23, 2010
Rev.1.10
Page 59 of 95
R32C/116 Group
Table 5.7
5. Electrical Characteristics
RAM Electrical Characteristics
(VCC = 3.0 to 5.5 V, VSS = 0 V, and Ta = Topr, unless otherwise noted)
Symbol
VRDR
Table 5.8
Characteristic
RAM data retention voltage
—
—
—
—
in stop mode
Value
Min.
Typ.
Max.
2.0
Unit
V
Flash Memory Electrical Characteristics
(VCC = 3.0 to 5.5 V, VSS = 0 V, and Ta = Topr, unless otherwise noted)
Symbol
—
Measurement
condition
Value
Characteristic
Min.
Programming and erasure endurance of flash Program area
memory (1)
Data area
4-word program time
Lock bit-program time
Block erasure time
Data retention
(2)
Typ.
Max.
Unit
1000
times
10000
times
Program area
150
900
µs
Data area
300
1700
µs
Program area
70
500
µs
Data area
140
1000
µs
4 Kbyte block
0.12
3.0
s
32 Kbyte block
0.17
3.0
s
64 Kbyte block
0.20
3.0
s
Ta = 55°C
(3)
10
years
Notes:
1. Program/erase definition
This value represents the number of erasures per block.
If the flash memory is programmed/erased n times, each block can be erased n times.
i.e. If 4-word write is performed in 512 different addresses in the block A of 4 Kbyte and then the
block is erased, it is considered the programming/erasure is performed just once.
However a write in the same address more than once for one erasure is disabled (overwrite
disabled).
2. The data retention time includes the periods when the supply voltage is not applied and no clock is
provided.
3. Please contact a Renesas Electronics sales office regarding data retention time other than the
above.
REJ03B0253-0110
Jun 23, 2010
Rev.1.10
Page 60 of 95
R32C/116 Group
Table 5.9
5. Electrical Characteristics
Power Supply Circuit Timing Characteristics
(VCC = 3.0 to 5.5 V, VSS = 0 V, and Ta = Topr, unless otherwise noted)
Symbol
Measurement
condition
Characteristic
Value
Min. Typ. Max.
Internal power supply start-up stabilization
time after the main power supply is turned on
td(P-R)
t d(P-R)
Internal power supply start-up
stabilization time after the main
power supply is turned on
V CC
2
Unit
ms
Recommended
operating voltage
t d(P-R)
Supply voltage for
internal logic
PLL oscillatoroutput waveform
Figure 5.3
Power Supply Circuit Timing
Table 5.10
Electrical Characteristics of Voltage Regulator for Internal Logic
(VCC = 3.0 to 5.5 V, VSS = 0 V, and Ta = Topr, unless otherwise noted)
Symbol
Measurement
condition
Characteristics
Value
Min.
Typ.
Output voltage
VVDC1
Table 5.11
Max.
1.5
Unit
V
Electrical Characteristics of Low Voltage Detector
(VCC = 4.2 to 5.5 V, VSS = 0 V, and Ta = Topr, unless otherwise noted)
Symbol
ΔVdet
Characteristics
Measurement
condition
Value
Min.
Typ.
Detected voltage error
±0.3
Vdet(R)-Vdet(F) Hysteresis width
—
td(E-A)
REJ03B0253-0110
Jun 23, 2010
Self-consuming current
0
VCC = 5.0 V, low voltage
detector enabled
Operation start time of low voltage detector
Rev.1.10
Max.
Unit
V
V
4
µA
150
µs
Page 61 of 95
R32C/116 Group
Table 5.12
5. Electrical Characteristics
Electrical Characteristics of Oscillator
(VCC = 3.0 to 5.5 V, VSS = 0 V, and Ta = Topr, unless otherwise noted)
Symbol
Measurement
condition
Characteristics
fSO(PLL)
PLL clock self-oscillation frequency
tLOCK(PLL)
PLL lock time (1)
tjitter(p-p)
PLL jitter period (p-p)
f(OCO)
On-chip oscillator frequency
Value
Unit
Min.
Typ.
Max.
35
50
65
MHz
1
ms
2.0
ns
250
kHz
62.5
125
Note:
1. This value is applicable only when the main clock oscillation is stable.
Table 5.13
Electrical Characteristics of Clock Circuitry
(VCC = 3.0 to 5.5 V, VSS = 0 V, and Ta = Topr, unless otherwise noted)
Symbol
Characteristics
Measurement
condition
Value
Min.
Typ.
Max.
Unit
trec(WAIT)
Recovery time from wait mode to low power mode
225
µs
trec(STOP)
Recovery time from stop mode (1)
225
µs
Note:
1. This recovery time does not include the period until the main clock oscillator is stabilized. The CPU
starts operating before the oscillator is stabilized.
t rec(WAIT)
Recovery time from wait mode
to low power mode
Interrupt for exiting
wait mode
Sub clock oscillator
output
On-chip oscillator
output
CPU clock
t rec(WAIT)
t rec(STOP)
Recovery time from stop mode
Interrupt for exiting
stop mode
Main clock oscillator
output
On-chip oscillator
output
CPU clock
t rec(STOP)
Figure 5.4
Clock Circuit Timing
REJ03B0253-0110
Jun 23, 2010
Rev.1.10
Page 62 of 95
R32C/116 Group
5. Electrical Characteristics
Timing Requirements (VCC = 3.0 to 5.5 V, VSS = 0 V, and Ta = Topr, unless otherwise noted)
Table 5.14
Flash Memory CPU Rewrite Mode Timing
Symbol
Value
Characteristics
Min.
Max.
Unit
tcR
Read cycle time
200
ns
tsu(S-R)
Chip-select setup time for read
200
ns
th(R-S)
Chip-select hold time after read
0
ns
tsu(A-R)
Address setup time for read
200
ns
th(R-A)
Address hold time after read
0
ns
tw(R)
Read pulse width
100
ns
tcW
Write cycle time
200
ns
tsu(S-W)
Chip-select setup time for write
0
ns
th(W-S)
Chip-select hold time after write
30
ns
tsu(A-W)
Address setup time for write
0
ns
th(W-A)
Address hold time after write
30
ns
tw(W)
Write pulse width
50
ns
Read cycle
t cR
t su(S-R)
t h(R-S)
t su(A-R)
t h(R-A)
Chip select
Address
t w(R)
RD
Write cycle
t cW
t su(S-W)
t h(W-S)
t su(A-W)
t h(W-A)
Chip select
Address
t w(W)
WR
Figure 5.5
Flash Memory CPU Rewrite Mode Timing
REJ03B0253-0110
Jun 23, 2010
Rev.1.10
Page 63 of 95
R32C/116 Group
5. Electrical Characteristics
VCC = 5 V
Table 5.15
Electrical Characteristics (1/3)
(VCC = 4.2 to 5.5 V, VSS = 0 V, Ta = Topr, and f(CPU) = 64 MHz, unless otherwise noted)
VOH
Min.
IOH = -5 mA
VCC - 2.0
VCC
V
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4,
IOH = -200 µA VCC - 0.3
P8_6, P8_7, P9_0 to P9_7,
P10_0 to P10_7, P11_0 to P11_4,
P12_0 to P12_7, P13_0 to P13_7,
P14_3 to P14_6, P15_0 to P15_7 (1)
VCC
V
VOL
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4,
P8_6, P8_7, P9_0 to P9_7,
P10_0 to P10_7, P11_0 to P11_4,
P12_0 to P12_7, P13_0 to P13_7,
P14_3 to P14_6, P15_0 to P15_7 (1)
IOL = 5 mA
2.0
V
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4,
P8_6, P8_7, P9_0 to P9_7,
P10_0 to P10_7, P11_0 to P11_4,
P12_0 to P12_7, P13_0 to P13_7,
P14_3 to P14_6, P15_0 to P15_7 (1)
IOL = 200 µA
0.45
V
Characteristic
High
level
output
voltage
Low
level
output
voltage
Value
Measurement
condition
Symbol
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4,
P8_6, P8_7, P9_0 to P9_7,
P10_0 to P10_7, P11_0 to P11_4,
P12_0 to P12_7, P13_0 to P13_7,
P14_3 to P14_6, P15_0 to P15_7 (1)
Typ. Max.
Unit
Note:
1. Ports P9_0, P9_2, and P11 to P15 are available in the 144-pin package only. Port P9_1 is designated
as input pin in the 100-pin package.
REJ03B0253-0110
Jun 23, 2010
Rev.1.10
Page 64 of 95
R32C/116 Group
5. Electrical Characteristics
VCC = 5 V
Table 5.16
Electrical Characteristics (2/3)
(VCC = 4.2 to 5.5 V, VSS = 0 V, Ta = Topr, and f(CPU) = 64 MHz, unless otherwise noted)
Symbol
Characteristic
Value
Measurement
Unit
condition
Min. Typ. Max.
VT+ - VT- Hysteresis HOLD, RDY, NMI, INT0 to INT8, KI0 to KI3,
TA0IN to TA4IN, TA0OUT to TA4OUT,
TB0IN to TB5IN, CTS0 to CTS8,
CLK0 to CLK8, RXD0 to RXD8,
SCL0 to SCL6, SDA0 to SDA6, SS0 to SS6,
SRXD0 to SRXD6, ADTRG, IIO0_0 to IIO0_7,
IIO1_0 to IIO1_7, UD0A, UD0B, UD1A,
UD1B, ISCLK2, ISRXD2, IEIN (1)
RESET
IIH
IIL
0.2
1.0
V
0.2
1.8
V
High level XIN, RESET, CNVSS, NSD,
input
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
current
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7,
P9_0 to P9_7, P10_0 to P10_7,
P11_0 to P11_4, P12_0 to P12_7,
P13_0 to P13_7, P14_1, P14_3 to P14_6,
P15_0 to P15_7 (2)
VI = 5 V
5.0
µA
XIN, RESET, CNVSS, NSD,
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7,
P9_0 to P9_7, P10_0 to P10_7,
P11_0 to P11_4, P12_0 to P12_7,
P13_0 to P13_7, P14_1, P14_3 to P14_6,
P15_0 to P15_7 (2)
VI = 0 V
-5.0
µA
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P5_0 to P5_3, P8_4, P8_6,
P8_7, P9_0 to P9_7, P10_0 to P10_7,
P11_0 to P11_4, P12_0 to P12_7,
P13_0 to P13_7, P14_1, P14_3 to P14_6,
P15_0 to P15_7 (2)
VI = 0 V
170
kΩ
Low level
input
current
RPULLUP Pull-up
resistor
30
50
RfXIN
Feedback XIN
resistor
1.5
MΩ
RfXCIN
Feedback XCIN
resistor
15
MΩ
Notes:
1. Pins INT6 to INT8 are available in the 144-pin package only.
2. Ports P9_0, P9_2, and P11 to P15 are available in the 144-pin package only. Port P9_1 is designated
as input pin in the 100-pin package.
REJ03B0253-0110
Jun 23, 2010
Rev.1.10
Page 65 of 95
R32C/116 Group
5. Electrical Characteristics
VCC = 5 V
Table 5.17
Symbol
ICC
Electrical Characteristics (3/3)
(VCC = 4.2 to 5.5 V, VSS = 0 V, and Ta = Topr, unless otherwise noted)
Characterist
ic
Measurement condition
Power supply In single-chip mode,
current
output pins are left open
and others are
connected to VSS
XIN-XOUT
Drive power: low
XCIN-XCOUT
Drive power: low
REJ03B0253-0110
Jun 23, 2010
Rev.1.10
f(CPU) = 64 MHz, f(BCLK) = 32 MHz,
f(XIN) = 8 MHz,
Active: XIN, PLL,
Stopped: XCIN, OCO
f(CPU) = 50 MHz, f(BCLK) = 25 MHz,
f(XIN) = 8 MHz,
Active: XIN, PLL,
Stopped: XCIN, OCO
f(CPU) = fSO(PLL)/24 MHz,
Active: PLL (self-oscillation),
Stopped: XIN, XCIN, OCO
f(CPU) = f(BCLK) = f(XIN)/256 MHz,
f(XIN) = 8 MHz,
Active: XIN,
Stopped: PLL, XCIN, OCO
f(CPU) = f(BCLK) = 32.768 kHz,
Active: XCIN,
Stopped: XIN, PLL, OCO,
Main regulator: shutdown
f(CPU) = f(BCLK) = f(OCO)/4 kHz,
Active: OCO,
Stopped: XIN, PLL, XCIN,
Main regulator: shutdown
f(CPU) = f(BCLK) = f(XIN)/256 MHz,
f(XIN) = 8 MHz,
Active: XIN,
Stopped: PLL, XCIN, OCO,
Ta = 25°C, Wait mode
Value
Unit
Min. Typ. Max.
45
60
mA
35
50
mA
12
mA
1.2
mA
220
µA
230
µA
960
1600
µA
f(CPU) = f(BCLK) = 32.768 kHz,
Active: XCIN,
Stopped: XIN, PLL, OCO,
Main regulator: shutdown,
Ta = 25°C, Wait mode
8
140
µA
f(CPU) = f(BCLK) = f(OCO)/4 kHz,
Active: OCO,
Stopped: XIN, PLL, XCIN,
Main regulator: shutdown,
Ta = 25°C, Wait mode
10
150
µA
Stopped: all clocks,
Main regulator: shutdown,
Ta = 25°C
5
70
µA
Page 66 of 95
R32C/116 Group
5. Electrical Characteristics
VCC = 5 V
Table 5.18
A/D Conversion Characteristics (VCC = AVCC = VREF = 4.2 to 5.5 V, VSS = AVSS = 0 V,
Ta = Topr, and f(BCLK) = 32 MHz, unless otherwise noted)
Symbol
—
Characteristic
Measurement condition
Resolution
VREF = VCC
Absolute error
VREF = VCC = 5 V
Value
Min.
Typ.
Max.
Unit
10
Bits
AN_0 to AN_7,
AN0_0 to AN0_7,
AN2_0 to AN2_7,
AN15_0 to AN15_7,
ANEX0, ANEX1 (1)
±3
LSB
External op-amp
connection mode
±7
LSB
AN_0 to AN_7,
AN0_0 to AN0_7,
AN2_0 to AN2_7,
AN15_0 to AN15_7,
ANEX0, ANEX1 (1)
±3
LSB
External op-amp
connection mode
±7
LSB
Differential non-linearity
error
±1
LSB
—
Offset error
±3
LSB
—
Gain error
±3
LSB
20
kΩ
—
INL
Integral non-linearity
error
DNL
VREF = VCC = 5 V
RLADDER
Resistor ladder
VREF = VCC
tCONV
Conversion time
(10 bits)
φAD = 16 MHz, with sample and hold
function
2.06
µs
φAD = 16 MHz, without sample and hold
function
3.69
µs
φAD = 16 MHz, with sample and hold
function
1.75
µs
φAD = 16 MHz, without sample and hold
function
3.06
µs
φAD = 16 MHz
0.188
µs
tCONV
Conversion time
(8 bits)
tSAMP
Sampling time
VIA
Analog input voltage
φAD
Operating clock
frequency
without sample and hold function
with sample and hold function
4
0
VREF
V
0.25
16
MHz
1
16
MHz
Note:
1. Pins AN15_0 to AN15_7 are available in the 144-pin package only.
REJ03B0253-0110
Jun 23, 2010
Rev.1.10
Page 67 of 95
R32C/116 Group
5. Electrical Characteristics
VCC = 5 V
Table 5.19
D/A Conversion Characteristics (VCC = AVCC = VREF = 4.2 to 5.5 V, VSS = AVSS = 0 V,
and Ta = Topr, unless otherwise noted)
Symbol
Characteristic
—
Resolution
—
Absolute precision
tS
Settling time
RO
Output resistance
IVREF
Reference input current
Measurement condition
Value
Min.
4
(1)
Typ.
10
Max.
Unit
8
Bits
1.0
%
3
µs
20
kΩ
1.5
mA
Note:
1. One D/A converter is used. The DAi register (i = 0, 1) of the other unused converter is set to 00h. The
resistor ladder for A/D converter is not considered.
Even when the VCUT bit in the AD0CON1 register is set to 0 (VREF disconnected), IVREF is supplied.
REJ03B0253-0110
Jun 23, 2010
Rev.1.10
Page 68 of 95
R32C/116 Group
5. Electrical Characteristics
VCC = 5 V
Timing Requirements (VCC = 4.2 to 5.5 V, VSS = 0 V, and Ta = Topr, unless otherwise noted)
Table 5.20
External Clock Input
Symbol
Value
Characteristic
Min.
Max.
62.5
250
Unit
tc(X)
External clock input period
tw(XH)
External clock input high level pulse width
25
ns
tw(XL)
External clock input low level pulse width
25
ns
tr(X)
External clock input rise time
5
ns
tf(X)
External clock input fall time
5
ns
tw / tc
External clock input duty
60
%
Table 5.21
40
ns
External Bus Timing
Symbol
Characteristic
Value
Min.
Unit
Max.
tsu(D-R)
th(R-D)
Data setup time for read
40
ns
Data hold time after read
0
ns
tdis(R-D)
Data disable time after read
REJ03B0253-0110
Jun 23, 2010
Rev.1.10
0.5 × tc(Base) + 10
ns
Page 69 of 95
R32C/116 Group
5. Electrical Characteristics
VCC = 5 V
Timing Requirements (VCC = 4.2 to 5.5 V, VSS = 0 V, and Ta = Topr, unless otherwise noted)
Table 5.22
Timer A Input (Counting input in event counter mode)
Symbol
Characteristic
Value
Min.
Max.
Unit
tc(TA)
TAiIN input clock period
200
ns
tw(TAH)
TAiIN input high level pulse width
80
ns
tw(TAL)
TAiIN input low level pulse width
80
ns
Table 5.23
Timer A Input (Gating input in timer mode)
Symbol
Characteristic
Value
Min.
Max.
Unit
tc(TA)
TAiIN input clock period
400
ns
tw(TAH)
TAiIN input high level pulse width
180
ns
tw(TAL)
TAiIN input low level pulse width
180
ns
Table 5.24
Timer A Input (External trigger input in one-shot timer mode)
Symbol
Characteristic
Value
Min.
Max.
Unit
tc(TA)
TAiIN input clock period
200
ns
tw(TAH)
TAiIN input high level pulse width
80
ns
tw(TAL)
TAiIN input low level pulse width
80
ns
Table 5.25
Timer A Input (External trigger input in pulse-width modulation mode)
Symbol
Characteristic
Value
Min.
Max.
Unit
tw(TAH)
TAiIN input high level pulse width
80
ns
tw(TAL)
TAiIN input low level pulse width
80
ns
Table 5.26
Timer A Input (Increment/decrement count switching input in event counter mode)
Symbol
Characteristic
Value
Min.
Max.
Unit
tc(UP)
TAiOUT input clock period
2000
ns
tw(UPH)
TAiOUT input high level pulse width
1000
ns
tw(UPL)
TAiOUT input low level pulse width
1000
ns
tsu(UP-TIN)
TAiOUT input setup time
400
ns
th(TIN-UP)
TAiOUT input hold time
400
ns
REJ03B0253-0110
Jun 23, 2010
Rev.1.10
Page 70 of 95
R32C/116 Group
5. Electrical Characteristics
VCC = 5 V
Timing Requirements (VCC = 4.2 to 5.5 V, VSS = 0 V, and Ta = Topr, unless otherwise noted)
Table 5.27
Timer B Input (Counting input in event counter mode)
Symbol
Characteristic
Value
Min.
Max.
Unit
tc(TB)
TBiIN input clock period (one edge counting)
200
ns
tw(TBH)
TBiIN input high level pulse width (one edge counting)
80
ns
tw(TBL)
TBiIN input low level pulse width (one edge counting)
80
ns
tc(TB)
TBiIN input clock period (both edges counting)
200
ns
tw(TBH)
TBiIN input high level pulse width (both edges counting)
80
ns
tw(TBL)
TBiIN input low level pulse width (both edges counting)
80
ns
Table 5.28
Timer B Input (Pulse period measure mode)
Symbol
Characteristic
Value
Min.
Max.
Unit
tc(TB)
TBiIN input clock period
400
ns
tw(TBH)
TBiIN input high level pulse width
180
ns
tw(TBL)
TBiIN input low level pulse width
180
ns
Table 5.29
Timer B Input (Pulse-width measure mode)
Symbol
Characteristic
Value
Min.
Max.
Unit
tc(TB)
TBiIN input clock period
400
ns
tw(TBH)
TBiIN input high level pulse width
180
ns
tw(TBL)
TBiIN input low level pulse width
180
ns
REJ03B0253-0110
Jun 23, 2010
Rev.1.10
Page 71 of 95
R32C/116 Group
5. Electrical Characteristics
VCC = 5 V
Timing Requirements (VCC = 4.2 to 5.5 V, VSS = 0 V, and Ta = Topr, unless otherwise noted)
Table 5.30
Serial Interface
Symbol
Characteristic
Value
Min.
Max.
Unit
tc(CK)
CLKi input clock period
200
ns
tw(CKH)
CLKi input high level pulse width
80
ns
tw(CKL)
CLKi input low level pulse width
80
ns
tsu(D-C)
RXDi input setup time
80
ns
th(C-D)
RXDi input hold time
90
ns
Table 5.31
A/D Trigger Input
Symbol
Characteristic
Value
Min.
Max.
Unit
tw(ADH)
ADTRG input high level pulse width
Hardware trigger input high level pulse width
3--------φ AD
ns
tw(ADL)
ADTRG input low level pulse width
Hardware trigger input high level pulse width
125
ns
Table 5.32
External Interrupt INTi Input
Symbol
INTi input high level pulse width
tw(INH)
INTi input low level pulse width
tw(INL)
Table 5.33
Value
Characteristic
Min.
Max.
Unit
Edge sensitive
250
ns
Level sensitive
tc(CPU) + 200
ns
Edge sensitive
250
ns
Level sensitive
tc(CPU) + 200
ns
Intelligent I/O
Symbol
Characteristic
Value
Min.
Max.
Unit
tc(ISCLK2)
ISCLK2 input clock period
600
ns
tw(ISCLK2H)
ISCLK2 input high level pulse width
270
ns
tw(ISCLK2L)
ISCLK2 input low level pulse width
270
ns
tsu(RXD-ISCLK2)
ISRXD2 input setup time
150
ns
th(ISCLK2-RXD)
ISRXD2 input hold time
100
ns
REJ03B0253-0110
Jun 23, 2010
Rev.1.10
Page 72 of 95
R32C/116 Group
5. Electrical Characteristics
VCC = 5 V
Timing Requirements (VCC = 4.2 to 5.5 V, VSS = 0 V, and Ta = Topr, unless otherwise noted)
Table 5.34
Multi-master I2C-bus Interface
Value
Symbol
Characteristic
Standard-mode
Min.
Max.
Fast-mode
Min.
Unit
Max.
tw(SCLH)
MSCL input high level pulse width
600
600
ns
tw(SCLL)
MSCL input low level pulse width
600
600
ns
tr(SCL)
MSCL input rise time
1000
300
ns
tf(SCL)
MSCL input fall time
300
300
ns
tr(SDA)
MSDA input rise time
1000
300
ns
tf(SDA)
MSDA input fall time
300
300
ns
th(SDA-SCL)S
MSCL high level hold time after start
condition/restart condition
(1)
2 × tc(φIIC) + 40
ns
tsu(SCL-SDA)P
MSCL high level setup time for
restart condition/stop condition
(1)
2 × tc(φIIC) + 40
ns
tw(SDAH)P
MSDA high level pulse width after
stop condition
(1)
4 × tc(φIIC) + 40
ns
tsu(SDA-SCL)
MSDA input setup time
100
100
ns
th(SCL-SDA)
MSDA input hold time
0
0
ns
Note:
1. The value is calculated by the following formulas based on a value SSC set by bits SSC4 to SSC0 in
the I2CSSCR register:
th(SDA-SCL)S = SSC ÷ 2 × tc(φIIC) + 40 [ns]
tsu(SCL-SDA)P = (SSC ÷ 2 + 1) × tc(φIIC) + 40 [ns]
tw(SDAH)P = (SSC + 1) × tc(φIIC) + 40 [ns]
REJ03B0253-0110
Jun 23, 2010
Rev.1.10
Page 73 of 95
R32C/116 Group
5. Electrical Characteristics
VCC = 5 V
Switching Characteristics (VCC = 4.2 to 5.5 V, VSS = 0 V, and Ta = Topr, unless otherwise noted)
Table 5.35
External Bus Timing (Separate bus)
Symbol
Characteristic
Measurement
condition
Value
Min.
Max.
Unit
tsu(S-R)
Chip-select setup time for read
(1)
ns
th(R-S)
Chip-select hold time after read
tc(Base) - 15
ns
tsu(A-R)
Address setup time for read
(1)
ns
th(R-A)
Address hold time after read
tc(Base) - 15
ns
tw(R)
Read pulse width
(1)
ns
tsu(S-W)
Chip-select setup time for write
(1)
ns
th(W-S)
Chip-select hold time after write
1.5 × tc(Base) - 15
ns
tsu(A-W)
Address setup time for write
(1)
ns
th(W-A)
Address hold time after write
1.5 × tc(Base) - 15
ns
tw(W)
Write pulse width
(1)
ns
tsu(D-W)
Data setup time for write
(1)
ns
th(W-D)
Data hold time after write
0
ns
Refer to
Figure 5.6
Note:
1. The value is calculated by the following formulas based on the base clock cycles (tc(Base)) and
respective cycles of Tsu(A-R), Tw(R), Tsu(A-W), and Tw(W) set by registers EBC0 to EBC3. If the
calculation results in a negative value, modify the value to be set. For the details of how to set values,
refer to the User’s manual.
tsu(S-R) = tsu(A-R) = Tsu(A-R) × tc(Base) - 15 [ns]
tw(R) = Tw(R) × tc(Base) - 10 [ns]
tsu(S-W) = tsu(A-W) = Tsu(A-W) × tc(Base) - 15 [ns]
tw(W) = tsu(D-W) = Tw(W) × tc(Base) - 10 [ns]
REJ03B0253-0110
Jun 23, 2010
Rev.1.10
Page 74 of 95
R32C/116 Group
5. Electrical Characteristics
VCC = 5 V
Switching Characteristics (VCC = 4.2 to 5.5 V, VSS = 0 V, and Ta = Topr, unless otherwise noted)
Table 5.36
External Bus Timing (Multiplexed bus)
Symbol
Characteristic
Measurement
condition
Value
Min.
Max.
Unit
tsu(S-ALE)
Chip-select setup time for ALE
(1)
ns
th(R-S)
Chip-select hold time after read
1.5 × tc(Base) - 15
ns
tsu(A-ALE)
Address setup time for ALE
(1)
ns
th(ALE-A)
Address hold time after ALE
0.5 × tc(Base) - 5
ns
th(R-A)
Address hold time after read
1.5 × tc(Base) - 15
ns
td(ALE-R)
ALE-read delay time
0.5 × tc(Base) - 5 0.5 × tc(Base) + 10 ns
tw(ALE)
ALE pulse width
tdis(R-A)
Address disable time after read
tw(R)
Read pulse width
th(W-S)
(1)
Refer to
Figure 5.6
ns
8
ns
(1)
ns
Chip-select hold time after write
1.5 × tc(Base) - 15
ns
th(W-A)
Address hold time after write
1.5 × tc(Base) - 15
ns
td(ALE-W)
ALE-write delay time
0.5 × tc(Base) - 5 0.5 × tc(Base) + 10 ns
tw(W)
Write pulse width
(1)
ns
tsu(D-W)
Data setup time for write
(1)
ns
th(W-D)
Data hold time after write
0.5 × tc(Base)
ns
Note:
1. The value is calculated by the following formulas based on the base clock cycles (tc(Base)) and
respective cycles of Tsu(A-R), Tw(R), Tsu(A-W), and Tw(W) set by registers EBC0 to EBC3. If the
calculation results in a negative value, modify the value to be set. For the details of how to set values,
refer to the User’s manual.
tsu(S-ALE) = tsu(A-ALE) = tw(ALE) = (Tsu(A-R) - 0.5) × tc(Base) -15 [ns]
tw(R) = Tw(R) × tc(Base) -10 [ns]
tw(W) = tsu(D-W) = Tw(W) × tc(Base) -10 [ns]
REJ03B0253-0110
Jun 23, 2010
Rev.1.10
Page 75 of 95
R32C/116 Group
5. Electrical Characteristics
VCC = 5 V
Switching Characteristics (VCC = 4.2 to 5.5 V, VSS = 0 V, and Ta = Topr, unless otherwise noted)
Table 5.37
Serial Interface
Symbol
td(C-Q)
TXDi output delay time
th(C-Q)
TXDi output hold time
Table 5.38
Min.
Max.
Unit
80
Refer to
Figure 5.6
ns
0
ns
Intelligent I/O
Symbol
ISTXD2 output delay time
th(ISCLK2-RXD)
ISTXD2 output hold time
Value
Measurement
condition
Characteristic
td(ISCLK2-TXD)
Table 5.39
Value
Measurement
condition
Characteristic
Min.
Max.
Unit
180
Refer to
Figure 5.6
ns
0
ns
Multi-master I2C-bus Interface (Standard-mode)
Symbol
Characteristic
Value
Measurement
condition
Min.
Unit
Max.
tf(SCL)
MSCL output fall time
2
ns
tf(SDA)
MSDA output fall time
2
ns
td(SDA-SCL)S MSCL output delay time after start
condition/restart condition
td(SCL-SDA)P Restart condition/stop condition
output delay time after MSCL
becomes high
Refer to
Figure 5.6
td(SCL-SDA) MSDA output delay time
Table 5.40
20 × tc(φIIC) - 120 52 × tc(φIIC) - 40
ns
20 × tc(φIIC) + 40 52 × tc(φIIC) + 120
ns
2 × tc(φIIC) + 40
ns
3 × tc(φIIC) + 120
Multi-master I2C-bus Interface (Fast-mode)
Symbol
Characteristic
Value
Measurement
condition
Min.
Unit
Max.
tf(SCL)
MSCL output fall time
2 (1)
ns
tf(SDA)
MSDA output fall time
2 (1)
ns
td(SDA-SCL)S MSCL output delay time after start
condition/restart condition
td(SCL-SDA)P Restart condition/stop condition
output delay time after MSCL
becomes high
td(SCL-SDA) MSDA output delay time
Refer to
Figure 5.6
10 × tc(φIIC) - 120 26 × tc(φIIC) - 40
ns
10 × tc(φIIC) + 40 26 × tc(φIIC) + 120
ns
2 × tc(φIIC) + 40
ns
3 × tc(φIIC) + 120
Note:
1. External circuits are required to satisfy the I2C-bus specification.
REJ03B0253-0110
Jun 23, 2010
Rev.1.10
Page 76 of 95
R32C/116 Group
5. Electrical Characteristics
VCC = 3.3 V
Table 5.41
Electrical Characteristics (1/3) (VCC = 3.0 to 3.6 V, VSS = 0 V, Ta = Topr, and
f(CPU) = 64 MHz, unless otherwise noted)
Symbol
VOH
VOL
Characteristic
Value
Measurement
condition
Min.
VCC - 0.6
High
level
output
voltage
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4,
P8_6, P8_7, P9_0 to P9_7,
P10_0 to P10_7, P11_0 to P11_4,
P12_0 to P12_7, P13_0 to P13_7,
P14_3 to P14_6, P15_0 to P15_7 (1)
IOH = -1 mA
Low
level
output
voltage
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4,
P8_6, P8_7, P9_0 to P9_7,
P10_0 to P10_7, P11_0 to P11_4,
P12_0 to P12_7, P13_0 to P13_7,
P14_3 to P14_6, P15_0 to P15_7 (1)
IOL = 1 mA
Typ. Max.
Unit
VCC
V
0.5
V
Note:
1. Ports P9_0, P9_2, and P11 to P15 are available in the 144-pin package only. Port P9_1 is designated
as input pin in the 100-pin package.
REJ03B0253-0110
Jun 23, 2010
Rev.1.10
Page 77 of 95
R32C/116 Group
5. Electrical Characteristics
VCC = 3.3 V
Table 5.42
Electrical Characteristics (2/3) (VCC = 3.0 to 3.6 V, VSS = 0 V, Ta = Topr, and
f(CPU) = 64 MHz, unless otherwise noted)
Symbol
Characteristic
VT+ - VT- Hysteresis HOLD, RDY, NMI, INT0 to INT8, KI0 to KI3,
TA0IN to TA4IN, TA0OUT to TA4OUT,
TB0IN to TB5IN, CTS0 to CTS8,
CLK0 to CLK8, RXD0 to RXD8,
SCL0 to SCL6, SDA0 to SDA6, SS0 to SS6,
SRXD0 to SRXD6, ADTRG,
IIO0_0 to IIO0_7, IIO1_0 to IIO1_7, UD0A,
UD0B, UD1A, UD1B, ISCLK2, ISRXD2,
IEIN (1)
RESET
IIH
High level XIN, RESET, CNVSS, NSD,
input
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
current
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7,
P9_0 to P9_7, P10_0 to P10_7,
P11_0 to P11_4, P12_0 to P12_7,
P13_0 to P13_7, P14_1, P14_3 to P14_6,
P15_0 to P15_7 (2)
Low level XIN, RESET, CNVSS, NSD,
IIL
input
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
current
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7,
P9_0 to P9_7, P10_0 to P10_7,
P11_0 to P11_4, P12_0 to P12_7,
P13_0 to P13_7, P14_1, P14_3 to P14_6,
P15_0 to P15_7 (2)
RPULLUP Pull-up
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
resistor
P3_0 to P3_7, P5_0 to P5_3, P8_4, P8_6,
P8_7, P9_0 to P9_7, P10_0 to P10_7,
P11_0 to P11_4, P12_0 to P12_7,
P13_0 to P13_7, P14_1, P14_3 to P14_6,
P15_0 to P15_7 (2)
RfXIN
Feedback XIN
resistor
RfXCIN
Feedback XCIN
resistor
Value
Measurement
Unit
condition
Min. Typ. Max.
0.2
1.0
V
0.2
1.8
V
VI = 3.3 V
4.0
µA
VI = 0 V
-4.0
µA
500
kΩ
VI = 0 V
50
100
3
MΩ
25
MΩ
Notes:
1. Pins INT6 to INT8 are available in the 144-pin package only.
2. Ports P9_0, P9_2, and P11 to P15 are available in the 144-pin package only. Port P9_1 is designated
as input pin in the 100-pin package.
REJ03B0253-0110
Jun 23, 2010
Rev.1.10
Page 78 of 95
R32C/116 Group
5. Electrical Characteristics
VCC = 3.3 V
Table 5.43
Symbol
ICC
Electrical Characteristics (3/3)
(VCC = 3.0 to 3.6 V, VSS = 0 V, and Ta = Topr, unless otherwise noted)
Characte
ristic
Power
supply
current
Measurement condition
Min. Typ. Max.
Unit
In single-chip mode,
output pins are left open
and others are
connected to VSS
f(CPU) = 64 MHz, f(BCLK) = 32 MHz,
f(XIN) = 8 MHz,
Active: XIN, PLL,
Stopped: XCIN, OCO
40
55
mA
XIN-XOUT
Drive power: low
f(CPU) = 50 MHz, f(BCLK) = 25 MHz,
f(XIN) = 8 MHz,
Active: XIN, PLL,
Stopped: XCIN, OCO
32
45
mA
f(CPU) = fSO(PLL)/24 MHz,
Active: PLL (self-oscillation),
Stopped: XIN, XCIN, OCO
9
mA
f(CPU) = f(BCLK) = f(XIN)/256 MHz,
f(XIN) = 8 MHz,
Active: XIN,
Stopped: PLL, XCIN, OCO
670
µA
f(CPU) = f(BCLK) = 32.768 kHz,
Active: XCIN,
Stopped: XIN, PLL, OCO,
Main regulator: shutdown
180
µA
f(CPU) = f(BCLK) = f(OCO)/4 kHz,
Active: OCO,
Stopped: XIN, PLL, XCIN,
Main regulator: shutdown
190
µA
f(CPU) = f(BCLK) = f(XIN)/256 MHz,
f(XIN) = 8 MHz,
Active: XIN,
Stopped: PLL, XCIN, OCO,
Ta = 25°C, Wait mode
500
900
µA
f(CPU) = f(BCLK) = 32.768 kHz,
Active: XCIN,
Stopped: XIN, PLL, OCO,
Main regulator: shutdown,
Ta = 25°C, Wait mode
8
140
µA
f(CPU) = f(BCLK) = f(OCO)/4 kHz,
Active: OCO,
Stopped: XIN, PLL, XCIN,
Main regulator: shutdown,
Ta = 25°C, Wait mode
10
150
µA
Stopped: all clocks,
Main regulator: shutdown,
Ta = 25°C
5
70
µA
XCIN-XCOUT
Drive power: low
REJ03B0253-0110
Jun 23, 2010
Value
Rev.1.10
Page 79 of 95
R32C/116 Group
5. Electrical Characteristics
VCC = 3.3 V
Table 5.44
A/D Conversion Characteristics (VCC = AVCC = VREF = 3.0 to 3.6 V, VSS = AVSS = 0 V,
Ta = Topr, and f(BCLK) = 32 MHz, unless otherwise noted)
Symbol
—
Characteristic
Measurement condition
Value
Min.
Unit
VREF = VCC
10
Bits
Absolute error
VREF = VCC = 3.3 V AN_0 to AN_7,
AN0_0 to AN0_7,
AN2_0 to AN2_7,
AN15_0 to AN15_7,
ANEX0, ANEX1 (1)
±5
LSB
±7
LSB
±5
LSB
±7
LSB
±1
LSB
External op-amp
connection mode
Integral non-linearity
error
VREF = VCC = 3.3 V AN_0 to AN_7,
AN0_0 to AN0_7,
AN2_0 to AN2_7,
AN15_0 to AN15_7,
ANEX0, ANEX1 (1)
External op-amp
connection mode
DNL
Max.
Resolution
—
INL
Typ.
Differential nonlinearity error
VREF = VCC = 3.3 V
—
Offset error
±3
LSB
—
Gain error
±3
LSB
20
kΩ
RLADDER
Resistor ladder
VREF = VCC
tCONV
Conversion time
(10 bits)
φAD = 10 MHz,
with sample and hold function
3.3
µs
tCONV
Conversion time
(8 bits)
φAD = 10 MHz,
with sample and hold function
2.8
µs
tSAMP
Sampling time
φAD = 10 MHz
0.3
µs
VIA
Analog input voltage
φAD
Operating clock
frequency
without sample and hold function
with sample and hold function
4
0
VREF
V
0.25
10
MHz
1
10
MHz
Note:
1. Pins AN15_0 to AN15_7 are available in the 144-pin package only.
REJ03B0253-0110
Jun 23, 2010
Rev.1.10
Page 80 of 95
R32C/116 Group
5. Electrical Characteristics
VCC = 3.3 V
Table 5.45
D/A Conversion Characteristics (VCC = AVCC = VREF = 3.0 to 3.6 V, VSS = AVSS = 0 V,
and Ta = Topr, unless otherwise noted)
Symbol
Characteristic
—
Resolution
—
Absolute precision
tS
Settling time
RO
Output resistance
IVREF
Reference input current
Measurement condition
Value
Min.
4
(1)
Typ.
10
Max.
Unit
8
Bits
1.0
%
3
µs
20
kΩ
1.0
mA
Note:
1. One D/A converter is used. The DAi register (i = 0, 1) of the other unused converter is set to 00h. The
resistor ladder for A/D converter is not considered.
Even when the VCUT bit in the AD0CON1 register is set to 0 (VREF disconnected), IVREF is supplied.
REJ03B0253-0110
Jun 23, 2010
Rev.1.10
Page 81 of 95
R32C/116 Group
5. Electrical Characteristics
VCC = 3.3 V
Timing Requirements (VCC = 3.0 to 3.6 V, VSS = 0 V, and Ta = Topr, unless otherwise noted)
Table 5.46
External Clock Input
Symbol
Value
Characteristic
Min.
Max.
62.5
250
Unit
tc(X)
External clock input period
tw(XH)
External clock input high level pulse width
25
ns
tw(XL)
External clock input low level pulse width
25
ns
tr(X)
External clock input rise time
5
ns
tf(X)
External clock input fall time
5
ns
tw / tc
External clock input duty
60
%
Table 5.47
40
ns
External Bus Timing
Symbol
Characteristic
Value
Min.
Unit
Max.
tsu(D-R)
Data setup time for read
40
ns
th(R-D)
Data hold time after read
0
ns
tdis(R-D)
Data disable time after read
REJ03B0253-0110
Jun 23, 2010
Rev.1.10
0.5 × tc(Base) + 10
ns
Page 82 of 95
R32C/116 Group
5. Electrical Characteristics
VCC = 3.3 V
Timing Requirements (VCC = 3.0 to 3.6 V, VSS = 0 V, and Ta = Topr, unless otherwise noted)
Table 5.48
Timer A Input (Counting input in event counter mode)
Symbol
Characteristic
Value
Min.
Max.
Unit
tc(TA)
TAiIN input clock period
200
ns
tw(TAH)
TAiIN input high level pulse width
80
ns
tw(TAL)
TAiIN input low level pulse width
80
ns
Table 5.49
Timer A Input (Gating input in timer mode)
Symbol
Characteristic
Value
Min.
Max.
Unit
tc(TA)
TAiIN input clock period
400
ns
tw(TAH)
TAiIN input high level pulse width
180
ns
tw(TAL)
TAiIN input low level pulse width
180
ns
Table 5.50
Timer A Input (External trigger input in one-shot timer mode)
Symbol
Characteristic
Value
Min.
Max.
Unit
tc(TA)
TAiIN input clock period
200
ns
tw(TAH)
TAiIN input high level pulse width
80
ns
tw(TAL)
TAiIN input low level pulse width
80
ns
Table 5.51
Timer A Input (External trigger input in pulse-width modulation mode)
Symbol
Characteristic
Value
Min.
Max.
Unit
tw(TAH)
TAiIN input high level pulse width
80
ns
tw(TAL)
TAiIN input low level pulse width
80
ns
Table 5.52
Timer A Input (Increment/decrement count switching input in event counter mode)
Symbol
Characteristic
Value
Min.
Max.
Unit
tc(UP)
TAiOUT input clock period
2000
ns
tw(UPH)
TAiOUT input high level pulse width
1000
ns
tw(UPL)
TAiOUT input low level pulse width
1000
ns
tsu(UP-TIN)
TAiOUT input setup time
400
ns
th(TIN-UP)
TAiOUT input hold time
400
ns
REJ03B0253-0110
Jun 23, 2010
Rev.1.10
Page 83 of 95
R32C/116 Group
5. Electrical Characteristics
VCC = 3.3 V
Timing Requirements (VCC = 3.0 to 3.6 V, VSS = 0 V, and Ta = Topr, unless otherwise noted)
Table 5.53
Timer B Input (Counting input in event counter mode)
Symbol
Characteristic
Value
Min.
Max.
Unit
tc(TB)
TBiIN input clock period (one edge counting)
200
ns
tw(TBH)
TBiIN input high level pulse width (one edge counting)
80
ns
tw(TBL)
TBiIN input low level pulse width (one edge counting)
80
ns
tc(TB)
TBiIN input clock period (both edges counting)
200
ns
tw(TBH)
TBiIN input high level pulse width (both edges counting)
80
ns
tw(TBL)
TBiIN input low level pulse width (both edges counting)
80
ns
Table 5.54
Timer B Input (Pulse period measure mode)
Symbol
Characteristic
Value
Min.
Max.
Unit
tc(TB)
TBiIN input clock period
400
ns
tw(TBH)
TBiIN input high level pulse width
180
ns
tw(TBL)
TBiIN input low level pulse width
180
ns
Table 5.55
Timer B Input (Pulse-width measure mode)
Symbol
Characteristic
Value
Min.
Max.
Unit
tc(TB)
TBiIN input clock period
400
ns
tw(TBH)
TBiIN input high level pulse width
180
ns
tw(TBL)
TBiIN input low level pulse width
180
ns
REJ03B0253-0110
Jun 23, 2010
Rev.1.10
Page 84 of 95
R32C/116 Group
5. Electrical Characteristics
VCC = 3.3 V
Timing Requirements (VCC = 3.0 to 3.6 V, VSS = 0 V, and Ta = Topr, unless otherwise noted)
Table 5.56
Serial Interface
Symbol
Characteristic
Value
Min.
Max.
Unit
tc(CK)
CLKi input clock period
200
ns
tw(CKH)
CLKi input high level pulse width
80
ns
tw(CKL)
CLKi input low level pulse width
80
ns
tsu(D-C)
RXDi input setup time
80
ns
th(C-D)
RXDi input hold time
90
ns
Table 5.57
A/D Trigger Input
Symbol
Characteristic
Value
Min.
Max.
Unit
tw(ADH)
ADTRG input high level pulse width
Hardware trigger input high level pulse width
3--------φ AD
ns
tw(ADL)
ADTRG input low level pulse width
Hardware trigger input high level pulse width
125
ns
Table 5.58
External Interrupt INTi Input
Symbol
tw(INH)
tw(INL)
Table 5.59
Value
Characteristic
INTi input high level pulse width
INTi input low level pulse width
Min.
Max.
Unit
Edge sensitive
250
ns
Level sensitive
tc(CPU) + 200
ns
Edge sensitive
250
ns
Level sensitive
tc(CPU) + 200
ns
Intelligent I/O
Symbol
Characteristic
Value
Min.
Max.
Unit
tc(ISCLK2)
ISCLK2 input clock period
600
ns
tw(ISCLK2H)
ISCLK2 input high level pulse width
270
ns
tw(ISCLK2L)
ISCLK2 input low level pulse width
270
ns
150
ns
100
ns
tsu(RXD-ISCLK2) ISRXD2 input setup time
th(ISCLK2-RXD)
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ISRXD2 input hold time
Rev.1.10
Page 85 of 95
R32C/116 Group
5. Electrical Characteristics
VCC = 3.3 V
Timing Requirements (VCC = 3.0 to 3.6 V, VSS = 0 V, and Ta = Topr, unless otherwise noted)
Table 5.60
Multi-master I2C-bus Interface
Value
Symbol
Characteristic
Standard-mode
Min.
Max.
600
Fast-mode
Min.
Max.
600
Unit
tw(SCLH)
MSCL input high level pulse width
tw(SCLL)
MSCL input low level pulse width
tr(SCL)
MSCL input rise time
1000
300
ns
tf(SCL)
MSCL input fall time
300
300
ns
tr(SDA)
MSDA input rise time
1000
300
ns
tf(SDA)
MSDA input fall time
300
300
ns
th(SDA-SCL)S
tsu(SDA-SCL)
MSCL high level hold time after start
condition/restart condition
MSCL high level setup time for
restart condition/stop condition
MSDA high level pulse width after
stop condition
MSDA input setup time
th(SCL-SDA)
MSDA input hold time
tsu(SCL-SDA)P
tw(SDAH)P
600
600
ns
ns
(1)
2 × tc(φIIC) + 40
ns
(1)
2 × tc(φIIC) + 40
ns
(1)
4 × tc(φIIC) + 40
ns
100
100
ns
0
0
ns
Note:
1. The value is calculated by the following formulas based on a value SSC set by bits SSC4 to SSC0 in
the I2CSSCR register:
th(SDA-SCL)S = SSC ÷ 2 × tc(φIIC) + 40 [ns]
tsu(SCL-SDA)P = (SSC ÷ 2 + 1) × tc(φIIC) + 40 [ns]
tw(SDAH)P = (SSC + 1) × tc(φIIC) + 40 [ns]
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R32C/116 Group
5. Electrical Characteristics
VCC = 3.3 V
Switching Characteristics (VCC = 3.0 to 3.6 V, VSS = 0 V, and Ta = Topr, unless otherwise noted)
Table 5.61
External Bus Timing (Separate bus)
Symbol
Characteristic
Measurement
condition
Value
Min.
Max.
Unit
tsu(S-R)
Chip-select setup time for read
(1)
ns
th(R-S)
Chip-select hold time after read
tc(Base) - 15
ns
tsu(A-R)
Address setup time for read
(1)
ns
th(R-A)
Address hold time after read
tc(Base) - 15
ns
tw(R)
Read pulse width
(1)
ns
tsu(S-W)
Chip-select setup time for write
(1)
ns
th(W-S)
Chip-select hold time after write
1.5 × tc(Base) - 15
ns
tsu(A-W)
Address setup time for write
(1)
ns
th(W-A)
Address hold time after write
1.5 × tc(Base) - 15
ns
tw(W)
Write pulse width
(1)
ns
tsu(D-W)
Data setup time for write
(1)
ns
th(W-D)
Data hold time after write
0
ns
Refer to
Figure 5.6
Note:
1. The value is calculated by the following formulas based on the base clock cycles (tc(Base)) and
respective cycles of Tsu(A-R), Tw(R), Tsu(A-W), and Tw(W) set by registers EBC0 to EBC3. If the
calculation results in a negative value, modify the value to be set. For the details of how to set values,
refer to the User’s manual.
tsu(S-R) = tsu(A-R) = Tsu(A-R) × tc(Base) - 15 [ns]
tw(R) = Tw(R) × tc(Base) - 10 [ns]
tsu(S-W) = tsu(A-W) = Tsu(A-W) × tc(Base) - 15 [ns]
tw(W) = tsu(D-W) = Tw(W) × tc(Base) - 10 [ns]
REJ03B0253-0110
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Page 87 of 95
R32C/116 Group
5. Electrical Characteristics
VCC = 3.3 V
Switching Characteristics (VCC = 3.0 to 3.6 V, VSS = 0 V, and Ta = Topr, unless otherwise noted)
Table 5.62
External Bus Timing (Multiplexed bus)
Symbol
Characteristic
Measurement
condition
Value
Min.
Max.
Unit
tsu(S-ALE)
Chip-select setup time for ALE
(1)
ns
th(R-S)
Chip-select hold time after read
1.5 × tc(Base) - 15
ns
tsu(A-ALE)
Address setup time for ALE
(1)
ns
th(ALE-A)
Address hold time after ALE
0.5 × tc(Base) - 5
ns
th(R-A)
Address hold time after read
1.5 × tc(Base) - 15
ns
td(ALE-R)
ALE-read delay time
0.5 × tc(Base) - 5 0.5 × tc(Base) + 10 ns
tw(ALE)
ALE pulse width
tdis(R-A)
Address disable time after read
tw(R)
Read pulse width
th(W-S)
(1)
Refer to
Figure 5.6
ns
8
ns
(1)
ns
Chip-select hold time after write
1.5 × tc(Base) - 15
ns
th(W-A)
Address hold time after write
1.5 × tc(Base) - 15
ns
td(ALE-W)
ALE-write delay time
0.5 × tc(Base) - 5 0.5 × tc(Base) + 10 ns
tw(W)
Write pulse width
(1)
ns
tsu(D-W)
Data setup time for write
(1)
ns
th(W-D)
Data hold time after write
0.5 × tc(Base)
ns
Note:
1. The value is calculated by the following formulas based on the base clock cycles (tc(Base)) and
respective cycles of Tsu(A-R), Tw(R), Tsu(A-W), and Tw(W) set by registers EBC0 to EBC3. If the
calculation results in a negative value, modify the value to be set. For the details of how to set values,
refer to the User’s manual.
tsu(S-ALE) = tsu(A-ALE) = (Tsu(A-R) - 0.5) × tc(Base) -15 [ns]
tw(ALE) = (Tsu(A-R) - 0.5) × tc(Base) - 20 [ns]
tw(R) = Tw(R) × tc(Base) -10 [ns]
tw(W) = tsu(D-W) = Tw(W) × tc(Base) -10 [ns]
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R32C/116 Group
5. Electrical Characteristics
VCC = 3.3 V
Switching Characteristics (VCC = 3.0 to 3.6 V, VSS = 0 V, and Ta = Topr, unless otherwise noted)
Table 5.63
Serial Interface
Symbol
td(C-Q)
TXDi output delay time
th(C-Q)
TXDi output hold time
Table 5.64
Intelligent I/O
Symbol
ISTXD2 output delay time
th(ISCLK2-RXD)
ISTXD2 output hold time
Table 5.65
Min.
Unit
Max.
80
Refer to
Figure 5.6
ns
0
ns
Value
Measurement
condition
Characteristic
td(ISCLK2-TXD)
Value
Measurement
condition
Characteristic
Min.
Max.
Unit
180
Refer to
Figure 5.6
ns
0
ns
Multi-master I2C-bus Interface (Standard-mode)
Symbol
Characteristic
Value
Measurement
condition
Min.
Unit
Max.
tf(SCL)
MSCL output fall time
2
ns
tf(SDA)
MSDA output fall time
2
ns
td(SDA-SCL)S MSCL output delay time after start
condition/restart condition
td(SCL-SDA)P Restart condition/stop condition
output delay time after MSCL
becomes high
Refer to
Figure 5.6
td(SCL-SDA) MSDA output delay time
Table 5.66
20 × tc(φIIC) - 120 52 × tc(φIIC) - 40
ns
20 × tc(φIIC) + 40 52 × tc(φIIC) + 120
ns
2 ×tc(φIIC) + 40
3 × tc(φIIC) + 120
ns
Multi-master I2C-bus Interface (Fast-mode)
Symbol
Characteristic
Value
Measurement
condition
Min.
Unit
Max.
tf(SCL)
MSCL output fall time
2 (1)
ns
tf(SDA)
MSDA output fall time
2 (1)
ns
td(SDA-SCL)S MSCL output delay time after start
condition/restart condition
td(SCL-SDA)P Restart condition/stop condition
output delay time after MSCL
becomes high
td(SCL-SDA) MSDA output delay time
Refer to
Figure 5.6
10 × tc(φIIC) - 120 26 × tc(φIIC) - 40
ns
10 × tc(φIIC) + 40 26 × tc(φIIC) + 120
ns
2 × tc(φIIC) + 40
ns
3 × tc(φIIC) + 120
Note:
1. External circuits are required to satisfy the I2C-bus specification.
REJ03B0253-0110
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R32C/116 Group
5. Electrical Characteristics
MCU
Pin to be
measured
30 pF
Figure 5.6
Switching Characteristic Measurement Circuit
t c(X)
XIN
t w(XH)
t r(X)
Figure 5.7
t w(XL)
t f(X)
External Clock Input Timing
REJ03B0253-0110
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R32C/116 Group
5. Electrical Characteristics
External bus timing (Separate bus)
Read cycle
t cR
t su(S-R)
t h(R-S)
t su(A-R)
t h(R-A)
CS0 to CS3
A23 to A0, BC0 to BC3
t w(R)
RD
t su(D-R)
t h(R-D)
D31 to D0
Write cycle
t cW
t su(S-W)
t h(W-S)
t su(A-W)
t h(W-A)
CS0 to CS3
A23 to A0, BC0 to BC3
t w(W)
WR, WR0 to WR3
t su(D-W)
t h(W-D)
D31 to D0
Measurement conditions
Item
Figure 5.8
V CC = 4.2 to 5.5 V
V CC = 3.0 to 3.6 V
Criterion for
input voltage
VIH
2.5 V
1.5 V
VIL
0.8 V
0.5 V
Criterion for
output voltage
VOH
2.0 V
2.4 V
VOL
0.8 V
0.5 V
External Bus Timing (Separate Bus)
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R32C/116 Group
5. Electrical Characteristics
External bus timing (Multiplexed bus)
Read timing
t cR
t su(S-ALE)
t h(R-S)
t su(A-ALE)
t h(R-A)
CS0 to CS3
A23 to A8, BC0 to BC3
t w(ALE)
t h(ALE-A)
ALE
t su(A-ALE)
A15/D15 to A0/D0,
BC0/D0, BC2/D1
t dis(R-A)
t su(D-R)
Address
t h(R-D)
Data
t d(ALE-R)
t w(R)
t dis(R-D)
RD
t su(D-R)
t h(R-D)
D31 to D8
Write cycle
t cW
t su(S-ALE)
t h(W-S)
t su(A-ALE)
t h(W-A)
CS0 to CS3
A23 to A8, BC0 to BC3
t w(ALE)
ALE
t su(A-ALE)
A15/D15 to A0/D0,
BC0/D0, BC2/D1
t h(ALE-A)
t su(D-W)
Address
t d(ALE-W)
t h(W-D)
Data
t w(W)
WR, WR0 to WR3
t su(D-W)
t h(W-D)
D31 to D8
Measurement conditions
Item
Criterion for
input voltage
Criterion for
output voltage
Figure 5.9
V CC = 4.2 to 5.5 V
V CC = 3.0 to 3.6 V
VIH
2.5 V
1.5 V
VIL
0.8 V
0.5 V
VOH
2.0 V
2.4 V
VOL
0.8 V
0.5 V
External Bus Timing (Multiplexed Bus)
REJ03B0253-0110
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R32C/116 Group
5. Electrical Characteristics
t c(TA)
t w(TAH)
t w(TAL)
TAiIN input
t c(UP)
t w(UPH)
t w(UPL)
TAiOUT input
In event counter mode
TAiOUT input (input for increment/
decrement count switching)
t su(UP-TIN)
t h(TIN-UP)
TAiIN input (in falling edge counting)
TAiIN input (in rising edge counting)
t c(TB)
t w(TBH)
t w(TBL)
TBiIN input
t c(CK)
t w(CKH)
t w(CKL)
CLKi
t d(C-Q)
t h(C-Q)
TXDi
t su(D-C)
t h(C-D)
RXDi
t w(ADL)
t w(ADH)
t w(INL)
t w(INH)
ADTRG input
INTi input
2 CPU clock cycles +
300 ns or more
2 CPU clock cycles +
300 ns or more
NMI input
Figure 5.10
Timing of Peripheral Functions
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R32C/116 Group
5. Electrical Characteristics
t c(SCL)
MSCL
t w(SCLH)
t w(SCLL)
t r(SCL)
t f(SCL)
t r(SDA)
t f(SDA)
MSDA
t w(SDAH)P
t h(SDA-SCL)S
t su(SCL-SDA)P
t su(SCL-SDA)P
MSCL
MSDA (input)
t h(SDA-SCL)S
t d(SDA-SCL)S
t d(SCL-SDA)P
t d(SCL-SDA)P
MSCL
MSDA (output)
t d(SDA-SCL)S
t su(SDA-SCL)
t h(SCL-SDA)
MSCL
MSDA (input)
t d(SCL-SDA)
MSCL
MSDA (output)
Figure 5.11
Timing of Multi-master I2C-bus Interface
REJ03B0253-0110
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R32C/116 Group
Appendix 1. Package Dimensions
Appendix 1. Package Dimensions
JEITA Package Code
P-LQFP144-20x20-0.50
RENESAS Code
PLQP0144KA-A
Previous Code
144P6Q-A / FP-144L / FP-144LV
MASS[Typ.]
1.2g
HD
*1
D
108
73
109
NOTE)
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
72
bp
c
Reference Dimension in Millimeters
Symbol
*2
E
HE
c1
b1
Terminal cross section
Index mark
c
36
A
1
ZD
ZE
37
A2
144
D
E
A2
HD
HE
A
A1
bp
b1
c
c1
F
A1
S
L
L1
*3
e
y S
JEITA Package Code
P-LQFP100-14x14-0.50
RENESAS Code
PLQP0100KB-A
bp
e
x
y
ZD
ZE
L
L1
Detail F
x
Previous Code
100P6Q-A / FP-100U / FP-100UV
Min Nom Max
19.9 20.0 20.1
19.9 20.0 20.1
1.4
21.8 22.0 22.2
21.8 22.0 22.2
1.7
0.05 0.1 0.15
0.17 0.22 0.27
0.20
0.09 0.145 0.20
0.125
8°
0°
0.5
0.08
0.10
1.25
1.25
0.35 0.5 0.65
1.0
MASS[Typ.]
0.6g
HD
*1
D
51
75
NOTE)
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
50
76
bp
HE
Reference
Symbol
c
c1
*2
E
b1
D
E
A2
HD
HE
A
A1
bp
b1
c
c1
100
26
1
ZE
Terminal cross section
25
Index mark
ZD
F
y S
e
*3
bp
A1
c
A
A2
S
L
x
L1
Detail F
REJ03B0253-0110
Jun 23, 2010
Rev.1.10
e
x
y
ZD
ZE
L
L1
Dimension in Millimeters
Min Nom Max
13.9 14.0 14.1
13.9 14.0 14.1
1.4
15.8 16.0 16.2
15.8 16.0 16.2
1.7
0.05 0.1 0.15
0.15 0.20 0.25
0.18
0.09 0.145 0.20
0.125
8°
0°
0.5
0.08
0.08
1.0
1.0
0.35 0.5 0.65
1.0
Page 95 of 95
Revision History
Rev.
1.00
1.10
Date
Nov 19, 2009
Jun 23, 2010
Page
—
—
—
3, 5
9
19
34, 37
39
41
52
63
95
R32C/116 Group Datasheet
Description
Summary
Initial release
Second edition released
This manual in general
• Applied new Renesas templates and formats to the manual
• Changed company name to “Renesas Electronics Corporation” and
changed related descriptions due to business merger of Renesas
Technology Corporation and NEC Electronics Corporation (under
Chapters 1 and 5)
• Added specifications of 64 MHz version
Chapter 1. Overview
• Deleted Note 1 from Tables 1.2 and 1.4
• Deleted Note 4 from Figure 1.2
• Modified expression “fC” in Table 1.14 to “low speed clocks”
Chapter 4. SFRs
• Changed register name “Group i Timer Measurement Prescaler
Register” in Tables 4.6 and 4.9 to “Group i Time Measurement
Prescaler Register”
• Modified expression “XY Control Register” in Table 4.11 to “X-Y
Control Register”
• Changed register name “UART2 Transmission/Receive Mode
Register” in Table 4.13 to “UART2 Transmit/Receive Mode Register”;
Changed hexadecimal format of reset values for registers TABSR,
ONSF, and TRGSR to binary
• Changed register name “External Interrupt Source Select Register i” in
Table 4.24 to “External Interrupt Request Source Select Register i”
Chapter 5. Electrical Characteristics
• Changed expressions “CS0” and “A23 to A0, BC3 to BC0” in Figure
5.5 to “Chip select” and “Address”, respectively
Appendix 1. Package Dimensions
• Added a seating plane to the drawing of package dimension
All trademarks and registered trademarks are the property of their respective owners.
A- 1
General Precautions in the Handling of MPU/MCU Products
The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes
on the products covered by this manual, refer to the relevant sections of the manual. If the descriptions under
General Precautions in the Handling of MPU/MCU Products and in the body of the manual differ from each
other, the description in the body of the manual takes precedence.
1. Handling of Unused Pins
Handle unused pins in accord with the directions given under Handling of Unused Pins in the
manual.
 The input pins of CMOS products are generally in the high-impedance state. In operation
with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the
vicinity of LSI, an associated shoot-through current flows internally, and malfunctions occur
due to the false recognition of the pin state as an input signal become possible. Unused
pins should be handled as described under Handling of Unused Pins in the manual.
2. Processing at Power-on
The state of the product is undefined at the moment when power is supplied.
 The states of internal circuits in the LSI are indeterminate and the states of register
settings and pins are undefined at the moment when power is supplied.
In a finished product where the reset signal is applied to the external reset pin, the states
of pins are not guaranteed from the moment when power is supplied until the reset
process is completed.
In a similar way, the states of pins in a product that is reset by an on-chip power-on reset
function are not guaranteed from the moment when power is supplied until the power
reaches the level at which resetting has been specified.
3. Prohibition of Access to Reserved Addresses
Access to reserved addresses is prohibited.
 The reserved addresses are provided for the possible future expansion of functions. Do
not access these addresses; the correct operation of LSI is not guaranteed if they are
accessed.
4. Clock Signals
After applying a reset, only release the reset line after the operating clock signal has become
stable. When switching the clock signal during program execution, wait until the target clock
signal has stabilized.
 When the clock signal is generated with an external resonator (or from an external
oscillator) during a reset, ensure that the reset line is only released after full stabilization of
the clock signal. Moreover, when switching to a clock signal produced with an external
resonator (or by an external oscillator) while program execution is in progress, wait until
the target clock signal is stable.
5. Differences between Products
Before changing from one product to another, i.e. to one with a different part number, confirm
that the change will not lead to problems.
 The characteristics of MPU/MCU in the same group but having different part numbers may
differ because of the differences in internal memory capacity and layout pattern. When
changing to products of different part numbers, implement a system-evaluation test for
each of the products.
Notice
1.
All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas
Electronics products listed herein, please confirm the latest product information with a Renesas Electronics sales office. Also, please pay regular and careful attention to additional and different information to
be disclosed by Renesas Electronics such as that disclosed through our website.
2.
Renesas Electronics does not assume any liability for infringement of patents, copyrights, or other intellectual property rights of third parties by or arising from the use of Renesas Electronics products or
technical information described in this document. No license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property rights of Renesas Electronics or
others.
3.
You should not alter, modify, copy, or otherwise misappropriate any Renesas Electronics product, whether in whole or in part.
4.
Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples. You are fully responsible for
the incorporation of these circuits, software, and information in the design of your equipment. Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from the
use of these circuits, software, or information.
5.
When exporting the products or technology described in this document, you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and
regulations. You should not use Renesas Electronics products or the technology described in this document for any purpose relating to military applications or use by the military, including but not limited to
the development of weapons of mass destruction. Renesas Electronics products and technology may not be used for or incorporated into any products or systems whose manufacture, use, or sale is
prohibited under any applicable domestic or foreign laws or regulations.
6.
Renesas Electronics has used reasonable care in preparing the information included in this document, but Renesas Electronics does not warrant that such information is error free. Renesas Electronics
7.
Renesas Electronics products are classified according to the following three quality grades: "Standard", "High Quality", and "Specific". The recommended applications for each Renesas Electronics product
assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information included herein.
depends on the product's quality grade, as indicated below. You must check the quality grade of each Renesas Electronics product before using it in a particular application. You may not use any Renesas
Electronics product for any application categorized as "Specific" without the prior written consent of Renesas Electronics. Further, you may not use any Renesas Electronics product for any application for
which it is not intended without the prior written consent of Renesas Electronics. Renesas Electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the
use of any Renesas Electronics product for an application categorized as "Specific" or for which the product is not intended where you have failed to obtain the prior written consent of Renesas Electronics.
The quality grade of each Renesas Electronics product is "Standard" unless otherwise expressly specified in a Renesas Electronics data sheets or data books, etc.
"Standard":
Computers; office equipment; communications equipment; test and measurement equipment; audio and visual equipment; home electronic appliances; machine tools;
personal electronic equipment; and industrial robots.
"High Quality": Transportation equipment (automobiles, trains, ships, etc.); traffic control systems; anti-disaster systems; anti-crime systems; safety equipment; and medical equipment not specifically
designed for life support.
"Specific":
Aircraft; aerospace equipment; submersible repeaters; nuclear reactor control systems; medical equipment or systems for life support (e.g. artificial life support devices or systems), surgical
implantations, or healthcare intervention (e.g. excision, etc.), and any other applications or purposes that pose a direct threat to human life.
8.
You should use the Renesas Electronics products described in this document within the range specified by Renesas Electronics, especially with respect to the maximum rating, operating supply voltage
range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas Electronics shall have no liability for malfunctions or damages arising out of the
use of Renesas Electronics products beyond such specified ranges.
9.
Although Renesas Electronics endeavors to improve the quality and reliability of its products, semiconductor products have specific characteristics such as the occurrence of failure at a certain rate and
malfunctions under certain use conditions. Further, Renesas Electronics products are not subject to radiation resistance design. Please be sure to implement safety measures to guard them against the
possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas Electronics product, such as safety design for hardware and software including but not limited to
redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures. Because the evaluation of microcomputer software alone is very difficult,
please evaluate the safety of the final products or system manufactured by you.
10. Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility of each Renesas Electronics product. Please use Renesas Electronics
products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances, including without limitation, the EU RoHS Directive. Renesas Electronics assumes
no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations.
11. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written consent of Renesas Electronics.
12. Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electronics products, or if you have any other inquiries.
(Note 1)
"Renesas Electronics" as used in this document means Renesas Electronics Corporation and also includes its majority-owned subsidiaries.
(Note 2)
"Renesas Electronics product(s)" means any product developed or manufactured by or for Renesas Electronics.
http://www.renesas.com
SALES OFFICES
Refer to "http://www.renesas.com/" for the latest and detailed information.
Renesas Electronics America Inc.
2880 Scott Boulevard Santa Clara, CA 95050-2554, U.S.A.
Tel: +1-408-588-6000, Fax: +1-408-588-6130
Renesas Electronics Canada Limited
1101 Nicholson Road, Newmarket, Ontario L3Y 9C3, Canada
Tel: +1-905-898-5441, Fax: +1-905-898-3220
Renesas Electronics Europe Limited
Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K
Tel: +44-1628-585-100, Fax: +44-1628-585-900
Renesas Electronics Europe GmbH
Arcadiastrasse 10, 40472 Düsseldorf, Germany
Tel: +49-211-65030, Fax: +49-211-6503-1327
Renesas Electronics (China) Co., Ltd.
7th Floor, Quantum Plaza, No.27 ZhiChunLu Haidian District, Beijing 100083, P.R.China
Tel: +86-10-8235-1155, Fax: +86-10-8235-7679
Renesas Electronics (Shanghai) Co., Ltd.
Unit 204, 205, AZIA Center, No.1233 Lujiazui Ring Rd., Pudong District, Shanghai 200120, China
Tel: +86-21-5877-1818, Fax: +86-21-6887-7858 / -7898
Renesas Electronics Hong Kong Limited
Unit 1601-1613, 16/F., Tower 2, Grand Century Place, 193 Prince Edward Road West, Mongkok, Kowloon, Hong Kong
Tel: +852-2886-9318, Fax: +852 2886-9022/9044
Renesas Electronics Taiwan Co., Ltd.
7F, No. 363 Fu Shing North Road Taipei, Taiwan
Tel: +886-2-8175-9600, Fax: +886 2-8175-9670
Renesas Electronics Singapore Pte. Ltd.
1 harbourFront Avenue, #06-10, keppel Bay Tower, Singapore 098632
Tel: +65-6213-0200, Fax: +65-6278-8001
Renesas Electronics Malaysia Sdn.Bhd.
Unit 906, Block B, Menara Amcorp, Amcorp Trade Centre, No. 18, Jln Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, Malaysia
Tel: +60-3-7955-9390, Fax: +60-3-7955-9510
Renesas Electronics Korea Co., Ltd.
11F., Samik Lavied' or Bldg., 720-2 Yeoksam-Dong, Kangnam-Ku, Seoul 135-080, Korea
Tel: +82-2-558-3737, Fax: +82-2-558-5141
© 2010 Renesas Electronics Corporation. All rights reserved.
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