ILI9335 - NewHaven Display

ILI9335
a-Si TFT LCD Single Chip Driver
240RGBx320 Resolution and 262K color
Datasheet
Version: V0.19
Document No.: ILI9335DS_V0.19.pdf
ILI TECHNOLOGY CORP.
8F, No.38, Taiyuan St., Jhubei City, Hsinchu County 302,
Taiwan, R.O.C
Tel.886-3-5600099; Fax.886-3-5600055
http://www.ilitek.com
a-Si TFT LCD Single Chip Driver
240RGBx320 Resolution and 262K color
ILI9335
Table of Contents
Section
Page
1. Introduction.................................................................................................................................................... 7
2. Features ........................................................................................................................................................ 8
3. Block Diagram ............................................................................................................................................. 10
4. Pin Descriptions .......................................................................................................................................... 11
5. Pad Arrangement and Coordination............................................................................................................ 15
6. Block Description ........................................................................................................................................ 25
7. System Interface ......................................................................................................................................... 27
7.1.
Interface Specifications .................................................................................................................. 27
7.2.
Input Interfaces .............................................................................................................................. 28
7.2.1.
i80/18-bit System Interface.................................................................................................. 29
7.2.2.
i80/16-bit System Interface (DB[15:0]) ................................................................................ 30
7.2.3.
i80/16-bit System Interface (DB[17:10][8:1]) ....................................................................... 30
7.2.4.
i80/9-bit System Interface (DB[17:9]) .................................................................................. 31
7.2.5.
i80/8-bit System Interface (DB[17:10]) ................................................................................ 31
7.3.
Serial Peripheral Interface (SPI) .................................................................................................... 33
7.4.
VSYNC Interface............................................................................................................................ 37
7.5.
RGB Input Interface ....................................................................................................................... 41
7.6.
7.5.1.
RGB Interface...................................................................................................................... 42
7.5.2.
RGB Interface Timing .......................................................................................................... 43
7.5.3.
Moving Picture Mode........................................................................................................... 45
7.5.4.
6-bit RGB Interface.............................................................................................................. 46
7.5.5.
16-bit RGB Interface............................................................................................................ 47
7.5.6.
18-bit RGB Interface............................................................................................................ 47
Interface Timing.............................................................................................................................. 49
8. Register Descriptions .................................................................................................................................. 50
8.1.
Registers Access............................................................................................................................ 50
8.2.
Instruction Descriptions.................................................................................................................. 53
8.2.1.
Index (IR) ............................................................................................................................. 55
8.2.2.
ID code (R00h) .................................................................................................................... 55
8.2.3.
Driver Output Control (R01h)............................................................................................... 55
8.2.4.
LCD Driving Wave Control (R02h) ...................................................................................... 57
8.2.5.
Entry Mode (R03h) .............................................................................................................. 57
8.2.6.
16bits Data Format Selection (R05h) .................................................................................. 60
8.2.7.
Display Control 1 (R07h) ..................................................................................................... 61
8.2.8.
Display Control 2 (R08h) ..................................................................................................... 62
8.2.9.
Display Control 3 (R09h) ..................................................................................................... 63
8.2.10. Display Control 4 (R0Ah)..................................................................................................... 64
The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed,
reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp.
Page 2 of 113
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240RGBx320 Resolution and 262K color
ILI9335
8.2.11. RGB Display Interface Control 1 (R0Ch)............................................................................. 64
8.2.12. Frame Marker Position (R0Dh)............................................................................................ 65
8.2.13. RGB Display Interface Control 2 (R0Fh) ............................................................................. 66
8.2.14. Power Control 1 (R10h)....................................................................................................... 66
8.2.15. Power Control 2 (R11h) ....................................................................................................... 68
8.2.16. Power Control 3 (R12h)....................................................................................................... 69
8.2.17. Power Control 4 (R13h)....................................................................................................... 70
8.2.18. GRAM Horizontal/Vertical Address Set (R20h, R21h) ........................................................ 70
8.2.19. Write Data to GRAM (R22h)................................................................................................ 71
8.2.20. Read Data from GRAM (R22h) ........................................................................................... 71
8.2.21. Power Control 7 (R29h)....................................................................................................... 73
8.2.22. Frame Rate and Color Control (R2Bh)................................................................................ 73
8.2.23. Gamma Control (R30h ~ R3Dh).......................................................................................... 74
8.2.24. Horizontal and Vertical RAM Address Position (R50h, R51h, R52h, R53h) ....................... 74
8.2.25. Gate Scan Control (R60h, R61h, R6Ah) ............................................................................. 76
8.2.26. Partial Image 1 Display Position (R80h).............................................................................. 78
8.2.27. Partial Image 1 RAM Start/End Address (R81h, R82h)....................................................... 78
8.2.28. Partial Image 2 Display Position (R83h).............................................................................. 78
8.2.29. Partial Image 2 RAM Start/End Address (R84h, R85h)....................................................... 78
8.2.30. Panel Interface Control 1 (R90h)......................................................................................... 79
8.2.31. Panel Interface Control 2 (R92h)......................................................................................... 79
8.2.32. Panel Interface Control 4 (R95h)......................................................................................... 80
8.2.33. Panel Interface Control 5 (R97h)......................................................................................... 80
8.2.34. OTP VCM Programming Control (RA1h) ............................................................................ 81
8.2.35. OTP VCM Status and Enable (RA2h).................................................................................. 81
8.2.36. OTP Programming ID Key (RA5h) ...................................................................................... 81
8.2.37. Deep stand by control (RE6h) ............................................................................................. 82
9. OTP Programming Flow.............................................................................................................................. 84
10. GRAM Address Map & Read/Write ............................................................................................................. 85
11. Window Address Function........................................................................................................................... 90
12. Gamma Correction ...................................................................................................................................... 91
13. Application................................................................................................................................................... 99
13.1. Configuration of Power Supply Circuit ........................................................................................... 99
13.2. Display ON/OFF Sequence.......................................................................................................... 101
13.3. Standby and Sleep Mode ............................................................................................................. 102
13.4. Power Supply Configuration......................................................................................................... 103
13.5. Voltage Generation ...................................................................................................................... 104
13.6. Applied Voltage to the TFT panel ................................................................................................. 105
13.7. Partial Display Function ............................................................................................................... 105
The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed,
reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp.
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240RGBx320 Resolution and 262K color
ILI9335
14. Electrical Characteristics........................................................................................................................... 107
14.1. Absolute Maximum Ratings ......................................................................................................... 107
14.2. DC Characteristics ....................................................................................................................... 108
14.3. Reset Timing Characteristics ....................................................................................................... 108
14.4. AC Characteristics ....................................................................................................................... 109
14.4.1. i80-System Interface Timing Characteristics ..................................................................... 109
14.4.2. Serial Data Transfer Interface Timing Characteristics ....................................................... 110
14.4.3. RGB Interface Timing Characteristics ................................................................................111
14.4.4. Vcom Driving ..................................................................................................................... 112
15. Revision History ........................................................................................................................................ 113
The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed,
reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp.
Page 4 of 113
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240RGBx320 Resolution and 262K color
ILI9335
Figures
FIGURE1 SYSTEM INTERFACE AND RGB INTERFACE CONNECTION .................................................................................... 28
FIGURE2 18-BIT SYSTEM INTERFACE DATA FORMAT ......................................................................................................... 29
FIGURE3 16-BIT SYSTEM INTERFACE DATA FORMAT ......................................................................................................... 30
FIGURE4 9-BIT SYSTEM INTERFACE DATA FORMAT ........................................................................................................... 31
FIGURE 6 DATA FORMAT OF SPI INTERFACE ..................................................................................................................... 34
FIGURE7 DATA TRANSMISSION THROUGH SERIAL PERIPHERAL INTERFACE (SPI) ............................................................... 35
FIGURE8 DATA TRANSMISSION THROUGH SERIAL PERIPHERAL INTERFACE (SPI), TRI=”1” AND DFM=”10”).................... 36
FIGURE9 DATA TRANSMISSION THROUGH VSYNC INTERFACE)......................................................................................... 37
FIGURE10 MOVING PICTURE DATA TRANSMISSION THROUGH VSYNC INTERFACE ............................................................ 37
FIGURE11 OPERATION THROUGH VSYNC INTERFACE....................................................................................................... 38
FIGURE13 RGB INTERFACE DATA FORMAT ...................................................................................................................... 41
FIGURE14 GRAM ACCESS AREA BY RGB INTERFACE ..................................................................................................... 42
FIGURE15 TIMING CHART OF SIGNALS IN 18-/16-BIT RGB INTERFACE MODE .................................................................. 43
FIGURE16 TIMING CHART OF SIGNALS IN 6-BIT RGB INTERFACE MODE ............................................................................ 44
FIGURE17 EXAMPLE OF UPDATE THE STILL AND MOVING PICTURE .................................................................................... 45
FIGURE18 INTERNAL CLOCK OPERATION/RGB INTERFACE MODE SWITCHING ................................................................... 48
FIGURE20 RELATIONSHIP BETWEEN RGB I/F SIGNALS AND LCD DRIVING SIGNALS FOR PANEL ..................................... 49
FIGURE21 REGISTER SETTING WITH SERIAL PERIPHERAL INTERFACE (SPI)...................................................................... 50
FIGURE22 REGISTER SETTING WITH I80 SYSTEM INTERFACE ............................................................................................ 51
FIGURE 23 REGISTER READ/WRITE TIMING OF I80 SYSTEM INTERFACE ........................................................................... 52
FIGURE24 GRAM ACCESS DIRECTION SETTING ............................................................................................................... 57
FIGURE26 8-BIT MPU SYSTEM INTERFACE DATA FORMAT............................................................................................... 59
FIGURE 27 DATA READ FROM GRAM THROUGH READ DATA REGISTER IN 18-/16-/9-/8-BIT INTERFACE MODE .............. 71
FIGURE 28 GRAM DATA READ BACK FLOW CHART ........................................................................................................ 72
FIGURE 29 GRAM ACCESS RANGE CONFIGURATION ........................................................................................................ 75
FIGURE30 GRAM READ/WRITE TIMING OF I80-SYSTEM INTERFACE ............................................................................... 85
FIGURE31 I80-SYSTEM INTERFACE WITH 18-/16-/9-BIT DATA BUS (SS=”0”, BGR=”0”) ................................................. 87
FIGURE32 I80-SYSTEM INTERFACE WITH 8-BIT DATA BUS (SS=”0”, BGR=”0”) .............................................................. 88
FIGURE 33 I80-SYSTEM INTERFACE WITH 18-/9-BIT DATA BUS (SS=”1”, BGR=”1”) ....................................................... 89
FIGURE 34 GRAM ACCESS WINDOW MAP ....................................................................................................................... 90
FIGURE 35 GRAYSCALE VOLTAGE GENERATION ............................................................................................................... 91
FIGURE 36 GRAYSCALE VOLTAGE ADJUSTMENT .............................................................................................................. 92
FIGURE 37 GAMMA CURVE ADJUSTMENT ......................................................................................................................... 93
FIGURE 38 EXAMPLE OF RMP(N)0~5 DEFINITION ............................................................................................................. 95
FIGURE 39 RELATIONSHIP BETWEEN SOURCE OUTPUT AND VCOM ................................................................................. 98
FIGURE 40 RELATIONSHIP BETWEEN GRAM DATA AND OUTPUT LEVEL.......................................................................... 98
FIGURE 41 POWER SUPPLY CIRCUIT BLOCK ...................................................................................................................... 99
FIGURE 42 DISPLAY ON/OFF REGISTER SETTING SEQUENCE .......................................................................................... 101
The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed,
reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp.
Page 5 of 113
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a-Si TFT LCD Single Chip Driver
240RGBx320 Resolution and 262K color
ILI9335
FIGURE 43 STANDBY/SLEEP MODE REGISTER SETTING SEQUENCE ........................................................................... 102
FIGURE 44 POWER SUPPLY ON/OFF SEQUENCE ............................................................................................................. 103
FIGURE 45 VOLTAGE CONFIGURATION DIAGRAM ........................................................................................................... 104
FIGURE 46 VOLTAGE OUTPUT TO TFT LCD PANEL ........................................................................................................ 105
FIGURE 47 PARTIAL DISPLAY EXAMPLE .......................................................................................................................... 106
FIGURE 48 I80-SYSTEM BUS TIMING ............................................................................................................................... 109
FIGURE50 RGB INTERFACE TIMING ................................................................................................................................ 111
The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed,
reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp.
Page 6 of 113
Version: 0.19
a-Si TFT LCD Single Chip Driver
240RGBx320 Resolution and 262K color
ILI9335
1. Introduction
ILI9335 is a 262,144-color one-chip SoC driver for a-TFT liquid crystal display with resolution of 240RGBx320
dots, comprising a 720-channel source driver, a 320-channel gate driver, 172,800 bytes RAM for graphic data
of 240RGBx320 dots, and power supply circuit.
ILI9335 has four kinds of system interfaces which are i80-system MPU interface (8-/9-/16-/18-bit bus width),
VSYNC interface (system interface + VSYNC, internal clock, DB[17:0]), serial data transfer interface (SPI),
RGB 6-/16-/18-bit interface (DOTCLK, VSYNC, HSYNC, ENABLE, DB[17:0]).
In RGB interface and VSYNC interface mode, the combined use of high-speed RAM write function and widow
address function enables to display a moving picture at a position specified by a user and still pictures in other
areas on the screen simultaneously, which makes it possible to transfer display the refresh data only to
minimize data transfers and power consumption.
ILI9335 can operate with 1.65V I/O interface voltage, and an incorporated voltage follower circuit to generate
voltage levels for driving an LCD. The ILI9335 also supports a function to display in 8 colors and a sleep mode,
allowing for precise power control by software and these features make the ILI9335 an ideal LCD driver for
medium or small size portable products such as digital cellular phones, smart phone, PDA and PMP where
long battery life is a major concern.
The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed,
reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp.
Page 7 of 113
Version: 0.19
a-Si TFT LCD Single Chip Driver
240RGBx320 Resolution and 262K color
ILI9335
2. Features
Single chip solution for a liquid crystal QVGA TFT LCD display
240RGBx320-dot resolution capable with real 262,144 display color
Support MVA (Multi-domain Vertical Alignment) wide view display
Incorporate 720-channel source driver and 320-channel gate driver
Internal 172,800 bytes graphic RAM
System interfaces
i80 system interface with 8-/ 9-/16-/18-bit bus width
Serial Peripheral Interface (SPI)
RGB interface with 6-/16-/18-bit bus width (VSYNC, HSYNC, DOTCLK, ENABLE, DB[17:0])
VSYNC interface (System interface + VSYNC)
Internal oscillator and hardware reset
Reversible source/gate driver shift direction
Window address function to specify a rectangular area for internal GRAM access
Bit operation function for facilitating graphics data processing
Bit-unit write data mask function
Pixel-unit logical/conditional write function
Abundant functions for color display control
γ-correction function enabling display in 262,144 colors
Line-unit vertical scrolling function
Partial drive function, enabling partially driving an LCD panel at positions specified by user
Incorporate step-up circuits for stepping up a liquid crystal drive voltage level up to 6 times (x6)
Power saving functions
8-color mode
standby mode
sleep mode
deep stand by mode
Low -power consumption architecture
Low operating power supplies:
IOVcc = 1.65V ~ 3.6 V (interface I/O)
VCI = 2.5V ~ 3.6 V (analog)
LCD Voltage drive:
Source/VCOM power supply voltage
DDVDH - GND = 4.5V ~ 6.0
VCL – GND = -2.0V ~ -3.0V
VCI – VCL
≦ 6.0V
Gate driver output voltage
VGH - GND = 10V ~ 20V
VGL – GND = -5V ~ -15V
The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed,
reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp.
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a-Si TFT LCD Single Chip Driver
240RGBx320 Resolution and 262K color
VGH – VGL
ILI9335
≦ 30V
VCOM driver output voltage
VCOMH = (VCI+0.2)V ~ (DDVDH-0.2)V
VCOML = (VCL+0.2)V ~ 0V
VCOMH-VCOML
≦ 6.0V
a-TFT LCD storage capacitor: Cst only
The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed,
reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp.
Page 9 of 113
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a-Si TFT LCD Single Chip Driver
240RGBx320 Resolution and 262K color
ILI9335
3. Block Diagram
Index
Register
(IR)
IOVCC
IM[3:0]
nRESET
nCS
n WR/SCL
nRD
RS
SDI
SDO
DB[1 7:0]
HSYNC
VSYNC
DOTCLK
ENABLE
TEST1
TEST2
MPU I/F
18-bit
16-bit
9-bit
8-bit
SPI I/F
RGB I/F
18-bit
16-bit
6-bit
VSYNC I/F
7
18
18
Control
Register
(CR)
Address
Counter
(AC)
Graphics
Operation
LCD
Source
Driver
18
V63 ~ 0
18
TEST3
Read
Latch
TS[8:0]
Write
Latch
18
Grayscale
Reference
Voltage
18
Graphics RAM
(GRAM)
VCC
VDDD
GND
S[72 0:1]
VREG1OUT
VGS
DUMMY20~27
Regulator
RC-OSC.
LCD
Gate
Driver
Timing
Controller
G[ 320:1]
DUMMY1~ 15
VCI
VCI1
VCOM
Generator
Charge-pump Power Circuit
GND
B
1A
1 11C
C
H A
B 3 3B
D 12 21 A
V C C 1C 1C
D
D
L
C
V
A
12
C
B
12
C
A
22
C
B
L
22 H
G G
C V V
H
M
O
C
V
VCOM
L
M
O
C
V
The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed,
reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp.
Page 10 of 113
Version: 0.19
a-Si TFT LCD Single Chip Driver
240RGBx320 Resolution and 262K color
ILI9335
4. Pin Descriptions
Pin Name
I/O
Type
Descriptions
Input Interface
Select the MPU system interface mode
IM3,
IM2,
IM1,
IM0/ID
I
IOVcc
IM3
IM2
IM1
IM0
MPU-Interface Mode
DB Pin in use
0
0
0
0
Setting invalid
0
0
0
1
Setting invalid
0
0
1
0
i80-system 16-bit interface
0
0
1
1
i80-system 8-bit interface
DB[17:10]
0
1
0
ID
Serial Peripheral Interface (SPI)
SDI, SDO
0
1
1
*
Setting invalid
1
0
0
0
Setting invalid
1
0
0
1
i80-system 16-bit interface
DB[15:0]
1
0
1
0
i80-system 18-bit interface
DB[17:0]
1
0
1
1
i80-system 9-bit interface
DB[17:9]
1
1
*
*
Setting invalid
DB[17:10], DB[8:1]
When the serial peripheral interface is selected, IM0 pin is used for the device code ID
setting.
I
MPU
IOVcc
A chip select signal.
Low: the ILI9335 is selected and accessible
High: the ILI9335 is not selected and not accessible
Fix to the GND level when not in use.
I
MPU
IOVcc
A register select signal.
Low: select an index or status register
High: select a control register
Fix to either IOVcc or GND level when not in use.
nWR/SCL
I
MPU
IOVcc
A write strobe signal and enables an operation to write data when the signal is low.
Fix to either IOVcc or GND level when not in use.
SPI Mode:
Synchronizing clock signal in SPI mode.
nRD
I
MPU
IOVcc
A read strobe signal and enables an operation to read out data when the signal is low.
Fix to either IOVcc or GND level when not in use.
nRESET
I
MPU
IOVcc
A reset pin.
Initializes the ILI9335 with a low input. Be sure to execute a power-on reset after
supplying power.
SDI
I
MPU
IOVcc
SPI interface input pin.
The data is latched on the rising edge of the SCL signal.
SDO
O
MPU
IOVcc
SPI interface output pin.
The data is outputted on the falling edge of the SCL signal.
Let SDO as floating when not used.
nCS
RS
DB[17:0]
ENABLE
I/O
MPU
IOVcc
I
MPU
IOVcc
An 18-bit parallel bi-directional data bus for MPU system interface mode
8-bit I/F: DB[17:10] is used.
9-bit I/F: DB[17:9] is used.
16-bit I/F: DB[17:10] and DB[8:1] is used.
18-bit I/F: DB[17:0] is used.
18-bit parallel bi-directional data bus for RGB interface operation
6-bit RGB I/F: DB[17:12] are used.
16-bit RGB I/F: DB[17:13] and DB[11:1] are used.
18-bit RGB I/F: DB[17:0] are used.
Unused pins must be fixed to GND level.
Data ENEABLE signal for RGB interface operation.
Low: Select (access enabled)
The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed,
reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp.
Page 11 of 113
Version: 0.19
a-Si TFT LCD Single Chip Driver
240RGBx320 Resolution and 262K color
Pin Name
I/O
Type
ILI9335
Descriptions
High: Not select (access inhibited)
The EPL bit inverts the polarity of the ENABLE signal.
Fix to either IOVcc or GND level when not in use.
I
MPU
IOVcc
Dot clock signal for RGB interface operation.
DPL = “0”: Input data on the rising edge of DOTCLK
DPL = “1”: Input data on the falling edge of DOTCLK
Fix to the GND level when not in use
I
MPU
IOVcc
Frame synchronizing signal for RGB interface operation.
VSPL = “0”: Active low.
VSPL = “1”: Active high.
Fix to the GND level when not in use.
HSYNC
I
MPU
IOVcc
Line synchronizing signal for RGB interface operation.
HSPL = “0”: Active low.
HSPL = “1”: Active high.
Fix to the GND level when not in use
FMARK
O
MPU
IOVcc
Output a frame head pulse signal.
The FMARK signal is used when writing RAM data in synchronization with frame. Leave
the pin open when not in use.
DOTCLK
VSYNC
LCD Driving signals
S720~S1
O
LCD
Source output voltage signals applied to liquid crystal.
To change the shift direction of signal outputs, use the SS bit.
SS = “0”, the data in the RAM address “h00000” is output from S1.
SS = “1”, the data in the RAM address “h00000” is output from S720. S1, S4, S7, …
display red (R), S2, S5, S8, ... display green (G), and S3, S6, S9, ... display blue (B) (SS
= 0).
G320~G1
O
LCD
Gate line output signals.
VGH: the level selecting gate lines
VGL: the level not selecting gate lines
VCOM
O
TFT common
electrode
VCOMH
O
Stabilizing
capacitor
The high level of VCOM AC voltage.
VCOML
O
Stabilizing
capacitor
The low level of VCOM AC voltage.
Connect to a stabilizing capacitor.
VGS
I
GND or
external
resistor
A supply voltage to the common electrode of TFT panel.
VCOM is AC voltage alternating signal between the VCOMH and VCOML levels.
Connect to a stabilizing capacitor.
Adjust the VCOML level with the VDV bits.
Reference level for the grayscale voltage generating circuit. The VGS level can be
changed by connecting to an external resistor.
Charge-pump and Regulator Circuit
VCI
I
Power
supply
A supply voltage to the analog circuit.
3.6V.
Connect to an external power supply of 2.5 ~
VCC
I
Power
supply
A supply voltage to the digital circuit.
3.6V.
Connect to an external power supply of 2.5 ~
VCI1
O
Stabilizing
capacitor
An internal reference voltage for the step-up circuit1.
The amplitude between VCI and GND is determined by the VC[2:0] bits.
Make sure to set the VCI1 voltage so that the DDVDH, VGH and VGL voltages are set
within the respective specification.
DDVDH
O
Stabilizing
capacitor
Power supply for the source driver and Vcom drive.
VGH
O
Stabilizing
capacitor
Power supply for the gate driver.
VGL
O
Stabilizing
capacitor
Power supply for the gate driver.
VCL
O
Stabilizing
capacitor
C11A, C11B
I/O
Step-up
VCOML driver power supply.
VCL = 0.5 ~ –VCI . Place a stabilizing capacitor between GND
Capacitor connection pins for the step-up circuit 1.
The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed,
reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp.
Page 12 of 113
Version: 0.19
a-Si TFT LCD Single Chip Driver
240RGBx320 Resolution and 262K color
Pin Name
I/O
C12A, C12B
Type
ILI9335
Descriptions
capacitor
C13A, C13B
C21A, C21B
C22A, C22B
I/O
Step-up
capacitor
Capacitor connection pins for the step-up circuit 2.
Output voltage generated from the reference voltage.
VREG1OUT
I/O
Stabilizing
capacitor
The voltage level is set with the VRH bits.
VREG1OUT is (1) a source driver grayscale reference voltage, (2) VcomH level
reference voltage, and (3) Vcom amplitude reference voltage. Connect to a stabilizing
capacitor. VREG1OUT = 3.0 ~ (DDVDH – 0.5)V.
Power Pads
IOVCC
I
Power
supply
A supply voltage to the interface pins:
IM[3:0], nRESET, nCS, nWR, nRD, RS, DB[17:0], VSYNC, HSYNC, DOTCLK,
ENABLE, SCL, SDI, SDO.
IOVcc = 1.65 ~ 3.6V. In case of COG, connect to Vcc on the FPC if IOVcc=Vcc, to
prevent noise.
VDD
O
Power
Digital circuit power pad.
Connect these pins with the 1uF capacitor.
DGND
I
Power
supply
DGND for the digital side: DGND = 0V.
to prevent noise.
AGND
I
Power
supply
AGND for the analog side: AGND = 0V. In case of COG, connect to GND on the FPC
to prevent noise.
VGMMA1, 62
O
-
VGLDMY1~4
O
Unused gate
lines
In case of COG, connect to GND on the FPC
Test pad.
Leave these pins as open
Connect unused gate lines to fix the level at VGL
Test Pads
DUMMY3,
31.
5~27,30,
-
-
Dummy pad.
Leave these pins as open
DUMMYR1,2, 28, 29.
-
-
Short circuited within the chip for COG contact resistance measurement. DUMMYR
pins are short circuited as below:
DUMMYR1 and DUMMYR29
DUMMYR2 and DUMMYR28
DUMMY
-
-
Dummy pad and no output (no gold bump)
IOVCCDUM
O
AGNDDUM1~6
O
-
DGNDDUM1~7
O
-
TESTO1~16
O
Open
Connect unused interface and test pins to these pins on the glass to fix voltage
levels. Leave open when not used.
Test pins. Leave them open.
TEST1, 2, 3
I
IOGND
Test pins (internal pull low).
Connect to GND or leave these pins as open.
TS0~8
I
OPEN
Test pins (internal pull low). Leave them open.
TSO
O
OPEN
Test pins. Leave it open or short to ground.
TEST_EN
I
OPEN
Test pins. Leave it open or short to ground.
The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed,
reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp.
Page 13 of 113
Version: 0.19
a-Si TFT LCD Single Chip Driver
240RGBx320 Resolution and 262K color
ILI9335
Liquid crystal power supply specifications Table 1
No.
Item
Description
1
TFT Source Driver
720 pins (240 x RGB)
2
TFT Gate Driver
320 pins
3
TFT Display’s Capacitor Structure
Cst structure only (Common VCOM)
4
Liquid Crystal Drive Output
S1 ~ S720
5
6
7
Input Voltage
Liquid Crystal Drive Voltages
Internal Step-up Circuits
V0 ~ V63 grayscales
G1 ~ G320
VGH - VGL
VCOM
VCOMH - VCOML: Amplitude = electronic volumes
IOVcc
1.65 ~ 3.60V
VCI
2.50 ~ 3.60V
DDVDH
4.5V ~ 6.0V
VGH
10V ~ 20V
VGL
-5V ~ -15V
VCL
-1.9V ~ -3.0V
VGH - VGL
Max. 30V
VCI - VCL
Max. 6.0V
DDVDH
VCI1 x2
VGH
VCI1 x4, x5, x6
VGL
VCI1 x-3, x-4, x-5
VCL
VCI1 x-1
The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed,
reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp.
Page 14 of 113
Version: 0.19
a-Si TFT LCD Single Chip Driver
240RGBx320 Resolution and 262K color
ILI9335
5. Pad Arrangement and Coordination
Chip Size: 18800 um x 680 um
Au Bump Size:
.…
……
……
……
…
6
0
7
0
8
0
1
0
0
1
1
0
1
2
0
ILI9335
Face Up
(Bum p View)
9
0
S35 8
S35 9
S36 0
VGM M A1
y
1
3
0
(0,0)
VGM M A62
S36 1
S36 2
S36 3
1
4
0
x
1
5
0
1
6
0
1
7
0
1
8
0
1
9
0
.…
……
……
……
…
2
0
0
2
1
0
2
2
0
2
3
0
2
4
0
2
5
0
Bum p View
DUM M Y26
DUM M Y25
S1
S2
S3
S4
5
0
2. 50um x 80um
Input Pads
G 31 6
G 34 8
G 32 0
VGL DM Y 3
DUM M Y27
4
0
1. 16um x 94um
Output to panel
DUM M Y31
DUM M Y30
DUM M YR2 9
DUM M YR2 8
VGL DM Y4
G2
G4
G6
G8
3
0
Au bump height: 12um (typ.)
2
0
Coordinate Origin: Chip center
……
……
1
0
Pad Location: Pad Center.
S71 7
S71 8
S71 9
S72 0
DUM M Y24
DUM M Y23
DUM M Y22
VGL DM Y2
G31 9
G31 7
G31 5
……
……
G7
G5
G3
G1
VGL DM Y1
DUM M Y21
DUM M Y20
DUM M Y19
DUM M Y18
2
6
0
DGNDDUM
1
DUMMYR1
DUMMYR2
TESTO
1
TESTO
2
TESTO
3
TESTO
4
TESTO
5
TESTO
6
TESTO
7
TESTO
8
LEDPWM
LEDPWM
TESTO9
TESTO
10
TESTO
11
TESTO
12
DGND
DGND
DGND
DGND
DGND
DGND
DGND
DGND
DGND
DGND
TESTO13
TESTO14
DGNDDUM2
IM0 /I D
IM1
IM2
IM3
IOVCCDUM
TESTO
15
TESTO
16
TEST3
TEST2
TEST1
DGNDDUM3
FMARK
VSYNC
HSYNC
DOTCLK
ENABLE
TEST_EN
DB[17]
DB[16]
DB[15]
TS[8]
TS[7]
DB[14]
DB[13]
DB[12]
TS[6]
TS[5]
DB[11]
DB[10]
DB[9]
IOVCC
IOVCC
IOVCC
IOVCC
IOVCC
IOVCC
IOVCC
IOVCC
DB[8]
DB[7]
DB[6]
TS[4 ]
TS[3 ]
DB[5 ]
DB[4 ]
DB[3 ]
TS[2 ]
TS[1 ]
DB[2 ]
DB[1 ]
DB[0 ]
TS[0 ]
TSO
DGNDDUM5
nCS
RS
nWR/SCL
nRD
nRESET
SDO
SDI
DGNDDUM6
DUMMY5
DUMMY6
DUMMY7
DUMMY8
DUMMY9
DGNDDUM7
VCC
VCC
VCC
VCC
VCC
VCC
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
DGND
DGND
DGND
DGND
DGND
DGND
DGND
DGND
VGS
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
VCOMH
VCOMH
VCOMH
VCOMH
VCOMH
VCOMH
VCOM
VCOM
VCOM
VCOM
VCOM
VCOM
VCOML
VCOML
VCOML
VCOML
VCOML
VCOML
VCOML
C11A
C11A
C11A
C11A
C11A
C11B
C11B
C11B
C11B
C11B
C12B
C12B
C12B
C12B
C12B
C12A
C12A
C12A
C12A
C12A
DDVDH
DDVDH
DDVDH
DDVDH
DDVDH
DDVDH
DDVDH
DDVDH
DDVDH
DDVDH
DUMMY10
VREG1OUT
DUMMY11
DUMMY12
AGNDDUM1
AGNDDUM2
VCI1
VCI1
VCI1
VCI1
VCI1
VCI1
VCI1
VCI1
VCI
VCI
VCI
VCI
VCI
VCI
VCI
VCI
VCI
AGNDDUM3
VGH
VGH
VGH
VGH
VGH
VGH
AGNDDUM4
VGL
VGL
VGL
VGL
VGL
VGL
VGL
VGL
VGL
VGL
AGNDDUM5
VCL
VCL
VCL
VCL
C13B
C13B
C13B
C13B
C13A
C13A
C13A
C13A
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
C21B
C21B
C21B
C21A
C21A
C21A
C22B
C22B
C22B
C22A
C22A
C22A
DUMMY 13
DUMMY 14
DUMMY 15
DUMMY 16
DUMMY 17
AGNDDUM6
1
Chip thickness : 280 um (typ.)
The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed,
reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp.
Page 15 of 113
Version: 0.19
a-Si TFT LCD Single Chip Driver
240RGBx320 Resolution and 262K color
NO.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
Pad Name
DGNDDUM1
DUMMYR1
DUMMYR2
TESTO[1]
TESTO[2]
TESTO[3]
TESTO[4]
TESTO[5]
TESTO[6]
TESTO[7]
TESTO[8]
DUMMY
DUMMY
TESTO[9]
TESTO[10]
TESTO[11]
TESTO[12]
DGND
DGND
DGND
DGND
DGND
DGND
DGND
DGND
DGND
DGND
TESTO[13]
TESTO[14]
DGNDDUM2
IM0/ID
IM1
IM2
IM3
IOVCCDUM
TESTO[15]
TESTO[16]
TEST3
TEST2
TEST1
DGNDDUM3
FMARK
VSYNC
HSYNC
DOTCLK
ENABLE
TEST_EN
DB[17]
DB[16]
DB[15]
TS[8]
TS[7]
DB[14]
DB[13]
DB[12]
TS[6]
TS[5]
DB[11]
DB[10]
DB[9]
X
-9065
-8995
-8925
-8855
-8785
-8715
-8645
-8575
-8505
-8435
-8365
-8295
-8225
-8155
-8085
-8015
-7945
-7875
-7805
-7735
-7665
-7595
-7525
-7455
-7385
-7315
-7245
-7175
-7105
-7035
-6965
-6895
-6825
-6755
-6685
-6615
-6545
-6475
-6405
-6335
-6265
-6195
-6125
-6055
-5985
-5915
-5845
-5775
-5705
-5635
-5565
-5495
-5425
-5355
-5285
-5215
-5145
-5075
-5005
-4935
Y
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
NO.
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
Pad Name
IOVCC
IOVCC
IOVCC
IOVCC
IOVCC
IOVCC
IOVCC
IOVCC
DB[8]
DB[7]
DB[6]
TS[4]
TS[3]
DB[5]
DB[4]
DB[3]
TS[2]
TS[1]
DB[2]
DB[1]
DB[0]
TS[0]
TSO
DGNDDUM5
nCS
RS
nWR/SCL
nRD
nRESET
SDO
SDI
DGNDDUM6
DUMMY5
DUMMY6
DUMMY7
DUMMY8
DUMMY9
DGNDDUM7
VCC
VCC
VCC
VCC
VCC
VCC
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
DGND
DGND
DGND
DGND
DGND
DGND
DGND
DGND
X
-4865
-4795
-4725
-4655
-4585
-4515
-4445
-4375
-4305
-4235
-4165
-4095
-4025
-3955
-3885
-3815
-3745
-3675
-3605
-3535
-3465
-3395
-3325
-3255
-3185
-3115
-3045
-2975
-2905
-2835
-2765
-2695
-2625
-2555
-2485
-2415
-2345
-2275
-2205
-2135
-2065
-1995
-1925
-1855
-1785
-1715
-1645
-1575
-1505
-1435
-1365
-1295
-1225
-1155
-1085
-1015
-945
-875
-805
-735
Y
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
ILI9335
NO.
121
122
123
124
125
126
127
128
129
120
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
120
167
168
169
170
171
172
173
174
175
176
177
178
179
180
Pad Name
VGS
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
VCOMH
VCOMH
VCOMH
VCOMH
VCOMH
VCOMH
VCOM
VCOM
VCOM
VCOM
VCOM
VCOM
VCOML
VCOML
VCOML
VCOML
VCOML
VCOML
VCOML
C11A
C11A
C11A
C11A
C11A
C11B
C11B
C11B
C11B
C11B
C12B
C12B
C12B
C12B
C12B
C12A
C12A
C12A
C12A
C12A
DDVDH
DDVDH
DDVDH
DDVDH
DDVDH
DDVDH
DDVDH
DDVDH
DDVDH
DDVDH
DUMMY10
VREG1OUT
X
-665
-595
-525
-455
-385
-315
-245
-175
-105
-35
35
105
175
245
315
385
455
525
595
665
735
805
875
945
1015
1085
1155
1225
1295
1365
1435
1505
1575
1645
1715
1785
1855
1925
1995
2065
2135
2205
2275
2345
2415
2485
2555
2625
2695
2765
2835
2905
2975
3045
3115
3185
3255
3325
3395
3465
Y
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed,
reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp.
Page 16 of 113
Version: 0.19
a-Si TFT LCD Single Chip Driver
240RGBx320 Resolution and 262K color
NO.
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
Pad Name
DUMMY11
DUMMY12
AGNDDUM1
AGNDDUM2
VCI1
VCI1
VCI1
VCI1
VCI1
VCI1
VCI1
VCI1
VCI
VCI
VCI
VCI
VCI
VCI
VCI
VCI
VCI
AGNDDUM3
VGH
VGH
VGH
VGH
VGH
VGH
AGNDDUM4
VGL
VGL
VGL
VGL
VGL
VGL
VGL
VGL
VGL
VGL
AGNDDUM5
VCL
VCL
VCL
VCL
C13B
C13B
C13B
C13B
C13A
C13A
C13A
C13A
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
X
3535
3605
3675
3745
3815
3885
3955
4025
4095
4165
4235
4305
4375
4445
4515
4585
4655
4725
4795
4865
4935
5005
5075
5145
5215
5285
5355
5425
5495
5565
5635
5705
5775
5845
5915
5985
6055
6125
6195
6265
6335
6405
6475
6545
6615
6685
6755
6825
6895
6965
7035
7105
7175
7245
7315
7385
7455
7525
7595
7665
Y
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
NO.
241
242
233
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
233
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
Pad Name
AGND
AGND
C21B
C21B
C21B
C21A
C21A
C21A
C22B
C22B
C22B
C22A
C22A
C22A
DUMMY13
DUMMY14
DUMMY15
DUMMY16
DUMMY17
AGNDDUM6
DUMMY18
DUMMY19
DUMMY20
DUMMY21
VGLDMY1
G[1]
G[3]
G[5]
G[7]
G[9]
G[11]
G[13]
G[15]
G[17]
G[19]
G[21]
G[23]
G[25]
G[27]
G[29]
G[31]
G[33]
G[35]
G[37]
G[39]
G[41]
G[43]
G[45]
G[47]
G[49]
G[51]
G[53]
G[55]
G[57]
G[59]
G[61]
G[63]
G[65]
G[67]
G[69]
X
7735
7805
7875
7945
8015
8085
8155
8225
8295
8365
8435
8505
8575
8645
8715
8785
8855
8925
8995
9065
9216
9200
9184
9168
9152
9136
9120
9104
9088
9072
9056
9040
9024
9008
8992
8976
8960
8944
8928
8912
8896
8880
8864
8848
8832
8816
8800
8784
8768
8752
8736
8720
8704
8688
8672
8656
8640
8624
8608
8592
Y
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
-239
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
NO.
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
ILI9335
Pad Name
G[71]
G[73]
G[75]
G[77]
G[79]
G[81]
G[83]
G[85]
G[87]
G[89]
G[91]
G[93]
G[95]
G[97]
G[99]
G[101]
G[103]
G[105]
G[107]
G[109]
G[111]
G[113]
G[115]
G[117]
G[119]
G[121]
G[123]
G[125]
G[127]
G[129]
G[131]
G[133]
G[135]
G[137]
G[139]
G[141]
G[143]
G[145]
G[147]
G[149]
G[151]
G[153]
G[155]
G[157]
G[159]
G[161]
G[163]
G[165]
G[167]
G[169]
G[171]
G[173]
G[175]
G[177]
G[179]
G[181]
G[183]
G[185]
G[187]
G[189]
X
8576
8560
8544
8528
8512
8496
8480
8464
8448
8432
8416
8400
8384
8368
8352
8336
8320
8304
8288
8272
8256
8240
8224
8208
8192
8176
8160
8144
8128
8112
8096
8080
8064
8048
8032
8016
8000
7984
7968
7952
7936
7920
7904
7888
7872
7856
7840
7824
7808
7792
7776
7760
7744
7728
7712
7696
7680
7664
7648
7632
Y
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed,
reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp.
Page 17 of 113
Version: 0.19
a-Si TFT LCD Single Chip Driver
240RGBx320 Resolution and 262K color
NO.
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
Pad Name
G[191]
G[193]
G[195]
G[197]
G[199]
G[201]
G[203]
G[205]
G[207]
G[209]
G[211]
G[213]
G[215]
G[217]
G[219]
G[221]
G[223]
G[225]
G[227]
G[229]
G[231]
G[233]
G[235]
G[237]
G[239]
G[241]
G[233]
G[245]
G[247]
G[249]
G[251]
G[253]
G[255]
G[257]
G[259]
G[261]
G[263]
G[265]
G[267]
G[269]
G[271]
G[273]
G[275]
G[277]
G[233]
G[281]
G[283]
G[285]
G[287]
G[289]
G[291]
G[293]
G[295]
G[297]
G[299]
G[301]
G[303]
G[305]
G[307]
G[309]
X
7616
7600
7584
7568
7552
7536
7520
7504
7488
7472
7456
7440
7424
7408
7392
7376
7360
7344
7328
7312
7296
7280
7264
7248
7232
7216
7200
7184
7168
7152
7136
7120
7104
7088
7072
7056
7040
7024
7008
6992
6976
6960
6944
6928
6912
6896
6880
6864
6848
6832
6816
6800
6784
6768
6752
6736
6720
6704
6688
6672
Y
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
NO.
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
Pad Name
G[311]
G[313]
G[315]
G[317]
G[319]
VGLDMY2
DUMMY22
DUMMY23
DUMMY24
S[720]
S[719]
S[718]
S[717]
S[716]
S[715]
S[714]
S[713]
S[712]
S[711]
S[710]
S[709]
S[708]
S[707]
S[706]
S[705]
S[704]
S[703]
S[702]
S[701]
S[700]
S[699]
S[698]
S[697]
S[696]
S[695]
S[694]
S[693]
S[692]
S[691]
S[690]
S[689]
S[688]
S[687]
S[686]
S[685]
S[684]
S[683]
S[682]
S[681]
S[680]
S[679]
S[678]
S[677]
S[676]
S[675]
S[674]
S[673]
S[672]
S[671]
S[670]
X
6656
6640
6624
6608
6592
6576
6560
6368
6352
6336
6320
6304
6288
6272
6256
6240
6224
6208
6192
6176
6160
6144
6128
6112
6096
6080
6064
6048
6032
6016
6000
5984
5968
5952
5936
5920
5904
5888
5872
5856
5840
5824
5808
5792
5776
5760
5744
5728
5712
5696
5680
5664
5648
5632
5616
5600
5584
5568
5552
5536
Y
233
120
233
120
233
120
233
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
NO.
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
ILI9335
Pad Name
S[669]
S[668]
S[667]
S[666]
S[665]
S[664]
S[663]
S[662]
S[661]
S[660]
S[659]
S[658]
S[657]
S[656]
S[655]
S[654]
S[653]
S[652]
S[651]
S[650]
S[649]
S[648]
S[647]
S[646]
S[645]
S[644]
S[643]
S[642]
S[641]
S[640]
S[639]
S[638]
S[637]
S[636]
S[635]
S[634]
S[633]
S[632]
S[631]
S[630]
S[629]
S[628]
S[627]
S[626]
S[625]
S[624]
S[623]
S[622]
S[621]
S[620]
S[619]
S[618]
S[617]
S[616]
S[615]
S[614]
S[613]
S[612]
S[611]
S[610]
X
5520
5504
5488
5472
5456
5440
5424
5408
5392
5376
5360
5344
5328
5312
5296
5280
5264
5248
5232
5216
5200
5184
5168
5152
5136
5120
5104
5088
5072
5056
5040
5024
5008
4992
4976
4960
4944
4928
4912
4896
4880
4864
4848
4832
4816
4800
4784
4768
4752
4736
4720
4704
4688
4672
4656
4640
4624
4608
4592
4576
Y
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed,
reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp.
Page 18 of 113
Version: 0.19
a-Si TFT LCD Single Chip Driver
240RGBx320 Resolution and 262K color
NO.
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
Pad Name
S[609]
S[608]
S[607]
S[606]
S[605]
S[604]
S[603]
S[602]
S[601]
S[600]
S[599]
S[598]
S[597]
S[596]
S[595]
S[594]
S[593]
S[592]
S[591]
S[590]
S[589]
S[588]
S[587]
S[586]
S[585]
S[584]
S[583]
S[582]
S[581]
S[580]
S[579]
S[578]
S[577]
S[576]
S[575]
S[574]
S[573]
S[572]
S[571]
S[570]
S[569]
S[568]
S[567]
S[566]
S[565]
S[564]
S[563]
S[562]
S[561]
S[560]
S[559]
S[558]
S[557]
S[556]
S[555]
S[554]
S[553]
S[552]
S[551]
S[550]
X
4560
4544
4528
4512
4496
4480
4464
4448
4432
4416
4400
4384
4368
4352
4336
4320
4304
4288
4272
4256
4240
4224
4208
4192
4176
4160
4144
4128
4112
4096
4080
4064
4048
4032
4016
4000
3984
3968
3952
3936
3920
3904
3888
3872
3856
3840
3824
3808
3792
3776
3760
3744
3728
3712
3696
3680
3664
3648
3632
3616
Y
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
NO.
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
Pad Name
S[549]
S[548]
S[547]
S[546]
S[545]
S[544]
S[543]
S[542]
S[541]
S[540]
S[539]
S[538]
S[537]
S[536]
S[535]
S[534]
S[533]
S[532]
S[531]
S[530]
S[529]
S[528]
S[527]
S[526]
S[525]
S[524]
S[523]
S[522]
S[521]
S[520]
S[519]
S[518]
S[517]
S[516]
S[515]
S[514]
S[513]
S[512]
S[511]
S[510]
S[509]
S[508]
S[507]
S[506]
S[505]
S[504]
S[503]
S[502]
S[501]
S[500]
S[499]
S[498]
S[497]
S[496]
S[495]
S[494]
S[493]
S[492]
S[491]
S[490]
X
3600
3584
3568
3552
3536
3520
3504
3488
3472
3456
3440
3424
3408
3392
3376
3360
3344
3328
3312
3296
3280
3264
3248
3232
3216
3200
3184
3168
3152
3136
3120
3104
3088
3072
3056
3040
3024
3008
2992
2976
2960
2944
2928
2912
2896
2880
2864
2848
2832
2816
2800
2784
2768
2752
2736
2720
2704
2688
2672
2656
Y
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
NO.
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
ILI9335
Pad Name
S[489]
S[488]
S[487]
S[486]
S[485]
S[484]
S[483]
S[482]
S[481]
S[480]
S[479]
S[478]
S[477]
S[476]
S[475]
S[474]
S[473]
S[472]
S[471]
S[470]
S[469]
S[468]
S[467]
S[466]
S[465]
S[464]
S[463]
S[462]
S[461]
S[460]
S[459]
S[458]
S[457]
S[456]
S[455]
S[454]
S[453]
S[452]
S[451]
S[450]
S[449]
S[448]
S[447]
S[446]
S[445]
S[444]
S[443]
S[442]
S[441]
S[440]
S[439]
S[438]
S[437]
S[436]
S[435]
S[434]
S[433]
S[432]
S[431]
S[430]
X
2640
2624
2608
2592
2576
2560
2544
2528
2512
2496
2480
2464
2448
2432
2416
2400
2384
2368
2352
2336
2320
2304
2288
2272
2256
2240
2224
2208
2192
2176
2160
2144
2128
2112
2096
2080
2064
2048
2032
2016
2000
1984
1968
1952
1936
1920
1904
1888
1872
1856
1840
1824
1808
1792
1776
1760
1744
1728
1712
1696
Y
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed,
reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp.
Page 19 of 113
Version: 0.19
a-Si TFT LCD Single Chip Driver
240RGBx320 Resolution and 262K color
NO.
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
Pad Name
S[429]
S[428]
S[427]
S[426]
S[425]
S[424]
S[423]
S[422]
S[421]
S[420]
S[419]
S[418]
S[417]
S[416]
S[415]
S[414]
S[413]
S[412]
S[411]
S[410]
S[409]
S[408]
S[407]
S[406]
S[405]
S[404]
S[403]
S[402]
S[401]
S[400]
S[399]
S[398]
S[397]
S[396]
S[395]
S[394]
S[393]
S[392]
S[391]
S[390]
S[389]
S[388]
S[387]
S[386]
S[385]
S[384]
S[383]
S[382]
S[381]
S[380]
S[379]
S[378]
S[377]
S[376]
S[375]
S[374]
S[373]
S[372]
S[371]
S[370]
X
1680
1664
1648
1632
1616
1600
1584
1568
1552
1536
1520
1504
1488
1472
1456
1440
1424
1408
1392
1376
1360
1344
1328
1312
1296
1280
1264
1248
1232
1216
1200
1184
1168
1152
1136
1120
1104
1088
1072
1056
1040
1024
1008
992
976
960
944
928
912
896
880
864
848
832
816
800
784
768
752
736
Y
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
NO.
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
Pad Name
S[369]
S[368]
S[367]
S[366]
S[365]
S[364]
S[363]
S[362]
S[361]
VGMMA62
VGMMA1
S[360]
S[359]
S[358]
S[357]
S[356]
S[355]
S[354]
S[353]
S[352]
S[351]
S[350]
S[349]
S[348]
S[347]
S[346]
S[345]
S[344]
S[343]
S[342]
S[341]
S[340]
S[339]
S[338]
S[337]
S[336]
S[335]
S[334]
S[333]
S[332]
S[331]
S[330]
S[329]
S[328]
S[327]
S[326]
S[325]
S[324]
S[323]
S[322]
S[321]
S[320]
S[319]
S[318]
S[317]
S[316]
S[315]
S[314]
S[313]
S[312]
X
720
704
688
672
656
640
624
608
592
576
-576
-592
-608
-624
-640
-656
-672
-688
-704
-720
-736
-752
-768
-784
-800
-816
-832
-848
-864
-880
-896
-912
-928
-944
-960
-976
-992
-1008
-1024
-1040
-1056
-1072
-1088
-1104
-1120
-1136
-1152
-1168
-1184
-1200
-1216
-1232
-1248
-1264
-1280
-1296
-1312
-1328
-1344
-1360
Y
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
NO.
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
ILI9335
Pad Name
S[311]
S[310]
S[309]
S[308]
S[307]
S[306]
S[305]
S[304]
S[303]
S[302]
S[301]
S[300]
S[299]
S[298]
S[297]
S[296]
S[295]
S[294]
S[293]
S[292]
S[291]
S[290]
S[289]
S[288]
S[287]
S[286]
S[285]
S[284]
S[283]
S[282]
S[281]
S[280]
S[233]
S[278]
S[277]
S[276]
S[275]
S[274]
S[273]
S[272]
S[271]
S[270]
S[269]
S[268]
S[267]
S[266]
S[265]
S[264]
S[263]
S[262]
S[261]
S[260]
S[259]
S[258]
S[257]
S[256]
S[255]
S[254]
S[253]
S[252]
X
-1376
-1392
-1408
-1424
-1440
-1456
-1472
-1488
-1504
-1520
-1536
-1552
-1568
-1584
-1600
-1616
-1632
-1648
-1664
-1680
-1696
-1712
-1728
-1744
-1760
-1776
-1792
-1808
-1824
-1840
-1856
-1872
-1888
-1904
-1920
-1936
-1952
-1968
-1984
-2000
-2016
-2032
-2048
-2064
-2080
-2096
-2112
-2128
-2144
-2160
-2176
-2192
-2208
-2224
-2240
-2256
-2272
-2288
-2304
-2320
Y
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed,
reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp.
Page 20 of 113
Version: 0.19
a-Si TFT LCD Single Chip Driver
240RGBx320 Resolution and 262K color
NO.
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
Pad Name
S[251]
S[250]
S[249]
S[248]
S[247]
S[246]
S[245]
S[244]
S[233]
S[242]
S[241]
S[240]
S[239]
S[238]
S[237]
S[236]
S[235]
S[234]
S[233]
S[232]
S[231]
S[230]
S[229]
S[228]
S[227]
S[226]
S[225]
S[224]
S[223]
S[222]
S[221]
S[220]
S[219]
S[218]
S[217]
S[216]
S[215]
S[214]
S[213]
S[212]
S[211]
S[210]
S[209]
S[208]
S[207]
S[206]
S[205]
S[204]
S[203]
S[202]
S[201]
S[200]
S[199]
S[198]
S[197]
S[196]
S[195]
S[194]
S[193]
S[192]
X
-2336
-2352
-2368
-2384
-2400
-2416
-2432
-2448
-2464
-2480
-2496
-2512
-2528
-2544
-2560
-2576
-2592
-2608
-2624
-2640
-2656
-2672
-2688
-2704
-2720
-2736
-2752
-2768
-2784
-2800
-2816
-2832
-2848
-2864
-2880
-2896
-2912
-2928
-2944
-2960
-2976
-2992
-3008
-3024
-3040
-3056
-3072
-3088
-3104
-3120
-3136
-3152
-3168
-3184
-3200
-3216
-3232
-3248
-3264
-3280
Y
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
NO.
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
1001
1002
1003
1004
1005
1006
1007
1008
1009
1010
1011
1012
1013
1014
1015
1016
1017
1018
1019
1020
Pad Name
S[191]
S[190]
S[189]
S[188]
S[187]
S[186]
S[185]
S[184]
S[183]
S[182]
S[181]
S[180]
S[179]
S[178]
S[177]
S[176]
S[175]
S[174]
S[173]
S[172]
S[171]
S[170]
S[169]
S[168]
S[167]
S[120]
S[165]
S[164]
S[163]
S[162]
S[161]
S[160]
S[159]
S[158]
S[157]
S[156]
S[155]
S[154]
S[153]
S[152]
S[151]
S[150]
S[149]
S[148]
S[147]
S[146]
S[145]
S[144]
S[143]
S[142]
S[141]
S[140]
S[139]
S[138]
S[137]
S[136]
S[135]
S[134]
S[133]
S[132]
X
-3296
-3312
-3328
-3344
-3360
-3376
-3392
-3408
-3424
-3440
-3456
-3472
-3488
-3504
-3520
-3536
-3552
-3568
-3584
-3600
-3616
-3632
-3648
-3664
-3680
-3696
-3712
-3728
-3744
-3760
-3776
-3792
-3808
-3824
-3840
-3856
-3872
-3888
-3904
-3920
-3936
-3952
-3968
-3984
-4000
-4016
-4032
-4048
-4064
-4080
-4096
-4112
-4128
-4144
-4160
-4176
-4192
-4208
-4224
-4240
Y
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
NO.
1021
1022
1023
1024
1025
1026
1027
1028
1029
1030
1031
1032
1033
1034
1035
1036
1037
1038
1039
1040
1041
1042
1043
1044
1045
1046
1047
1048
1049
1050
1051
1052
1053
1054
1055
1056
1057
1058
1059
1060
1061
1062
1063
1064
1065
1066
1067
1068
1069
1070
1071
1072
1073
1074
1075
1076
1077
1078
1079
1080
ILI9335
Pad Name
S[131]
S[120]
S[129]
S[128]
S[127]
S[126]
S[125]
S[124]
S[123]
S[122]
S[121]
S[120]
S[119]
S[118]
S[117]
S[116]
S[115]
S[114]
S[113]
S[112]
S[111]
S[110]
S[109]
S[108]
S[107]
S[106]
S[105]
S[104]
S[103]
S[102]
S[101]
S[100]
S[99]
S[98]
S[97]
S[96]
S[95]
S[94]
S[93]
S[92]
S[91]
S[90]
S[89]
S[88]
S[87]
S[86]
S[85]
S[84]
S[83]
S[82]
S[81]
S[80]
S[79]
S[78]
S[77]
S[76]
S[75]
S[74]
S[73]
S[72]
X
-4256
-4272
-4288
-4304
-4320
-4336
-4352
-4368
-4384
-4400
-4416
-4432
-4448
-4464
-4480
-4496
-4512
-4528
-4544
-4560
-4576
-4592
-4608
-4624
-4640
-4656
-4672
-4688
-4704
-4720
-4736
-4752
-4768
-4784
-4800
-4816
-4832
-4848
-4864
-4880
-4896
-4912
-4928
-4944
-4960
-4976
-4992
-5008
-5024
-5040
-5056
-5072
-5088
-5104
-5120
-5136
-5152
-5168
-5184
-5200
Y
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed,
reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp.
Page 21 of 113
Version: 0.19
a-Si TFT LCD Single Chip Driver
240RGBx320 Resolution and 262K color
NO.
1081
1082
1083
1084
1085
1086
1087
1088
1089
1090
1091
1092
1093
1094
1095
1096
1097
1098
1099
1100
1101
1102
1103
1104
1105
1106
1107
1108
1109
1110
1111
1112
1113
1114
1115
1116
1117
1118
1119
1120
1121
1122
1123
1124
1125
1126
1127
1128
1129
1120
1131
1132
1133
1134
1135
1136
1137
1138
1139
1140
Pad Name
S[71]
S[70]
S[69]
S[68]
S[67]
S[66]
S[65]
S[64]
S[63]
S[62]
S[61]
S[60]
S[59]
S[58]
S[57]
S[56]
S[55]
S[54]
S[53]
S[52]
S[51]
S[50]
S[49]
S[48]
S[47]
S[46]
S[45]
S[44]
S[43]
S[42]
S[41]
S[40]
S[39]
S[38]
S[37]
S[36]
S[35]
S[34]
S[33]
S[32]
S[31]
S[30]
S[29]
S[28]
S[27]
S[26]
S[25]
S[24]
S[23]
S[22]
S[21]
S[20]
S[19]
S[18]
S[17]
S[16]
S[15]
S[14]
S[13]
S[12]
X
-5216
-5232
-5248
-5264
-5280
-5296
-5312
-5328
-5344
-5360
-5376
-5392
-5408
-5424
-5440
-5456
-5472
-5488
-5504
-5520
-5536
-5552
-5568
-5584
-5600
-5616
-5632
-5648
-5664
-5680
-5696
-5712
-5728
-5744
-5760
-5776
-5792
-5808
-5824
-5840
-5856
-5872
-5888
-5904
-5920
-5936
-5952
-5968
-5984
-6000
-6016
-6032
-6048
-6064
-6080
-6096
-6112
-6128
-6144
-6160
Y
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
NO.
1141
1142
1143
1144
1145
1146
1147
1148
1149
1150
1151
1152
1153
1154
1155
1156
1157
1158
1159
1160
1161
1162
1163
1164
1165
1120
1167
1168
1169
1170
1171
1172
1173
1174
1175
1176
1177
1178
1179
1180
1181
1182
1183
1184
1185
1186
1187
1188
1189
1190
1191
1192
1193
1194
1195
1196
1197
1198
1199
1200
Pad Name
S[11]
S[10]
S[9]
S[8]
S[7]
S[6]
S[5]
S[4]
S[3]
S[2]
S[1]
DUMMY25
DUMMY26
DUMMY27
VGLDMY3
G[320]
G[318]
G[316]
G[314]
G[312]
G[310]
G[308]
G[306]
G[304]
G[302]
G[300]
G[298]
G[296]
G[294]
G[292]
G[290]
G[288]
G[286]
G[284]
G[282]
G[280]
G[278]
G[276]
G[274]
G[272]
G[270]
G[268]
G[266]
G[264]
G[262]
G[260]
G[258]
G[256]
G[254]
G[252]
G[250]
G[248]
G[246]
G[244]
G[242]
G[240]
G[238]
G[236]
G[234]
G[232]
X
-6176
-6192
-6208
-6224
-6240
-6256
-6272
-6288
-6304
-6320
-6336
-6352
-6368
-6560
-6576
-6592
-6608
-6624
-6640
-6656
-6672
-6688
-6704
-6720
-6736
-6752
-6768
-6784
-6800
-6816
-6832
-6848
-6864
-6880
-6896
-6912
-6928
-6944
-6960
-6976
-6992
-7008
-7024
-7040
-7056
-7072
-7088
-7104
-7120
-7136
-7152
-7168
-7184
-7200
-7216
-7232
-7248
-7264
-7280
-7296
Y
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
NO.
1201
1202
1203
1204
1205
1206
1207
1208
1209
1210
1211
1212
1213
1214
1215
1216
1217
1218
1219
1220
1221
1222
1223
1224
1225
1226
1227
1228
1229
1230
1231
1232
1233
1234
1235
1236
1237
1238
1239
1240
1241
1242
1233
1244
1245
1246
1247
1248
1249
1250
1251
1252
1253
1254
1255
1256
1257
1258
1259
1260
ILI9335
Pad Name
G[230]
G[228]
G[226]
G[224]
G[222]
G[220]
G[218]
G[216]
G[214]
G[212]
G[210]
G[208]
G[206]
G[204]
G[202]
G[200]
G[198]
G[196]
G[194]
G[192]
G[190]
G[188]
G[186]
G[184]
G[182]
G[180]
G[178]
G[176]
G[174]
G[172]
G[170]
G[168]
G[120]
G[164]
G[162]
G[160]
G[158]
G[156]
G[154]
G[152]
G[150]
G[148]
G[146]
G[144]
G[142]
G[140]
G[138]
G[136]
G[134]
G[132]
G[120]
G[128]
G[126]
G[124]
G[122]
G[120]
G[118]
G[116]
G[114]
G[112]
X
-7312
-7328
-7344
-7360
-7376
-7392
-7408
-7424
-7440
-7456
-7472
-7488
-7504
-7520
-7536
-7552
-7568
-7584
-7600
-7616
-7632
-7648
-7664
-7680
-7696
-7712
-7728
-7744
-7760
-7776
-7792
-7808
-7824
-7840
-7856
-7872
-7888
-7904
-7920
-7936
-7952
-7968
-7984
-8000
-8016
-8032
-8048
-8064
-8080
-8096
-8112
-8128
-8144
-8160
-8176
-8192
-8208
-8224
-8240
-8256
Y
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed,
reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp.
Page 22 of 113
Version: 0.19
a-Si TFT LCD Single Chip Driver
240RGBx320 Resolution and 262K color
NO.
1261
1262
1263
1264
1265
1266
1267
1268
1269
1270
1271
1272
1273
1274
1275
1276
1277
1278
1233
1280
Pad Name
G[110]
G[108]
G[106]
G[104]
G[102]
G[100]
G[98]
G[96]
G[94]
G[92]
G[90]
G[88]
G[86]
G[84]
G[82]
G[80]
G[78]
G[76]
G[74]
G[72]
X
-8272
-8288
-8304
-8320
-8336
-8352
-8368
-8384
-8400
-8416
-8432
-8448
-8464
-8480
-8496
-8512
-8528
-8544
-8560
-8576
Y
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
NO.
1281
1282
1283
1284
1285
1286
1287
1288
1289
1290
1291
1292
1293
1294
1295
1296
1297
1298
1299
1200
Pad Name
G[70]
G[68]
G[66]
G[64]
G[62]
G[60]
G[58]
G[56]
G[54]
G[52]
G[50]
G[48]
G[46]
G[44]
G[42]
G[40]
G[38]
G[36]
G[34]
G[32]
X
-8592
-8608
-8624
-8640
-8656
-8672
-8688
-8704
-8720
-8736
-8752
-8768
-8784
-8800
-8816
-8832
-8848
-8864
-8880
-8896
Y
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
NO.
1201
1202
1203
1204
1205
1206
1207
1208
1209
1310
1311
1312
1313
1314
1315
1316
1317
1318
1319
1320
ILI9335
Pad Name
G[30]
G[28]
G[26]
G[24]
G[22]
G[20]
G[18]
G[16]
G[14]
G[12]
G[10]
G[8]
G[6]
G[4]
G[2]
VGLDMY4
DUMMYR28
DUMMYR29
DUMMY30
DUMMY31
X
-8912
-8928
-8944
-8960
-8976
-8992
-9008
-9024
-9040
-9056
-9072
-9088
-9104
-9120
-9136
-9152
-9168
-9184
-9200
-9216
Y
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
120
233
The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed,
reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp.
Page 23 of 113
Version: 0.19
a-Si TFT LCD Single Chip Driver
240RGBx320 Resolution and 262K color
S1 ~ S720
16
16
ILI9335
16
G1 ~ G320
DUMMY18~31
VGMMA1, 62
9
4
VGLDMY1~4
1
9
9
4
Unit: um
I/O Pads
50
20
50
p
m
u
P
da
P
p
m
u
P
da
P
Min. 70
0
8
Unit : um
Alignment mark
5
25
30
25
5
5
25
30
5
20
2
0
25
5
5
20
20
25
25
30
30
25
25
5
5
Alignment Mark: 1 (Left)
Alignment Mark: 2 (Right)
Alignment mark
X
Y
1
-9301
226
2
9301
226
The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed,
reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp.
Page 24 of 113
Version: 0.19
a-Si TFT LCD Single Chip Driver
240RGBx320 Resolution and 262K color
ILI9335
6. Block Description
MPU System Interface
ILI9335 supports three system high-speed interfaces: i80-system high-speed interfaces to 8-, 9-, 16-, 18-bit
parallel ports and serial peripheral interface (SPI). The interface mode is selected by setting the IM[3:0] pins.
ILI9335 has a 16-bit index register (IR), an 18-bit write-data register (WDR), and an 18-bit read-data register
(RDR). The IR is the register to store index information from control registers and the internal GRAM. The
WDR is the register to temporarily store data to be written to control registers and the internal GRAM. The
RDR is the register to temporarily store data read from the GRAM. Data from the MPU to be written to the
internal GRAM are first written to the WDR and then automatically written to the internal GRAM in internal
operation. Data are read via the RDR from the internal GRAM. Therefore, invalid data are read out to the data
bus when the ILI9335 read the first data from the internal GRAM. Valid data are read out after the ILI9335
performs the second read operation.
Registers are written consecutively as the register execution time.
Registers selection by system interface (8-/9-/16-/18-bit bus width)
Function
I80
RS
nWR
nRD
Write an index to IR register
0
0
1
Write to control registers or the internal GRAM by WDR register.
1
0
1
Read from the internal GRAM by RDR register.
1
1
0
Registers selection by the SPI system interface
Function
R/W
RS
0
0
Write to control registers or the internal GRAM by WDR register.
0
1
Read from the internal GRAM by RDR register.
1
1
Write an index to IR register
Parallel RGB Interface
ILI9335 supports the RGB interface and the VSYNC interface as the external interface for displaying a moving
picture. When the RGB interface is selected, display operations are synchronized with externally supplied
signals, VSYNC, HSYNC, and DOTCLK. In RGB interface mode, data (DB17-0) are written in synchronization
with these signals according to the polarity of enable signal (ENABLE) to prevent flicker on display while
updating display data.
In VSYNC interface mode, the display operation is synchronized with the internal clock except frame
synchronization, where the operation is synchronized with the VSYNC signal. Display data are written to the
internal GRAM via the system interface. In this case, there are constraints in speed and method in writing data
to the internal RAM. For details, see the “External Display Interface” section. The ILI9335 allows for switching
between the external display interface and the system interface by instruction so that the optimum interface is
selected for the kind of picture to be displayed on the screen (still and/or moving picture(s)). The RGB
interface, by writing all display data to the internal RAM, allows for transferring data only when updating the
frames of a moving picture, contributing to low power requirement for moving picture display.
The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed,
reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp.
Page 25 of 113
Version: 0.19
a-Si TFT LCD Single Chip Driver
240RGBx320 Resolution and 262K color
ILI9335
Address Counter (AC)
The address counter (AC) gives an address to the internal GRAM. When the index of the register for setting a
RAM address in the AC is written to the IR, the address information is sent from the IR to the AC. As writing
data to the internal GRAM, the address in the AC is automatically updated plus or minus 1. The window
address function enables writing data only in the rectangular area arbitrarily set by users on the GRAM.
Graphics RAM (GRAM)
GRAM is graphics RAM storing bit-pattern data of 172,800 (240 x 320x 18/8) bytes with 18 bits per pixel.
Grayscale Voltage Generating Circuit
The grayscale voltage generating circuit generates a liquid crystal drive voltage according to grayscale data
set in the γ-correction register to display in 262,144 colors. For details, see the “γ-Correction Register”
section.
Timing Controller
The timing generator generates a timing signal for operation of internal circuits such as the internal GRAM.
The timing for the display operation such as RAM read operation and the timing for the internal operation such
as access from the MPU are generated in the way not to interfere each other.
Oscillator (OSC)
ILI9335 generates RC oscillation with an internal oscillation resistor. The frame rate is adjusted by the register
setting.
LCD Driver Circuit
The LCD driver circuit of ILI9335 consists of a 720-output source driver (S1 ~ S720) and a 320-output gate
th
driver (G1~G320). Display pattern data are latched when the 720 bit data are input. The latched data control
the source driver and generate a drive waveform. The gate driver for scanning gate lines outputs either VGH
or VGL level. The shift direction of 720 source outputs from the source driver is set with the SS bit and the
shift direction of gate outputs from the gate driver is set with the GS bit. The scan mode by the gate driver is
set with the SM bit. These bits allow setting an appropriate scan method for an LCD module.
LCD Driver Power Supply Circuit
The LCD drive power supply circuit generates the voltage levels VREG1OUT, VGH, VGL and Vcom for
driving an LCD
The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed,
reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp.
Page 26 of 113
Version: 0.19
a-Si TFT LCD Single Chip Driver
240RGBx320 Resolution and 262K color
ILI9335
7. System Interface
7.1. Interface Specifications
ILI9335 has the system interface to read/write the control registers and display graphics memory (GRAM),
and the RGB Input Interface for displaying a moving picture. User can select an optimum interface to display
the moving or still picture with efficient data transfer. All display data are stored in the GRAM to reduce the
data transfer efforts and only the updating data is necessary to be transferred. User can only update a
sub-range of GRAM by using the window address function.
ILI9335 also has the RGB interface and VSYNC interface to transfer the display data without flicker the
moving picture on the screen. In RGB interface mode, the display data is written into the GRAM through the
control signals of ENABLE, VSYNC, HSYNC, DOTCLK and data bus DB[17:0].
In VSYNC interface mode, the internal display timing is synchronized with the frame synchronization signal
(VSYNC). The VSYNC interface mode enables to display the moving picture display through the system
interface. In this case, there are some constraints of speed and method to write data to the internal RAM.
ILI9335 operates in one of the following 4 modes. The display mode can be switched by the control register.
When switching from one mode to another, refer to the sequences mentioned in the sections of RGB and
VSYNC interfaces.
Operation Mode
RAM Access Setting (RM)
Display Operation Mode (DM[1:0])
Internal operating clock only
(Displaying still pictures)
System interface
(RM = 0)
Internal operating clock
(DM[1:0] = 00)
RGB interface (1)
(Displaying moving pictures)
RGB interface
(RM = 1)
RGB interface
(DM[1:0] = 01)
RGB interface (2)
(Rewriting still pictures while
displaying moving pictures)
System interface
(RM = 0)
RGB interface
(DM[1:0] = 01)
VSYNC interface
(Displaying moving pictures)
System interface
(RM = 0)
VSYNC interface
(DM[1:0] = 01)
Note 1) Registers are set only via the system interface.
Note 2) The RGB-I/F and the VSYNC-I/F are not available simultaneously.
The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed,
reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp.
Page 27 of 113
Version: 0.19
a-Si TFT LCD Single Chip Driver
240RGBx320 Resolution and 262K color
System
Interface
18/16/6
ILI9335
nCS
RS
nW R
nRD
DB[17:0]
System
ILI9335
EN ABLE
VS YNC
RGB
Interface
HSYNC
DOTCLK
Figure1 System Interface and RGB Interface connection
7.2. Input Interfaces
The following are the system interfaces available with the ILI9335. The interface is selected by setting the
IM[3:0] pins. The system interface is used for setting registers and GRAM access.
IM3
IM2
IM1
IM0
MPU-Interface Mode
DB Pin in use
0
0
0
0
Setting invalid
0
0
0
1
Setting invalid
0
0
1
0
i80-system 16-bit interface
0
0
1
1
i80-system 8-bit interface
DB[17:10]
0
1
0
ID
Serial Peripheral Interface (SPI)
SDI, SDO
0
1
1
*
Setting invalid
1
0
0
0
Setting invalid
1
0
0
1
i80-system 16-bit interface
DB[15:0]
1
0
1
0
i80-system 18-bit interface
DB[17:0]
1
0
1
1
i80-system 9-bit interface
DB[17:9]
1
1
*
*
Setting invalid
DB[17:10], DB[8:1]
The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed,
reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp.
Page 28 of 113
Version: 0.19
a-Si TFT LCD Single Chip Driver
240RGBx320 Resolution and 262K color
ILI9335
7.2.1. i80/18-bit System Interface
The i80/18-bit system interface is selected by setting the IM[3:0] as “1010” levels.
System
nCS
A2
nWR
nRD
D[31:0]
nCS
RS
nWR
nRD
DB[17:0]
18
1818-bit System Interface (262K
262K colors)
colors) TRI=
TRI=0, DFM[
DFM[1:0]=00
]=00
Input Data
Write Data
Register
GRAM Data &
RGB Mapping
DB
17
DB
16
DB
15
DB
14
DB
13
DB
12
DB
11
DB
10
DB
9
DB
8
DB
7
DB
6
DB
5
DB
4
DB
3
DB
2
DB
1
DB
0
WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD
17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
R5
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
Figure2 18-bit System Interface Data Format
The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed,
reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp.
Page 29 of 113
Version: 0.19
a-Si TFT LCD Single Chip Driver
240RGBx320 Resolution and 262K color
ILI9335
7.2.2. i80/16-bit System Interface (DB[15:0])
The i80/16-bit system interface is selected by setting the IM[3:0] as “1001” levels. The 262K or 65K color can
st
be display through the 16-bit MPU interface. When the 262K color is displayed, two transfers (1 transfer: 2
nd
st
nd
bits, 2 transfer: 16 bits or 1 transfer: 16 bits, 2 transfer: 2 bits) are necessary for the 16-bit CPU interface.
TRI
DFM
16-bit MPU System Interface Data Format
system 16-bit interface (1 transfers/pixel) 65,536 colors
0
*
1st Transfer
DB
15
DB
14
DB
13
DB
12
DB
11
DB
10
DB
9
DB
8
R5
R4
R3
R2
R1
R0
G5
G4
DB
7
DB
6
DB
5
DB
4
DB
3
DB
2
DB
1
DB
0
G2
G1
G0
B5
B4
B3
B2
B1
G3
B0
80-system 16-bit interface (2 transfers/pixel) 262,144 colors
1
0
DB
15
DB
14
DB
13
DB
12
DB
11
DB
10
DB
9
R5
R4
R3
R2
R1
R0
G5
1st Transfer
DB
8
DB
7
DB
6
DB
5
DB
4
DB
3
DB
2
DB
1
DB
0
2nd Transfer
DB
DB
15
14
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
80-system 16-bit interface (2 transfers/pixel) 262,144 colors
1
1
1st Transfer
DB
DB
1
0
DB
15
DB
14
DB
13
DB
12
DB
11
DB
10
DB
9
R5
R3
R2
R1
R0
G5
G4
G3
R4
2nd Transfer
DB
8
DB
7
DB
6
DB
5
DB
4
DB
3
DB
2
DB
1
DB
0
G2
G1
G0
B5
B4
B3
B2
B1
B0
7.2.3. i80/16-bit System Interface (DB[17:10][8:1])
The i80/16-bit system interface is selected by setting the IM[3:0] as “0010” levels. The 262K or 65K color can
st
be display through the 16-bit MPU interface. When the 262K color is displayed, two transfers (1 transfer: 2
nd
st
nd
bits, 2 transfer: 16 bits or 1 transfer: 16 bits, 2 transfer: 2 bits) are necessary for the 16-bit CPU interface.
TRI
DFM
16-bit MPU System Interface Data Format
system 16-bit interface (1 transfers/pixel) 65,536 colors
0
*
DB
17
DB
16
DB
15
DB
14
DB
13
DB
12
DB
11
1st Transfer
DB
DB
10
8
DB
7
DB
6
DB
5
DB
4
DB
3
DB
2
DB
1
R5
R4
R3
R2
R1
R0
G5
G4
G1
G0
B5
B4
B3
B2
B1
DB
6
DB
5
DB
4
DB
3
DB
2
DB
1
2nd Transfer
DB DB
17 16
G1
G0
B5
B4
B3
B2
B1
B0
2nd Transfer
DB DB DB
10
8
7
DB
6
DB
5
DB
4
DB
3
DB
2
DB
1
B5
B4
B3
B2
B1
B0
G3
G2
B0
80-system 16-bit interface (2 transfers/pixel) 262,144 colors
1
0
DB
17
DB
16
DB
15
DB
14
DB
13
DB
12
DB
11
R5
R4
R3
R2
R1
R0
G5
1st Transfer
DB DB DB
10
8
7
G4
G3
G2
80-system 16-bit interface (2 transfers/pixel) 262,144 colors
1
1
1st Transfer
DB DB
2
1
DB
17
DB
16
DB
15
DB
14
DB
13
DB
12
DB
11
R5
R3
R2
R1
R0
G5
G4
G3
R4
G2
G1
G0
Figure3 16-bit System Interface Data Format
The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed,
reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp.
Page 30 of 113
Version: 0.19
a-Si TFT LCD Single Chip Driver
240RGBx320 Resolution and 262K color
ILI9335
7.2.4. i80/9-bit System Interface (DB[17:9])
The i80/9-bit system interface is selected by setting the IM[3:0] as “1011” and the DB17~DB9 pins are used to
transfer the data. When writing the 16-bit register, the data is divided into upper byte (8 bits and LSB is not
used) lower byte and the upper byte is transferred first. The display data is also divided in upper byte (9 bits)
and lower byte, and the upper byte is transferred first. The unused DB[8:0] pins must be tied to GND.
nCS
A1
nWR
nRD
D[8:0]
System
nCS
RS
nWR
nRD
DB[17:9]
9
9-bit System Interface (262K
262K colors)
colors) TRI=
TRI=0, DFM[
DFM[1:0]=00
]=00
Input Data
Write Data
Register
GRAM Data &
RGB Mapping
DB
17
DB
16
DB
15
1st Transfer (Upper bits)
DB
14
DB
13
DB
12
DB
11
DB
10
DB
9
DB
17
DB
16
DB
15
2nd Transfer (Lower bits)
DB
14
DB
13
DB
12
DB
11
DB
10
DB
9
WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD
17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
R5
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
Figure4 9-bit System Interface Data Format
7.2.5. i80/8-bit System Interface (DB[17:10])
The i80/8-bit system interface is selected by setting the IM[3:0] as “0011” and the DB17~DB10 pins are used
to transfer the data. When writing the 16-bit register, the data is divided into upper byte (8 bits and LSB is not
used) lower byte and the upper byte is transferred first. The display data is also divided in upper byte (8 bits)
and lower byte, and the upper byte is transferred first. The written data is expanded into 18 bits internally (see
the figure below) and then written into GRAM. The unused DB[9:0] pins must be tied to GND.
The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed,
reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp.
Page 31 of 113
Version: 0.19
a-Si TFT LCD Single Chip Driver
240RGBx320 Resolution and 262K color
TRI
DFM
ILI9335
8-bit MPU System Interface Data Format
system 8-bit interface (2 transfers/pixel) 65,536 colors
0
*
DB
17
DB
16
DB
15
R5
R4
R3
1st Transfer
DB
14
DB
13
DB
12
DB
11
DB
10
R2
R1
R0
G5
G4
G3
DB
17
DB
16
DB
15
G2
G1
2nd Transfer
DB
14
DB
13
DB
12
DB
11
DB
10
G0
B5
B4
B3
B2
B1
B0
80-system 8-bit interface (3 transfers/pixel) 262,144 colors
1
0
1st Transfer
DB DB
11
10
DB
17
DB
16
DB
15
R5
R3
R2
R1
R4
2nd Transfer
DB
14
DB
13
DB
12
DB
11
DB
10
DB
17
DB
16
DB
15
R0
G5
G4
G3
G2
G1
G0
3rd Transfer
DB
14
DB
13
DB
12
DB
11
DB
10
B5
B4
B3
B2
B1
B0
80-system 8-bit interface (3 transfers/pixel) 262,144 colors
1
1
DB
17
DB
16
R5
R4
1st Transfer
DB
15
DB
14
DB
13
DB
12
DB
17
DB
16
R3
R2
R1
R0
G5
G4
2nd Transfer
DB
15
DB
14
DB
13
DB
12
DB
17
DB
16
G3
G2
G1
G0
B5
B4
3rd Transfer
DB
15
DB
14
DB
13
DB
12
B3
B2
B1
B0
Figure5 8-bit System Interface Data Format
The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed,
reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp.
Page 32 of 113
Version: 0.19
a-Si TFT LCD Single Chip Driver
240RGBx320 Resolution and 262K color
ILI9335
7.3. Serial Peripheral Interface (SPI)
The Serial Peripheral Interface (SPI) is selected by setting the IM[3:0] pins as “010x” level. The chip select pin
(nCS), the serial transfer clock pin (SCL), the serial data input pin (SDI) and the serial data output pin (SDO)
are used in SPI mode. The ID pin sets the least significant bit of the identification code. The DB[17:0] pins,
which are not used, must be tied to GND.
The SPI interface operation enables from the falling edge of nCS and ends of data transfer on the rising edge
of nCS. The start byte is transferred to start the SPI interface and the read/write operation and RS information
are also included in the start byte. When the start byte is matched, the subsequent data is received by
ILI9335.
The seventh bit of start byte is RS bit. When RS = “0”, either index write operation or status read operation is
executed. When RS = “1”, either register write operation or RAM read/write operation is executed. The eighth
bit of the start byte is used to select either read or write operation (R/W bit). Data is written when the R/W bit is
“0” and read back when the R/W bit is “1”.
After receiving the start byte, ILI9335 starts to transfer or receive the data in unit of byte and the data transfer
starts from the MSB bit. All the registers of the ILI9335 are 16-bit format and receive the first and the second
byte datat as the upper and the lower eight bits of the 16-bit register respectively. In SPI mode, 5 bytes
th
dummy read is necessary and the valid data starts from 6 byte of read back data.
Start Byte Format
Transferred bits
S
Start byte format
Transfer start
1
2
3
4
5
6
Device ID code
0
1
1
1
0
ID
7
8
RS
R/W
1/0
1/0
Note: ID bit is selected by setting the IM0/ID pin.
RS and R/W Bit Function
RS
R/W
0
0
Set an index register
Function
0
1
Read a status
1
0
Write a register or GRAM data
1
1
Read a register or GRAM data
The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed,
reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp.
Page 33 of 113
Version: 0.19
a-Si TFT LCD Single Chip Driver
240RGBx320 Resolution and 262K color
ILI9335
Serial Peripheral Interface for register access
D
15
D
14
D
13
D
12
D
11
D
10
D
9
D
8
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
IB
15
IB
14
IB
13
IB
12
IB
11
IB
10
IB
9
IB
8
IB
7
IB
6
IB
5
IB
4
IB
3
IB
2
IB
1
IB
0
Serial Peripheral Interface 65K
65K colors
D D D D D D
15 14 13 12 11 10
D
9
D
8
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
SPI Input Data
Register Data
Input Data
Write Data Register
GRAM Data
RGB mapping
WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD
17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0
Figure 6 Data Format of SPI Interface
The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed,
reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp.
Page 34 of 113
Version: 0.19
a-Si TFT LCD Single Chip Driver
240RGBx320 Resolution and 262K color
ILI9335
(a) Basic data transmission through SPI
End
Start
nCS
(Input)
1
2
3
4
5
6
0
1
1
1
0
ID
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
RS RW D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D2
D1
D0
SCL
(Input)
SDI
(Input)
Start Byte
Index register, registers setting, and GRAM write
SDO
(Output)
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
Status, registers read and GRAM read
(b) Consecutive data transmission through SPI
Start
nCS
(Input)
1
8
9
16
24
17
25
32
SCL
(Input)
SDI
(Input)
Register 1
upper eight bits
Start Byte
Register 1
lower eight bits
Register 2
upper eight bits
Register 2
lower eight bits
Note: The first byte after the start byte is always the upper eight bits .
Register 1
execution time
(c) GRAM data read transmission
End
Start
nCS
(Input)
SCL
(Input)
SDI
(Input)
Start Byte
RS=1, RW=1
SDO
(Output)
Dummy
read 1
Dummy
read 2
Dummy
read 3
Dummy
read 4
Dummy
read 5
RAM read
upper byte
RAM read
lower byte
Note: Five bytes of invalid dummy data read after the start byte .
(d) Status/registers read transmission
End
Start
nCS
(Input)
1
8
9
16
24
17
SCL
(Input)
SDI
(Input)
SDO
(Output)
Start Byte
Register 1
upper eight bits
Register 1
lower eight bits
Note: One byte of invalid dummy data read after the start byte .
Figure7 Data transmission through serial peripheral interface (SPI)
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reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp.
Page 35 of 113
Version: 0.19
a-Si TFT LCD Single Chip Driver
240RGBx320 Resolution and 262K color
ILI9335
(e) Basic data transmission through SPI
Start
End
nCS
(Input)
1
2
3
4
5
6
0
1
1
1
0
ID
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
RS RW D23 D22 D21 D120 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D8
D7
D6
D5
D4
D3
D2
D1
D0
SCL
(Input)
SDI
(Input)
Start Byte
GRAM data write
SDO
(Output)
D23 D22 D21 D120 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9
GRAM data read
(f) GRAM data write transmission
End
Start
nCS
(Input)
SCL
(Input)
SDI
(Input)
RAM data 1
1st transfer
Start Byte
RAM data 1
2nd transfer
RAM data 1
3rd transfer
SDO
(Output)
RAM data 2
1st transfer
RAM data 2
2nd transfer
GRAM Data (1)
execution time
Note: Five bytes of invalid dummy data read after the start byte.
RAM data 2
3rd transfer
GRAM Data (2)
execution time
(g) GRAM data read transmission
End
Start
nCS
(Input)
SCL
(Input)
SDI
(Input)
SDO
(Output)
Start Byte
RS=1, RW=1
Dummy
read 1
Dummy
read 2
Dummy
read 3
Dummy
read 4
Dummy
read 5
RAM read
1st byte
RAM read
2nd byte
RAM read
3rd byte
Note: Five bytes of invalid dummy data read after the start byte.
RAM data transfer in SPI mode when TRI=1 and DFM[1:0]=10.
Figure8 Data transmission through serial peripheral interface (SPI), TRI=”1” and DFM=”10”)
The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed,
reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp.
Page 36 of 113
Version: 0.19
a-Si TFT LCD Single Chip Driver
240RGBx320 Resolution and 262K color
ILI9335
7.4. VSYNC Interface
ILI9335 supports the VSYNC interface in synchronization with the frame-synchronizing signal VSYNC to
display the moving picture with the i80 system interface. When the VSYNC interface is selected to display a
moving picture, the minimum GRAM update speed is limited and the VSYNC interface is enabled by setting
DM[1:0] = “10” and RM = “0”.
VSYNC
MPU
nCS
RS
nWR
DB[17:0]
Figure9 Data transmission through VSYNC interface)
In the VSYNC mode, the display operation is synchronized with the internal clock and VSYNC input and the
frame rate is determined by the pulse rate of VSYNC signal. All display data are stored in GRAM to minimize
total data transfer required for moving picture display.
VSYNC
Write data to RAM
through system
interface
Rewriting
screen data
Rewriting
screen data
Display operation
synchronized with
internal clocks
Figure10 Moving picture data transmission through VSYNC interface
The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed,
reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp.
Page 37 of 113
Version: 0.19
a-Si TFT LCD Single Chip Driver
240RGBx320 Resolution and 262K color
VSYNC
ILI9335
RAM
Write
Back porch (14 lines)
Display
operation
Display
(320 lines)
Front porch (2 lines)
Black period
Figure11 Operation through VSYNC Interface
The VSYNC interface has the minimum speed limitation of writing data to the internal GRAM via the system
interface, which are calculated from the following formula.
Internal clock frequency (fosc.) [Hz] = FrameFrequency x (DisplayLine (NL) + FrontPorch (FP) + BackPorch
(BP)) x ClockCyclePerLines (RTN) x FrequencyFluctuation.
240 x DisplayLines (NL)
Minimum RAM write speed (HZ)
[(BackPorch(BP)+DisplayLines(NL) - margins] x 16 (clocks) x 1/fosc
Note: When the RAM write operation does not start from the falling edge of VSYNC, the time from the falling
edge of VSYNC until the start of RAM write operation must also be taken into account.
An example of minimum GRAM writing speed and internal clock frequency in VSYNC interface mode is as
below.
[Example]
Display size: 240 RGB × 320 lines
Lines: 320 lines (NL = 1000111)
Back porch: 14 lines (BP = 1110)
Front porch: 2 lines (FP = 0010)
Frame frequency: 60 Hz
Frequency fluctuation: 10%
Internal oscillator clock (fosc.) [Hz] = 60 x [320+ 2 + 14] x 16 clocks x (1.1/0.9)
≒
394KHz
The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed,
reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp.
Page 38 of 113
Version: 0.19
a-Si TFT LCD Single Chip Driver
240RGBx320 Resolution and 262K color
ILI9335
When calculate the internal clock frequency, the oscillator variation is needed to be taken into consideration.
In the above example, the calculated internal clock frequency with ±10% margin variation is considered and
ensures to complete the display operation within one VSYNC cycle. The causes of frequency variation come
from fabrication process of LSI, room temperature, external resistors and VCI voltage variation.
Minimum speed for RAM writing [Hz] > 240 x 320 x 394K / [ (14 + 320 – 2)lines x 16clocks]
≒
5.7 MHz
The above theoretical value is calculated based on the premise that the ILI9335 starts to write data into the
internal GRAM on the falling edge of VSYNC. There must at least be a margin of 2 lines between the physical
display line and the GRAM line address where data writing operation is performed. The GRAM write speed of
5.7MHz or more will guarantee the completion of GRAM write operation before the ILI9335 starts to display
the GRAM data on the screen and enable to rewrite the entire screen without flicker.
Notes in using the VSYNC interface
1. The minimum GRAM write speed must be satisfied and the frequency variation must be taken into
consideration.
2. The display frame rate is determined by the VSYNC signal and the period of VSYNC must be longer than
the scan period of an entire display.
3. When switching from the internal clock operation mode (DM[1:0] = “00”) to the VSYNC interface mode or
inversely, the switching starts from the next VSYNC cycle, i.e. after completing the display of the frame.
4. The partial display, vertical scroll functions are not available in VSYNC interface mode and set the AM bit to
“0” to transfer display data.
The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed,
reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp.
Page 39 of 113
Version: 0.19
a-Si TFT LCD Single Chip Driver
240RGBx320 Resolution and 262K color
System Interface Mode to VSYNC interface mode
VSYNC interface mode to System Interface Mode
System Interface
Opeartion through
VSYNC interface
Set AM=0
Set DM[1:0]=00, RM=0
for system interface mode
Set GRAM Address
Display operation in
synchronization with
internal clocks
Wait more than 1 frame
Set DM[1:0]=10, RM=0
for VSYNC interface mode
Set index register to R22h
DM[1:0], RM become
enable after completion
of displaying 1 frame
System Interface
Display operation in
synchronization with
VSYNC
DM[1:0], RM become
enable after completion
of displaying 1 frame
Display operation in
synchronization with
internal clocks
Note: input VSYNC for more than 1 frame
period after setting the DM , RM register.
Wait more than 1 fr ame
Write data to GRAM
through VSYNC interface
ILI9335
Display operation in
synchronization with
VSYNC
Opeartion through
VSYNC interface
Figure12 Transition flow between VSYNC and internal clock operation modes
The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed,
reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp.
Page 40 of 113
Version: 0.19
a-Si TFT LCD Single Chip Driver
240RGBx320 Resolution and 262K color
ILI9335
7.5. RGB Input Interface
The RGB Interface mode is available for ILI9335 and the interface is selected by setting the RIM[1:0] bits as
following table.
RIM1
RIM0
0
0
18-bit RGB Interface
RGB Interface
DB[17:0]
DB pins
0
1
16-bit RGB Interface
DB[17:13], DB[11:1]
1
0
6-bit RGB Interface
DB[17:12]
1
1
Setting prohibited
1818-bit RGB Interface (262K
262K colors)
colors)
Input Data
Write Data
Register
GRAM Data &
RGB Mapping
DB
17
DB
16
DB
15
DB
14
DB
13
DB
12
DB
11
DB
10
DB
9
DB
8
DB
7
DB
6
DB
5
DB
4
DB
3
DB
2
DB
1
DB
0
WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD
17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
R5
R4
R3
R2
R1
DB
14
DB
13
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
DB
11
DB
10
DB
9
DB
8
DB
7
DB
6
DB
5
DB
4
DB
3
DB
2
DB
1
B0
1616-bit RGB Interface (65K
65K colors)
colors)
Input Data
Write Data
Register
GRAM Data &
RGB Mapping
DB
17
DB
16
DB
15
WD WD WD WD WD
17 16 15 14 13
R5
R4
R3
R2
WD WD WD WD WD WD WD WD WD WD WD
11 10
9
8
7
6
5
4
3
2
1
R1
R0
G5
G4
DB
13
DB
12
DB
17
DB
16
G3
G2
G1
G0
B5
B4
DB
13
DB
12
DB
17
DB
16
B3
B2
B1
B0
DB
13
DB
12
6-bit RGB Interface (262K
262K colors)
colors)
Input Data
Write Data
Register
GRAM Data &
RGB Mapping
DB
17
DB
16
1st Transfer
DB
15
DB
14
2nd Transfer
DB
15
DB
14
3rd Transfer
DB
15
DB
14
WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD
17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
R5
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
Figure13 RGB Interface Data Format
The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed,
reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp.
Page 41 of 113
Version: 0.19
a-Si TFT LCD Single Chip Driver
240RGBx320 Resolution and 262K color
ILI9335
7.5.1. RGB Interface
The display operation via the RGB interface is synchronized with the VSYNC, HSYNC, and DOTCLK signals.
The RGB interface transfers the updated data to GRAM and the update area is defined by the window
address function. The back porch and front porch are used to set the RGB interface timing.
VSYNC
Back porch
period (BP[3:0])
RAM data display area
Moving picture
display area
Display period
(NL[4:0]
Front porch
period (FP[3:0])
HSYNC
Note 1: Front porch period continues until
the next input of VSYNC.
DOTCLK
Note 2: Input DOTCLK throughout the
operation.
ENABLE
Note 3: Supply the VSYNC, HSYNC and
DOTCLK with frequency that can meet the
resolution requirement of panel.
DB[17:0]
Figure14 GRAM Access Area by RGB Interface
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reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp.
Page 42 of 113
Version: 0.19
a-Si TFT LCD Single Chip Driver
240RGBx320 Resolution and 262K color
ILI9335
7.5.2. RGB Interface Timing
The timing chart of 18-/16-bit RGB interface mode is shown as follows.
1 frame
Back porch
VSYNC
Front porch
VLW >= 1H
HSYNC
DOTCLK
ENABLE
DB[17:0]
HLW >= 3 DOTCLK
//
HSYNC
1H
//
DOTCLK
DTST >= HLW
ENABLE
//
DB[17:0]
Valid data
VLW: VSYNC low period
HLW: HSYNC low period
DTST: data transfer startup time
Note 1: Use the high speed write mode (HWM=1) to write data through the RGB interface.
Figure15 Timing Chart of Signals in 18-/16-bit RGB Interface Mode
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reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp.
Page 43 of 113
Version: 0.19
a-Si TFT LCD Single Chip Driver
240RGBx320 Resolution and 262K color
ILI9335
The timing chart of 6-bit RGB interface mode is shown as follows.
1 frame
Back porch
VSYNC
Front porch
VLW >= 1H
HSYNC
DOTCLK
ENABLE
DB[17:12]
HLW >= 3 DOTCLK
//
1H
HSYNC
//
DOTCLK
DTST >= HLW
ENABLE
//
R G B R G B
//
B R G B
DB[17:12]
Valid data
VLW: VSYNC low period
HLW: HSYNC low period
DTST: data transfer startup time
Note 1) In 6-bit RGB interface mode, each dot of one pixel (R, G and B) is transferred in synchronization with
DOTCLKs.
Note 2) In 6-bit RGB interface mode, set the cycles of VSYNC, HSYNC and ENABLE to 3 multiples of DOTCLKs.
Figure16 Timing chart of signals in 6-bit RGB interface mode
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reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp.
Page 44 of 113
Version: 0.19
a-Si TFT LCD Single Chip Driver
240RGBx320 Resolution and 262K color
ILI9335
7.5.3. Moving Picture Mode
ILI9335 has the RGB interface to display moving picture and incorporates GRAM to store display data, which
has following merits in displaying a moving picture.
• The window address function defined the update area of GRAM.
• Only the moving picture area of GRAM is updated.
• When display the moving picture in RGB interface mode, the DB[17:0] can be switched as system
interface to update still picture area and registers, such as icons.
RAM access via a system interface in RGB-I/F mode
ILI9335 allows GRAM access via the system interface in RGB interface mode. In RGB interface mode, data
are written to the internal GRAM in synchronization with DOTCLK and ENABLE signals. When write data to
the internal GRAM by the system interface, set ENABLE to terminate the RGB interface and switch to the
system interface to update the registers (RM = “0”) and the still picture of GRAM. When restart RAM access in
RGB interface mode, wait one read/write cycle and then set RM = “1” and the index register to R22h to start
accessing RAM via the RGB interface. If RAM accesses via two interfaces conflicts, there is no guarantee that
data are written to the internal GRAM.
The following figure illustrates the operation of the ILI9335 when displaying a moving picture via the RGB
interface and rewriting the still picture RAM area via the system interface.
Still Picture Area
Moving
Picture Area
Update
a frame
Update a
frame
VSYNC
ENABLE
DOTCLK
DB[17:0]
Set
IR to
R22h
Update
moving
picture
area
Set
RM=0
Set
AD[15:0]
Set
IR to
R22h
Update display data in
other than the moving
picture area
Set
AD[15:0]
Set
RM=1
Set
IR to
R22h
Update
moving
picture
area
Figure17 Example of update the still and moving picture
The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed,
reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp.
Page 45 of 113
Version: 0.19
a-Si TFT LCD Single Chip Driver
240RGBx320 Resolution and 262K color
ILI9335
7.5.4. 6-bit RGB Interface
The 6-bit RGB interface is selected by setting the RIM[1:0] bits to “10”. The display operation is synchronized
with VSYNC, HSYNC, and DOTCLK signals. Display data are transferred to the internal GRAM in
synchronization with the display operation via 6-bit RGB data bus (DB[17:12]) according to the data enable
signal (ENABLE). Unused pins (DB[11:0]) must be fixed at GND level. Registers can be set by the system
interface (i80/SPI).
RGB interface with 6-bit data bus
1st Transfer
Input Data
RGB Assignment
2nd Transfer
3rd Transfer
DB
17
DB
16
DB
15
DB
14
DB
13
DB
12
DB
17
DB
16
DB
15
DB
14
DB
13
DB
12
DB
17
DB
16
DB
15
DB
14
DB
13
DB
12
R5
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
Data transfer synchronization in 6-bit RGB interface mode
ILI9335 has data transfer counters to count the first, second, third data transfers in 6-bit RGB interface mode.
The transfer counter is always reset to the state of first data transfer on the falling edge of VSYNC. If a
mismatch arises in the number of each data transfer, the counter is reset to the state of first data transfer at
the start of the frame (i.e. on the falling edge of VSYNC) to restart data transfer in the correct order from the
next frame. This function is expedient for moving picture display, which requires consecutive data transfer in
light of minimizing effects from failed data transfer and enabling the system to return to a normal state.
Note that internal display operation is performed in units of pixels (RGB: taking 3 inputs of DOTCLK).
Accordingly, the number of DOTCLK inputs in one frame period must be a multiple of 3 to complete data
transfer correctly. Otherwise it will affect the display of that frame as well as the next frame.
HSYNC
ENABLE
DOTCLK
DB[17:12]
1st 2nd 3rd 1st 2nd 3rd 1st 2nd 3rd 1st 2nd 3rd
Transfer synchronization
The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed,
reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp.
Page 46 of 113
Version: 0.19
a-Si TFT LCD Single Chip Driver
240RGBx320 Resolution and 262K color
ILI9335
7.5.5. 16-bit RGB Interface
The 16-bit RGB interface is selected by setting the RIM[1:0] bits to “01”. The display operation is synchronized
with VSYNC, HSYNC, and DOTCLK signals. Display data are transferred to the internal RAM in
synchronization with the display operation via 16-bit RGB data bus (DB17-13, DB11-1) according to the data
enable signal (ENABLE). Registers are set only via the system interface.
1616-bit RGB Interface (65K
65K colors)
colors)
DB
17
Input Data
DB
16
DB
15
DB
14
DB
13
DB
11
WD WD WD WD WD
17 16 15 14 13
Write Data
Register
R5
GRAM Data &
RGB Mapping
R4
R3
R2
R1
DB
10
DB
9
DB
8
DB
7
DB
6
DB
5
DB
4
DB
3
DB
2
DB
1
WD WD WD WD WD WD WD WD WD WD WD
11 10
9
8
7
6
5
4
3
2
1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
7.5.6. 18-bit RGB Interface
The 18-bit RGB interface is selected by setting the RIM[1:0] bits to “00”. The display operation is synchronized
with VSYNC, HSYNC, and DOTCLK signals. Display data are transferred to the internal RAM in
synchronization with the display operation via 18-bit RGB data bus (DB[17:0]) according to the data enable
signal (ENABLE). Registers are set only via the system interface.
RGB interface with 18-bit data bus
Input Data
DB
17
DB
16
DB
15
DB
14
DB
13
DB
12
DB
11
DB
10
DB
9
DB
8
DB
7
DB
6
DB
5
DB
4
DB
3
DB
2
DB
1
DB
0
RGB Assignment
R5
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
Notes in using the RGB Input Interface
1. The following are the functions not available in RGB Input Interface mode.
RGB interface
I80 system interface
Partial display
Function
Not available
Available
Scroll function
Not available
Available
Interlaced scan
Not available
Not available
Graphics operation function
Not available
Not available
2. VSYNC, HSYNC, and DOTCLK signals must be supplied throughout a display operation period.
3. The periods set with the NO[1:0] bits (gate output non-overlap period), STD[1:0] bits (source output delay
period) and EQ[1:0] bits (equalization period) are not based on the internal clock but based on DOTCLK in
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reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp.
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a-Si TFT LCD Single Chip Driver
240RGBx320 Resolution and 262K color
ILI9335
RGB interface mode.
4. In 6-bit RGB interface mode, each of RGB dots is transferred in synchronization with a DOTCLK input. In
other words, it takes 3 DOTCLK inputs to transfer one pixel. Be sure to complete data transfer in units of 3
DOTCLK inputs in 6-bit RGB interface mode.
5. In 6-bit RGB interface mode, data of one pixel, which consists of RGB dots, are transferred in units of
3 DOTCLK. Accordingly, set the cycle of each signal in 6-bit interface mode (VSYNC, HSYNC, ENABLE,
DB[17:0]) to contain DOTCLK inputs of a multiple of 3 to complete data transfer in units of pixels.
6. When switching from the internal operation mode to the RGB Input Interface mode, or the other way around,
follow the sequence below.
7. In RGB interface mode, the front porch period continues until the next VSYNC input is detected after
drawing one frame.
8. In RGB interface mode, a RAM address (AD[15:0]) is set in the address counter every frame on the falling
edge of VSYNC.
Figure18 Internal clock operation/RGB interface mode switching
Write data through RGB
interface to write data through
system interface
Write data through system
interface to write data through
RGB interface
System Interface operation
RGB Interface operation
Write data to GRAM through
system interface
Set DM[1:0]=01, RM=0
with RGB interface mode
Set AD[15;0]
Set AD[15; 0]
Set DM[1:0]=01, RM=1
with RGB interfac e mode
Set IR to R 22h
(GRAM data write )
Set IR to R 22h
(GRAM data write )
Write data to GRAM through
system interface
RGB Interface operation
System Interface operation
Figure19 GRAM access between system interface and RGB interface
The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed,
reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp.
Page 48 of 113
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a-Si TFT LCD Single Chip Driver
240RGBx320 Resolution and 262K color
ILI9335
7.6. Interface Timing
The following are diagrams of interfacing timing with LCD panel control signals in internal operation and RGB
interface modes.
//
VSYNC
//
HSYNC
DOTCLK
//
ENABLE
//
DB[17:0]
1
2
3
4
//
5
318 319
320
1
2
3
4
FLM
G1
G2
.
…
G320
S[720:1]
1
2
3
4
5
//
318 319
320
VCOM
Figure20 Relationship between RGB I/F signals and LCD Driving Signals for Panel
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reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp.
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a-Si TFT LCD Single Chip Driver
240RGBx320 Resolution and 262K color
ILI9335
8. Register Descriptions
8.1. Registers Access
ILI9335 adopts 18-bit bus interface architecture for high-performance microprocessor. All the functional
blocks of ILI9335 starts to work after receiving the correct instruction from the external microprocessor by the
18-, 16-, 9-, 8-bit interface. The index register (IR) stores the register address to which the instructions and
display data will be written. The register selection signal (RS), the read/write signals (nRD/nWR) and data
bus D17-0 are used to read/write the instructions and data of ILI9335. The registers of the ILI9335 are
categorized into the following groups.
1. Specify the index of register (IR)
2. Read a status
3. Display control
4. Power management Control
5. Graphics data processing
6. Set internal GRAM address (AC)
7. Transfer data to/from the internal GRAM (R22)
8. Internal grayscale γ-correction (R30 ~ R39)
Normally, the display data (GRAM) is most often updated, and in order since the ILI9335 can update internal
GRAM address automatically as it writes data to the internal GRAM and minimize data transfer by using the
window address function, there are fewer loads on the program in the microprocessor. As the following figure
shows, the way of assigning data to the 16 register bits (D[15:0]) varies for each interface. Send registers in
accordance with the following data transfer format.
Serial Peripheral Interface for register access
SPI Input Data
D
15
D
14
D
13
D
12
D
11
D
10
D
9
D
8
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
Register Data
D
15
D
14
D
13
D
12
D
11
D
10
D
9
D
8
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
Figure21 Register Setting with Serial Peripheral Interface (SPI)
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reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp.
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a-Si TFT LCD Single Chip Driver
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ILI9335
i80/M68 system 18-bit data bus interface
Data Bus
(DB[17:0])
DB
17
DB
12
DB
11
DB
10
Register Bit
(D[15:0])
D15 D14 D13 D12 D11 D10
D9
DB
16
DB
15
DB
14
DB
13
DB
9
DB
8
DB
7
DB
6
DB
5
DB
4
DB
3
DB
2
DB
1
D8
D7
D6
D5
D4
D3
D2
D1
D0
DB
0
i80/M68 system 16-bit data bus interface
Data Bus
(DB[17:10]),
(DB[8:1])
DB
17
DB
12
DB
11
DB
10
DB
8
DB
7
DB
6
DB
5
DB
4
DB
3
DB
2
DB
1
Register Bit
(D[15:0])
D15 D14 D13 D12 D11 D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
DB
17
DB
16
DB
15
2nd Transfer
DB DB DB
14 13 12
DB
11
DB
10
D7
D6
D5
D4
D1
D0
DB
11
DB
10
D1
D0
DB
16
DB
15
DB
14
DB
13
i80/M68 system 9-bit data bus interface
Data Bus
(DB[17:9])
DB
17
1st Transfer
DB DB DB
14 13 12
DB
11
DB
10
Register Bit
(D[15:0])
D15 D14 D13 D12 D11 D10
D9
D8
DB
16
DB
15
DB
9
D3
D2
DB
9
i80/M68 system 8-bit data bus interface/Serial peripheral interface (2/3 transmission)
Data Bus
(DB[17:10])
DB
17
1st Transfer
DB DB DB
14 13 12
DB
11
DB
10
DB
17
DB
16
DB
15
Register Bit
(D[15:0])
D15 D14 D13 D12 D11 D10
D9
D8
D7
D6
D5
DB
16
DB
15
2nd Transfer
DB DB DB
14 13 12
D4
D3
D2
Figure22 Register setting with i80 System Interface
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a-Si TFT LCD Single Chip Driver
240RGBx320 Resolution and 262K color
ILI9335
i80 1818-/1616-bit System Bus Interface Timing
(a) Write to register
nCS
RS
nRD
nWR
DB[17:0]
Write register “index”
Write register “data”
(b) Read from register
nCS
RS
nRD
nWR
DB[17:0]
Write register “index”
Read register “data”
i80 99-/8-bit System Bus Interface Timing
(a) Write to register
nCS
RS
nRD
nWR
DB[17:10]
“00h”
Write register “index”
Write register
“high byte data”
Write register
“low byte data”
(b) Read from register
nCS
RS
nRD
nWR
DB[17:10]
“00h”
Write register “index”
Read register
“high byte data”
Read register
“low byte data”
Figure 23 Register Read/Write Timing of i80 System Interface
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reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp.
Page 52 of 113
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a-Si TFT LCD Single Chip Driver
240RGBx320 Resolution and 262K color
ILI9335
8.2. Instruction Descriptions
No.
Registers Name
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
IR
Index Register
R/W RS
W
0
-
-
-
-
-
-
-
-
ID7
ID6
ID5
ID4
ID3
ID2
ID1
ID0
00h
Driver Code Read
RO
1
1
0
0
1
0
0
1
1
0
0
1
1
0
1
0
1
01h
Driver Output Control 1
W
1
0
0
0
0
0
SM
0
SS
0
0
0
0
0
0
0
0
02h
LCD Driving Control
W
1
0
0
0
0
0
0
B/C
0
0
0
0
0
0
0
0
0
03h
Entry Mode
W
1
TRI
DFM
0
BGR
0
0
0
0
ORG
0
I/D1
I/D0
AM
0
0
0
05h
16 bits data format control
W
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
EPF1
EPF0
07h
Display Control 1
W
1
0
0
PTDE1
PTDE0
0
0
0
BASEE
0
0
GON
DTE
CL
0
D1
D0
08h
Display Control 2
W
1
FP7
FP6
FP5
FP4
FP3
FP2
FP1
FP0
BP7
BP6
BP5
BP4
BP3
BP2
BP1
BP0
09h
Display Control 3
W
1
0
0
0
0
0
0
PTS1
PTS0
0
0
PTG1
PTG0
ISC3
ISC2
ISC1
ISC0
0Ah Display Control 4
W
1
0
0
0
0
0
0
0
0
0
0
0
0
FMARKOE
FMI2
FMI1
FMI0
0Ch RGB Display Interface Control 1
W
1
0
ENC2
ENC1
ENC0
0
0
0
RM
0
0
DM1
DM0
0
0
RIM1
RIM0
0Dh Frame Maker Position
W
1
0
0
0
0
0
0
0
FMP8
FMP7
FMP6
FMP5
FMP4
FMP3
FMP2
FMP1
FMP0
0Fh
RGB Display Interface Control 2
W
1
0
0
0
0
0
0
0
0
0
0
0
VSPL
HSPL
0
EPL
DPL
10h
Power Control 1
W
1
0
0
0
SAP
0
BT2
BT1
BT0
APE
AP2
AP1
AP0
0
0
SLP
STB
11h
Power Control 2
W
1
0
0
0
0
0
DC12
DC11
DC10
0
DC02
DC01
DC00
0
VC2
VC1
VC0
12h
Power Control 3
W
1
0
0
0
0
0
0
0
0
VCIRE
0
0
0
VRH3
VRH2
VRH1
VRH0
13h
Power Control 4
W
1
0
0
0
VDV4
VDV3
VDV2
VDV1
VDV0
0
0
0
0
0
0
0
0
20h
Horizontal GRAM Address Set
W
1
0
0
0
0
0
0
0
0
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
21h
Vertical GRAM Address Set
W
1
0
0
0
0
0
0
0
AD16
AD15
AD14
AD13
AD12
AD11
AD10
AD9
AD8
22h
Write Data to GRAM
W
1
29h
Power Control 7
W
1
2Bh Frame Rate and Color Control
W
30h
Gamma Control 1
W
31h
Gamma Control 2
32h
RAM write data (WD17-0) / read data (RD17-0) bits are transferred via different data bus lines according to the selected interfaces.
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
KP1[2]
W
1
0
0
0
0
0
KP3[2]
Gamma Control 3
W
1
0
0
0
0
0
35h
Gamma Control 4
W
1
0
0
0
0
0
36h
Gamma Control 5
W
1
0
0
0
VRP1[4]
VRP1[3]
37h
Gamma Control 6
W
1
0
0
0
0
0
KN1[2]
KN1[1]
38h
Gamma Control 7
W
1
0
0
0
0
0
KN3[2]
KN3[1]
39h
Gamma Control 8
W
1
0
0
0
0
0
KN5[2]
3Ch Gamma Control 9
W
1
0
0
0
0
0
RN1[2]
3Dh Gamma Control 10
W
1
0
0
0
VRN1[4]
VRN1[3]
50h
W
1
0
0
0
0
0
Horizontal Address Start
0
0
0
0
0
VCM5
VCM4
VCM3
VCM2
VCM1
VCM0
0
0
0
0
0
0
FRS[3]
FRS[2]
FRS[1]
FRS[0]
KP1[1]
KP1[0]
0
0
0
0
0
KP0[2]
KP0[1]
KP0[0]
KP3[1]
KP3[0]
0
0
0
0
0
KP2[2]
KP2[1]
KP2[0]
KP5[2]
KP5[1]
KP5[0]
0
0
0
0
0
KP4[2]
KP4[1]
KP4[0]
RP1[2]
RP1[1]
RP1[0]
0
0
0
0
0
RP0[2]
RP0[1]
RP0[0]
0
0
0
0
VRP0[3]
KN1[0]
0
0
0
0
0
KN0[2]
KN0[1]
KN0[0]
KN3[0]
0
0
0
0
0
KN2[2]
KN2[1]
KN2[0]
KN5[1]
KN5[0]
0
0
0
0
0
KN4[2]
KN4[1]
KN4[0]
RN1[1]
RN1[0]
0
0
0
0
0
RN0[2]
RN0[1]
RN0[0]
0
0
0
0
VRN0[3]
HSA7
HSA6
HSA5
HSA4
HSA3
VRP1[2] VRP1[1] VRP1[0]
VRN1[2] VRN1[1] VRN1[0]
0
0
0
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VRP0[2] VRP0[1] VRP0[0]
VRN0[2] VRN0[1] VRN0[0]
HSA2
HSA1
HSA0
a-Si TFT LCD Single Chip Driver
240RGBx320 Resolution and 262K color
No.
Registers Name
R/W RS
51h
Horizontal Address End Position
W
52h
Vertical Address Start Position
W
53h
Vertical Address End Position
60h
61h
ILI9335
D15
D14
D13
D12
D11
D10
D9
D8
D7
1
0
0
0
0
0
0
0
0
HEA7
1
0
0
0
0
0
0
0
VSA8
VSA7
W
1
0
0
0
0
0
0
0
VEA8
VEA7
Driver Output Control 2
W
1
GS
0
NL5
NL4
NL3
NL2
NL1
NL0
0
Base Image Display Control
D6
D5
D4
D3
D2
D1
D0
HEA6
HEA5
HEA4
HEA3
HEA2
HEA1
HEA0
VSA6
VSA5
VSA4
VSA3
VSA2
VSA1
VSA0
VEA6
VEA5
VEA4
VEA3
VEA2
VEA1
VEA0
0
SCN5
SCN4
SCN3
SCN2
SCN1
SCN0
Position
W
1
0
0
0
0
0
0
0
0
0
0
0
0
0
NDL
VLE
REV
6Ah Vertical Scroll Control
W
1
0
0
0
0
0
0
0
VL8
VL7
VL6
VL5
VL4
VL3
VL2
VL1
VL0
80h
Partial Image 1 Display Position
W
1
0
0
0
0
0
0
0
PTDP08 PTDP07 PTDP06 PTDP05 PTDP04
PTDP03
PTDP02 PTDP01 PTDP00
81h
Partial Image 1 Area (Start Line)
W
1
0
0
0
0
0
0
0
PTSA08 PTSA07 PTSA06 PTSA05
PTSA04
PTSA03
PTSA02 PTSA01 PTSA00
82h
Partial Image 1 Area (End Line)
W
1
0
0
0
0
0
0
0
PTEA08 PTEA07 PTEA06 PTEA05
PTEA04
PTEA03
PTEA02 PTEA01 PTEA00
83h
Partial Image 2 Display Position
W
1
0
0
0
0
0
0
0
PTDP18 PTDP17 PTDP16 PTDP15 PTDP14
PTDP13
PTDP12 PTDP11 PTDP10
84h
Partial Image 2 Area (Start Line)
W
1
0
0
0
0
0
0
0
PTSA18 PTSA17 PTSA16 PTSA15
PTSA14
PTSA13
PTSA12 PTSA11 PTSA10
85h
Partial Image 2 Area (End Line)
W
1
0
0
0
0
0
0
0
PTEA18 PTEA17 PTEA16 PTEA15
PTEA14
PTEA13
PTEA12 PTEA11 PTEA10
90h
Panel Interface Control 1
W
1
0
0
0
0
0
0
DIVI1
DIVI00
0
0
0
RTNI4
RTNI3
RTNI2
RTNI1
RTNI0
92h
Panel Interface Control 2
W
1
0
0
0
0
0
NOWI2
NOWI1
NOWI0
0
0
0
0
0
0
0
0
95h
Panel Interface Control 4
W
1
0
0
0
0
0
0
DIVE1
DIVE0
0
0
0
0
0
0
0
0
97h
Panel Interface Control 5
W
1
0
0
0
0
0
0
A1h OTP VCM Programming Control
W
1
0
0
0
0
0
0
0
VCM_
OTP5
0
VCM_
OTP4
0
VCM_
OTP3
0
VCM_
OTP2
0
VCM_
OTP1
A2h OTP VCM Status and Enable
W
1
0
0
0
0
E6h Deep stand by mode control
W
1
VCM_
D4
KEY
12
0
0
1
VCM_
D5
KEY
13
0
0
W
PGM_
CNT0
KEY
14
0
0
A5h OTP Programming ID Key
PGM_
CNT1
KEY
15
0
NOWE3
OTP_
PGM_EN
VCM_
D3
KEY
11
0
KEY
7
0
KEY
6
0
KEY
5
0
KEY
4
0
KEY
3
0
KEY
2
0
KEY
1
0
0
VCM_
OTP0
VCM_
EN
KEY
0
DSTB
NOWE2 NOWE1 NOWE0
0
0
0
VCM_
D2
KEY
10
0
VCM_
D1
KEY
9
0
VCM_
D0
KEY
8
0
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reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp.
Page 54 of 113
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a-Si TFT LCD Single Chip Driver
240RGBx320 Resolution and 262K color
ILI9335
8.2.1. Index (IR)
R/W
W
RS
0
D15
-
D14
-
D13
-
D12
-
D11
-
D10
-
D9
-
D8
-
D7
ID7
D6
ID6
D5
ID5
D4
ID4
D3
ID3
D2
ID2
D1
ID1
D0
ID0
The index register specifies the address of register (R00h ~ RFFh) or RAM which will be accessed.
8.2.2. ID code (R00h)
R/W
RO
RS
1
D15
1
D14
0
D13
0
D12
1
D11
0
D10
0
D9
1
D8
1
D7
0
D6
0
D5
1
D4
1
D3
0
D2
1
D1
0
D0
1
D7
0
0
D6
0
0
D5
0
0
D4
0
0
D3
0
0
D2
0
0
D1
0
0
D0
0
0
The device code “9335”h is read out when read this register.
8.2.3. Driver Output Control (R01h)
R/W
RS
W
1
Default
D15
0
0
D14
0
0
D13
0
0
D12
0
0
D11
0
0
D10
SM
0
D9
0
0
D8
SS
0
SS: Select the shift direction of outputs from the source driver.
When SS = 0, the shift direction of outputs is from S1 to S720
When SS = 1, the shift direction of outputs is from S720 to S1.
In addition to the shift direction, the settings for both SS and BGR bits are required to change the
assignment of R, G, B dots to the source driver pins.
To assign R, G, B dots to the source driver pins from S1 to S720, set SS = 0.
To assign R, G, B dots to the source driver pins from S720 to S1, set SS = 1.
When changing SS or BGR bits, RAM data must be rewritten.
SM: Sets the gate driver pin arrangement in combination with the GS bit (R60h) to select the optimal scan
mode for the module.
0
0
Scan Direction
Gate Output Sequence
G1, G2, G3, G4, …,G316
G2 to G320
GS
G1 to G319
SM
G317, G318, G319, G320
The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed,
reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp.
Page 55 of 113
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a-Si TFT LCD Single Chip Driver
240RGBx320 Resolution and 262K color
G320, G319, G318, …,
G2 to G320
1
G1 to G319
0
ILI9335
G6, G5, G4, G3, G2, G1
G1, G3, G5, G7, …,G311
G313, G315, G317, G319
G2 to G320
1
0
G2, G4, G6, G8, …,G312
G1 to G319
G314, G316, G318, G320
G320, G318, G316, …,
G10, G8, G6, G4, G2
G2 to G320
1
1
G319, G317, G315, …,
G1 to G319
G9, G78, G5, G3, G1
The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed,
reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp.
Page 56 of 113
Version: 0.19
a-Si TFT LCD Single Chip Driver
240RGBx320 Resolution and 262K color
ILI9335
8.2.4. LCD Driving Wave Control (R02h)
R/W
RS
W
1
Default
.B/C
D15
0
0
D14
0
0
D13
0
0
D12
0
0
D11
0
0
D10
0
0
D9
B/C
0
D8
0
0
D7
0
0
D6
0
0
D5
0
0
D4
0
0
D3
0
0
D2
0
0
D1
0
0
D0
0
0
0 : Frame/Field inversion
1 : Line inversion
8.2.5. Entry Mode (R03h)
R/W
RS
W
1
Default
D15
TRI
0
D14
DFM
0
D13
0
0
D12
BGR
0
D11
0
0
D10
0
0
D9
0
0
D8
0
0
D7
ORG
0
D6
0
0
D5
I/D1
1
D4
I/D0
1
D3
AM
0
D2
0
0
D1
0
0
D0
0
0
AM Control the GRAM update direction.
When AM = “0”, the address is updated in horizontal writing direction.
When AM = “1”, the address is updated in vertical writing direction.
When a window area is set by registers R50h ~R53h, only the addressed GRAM area is updated based
on I/D[1:0] and AM bits setting.
I/D[1:0] Control the address counter (AC) to automatically increase or decrease by 1 when update one pixel
display data. Refer to the following figure for the details.
I/D[1:0] = 00
I/D[1:0] = 01
I/D[1:0] = 10
I/D[1:0] = 11
Horizontal : decrement
Horizontal : increment
Horizontal : decrement
Horizontal : increment
Vertical : decrement
Vertical : decrement
Vertical : increment
Vertical : increment
E
E
B
B
AM = 0
Horizontal
B
B
E
E
E
E
B
B
AM = 1
Vertical
B
B
E
E
Figure24 GRAM Access Direction Setting
ORG
Moves the origin address according to the ID setting when a window address area is made. This
function is enabled when writing data with the window address area using high-speed RAM write.
ORG = “0”: The origin address is not moved. In this case, specify the address to start write operation
according to the GRAM address map within the window address area.
ORG = “1”: The original address “00000h” moves according to the I/D[1:0] setting.
Notes: 1. When ORG=1, only the origin address address”00000h” can be set in the RAM address set
registers R20h, and R21h.
The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed,
reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp.
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a-Si TFT LCD Single Chip Driver
240RGBx320 Resolution and 262K color
ILI9335
2. In RAM read operation, make sure to set ORG=0.
BGR Swap the R and B order of written data.
BGR=”0”: Follow the RGB order to write the pixel data.
BGR=”1”: Swap the RGB data to BGR in writing into GRAM.
TRI When TRI = “1”, data are transferred to the internal RAM in 8-bit x 3 transfers mode via the 8-bit interface.
It is also possible to send data via the 16-bit interface or SPI in the transfer mode that realizes display in 262k
colors in combination with DFM bits. When not using these interface modes, be sure to set TRI = “0”.
DFM Set the mode of transferring data to the internal RAM when TRI = “1”. See the following figures for
details.
TRI
DFM
16-bit MPU System Interface Data Format
system 16-bit interface (1 transfers/pixel) 65,536 colors
0
*
1st Transfer
DB
17
DB
16
DB
15
DB
14
DB
13
DB
12
DB
11
DB
10
R5
R4
R3
R2
R1
R0
G5
G4
G3
DB
8
DB
7
DB
6
DB
5
DB
4
DB
3
DB
2
DB
1
G2
G1
G0
B5
B4
B3
B2
B1
B0
80-system 16-bit interface (2 transfers/pixel) 262,144 colors
1
0
DB
17
DB
16
DB
15
DB
14
DB
13
DB
12
DB
11
R5
R4
R3
R2
R1
R0
G5
1st Transfer
2nd Transfer
DB DB
17
16
DB
10
DB
8
DB
7
DB
6
DB
5
DB
4
DB
3
DB
2
DB
1
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
80-system 16-bit interface (2 transfers/pixel) 262,144 colors
1
1
1st Transfer
DB DB
2
1
DB
17
DB
16
DB
15
DB
14
DB
13
DB
12
DB
11
R5
R3
R2
R1
R0
G5
G4
G3
R4
2nd Transfer
DB
10
DB
8
DB
7
DB
6
DB
5
DB
4
DB
3
DB
2
DB
1
G2
G1
G0
B5
B4
B3
B2
B1
B0
Figure25 16-bit MPU System Interface Data Format
The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed,
reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp.
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Version: 0.19
a-Si TFT LCD Single Chip Driver
240RGBx320 Resolution and 262K color
TRI
DFM
ILI9335
8-bit MPU System Interface Data Format
system 8-bit interface (2 transfers/pixel) 65,536 colors
0
*
DB
17
DB
16
DB
15
R5
R4
R3
1st Transfer
DB
14
DB
13
DB
12
DB
11
DB
10
R2
R1
R0
G5
G4
G3
DB
17
DB
16
DB
15
G2
G1
2nd Transfer
DB
14
DB
13
DB
12
DB
11
DB
10
G0
B5
B4
B3
B2
B1
B0
80-system 8-bit interface (3 transfers/pixel) 262,144 colors
1
0
1st Transfer
DB DB
11
10
DB
17
DB
16
DB
15
R5
R3
R2
R1
R4
2nd Transfer
DB
14
DB
13
DB
12
DB
11
DB
10
DB
17
DB
16
DB
15
R0
G5
G4
G3
G2
G1
G0
3rd Transfer
DB
14
DB
13
DB
12
DB
11
DB
10
B5
B4
B3
B2
B1
B0
80-system 8-bit interface (3 transfers/pixel) 262,144 colors
1
1
DB
17
DB
16
R5
R4
1st Transfer
DB
15
DB
14
DB
13
DB
12
DB
17
DB
16
R3
R2
R1
R0
G5
G4
2nd Transfer
DB
15
DB
14
DB
13
DB
12
DB
17
DB
16
G3
G2
G1
G0
B5
B4
3rd Transfer
DB
15
DB
14
DB
13
DB
12
B3
B2
B1
B0
Figure26 8-bit MPU System Interface Data Format
The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed,
reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp.
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ILI9335
8.2.6. 16bits Data Format Selection (R05h)
R/W
RS
W
1
Default
D15
0
0
D14
0
0
D13
0
0
D12
0
0
DB15
DB14
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
Read
Data
DB15
DB14
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
Data
Bus
DB15
DB14
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
R4
R3
R2
R1
0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
Read
Data
DB15
DB14
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
Data
Bus
DB15
DB14
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
R4
R3
R2
R1
1
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
Read
Data
DB15
DB14
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
Data
Bus
DB15
DB14
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
Data
Bus
D11
0
0
D10
0
0
D9
0
0
D8
0
0
D7
0
0
D6
0
0
D5
0
0
D4
0
0
D3
0
0
D2
0
0
D1
FPF1
0
D0
EPF0
0
EPF=00
Frame
Data
R5
B0
EPF=01
Frame
Data
R5
0
EPF=10
Frame
Data
R5
EPF=11
Frame
Data
Read
Data
Condition Copy
Condition Copy
R5
1
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
DB15
DB14
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
B0
Input data
Green Data
Green data =
odd
Green data =
even
R=B
R/B Data
R != B
By-pass
G0 is copied to
R0/B0
The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed,
reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp.
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ILI9335
8.2.7. Display Control 1 (R07h)
R/W RS
W
1
Default
D15
0
0
D14
0
0
D13
PTDE1
0
D12
PTDE0
0
D11
0
0
D10
0
0
D9
0
0
D8
BASEE
0
D7
0
0
D6
0
0
D5
GON
0
D4
DTE
0
D3
CL
0
D2
0
0
D1
D1
0
D0
D0
0
D[1:0] Set D[1:0]=”11” to turn on the display panel, and D[1:0]=”00” to turn off the display panel.
A graphics display is turned on the panel when writing D1 = “1”, and is turned off when writing
D1 = “0”.
When writing D1 = “0”, the graphics display data is retained in the internal GRAM and the
ILI9335 displays the data when writing D1 = “1”. When D1 = “0”, i.e. while no display is shown on the
panel, all source outputs becomes the GND level to reduce charging/discharging current, which is
generated within the LCD while driving liquid crystal with AC voltage.
When the display is turned off by setting D[1:0] = “01”, the ILI9335 continues internal display
operation. When the display is turned off by setting D[1:0] = “00”, the ILI9335 internal display
operation is halted completely. In combination with the GON, DTE setting, the D[1:0] setting controls
display ON/OFF.
D1
D0
BASEE
0
0
0
GND
Source, VCOM Output
ILI9335 internal operation
Halt
0
1
1
GND
Operate
1
0
0
Non-lit display
Operate
1
1
0
Non-lit display
Operate
1
1
1
Base image display
Operate
Note: 1. data write operation from the microcontroller is performed irrespective of the setting of D[1:0] bits.
st
2. The D[1:0] setting is valid on both 1 and 2
nd
displays.
3. The non-lit display level from the source output pins is determined by instruction (PTS).
CL When CL = “1”, the 8-color display mode is selected.
CL
Colors
0
262,144
1
8
GON and DTE Set the output level of gate driver G1 ~ G320 as follows
GON
DTE
0
0
VGH
G1 ~G320 Gate Output
0
1
VGH
1
0
VGL
1
1
Normal Display
BASEE
Base image display enable bit. When BASEE = “0”, no base image is displayed. The ILI9335 drives
liquid crystal at non-lit display level or displays only partial images. When BASEE = “1”, the base
image is displayed. The D[1:0] setting has higher priority over the BASEE setting.
PTDE[1:0]
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a-Si TFT LCD Single Chip Driver
240RGBx320 Resolution and 262K color
ILI9335
Partial image 2 and Partial image 1 enable bits
PTDE1/0 = 0: turns off partial image. Only base image is displayed.
PTDE1/0 = 1: turns on partial image. Set the base image display enable bit to 0 (BASEE = 0).
8.2.8. Display Control 2 (R08h)
R/W
RS
W
1
Default
D15
FP7
0
D14
FP6
0
D13
FP5
0
D12
FP4
0
D11
FP3
1
D10
FP2
0
D9
FP1
0
D8
FP0
0
D7
BP7
0
D6
BP6
0
D5
BP5
0
D4
BP4
0
D3
BP3
1
D2
BP2
0
D1
BP1
0
D0
BP0
0
FP[7:0]/BP[7:0]
The FP[7:0] and BP[7:0] bits specify the line number of front and back porch periods respectively.
When setting the FP[7:0] and BP[7:0] value, the following conditions shall be met:
BP + FP ≤ 256 lines
FP ≥ 2 lines
BP ≥ 2 lines
Number of lines for Front
Porch
Number of lines for Back
Porch
00h
Setting Prohibited
Setting Prohibited
01h
Setting Prohibited
Setting Prohibited
02h
2 lines
2 lines
03h
3 lines
3 lines
04h
4 lines
4 lines
05h
5 lines
5 lines
06h
6 lines
6 lines
07h
7 lines
7 lines
08h
8 lines
8 lines
09h
9 lines
9 lines
0Ah
10 lines
10 lines
:
:
:
7Fh
127 lines
127 lines
80h
128 lines
128 lines
81h
Setting Prohibited
Setting Prohibited
:
:
:
FFh
Setting Prohibited
Setting Prohibited
Back Porch
VSYNC
FP[7:0]
/BP[7:0]
Display
Area
Front Porch
Note: The output timing to the LCD is delayed by 2
lines period from the input of synchronizing signal.
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reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp.
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240RGBx320 Resolution and 262K color
ILI9335
8.2.9. Display Control 3 (R09h)
R/W RS
W
1
Default
D15
0
0
D14
0
0
D13
0
0
D12
0
0
D11
0
0
D10
0
0
D9
PTS1
0
D8
PTS0
0
D7
0
0
D6
0
0
D5
PTG1
0
D4
PTG0
0
D3
ISC3
0
D2
ISC2
0
D1
ISC1
0
D0
ISC0
0
ISC[3:0]: Specify the scan cycle interval of gate driver in non-display area when PTG[1:0]=”10” to select
interval scan. Then scan cycle is set as odd number from 0~29 frame periods. The polarity is
inverted every scan cycle.
ISC3
ISC2
ISC1
ISC0
Scan Cycle
fFLM=60 Hz
0
0
0
0
0 frame
-
0
0
0
1
0 frame
-
0
0
1
0
3 frame
50ms
0
0
1
1
5 frame
84ms
0
1
0
0
7 frame
117ms
0
1
0
1
9 frame
150ms
0
1
1
0
11 frame
184ms
0
1
1
1
13 frame
217ms
1
0
0
0
15 frame
251ms
1
0
0
1
17 frame
284ms
1
0
1
0
19 frame
317ms
1
0
1
1
21 frame
351ms
1
1
0
0
23 frame
384ms
1
1
0
1
25 frame
418ms
1
1
1
0
27 frame
451ms
1
1
1
1
29 frame
484ms
PTG[1:0] Set the scan mode in non-display area.
PTG1
PTG0
Gate outputs in non-display area
Source outputs in non-display area
Vcom output
0
0
Normal scan
Set with the PTS[1:0] bits
VcomH/VcomL
0
1
Setting Prohibited
-
-
1
0
Interval scan
Set with the PTS[1:0] bits
VcomH/VcomL
1
1
Setting Prohibited
-
-
PTS[1:0]
Set the source output level in non-display area drive period (front/back porch period and blank area
between partial displays).
When PTS[1] = 1, the operation of amplifiers which generates the grayscales other than V0 and V63
are halted.
Positive polarity
Negative polarity
Grayscale amplifier
in operation
00
V63
V0
V63 to V0
01
Setting Prohibited
Setting Prohibited
-
10
GND
GND
V63 to V0
11
Hi-Z
Hi-Z
V63 to V0
PTS[1:0]
Source output level
Notes: 1. The power efficiency can be improved by halting grayscale amplifiers only in non-display drive period.
2. The gate output level in non-lit display area drive period is determined by PTG[1:0].
The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed,
reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp.
Page 63 of 113
Version: 0.19
a-Si TFT LCD Single Chip Driver
240RGBx320 Resolution and 262K color
ILI9335
8.2.10. Display Control 4 (R0Ah)
R/W
RS
W
1
Default
D15
0
0
D14
0
0
D13
0
0
D12
0
0
D11
0
0
D10
0
0
D9
0
0
D8
0
0
D7
0
0
D6
0
0
D5
0
0
D4
0
0
D3
FMARKOE
0
D2
FMI2
0
D1
FMI1
0
D0
FMI0
0
FMI[2:0] Set the output interval of FMARK signal according to the display data rewrite cycle and data transfer
rate.
FMARKOE When FMARKOE=1, ILI9335 starts to output FMARK signal in the output interval set by FMI[2:0]
bits.
FMI[2:0]
Output Interval
000
1 frame
001
2 frame
011
4 frame
101
6 frame
Others
Setting disabled
8.2.11. RGB Display Interface Control 1 (R0Ch)
R/W RS
W
1
Default
D15
0
0
D14
ENC2
0
D13
ENC1
0
D12
ENC0
0
D11
0
0
D10
0
0
D9
0
0
D8
RM
0
D7
0
0
D6
0
0
D5
DM1
0
D4
DM0
0
D3
0
0
D2
0
0
D1
RIM1
0
D0
RIM0
0
RIM[1:0] Select the RGB interface data width.
RIM1
RIM0
0
0
18-bit RGB interface (1 transfer/pixel), DB[17:0]
RGB Interface Mode
0
1
16-bit RGB interface (1 transfer/pixel), DB[17:13] and DB[11:1]
1
0
6-bit RGB interface (3 transfers/pixel), DB[17:12]
1
1
Setting disabled
Note1: Registers are set only by the system interface.
Note2: Be sure that one pixel (3 dots) data transfer finished when interface switch.
DM[1:0] Select the display operation mode.
DM1
DM0
0
0
Display Interface
0
1
RGB interface
1
0
VSYNC interface
1
1
Setting disabled
Internal system clock
The DM[1:0] setting allows switching between internal clock operation mode and external display
interface operation mode. However, switching between the RGB interface operation mode and the
VSYNC interface operation mode is prohibited.
RM Select the interface to access the GRAM.
Set RM to “1” when writing display data by the RGB interface.
RM
Interface for RAM Access
0
System interface/VSYNC interface
1
RGB interface
The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed,
reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp.
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Version: 0.19
a-Si TFT LCD Single Chip Driver
240RGBx320 Resolution and 262K color
Display State
ILI9335
Operation Mode
RAM Access (RM)
Display Operation Mode (DM[1:0]
Internal clock operation
System interface
(RM = 0)
Internal clock operation
(DM[1:0] = 00)
RGB interface (1)
RGB interface
(RM = 1)
RGB interface
(DM[1:0] = 01)
Rewrite still picture area while RGB interface
Displaying moving pictures.
System interface
(RM = 0)
RGB interface
(DM[1:0] = 01)
Moving pictures
System interface
(RM = 0)
VSYNC interface
(DM[1:0] = 10)
Still pictures
Moving pictures
VSYNC interface
Note 1: Registers are set only via the system interface or SPI interface.
Note 2: Refer to the flowcharts of “RGB Input Interface” section for the mode switch.
ENC[2:0] Set the GRAM write cycle through the RGB interface
ENC[2:0]
GRAM Write Cycle (Frame periods)
000
1 Frame
001
2 Frames
010
3 Frames
011
4 Frames
100
5 Frames
101
6 Frames
110
7 Frames
111
8 Frames
8.2.12. Frame Marker Position (R0Dh)
R/W RS
W
1
Default
D15
0
0
D14
0
0
D13
0
0
D12
0
0
D11
0
0
D10
0
0
D9 D8
D7
D6
D5
D4
D3
D2
D1
D0
0 FMP8 FMP7 FMP6 FMP5 FMP4 FMP3 FMP2 FMP1 FMP0
0
0
0
0
0
0
0
0
0
0
EMP[8:0] Sets the output position of frame cycle (frame marker).
When FMP[8:0]=0, a high-active pulse FMARK is output at the start of back porch period for one display line
period (1H).
Make sure the 9’h000
≦ FMP ≦ BP+NL+FP
FMP[8:0]
FMARK Output Position
9’h000
0th line
9’h001
1st line
9’h002
2nd line
9’h003
3rd line
.
.
.
.
.
.
9’h175
373rd line
9’h176
374th line
9’h177
375th line
The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed,
reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp.
Page 65 of 113
Version: 0.19
a-Si TFT LCD Single Chip Driver
240RGBx320 Resolution and 262K color
ILI9335
8.2.13. RGB Display Interface Control 2 (R0Fh)
R/W
RS
W
1
Default
D15
0
0
D14
0
0
D13
0
0
D12
0
0
D11
0
0
D10
0
0
D9
0
0
D8
0
0
D7
0
0
D6
0
0
D5
0
0
D4
VSPL
0
D3
HSPL
0
D2
0
0
D1
EPL
0
D0
DPL
0
DPL: Sets the signal polarity of the DOTCLK pin.
DPL = “0” The data is input on the rising edge of DOTCLK
DPL = “1” The data is input on the falling edge of DOTCLK
EPL: Sets the signal polarity of the ENABLE pin.
EPL = “0” The data DB17-0 is written when ENABLE = “0”. Disable data write operation when
ENABLE = “1”.
EPL = “1” The data DB17-0 is written when ENABLE = “1”. Disable data write operation when
ENABLE = “0”.
HSPL: Sets the signal polarity of the HSYNC pin.
HSPL = “0” Low active
HSPL = “1” High active
VSPL: Sets the signal polarity of the VSYNC pin.
VSPL = “0” Low active
VSPL = “1” High active
8.2.14. Power Control 1 (R10h)
R/W RS
W
1
Default
D15
0
0
D14
0
0
D13
0
0
D12
SAP
0
D11
0
0
D10
BT2
0
D9
BT1
0
D8
BT0
0
D7
APE
0
D6
AP2
0
D5
AP1
0
D4
AP0
0
D3
0
0
D2
0
0
D1
SLP
0
D0
STB
0
SLP: When SLP = 1, ILI9335 enters the sleep mode and the display operation stops except the RC oscillator
to reduce the power consumption. In the sleep mode, the GRAM data and instructions cannot be
updated except the following instruction.
a. Exit sleep mode (SLP = “0”)
STB: When STB = 1, ILI9335 enters the standby mode and the display operation stops except the GRAM
power supply to reduce the power consumption. In the STB mode, the GRAM data and instructions
cannot be updated except the following instruction.
a. Exit standby mode (STB = “0”)
AP[2:0]: Adjusts the constant current in the operational amplifier circuit in the LCD power supply circuit. The
larger constant current enhances the drivability of the LCD, but it also increases the current
consumption. Adjust the constant current taking the trade-off into account between the display quality
and the current consumption. In no-display period, set AP[2:0] = “000” to halt the operational amplifier
circuits and the step-up circuits to reduce current consumption.
The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed,
reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp.
Page 66 of 113
Version: 0.19
a-Si TFT LCD Single Chip Driver
240RGBx320 Resolution and 262K color
AP[2:0]
Gamma driver amplifiers
Source driver amplifiers
000
Halt
Halt
001
1.00
1.00
010
1.00
0.75
011
1.00
0.50
100
0.75
1.00
101
0.75
0.75
110
0.75
0.50
111
0.50
0.50
ILI9335
SAP: Source Driver output control
SAP=0, Source driver is disabled.
SAP=1, Source driver is enabled.
When starting the charge-pump of LCD in the Power ON stage, make sure that SAP=0, and set the
SAP=1, after starting up the LCD power supply circuit.
APE: Power supply enable bit.
Set APE = “1” to start the generation of power supply according to the power supply startup sequence.
BT[3:0]: Sets the factor used in the step-up circuits.
Select the optimal step-up factor for the operating voltage. To reduce power consumption, set a smaller
factor.
BT[2:0]
DDVDH
VCL
3’h0
VCI1 x 2
- VCI1
3’h1
3’h2
VCI1 x 2
- VCI1
VGH
VGL
VCI1 x 6
- VCI1 x 4
- VCI1 x 5
- VCI1 x 3
3’h3
3’h4
- VCI1 x 5
VCI1 x 2
- VCI1
VCI1 x 5
- VCI1 x 4
3’h5
- VCI1 x 3
3’h6
- VCI1 x 4
3’h7
VCI1 x 2
- VCI1
VCI1 x 4
- VCI1 x 3
Notes: 1. Connect capacitors to the capacitor connection pins when generating DDVDH, VGH, VGL and VCL levels.
2. Make sure DDVDH = 6.0V (max.),
The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed,
reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp.
Page 67 of 113
Version: 0.19
a-Si TFT LCD Single Chip Driver
240RGBx320 Resolution and 262K color
ILI9335
8.2.15. Power Control 2 (R11h)
R/W RS
W
1
Default
D15
0
0
D14
0
0
D13
0
0
D12
0
0
D11
0
0
D10
DC12
1
D9
DC11
1
D8
DC10
1
D7
0
0
D6
DC02
1
D5
DC01
1
D4
DC00
1
D3
0
0
D2
VC2
0
D1
VC1
0
D0
VC0
0
VC[2:0] Sets the ratio factor of VCI to generate the reference voltages VCI1.
VC2
VC1
VC0
VCI1 voltage
0
0
0
0.95 x VCI
0
0
1
0.90 x VCI
0
1
0
0.85 x VCI
0
1
1
0.80 x VCI
1
0
0
0.75 x VCI
1
0
1
0.70 x VCI
1
1
0
Disabled
1
1
1
1.0 x VCI
DC0[2:0]: Selects the operating frequency of the step-up circuit 1. The higher step-up operating frequency
enhances the drivability of the step-up circuit and the quality of display but increases the current
consumption. Adjust the frequency taking the trade-off between the display quality and the current
consumption into account.
DC1[2:0]: Selects the operating frequency of the step-up circuit 2. The higher step-up operating frequency
enhances the drivability of the step-up circuit and the quality of display but increases the current
consumption. Adjust the frequency taking the trade-off between the display quality and the current
consumption into account.
Step-up circuit1
step-up frequency (fDCDC1)
DC12
DC11
DC10
Step-up circuit2
step-up frequency (fDCDC2)
0
Fosc
0
0
0
Fosc / 4
1
Fosc / 2
0
0
1
Fosc / 8
1
0
Fosc / 4
0
1
0
Fosc / 16
0
1
1
Fosc / 8
0
1
1
Fosc / 32
1
0
0
Fosc / 16
1
0
0
Fosc / 64
1
0
1
Fosc / 32
1
0
1
Fosc / 128
1
1
0
Fosc / 64
1
1
0
Fosc / 256
1
1
1
Halt step-up circuit 1
1
1
1
Halt step-up circuit 2
DC02
DC01
DC00
0
0
0
0
0
Note: Be sure fDCDC1≥fDCDC2 when setting DC0[2:0] and DC1[2:0].
The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed,
reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp.
Page 68 of 113
Version: 0.19
a-Si TFT LCD Single Chip Driver
240RGBx320 Resolution and 262K color
ILI9335
8.2.16. Power Control 3 (R12h)
R/W RS
W
1
Default
D15
0
0
D14
0
0
D13
0
0
D12
0
0
D11
0
0
D10
0
0
D9
0
0
D8
0
0
D7
VCIRE
0
D6
0
0
D5
0
0
D4
0
0
D3
VRH3
0
D2
VRH2
0
D1
VRH1
0
D0
VRH0
0
VRH[3:0] Set the amplifying rate (1.6 ~ 1.9) of VCI applied to output the VREG1OUT level, which is a
reference level for the VCOM level and the grayscale voltage level.
VCIRE: Select the external reference voltage VCI or internal reference voltage VCIR.
VCIRE=0
External reference voltage VCI (default)
VCIRE =1
Internal reference voltage 2.5V
VCIRE =0
VCIRE =1
VRH3
VRH2
VRH1
VRH0
VREG1OUT
VRH3
VRH2
VRH1
VRH0
0
0
0
0
0
0
0
0
0
0
0
VREG1OUT
0
Halt
0
0
0
0
Halt
1
VCI x 2.00
0
0
0
1
2.5V x 2.00 = 5.000V
1
0
VCI x 2.05
0
0
1
0
2.5V x 2.05 = 5.125V
1
1
VCI x 2.10
0
0
1
1
2.5V x 2.10 = 5.250V
1
0
0
VCI x 2.20
0
1
0
0
2.5V x 2.20 = 5.500V
0
1
0
1
VCI x 2.30
0
1
0
1
2.5V x 2.30 = 5.750V
0
1
1
0
VCI x 2.40
0
1
1
0
2.5V x 2.40 = 6.000V
0
1
1
1
VCI x 2.40
0
1
1
1
2.5V x 2.40 = 6.000V
1
0
0
0
VCI x 1.60
1
0
0
0
2.5V x 1.60 = 4.000V
1
0
0
1
VCI x 1.65
1
0
0
1
2.5V x 1.65 = 4.125V
1
0
1
0
VCI x 1.70
1
0
1
0
2.5V x 1.70 = 4.250V
1
0
1
1
VCI x 1.75
1
0
1
1
2.5V x 1.75 = 4.375V
1
1
0
0
VCI x 1.80
1
1
0
0
2.5V x 1.80 = 4.500V
1
1
0
1
VCI x 1.85
1
1
0
1
2.5V x 1.85 = 4.625V
1
1
1
0
VCI x 1.90
1
1
1
0
2.5V x 1.90 = 4.750V
1
1
1
1
VCI x 1.95
1
1
1
1
2.5V x 1.95 = 4.875V
When VCI<2.5V, Internal reference voltage will be same as VCI.
Make sure that VC and VRH setting restriction: VREG1OUT
≦ (DDVDH - 0.2)V.
The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed,
reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp.
Page 69 of 113
Version: 0.19
a-Si TFT LCD Single Chip Driver
240RGBx320 Resolution and 262K color
ILI9335
8.2.17. Power Control 4 (R13h)
R/W
RS
W
1
Default
D15
0
0
D14
0
0
D13
0
0
D12
D11
VDV4 VDV3
0
0
D10
VDV2
0
D9
D8
VDV1 VDV0
0
0
D7
0
0
D6
0
0
D5
0
0
D4
0
0
D3
0
0
D2
0
0
D1
0
0
D0
0
0
VDV[4:0] Select the factor of VREG1OUT to set the amplitude of Vcom alternating voltage from 0.70 to 1.24 x
VREG1OUT .
VDV4 VDV3 VDV2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
0
0
1
0
0
1
0
1
0
0
1
0
0
1
0
0
1
0
0
1
1
0
1
1
0
1
1
0
1
1
VDV1 VDV0
0
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
VCOM amplitude
VREG1OUT x 0.70
VREG1OUT x 0.72
VREG1OUT x 0.74
VREG1OUT x 0.76
VREG1OUT x 0.78
VREG1OUT x 0.80
VREG1OUT x 0.82
VREG1OUT x 0.84
VREG1OUT x 0.86
VREG1OUT x 0.88
VREG1OUT x 0.90
VREG1OUT x 0.92
VREG1OUT x 0.94
VREG1OUT x 0.96
VREG1OUT x 0.98
VREG1OUT x 1.00
VDV4 VDV3 VDV2 VDV1 VDV0
1
0
0
0
0
1
0
0
0
1
1
0
0
1
0
1
0
0
1
1
1
0
1
0
0
1
0
1
0
1
1
0
1
1
0
1
0
1
1
1
1
1
0
0
0
1
1
0
0
1
1
1
0
1
0
1
1
0
1
1
1
1
1
0
0
1
1
1
0
1
1
1
1
1
0
1
1
1
1
1
VCOM amplitude
VREG1OUT x 0.94
VREG1OUT x 0.96
VREG1OUT x 0.98
VREG1OUT x 1.00
VREG1OUT x 1.02
VREG1OUT x 1.04
VREG1OUT x 1.06
VREG1OUT x 1.08
VREG1OUT x 1.10
VREG1OUT x 1.12
VREG1OUT x 1.14
VREG1OUT x 1.16
VREG1OUT x 1.18
VREG1OUT x 1.20
VREG1OUT x 1.22
VREG1OUT x 1.24
Set VDV[4:0] to let Vcom amplitude less than 6V.
8.2.18. GRAM Horizontal/Vertical Address Set (R20h, R21h)
R/W
W
W
RS
1
1
Default
D15
0
0
0
0
D14
0
0
0
0
D13
0
0
0
0
D12
0
0
0
0
D11
0
0
0
0
D10
0
0
0
0
D9
0
0
0
0
D8
0
AD16
0
0
D7
AD7
AD15
0
0
D6
AD6
AD14
0
0
D5
AD5
AD13
0
0
D4
AD4
AD12
0
0
D3
AD3
AD11
0
0
D2
AD2
AD10
0
0
D1
AD1
AD9
0
0
D0
AD0
AD8
0
0
AD[16:0] Set the initial value of address counter (AC).
The address counter (AC) is automatically updated in accordance to the setting of the AM, I/D bits
as data is written to the internal GRAM. The address counter is not automatically updated when
read data from the internal GRAM.
AD[16:0]
GRAM Data Map
17’h00000 ~ 17’h000EF
1st line GRAM Data
17’h00100 ~ 17’h001EF
2nd line GRAM Data
17’h00200 ~ 17’h002EF
3rd line GRAM Data
17’h00300 ~ 17’h003EF
4th line GRAM Data
17’h13D00 ~ 17’ h13DEF
318th line GRAM Data
17’h13E00 ~ 17’ h13EEF
319th line GRAM Data
17’h13F00 ~ 17’h13FEF
320th line GRAM Data
Note1: When the RGB interface is selected (RM = “1”), the address AD[16:0] is set to the address counter
every frame on the falling edge of VSYNC.
.
The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed,
reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp.
Page 70 of 113
Version: 0.19
a-Si TFT LCD Single Chip Driver
240RGBx320 Resolution and 262K color
ILI9335
8.2.19. Write Data to GRAM (R22h)
R/W
W
RS
1
D17
D16
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2
RAM write data (WD[17:0], the DB[17:0] pin assignment differs for each interface.
D1
D0
This register is the GRAM access port. When update the display data through this register, the address
counter (AC) is increased/decreased automatically.
8.2.20. Read Data from GRAM (R22h)
R/W
R
RS
1
D17
D16
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2
RAM Read Data (RD[17:0], the DB[17:0] pin assignment differs for each interface.
D1
D0
RD[17:0] Read 18-bit data from GRAM through the read data register (RDR).
18-bit System Interface
GRAM Data &
RGB Mapping
R5
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
Write Data
Register
RD
17
RD
16
RD
15
RD
14
RD
13
RD
12
RD
11
RD
10
RD
9
RD
8
RD
7
RD
6
RD
5
RD
4
RD
3
RD
2
RD
1
RD
0
Output Data
DB
17
DB
16
DB
15
DB
14
DB
13
DB
12
DB
11
DB
10
DB
9
DB
8
DB
7
DB
6
DB
5
DB
4
DB
3
DB
2
DB
1
DB
0
16-bit System Interface
GRAM Data &
RGB Mapping
R5
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
Write Data
Register
RD
17
RD
16
RD
15
RD
14
RD
13
RD
12
RD
11
RD
10
RD
9
RD
8
RD
7
RD
6
RD
5
RD
4
RD
3
RD
2
RD
1
RD
0
Output Data
DB
17
DB
16
DB
15
DB
14
DB
13
DB
12
DB
11
DB
10
DB
8
DB
7
DB
6
DB
5
DB
4
DB
3
DB
2
DB
1
9-bit System Interface
GRAM Data &
RGB Mapping
R5
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
Write Data
Register
RD
17
RD
16
RD
15
RD
14
RD
13
RD
12
RD
11
RD
10
RD
9
RD
8
RD
7
RD
6
RD
5
RD
4
RD
3
RD
2
RD
1
RD
0
Output Data
DB
17
DB
16
DB
15
DB
14
DB
13
DB
12
DB
11
DB
10
DB
9
DB
17
DB
16
DB
15
DB
14
DB
13
DB
12
DB
11
DB
10
DB
9
1st Transfer
2nd Transfer
8-bit System Interface / Serial Data Transfer Interface
GRAM Data &
RGB Mapping
R5
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
Write Data
Register
RD
17
RD
16
RD
15
RD
14
RD
13
RD
12
RD
11
RD
10
RD
9
RD
8
RD
7
RD
6
RD
5
RD
4
RD
3
RD
2
RD
1
RD
0
Output Data
DB
17
DB
16
DB
15
DB
14
DB
13
DB
12
DB
11
DB
10
DB
17
DB
16
DB
15
DB
14
DB
13
DB
12
DB
11
DB
10
1st Transfer
2nd Transfer
Figure 27 Data Read from GRAM through Read Data Register in 18-/16-/9-/8-bit Interface Mode
The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed,
reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp.
Page 71 of 113
Version: 0.19
a-Si TFT LCD Single Chip Driver
240RGBx320 Resolution and 262K color
ILI9335
Set I/D AM, HAS/HEA, VSA/VEA
Set address M
Dummy read (invalid data)
GRAM -> Read data latch
Read Output (data of address M)
Read datalatch -> DB[17:0]
Read Output (data of address M+1)
Read datalatch -> DB[17:0]
Set address N
Dummy read (invalid data)
GRAM -> Read data latch
Read Output (data of address N)
Read datalatch -> DB[17:0]
Figure 28 GRAM Data Read Back Flow Chart
The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed,
reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp.
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240RGBx320 Resolution and 262K color
ILI9335
8.2.21. Power Control 7 (R29h)
R/W
RS
W
1
Default
D15
0
0
D14
0
0
D13
0
0
D12
0
0
D11
0
0
D10
0
0
D9
0
0
D8
0
0
D7
0
0
D6
0
0
D5
D4
D3
D2
D1
D0
VCM5 VCM4 VCM3 VCM2 VCM1 VCM0
0
0
0
0
0
0
VCM[5:0] Set the internal VcomH voltage.
VCM5
VCM4 VCM3 VCM2 VCM1 VCM0
VCOMH
VCM5
VCM4 VCM3 VCM2 VCM1 VCM0
VCOMH
0
0
0
0
0
0
VREG1OUT
x 0.685
1
0
0
0
0
0
VREG1OUT
x 0.845
0
0
0
0
0
1
VREG1OUT
x 0.690
1
0
0
0
0
1
VREG1OUT
x 0.850
0
0
0
0
1
0
VREG1OUT
x 0.695
1
0
0
0
1
0
VREG1OUT
x 0.855
0
0
0
0
1
1
VREG1OUT
x 0.700
1
0
0
0
1
1
VREG1OUT
x 0.860
0
0
0
1
0
0
VREG1OUT
x 0.705
1
0
0
1
0
0
VREG1OUT
x 0.865
0
0
0
1
0
1
VREG1OUT
x 0.710
1
0
0
1
0
1
VREG1OUT
x 0.870
0
0
0
1
1
0
VREG1OUT
x 0.715
1
0
0
1
1
0
VREG1OUT
x 0.875
0
0
0
1
1
1
VREG1OUT
x 0.720
1
0
0
1
1
1
VREG1OUT
x 0.880
0
0
1
0
0
0
VREG1OUT
x 0.725
1
0
1
0
0
0
VREG1OUT
x 0.885
0
0
1
0
0
1
VREG1OUT
x 0.730
1
0
1
0
0
1
VREG1OUT
x 0.890
0
0
1
0
1
0
VREG1OUT
x 0.735
1
0
1
0
1
0
VREG1OUT
x 0.895
0
0
1
0
1
1
VREG1OUT
x 0.740
1
0
1
0
1
1
VREG1OUT
x 0.900
0
0
1
1
0
0
VREG1OUT
x 0.745
1
0
1
1
0
0
VREG1OUT
x 0.905
0
0
1
1
0
1
VREG1OUT
x 0.750
1
0
1
1
0
1
VREG1OUT
x 0.910
0
0
1
1
1
0
VREG1OUT
x 0.755
1
0
1
1
1
0
VREG1OUT
x 0.915
0
0
1
1
1
1
VREG1OUT
x 0.760
1
0
1
1
1
1
VREG1OUT
x 0.920
0
1
0
0
0
0
VREG1OUT
x 0.765
1
1
0
0
0
0
VREG1OUT
x 0.925
0
1
0
0
0
1
VREG1OUT
x 0.770
1
1
0
0
0
1
VREG1OUT
x 0.930
0
1
0
0
1
0
VREG1OUT
x 0.775
1
1
0
0
1
0
VREG1OUT
x 0.935
0
1
0
0
1
1
VREG1OUT
x 0.780
1
1
0
0
1
1
VREG1OUT
x 0.940
0
1
0
1
0
0
VREG1OUT
x 0.785
1
1
0
1
0
0
VREG1OUT
x 0.945
0
1
0
1
0
1
VREG1OUT
x 0.790
1
1
0
1
0
1
VREG1OUT
x 0.950
0
1
0
1
1
0
VREG1OUT
x 0.795
1
1
0
1
1
0
VREG1OUT
x 0.955
0
1
0
1
1
1
VREG1OUT
x 0.800
1
1
0
1
1
1
VREG1OUT
x 0.960
0
1
1
0
0
0
VREG1OUT
x 0.805
1
1
1
0
0
0
VREG1OUT
x 0.965
0
1
1
0
0
1
VREG1OUT
x 0.810
1
1
1
0
0
1
VREG1OUT
x 0.970
0
1
1
0
1
0
VREG1OUT
x 0.815
1
1
1
0
1
0
VREG1OUT
x 0.975
0
1
1
0
1
1
VREG1OUT
x 0.820
1
1
1
0
1
1
VREG1OUT
x 0.980
0
1
1
1
0
0
VREG1OUT
x 0.825
1
1
1
1
0
0
VREG1OUT
x 0.985
0
1
1
1
0
1
VREG1OUT
x 0.830
1
1
1
1
0
1
VREG1OUT
x 0.990
0
1
1
1
1
0
VREG1OUT
x 0.835
1
1
1
1
1
0
VREG1OUT
x 0.995
0
1
1
1
1
1
VREG1OUT
x 0.840
1
1
1
1
1
1
VREG1OUT
x 1.000
8.2.22. Frame Rate and Color Control (R2Bh)
R/W
RS
W
1
Default
D15
0
0
D14
0
0
D13
0
0
D12 D11
0
0
0
0
D10
0
0
D9
0
0
D8
0
0
D7
0
0
D6
0
0
D5
0
0
D4
0
0
D3
D2
D1
D0
FRS3 FRS2 FRS1 FRS0
1
0
1
1
FRS[4:0] Set the frame rate when the internal resistor is used for oscillator circuit.
FRS[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
FRS[3:0]
4’h0
4’h1
4’h2
4’h3
4’h4
4’h5
4’h6
4’h7
4’h8
4’h9
4’hA
4’hB
4’hC
4’hD
4’hE
4’hF
Frame Rate
33
35
37
39
41
44
47
50
55
60
66
73
82
94
Setting Prohibited
Setting Prohibited
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reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp.
Page 73 of 113
Version: 0.19
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ILI9335
8.2.23. Gamma Control (R30h ~ R3Dh)
R30h
R31h
R32h
R35h
R36h
R37h
R38h
R39h
R3Ch
R3Dh
R/W
W
W
W
W
W
W
W
W
W
W
RS
1
1
1
1
1
1
1
1
1
1
D15 D14 D13 D12
D11
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0 VRP1[4] VRP1[3]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0 VRN1[4] VRN1[3]
D10
KP1[2]
KP3[2]
KP5[2]
RP1[2]
VRP1[2]
KN1[2]
KN3[2]
KN5[2]
RN1[2]
VRN1[2]
D9
KP1[1]
KP3[1]
KP5[1]
RP1[1]
VRP1[1]
KN1[1]
KN3[1]
KN5[1]
RN1[1]
VRN1[1]
γfine adjustment register for positive polarity
RP1-0[2:0] : γgradient adjustment register for positive polarity
VRP1-0[4:0] : γamplitude adjustment register for positive polarity
KN5-0[2:0] : γfine adjustment register for negative polarity
RN1-0[2:0] : γgradient adjustment register for negative polarity
VRN1-0[4:0] : γamplitude adjustment register for negative polarity
For details “γ-Correction Function” section.
D8
KP1[0]
KP3[0]
KP5[0]
RP1[0]
VRP1[0]
KN1[0]
KN3[0]
KN5[0]
RN1[0]
VRN1[0]
D7 D6 D5 D4
D3
D2
D1
0 0 0 0
0
KP0[2] KP0[1]
0 0 0 0
0
KP2[2] KP2[1]
0 0 0 0
0
KP4[2] KP4[1]
0 0 0 0
0
RP0[2] RP0[1]
0 0 0 0 VRP0[3] VRP0[2] VRP0[1]
0 0 0 0
0
KN0[2] KN0[1]
0 0 0 0
0
KN2[2] KN2[1]
0 0 0 0
0
KN4[2] KN4[1]
0 0 0 0
0
RN0[2] RN0[1]
0 0 0 0 VRN0[3] VRN0[2] VRN0[1]
D0
KP0[0]
KP2[0]
KP4[0]
RP0[0]
VRP0[0]
KN0[0]
KN2[0]
KN4[0]
RN0[0]
VRN0[0]
KP5-0[2:0] :
8.2.24. Horizontal and Vertical RAM Address Position (R50h, R51h, R52h, R53h)
R50h
R51h
R52h
R53h
R50h
R51h
R52h
R53h
R/W
W
W
W
W
RS
1
1
1
1
Default
D15 D14 D13 D12 D11 D10 D9 D8
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0 VSA8
0
0
0
0
0
0
0 VEA8
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
D7
HSA7
HEA7
VSA7
VEA7
0
1
0
0
D6
HSA6
HEA6
VSA6
VEA6
0
1
0
0
D5
HSA5
HEA5
VSA5
VEA5
0
1
0
1
D4
HSA4
HEA4
VSA4
VEA4
0
0
0
1
D3
HSA3
HEA3
VSA3
VEA3
0
1
0
1
D2
HSA2
HEA2
VSA2
VEA2
0
1
0
1
D1
HSA1
HEA1
VSA1
VEA1
0
1
0
1
D0
HSA0
HEA0
VSA0
VEA0
0
1
0
1
HSA[7:0]/HEA[7:0] HSA[7:0] and HEA[7:0] represent the respective addresses at the start and end of the
window address area in horizontal direction. By setting HSA and HEA bits, it is possible to limit the
area on the GRAM horizontally for writing data. The HSA and HEA bits must be set before starting
RAM write operation. In setting these bits, be sure “00”h ≤ HSA[7:0]< HEA[7:0] ≤ “EF”h. and
“01”h≦HEA-HAS.
VSA[8:0]/VEA[8:0] VSA[8:0] and VEA[8:0] represent the respective addresses at the start and end of the
window address area in vertical direction. By setting VSA and VEA bits, it is possible to limit the
area on the GRAM vertically for writing data. The VSA and VEA bits must be set before starting
RAM write operation. In setting, be sure “000”h ≤ VSA[8:0]< VEA[8:0] ≤ “13F”h.
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reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp.
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Version: 0.19
a-Si TFT LCD Single Chip Driver
240RGBx320 Resolution and 262K color
0000h
HSA
ILI9335
HEA
VSA
Window Address
Area
VEA
GRAM Address Area
13FEFh
Figure 29 GRAM Access Range Configuration
“00”h ≤HSA[7:0] ≤HEA[7:0] ≤”EF”h
“00”h ≤VSA[8:0] ≤VEA[8:0] ≤”13F”h
Note1. The window address range must be within the GRAM address space.
Note2. Data are written to GRAM in four-words when operating in high speed mode, the dummy write
operations should be inserted depending on the window address area. For details, see the High-Speed RAM
Write Function section.
The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed,
reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp.
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Version: 0.19
a-Si TFT LCD Single Chip Driver
240RGBx320 Resolution and 262K color
ILI9335
8.2.25. Gate Scan Control (R60h, R61h, R6Ah)
R60h
R61h
R6Ah
R60h
R61h
R6Ah
R/W
W
W
W
RS
1
1
1
Default
SCN[5:0]
D15
GS
0
0
0
0
0
D14
0
0
0
0
0
0
D13
NL5
0
0
1
0
0
D12
NL4
0
0
0
0
0
D11
NL3
0
0
0
0
0
D10
NL2
0
0
1
0
0
D9
NL1
0
0
1
0
0
D8
NL0
0
VL8
1
0
0
D7
0
0
VL7
0
0
0
D6
D5
D4
D3
D2
D1
D0
0 SCN5 SCN4 SCN3 SCN2 SCN1 SCN0
0
0
0
0
NDL VLE REV
VL6 VL5 VL4 VL3 VL2 VL1 VL0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
The ILI9335 allows to specify the gate line from which the gate driver starts to scan by setting the
SCN[5:0] bits.
Scanning Start Position
SM=0
SCN[5:0]
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
20h
21h
22h
23h
24h
25h
26h
27h
28h ~ 3Fh
SM=1
GS=0
GS=1
GS=0
GS=1
G1
G9
G17
G25
G33
G41
G49
G57
G65
G73
G81
G89
G97
G105
G113
G121
G129
G137
G145
G153
G161
G169
G177
G185
G193
G201
G209
G217
G225
G233
G241
G249
G257
G265
G273
G281
G289
G297
G305
G313
Setting disabled
G320
G312
G304
G296
G288
G280
G272
G264
G256
G248
G240
G232
G224
G216
G208
G200
G192
G184
G176
G168
G160
G152
G144
G136
G128
G120
G112
G104
G96
G88
G80
G72
G64
G56
G48
G40
G32
G24
G16
G8
Setting disabled
G1
G17
G33
G49
G65
G81
G97
G113
G129
G145
G161
G177
G193
G209
G2
G18
G34
G50
G66
G82
G98
G114
G130
G146
G162
G178
G194
G114
G130
G146
G162
G178
G194
G210
G226
G242
G258
G274
G290
G306
Setting disabled
G320
G304
G288
G272
G256
G240
G224
G208
G192
G176
G160
G144
G128
G112
G96
G80
G64
G48
G32
G16
G319
G303
G287
G271
G255
G239
G223
G207
G191
G175
G159
G143
G127
G111
G95
G79
G63
G47
G31
G15
Setting disabled
Note: When SM=1, it is a interlacing scanning. Please reference page 72!
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240RGBx320 Resolution and 262K color
ILI9335
NL[5:0]: Sets the number of lines to drive the LCD at an interval of 8 lines. The GRAM address mapping is
not affected by the number of lines set by NL[5:0]. The number of lines must be the same or more
than the number of lines necessary for the size of the liquid crystal panel.
NL[5:0]
LCD Drive Line
6’h00
8 lines
6’h01
16 lines
6’h02
24lines
…
…
6’h1D
240 lines
6’h1E
248 lines
6’h1F
256 lines
6’h20
264 lines
6’h21
272 lines
6’h22
280 lines
6’h23
288 lines
6’h24
296 lines
6’h25
304 lines
6’h26
312 line
6’h27
320 line
Others
Setting inhibited
NDL: Sets the source driver output level in the non-display area.
NDL
Non-Display Area
Positive Polarity
Negative Polarity
0
V63
V0
1
V0
V63
GS: Sets the direction of scan by the gate driver in the range determined by SCN[4:0] and NL[4:0]. The scan
direction determined by GS = 0 can be reversed by setting GS = 1.
When GS = 0, the scan direction is from G1 to G320.
When GS = 1, the scan direction is from G320 to G1
REV: Enables the grayscale inversion of the image by setting REV=1.
REV
0
1
GRAM Data
18’h00000
.
.
.
18’h3FFFF
18’h00000
.
.
.
18’h3FFFF
Source Output in Display Area
Positive polarity
negative polarity
V63
V0
.
.
.
.
.
.
V0
V63
V0
V63
.
.
.
.
.
.
V63
V0
VLE: Vertical scroll display enable bit. When VLE = 1, the ILI9335 starts displaying the base image from the
line (of the physical display) determined by VL[8:0] bits. VL[8:0] sets the amount of scrolling, which is the
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240RGBx320 Resolution and 262K color
ILI9335
number of lines to shift the start line of the display from the first line of the physical display. Note that the
partial image display position is not affected by the base image scrolling.
The vertical scrolling is not available in external display interface operation. In this case, make sure to
set VLE = “0”.
VLE
Base Image Display
0
Fixed
1
Enable Scrolling
VL[8:0]: Sets the scrolling amount of base image. The base image is scrolled in vertical direction and
displayed from the line determined by VL[8:0]. Make sure that VL[8:0]
≦320.
8.2.26. Partial Image 1 Display Position (R80h)
R/W
RS
D15
D14
D13
D12
D11
D10
D9
W
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Default
D8
PTD
P0[8]
0
D7
PTD
P0[7]
0
D6
PTD
P0[6]
0
D5
PTD
P0[5]
0
D4
PTD
P0[4]
0
D3
PTD
P0[3]
0
D2
PTD
P0[2]
0
D1
PTD
P0[1]
0
D0
PTD
P0[0]
0
PTDP0[8:0]: Sets the display start position of partial image 1. The display areas of the partial images 1 and 2
must not overlap each another.
8.2.27. Partial Image 1 RAM Start/End Address (R81h, R82h)
R/W
RS
D15
D14
D13
D12
D11
D10
D9
W
1
0
0
0
0
0
0
0
W
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Default
D8
PTS
A0[8]
PTE
A0[8]
0
0
D7
PTS
A0[7]
PTE
A0[7]
0
0
D6
PTS
A0[6]
PTE
A0[6]
0
0
D5
PTS
A0[5]
PTE
A0[5]
0
0
D4
PTS
A0[4]
PTE
A0[4]
0
0
D3
PTS
A0[3]
PTE
A0[3]
0
0
D2
PTS
A0[2]
PTE
A0[2]
0
0
D1
PTS
A0[1]
PTE
A0[1]
0
0
D0
PTS
A0[0]
PTE
A0[0]
0
0
PTSA0[8:0] PTEA0[8:0]: Sets the start line address and the end line address of the RAM area storing the
data of partial image 1. Make sure PTSA0[8:0] ≤ PTEA0[8:0].
8.2.28. Partial Image 2 Display Position (R83h)
R/W
RS
D15
D14
D13
D12
D11
D10
D9
W
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Default
D8
D7
PTD PTD
P1[8] P1[7]
0
0
D6
PTD
P1[6]
0
D5
PTD
P1[5]
0
D4
PTD
P1[4]
0
D3
PTD
P1[3]
0
D2
PTD
P1[2]
0
D1
PTD
P1[1]
0
D0
PTD
P1[0]
0
PTDP1[8:0]: Sets the display start position of partial image 2 The display areas of the partial images 1 and 2
must not overlap each another.
8.2.29. Partial Image 2 RAM Start/End Address (R84h, R85h)
R/W
RS
D15
D14
D13
D12
D11
D10
D9
W
1
0
0
0
0
0
0
0
W
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Default
D8
PTS
A1[8]
PTE
A1[8]
0
0
D7
PTS
A1[7]
PTE
A1[7]
0
0
D6
PTS
A1[6]
PTE
A1[6]
0
0
D5
PTS
A1[5]
PTE
A1[5]
0
0
D4
PTS
A1[4]
PTE
A1[4]
0
0
D3
PTS
A1[3]
PTE
A1[3]
0
0
D2
PTS
A1[2]
PTE
A1[2]
0
0
D1
PTS
A1[1]
PTE
A1[1]
0
0
D0
PTS
A1[0]
PTE
A1[0]
0
0
PTSA1[8:0] PTEA1[8:0]: Sets the start line address and the end line address of the RAM area storing the
data of partial image 2 Make sure PTSA1[8:0] ≤ PTEA1[8:0].
The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed,
reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp.
Page 78 of 113
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a-Si TFT LCD Single Chip Driver
240RGBx320 Resolution and 262K color
ILI9335
8.2.30. Panel Interface Control 1 (R90h)
R/W RS
W
1
Default
D15
0
0
D14
0
0
D13
0
0
D12
0
0
D11
0
0
D10
0
0
D9
DIVI1
0
D8
DIVI0
0
D7
0
0
D6
0
0
D5
0
0
D4
RTNI4
1
D3
RTNI3
0
D2
RTNI2
0
D1
RTNI1
0
D0
RTNI0
0
RTNI[4:0]: Sets 1H (line) clock number of internal clock operating mode. In this mode, ILI9335 display
operation is synchronized with internal clock signal.
RTNI[4:0]
00000~01111
10000
10001
10010
10011
10100
10101
10110
10111
Clocks/Line
Setting Disabled
16 clocks
17 clocks
18 clocks
19 clocks
20 clocks
21 clocks
22 clocks
23 clocks
RTNI[4:0]
11000
11001
11010
11011
11100
11101
11110
11111
Clocks/Line
24 clocks
25 clocks
26 clocks
27 clocks
28 clocks
29 clocks
30 clocks
31 clocks
DIVI[1:0]: Sets the division ratio of internal clock frequency.
DIVI1
DIVI0
Division Ratio
Internal Operation Clock Frequency
0
0
1
fosc / 1
0
1
2
fosc / 2
1
0
4
fosc / 4
1
1
8
fosc / 8
8.2.31. Panel Interface Control 2 (R92h)
R/W RS
W
1
Default
D15
0
0
D14
0
0
D13
0
0
D12
0
0
D11
0
0
D10
D9
D8
NOWI[2] NOWI[1] NOWI[0]
1
1
0
D7
0
0
D6
0
0
D5
0
0
D4
0
0
D3
0
0
D2
0
0
D1
0
0
D0
0
0
NOWI[2:0]: Sets the gate output non-overlap period when ILI9335 display operation is synchronized with
internal clock signal.
NOWI[2:0]
000
001
010
011
100
101
110
111
Gate Non-overlap Period
Setting inhibited
1 clocks
2 clocks
3 clocks
4 clocks
5 clocks
6 clocks
Setting inhibited
Note: The gate output non-overlap period is defined by the number of frequency-divided internal clocks, the
frequency of which is determined by instruction (DIVI), from the reference point.
The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed,
reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp.
Page 79 of 113
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ILI9335
8.2.32. Panel Interface Control 4 (R95h)
R/W
RS
W
1
Default
D15
0
0
D14
0
0
D13
0
0
D12
0
0
D11
0
0
D10
0
0
D9
DIVE1
1
D8
DIVE0
0
D7
0
0
D6
0
0
D5
0
0
D4
0
0
D3
0
0
D2
0
0
D1
0
0
D0
0
0
DIVE[1:0]: Sets the division ratio of DOTCLK when ILI9335 display operation is synchronized with RGB
interface signals.
DIVE[1:0]
Division Ratio
18/16-bit RGB Interface
DOTCLK=5MHz
6-bit x 3 Transfers RGB Interface
00
Setting Prohibited
Setting Prohibited
-
Setting Prohibited
DOTCLK=5MHz
01
1/4
4
DOTCLKS
0.8 µs
12
DOTCLKS
0.8 µs
10
1/8
8
DOTCLKS
1.6 µs
24
DOTCLKS
1.6 µs
11
1/16
16
DOTCLKS
3.2 µs
48
DOTCLKS
3.2 µs
-
8.2.33. Panel Interface Control 5 (R97h)
R/W RS
W
1
Default
D15
0
0
D14
0
0
D13
0
0
D12
0
0
D11
D10
D9
D8
NOWE3 NOWE2 NOWE1 NOWE0
1
1
0
0
D7
0
0
D6
0
0
D5
0
0
D4
0
0
D3
0
0
D2
0
0
D1
0
0
D0
0
0
NOWE[3:0]: Sets the gate output non-overlap period when the ILI9335 display operation is synchronized with
RGB interface signals.
NOWE[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
Gate Non-overlap Period
Setting inhibited
1 clocks
2 clocks
3 clocks
4 clocks
5 clocks
6 clocks
7 clocks
NOWE[3:0]
1000
1001
1010
1011
1100
1101
1110
1111
Gate Non-overlap Period
8 clocks
9 clocks
10 clocks
Setting inhibited
Setting inhibited
Setting inhibited
Setting inhibited
Setting inhibited
Note: 1 clock = (number of data transfer/pixel) x DIVE (division ratio) [DOTCLK]
The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed,
reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp.
Page 80 of 113
Version: 0.19
a-Si TFT LCD Single Chip Driver
240RGBx320 Resolution and 262K color
ILI9335
8.2.34. OTP VCM Programming Control (RA1h)
R/W
RS
D15
D14
D13
D12
W
1
0
0
0
0
0
0
0
0
Default
D11
OTP_
PGM_EN
0
D10
D9
D8
D7
D6
0
0
0
0
0
0
0
0
0
0
D5
VCM_
OTP5
0
D4
VCM_
OTP4
0
D3
VCM_
OTP3
0
D2
VCM_
OTP2
0
D1
VCM_
OTP1
0
D0
VCM_
OTP0
0
OTP_PGM_EN: OTP programming enable. When program OTP, must set this bit. OTP data can be
programmed 2 times.
VCM_OTP[5:0]: OTP programming data for VCOMH voltage, the voltage refer to VCM[5:0] value.
8.2.35. OTP VCM Status and Enable (RA2h)
R/W
RS
W
1
Default
D15
PGM_
CNT1
0
D14
PGM_
CNT0
0
D13
VCM_
D5
0
D12
VCM_
D4
0
D11
VCM_
D3
0
D10
VCM_
D2
0
D9
VCM_
D1
0
D8
VCM_
D0
0
D7
D6
D5
D4
D3
D2
D1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
D0
VCM_
EN
0
PGM_CNT[1:0]: OTP programmed record. These bits are read only.
OTP_PGM_CNT[1:0]
00
01
10
11
Description
OTP clean
OTP programmed 1 time
OTP programmed 2 times
OTP programmed 3 times
VCM_D[5:0]: OTP VCM data read value. These bits are read only.
VCM_EN: OTP VCM data enable.
’1’: Set this bit to enable OTP VCM data to replace R29h VCM value.
’0’: Default value, use R29h VCM value.
8.2.36. OTP Programming ID Key (RA5h)
R/W
RS
W
1
Default
D15
KEY
15
0
D14
KEY
14
0
D13
KEY
13
0
D12
KEY
12
0
D11
KEY
11
0
D10
KEY
10
0
D9
KEY
9
0
D8
KEY
8
0
D7
KEY
7
0
D6
KEY
6
0
D5
KEY
5
0
D4
KEY
4
0
D3
KEY
3
0
D2
KEY
2
0
D1
KEY
1
0
D0
KEY
0
0
KEY[15:0]: OTP Programming ID key protection. Before writing OTP programming data RA1h, it must write
RA5h with 0xAA55 value first to make OTP programming successfully. If RA5h is not written with
0xAA55, OTP programming will be fail. See OTP Programming flow.
The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed,
reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp.
Page 81 of 113
Version: 0.19
a-Si TFT LCD Single Chip Driver
240RGBx320 Resolution and 262K color
ILI9335
8.2.37. Deep stand by control (RE6h)
R/W
RS
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
W
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DSTB
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Default
DSTB: When DSTB = 1, the ILI9335 enters the deep standby mode. In deep standby mode, the internal logic
power supply is turned off to reduce power consumption. The GRAM data and instruction setting are not
maintained when the ILI9335 enters the deep standby mode, and they must be reset after exiting deep
standby mode.
Basic operation
The basic operation modes of 9335 are as shown in the following diagram.
The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed,
reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp.
Page 82 of 113
Version: 0.19
a-Si TFT LCD Single Chip Driver
240RGBx320 Resolution and 262K color
ILI9335
CPU interface transition setting sequences
Deep Standby Mode
Display Off Sequence
Enter
deep
standby
mode
Set RE6h:DSTB = 1
Set nCS pin = Low, then
Set nCS pin = High
Set nCS pin = Low, then
Set nCS pin = High
Release
from
deep
standby
Set nCS pin = Low, then
Set nCS pin = High
Set nCS pin = Low, then
Set nCS pin = High
Set nCS pin
low to high x6
Set nCS pin = Low, then
Set nCS pin = High
Set nCS pin = Low, then
Set nCS pin = High
Registers set as default value
ILI9335's register setting
GRAM data setting
Display On Sequence
> 100 n sec
nCS
1
2
3
4
5
6
> 31ms
> 100 n sec
The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed,
reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp.
Page 83 of 113
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a-Si TFT LCD Single Chip Driver
240RGBx320 Resolution and 262K color
ILI9335
9. OTP Programming Flow
V C O M H O T P program m ing F low
S tart
R es et
C hec k
P G M _C N T = 2'b11 ?
Y
N
S et
R E B h= 0 x8010
S upply
D D V D H = 7V
D GN D = GN D
W rite V C M D ata &
E na ble V C M program
R A 1h .= 0 x08 x x
(x x = 6 bit V C M v alue)
S et ID K ey
R A5 h= 0 xA A 55
W ai t for P rogram m ing
A t leas t 10 m s
D is a ble V C M P rogram
R A 1 h.D 11= 1 'b 0
R A 1h = 0x 0000
R em ov e D D V D H
v oltage
C o nfirm O T P v alue
R A 2h. D00 = 1'b1
R A 2h = 0x 0001
R es et
E nd
The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed,
reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp.
Page 84 of 113
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a-Si TFT LCD Single Chip Driver
240RGBx320 Resolution and 262K color
ILI9335
10. GRAM Address Map & Read/Write
ILI9335 has an internal graphics RAM (GRAM) of 172,800 bytes to store the display data and one pixel is
constructed of 18 bits. The GRAM can be accessed through the i80 system, SPI and RGB interfaces.
i80 1818-/1616-bit System Bus Interface Timing
(a) Write to GRAM
nCS
RS
nRD
nWR
DB[17:0]
Write “0022h” to
index register
Write GRAM “data”
Nth pixel
Write GRAM “data”
(N+1)th pixel
Write GRAM “data”
(N+2)th pixel
Write GRAM “data”
(N+3)th pixel
Dummy
Read
1st Read “data”
Nth pixel
2nd Read “data”
(N+1)th pixel
3rd Read “data”
(N+2)th pixel
(b) Read from GRAM
nCS
RS
nRD
nWR
DB[17:0]
Write “0022h” to
index register
i80 99-/8-bit System Bus Interface Timing
(a) Write to GRAM
nCS
RS
nRD
nWR
DB[17:9]
“00h”
“22h”
1st write 1st write
high byte low byte
Nth pixel
2nd write 2nd write
high byte low byte
(N+1)th pixel
3rd write 3rd write
high byte low byte
(N+2)th pixel
Dummy
Read 1
1st read
high byte
2nd read 2nd read
high byte low byte
(b) Read from GRAM
nCS
RS
nRD
nWR
DB[17:9]
“00h”
“22h”
Dummy
Read 2
1st read
low byte
Nth pixel
(N+1)th pixel
Figure30 GRAM Read/Write Timing of i80-System Interface
The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed,
reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp.
Page 85 of 113
Version: 0.19
a-Si TFT LCD Single Chip Driver
240RGBx320 Resolution and 262K color
ILI9335
GRAM address map table of SS=0, BGR=0
SS=0, BGR=0
S1…S3
S4…S6
S7…S9
S10…S12
…
S517…S519
S520…S522
S523…S525
S526…S720
GS=0
GS=1
DB17…0
DB17…0
DB17…0
DB17…0
…
DB17…0
DB17…0
DB17…0
DB17…0
G1
G320
“00000h”
“00001h”
“00002h”
“00003h”
…
“000ECh”
“000Edh”
“000Eeh”
“000Efh”
G2
G319
“00100h”
“00101h”
“00102h”
“00103h”
…
“001Ech”
“001Edh”
“001Eeh”
“001Efh”
G3
G318
“00200h”
“00201h”
“00202h”
“00203h”
…
“002Ech”
“002Edh”
“002Eeh”
“002Efh”
G4
G317
“00300h”
“00301h”
“00302h”
“00303h”
…
“003Ech”
“003Edh”
“003Eeh”
“003Efh”
G5
G316
“00400h”
“00401h”
“00402h”
“00403h”
…
“004Ech”
“004Edh”
“004Eeh”
“004Efh”
G6
G315
“00500h”
“00501h”
“00502h”
“00503h”
…
“005Ech”
“005Edh”
“005Eeh”
“005Efh”
G7
G314
“00600h”
“00601h”
“00602h”
“00603h”
…
“006Ech”
“006Edh”
“006Eeh”
“006Efh”
G8
G313
“00700h”
“00701h”
“00702h”
“00703h”
…
“007Ech”
“007Edh”
“007Eeh”
“007Efh”
G9
G312
“00800h”
“00801h”
“00802h”
“00803h”
…
“008Ech”
“008Edh”
“008Eeh”
“008Efh”
G10
G311
“00900h”
“00901h”
“00902h”
“00903h”
…
“009Ech”
“009Edh”
“009Eeh”
“009Efh”
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
…
.
.
.
.
.
.
.
.
.
.
.
.
G311
G10
“13600h”
“13601h”
“13602h”
“13603h”
…
“136Ech”
“136Edh”
“136Eeh”
“136Efh”
G312
G9
“13700h”
“13701h”
“13702h”
“13703h”
…
“137Ech”
“137Edh”
“137Eeh”
“137Efh”
G313
G8
“13800h”
“13801h”
“13802h”
“13803h”
…
“138Ech”
“138Edh”
“138Eeh”
“138Efh”
G314
G7
“13900h”
“13901h”
“13902h”
“13903h”
…
“139Ech”
“139Edh”
“139Eeh”
“139Efh”
G315
G6
“13A00h”
“13A01h”
“13A02h”
“13A03h”
…
“13AECh”
“13AEDh”
“13AEEh”
“13AEFh”
G316
G5
“13B00h”
“13B01h”
“13B02h”
“13B03h”
…
“13BECh”
“13BEDh”
“13BEEh”
“13BEFh”
G317
G4
“13C00h”
“13C01h”
“13C02h”
“13C03h”
…
“13CECh”
“13CEDh”
“13CEEh”
“13CEFh”
G318
G3
“13D00h”
“13D01h”
“13D02h”
“13D03h”
…
“13DECh”
“13DEDh”
“13DEEh”
“13DEFh”
G319
G2
“13E00h”
“13E01h”
“13E02h”
“13E03h”
…
“13EECh”
“13EEDh”
“13EEEh”
“13EEFh”
G320
G1
“13F00h”
“13F01h”
“13F02h”
“13F03h”
…
“13FECh”
“13FEDh”
“13FEEh”
“13FEFh”
The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed,
reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp.
Page 86 of 113
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ILI9335
i 80/
80/M 68 system 1818-bit data bus inte rfa c e
GRAM Data DB
17
DB
16
DB
15
DB
14
DB
13
DB
12
DB
11
DB
10
DB
9
DB
8
DB
7
DB
6
DB
5
DB
4
DB
3
DB
2
DB
1
DB
0
RGB Assignment R5
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
Source Output Pin
S (3n+1)
S (3n+2)
S (3n+3)
N=0 to 239
i 80/
80/M 68 system 1616-bit data bus inte rfa c e
GRAM Data DB
17
DB
16
DB
15
DB
14
DB
13
DB
12
DB
11
DB
10
RGB Assignment R5
R4
R3
R2
R1
R0
G5
G4
Source Output Pin
S (3n+1)
G3
DB
8
DB
7
DB
6
DB
5
DB
4
DB
3
DB
2
DB
1
G2
G1
G0
B5
B4
B3
B2
B1
S (3n+2)
B0
S (3n+3)
N=0 to 239
i 80/
80/M 68 system 9-bit da ta bus inte rfac e
1st Transfer
2nd Transfer
GRAM Data DB
17
DB
16
DB
15
DB
14
DB
13
DB
12
DB
11
DB
10
DB
9
DB
17
DB
16
DB
15
DB
14
DB
13
DB
12
DB
11
DB
10
DB
9
RGB Assignment R5
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
Source Output Pin
S (3n+1)
S (3n+2)
S (3n+3)
N=0 to 239
GRAM Data and display data of 18-/16-/9-bit system interface (SS=”0", BGR=”0")
Figure31 i80-System Interface with 18-/16-/9-bit Data Bus (SS=”0”, BGR=”0”)
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reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp.
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Version: 0.19
a-Si TFT LCD Single Chip Driver
240RGBx320 Resolution and 262K color
ILI9335
i 80/
80/M 68 system 8 -bit inte rfa c e / SPI Interfa ce (2 tra nsfe rs/
rs/pixe l )
DB
17
DB
16
DB
15
1st transfer
DB DB
14
13
DB
12
DB
11
DB
10
RGB Assignment R5
Source Output Pin
R4
R3
R2
R0
G5
G4
GRAM Data
R1
S (3n +1)
G3
DB
17
DB
16
DB
15
2nd transfer
DB DB
14
13
DB
12
DB
11
DB
10
G2
G1
G0
B5
B3
B2
B1
B4
S (3n +2)
S (3 n+3)
B0
N=0 to 239
i 80/
80/M 68 system 8 -bit inte rfa c e (3 tra nsfers / pixel , TRI =”1 ", DFM [1:0]= ”00")
00 ")
2 nd Transfer
st
1 T r ansfer
3rd Transfer
GRAM Data DB
11
DB
10
DB
17
DB
16
DB
15
DB
14
DB
13
DB
12
DB
11
DB
10
DB
17
DB
16
DB
15
DB
14
DB
13
DB
12
DB
11
DB
10
RGB Assignment R5
Source Output Pin
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
S (3n +1)
S (3n +2)
S (3 n+3)
N=0 to 239
i80/
80/M 68 system 8 -bit inte rfac e (3 tra nsfers / pixel , TRI =” 1", DFM[
DFM[1:0 ]=”
]= ”10 )
1 st Transfer
2 nd Transfer
3 rd Transfer
DB
17
DB
16
DB
15
DB
14
DB
13
DB
12
DB
17
DB
16
DB
15
DB
14
DB
13
DB
12
DB
17
DB
16
DB
15
DB
14
DB
13
DB
12
RGB Assignment R5
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
GRAM Data
Source Output Pin
S (3n +1)
S (3n +2)
i80/
80/M 68 system 8-bit inte rfa c e
S (3 n+3)
N=0 to 239
(SS=” 0", BGR=”0")
Figure32 i80-System Interface with 8-bit Data Bus (SS=”0”, BGR=”0”)
The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed,
reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp.
Page 88 of 113
Version: 0.19
a-Si TFT LCD Single Chip Driver
240RGBx320 Resolution and 262K color
ILI9335
GRAM address map table of SS=1, BGR=1
S720…S718
S717…S715
S714…S712
S711…S709
…
S12…S10
S9…S7
S6…S4
S3…S1
GS=0
SS=1, BGR=1
GS=1
DB17…0
DB17…0
DB17…0
DB17…0
…
DB17…0
DB17…0
DB17…0
DB17…0
G1
G320
“00000h”
“00001h”
“00002h”
“00003h”
…
“000Ech”
“000Edh”
“000Eeh”
“000Efh”
G2
G319
“00100h”
“00101h”
“00102h”
“00103h”
…
“001Ech”
“001Edh”
“001Eeh”
“001Efh”
G3
G318
“00200h”
“00201h”
“00202h”
“00203h”
…
“002Ech”
“002Edh”
“002Eeh”
“002Efh”
G4
G317
“00300h”
“00301h”
“00302h”
“00303h”
…
“003Ech”
“003Edh”
“003Eeh”
“003Efh”
G5
G316
“00400h”
“00401h”
“00402h”
“00403h”
…
“004Ech”
“004Edh”
“004Eeh”
“004Efh”
G6
G315
“00500h”
“00501h”
“00502h”
“00503h”
…
“005Ech”
“005Edh”
“005Eeh”
“005Efh”
G7
G314
“00600h”
“00601h”
“00602h”
“00603h”
…
“006Ech”
“006Edh”
“006Eeh”
“006Efh”
G8
G313
“00700h”
“00701h”
“00702h”
“00703h”
…
“007Ech”
“007Edh”
“007Eeh”
“007Efh”
G9
G312
“00800h”
“00801h”
“00802h”
“00803h”
…
“008Ech”
“008Edh”
“008Eeh”
“008Efh”
G10
G311
“00900h”
“00901h”
“00902h”
“00903h”
…
“009Ech”
“009Edh”
“009Eeh”
“009Efh”
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
…
.
.
.
.
.
.
.
.
.
.
.
.
G311
G10
“13600h”
“13601h”
“13602h”
“13603h”
…
“136Ech”
“136Edh”
“136Eeh”
“136Efh”
G312
G9
“13700h”
“13701h”
“13702h”
“13703h”
…
“137Ech”
“137Edh”
“137Eeh”
“137Efh”
G313
G8
“13800h”
“13801h”
“13802h”
“13803h”
…
“138Ech”
“138Edh”
“138Eeh”
“138Efh”
G314
G7
“13900h”
“13901h”
“13902h”
“13903h”
…
“139Ech”
“139Edh”
“139Eeh”
“139Efh”
G315
G6
“13A00h”
“13A01h”
“13A02h”
“13A03h”
…
“13AECh”
“13AEDh”
“13AEEh”
“13AEFh”
G316
G5
“13B00h”
“13B01h”
“13B02h”
“13B03h”
…
“13BECh”
“13BEDh”
“13BEEh”
“13BEFh”
G317
G4
“13C00h”
“13C01h”
“13C02h”
“13C03h”
…
“13CECh”
“13CEDh”
“13CEEh”
“13CEFh”
G318
G3
“13D00h”
“13D01h”
“13D02h”
“13D03h”
…
“13DECh”
“13DEDh”
“13DEEh”
“13DEFh”
G319
G2
“13E00h”
“13E01h”
“13E02h”
“13E03h”
…
“13EECh”
“13EEDh”
“13EEEh”
“13EEFh”
G320
G1
“13F00h”
“13F01h”
“13F02h”
“13F03h”
…
“13FECh”
“13FEDh”
“13FEEh”
“13FEFh”
i 8 0 /M 68 sy s tem 18 - bit da ta bus inte rfac e
GR AM Data
DB
17
DB
16
DB
15
DB
14
DB
13
DB
12
DB
11
DB
10
DB
9
DB
8
DB
7
DB
6
DB
5
DB
4
DB
3
DB
2
DB
1
DB
0
RGB Assignment
R5
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
S ource Output P in
S (720 -3n)
S (719 -3n)
S (718-3n )
N=0 to 239
i 8 0 /M 68 sy s tem 9 - bit data bus in terfa ce
1 st Tr a nsfer
2n d Tra nsfer
GR AM Data
DB
17
DB
16
DB
15
DB
14
DB
13
DB
12
DB
11
DB
10
DB
9
DB
17
DB
16
DB
15
DB
14
DB
13
DB
12
DB
11
DB
10
DB
9
RGB Assignment
R5
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
S ource Output P in
S (720 -3n)
S (719 -3n)
S (718-3n )
N=0 to 239
G RA M D ata and display data of 18-/9-bit system interface ( SS=” 1", BG R=”1")
Figure 33 i80-System Interface with 18-/9-bit Data Bus (SS=”1”, BGR=”1”)
The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed,
reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp.
Page 89 of 113
Version: 0.19
a-Si TFT LCD Single Chip Driver
240RGBx320 Resolution and 262K color
ILI9335
11. Window Address Function
The window address function enables writing display data consecutively in a rectangular area (a window
address area) made on the internal RAM. The window address area is made by setting the horizontal address
register (start: HSA[7:0], end: HEA[7:0] bits) and the vertical address register (start: VSA[8:0], end: VEA[8:0]
bits). The AM bit sets the transition direction of RAM address (either increment or decrement). These bits
enable the ILI9335 to write data including image data consecutively not taking data wrap positions into
account.
The window address area must be made within the GRAM address map area. Also, the GRAM address bits
(RAM address set register) must be an address within the window address area.
[Window address setting area]
(Horizontal direction) 00H ≤ HSA[7:0] ≤ HEA[7:0] ≤ “EF”H
(Vertical direction) 00H ≤ VSA[8:0] ≤ VEA[8:0]≤ “13F”H
[RAM address, AD (an address within a window address area)]]
(RAM address) HSA[7:0] ≤ AD[7:0] ≤ HEA[7:0]
VSA[8:0] ≤ AD[15:8] ≤ VEA[8:0]
GRAM Address Map
“00000”
h
“000EF”h
Window Address Area
2010h
203Fh
2110h
213Fh
4F10h
4F3Fh
“13F00”h
Window address setting area
HSA[7:0] = 10h, HEA[7:0] = 3Fh, I/D = 1 (increment)
VSA[8:0] = 20h, VEA[8:0] = 4Fh, AM = 0 (horizontal writing )
“13FEF”h
Figure 34 GRAM Access Window Map
The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed,
reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp.
Page 90 of 113
Version: 0.19
a-Si TFT LCD Single Chip Driver
240RGBx320 Resolution and 262K color
ILI9335
12. Gamma Correction
ILI9335 incorporates the γ-correction function to display 262,144 colors for the LCD panel. The γ-correction is
performed with 3 groups of registers determining eight reference grayscale levels, which are gradient
adjustment, amplitude adjustment and fine-adjustment registers for positive and negative polarities, to make
ILI9335 available with liquid crystal panels of various characteristics.
VREG1OUT
Gradient
Adjustment
Register
PRP/N0
PRP/N1
Fine Adjustment Registers (6 x 3 bits)
PKP/N5 PKP/N4 PKP/N3 PKP/N2 PKP/N1 PKP/N0
Amplitude
Adjustment
Register
VRP/N0
VRP/N1
VgP0/VgN0
1
to
8
n
o
tic
e
l
e
s
V0
VgP1/VgN1
V1
V2
..
…
1
to
8
n
o
tic
e
l
e
s
n
1 tio
to cle
8 e
s
1
o
t
8
1
to
8
n
o
i
ct
e
le
s
n
tio
c
le
e
s
VgP8/VgN8
VgP20/VgN20
VgP43/VgN43
VgP55/VgN55
.
…
..
…
..
…
V7
V8
V20
V43
V55
V56
..…
1
o
t
8
n
io
cte
le
s
VgP62/VgN62
VgP63/VgN63
V61
V62
V63
VGS
Figure 35 Grayscale Voltage Generation
The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed,
reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp.
Page 91 of 113
Version: 0.19
a-Si TFT LCD Single Chip Driver
240RGBx320 Resolution and 262K color
ILI9335
1
to
8
n
io
tc
e
le
S
1
to
8
n
io
tc
e
le
S
1
o
t
8
n
io
tc
e
le
S
1
o
t
8
n
io
tc
e
le
S
1
o
t
8
n
io
tc
e
l
e
S
1
o
t
8
n
io
tc
e
l
e
S
1
to
8
n
o
tic
e
le
S
1
to
8
n
o
tic
e
le
S
1
to
8
n
o
tic
e
le
S
1
to
8
n
o
tic
e
le
S
1
o
t
8
n
io
tc
e
le
S
1
o
t
8
n
io
tc
e
le
S
Figure 36 Grayscale Voltage Adjustment
The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed,
reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp.
Page 92 of 113
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a-Si TFT LCD Single Chip Driver
240RGBx320 Resolution and 262K color
4-
ILI9335
Gradient adjustment registers
The gradient adjustment registers are used to adjust the gradient of the curve representing the relationship
between the grayscale and the grayscale reference voltage level. To adjust the gradient, the resistance
values of variable resistors in the middle of the ladder resistor are adjusted by registers PRP0[2:0]/PRN0[2:0],
PRP1[2:0]/PRN1[2:0]. The registers consist of positive and negative polarity registers, allowing asymmetric
drive.
4-
Amplitude adjustment registers
The amplitude adjustment registers, VRP0[3:0]/VRN0[3:0], VRP1[4:0]/VRN1[4:0], are used to adjust the
amplitude of grayscale voltages. To adjust the amplitude, the resistance values of variable resistors at the top
and bottom of the ladder resistor are adjusted. Same as the gradient registers, the amplitude adjustment
registers consist of positive and negative polarity registers.
4-
Fine adjustment registers
The fine adjustment registers are used to fine-adjust grayscale voltage levels. To fine-adjust grayscale
voltage levels, fine adjustment registers adjust the reference voltage levels, 8 levels for each register
generated from the ladder resistor, in respective 8-to-1 selectors. Same with other registers, the fine
adjustment registers consist of positive and negative polarity registers.
eg
alt
ov
lea
cs
ya
r
G
eg
alt
ov
lea
cs
ya
rG
Gradient adjustment
eg
alt
ov
lea
cs
ya
rG
Amplitude adjustment
Fine adjustment
Figure 37 Gamma Curve Adjustment
Register Groups
Gradient
adjustment
Amplitude
adjustment
Fine adjustment
Positive Polarity
Negative Polarity
Description
PRP0 [2:0]
PRN0 [2:0]
Variable resistor VRCP0, VRCN0
PRP1 [2:0]
PRN1 [2:0]
Variable resistor VRCP1, VRCN1
VRP0 [3:0]
VRN0 [3:0]
Variable resistor VROP0, VRON0
VRP1 [4:0]
VRN1 [4:0]
Variable resistor VROP1, VRON1
KP0 [2:0]
KN0 [2:0]
8-to-1 selector (voltage level of grayscale 1)
KP1 [2:0]
KN1 [2:0]
8-to-1 selector (voltage level of grayscale 8)
KP2 [2:0]
KN2 [2:0]
8-to-1 selector (voltage level of grayscale 20)
KP3 [2:0]
KN3 [2:0]
8-to-1 selector (voltage level of grayscale 43)
KP4 [2:0]
KN4 [2:0]
8-to-1 selector (voltage level of grayscale 55)
KP5 [2:0]
KN5 [2:0]
8-to-1 selector (voltage level of grayscale 62)
The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed,
reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp.
Page 93 of 113
Version: 0.19
a-Si TFT LCD Single Chip Driver
240RGBx320 Resolution and 262K color
ILI9335
Ladder resistors and 8-to-1 selector Block configuration
The reference voltage generating block consists of two ladder resistor units including variable resistors and
8-to-1 selectors. Each 8-to-1 selector selects one of the 8 voltage levels generated from the ladder resistor
unit to output as a grayscale reference voltage. Both variable resistors and 8-to-1 selectors are controlled
according to the γ-correction registers. This unit has pins to connect a volume resistor externally to
compensate differences in various characteristics of panels.
Variable resistors
ILI9335 uses variable resistors of the following three purposes: gradient adjustment (VRCP(N)0/VRCP(N)1);
amplitude adjustment (1) (VROP(N)0); and the amplitude adjustment (2) (VROP(N)1). The resistance values
of these variable resistors are set by gradient adjustment registers and amplitude adjustment registers as
follows.
Gradient adjustment
Amplitude adjustment (1)
Amplitude adjustment (2)
PRP(N)0/1[2:0]
Register
VRCP(N)0/1
Resistance
VRP(N)0[3:0]
Register
VROP(N)0
Resistance
VRP(N)1[4:0]
Register
VROP(N)1
Resistance
000
0R
0000
0R
00000
0R
001
4R
0001
2R
00001
1R
010
8R
0010
4R
00010
2R
011
12R
:
:
:
:
100
16R
:
:
:
:
101
20R
1101
26R
11101
29R
110
24R
1111
28R
11110
30R
111
28R
1111
30R
11111
31R
8-to-1 selectors
The 8-to-1 selector selects one of eight voltage levels generated from the ladder resistor unit according to the
fine adjustment register and output the selected voltage level as a reference grayscale voltage (VgP(N)1~6).
The table below shows the setting in the fine adjustment register and the selected voltage levels for
respective reference grayscale voltages.
Fine adjustment registers and selected voltage
Register
Selected Voltage
KP(N)[2:0]
VgP(N)1
VgP(N)8
VgP(N)20
VgP(N)43
VgP(N)55
VgP(N)62
000
VP(N)1
VP(N)9
VP(N)17
VP(N)25
VP(N)33
VP(N)41
001
VP(N)2
VP(N)10
VP(N)18
VP(N)26
VP(N)34
VP(N)42
010
VP(N)3
VP(N)11
VP(N)19
VP(N)27
VP(N)35
VP(N)43
011
VP(N)4
VP(N)12
VP(N)20
VP(N)28
VP(N)36
VP(N)44
100
VP(N)5
VP(N)13
VP(N)21
VP(N)29
VP(N)37
VP(N)45
101
VP(N)6
VP(N)14
VP(N)22
VP(N)30
VP(N)38
VP(N)46
110
VP(N)7
VP(N)15
VP(N)23
VP(N)31
VP(N)39
VP(N)47
111
VP(N)8
VP(N)16
VP(N)24
VP(N)32
VP(N)40
VP(N)48
The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed,
reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp.
Page 94 of 113
Version: 0.19
a-Si TFT LCD Single Chip Driver
240RGBx320 Resolution and 262K color
ILI9335
Fine adjustment registers and selected resistor
Register
Selected Resistor
KP(N)[2:0]
RMP(N)0
RMP(N)1
RMP(N)2
RMP(N)3
RMP(N)4
RMP(N)5
000
0R
0R
0R
0R
0R
0R
001
4R
1R
1R
1R
1R
4R
010
8R
2R
2R
2R
2R
8R
011
12R
3R
3R
3R
3R
12R
100
16R
4R
4R
4R
4R
16R
101
20R
5R
5R
5R
5R
20R
110
24R
6R
6R
6R
6R
24R
111
28R
7R
7R
7R
7R
28R
VP1
VP2
VP3
VP4
VP5
VP6
VP7
VP8
KP0[2:0]=010
{
{
4Rx7=28R
RP1
RP2
RP3
RP4
RP5
RP6
RP7
RMP0=8R
VgP1=VP3
Figure 38 Example of RMP(N)0~5 definition
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a-Si TFT LCD Single Chip Driver
240RGBx320 Resolution and 262K color
ILI9335
Gamma correction resister ratio
Data
Positive polarity output voltage
Negative polarity output voltage
00h
VP0
(VgP0)
VN0
(VgN0)
01h
VP1
(VgP1)
VN1
(VgN1)
02h
VP2
(VP8+(VP1-VP8)*(30/48))
VN2
(VN8+(VN1-VN8)*(30/48))
03h
VP3
(VP8+(VP1-VP8)*(23/48))
VN3
(VN8+(VN1-VN8)*(23/48))
04h
VP4
(VP8+(VP1-VP8)*(16/48))
VN4
(VN8+(VN1-VN8)*(16/48))
05h
VP5
(VP8+(VP1-VP8)*(12/48))
VN5
(VN8+(VN1-VN8)*(12/48))
06h
VP6
(VP8+(VP1-VP8)*(8/48))
VN6
(VN8+(VN1-VN8)*(8/48))
07h
VP7
(VP8+(VP1-VP8)*(4/48))
VN7
(VN8+(VN1-VN8)*(4/48))
08h
VP8
(VgP8)
VN8
(VgN8)
09h
VP9
VP20+(VP8-VP20)*(22/24)
VN9
VN20+(VN8-VN20)*(22/24)
0Ah
VP10
VP20+(VP8-VP20)*(20/24)
VN10
VN20+(VN8-VN20)*(20/24)
0Bh
VP11
VP20+(VP8-VP20)*(18/24)
VN11
VN20+(VN8-VN20)*(18/24)
0Ch
VP12
VP20+(VP8-VP20)*(16/24)
VN12
VN20+(VN8-VN20)*(16/24)
0Dh
VP13
VP20+(VP8-VP20)*(14/24)
VN13
VN20+(VN8-VN20)*(14/24)
0Eh
VP14
VP20+(VP8-VP20)*(12/24)
VN14
VN20+(VN8-VN20)*(12/24)
0Fh
VP15
VP20+(VP8-VP20)*(10/24)
VN15
VN20+(VN8-VN20)*(10/24)
10h
VP16
VP20+(VP8-VP20)*(8/24)
VN16
VN20+(VN8-VN20)*(8/24)
11h
VP17
VP20+(VP8-VP20)*(6/24)
VN17
VN20+(VN8-VN20)*(6/24)
12h
VP18
VP20+(VP8-VP20)*(4/24)
VN18
VN20+(VN8-VN20)*(4/24)
13h
VP19
VP20+(VP8-VP20)*(2/24)
VN19
VN20+(VN8-VN20)*(2/24)
14h
VP20
(VgP20)
VN20
(VgN20)
15h
VP21
(VP43+(VP20-VP43)*(22/23))
VN21
(VN43+(VN20-VN43)*(22/23))
16h
VP22
(VP43+(VP20-VP43)*(21/23))
VN22
(VN43+(VN20-VN43)*(21/23))
17h
VP23
(VP43+(VP20-VP43)*(20/23))
VN23
(VN43+(VN20-VN43)*(20/23))
18h
VP24
(VP43+(VP20-VP43)*(19/23))
VN24
(VN43+(VN20-VN43)*(19/23))
19h
VP25
(VP43+(VP20-VP43)*(18/23))
VN25
(VN43+(VN20-VN43)*(18/23))
1Ah
VP26
(VP43+(VP20-VP43)*(17/23))
VN26
(VN43+(VN20-VN43)*(17/23))
1Bh
VP27
(VP43+(VP20-VP43)*(16/23))
VN27
(VN43+(VN20-VN43)*(16/23))
1Ch
VP28
(VP43+(VP20-VP43)*(15/23))
VN28
(VN43+(VN20-VN43)*(15/23))
1Dh
VP29
(VP43+(VP20-VP43)*(14/23))
VN29
(VN43+(VN20-VN43)*(14/23))
1Eh
VP30
(VP43+(VP20-VP43)*(13/23))
VN30
(VN43+(VN20-VN43)*(13/23))
1Fh
VP31
(VP43+(VP20-VP43)*(12/23))
VN31
(VN43+(VN20-VN43)*(12/23))
The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed,
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Data
Positive polarity output voltage
ILI9335
Negative polarity output voltage
20h
VP32
(VP43+(VP20-VP43)*(11/23))
VN32
(VN43+(VN20-VN43)*(11/23))
21h
VP33
(VP43+(VP20-VP43)*(10/23))
VN33
(VN43+(VN20-VN43)*(10/23))
22h
VP34
(VP43+(VP20-VP43)*(9/23))
VN34
(VN43+(VN20-VN43)*(9/23))
23h
VP35
(VP43+(VP20-VP43)*(8/23))
VN35
(VN43+(VN20-VN43)*(8/23))
24h
VP36
(VP43+(VP20-VP43)*(7/23))
VN36
(VN43+(VN20-VN43)*(7/23))
25h
VP37
(VP43+(VP20-VP43)*(6/23))
VN37
(VN43+(VN20-VN43)*(6/23))
26h
VP38
(VP43+(VP20-VP43)*(5/23))
VN38
(VN43+(VN20-VN43)*(5/23))
27h
VP39
(VP43+(VP20-VP43)*(4/23))
VN39
(VN43+(VN20-VN43)*(4/23))
28h
VP40
(VP43+(VP20-VP43)*(3/23))
VN40
(VN43+(VN20-VN43)*(3/23))
29h
VP41
(VP43+(VP20-VP43)*(2/23))
VN41
(VN43+(VN20-VN43)*(2/23))
2Ah
VP42
(VP43+(VP20-VP43)*(1/23))
VN42
(VN43+(VN20-VN43)*(1/23))
2Bh
VP43
(VgP43)
VN43
(VgN43)
2Ch
VP44
(VP55+(VP43-VP55)*(22/24))
VN44
(VN55+(VN43-VN55)*(22/24))
2Dh
VP45
(VP55+(VP43-VP55)*(20/24))
VN45
(VN55+(VN43-VN55)*(20/24))
2Eh
VP46
(VP55+(VP43-VP55)*(18/24))
VN46
(VN55+(VN43-VN55)*(18/24))
2Fh
VP47
(VP55+(VP43-VP55)*(16/24))
VN47
(VN55+(VN43-VN55)*(16/24))
30h
VP48
(VP55+(VP43-VP55)*(14/24))
VN48
(VN55+(VN43-VN55)*(14/24))
31h
VP49
(VP55+(VP43-VP55)*(12/24))
VN49
(VN55+(VN43-VN55)*(12/24))
32h
VP50
(VP55+(VP43-VP55)*(10/24))
VN50
(VN55+(VN43-VN55)*(10/24))
33h
VP51
(VP55+(VP43-VP55)*(8/24))
VN51
(VN55+(VN43-VN55)*(8/24))
34h
VP52
(VP55+(VP43-VP55)*(6/24))
VN52
(VN55+(VN43-VN55)*(6/24))
35h
VP53
(VP55+(VP43-VP55)*(4/24))
VN53
(VN55+(VN43-VN55)*(4/24))
36h
VP54
(VP55+(VP43-VP55)*(2/24))
VN54
(VN55+(VN43-VN55)*(2/24))
37h
VP55
(VgP55)
VN55
(VgN55)
38h
VP56
(VP62+(VP55-VP62)*(44/48))
VN56
(VN62+(VN55-VN62)*(44/48))
39h
VP57
(VP62+(VP55-VP62)*(40/48))
VN57
(VN62+(VN55-VN62)*(40/48))
3Ah
VP58
(VP62+(VP55-VP62)*(36/48))
VN58
(VN62+(VN55-VN62)*(36/48))
3Bh
VP59
(VP62+(VP55-VP62)*(32/48))
VN59
(VN62+(VN55-VN62)*(32/48))
3Ch
VP60
(VP62+(VP55-VP62)*(25/48))
VN60
(VN62+(VN55-VN62)*(25/48))
3Dh
VP61
(VP62+(VP55-VP62)*(18/48))
VN61
(VN62+(VN55-VN62)*(18/48))
3Eh
VP62
(VgP62)
VN62
(VgN62)
3Fh
VP63
(VgP63)
VN63
(VgN63)
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reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp.
Page 97 of 113
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240RGBx320 Resolution and 262K color
ILI9335
S o ur c e
D r ive r
O u tp ut
(S [ 7 20 : 1] )
VC OM
N e ga tiv e po la rity
P os tiv e po larity
Figure 39 Relationship between Source Output and VCOM
V0
N egativ e Polarity
sl
ev
e
Lt
put
u
O
ec
ru
oS
Positive Polarity
V 63
000000
G RA M Dat a
111111
Figure 40 Relationship between GRAM Data and Output Level
The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed,
reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp.
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ILI9335
13. Application
13.1. Configuration of Power Supply Circuit
1
1
0
……
……
2
0
3
0
4
0
5
0
6
0
7
0
8
0
1
0
0
1
1
0
1
2
0
ILI9335
Face Up
(Bump View)
9
0
.…
…
……
……
…
…
1
3
0
1
4
0
1
5
0
1
6
0
1
7
0
1
8
0
1
9
0
.…
…
……
……
…
…
2
0
0
2
1
0
2
2
0
2
3
0
2
4
0
…
……
…
2
5
0
2
6
0
Figure 41 Power Supply Circuit Block
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reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp.
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ILI9335
The following table shows specifications of external elements connected to the ILI9335’s power supply circuit.
Items
Capacity
1 µF (B characteristics)
Recommended Specification
Pin connection
6.3V
VREG1OUT,VDD, VCL, C11A/B, C13 A/B,
10V
25V
DDVDH, C21 A/B, C22 A/B
VGH, VGL
The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed,
reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp.
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ILI9335
13.2. Display ON/OFF Sequence
Display Off Flow
Display On Flow
Display OFF
Power Setting
GON = 1
DTE = 1
D[1:0] = 01
Set SAP=1
Display On
Wait for 2 frames
or more
GON = 0
DTE = 0
D[1:0] = 01
Display OFF
GON = 1
DTE = 1
D[1:0] = 00
Wait for 2 frames
or more
Display On
Wait for 2 frames
or more
GON = 1
DTE = 0
D[1:0] = 01
Display OFF
GON = 0
DTE = 0
D[1:0] = 00
Display On
Display Supply Off
Wait for 2 frames
or more
GON = 1
DTE = 0
D[1:0] = 11
SAP = 0
AP[2:0] = 000
PON = 0
Display On
GON = 1
DTE = 1
D[1:0] = 11
Display Off
Display ON
Figure 42 Display On/Off Register Setting Sequence
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reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp.
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ILI9335
13.3. Standby and Sleep Mode
Standby
Sleep
Display Off Sequence
Display Off Sequence
Set Standby (S TB = 1)
Set Sleep (SLP = 1)
Release from Standby
(STB = 0)
Release
from
standby
R10 ? 0190h
Release from S leep
(SLP = 0)
R10
Release
from
Sleep
← 0190h
80ms or more
Stabilizing time
80ms or more
Stabilizing time
Display On Sequence
Display On Sequence
Figure 43 Standby/Sleep Mode Register Setting Sequence
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reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp.
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ILI9335
13.4. Power Supply Configuration
When supplying and cutting off power, follow the sequence below. The setting time for step-up circuits and
operational amplifiers depends on external resistance and capacitance.
VCI
VCI
IOVCC
IOVCC
GND
Display OFF
Sequence
or VCI, IOV CC Simultaneously
Power On Reset
and
Display OFF
LCD Power
Supply ON
Sequence
Registers setting before
power supply startup
Display ON Setting
DTE=1
D[1:0]=11
GON=1
Normal Display
Power Supply ON (VCC, VCI, IOV CC)
Display OFF Setting
DTE = 0
D[1:0] = 00
GON = 0
PON = 0
Power supply initial setting
Set VC[2:0], VRH[3:0], VCM[5;0 ],
VDV[5: 0], PON=0,BT[2:0] = 000
50 ms or more
S tabilizing time
Display OFF
Power Supply Halt
Setting
SAP =0
AP[2:0] =000
PON = 0
Power Supply OF F (VCC, VCI, IOV CC )
IOV CC
Registers setting for
power supply startup
80ms or more
Step-up circuit
stabilizing time
Power supply operation setting
Set BT[2:0],PON = 1,
Set AP[2:0],APE=1,
Set DC1[2:0], DC0[2:0]
IOVCC
VCI
GND
VCI
Or IOV CC, VCI Simultaneously
Power OFF Sequence
Operational
Amplifier
stabilizing time
Set the other registers
Display ON
Sequence
Set SAP=1
Display ON
DTE=1
D[1:0]=11
GON =1
Power ON Sequence
Figure 44 Power Supply ON/OFF Sequence
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reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp.
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ILI9335
13.5. Voltage Generation
The pattern diagram for setting the voltages and the waveforms of the voltages of the ILI9335 are as follows.
BT
VGH
VGH (+9 ~ 16.5V)
DDVDH
VLCD (4.5 ~ 5.5V)
VRH
VREG1OUT (3.0 ~ (VLCD-0.5)V )
VCM
Vci
(2 .5 ~ 3.3 V)
VCOMH (3.0 ~ (VLCD-0.5)V )
VDV
VC[
VC[2 :0]
VCI1
VCI1
VCOML (VCL+0.5) ~ -1V )
VCL
BT
VGL
VCL (0 ~ -3.3V)
VGL (-4.0 ~ -16.5V)
Figure 45 Voltage Configuration Diagram
Note: The DDVDH, VGH, VGL, and VCL output voltage levels are lower than their theoretical levels (ideal
voltage levels) due to current consumption at respective outputs. The voltage levels in the following
relationships (DDVDH – VREG1OUT ) > 0.2V and (VCOML – VCL) > 0.5V are the actual voltage levels.
When the alternating cycles of VCOM are set high (e.g. the polarity inverts every line cycle), current
consumption is large. In this case, check the voltage before use.
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reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp.
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ILI9335
13.6. Applied Voltage to the TFT panel
VGH
Gate
Output
VCOM
Source
output
VGL
Figure 46 Voltage Output to TFT LCD Panel
13.7. Partial Display Function
The ILI9335 allows selectively driving two partial images on the screen at arbitrary positions set in the screen
drive position registers.
The following example shows the setting for partial display function:
BASEE
NL[5:0]
PTDE0
PTSA0[8:0]
PTEA0[8:0]
PTDP0[8:0]
PTDE1
PTSA1[8:0]
PTEA1[8:0]
PTDP1[8:0]
Base Image Display Setting
0
6’h27
Partial Image 1 Display Setting
1
9’h000
9’h00F
9’h080
Partial Image 2 Display Setting
1
9’h020
9’h02F
9’h0C0
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PTSA0=9'h000
GRAM MAP
ILI9335
LCD Panel
0 (1st line)
1 (2nd line)
2 (3rd line)
Partial Image 1
GRAM Area
PTEA0=9'h00F
PTSA1=9'h020
PTDP0=9'h080
Partial Image 2
GRAM Area
Partial Image 1
Display Area
PTEA1=9'h02F
PTDP1=9'h0C0
Partial Image 2
Display Area
319 (320th line)
Figure 47 Partial Display Example
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ILI9335
14. Electrical Characteristics
14.1. Absolute Maximum Ratings
The absolute maximum rating is listed on following table. When ILI9335 is used out of the absolute maximum
ratings, the ILI9335 may be permanently damaged. To use the ILI9335 within the following electrical
characteristics limit is strongly recommended for normal operation. If these electrical characteristic conditions
are exceeded during normal operation, the ILI9335 will malfunction and cause poor reliability.
Item
Symbol
Unit
Value
Power supply voltage (1)
IOVCC
V
-0.3 ~ + 4.6
1, 2
Power supply voltage (1)
VCI – GND
V
-0.3 ~ + 4.6
1, 4
Power supply voltage (1)
DDVDH – GND
V
-0.3 ~ + 6.0
1, 4
Power supply voltage (1)
GND –VCL
V
-0.3 ~ + 4.6
1
Power supply voltage (1)
DDVDH – VCL
V
-0.3 ~ + 9.0
1, 5
Power supply voltage (1)
VGH – VGL
V
0.3 ~ + 30
1, 5
Vt
V
-0.3 ~ VCC+ 0.3
1
Input voltage
Note
Operating temperature
Topr
°C
-40 ~ + 85
8, 9
Storage temperature
Tstg
°C
-55 ~ + 110
8, 9
Notes:
1. GND must be maintained
2. (High) (VCC = VCC) ≥ GND (Low), (High) IOVCC ≥ GND (Low).
3. Make sure (High) VCI ≥ GND (Low).
4. Make sure (High) DDVDH ≥ GND (Low).
5. Make sure (High) DDVDH ≥ VCL (Low).
6. Make sure (High) VGH ≥ GND (Low).
7. Make sure (High) GND ≥ VGL (Low).
8. For die and wafer products, specified up to 85°C.
9. This temperature specifications apply to the TCP package
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reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp.
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ILI9335
14.2. DC Characteristics
(VCC = VCI=2.50 ~ 3.6V, IOVCC = 1.65 ~ 3.60V, Ta= -40 ~ 85 °C)
Item
Symbol
Unit
Test Condition
Input high voltage
VIH
V
IOVCC= 1.65 ~ 3.6V
Input low voltage
VIL
V
IOVCC= 1.65 ~ 3.6V
Max.
Note
-
IOVCC
-
-0.3
-
0.2*IOVCC
-
-
-
-
-
-
0.2*IOVCC
-
-0.1
-
0.1
-
VCC=IOVCC=2.8V , Ta=25°C , fOSC =
512KHz ( Line) GRAM data = 0000h
-
TBD
-
-
µA
VCC=IOVCC=2.8V , Ta=25 °C
-
30
60
-
ILCD
mA
VCI=2.8V , VREG1OUT =4.8V
DDVDH=5.2V , Frame Rate: 70Hz,
line-inversion, Ta=25 °C, GRAM data =
0000h,
-
5.5
-
-
DDVDH
V
-
4.5
-
6
-
VDEV
mV
-
-
-
20
-
VOFFSET
mV
-
-
35
-
VOH1
V
IOH = -0.1 mA
Output low voltage
( DB0-17 Pins)
VOL1
V
IOVCC=1.65~3.6V
I/O leakage current
ILI
µA
Vin = 0 ~ VCC
Current consumption
during normal operation
(VCC – GND)+ (IOVCC GND )
IOP
µA
Current consumption
during standby mode
(VCC – GND)+ (IOVCC GND )
IST
LCD Drive Power Supply
Current ( DDVDH-GND )
Output deviation voltage
Output offset voltage
Typ.
0.8*IOV
CC
Output high voltage(1)
( DB0-17 Pins)
LCD Driving Voltage
( DDVDH-GND )
Min.
0.8*IOV
CC
Note1
Note1: The Max. value is between with measure point and Gamma setting value.
14.3. Reset Timing Characteristics
Reset Timing Characteristics (IOVCC = 1.65 ~ 3.6 V)
Item
Symbol
Unit
Min.
Typ.
Reset low-level width
tRES_L
ms
1
-
-
Reset rise time
trRES
µs
-
-
10
Reset high-level width
tRES_H
ms
50
-
-
t
nRESET
V
RES_ L
t
Max.
rRES
V
t
IH
RES_ H
IL
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ILI9335
14.4. AC Characteristics
14.4.1. i80-System Interface Timing Characteristics
Normal Write Mode (IOVCC = 1.65~3.6V)
Item
Symbol
Unit
Min.
Write
tCYCW
ns
(75)
-
Read
tCYCR
ns
300
-
-
-
Write low-level pulse width
PW LW
ns
(40)
-
500
-
Write high-level pulse width
PWHW
ns
(30 )
-
-
-
Read low-level pulse width
PW LR
ns
150
-
-
-
Bus cycle time
Read high-level pulse width
Typ.
Max.
-
PWHR
ns
150
-
-
tWRr/tWRf
ns
-
-
25
tAS
ns
10
-
-
5
-
-
Address hold time
tAH
ns
5
-
-
Write data set up time
tDSW
ns
10
-
-
Write data hold time
tH
ns
15
-
-
Read data delay time
tDDR
ns
-
-
100
Read data hold time
tDHR
ns
5
-
-
nCS/RS/ DB Write / Read rise / fall time
Write ( RS to nCS, E/nWR )
Setup time
Read ( RS to nCS, RW/nRD )
RS
VIH
VIL
Test Condition
VIH
VIL
tAS
t AH
t cs
t chw
nCS
tc Ycw
nWR
PW LW
PWH W
t DSW
t wR f
DB[17:0]
(Write)
nRD
DB[17:0]
(Read)
t wRr
tH
Valid data
t AS
tAH
tCYCR
PWLR
tw Rf
t wRr
t DDR
PW HR
t DHR
Valid data
Figure 48 i80-System Bus Timing
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ILI9335
14.4.2. Serial Data Transfer Interface Timing Characteristics
(IOVCC= 1.65 ~ 3.6V)
Item
Serial clock cycle time
Serial clock high – level
pulse width
Serial clock low – level pulse
width
Symbol
Unit
Min.
Typ.
Max.
Write ( received )
tSCYC
ns
(100)
-
-
Read ( transmitted )
tSCYC
ns
200
-
-
Write ( received )
tSCH
ns
40
-
-
Read ( transmitted )
tSCH
ns
100
-
-
Write ( received )
tSCL
ns
40
-
-
Read ( transmitted )
Serial clock rise / fall time
Chip select set up time
tSCL
ns
100
-
-
tSCr, tSCf
ns
-
-
5
tCSU
ns
10
-
-
Chip select hold time
tCH
ns
50
-
-
Serial input data set up time
tSISU
ns
20
-
-
Serial input data hold time
tSIH
ns
20
-
-
Serial output data set up time
tSOD
ns
-
-
100
Serial output data hold time
tSOH
ns
5
-
-
nCS
Test Condition
V
IH
V
IL
t
CSU
SCL
V
SCr
V
V
IL
t
SCf
V
IH
t
t
SCL
V
IH
IL
V
IL
CH
V
V
IH
IL
t
t
SIH
SISU
SDI
SCYC
SCH
t
IH
t
t
V
V
Input Data
V
V
Input Data
V
V
Output Data
V
V
Output Data
IH
IL
IH
IL
t
SOD
SDO
OH
OL
OH
OL
V
V
OH
OL
Figure 49 SPI System Bus Timing
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reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp.
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ILI9335
14.4.3. RGB Interface Timing Characteristics
18/16-bit Bus RGB Interface Mode (IOVCC = 1.65 ~ 3.6V)
Item
Symbol
Unit
Min.
Typ.
Max.
Test Condition
tSYNCS
ns
0
-
-
-
ENABLE setup time
tENS
ns
10
-
-
-
ENABLE hold time
tENH
ns
10
-
-
-
PD Data setup time
tPDS
ns
10
-
-
-
PD Data hold time
tPDH
ns
40
-
-
-
DOTCLK high-level pulse width
PWDH
ns
40
-
-
-
DOTCLK low-level pulse width
PWDL
ns
40
-
-
-
tCYCD
ns
(150)
-
-
-
trghr, trghf
ns
-
-
25
-
Symbol
Unit
Min.
Typ.
Max.
Test Condition
tSYNCS
ns
0
-
-
-
ENABLE setup time
tENS
ns
10
-
-
-
ENABLE hold time
tENH
ns
10
-
-
-
PD Data setup time
tPDS
ns
10
-
-
-
PD Data hold time
tPDH
ns
30
-
-
-
DOTCLK high-level pulse width
PWDH
ns
30
-
-
-
DOTCLK low-level pulse width
PWDL
ns
30
-
-
-
tCYCD
ns
80
-
-
-
trghr, trghf
ns
-
-
25
-
VSYNC/HSYNC setup time
DOTCLK cycle time
DOTCLK, VSYNC, HSYNC, rise/fall time
6-bit Bus RGB Interface Mode (IOVCC = 1.65 ~ 3.6V)
Item
VSYNC/HSYNC setup time
DOTCLK cycle time
DOTCLK, VSYNC, HSYNC, rise/fall time
t
t
t
rgbf
rgbr
HSYNC
VSYNC
V
V
SYNCS
IH
IL
t
ASE
t
t
ENS
HSYNC
VSYNC
ENH
V
V
V
V
IH
IH
IL
t
PWDL
rgbf
V
IH
V
IL
t
V
IL
PWDH
rgbr
V
IL
V
IH
IH
t
CYCD
t
t
PDS
V
V
IH
PDH
Write Data
IL
V
V
IH
IL
Figure50 RGB Interface Timing
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reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp.
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a-Si TFT LCD Single Chip Driver
240RGBx320 Resolution and 262K color
ILI9335
14.4.4. Vcom Driving
The Vcom driving capability is descript as shown in the graph below by setting R=100
Ω
with different
capacitor loaded! The output delay time is considered as 5r!
Delay times means (tpHL or tpLH)
VcomH
99.33%
0.67%
VcomL
tpHL
tpLH
VCOM output delay time (uS)
VCOM
30
25
20
15
10
5
0
0
10
20
30
40
Load capacitance (nF)
The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed,
reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp.
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a-Si TFT LCD Single Chip Driver
240RGBx320 Resolution and 262K color
ILI9335
15. Revision History
Version No.
V0.00
V0,01
Date
2008/08/06
2008/08/14
2008/10/08
V0,02
2008/11/3
2008/11/03
V0,03
V0,04
V0,05
V0,06
2008/11/14
2008/11/24
2008/12/22
2008/12/30
V0.07
2009/01/19
V0.08
2009/02/03
V0.09
V0.10
2009/02/19
2009/02/20
V0.11
V0.12
2009/03/04
2009/03/20
2009/03/24
V0.13
V0.14~0.16
V0.17
2009/04/07
V0.18
V0.19
2009/07/14
2009/09/07
2009/06/22
Page
all
104
15~24
72
96
73
100
19,20,21
82, 83
61
99
100
84
24
99,100
8,12,13,
108~111
83
110
109
40, 48, 49
13
47, 29
11, 28, 30,
31
99, 100
57
112
61
64
32
74
109
11, 28
99
Description
new built
Change condition of stand by and normal mode.
Modify IC height and relative pad and alignment mark coordinate!
Frame rate modified
Schottky diode VCL-VGL GND-VGL
“04”h HEA-HAS “01”h HEA-HAS.
Modify figure 45
Modify pad coordinate of number 674,722, 859, 907 and 931
Add deep stand by mode
Add 16 bit data format
Add application circuit
Modify Schottky diode number and capacitor number
Modify OTP flow
Modify alignment mark coordinate
Modify component number
Modify IOVCC, VCI, VCC range to 3.6V
≦
≦
Add wake up timing
Add timing value
Add timing value
Delete HWM description
Delete MDDI description in IOVCC
Remove interlaced and graphics function description
Add DB[15:0], DB[7:0], DB[8:0]data input format
Modify component number
Gate scan modification drawing
Add Vcom driving capability
Modify EPF setting of 00, 01 and 10
Modify PTS[2:0]PTS[1:0]
Modify drawing of data mapping
Modify for specific customers
Modify frame rate
Modify stand by current max value
Modify IM=0 and 1 definition
Remove MDDI describe in configuration of power supply 0 and 1 definition
The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed,
reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp.
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