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DATA SHEET
( DOC No. HX8353-D-DS )
HX8353-D
132RGB x 162 dots, 262K color,
with Internal GRAM,
TFT Mobile Single Chip Driver
Preliminary version 01 Apr, 2010
HX8353-D
132RGB x 162 dot, 262K Color, with Internal
GRAM, TFT Mobile Single Chip Driver
List of Contents
1.
2.
3.
4.
5.
6.
7.
Apr, 2010
General Description ................................................................................................................................. 5
Features..................................................................................................................................................... 6
Block Diagram .......................................................................................................................................... 8
Pin Description ......................................................................................................................................... 9
4.1
Pin description ................................................................................................................................. 9
4.2
Pin assignment .............................................................................................................................. 13
4.3
PAD coordinates ............................................................................................................................ 14
4.4
Alignment mark.............................................................................................................................. 18
4.5
Bump size ...................................................................................................................................... 19
Interface................................................................................................................................................... 20
5.1
System interface ............................................................................................................................ 20
5.1.1 Parallel bus system interface................................................................................................ 21
5.1.2 MCU data color coding ......................................................................................................... 28
5.1.3 Serial Interface ..................................................................................................................... 37
5.1.4 Display module data transfer recovery................................................................................. 42
5.1.5 Display module data transfer pause ..................................................................................... 43
5.1.6 Display module data transfer modes.................................................................................... 44
5.2
Color depth conversion.................................................................................................................. 45
Display Data GRAM ................................................................................................................................ 49
6.1
Display data GRAM mapping ........................................................................................................ 49
6.2
Address counter (AC) of GRAM .................................................................................................... 49
6.2.1 System interface to GRAM write direction............................................................................ 50
6.3
Source, gate and memory map ..................................................................................................... 55
6.3.1 When using 132 x 162 GRAM resolution, display resolution 132RGB x 162
(RSO[2:0]=3’b000 & STE_SEL=0).................................................................................................... 55
6.3.2 When using 132 x 162 GRAM resolution, display resolution 128RGB x 160
(RSO[2:0]=3’b000 & STE_SEL=1).................................................................................................... 56
6.3.3 When using 128 x 128 GRAM resolution, display resolution 128RGB x 128
(RSO[2:0]=3’b001) ............................................................................................................................ 57
6.3.4 When using 120 x 160 GRAM resolution, display resolution 120RGB x 160
(RSO[2:0]=3’b010) ............................................................................................................................ 58
6.3.5 When using 128 x 160 GRAM resolution, display resolution 128RGB x 160
(RSO[2:0]=3’b011) ............................................................................................................................ 59
6.3.6 When using 96 x 68 GRAM resolution, display resolution 96RGB x 68 (RSO[2:0]=3’b100) 60
6.3.7 When using 96 x 64 GRAM resolution, display resolution 96RGB x 64 (RSO[2:0]=3’b101) 61
6.3.8 Normal display on or partial display on ................................................................................ 62
6.4
Vertical scrolling display ................................................................................................................ 76
Functional Description .......................................................................................................................... 78
7.1
Internal Oscillator........................................................................................................................... 78
7.2
Gamma characteristic correction function ..................................................................................... 79
7.2.1 Structure of grayscale voltage generator.............................................................................. 81
7.2.2 Gamma-characteristics adjustment register......................................................................... 82
7.2.3 Gamma resister stream and 8 to 1 selector ......................................................................... 83
7.2.4 Variable resister .................................................................................................................... 84
7.3
Tearing effect output line ............................................................................................................... 90
7.3.1 Tearing effect line modes...................................................................................................... 90
7.3.2 Tearing effect line timing....................................................................................................... 92
7.3.3 Example 1: MPU write is faster than panel read .................................................................. 93
7.3.4 Example 2: MPU write is slower than panel read................................................................. 94
7.4
Scan Mode Setting ........................................................................................................................ 95
7.5
LCD power generation circuit ........................................................................................................ 96
7.5.1 Power supply circuit.............................................................................................................. 96
7.5.2 LCD power generation scheme............................................................................................ 98
7.6
Power function ............................................................................................................................... 99
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.2Apr, 2010
HX8353-D
132RGB x 162 dot, 262K Color, with Internal
GRAM, TFT Mobile Single Chip Driver
List of Contents
8.
Apr, 2010
7.6.1 Power on/off sequence......................................................................................................... 99
7.6.2 Power levels definition........................................................................................................ 102
7.6.3 Deep standby mode set up flow ......................................................................................... 103
7.7
Sleep out – command and self-diagnostic functions of display module...................................... 104
7.7.1 Register loading detection .................................................................................................. 104
7.7.2 Functionality detection........................................................................................................ 105
7.8
Input / output pin state ................................................................................................................. 106
7.8.1 Output pins ......................................................................................................................... 106
7.8.2 Input pins ............................................................................................................................ 106
Command Set ....................................................................................................................................... 107
8.1
Command set list ......................................................................................................................... 107
8.2
Command description...................................................................................................................112
8.2.1 NOP .....................................................................................................................................112
8.2.2 Software reset (01h) ............................................................................................................113
8.2.3 Read display identification information (04h) ......................................................................114
8.2.4 Read display status (09h)....................................................................................................116
8.2.5 Read display power mode (0Ah) ........................................................................................ 120
8.2.6 Read display MADCTL (0Bh) ............................................................................................. 122
8.2.7 Read display pixel format (0Ch) ......................................................................................... 124
8.2.8 Read display image mode (0Dh) ........................................................................................ 126
8.2.9 Read display signal mode (0Eh) ........................................................................................ 128
8.2.10 Read display self-diagnostic result (0Fh) ........................................................................... 129
8.2.11 Sleep in (10h) ..................................................................................................................... 130
8.2.12 Sleep out (11h) ................................................................................................................... 132
8.2.13 Partial mode on (12h) ......................................................................................................... 134
8.2.14 Normal display mode on (13h) ........................................................................................... 135
8.2.15 Display inversion off (20h) .................................................................................................. 136
8.2.16 Display inversion on (21h) .................................................................................................. 137
8.2.17 Gamma set (26h)................................................................................................................ 138
8.2.18 Display off (28h).................................................................................................................. 139
8.2.19 Display on (29h) ................................................................................................................. 140
8.2.20 Column address set (2Ah).................................................................................................. 141
8.2.21 Page address set (2Bh)...................................................................................................... 143
8.2.22 Memory write (2Ch) ............................................................................................................ 145
8.2.23 Color set (2Dh) ................................................................................................................... 146
8.2.24 Memory read (2Eh)............................................................................................................. 147
8.2.25 Partial area (30h) ................................................................................................................ 148
8.2.26 Vertical scrolling definition (33h)......................................................................................... 150
8.2.27 Tearing effect line off (34h) ................................................................................................. 153
8.2.28 Tearing effect line on (35h) ................................................................................................. 154
8.2.29 Memory access control (36h) ............................................................................................. 155
8.2.30 Vertical scrolling start address (37h) .................................................................................. 157
8.2.31 Idle mode off (38h) ............................................................................................................. 158
8.2.32 Idle mode on (39h) ............................................................................................................. 159
8.2.33 Interface pixel format (3Ah) ................................................................................................ 161
8.2.34 Read ID1 (DAh) .................................................................................................................. 162
8.2.35 Read ID2 (DBh) .................................................................................................................. 163
8.2.36 Read ID3 (DCh) .................................................................................................................. 164
8.2.37 SETOSC: set internal oscillator (B0h) ................................................................................ 165
8.2.38 SETPOWER: set power (B1h)............................................................................................ 166
8.2.39 SETDISPLAY: set display related register (B2h)................................................................ 170
8.2.40 SETCYC: set display cycle register (B4h).......................................................................... 173
8.2.41 SETBGP: set BGP voltage related register (B5h) .............................................................. 176
8.2.42 SETCOM: set VCOM voltage related register (B6h) .......................................................... 178
8.2.43 SETEXTC: enable extension command (B9h) ................................................................... 180
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.3Apr, 2010
HX8353-D
132RGB x 162 dot, 262K Color, with Internal
GRAM, TFT Mobile Single Chip Driver
List of Contents
9.
10.
11.
12.
13.
14.
Apr, 2010
8.2.44 SETOTP: set OTP setting (BBh) ........................................................................................ 181
8.2.45 SETVDC: set internal digital and GRAM voltage (BCh) ..................................................... 182
8.2.46 SETSTBA: set source option (C0h).................................................................................... 183
8.2.47 SETTID: set ID (C3h) ......................................................................................................... 184
8.2.48 SETUADJ: (C6h) ................................................................................................................ 185
8.2.49 SETCLOCK: (CBh) ............................................................................................................. 186
8.2.50 SETPANEL: set panel characteristic (CCh) ....................................................................... 187
8.2.51 GETHID: Read Product ID (D0h) ....................................................................................... 188
8.2.52 SETGAMMA: set gamma curve (E0h) ............................................................................... 189
8.2.53 SETEQ: set EQ (E3h)......................................................................................................... 190
Layout Recommendation .................................................................................................................... 191
OTP Programming................................................................................................................................ 193
10.1 Programming flow........................................................................................................................ 195
10.2 OTP Programming example for VMF1 ........................................................................................ 196
10.3 Programming sequence .............................................................................................................. 197
10.4 OTP Read flow and example....................................................................................................... 197
10.5 Programming circuitry.................................................................................................................. 198
Electrical Characteristic ...................................................................................................................... 199
11.1 Absolute maximum ratings .......................................................................................................... 199
11.2 ESD protection level .................................................................................................................... 199
11.3 DC characteristics ....................................................................................................................... 200
11.3.1 Current consumption .......................................................................................................... 202
11.4 AC characteristics........................................................................................................................ 203
11.4.1 Parallel interface characteristics (8080-series MPU) ......................................................... 203
11.4.2 Serial interface characteristics ........................................................................................... 205
11.4.3 Reset input timing............................................................................................................... 206
11.5 tACC, tOH Measurement Condition ............................................................................................ 207
Reference Application ......................................................................................................................... 209
12.1 I80 system ................................................................................................................................... 209
12.2 SPI system................................................................................................................................... 210
st
12.3 1 Pixel is at right-bottom of the panel & RGB filter order = RGB................................................211
st
12.4 1 Pixel is at left-top of the panel & RGB filter order = BGR ....................................................... 212
12.5 Application of connection with Different resolution...................................................................... 213
Ordering Information............................................................................................................................ 227
Revision History ................................................................................................................................... 227
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.4Apr, 2010
HX8353-D
132RGB x 162 dot, 262K Color, with Internal
GRAM, TFT Mobile Single Chip Driver
Preliminary Version 01
Apr, 2010
1. General Description
This manual is describes the Himax’s HX8353-D 132RGB*162 dots resolution driving
controller. The HX8353-D is designed to provide a single-chip solution that combined
a gate driver, a source driver, power supply circuit, and internal graphics RAM for
262,144 colors to drive a TFT panel with 132RGB*162 dots at maximum.
The HX8353-D can be operated in low-voltage (1.65V) condition to the interface and
integrated internal boosters that produce the liquid crystal voltage, breeder resistance
and the voltage follower circuit for liquid crystal driver. In addition, The HX8353-D also
supports various functions to reduce the power consumption of a LCD system via
software control.
The HX8353-D is suitable for any small portable battery-driven product and requiring
long-term driving capabilities, such as small PDAs, digital cellular phones and
bi-directional pagers.
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.5Apr, 2010
HX8353-D
132RGB x 162 dots, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
2. Features
Single chip solution to drive a TFT panel
132RGB x 162-dot graphics display LCD controller/driver and 262,144 TFT colors
Support resolution:
132RGB x 162-dot: Display with 132 x 18-bits x 162 display RAM
128RGB x 160-dot
Type
1: Display with 128 x 18-bits x 160 display RAM
Type
2: Display with 132 x 18-bits x 162 display RAM
128RGB x 128-dot
120RGB x 160-dot
96RGB x 68-dot: Display with 96 x 18-bits x 68 display RAM
96RGB x 64-dot
Internal operation circuit of liquid crystal display:
Source channel: 396ch (132RGB)
Gate line: 162 Gate output
Display mode (Color modes):
Full colors
262k colors (18bit 6(R):6(G):6(B))
Reduce color mode:
65k colors (16bit 5(R):6(G):5(B))
4k colors (12bit 4(R):4(G):4(B))
8 colors (Idle mode on): 8 colors (3 bit binary mode)
Internal graphics RAM capacity: 132 x 162 x 18-bit = 0.38M bit:
Support interface mode:
I80 System interface: 8-/9-/16-/18-bits bus
M68 System interface: 8-/9-/16- /18-bits bus
3-/4- Wires Serial Data Transfer Interface
Display features
Area scrolling
Partial display mode
Software programmable color depth mode
On chip features:
DC/DC converter
OTP to store initialization register setting and MTP (Multi-time-programming)
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.6Apr, 2010
HX8353-D
132RGB x 162 dots, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
non-volatile memory to store for VCM setting
Oscillator for display clock generation
Line inversion, frame inversion
Support default value for factory use
Low-power consumption architecture supports:
Logic supply voltage range for IOVCC to VSSD: 1.65 to 3.3V
Analog supply voltage range for VCI to VSSA: 2.5 to 3.3V
Output voltage range:
DDVDH = 5.0 V for two time pump (Power supply for driver circuit range)
VREG1 = 3.3V to 4.8V (Source output voltage range)
VGH = +8.0 to +14.5V (Positive Gate output voltage range)
VGL = -5.0 to -12.5V (Negative Gate output voltage range)
VCOMH = 2.5V to 4.8V, 15mV/step (Common electrode output high voltage)
VCOML = -2.5V to 0.0V, 15mV/step (Common electrode output low voltage)
Low power consumption, suitable for battery operated systems
Suitable for all brand LCM module
Command set:
128RGB x 160-dot
132RGB x 162-dot
120RGB x 160-dot
96RGB x 68-dot
96RGB x 64-dot
Himax defined command set
CMOS compatible inputs
Optimized layout for COG assembly
Temperature range: -30℃ ~ 80℃
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.7Apr, 2010
HX8353-D
132RGB x 162 dots, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
3. Block Diagram
S396~1
IOVCC
VSSD
Index Register
(IR)
P68
BS0
BS1
BS2
Source driver
7
D/A converter circuit
System I/F
I80 & m68
8 bits
9 bits
16 bits
18 bits
nWR_RNW
EXTC
18
18
nRESET
GC_SEL
Read data
latch
Instruction
Controller
Latch circuit
Write data
latch
V0~63
18
18
TEST2~1
LC_SEL_0~1
STE_SEL
RSO0
RSO1
RSO2
16
18
Grayscale voltage
generator
VTESTOUT
Graphic RAM
(GRAM)
132x18x162bits
Gamma adjusting
circuit
Power
Regulator
IOVCC
VDDD
Timing
Generator
RSOC
OSC
Gate
Driver
TE
18
Address Counter
(AC)
nCS
DNC_SCL
nRD_E
DB17~0
Control
Register
(CR)
G1 ~ G162
VSSD
VSSA
LCD driving power circuit
VDDD
VCOMH
VCOML
VCOM
VCL
VGH
VGL
DDVDH
C11A/C11B
VREG1
VCI
VGH/VGL
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.8Apr, 2010
HX8353-D
132RGB x 162 dots, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
4. Pin Description
4.1 Pin description
Input Part
Signals
I/O
Pin
Connected
Number
with
Description
Select the MPU interface mode as listed below
P68 BS2 BS1 BS0 Interface mode
DB pins
P68, BS2,BS1,BS0
I
4
VSSD/
IOVCC
SPI_SEL
I
1
VSSD/
IOVCC
NCS
I
1
MPU
DNC_SCL
I
1
MPU
NRD_E
I
1
MPU
NWR_RNW
I
1
MPU
EXTC
I
1
VSSD/
IOVCC
STE_SEL
I
1
VSSD/
IOVCC
GC_SEL
I
1
VSSD/
IOVCC
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
8-bit bus interface,
80-system
16-bit bus interface,
80-system
9-bit bus interface,
80-system
18-bit bus interface,
80-system
8-bit bus interface,
68-system
16-bit bus interface,
68-system
9-bit bus interface,
68-system
18-bit bus interface,
68-system
X
0
X
X
3-/4- wire serial
interface
DB17-DB8:Unused
DB7-DB0: Data
DB17-DB16:Unused
DB15-DB0: Data
DB17-DB9:Unused
DB8-DB0: Data
DB17-DB0: Data
DB17-DB8:Unused
DB7-DB0: Data
DB17-DB16:Unused
DB15-DB0: Data
DB17-DB9:Unused
DB8-DB0: Data
DB17-DB0: Data
DB17-DB0:Unused
SDA: Data
input/output
Must be connected to VSSD or IOVCC.
Interface format select pin
SPI_SEL
Serial Interface Format Selection
0
3-wire serial interface (default)
1
4-wire serial interface
If not used, connect it to VSSD.
Chip select signal.
Low: chip can be accessed;
High: chip cannot be accessed.
The signal for command or parameter select under parallel mode(i.e.
Not serial interface):
Low: command. High: parameter.
When under serial interface, it servers as SCL.
I80 system: Serves as a read signal and read data at the low level.
M68 system: 0: Read/Write disable, 1: Read/Write enable.
If not used, connected to IOVCC.
I80 system: Serves as a write signal and writes data at the rising
edge.
M68 system: 0: Write, 1: Read.
4-wire SPI interface: 0: Command, 1: Data.
If not used, connected to IOVCC.
Extended command set enable.
Low (VSSD): extended command set is discarded
High (IOVCC): extended command set is accepted
If not used, let it open or connected to VSSD.(weak pull low)
This Pin is only valid for RSO[2:0]=3’b000.
Low (VSSD): Scrolling function enable and TE lines (162 lines)
High (IOVCC): Scrolling function disable and TE lines (160 lines)
Must be connected to VSSD or IOVCC.
This signal is used to select gamma curve order.
Low (VSSD): GC0(1.0), GC1(2.5), GC2(2.2), GC3(1.8)
High (IOVCC): GC0(2.2), GC1(1.8), GC2(2.5), GC3(1.0)
Must be connected to VSSD or IOVCC.
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.9Apr, 2010
HX8353-D
132RGB x 162 dots, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
Input Part
Signals
LC_SEL0~1
I/O
I
Pin
Connected
Number
with
2
Description
VSSD/
IOVCC
The selection pins of different liquid crystal type. Must be connected
to VSSD or IOVCC.
Different liquid crystal type
LC_SEL1
LC_SEL0
Selection
0
0
LC type 1
0
1
LC type 2
1
0
LC type 3
1
1
LC type 4
VSSD/
IOVCC
Resolution selection pins. RSO[2:0] is used for selecting resolution.
Must be connected to VSSD or IOVCC.
RSO2 RSO1 RSO0
Resolution
GRAM resolution (Size): 132RGBX162
Display resolution:
Type1 :132RGBx162 (S1~S396 and
0
0
0
G1~G162)
Type2 :128RGBx160 (S7~S390 and
G2~G161)
GRAM resolution (Size): 128RGBx128
0
0
1
Display resolution:
128RGBx128 (S7~S390 and G2~G129)
GRAM resolution (Size): 120RGBx160
0
1
0
Display resolution:
120RGBx160 (S7~S366, G2~G161)
GRAM resolution (Size): 128RGBx160
0
1
1
Display resolution:
128RGBx160 (S7~S390 and G2~G161)
GRAM resolution: 96RGBx68
1
0
0
Display resolution:
96RGBx68 (S55~S342, G1~G68)
GRAM resolution: 96RGBx64
1
0
1
Display resolution:
96RGBx64 (S55~S342, G1~G64)
1
1
0
Setting disable
1
1
1
Setting disable
RSO0~2
I
3
NRESET
I
1
MPU or reset Reset pin. Setting this pin low initializes the LSI. Must be reset after
circuit
power is supplied.
1
VSSD/
IOVCC
Input pin to select the source driver scan direction on panel module.
Must be connected to VSSD or IOVCC.
Module source output direction
RSO[2:0]
RSO[2:0]
SS_PANEL RSO[2:0]
RSO[2:0]
=3’b000
=3’b100,
=3’b000
=3’b010
(type2),
3’b101
(type1)
3’b001, 3’b011
S55 ->
S1 ->
0
S7 -> S366
S7 -> S390
S342
S396
S396 ->
S342 ->
1
S366 -> S7
S390 -> S7
S55
S1
VSSD/
IOVCC
Input pin to select the Gate driver scan direction on panel module.
Must be connected to VSSD or IOVCC.
Module Gate output direction
RSO[2:0]
GS_PA
RSO[2:0]
=3’b000
RSO[2:0] RSO[2:0]
RSO[2:0]
NEL
(type2),
=3’b000
=3’b101 =3’b100
=3’b001
3’b010,
(type1)
3’b011
G1 ->
G1 ->
G2 ->
G2 ->
G1 ->
0
G64
G68
G161
G129
G162
G64 ->
G68 ->
G161 ->
G129 ->
G162 ->
1
G1
G1
G2
G2
G1
SS_PANEL
GS_PANEL
I
I
1
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.10Apr, 2010
HX8353-D
132RGB x 162 dots, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
Input Part
Signals
I/O
Pin
Connected
Number
with
REV_PANEL
I
1
VSSD/
IOVCC
BGR_PANEL
I
1
VSSD/
IOVCC
TEST2-1
I
2
VSSD
OSC
I
1
Open or
Connect to
VSSD
I/O
Pin
Number
Connected
with
Description
Input pin to select the display reversion. Must be connected to VSSD
or IOVCC.
REV_PANEL
Mapping data
“0” to maximum pixel voltage for normal white
0
panel
“0” to minimum pixel voltage for normal black
1
panel
Input pin to select the color mapping. Must be connected to VSSD or
IOVCC.
BGR_PANEL
Color mapping
S1、S2、S3 filter order = R → G → B
0
S1、S2、S3 filter order = B → G → R
1
Test pins. Let it open or connected to VSSD. (weak pull low)
Oscillator input for test purpose.
If not used, please let it open or connected to VSSD.
Output Part
Signals
S1~396
O
396
LCD
G1~162
O
162
LCD
VCOM
O
3
TFT
common
electrode
VCOMH
O
3
Open
VCOML
O
3
Open
VREG1
O
3
DDVDH
O
5
VGH
O
3
VGL
O
3
Open
Stabilizing
capacitor
Open
Stabilizing
capacitor
VCL
O
3
Open
TE
O
1
MPU or
open
VTESTOUT
VDDD
VBGP
TS7~0
O
O
O
O
1
3
3
8
Open
Open
Open
Open
Description
Output voltages applied to the liquid crystal.
SS=0, ram address “0000” is output from S1.
SS=1, ram address “0000” is output from S396.
S1,S2,S3 =’R’,’G’,’B’ (SS=0, BGR=0).
Output signals from gate lines.
VGH: the level to select the gate lines
VGL: the level not to select the gate lines
The power supply of common voltage in TFT driving. The voltage
amplitude between VCOMH and VCOML is output. The alternation
cycle can be set by the POL pin. Connect this pin to the common
electrode in TFT panel.
This pin indicates a high level of VCOM amplitude generated in
driving the VCOM alternation. Let it open.
When the VCOM alternation is driven, this pin indicates a low level of
VCOM amplitude. When the VCOMG bit is low, the VCOML output
stops. Let it open.
Internal generated stable power for source driver. Let it open.
An output from the step-up circuit1, of twice the VCI level.
Connect to a stabilizing capacitor between VSSA and DDVDH.
The step-up rate is determined with BT2-0 bits. Let it open.
The step-up rate is determined with BT2-0 bits.
Connect to a stabilizing capacitor between VSSA and VGL.
An output from the step-up circuit1.
A negative voltage for VCOML circuit, VCL= -VCI. Let it open.
A frame start pulse output (amplitude: IOVCC-VSSD). Use when
writing data to RAM in synchronization with FLM. When FLM is not
used, disconnect it
A test pin. Disconnect it.
Output from internal logic voltage. Let it open.
Reference voltage for power circuit. Let it open.
Test pins. Let these pins open.
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.11Apr, 2010
HX8353-D
132RGB x 162 dots, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
Signals
I/O
Pin
Number
C11A,C11B
I/O
4,4
Dummy35 ~ 40
I/O
Dummy23 ~ 34
I/O
3,3
3,3
3,3
Input/Output Part
Connected
Description
with
Stabilizing
Connect a pump capacitor between C11A and C11B.
capacitor
Dummy pads. Please open these pins.
Open
Open
DB0_SDA
DB1~17
I/O
18
MPU
DUMMY
-
39
Open
DUMMYR1~R2
-
2
-
Signals
I/O
Pin
Number
IOVCC
P
17
VSSD
P
17
VSSA
P
9
Connected
with
Power
supply
Power
supply
Power
supply
VCI
P
6
Dummy pads. Please open these pins.
When Operates in system interface mode, it is used liked an 18-bit
bi-directional data bus.
8-bit bus: use DB7-DB0
9-bit bus: use DB8-DB0
16-bit bus: use DB15-DB0
18-bit bus: use DB17-DB0
For serial interface, this pin (SDA) is for serial data pin when operate
on serial data transfer interface mode of Command-parameter
Interface mode. Data would be latched on the rising edge of the SCL
signal.
Let unused data pins open or pulled Gnd or pulled IOVCC.
Dummy pads. Disconnect them.
Dummy pads. Available for measuring the COG contact resistance.
DUMMYR1 and DUMMYR2 are short-circuited within the chip.
Power Part
Power
supply
Description
Power supply for interface pin. IOVCC = 1.65 ~3.3 V.
Ground for the logic side. VSSD = 0V
Analog ground. VSSA = 0V. When using the COG method, connect to
VSSD on the FPC to prevent noise.
A power supply for the analog circuit. VCI = 2.5 ~ 3.3V
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.12Apr, 2010
HX8353-D
132RGB x 162 dots, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
4.2 Pin assignment
A1
NO.1
TS7
IOVCC
EXTC
VSSD
BS0
IOVCC
BS1
VSSD
P68
IOVCC
DUMMY
VSSD
DUMMY
IOVCC
BGR_ PANEL
VSSD
SS_ PANEL
IOVCC
GS_ PANEL
VSSD
DUMMY
IOVCC
REV_ PANEL
VSSD
DUMMY
IOVCC
DUMMY
VSSD
DUMMY
IOVCC
LC_ SEL0
VSSD
LC_ SEL1
IOVCC
RSO2
VSSD
RSO1
IOVCC
RSO0
VSSD
DUMMY
GC_ SEL
SPI_ SEL
IOVCC
TS6
TS5
TS4
TS3
TEST1
OSC
VCI
VCI
VCI
VCI
VCI
VCI
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
NRD_E
DNC_ SCL
STE_ SEL
VSSD
DB17
DB16
DB15
DB14
DB13
DB12
DB11
DB10
DB9
DB8
DB1
DB3
DB5
DB7
TE
NRESET
NCS
DB6
DB4
DB2
BS2
DB0_ SDA
NWR_ RNW
DUMMY
DUMMY
DUMMY
DUMMY
TS2
TS1
TS0
VSSD
Chip size : 9900um x 675um
Including : Seal-ring : 4um * 2
Scribe line : 40um * 2
Chip thickness : 250um(typ.)/350um
Pad coordinate : PAD center
Coordinate Origin : Chip Center
Au Bump Size
Bump height tolerance +/- 3um
Bump size tolerance :
Output bump width : 16 +/- 2um
Output bump length : 98 +/- 3um
Input bump width : 35/40 +/- 3um
Input bump length : 90 +/- 3um
Au bump height : 12um +/- 3um
Numbers in the figure corresponds to
pad coordinate numbers
Alignment Mark
Arrangement : Two places
A1 : Coordinate(X,Y)=(-4841,-220)
A2 : Coordinate(X,Y)=(4841,-220)
NO.97
DUMMY
DUMMY
G161
G 159
G3
G1
DUMMY
DUMMY
DUMMY
DUMMY
S1
S2
NO. 756
NO.678
NO. 671
FACE UP
(Bump View)
HX8353-D
Pin Assignment
S 197
S198
DUMMY
DUMMY
Y
DUMMY
DUMMY
S199
S200
NO.476
NO.473
NO.472
NO.469
NO. 102
VSSD
IOVCC
NO.108
IOVCC
X
VDDD
VDDD
VDDD
DUMMY
DUMMY
DUMMY
VBGP
VBGP
VBGP
TEST2
VTESTOUT
DDVDH
DDVDH
DDVDH
DDVDH
DDVDH
VREG1
VREG1
VREG1
DUMMYR1
DUMMYR2
C11A
C11A
C11A
C11A
C11B
C11B
C11B
C11B
DYMMY
NO.138
NO.145
DUMMY
VSSA
VSSA
VSSA
VCL
VCL
VCL
DUMMY
S 395
S 396
DUMMY
DUMMY
DUMMY
DUMMY
G2
G4
DUMMY
VGL
VGL
VGL
VGH
VGH
VGH
VCOMH
VCOMH
VCOMH
VCOML
VCOML
VCOML
VCOM
VCOM
VCOM
DUMMY
NO.185
A2
G160
G162
DUMMY
DUMMY
NO.274
NO. 267
NO.186
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.13Apr, 2010
HX8353-D
132RGB x 162 dots, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
4.3 PAD coordinates
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
Name
TS7
IOVCC
EXTC
VSSD
BS0
IOVCC
BS1
VSSD
P68
IOVCC
DUMMY
VSSD
DUMMY
IOVCC
BGR_PANEL
VSSD
SS_PANEL
IOVCC
GS_PANEL
VSSD
DUMMY
IOVCC
REV_PANEL
VSSD
DUMMY
IOVCC
DUMMY
VSSD
DUMMY
IOVCC
LC_SEL0
VSSD
LC_SEL1
IOVCC
RSO2
VSSD
RSO1
IOVCC
RSO0
VSSD
DUMMY
GC_SEL
SPI_SEL
IOVCC
TS6
TS5
TS4
TS3
TEST1
OSC
VCI
VCI
VCI
VCI
VCI
VCI
VSSA
VSSA
VSSA
VSSA
X
-4750
-4700
-4650
-4600
-4550
-4500
-4450
-4400
-4350
-4300
-4250
-4200
-4150
-4100
-4050
-4000
-3950
-3900
-3850
-3800
-3750
-3700
-3650
-3600
-3550
-3500
-3450
-3400
-3350
-3300
-3250
-3200
-3150
-3100
-3050
-3000
-2950
-2900
-2850
-2800
-2750
-2700
-2650
-2600
-2550
-2500
-2450
-2400
-2350
-2300
-2250
-2200
-2150
-2100
-2050
-2000
-1950
-1900
-1850
-1800
Y
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
2
2
-2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
No.
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
Name
VSSA
VSSA
NRD_E
DNC_SCL
STE_SEL
VSSD
DB17
DB16
DB15
DB14
DB13
DB12
DB11
DB10
DB9
DB8
DB1
DB3
DB5
DB7
TE
NRESET
NCS
DB6
DB4
DB2
BS2
DB0_SDA
NWR_RNW
DUMMY
DUMMY
DUMMY
DUMMY
TS2
TS1
TS0
VSSD
VSSD
VSSD
VSSD
VSSD
VSSD
IOVCC
IOVCC
IOVCC
IOVCC
IOVCC
IOVCC
VDDD
VDDD
VDDD
DUMMY
DUMMY
DUMMY
VBGP
VBGP
VBGP
TEST2
VTESTOUT
DDVDH
X
-1750
-1700
-1630
-1570
-1510
-1450
-1390
-1330
-1270
-1210
-1150
-1090
-1030
-970
-910
-850
-790
-730
-670
-610
-550
-490
-430
-370
-310
-250
-190
-130
-70
0
50
100
150
200
250
300
350
400
450
500
550
600
650
700
750
800
850
900
950
1000
1050
1100
1150
1200
1250
1300
1350
1400
1450
1500
Y
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
No.
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
Name
DDVDH
DDVDH
DDVDH
DDVDH
VREG1
VREG1
VREG1
DUMMYR1
DUMMYR2
C11A
C11A
C11A
C11A
C11B
C11B
C11B
C11B
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
VSSA
VSSA
VSSA
VCL
VCL
VCL
DUMMY23
DUMMY24
DUMMY25
DUMMY26
DUMMY27
DUMMY28
DUMMY29
DUMMY30
DUMMY31
DUMMY32
DUMMY33
DUMMY34
DUMMY35
DUMMY36
DUMMY37
DUMMY38
DUMMY39
DUMMY40
VGL
VGL
VGL
VGH
VGH
VGH
VCOMH
VCOMH
VCOMH
VCOML
VCOML
X
1550
1600
1650
1700
1750
1800
1850
1900
1950
2000
2050
2100
2150
2200
2250
2300
2350
2400
2450
2500
2550
2600
2650
2700
2750
2800
2850
2900
2950
3000
3050
3100
3150
3200
3250
3300
3350
3400
3450
3500
3550
3600
3650
3700
3750
3800
3850
3900
3950
4000
4050
4100
4150
4200
4250
4300
4350
4400
4450
4500
Y
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
No.
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
Name
VCOML
VCOM
VCOM
VCOM
DUMMY
DUMMY
DUMMY
G162
G160
G158
G156
G154
G152
G150
G148
G146
G144
G142
G140
G138
G136
G134
G132
G130
G128
G126
G124
G122
G120
G118
G116
G114
G112
G110
G108
G106
G104
G102
G100
G98
G96
G94
G92
G90
G88
G86
G84
G82
G80
G78
G76
G74
G72
G70
G68
G66
G64
G62
G60
G58
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
X
4550
4600
4650
4700
4750
4772
4756
4740
4724
4708
4692
4676
4660
4644
4628
4612
4596
4580
4564
4548
4532
4516
4500
4484
4468
4452
4436
4420
4404
4388
4372
4356
4340
4324
4308
4292
4276
4260
4244
4228
4212
4196
4180
4164
4148
4132
4116
4100
4084
4068
4052
4036
4020
4004
3988
3972
3956
3940
3924
3908
Y
-231
-231
-231
-231
-231
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
-P.14Apr, 2010
HX8353-D
132RGB x 162 dots, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
No.
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
Name
G56
G54
G52
G50
G48
G46
G44
G42
G40
G38
G36
G34
G32
G30
G28
G26
G24
G22
G20
G18
G16
G14
G12
G10
G8
G6
G4
G2
DUMMY
DUMMY
DUMMY
DUMMY
S396
S395
S394
S393
S392
S391
S390
S389
S388
S387
S386
S385
S384
S383
S382
S381
S380
S379
S378
S377
S376
S375
S374
S373
S372
S371
S370
S369
X
3892
3876
3860
3844
3828
3812
3796
3780
3764
3748
3732
3716
3700
3684
3668
3652
3636
3620
3604
3588
3572
3556
3540
3524
3508
3492
3476
3460
3444
3428
3412
3396
3380
3364
3348
3332
3316
3300
3284
3268
3252
3236
3220
3204
3188
3172
3156
3140
3124
3108
3092
3076
3060
3044
3028
3012
2996
2980
2964
2948
Y
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
No.
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
Name
S368
S367
S366
S365
S364
S363
S362
S361
S360
S359
S358
S357
S356
S355
S354
S353
S352
S351
S350
S349
S348
S347
S346
S345
S344
S343
S342
S341
S340
S339
S338
S337
S336
S335
S334
S333
S332
S331
S330
S329
S328
S327
S326
S325
S324
S323
S322
S321
S320
S319
S318
S317
S316
S315
S314
S313
S312
S311
S310
S309
X
2932
2916
2900
2884
2868
2852
2836
2820
2804
2788
2772
2756
2740
2724
2708
2692
2676
2660
2644
2628
2612
2596
2580
2564
2548
2532
2516
2500
2484
2468
2452
2436
2420
2404
2388
2372
2356
2340
2324
2308
2292
2276
2260
2244
2228
2212
2196
2180
2164
2148
2132
2116
2100
2084
2068
2052
2036
2020
2004
1988
Y
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
No.
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
Name
S308
S307
S306
S305
S304
S303
S302
S301
S300
S299
S298
S297
S296
S295
S294
S293
S292
S291
S290
S289
S288
S287
S286
S285
S284
S283
S282
S281
S280
S279
S278
S277
S276
S275
S274
S273
S272
S271
S270
S269
S268
S267
S266
S265
S264
S263
S262
S261
S260
S259
S258
S257
S256
S255
S254
S253
S252
S251
S250
S249
X
1972
1956
1940
1924
1908
1892
1876
1860
1844
1828
1812
1796
1780
1764
1748
1732
1716
1700
1684
1668
1652
1636
1620
1604
1588
1572
1556
1540
1524
1508
1492
1476
1460
1444
1428
1412
1396
1380
1364
1348
1332
1316
1300
1284
1268
1252
1236
1220
1204
1188
1172
1156
1140
1124
1108
1092
1076
1060
1044
1028
Y
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
No.
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
Name
S248
S247
S246
S245
S244
S243
S242
S241
S240
S239
S238
S237
S236
S235
S234
S233
S232
S231
S230
S229
S228
S227
S226
S225
S224
S223
S222
S221
S220
S219
S218
S217
S216
S215
S214
S213
S212
S211
S210
S209
S208
S207
S206
S205
S204
S203
S202
S201
S200
S199
DUMMY
DUMMY
DUMMY
DUMMY
S198
S197
S196
S195
S194
S193
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
X
1012
996
980
964
948
932
916
900
884
868
852
836
820
804
788
772
756
740
724
708
692
676
660
644
628
612
596
580
564
548
532
516
500
484
468
452
436
420
404
388
372
356
340
324
308
292
276
260
244
228
212
196
-196
-212
-228
-244
-260
-276
-292
-308
Y
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
110
227
110
227
110
227
110
227
-P.15Apr, 2010
HX8353-D
132RGB x 162 dots, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
No.
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
Name
S192
S191
S190
S189
S188
S187
S186
S185
S184
S183
S182
S181
S180
S179
S178
S177
S176
S175
S174
S173
S172
S171
S170
S169
S168
S167
S166
S165
S164
S163
S162
S161
S160
S159
S158
S157
S156
S155
S154
S153
S152
S151
S150
S149
S148
S147
S146
S145
S144
S143
S142
S141
S140
S139
S138
S137
S136
S135
S134
S133
X
-324
-340
-356
-372
-388
-404
-420
-436
-452
-468
-484
-500
-516
-532
-548
-564
-580
-596
-612
-628
-644
-660
-676
-692
-708
-724
-740
-756
-772
-788
-804
-820
-836
-852
-868
-884
-900
-916
-932
-948
-964
-980
-996
-1012
-1028
-1044
-1060
-1076
-1092
-1108
-1124
-1140
-1156
-1172
-1188
-1204
-1220
-1236
-1252
-1268
Y
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
No.
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
Name
S132
S131
S130
S129
S128
S127
S126
S125
S124
S123
S122
S121
S120
S119
S118
S117
S116
S115
S114
S113
S112
S111
S110
S109
S108
S107
S106
S105
S104
S103
S102
S101
S100
S99
S98
S97
S96
S95
S94
S93
S92
S91
S90
S89
S88
S87
S86
S85
S84
S83
S82
S81
S80
S79
S78
S77
S76
S75
S74
S73
X
-1284
-1300
-1316
-1332
-1348
-1364
-1380
-1396
-1412
-1428
-1444
-1460
-1476
-1492
-1508
-1524
-1540
-1556
-1572
-1588
-1604
-1620
-1636
-1652
-1668
-1684
-1700
-1716
-1732
-1748
-1764
-1780
-1796
-1812
-1828
-1844
-1860
-1876
-1892
-1908
-1924
-1940
-1956
-1972
-1988
-2004
-2020
-2036
-2052
-2068
-2084
-2100
-2116
-2132
-2148
-2164
-2180
-2196
-2212
-2228
Y
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
No.
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
Name
S72
S71
S70
S69
S68
S67
S66
S65
S64
S63
S62
S61
S60
S59
S58
S57
S56
S55
S54
S53
S52
S51
S50
S49
S48
S47
S46
S45
S44
S43
S42
S41
S40
S39
S38
S37
S36
S35
S34
S33
S32
S31
S30
S29
S28
S27
S26
S25
S24
S23
S22
S21
S20
S19
S18
S17
S16
S15
S14
S13
X
-2244
-2260
-2276
-2292
-2308
-2324
-2340
-2356
-2372
-2388
-2404
-2420
-2436
-2452
-2468
-2484
-2500
-2516
-2532
-2548
-2564
-2580
-2596
-2612
-2628
-2644
-2660
-2676
-2692
-2708
-2724
-2740
-2756
-2772
-2788
-2804
-2820
-2836
-2852
-2868
-2884
-2900
-2916
-2932
-2948
-2964
-2980
-2996
-3012
-3028
-3044
-3060
-3076
-3092
-3108
-3124
-3140
-3156
-3172
-3188
Y
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
No.
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
Name
S12
S11
S10
S9
S8
S7
S6
S5
S4
S3
S2
S1
DUMMY
DUMMY
DUMMY
DUMMY
G1
G3
G5
G7
G9
G11
G13
G15
G17
G19
G21
G23
G25
G27
G29
G31
G33
G35
G37
G39
G41
G43
G45
G47
G49
G51
G53
G55
G57
G59
G61
G63
G65
G67
G69
G71
G73
G75
G77
G79
G81
G83
G85
G87
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
X
-3204
-3220
-3236
-3252
-3268
-3284
-3300
-3316
-3332
-3348
-3364
-3380
-3396
-3412
-3428
-3444
-3460
-3476
-3492
-3508
-3524
-3540
-3556
-3572
-3588
-3604
-3620
-3636
-3652
-3668
-3684
-3700
-3716
-3732
-3748
-3764
-3780
-3796
-3812
-3828
-3844
-3860
-3876
-3892
-3908
-3924
-3940
-3956
-3972
-3988
-4004
-4020
-4036
-4052
-4068
-4084
-4100
-4116
-4132
-4148
Y
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
-P.16Apr, 2010
HX8353-D
132RGB x 162 dots, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
No.
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
Name
G89
G91
G93
G95
G97
G99
G101
G103
G105
G107
G109
G111
G113
G115
G117
G119
G121
G123
G125
G127
G129
G131
G133
G135
G137
G139
G141
G143
G145
G147
G149
G151
G153
G155
G157
G159
G161
DUMMY
DUMMY
X
-4164
-4180
-4196
-4212
-4228
-4244
-4260
-4276
-4292
-4308
-4324
-4340
-4356
-4372
-4388
-4404
-4420
-4436
-4452
-4468
-4484
-4500
-4516
-4532
-4548
-4564
-4580
-4596
-4612
-4628
-4644
-4660
-4676
-4692
-4708
-4724
-4740
-4756
-4772
Y
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
Alignment mark
X
Y
A1
A2
-4841
4841
-220
-220
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.17Apr, 2010
HX8353-D
132RGB x 162 dots, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
4.4 Alignment mark
A_MARK (A1)
10 um 5um
15 um
10 um
15 um
5 um
20 um
15 um
15 um
15um 15 um 20um 15 um
15 um
A_MARK (A2)
5 um 10 um
15 um
10um
15 um
5 um
20um
15um
15um
15 um 15 um 20 um 15um
15um
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.18Apr, 2010
HX8353-D
132RGB x 162 dots, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
4.5 Bump size
90µm
35 µm X 90 µm
50µm
35µm
Input/Output PAD
90µm
40 µm X90 µm
60µm
40µm
Note: 35µmX90µm : Pad no. 1~62
Pad no. 90~185
40µmX90µm: Pad no. 63~89
16µm
19µm
Output PAD
98µm
16 µm X 98 µm
32µm
Note: 16µmX98µm : Pad no.186~759
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.19Apr, 2010
HX8353-D
132RGB x 162 dots, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
5. Interface
5.1 System interface
The HX8353-D supports parallel 80-system and 68-system 18-/16-/9-/8-bits bus
interface mode and 3-/4- wires serial interface mode. When NCS = “L”, the parallel
and serial bus system interface of the HX8353-D become active and data transfer
through the interface circuit is available. The DNC_SCL pin specifies whether the
system interface circuit access is to the register command or to the GRAM. The input
bus width format of system interface circuit is selected by external pins BS2-0. For
selecting the format of input bus, please refer to Table 5.1 and Table 5.2.
The HX8353-D includes command code and the following parameter and GRAM data.
The command code can be written through data bus by setting DNC_SCL=0. Then
the command or GRAM data can be written to register at which that index pointer
pointed by setting DNC_SCL=1.
Furthermore, there are two 18-bit bus control registers used to temporarily store the
data written to or read from the GRAM. When the data is written into the GRAM from
the MPU, it is first written into the write-data latch and then automatically written into
the GRAM by internal operation. Data is read through the read-data latch when
reading from the GRAM. Therefore, the first read data operation is invalid and the
following read data operations are valid.
SPI_SEL
x
x
x
x
x
x
x
x
0
1
P68
0
0
0
0
1
1
1
1
x
x
BS2
1
1
1
1
1
1
1
1
0
0
BS1
0
0
1
1
0
0
1
1
x
x
BS0
0
1
0
1
0
1
0
1
x
x
Interface
80-system 8-bit Parallel
80-system 16-bit Parallel
80-system 9-bit Parallel
80-system 18-bit Parallel
68-system 8-bit Parallel
68-system 16-bit Parallel
68-system 9-bit Parallel
68-system 18-bit Parallel
3 wire serial Interface only
4 wire serial Interface only
Table 5.1 Interface selection
Interface
NRD_E
80-system 8-bit Parallel
80-system 9-bit Parallel
80-system 16-bit Parallel
80-system 18-bit Parallel
3 wire serial Interface
68-system 8-bit Parallel
68-system 9-bit Parallel
68-system 16-bit Parallel
68-system 18-bit Parallel
4 wire serial Interface
NRD
NRD
NRD
NRD
E
E
E
E
-
NWR_RNW DNC_SCL
NWR
NWR
NWR
NWR
RW
RW
RW
RW
DNC
DNC
DNC
DNC
DNC
SCL
DNC
DNC
DNC
DNC
SCL
DB17 – DB0
Command/Parameter
DB7-DB0
DB7-DB0
DB7-DB0
DB7-DB0
DB0 as SDA
DB7-DB0
DB7-DB0
DB7-DB0
DB7-DB0
DB0 as SDA
GRAM
DB7-DB0
DB8-DB0
DB15-DB0
DB17-DB0
DB7-DB0
DB8-DB0
DB15-DB0
DB17-DB0
Table 5.2 Interface mode selection
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.20Apr, 2010
HX8353-D
132RGB x 162 dots, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
5.1.1 Parallel bus system interface
The input / output data from data pins (DB17-0) and signal operation of the I80/M68
series parallel bus interface as listed in Table 5.3 and Table 5.4.
Operations
NWR_RNW
NRD_E
Writes command code
0
1
Reads internal status
1
0
Writes parameter into command or data into GRAM
0
1
Reads parameter from command or data from GRAM
1
0
Table 5.3 Data pin function for I80 series CPU
DNC_SCL
0
0
1
1
Operations
NWR_RNW
NRD_E
Writes command code
0
1
Reads internal status
1
1
Writes parameter into command or data into GRAM
0
1
Reads parameter from command or data from GRAM
1
1
Table 5.4 Data pin function for M68 series CPU
DNC_SCL
0
0
1
1
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.21Apr, 2010
HX8353-D
132RGB x 162 dots, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
Write to register
1 byte command
2
S
byte command
CMD
CMD
CMD
CMD
PA1
n byte command
CMD
PA1
PAn-3
PAn-2
PA n-1
CMD
PA1
PAn-3
PAn-2
PA n-1
NCS
DNC_SCL
NRD_E
NWR_RNW
HOST DB7-0
(MPU to LCD)
Driver DB7-0
( LCD to MPU)
PA1
Hi - Z
CMD: command code
PA: parameter
Read from register
2 byte command
S
n byte command
CMD
dummy
PA1
CMD
dummy
CMD
dummy
PA1
CMD
dummy
PA1
PAn-3
PAn-2
PAn-1
PAn-3
PAn-2
PAn-1
PAn-3
PAn-2
PAn-1
NCS
DNC _ SCL
NRD_E
NWR_RNW
DB7-0
HOST DB7-0
( MPU to LCD )
Driver DB7-0
( LCD to MPU)
CMD
Hi-Z
Hi-Z
dummy
CMD: command code
PA1
Hi-Z
CMD
PA1
Hi-Z
dummy
PA1
PA: parameter
Figure 5.1 Register read/write timing in parallel bus system interface (for I80 series MPU)-1
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.22Apr, 2010
HX8353-D
132RGB x 162 dots, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
Write to register
1 byte command
2
S
byte command
CMD
CMD
CMD
CMD
n byte command
PA1
CMD
PA1
FDh
PA2
FDh
PA n-1
CMD
PA1
FDh
PA2
FDh
PA n-1
NCS
DNC_SCL
NRD_E
NWR_RNW
HOST DB7-0
(MPU to LCD)
Driver DB7-0
( LCD to MPU)
PA1
Hi - Z
CMD: command code
PA: parameter
Read from register
2 byte command
S
CMD
dummy
CMD
dummy
FCh
n byte command
PA1
CMD
dummy
PA1
CMD
dummy
FCh
PA1
FCh
PA n-1
NCS
DNC _ SCL
NRD_E
NWR_RNW
DB7-0
HOST DB7-0
( MPU to LCD )
Driver DB7-0
( LCD to MPU)
CMD
Hi-Z
FCh
Hi-Z
Hi-Z
FCh
dummy
Hi-Z
CMD: command code
Hi-Z
CMD
PA1
FCh
Hi-Z
FCh
dummy
Hi-Z
PA1
Hi-Z
PA1
FCh
FCh
Hi-Z
PA n-1
Hi-Z
PA n-1
PA: parameter
Figure 5.2 Register read/write timing in parallel bus system interface (for I80 series MPU)-2
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.23Apr, 2010
HX8353-D
132RGB x 162 dots, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
Write to register
1 byte command
2 byte command
S
CMD
CMD
CMD
CMD
PA1
n byte command
CMD
PA1
PAn-3
PAn-2
PA n-1
CMD
PA1
PAn-3
PAn-2
PA n-1
NCS
DNC_SCL
NWR_RNW
NRD_E
HOST DB7-0
(MPU to LCD)
PA1
H
-Z
i
Driver DB7-0
(LCD to MPU)
CMD: command code
PA: parameter
Read from register
2 byte command
S
n byte command
CMD
dummy
PA1
CMD
dummy
CMD
dummy
PA1
CMD
dummy
PA1
PAn-3
PAn-2
PA n-1
NCS
DNC _ SCL
NWR_RNW
NRD_E
DB 7 -0
HOST DB7-0
( MPU to LCD )
Driver DB7-0
(LCD to MPU)
Hi-Z
CMD
Hi-Z
dummy
CMD: command code
PA1
Hi-Z
PAn-2
PA n-1
PAn-3
PAn-2
PA n-1
Hi-Z
CMD
PA1
PAn-3
dummy
PA1
PA: parameter
Figure 5.3 Register read/write timing in parallel bus system interface (for M68 series MPU)-1
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.24Apr, 2010
HX8353-D
132RGB x 162 dots, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
Write to register
1 byte command
2 byte command
S
CMD
CMD
CMD
CMD
n byte command
PA1
CMD
PA1
FDh
PA2
FDh
PA n-1
CMD
PA1
FDh
PA2
FDh
PA n-1
NCS
DNC_SCL
NWR_RNW
NRD_E
HOST DB7-0
(MPU to LCD)
PA1
H
-Z
i
Driver DB7-0
(LCD to MPU)
CMD: command code
PA: parameter
Read from register
2 byte command
S
CMD
dummy
CMD
dummy
FCh
n byte command
PA1
CMD
dummy
PA1
CMD
dummy
FCh
PA1
FCh
PA n-1
NCS
DNC _ SCL
NWR_RNW
NRD_E
DB7-0
HOST DB7-0
( MPU to LCD )
Driver DB7-0
( LCD to MPU)
CMD
Hi-Z
FCh
Hi-Z
Hi-Z
FCh
dummy
Hi-Z
CMD: command code
Hi-Z
CMD
PA1
FCh
Hi-Z
FCh
dummy
Hi-Z
PA1
Hi-Z
PA1
FCh
FCh
Hi-Z
PA n-1
Hi-Z
PA n-1
PA: parameter
Figure 5.4 Register read/write timing in parallel bus system interface (for M68 series MPU)-2
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.25Apr, 2010
HX8353-D
132RGB x 162 dots, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
Write to GRAM
n pixel RAM data write
S
2Ch
Data 1
Data n-2
Data n-1
Data n
2Ch
Data 1
Data n-2
Data n-1
Data n
NCS
DNC_SCL
NRD_E
NWR_RNW
(MPU to LCD)
Hi - Z
(LCD to MPU )
CMD: command code
PA: parameter
Read from GRAM
n pixel RAM data read
S
2Eh
dummy
Data 1
2Eh
dummy
Data1
Data n-2
Data n-1
Data n
Data n-2
Data n-1
Data n
NCS
DNC_ SCL
NRD_E
NWR_WNR
( MPU to LCD )
(LCD to MPU)
Hi - Z
2Eh
Hi -Z
dummy
Data 1
Data n-2
Data n-1
Data n
Figure 5.5 GRAM read/write timing in parallel bus system interface (for I80 series MPU)
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.26Apr, 2010
HX8353-D
132RGB x 162 dots, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
Write to GRAM
n pixel RAM data write
S
2Ch
Data 1
Data n-2
Data n-1
Data n
2Ch
Data 1
Data n-2
Data n-1
Data n
NCS
DNC_SCL
NWR_RNW
NRD_E
(MPU to LCD)
Hi - Z
(LCD to MPU )
CMD: command code
PA: parameter
Read from GRAM
n pixel RAM data read
S
2Eh
dummy
Data 1
2Eh
dummy
Data1
Data n-1
Data n
Data n-2
Data n-1
Data n
Data n-2
Data n-1
Data n
Data n-2
NCS
DNC _ SCL
NWR_RNW
NRD_E
( MPU to LCD )
(LCD to MPU)
Hi - Z
2Eh
Hi - Z
dummy
Data 1
:
Figure 5.6 GRAM read/write timing in parallel bus system interface (for M68 series MPU)
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.27Apr, 2010
HX8353-D
132RGB x 162 dots, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
5.1.2 MCU data color coding
MCU Data Color Coding for RAM data Write
- Parallel 8-Bit Bus Interface (BS2,BS1,BS0=”100”)
Register
Command
D17
D16
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
x
x
x
x
x
x
x
x
x
x
0
0
1
0
1
1
0
0
3AH
D17
D16
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
R3
B3
G3
R4
G2
R5
G5
B5
R2
B2
G2
R3
G1
R4
G4
B4
R1
B1
G1
R2
G0
R3
G3
B3
R0
B0
G0
R1
B4
R2
G2
B2
G3
R3
B3
R0
B3
R1
G1
B1
G2
R2
B2
G5
B2
R0
G0
B0
G1
R1
B1
G4
B1
x
x
x
G0
4K-Color
R0 (2-pixel/ 3-bytes)
B0
G3
65K-Color
B0 (1-pixel/ 2-bytes)
x
262K-Color
x
(1-pixel/ 3bytes)
x
03h
05h
06h
Command
2CH
Color
Table 5.5 8-bit parallel interface GRAM write table
- Parallel 16-Bit Bus Interface (BS2,BS1,BS0=”101”)
Register
Command
D17
D16
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
x
x
x
x
x
x
x
x
x
x
0
0
1
0
1
1
0
0
3AH
03h
05h
D17
D16
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
x
x
x
x
x
x
x
x
x
x
x
R4
R5
B5
G5
x
R3
R4
B4
G4
x
R2
R3
B3
G3
x
R1
R2
B2
G2
R3
R0
R1
B1
G1
R2
G5
R0
B0
G0
R1
G4
x
x
x
R0
G3
x
x
x
G3
G2
G5
R5
B5
G2
G1
G4
R4
B4
G1
G0
G3
R3
B3
G0
B5
G2
R2
B2
B3
B4
G1
R1
B1
B2
B3
G0
R0
B0
B1
B2
x
x
x
B0
B1
x
x
x
06h
Command
2CH
Color
4K-Color
65K-Color
262K-Color
(2-pixel/ 3bytes)
Table 5.6 16-bit parallel interface GRAM write table
- Parallel 9-Bit Bus Interface (BS2,BS1,BS0=”110”)
Register
Command
D17
D16
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
x
x
x
x
x
x
x
x
x
x
0
0
1
0
1
1
0
0
3AH
D17
D16
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
06h
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
R5
G2
R4
G1
R3
G0
R2
B5
R1
B4
R0
B3
G5
B2
G4
B1
G3
B0
DB2 DB1
DB0
Register
2CH
Color
262K-Color
(1-pixel/ 2bytes)
Table 5.7 9-bit parallel interface GRAM write table
- Parallel 18-Bit Bus Interface (BS2,BS1,BS0=”111”)
Register
Command
DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9
3AH
06h
DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9
x
R5
x
R4
x
R3
x
R2
x
R1
x
R0
x
G5
x
G4
x
G3
DB8 DB7
x
0
DB6 DB5
0
1
DB4 DB3
0
1
1
0
0
DB8 DB7
DB6 DB5
DB4 DB3
DB2 DB1
DB0
G2
G0
B4
B2
B0
G1
B5
B3
B1
Register
2CH
Color
262K-Color
Table 5.8 18-bit parallel interface GRAM write table
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.28Apr, 2010
HX8353-D
132RGB x 162 dots, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
8-bit bus interface
The I80-system 8-bit parallel bus interface can be used by setting external pins “P68,
BS2, BS1, BS0” pins to “0100”. And the M68-system 8-bit parallel bus interface can
be used by setting “P68, BS2, BS1, and BS0” pins to “1100”. Figure 5.7 is the
example of interface with I80/M68 microcomputer system interface and Figure 5.8
~Figure 5.10 is bit format per pixel color order.
NCS
DNC_SCL
NWR_RNW
NRD_E
/
8
DB7-0
/
DB17-8
10
Figure 5.7 Example of 80- / 68- system 8-bit bus interface
262k Color
Data
MEMWR
1st write
2nd write
3rd write
4th write
5th write
6th write
DNC_
SCL
0
1
1
1
1
1
1
DB7
R15
G15
B15
R25
G25
B25
DB6
DB5
DB4
DB3
DB2
DB1
GRAM Write command code
R14 R13 R12 R11 R10
x
G14 G13 G12 G11 G10 x
B14 B13 B12 B11 B10
x
R24 R23 R22 R21 R20
x
G24 G23 G22 G21 G20 x
B24 B23 B22 B21 B20
x
18-bit
DB0
GRAM Write
x
x
x
x
x
x
1st pixel (R1/G1/B1)
2nd pixel (R2/G2/B2)
18-bit
GRAM
R1
G1
B1
R2
G2
B2
R3
G3
B3
Figure 5.8 Write data for RGB 6-6-6-bit input
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.29Apr, 2010
HX8353-D
132RGB x 162 dots, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
4k Color
Data
MEMWR
1st write
2nd write
3rd write
DNC_
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
SCL
0
GRAM Write command code
R13 R12 R11 R10 G13 G12 G11 G10
1
B13 B12 B11 B10 R23 R22 R21 R20
1
G23 G22 G21 G20 B23 B22 B21 B20
1
GRAM Write
1st pixel (R1/G1/B1)
2nd pixel (R2/G2/B2)
12-bit
12-bit
Look-Up Table for 4k Color data mapping (12-bit to 18-bit)
18-bit
18-bit
GRAM
R1
G1
B1
R2
G2
B2
R3
G3
B3
Figure 5.9 Write data for RGB 4-4-4-bit input
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.30Apr, 2010
HX8353-D
132RGB x 162 dots, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
6 5 k C o lo r
D a ta
M EM W R
1 s t w r ite
2 n d w r ite
3 r d w r ite
4 th w r ite
DNC_
SCL
0
1
1
1
1
DB7
R 14
G 12
R 24
G 22
DB6
DB5
DB4
DB3
DB2
DB1
G R A M W r ite c o m m a n d c o d e
R 13 R 12 R 11 R 10 G 15 G 14
G 11 G 10 B14 B13 B12 B 11
R 23 R 22 R 21 R 20 G 25 G 24
G 21 G 20 B24 B23 B22 B 21
1 6 - b it
DB0
G R A M W r ite
G 13
B10
G 23
B20
1 s t p ix e l ( R 1 /G 1 /B 1 )
2 n d p ix e l ( R 2 /G 2 /B 2 )
1 6 - b it
L o o k - U p T a b le fo r 6 5 k C o lo r d a ta m a p p in g ( 1 6 - b it to 1 8 - b it )
1 8 - b it
1 8 - b it
GRAM
R1
G1
B1
R2
G2
B2
R3
G3
B3
Figure 5.10 Write data for RGB 5-6-5-bit input
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.31Apr, 2010
HX8353-D
132RGB x 162 dots, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
16-bit parallel bus system interface
The I80-system 16-bit parallel bus interface in command-parameter interface mode
can be used by setting external pins “P68, BS2, BS1, BS0” pins to “0101”. And the
M68-system 16-bit parallel bus interface in MPU interface mode can be used by
setting “P68, BS2, BS1” pins to “1101”. The Figure 5.11 is the example of interface
with I80/M68 microcomputer system interface. There are three types of data format to
write display data at 18-bit bus Interface. See Figure 5.12 ~ Figure 5.14.
Figure 5.11 Example of I80- / M68- system 16-bit parallel bus interface
Figure 5.12 GRAM write data for RGB 6-6-6-(262k colors) bit input
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.32Apr, 2010
HX8353-D
132RGB x 162 dots, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
4k Color
Data
MEMWR
1st write
2nd write
DNC_S
DB15 DB14 DB13 DB12 DB11 DB10
CL
0
1
1
x
x
x
x
x
x
x
x
R13
R23
DB4
DB3
DB2
DB1
DB0
GRAM Write
GRAM Write command code
R12 R11 R10 G13 G12 G11 G10
R22 R21 R20 G23 G22 G21 G20
B13
B23
B12
B22
B11
B21
B10
B20
1st pixel (R1/G1/B1)
2nd pixel (R2/G2/B2)
DB9
DB8
DB7
12-bit
DB6
DB5
12-bit
Look-Up Table for 4k Color data mapping (12-bit to 18-bit)
18-bit
18-bit
GRAM
R1
G1
B1
R2
G2
B2
R3
G3
B3
Figure 5.13 Write data for RGB 4-4-4 (4k colors) bit input on 16-bit parallel interface
65k Color
Data
MEMWR
1st write
2nd write
DNC_S
DB15 DB14 DB13 DB12 DB11 DB10
CL
0
1
1
x
x
x
R14 R13 R12
R24 R23 R22
x
R11
R21
DB1
DB0
GRAM Write
x
x
x
x
GRAM Write command code
R10 G15 G14 G13 G12 G11 G10 B14 B13 B12 B11
R20 G25 G24 G23 G22 G21 G20 B24 B23 B22 B21
B10
B20
1st pixel (R1/G1/B1)
2nd pixel (R2/G2/B2)
DB9
DB8
DB7
16-bit
DB6
DB5
DB4
DB3
DB2
16-bit
Look-Up Table for 65k Color data mapping (16-bit to 18-bit)
18-bit
18-bit
GRAM
R1
G1
B1
R2
G2
B2
R3
G3
B3
Figure 5.14 Write data for RGB 5-6-5 (65k colors) bit input on 16-bit parallel interface
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.33Apr, 2010
HX8353-D
132RGB x 162 dots, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
18-bit parallel bus system interface
The I80-system 18-bit parallel bus interface in MPU interface mode can be used by
setting external pins “P68, BS2, BS1, BS0” pins to “0111”. And the M68-system 18-bit
parallel bus interface in MPU interface mode can be used by setting “P68, BS2, BS1,
BS0” pins to “1111”. The Figure5.15 is the example of interface with I80/M68
microcomputer system interface.
Figure 5.15 Example of I80- / M68- system 18-bit parallel bus interface
There is one type of data format to write display data at 18-bit bus Interface. See
Figure 5.16.
Figure 5.16 Write data for RGB 6-6-6(262k colors) bit input in 18-bit parallel interface
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.34Apr, 2010
HX8353-D
132RGB x 162 dots, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
9-bit bus interface
The I80-system 9-bit parallel bus interface in MPU interface mode can be used by
setting external pins “P68, BS2, BS1, BS0” pins to “0110”. And the M68-system 9-bit
parallel bus interface in MPU interface mode can be used by setting “P68, BS2, BS1,
BS0” pins to “1110”. The Figure5.17 is the example of interface with I80/M68
microcomputer system interface.
NCS
DNC_SCL
NWR_RNW
NRD_E
/
9
DB8-0
/
DB17-9
9
Figure 5.17 Example of 80- / 68- system 9-bit bus interface
There is one type of data format to write display data at 9-bit bus Interface. See Figure
5.18.
Figure 5.18 Write data for RGB 6-6-6-bit (262k colors) input in 9-bit parallel interface
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.35Apr, 2010
HX8353-D
132RGB x 162 dots, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
MCU Data Color Coding for RAM data Read
- Parallel 8-Bit Bus Interface (BS2,BS1,BS0=”100”)
Register
Command
Read
Data Format
D17
D16
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
x
x
x
x
x
x
x
x
x
x
0
0
1
0
1
1
1
0
D17
D16
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
R5
G5
B5
x
R4
G4
B4
x
R3
G3
B3
x
R2
G2
B2
x
R1
G1
B1
x
R0
G0
B0
x
x
x
x
x
x
x
x
Command
2EH
Color
Dummy Read
262K-Color
(1-pixel/ 3bytes)
Table 5.9 8-bit parallel interface GRAM read table
- Parallel 16-Bit Bus Interface (BS2,BS1,BS0=”101”)
Register
Command
Read
Data Format
D17
D16
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
x
x
x
x
x
x
x
x
x
x
0
0
1
0
1
1
1
0
D17
D16
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
x
x
x
x
x
x
x
x
x
R5
B5
G5
x
R4
B4
G4
x
R3
B3
G3
x
R2
B2
G2
x
R1
B1
G1
x
R0
B0
G0
x
x
x
x
x
x
x
x
x
G5
R5
B5
x
G4
R4
B4
x
G3
R3
B3
x
G2
R2
B2
x
G1
R1
B1
x
G0
R0
B0
x
x
x
x
x
x
x
x
Command
2EH
Color
Dummy Read
262K-Color
(2-pixel/ 3bytes)
Table 5.10 16-bit parallel interface GRAM read table
- Parallel 9-Bit Bus Interface (BS2,BS1,BS0=”110”)
Register
Command
Read
Data Format
D17
D16
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
x
x
x
x
x
x
x
x
x
x
0
0
1
0
1
1
1
0
D17
D16
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
R5
G2
x
R4
G1
x
R3
G0
x
R2
B5
x
R1
B4
x
R0
B3
x
G5
B2
x
G4
B1
x
G3
B0
Register
2EH
Color
Dummy Read
262K-Color
(1-pixel/ 2bytes)
Table 5.11 9-bit parallel interface GRAM read table
- Parallel 18-Bit Bus Interface (BS2,BS1,BS0=”111”)
Register
Command
Read
Data Format
D17
D16
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
x
x
x
x
x
x
x
x
x
x
0
0
1
0
1
1
1
0
D17
D16
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
x
R5
x
R4
x
R3
x
R2
x
R1
x
R0
x
G5
x
G4
x
G3
x
G2
x
G1
x
G0
x
B5
x
B4
x
B3
x
B2
x
B1
x
B0
Register
2EH
Color
Dummy Read
262K-Color
Table 5.12 18-bit parallel interface GRAM read table
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.36Apr, 2010
HX8353-D
132RGB x 162 dots, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
5.1.3 Serial Interface
The HX8353-D supports serial data transfer interface. The interface selection by
setting BS2=0 for serial interface mode. The 3-wires serial bus and 4-wires serial bus
is select by SPI_SEL pin. When SPI_SEL pin is low (VSSD), it is selected by 3-wires
serial bus and use: chip select line (NCS), serial input/output data (SDA), and the
serial transfer clock line (DNC_SCL). When SPI_SEL pin is high (IOVCC), it is
selected by 4-wires serial bus and use: chip select line (NCS), serial input/output data
(SDA), and the serial transfer clock line (DNC_SCL) and the command or data
transfer signal (NWR_RNW).
Serial data write mode
The 3-wires serial data packet contains a control bit DNC and a transmission byte, and
in 4-wires serial case data packet contains just transmission byte and control bit DNC
is transferred by NWR_RNW pin. If NWR_RNW is low, the transmission byte is
command byte. If NWR_RNW is high, the transmission byte is stored to command
register or GRAM. The MSB is transmitted first. The serial interface is initialized when
NCS is high. In this state, DNC_SCL clock pulse or SDA data have no effect. A falling
edge on NCS enables the serial interface and indicates the start of data transmission.
Figure 5.19 Serial interface protocol 3-/4- wire, write mode
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.37Apr, 2010
HX8353-D
132RGB x 162 dots, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
Serial data read mode
The microcontroller first has to send a command and then the following byte is
transmitted in the opposite direction. The read mode has three type command data
transmitted (8- / 24- / 32-bit) is according command code.
3-Wire Serial Interface Protocol
Figure 5.20 3-wire serial interface protocol, read mode
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.38Apr, 2010
HX8353-D
132RGB x 162 dots, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
4-Wire Serial Interface Protocol
Figure 5.21 4-wire serial interface protocol, read mode
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.39Apr, 2010
HX8353-D
132RGB x 162 dots, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
The data format that write display data to SRAM at Serial data bus Interface is shown
as Figure5. 22 ~ Figure5. 27.
Figure 5.22 3-wire serial write data for RGB (6-6-6) bit input
DNC_SCL
SDA
1
R13 R12 R11 R10 G13 G12 G11 G10
1
B13 B12 B11 B10 R23 R22 R21 R20
12-bit
Look-Up Table for 4K Color data mapping (12-bit to 18-bit)
18-bit
18-bit
GRAM
R1
G1
B1
R2
G2
B2
R3
G3
B3
Figure 5.23 3-wire serial write data for RGB 4-4-4-bit input
DNC_SCL
SDA
1
R14 R13 R12 R11 R10 G15 G14 G13
1
G12 G11 G10 B14 B13 B12 B11 B10
16-bit
Look-Up Table for 65K Color data mapping (16-bit to 18-bit)
18-bit
18-bit
GRAM
R1
G1
B1
R2
G2
B2
R3
G3
B3
Figure 5.24 3-wire serial write data for RGB 5-6-5-bit input
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.40Apr, 2010
HX8353-D
132RGB x 162 dots, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
Figure 5.25 4-wire serial write data for RGB (6-6-6) bit input
NWR_RNW
1
1
DNC_SCL
SDA
R13 R12 R11 R10 G13 G12 G11 G10 B13 B12 B11 B10 R23 R22 R21 R20
12-bit
Look-Up Table for 4K Color data mapping (12-bit to 18-bit)
18-bit
18-bit
GRAM
R1
G1
B1
R2
G2
B2
R3
G3
B3
Figure 5.26 4-wire serial write data for RGB 4-4-4-bit input
NWR_RNW
1
1
DNC_SCL
SDA
R14 R13 R12 R11 R10 G15 G14 G13 G12 G11 G10 B14 B13 B12 B11 B10
16-bit
Look-Up Table for 65K Color data mapping (16-bit to 18-bit)
18-bit
18-bit
GRAM
R1
G1
B1
R2
G2
B2
R3
G3
B3
Figure 5.27 4-wire serial write data for RGB 5-6-5-bit input
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.41Apr, 2010
HX8353-D
132RGB x 162 dots, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
5.1.4 Display module data transfer recovery
If there is a break on data transmission when transmitting a command before a whole
byte has been completed, then the display module will reset the interface so that it will
be ready to receive the same byte re-transmitted when the chip select line (NCS) is
next activated. See the following figure.
Figure 5.28 Display module data transfer recovery
If 1 or more parameter command is being sent and a break occurs while sending any
parameter before the last one and if the host then sends a new command rather than
re-transmitting the parameter that was interrupted, then the parameters that were
successfully sent are stored and the parameter where the break occurred is rejected.
The interface is ready to receive next byte as shown:
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.42Apr, 2010
HX8353-D
132RGB x 162 dots, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
5.1.5 Display module data transfer pause
It will be possible when transferring a Command, Frame Memory Data or Multiple
Parameter Data to invoke a pause in the data transmission. If the Chip Select Line is
released after a whole byte of a Frame Memory Data or Multiple Parameter Data has
been completed, then the Display Module will wait and continue the Frame Memory
Data or Parameter Data Transmission from the point where it was paused. If the Chip
Select Line is released after a whole byte of a command has been completed, then
the Display Module will receive either the command’s parameters (if appropriate) or a
new command when the Chip Select Line is next enabled as shown below:
Serial interface pause
This applies to the following 4 conditions:
a. Command-Pause-Command
b. Command-Pause-Parameter
c. Parameter-Pause-Command
d. Parameter-Pause-Parameter
Parallel interface pause
This applies to the following 4 conditions:
a. Command-Pause-Command
b. Command-Pause-Parameter
c. Parameter-Pause-Command
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.43Apr, 2010
HX8353-D
132RGB x 162 dots, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
d. Parameter-Pause-Parameter
5.1.6 Display module data transfer modes
The Module has three colour modes for transferring data to the display RAM. These
are 12-bit colour per pixel, 16-bit colour per pixel and 18-bit colour per pixel. The data
format is described for each interface. Data can be downloaded to the Frame Memory
by 2 methods.
Method 1:
The Image data is sent to the Frame Memory in successive Frame writes, each time
the Frame Memory is filled, the Frame Memory pointer is reset to the start point and
the next Frame is written.
Method 2:
Image Data is sent and at the end of each Frame Memory download, a command is
sent to stop Frame Memory Write. Then Start Memory Write command is sent, and a
new Frame is downloaded.
Stop
Start
Start Frame
Image Data
Memory
Frame 1
Write
Any
Command
Start Frame
Image Data
Memory
Frame 2
Write
Any
Command
Any
Command
Note: (1) These apply to all Data Transfer Colour modes on both Serial and Parallel interfaces.
(2) The Frame Memory can contain both odd and even number of pixels for both Methods. Only complete pixel
data will be stored in the Frame Memory.
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.44Apr, 2010
HX8353-D
132RGB x 162 dots, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
5.2 Color depth conversion
R input (4bit)
12 bit/pixel -mode
4,096 colors
R input (5 bit)
16 bit/pixel -mode
65,536 colors
R output (6bit)
18 bit/pixel -mode
262,144 colors
RGBSET Parameter
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
No Input
No Input
No Input
No Input
No Input
No Input
No Input
No Input
No Input
No Input
No Input
No Input
No Input
No Input
No Input
No Input
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
R005 R004 R003 R002 R001 R000
R015 R014 R013 R012 R011 R010
R025 R024 R023 R022 R021 R020
R035 R034 R033 R032 R031 R030
R045 R044 R043 R042 R041 R040
R055 R054 R053 R052 R051 R050
R065 R064 R063 R062 R061 R060
R075 R074 R073 R072 R071 R070
R085 R084 R083 R082 R081 R080
R095 R094 R093 R092 R091 R090
R105 R104 R103 R102 R101 R100
R115 R114 R113 R112 R111 R110
R125 R124 R123 R122 R121 R120
R135 R134 R133 R132 R131 R130
R145 R144 R143 R142 R141 R140
R155 R154 R153 R152 R151 R150
R165 R164 R163 R162 R161 R160
R175 R174 R173 R172 R171 R170
R185 R184 R183 R182 R181 R180
R195 R194 R193 R192 R191 R190
R205 R204 R203 R202 R201 R200
R215 R214 R213 R212 R211 R210
R225 R224 R223 R222 R221 R220
R235 R234 R233 R232 R231 R230
R245 R244 R243 R242 R241 R240
R255 R254 R253 R252 R251 R250
R265 R264 R263 R262 R261 R260
R275 R274 R273 R272 R271 R270
R285 R284 R283 R282 R281 R280
R295 R294 R293 R292 R291 R290
R305 R304 R303 R302 R301 R300
R315 R314 R313 R312 R311 R310
1
2
3
4
5
6
7
8
9
10
11
12
13
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16
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18
19
20
21
22
23
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25
26
27
28
29
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31
32
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.45Apr, 2010
HX8353-D
132RGB x 162 dots, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
G input (4bit)
12 bit/pixel -mode
4,096 colors
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
No Input
No Input
No Input
No Input
No Input
No Input
No Input
No Input
No Input
No Input
No Input
No Input
No Input
No Input
No Input
No Input
G input (6 bit)
16 bit/pixel -mode
65,536 colors
000000
000001
000010
000011
000100
000101
000110
000111
001000
001001
001010
001011
001100
001101
001110
001111
010000
010001
010010
010011
010100
010101
010110
010111
011000
011001
011010
011011
011100
011101
011110
011111
G output (6bit)
18 bit/pixel -mode
262,144 colors
G005 G004 G003 G002 G001 G000
G015 G014 G013 G012 G011 G010
G025 G024 G023 G022 G021 G020
G035 G034 G033 G032 G031 G030
G045 G044 G043 G042 G041 G040
G055 G054 G053 G052 G051 G050
G065 G064 G063 G062 G061 G060
G075 G074 G073 G072 G071 G070
G085 G084 G083 G082 G081 G080
G095 G094 G093 G092 G091 G090
G105 G104 G103 G102 G101 G100
G115 G114 G113 G112 G111 G110
G125 G124 G123 G122 G121 G120
G135 G134 G133 G132 G131 G130
G145 G144 G143 G142 G141 G140
G155 G154 G153 G152 G151 G150
G165 G164 G163 G162 G161 G160
G175 G174 G173 G172 G171 G170
G185 G184 G183 G182 G181 G180
G195 G194 G193 G192 G191 G190
G205 G204 G203 G202 G201 G200
G215 G214 G213 G212 G211 G210
G225 G224 G223 G222 G221 G220
G235 G234 G233 G232 G231 G230
G245 G244 G243 G242 G241 G240
G255 G254 G253 G252 G251 G250
G265 G264 G263 G262 G261 G260
G275 G274 G273 G272 G271 G270
G285 G284 G283 G282 G281 G280
G295 G294 G293 G292 G291 G290
G305 G304 G303 G302 G301 G300
G315 G314 G313 G312 G311 G310
RGBSET Parameter
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
33
34
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64
-P.46Apr, 2010
HX8353-D
132RGB x 162 dots, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
G input (4bit)
12 bit/pixel -mode
4,096 colors
No Input
No Input
No Input
No Input
No Input
No Input
No Input
No Input
No Input
No Input
No Input
No Input
No Input
No Input
No Input
No Input
No Input
No Input
No Input
No Input
No Input
No Input
No Input
No Input
No Input
No Input
No Input
No Input
No Input
No Input
No Input
No Input
G input (6 bit)
16 bit/pixel -mode
65,536 colors
100000
100001
100010
100011
100100
100101
100110
100111
101000
101001
101010
101011
101100
101101
101110
101111
110000
110001
110010
110011
110100
110101
110110
110111
111000
111001
111010
111011
111100
111101
111110
111111
G output (6bit)
18 bit/pixel -mode
262,144 colors
G325 G324 G323 G322 G321 G320
G335 G334 G333 G332 G331 G330
G345 G344 G343 G342 G341 G340
G355 G354 G353 G352 G351 G350
G365 G364 G363 G362 G361 G360
G375 G374 G373 G372 G371 G370
G385 G384 G383 G382 G381 G380
G395 G394 G393 G392 G391 G390
G405 G404 G403 G402 G401 G400
G415 G414 G413 G412 G411 G410
G425 G424 G423 G422 G421 G420
G435 G434 G433 G432 G431 G430
G445 G444 G443 G442 G441 G440
G455 G454 G453 G452 G451 G450
G465 G464 G463 G462 G461 G460
G475 G474 G473 G472 G471 G470
G485 G484 G483 G482 G481 G480
G495 G494 G493 G492 G491 G490
G505 G504 G503 G502 G501 G500
G515 G514 G513 G512 G511 G510
G525 G524 G523 G522 G521 G520
G535 G534 G533 G532 G531 G530
G545 G544 G543 G542 G541 G540
G555 G554 G553 G552 G551 G550
G565 G564 G563 G562 G561 G560
G575 G574 G573 G572 G571 G570
G585 G584 G583 G582 G581 G580
G595 G594 G593 G592 G591 G590
G605 G604 G603 G602 G601 G600
G615 G614 G613 G612 G611 G610
G625 G624 G623 G622 G621 G620
G635 G634 G533 G632 G631 G630
RGBSET Parameter
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
65
66
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96
-P.47Apr, 2010
HX8353-D
132RGB x 162 dots, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
B input (4bit)
12 bit/pixel -mode
4,096 colors
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
No Input
No Input
No Input
No Input
No Input
No Input
No Input
No Input
No Input
No Input
No Input
No Input
No Input
No Input
No Input
No Input
B input (5 bit)
16 bit/pixel -mode
65,536 colors
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
B output (6bit)
18 bit/pixel -mode
262,144 colors
B005 B004 B003 B002 B001 B000
B015 B014 B013 B012 B011 B010
B025 B024 B023 B022 B021 B020
B035 B034 B033 B032 B031 B030
B045 B044 B043 B042 B041 B040
B055 B054 B053 B052 B051 B050
B065 B064 B063 B062 B061 B060
B075 B074 B073 B072 B071 B070
B085 B084 B083 B082 B081 B080
B095 B094 B093 B092 B091 B090
B105 B104 B103 B102 B101 B100
B115 B114 B113 B112 B111 B110
B125 B124 B123 B122 B121 B120
B135 B134 B133 B132 B131 B130
B145 B144 B143 B142 B141 B140
B155 B154 B153 B152 B151 B150
B165 B164 B163 B162 B161 B160
B175 B174 B173 B172 B171 B170
B185 B184 B183 B182 B181 B180
B195 B194 B193 B192 B191 B190
B205 B204 B203 B202 B201 B200
B215 B214 B213 B212 B211 B210
B225 B224 B223 B222 B221 B220
B235 B234 B233 B232 B231 B230
B245 B244 B243 B242 B241 B240
B255 B254 B253 B252 B251 B250
B265 B264 B263 B262 B261 B260
B275 B274 B273 B272 B271 B270
B285 B284 B283 B282 B281 B280
B295 B294 B293 B292 B291 B290
B305 B304 B303 B302 B301 B300
B315 B314 B313 B312 B311 B310
RGBSET Parameter
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
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127
128
-P.48Apr, 2010
HX8353-D
132RGB x 162 dots, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
6. Display Data GRAM
The display data RAM stores display dots and consists of 384,912 bits (132x18x162
bits). There is no restriction on access to the RAM even when the display data on the
same address is loaded to DAC. There will be no abnormal visible effect on the
display when there is a simultaneous Panel Read and Interface Read or Write to the
same location of the Frame Memory.
6.1 Display data GRAM mapping
Every pixel (18-bit) data in GRAM is located by a (Page, Column) address (Y, X). By
specifying the arbitrary window address CASET’s SC, EC and PASET’s SP, EP, it is
possible to access the GRAM by setting RAMWR or RAMRD commands from start
positions of the window address.
0000H
0100H
0200H
0300H
0400H
0500H
0001H
0101H
0201H
0301H
0401H
0501H
0002H
0102H
0202H
0302H
0402H
0502H
0003H
0103H
0203H
0303H
0403H
0503H
-------------------------------------------------
-------
-------
-------
-------
---------
-------
-------
-------
-------
0080H
0180H
0280H
0380H
0480H
0580H
0081H
0181H
0281H
0381H
0481H
0581H
0082H
0182H
0282H
0382H
0482H
0582H
0083H
0183H
0283H
0383H
0483H
0583H
9C00H
9D00H
9E00H
9F00H
A000H
A100H
9C01H
9D01H
9E01H
9F01H
A001H
A101H
9C02H
9D02H
9E02H
9F02H
A002H
A102H
9C03H
9D03H
9E03H
9F03H
A003H
A103H
-------------------------------------------------
9C80H
9D80H
9E80H
9F80H
A080H
A180H
9C81H
9D81H
9E81H
9F81H
A081H
A181H
9C82H
9D82H
9E82H
9F82H
A082H
A182H
9C83H
9D83H
9E83H
9F83H
A083H
A183H
Table 6.1 GRAM address for display panel position
6.2 Address counter (AC) of GRAM
The HX8353-D contains an address counter (AC) which assigns address for
writing/reading pixel data to/from GRAM. The address pointers set the position of
GRAM. Every time when a pixel data is written into the GRAM, the X address or Y
address of AC will be automatically increased by 1 (or decreased by 1), which is
decided by the register (MADTCL’s MV(B5), MX(B6) and MY(B7) bits) setting.
To simplify the address control of GRAM access, the window address function allows
for writing data only to a window area of GRAM specified by registers. After data
being written to the GRAM, the AC will be increased or decreased within setting
window address-range which is specified by the CASET (start: SC, end: EC) and the
PASET (start: SP, end: EP). Therefore, the data can be written consecutively without
thinking a data wrap by those bit function.
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.49Apr, 2010
HX8353-D
132RGB x 162 dots, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
6.2.1 System interface to GRAM write direction
Data stream from MCU is like
this figure
B
E
Figure 6.1 Image data sending order from host
The data is written in the order illustrated above. The counter which dictates where in
the physical memory the data is to be written is controlled by MADTCL’s MV(B5),
MX(B6) and MY(B7) bits setting
CASET
MY
MX
MV
PASET
MADCTL
Virtual to physical Pointer
transtator
Virtual (0,0) when
MV = don't care,
MX = '0', MY = '0'
Physical Column
Pointer
(0,0)
(0,X)
Physical Page
Pointer
Physical
axes
(Y,0)
Virtual (0,0) when
MV = don't care,
MX = '0', MY = '1'
Virtual (0,0) when
MV = don't care,
MX = '1', MY = '0'
X=131d, Y= 161d
(Y,X)
Virtual (0,0) when
MV = don't care,
MX = '1', MY = '1'
Figure 6.2 Image data writing control
MV
0
0
0
0
1
1
1
1
MX
0
0
1
1
0
0
1
1
MY
CASET
PASET
0
Direct to Physical Column Pointer
Direct to Physical Page Pointer
1
Direct to Physical Column Pointer
Direct to (Y - Physical Page Pointer)
0
Direct to (X-Physical Column Pointer)
Direct to Physical Page Pointer
1
Direct to (X - Physical Column Pointer)
Direct to (Y - Physical Page Pointer)
0
Direct to Physical Page Pointer
Direct to Physical Column Pointer
1
Direct to (Y - Physical Page Pointer)
Direct to Physical Column Pointer
0
Direct to Physical Page Pointer
Direct to (X-Physical Column Pointer)
1
Direct to (Y - Physical Page Pointer)
Direct to (X - Physical Column Pointer)
Table 6.2 CASET and PASET control for physical column/page pointers
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.50Apr, 2010
HX8353-D
132RGB x 162 dots, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
For each image orientation, the controls for the column and page counters apply as
below:
Condition
When RAMWR/RAMRD command is accepted.
Complete Pixel Pair Write/Read action
The Column counter value is larger than “End column.”
The Page counter value is larger than “End page”.
Column Counter
Return to
“Start Column”
Increment by 1
Return to
“Start Column”
Return to
“Start Column”
Page Counter
Return to
“Start Page”
No change
Increment by 1
Return to
“Start Page”
Note: Data is always written to the Frame Memory in the same order, regardless of the Memory Write
Direction set by MADCTL bits B7, B6 and B5.
Table 6.3 Rules for updating GRAM order
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.51Apr, 2010
HX8353-D
132RGB x 162 dots, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
The following figure depicts the GRAM address update method with MV, MX and MY
bit setting.
Display
MADCTR
Data
parameter
Direction MV MX MY
Image in the
Host
Image in the Driver (GRAM)
H/W Position (0,0)
B
Normal
0
0
B
X,Y address (0,0)
X: CASET
Y: RASET
0
E
E
B
Y-Invert
0
0
H/W Position (0,0)
1
X,Y address (0,0)
X: CASET
Y: RASET
E
B
E
B
X-Invert
0
1
H/W Position (0,0)
B
X,Y address (0,0)
X: CASET
Y: RASET
0
E
E
H/W Position (0,0)
B
X-Invert
Y-Invert
0
1
E
1
X,Y address (0,0)
X: CASET
Y: RASET
B
E
B
X-Y
Exchange
1
0
H/W Position (0,0)
B
X,Y address (0,0)
X: CASET
Y: RASET
0
E
E
H/W Position (0,0)
B
X-Y
Exchange
X-invert
1
0
1
X,Y address (0,0)
X: CASET
Y: RASET
E
B
X-Y
Exchange
Y-invert
1
1
H /W
Position (0,0)
1
B
X ,Y address ( 0, 0)
X : CASET
Y : RASET
E
H/W Position (0,0)
B
1
B
0
E
X-Y
Exchange
X-invert
Y-invert
E
E
1
E
B
X,Y address (0,0)
X: CASET
Y: RASET
Table 6.4 Address direction settings
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.52Apr, 2010
HX8353-D
132RGB x 162 dots, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
Example for rotation with MY, MX and MV
This example is using following values: start page=0, end page=40, start column=0
and end column=20=> commands: page address set (0, 40) and column address set
(0, 20). The sent figure is as follows and its sending order is as follows.
Written image and direction from the host to frame memory
Image from the host
Writieg direction
Start page =0
Start
End page=40
End
Start column =0
Image position on the frame memory with MY
Memory
Location
(0,0)
FRAM
MEMOR
E
Y
MY =0
MX =0
MV =0
Memory
Location
(0,0)
MY =1
MX =0
MV =0
End column =20
= 0 / 1 , MX = 0 / 1 , MV = 0 / 1
Memory
Location
(0,0)
FRAM
MEMOR
E
Y
MY =0
MX =1
MV =0
FRAM
MEMOR
E
Y
Memory
Location
(0,0)
FRAM
MEMOR
E
Y
MY =1
MX =1
MV =0
Figure 6.3 Example for rotation with MY, MX and MV – 1
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.53Apr, 2010
HX8353-D
132RGB x 162 dots, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
Written image and direction from the host to frame memory
Image from the host
Writieg direction
Start page =0
Start
End page=40
End
Start column =0
Image position on the frame memory with MY
Memory
Location
(0,0)
FRAM
MEMOR
E
Y
MY =0
MX =0
MV =1
Memory
Location
(0,0)
MY =1
MX =0
MV =1
End column =20
= 0 / 1 , MX = 0 / 1 , MV = 0 / 1
Memory
Location
(0,0)
FRAM
MEMOR
E
Y
MY =0
MX =1
MV =1
FRAM
MEMOR
E
Y
Memory
Location
(0,0)
FRAM
MEMOR
E
Y
MY =1
MX =1
MV =1
Figure 6.4 Example for rotation with MY, MX and MV – 2
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.54Apr, 2010
HX8353-D
132RGB x 162 dots, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
6.3 Source, gate and memory map
6.3.1 When using 132 x 162 GRAM resolution, display resolution 132RGB x 162
(RSO[2:0]=3’b000 & STE_SEL=0)
Pixel1
Source Out
S1
S2
Pixel2
S3
S4
S5
Pixel131
S391
S6
S392
Pixel132
S393
S394
S395
S396
RGB Order
RA
MY=0
MY=1
0
1
2
3
4
5
6
7
8
9
10
11
:
:
:
:
:
:
154
155
156
157
158
159
160
161
161
160
159
158
157
156
155
154
153
152
151
150
:
:
:
:
:
:
7
6
5
4
3
2
1
0
CA
MX=0
MX= 1
SA
:RGB=0
:RGB=1
R0 5-0
:
:
:
:
:
:
G0
5-0
:
:
:
:
:
:
B0 5-0
:
:
:
:
:
:
R1 5-0
:
:
:
:
:
:
G1 5-0
:
:
:
:
:
:
B15-0
:
:
:
:
:
:
--
-------------
ML=0
R1305-0 G1305-0 B1305-0 R1315-0 G1315-0 B1315-0
1
2
3
4
5
6
7
8
9
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
Display Pattern Data
:
:
:
:
:
:
--------0
131
1
130
0
:
:
:
:
:
:
10
11
:
:
:
:
:
:
154
155
156
157
158
159
160
161
130
1
Gate
ML=1 ML=0
G1
161
160
G2
G3
G4
159
158
157
156
155
G5
G6
G7
G8
G9
G10
154
153
152
151
150
:
:
:
:
:
:
G11
G12
:
:
:
:
:
:
G155
7
6
G156
5
4
3
G157
G158
G159
G160
G161
G162
2
1
0
ML=1
G162
G161
G160
G159
G158
G157
G156
G155
G154
G153
G152
G151
:
:
:
:
:
:
G8
G7
G6
G5
G4
G3
G2
G1
131
0
Note: RA = Row Address,
CA = Column Address,
SA = Scan Address,
MX = Mirror X-axis (Column address direction parameter), DB6 parameter of MADCTL command
MY = Mirror Y-axis (Row address direction parameter), DB7 parameter of MADCTL command
ML = Scan direction parameter, DB4 parameter of MADCTL command
RGB= Red, Green and Blue pixel position change, DB3 parameter of MADCTL command
Figure 6.5 Memory map, 132 x 162 GRAM resolution, display resolution 132RGB x 162
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.55Apr, 2010
HX8353-D
132RGB x 162 dots, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
6.3.2 When using 132 x 162 GRAM resolution, display resolution 128RGB x 160
(RSO[2:0]=3’b000 & STE_SEL=1)
Pixel1
Source Out
S7
S8
Pixel2
S9
S10
S11
Pixel127
S385
S12
S386
Pixel128
S387
S388
S389
S390
RGB Order
RA
MY=0
MY=1
0
1
2
3
4
5
6
7
8
9
10
11
:
:
:
:
:
:
154
155
156
157
158
159
160
161
161
160
159
158
157
156
155
154
153
152
151
150
:
:
:
:
:
:
7
6
5
4
3
2
1
0
CA
MX=0
MX= 1
SA
:RGB=0
:RGB=1
R0 5-0
:
:
:
:
:
:
G0
5-0
:
:
:
:
:
:
B0 5-0
:
:
:
:
:
:
R1 5-0
:
:
:
:
:
:
G1 5-0
:
:
:
:
:
:
B15-0
:
:
:
:
:
:
--
-------------
ML=0
R1265-0 G1265-0 B1265-0 R1275-0 G1275-0 B1275-0
1
2
3
4
5
6
7
8
9
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
Display Pattern Data
:
:
:
:
:
:
--------0
127
1
126
0
:
:
:
:
:
:
10
11
:
:
:
:
:
:
154
155
156
157
158
159
160
161
126
1
Gate
ML=1 ML=0
161
160
-G2
159
158
G3
G4
G5
G6
G7
157
156
155
ML=1
-G161
G160
G159
G158
G157
G8
G9
G156
G155
G154
G10
G11
G12
G153
G152
G151
:
:
:
:
:
:
:
:
:
:
:
:
5
4
3
G155
G156
G157
G158
G159
G8
G7
G6
G5
2
1
G160
G161
G4
G3
G2
0
--
--
154
153
152
151
150
:
:
:
:
:
:
7
6
127
0
Note: RA = Row Address,
CA = Column Address,
SA = Scan Address,
MX = Mirror X-axis (Column address direction parameter), DB6 parameter of MADCTL command
MY = Mirror Y-axis (Row address direction parameter), DB7 parameter of MADCTL command
ML = Scan direction parameter, DB4 parameter of MADCTL command
RGB= Red, Green and Blue pixel position change, DB3 parameter of MADCTL command
Figure 6.6 Memory map, 132 x 162 GRAM resolution, display resolution 128RGB x 160
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.56Apr, 2010
HX8353-D
132RGB x 162 dots, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
6.3.3 When using 128 x 128 GRAM resolution, display resolution 128RGB x 128
(RSO[2:0]=3’b001)
Pixel1
Source Out
S7
S8
Pixel2
S9
S10
S11
Pixel127
S385
S12
S386
Pixel128
S387
S388
S389
S390
RGB Order
RA
MY=0
MY=1
0
1
2
3
4
5
6
7
8
9
10
11
:
:
:
:
:
:
120
121
122
123
124
125
126
127
127
126
125
124
123
122
121
120
119
118
117
116
:
:
:
:
:
:
7
6
5
4
3
2
1
0
CA
MX=0
MX= 1
SA
:RGB=0
:RGB=1
R0 5-0
G0
:
:
:
:
:
:
5-0
:
:
:
:
:
:
B0 5-0
:
:
:
:
:
:
R1 5-0
:
:
:
:
:
:
G1 5-0
:
:
:
:
:
:
B15-0
:
:
:
:
:
:
--
-------------
ML=0
R1265-0 G1265-0 B1265-0 R1275-0 G1275-0 B127 5-0
1
2
3
4
5
6
7
8
9
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
Display Pattern Data
:
:
:
:
:
:
--------0
127
1
126
0
:
:
:
:
:
:
10
11
:
:
:
:
:
:
120
121
122
123
124
125
126
127
126
1
Gate
ML=1 ML=0
127
126
125
124
123
122
121
120
119
118
117
116
:
:
:
:
:
:
7
6
5
4
3
2
1
0
G2
G3
G4
G5
G6
G7
G8
G9
G10
G11
G12
G13
:
:
:
:
:
:
G122
G123
G124
G125
G126
G127
G128
G129
ML=1
G129
G128
G127
G126
G125
G124
G123
G122
G121
G120
G119
G118
:
:
:
:
:
:
G9
G8
G7
G6
G5
G4
G3
G2
127
0
Note: RA = Row Address,
CA = Column Address,
SA = Scan Address,
MX = Mirror X-axis (Column address direction parameter), DB6 parameter of MADCTL command
MY = Mirror Y-axis (Row address direction parameter), DB7 parameter of MADCTL command
ML = Scan direction parameter, DB4 parameter of MADCTL command
RGB= Red, Green and Blue pixel position change, DB3 parameter of MADCTL command
Figure 6.7 Memory map, 128 x 128 GRAM resolution, display resolution 128RGB x 128
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.57Apr, 2010
HX8353-D
132RGB x 162 dots, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
6.3.4 When using 120 x 160 GRAM resolution, display resolution 120RGB x 160
(RSO[2:0]=3’b010)
Pixel1
Source Out
S7
S8
Pixel2
S9
S10
S11
Pixel119
S361
S12
S362
Pixel120
S363
S364
S365
S366
RGB Order
RA
MY=0
MY=1
0
1
2
3
4
5
6
7
8
9
10
11
:
:
:
:
:
:
152
153
154
155
156
157
158
159
159
158
157
156
155
154
153
152
151
150
149
148
:
:
:
:
:
:
7
6
5
4
3
2
1
0
CA
MX=0
MX= 1
SA
:RGB=0
:RGB=1
R0 5-0
G0
:
:
:
:
:
:
5-0
:
:
:
:
:
:
B0 5-0
:
:
:
:
:
:
R1 5-0
:
:
:
:
:
:
G1 5-0
:
:
:
:
:
:
B15-0
:
:
:
:
:
:
--
-------------
ML=0
R1185-0 G1185-0 B1185-0 R1195-0 G1195-0 B1195-0
1
2
3
4
5
6
7
8
9
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
Display Pattern Data
:
:
:
:
:
:
--------0
119
1
118
0
:
:
:
:
:
:
10
11
:
:
:
:
:
:
152
153
154
155
156
157
158
159
118
1
Gate
ML=1 ML=0
159
158
157
156
155
154
153
152
151
150
149
148
:
:
:
:
:
:
7
6
5
4
3
2
1
0
G2
G3
G4
G5
G6
G7
G8
G9
G10
G11
G12
G13
:
:
:
:
:
:
G154
G155
G156
G157
G158
G159
G160
G161
ML=1
G161
G160
G159
G158
G157
G156
G155
G154
G153
G152
G151
G150
:
:
:
:
:
:
G9
G8
G7
G6
G5
G4
G3
G2
119
0
Note: RA = Row Address,
CA = Column Address,
SA = Scan Address,
MX = Mirror X-axis (Column address direction parameter), DB6 parameter of MADCTL command
MY = Mirror Y-axis (Row address direction parameter), DB7 parameter of MADCTL command
ML = Scan direction parameter, DB4 parameter of MADCTL command
RGB= Red, Green and Blue pixel position change, DB3 parameter of MADCTL command
Figure 6.8 Memory map, 120 x 160 GRAM resolution, display resolution 120RGB x 160
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.58Apr, 2010
HX8353-D
132RGB x 162 dots, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
6.3.5 When using 128 x 160 GRAM resolution, display resolution 128RGB x 160
(RSO[2:0]=3’b011)
Pixel1
Source Out
S7
S8
Pixel2
S9
S10
S11
Pixel127
S385
S12
S386
Pixel128
S387
S388
S389
S390
RGB Order
RA
MY=0
MY=1
0
1
2
3
4
5
6
7
8
9
10
11
:
:
:
:
:
:
152
153
154
155
156
157
158
159
159
158
157
156
155
154
153
152
151
150
149
148
:
:
:
:
:
:
7
6
5
4
3
2
1
0
CA
MX=0
MX= 1
R0 5-0
G0
:
:
:
:
:
:
5-0
:
:
:
:
:
:
B0 5-0
:
:
:
:
:
:
R1 5-0
:
:
:
:
:
:
G1 5-0
:
:
:
:
:
:
B15-0
:
:
:
:
:
:
--
-------------
ML=0
R1265-0 G1265-0 B1265-0 R1275-0 G1275-0 B1275-0
3
4
5
6
7
8
9
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
Display Pattern Data
1
126
0
1
2
:
:
:
:
:
:
--------0
127
Gate
SA
:RGB=0
:RGB=1
:
:
:
:
:
:
10
11
:
:
:
:
:
:
152
153
154
155
156
157
158
159
126
1
ML=1 ML=0
G2
159
158
G3
G4
G5
157
156
155
154
153
152
151
150
149
148
:
:
:
:
:
:
7
6
5
4
3
2
1
0
G6
G7
G8
G9
G10
G11
G12
G13
:
:
:
:
:
:
G154
G155
G156
G157
G158
G159
G160
G161
ML=1
G161
G160
G159
G158
G157
G156
G155
G154
G153
G152
G151
G150
:
:
:
:
:
:
G9
G8
G7
G6
G5
G4
G3
G2
127
0
Note: RA = Row Address,
CA = Column Address,
SA = Scan Address,
MX = Mirror X-axis (Column address direction parameter), DB6 parameter of MADCTL command
MY = Mirror Y-axis (Row address direction parameter), DB7 parameter of MADCTL command
ML = Scan direction parameter, DB4 parameter of MADCTL command
RGB= Red, Green and Blue pixel position change, DB3 parameter of MADCTL command
Figure 6.9 Memory map, 128 x 160 GRAM resolution, display resolution 128RGB x 160
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.59Apr, 2010
HX8353-D
132RGB x 162 dots, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
6.3.6 When using 96 x 68 GRAM resolution, display resolution 96RGB x 68
(RSO[2:0]=3’b100)
Pixel1
Source Out
S55
S56
Pixel2
S57
S58
S59
Pixel95
S337
S60
S338
Pixel 96
S339
S340
S341
S342
RGB Order
RA
MY=0
MY=1
0
1
2
3
4
5
6
7
8
9
10
11
:
:
:
:
:
:
60
61
62
63
64
65
66
67
67
66
65
64
63
62
61
60
59
58
57
56
:
:
:
:
:
:
7
6
5
4
3
2
1
0
CA
MX=0
MX= 1
SA
:RGB=0
:RGB=1
R0 5-0
G0
:
:
:
:
:
:
5-0
:
:
:
:
:
:
B0 5-0
:
:
:
:
:
:
R1 5-0
:
:
:
:
:
:
G1 5-0
:
:
:
:
:
:
B15-0
:
:
:
:
:
:
--
-------------
ML=0
R94 5-0 G94 5-0 B94 5-0 R95 5-0 G95 5-0 B95
3
4
5
6
7
8
9
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
Display Pattern Data
1
94
0
1
2
:
:
:
:
:
:
--------0
95
5-0
:
:
:
:
:
:
10
11
:
:
:
:
:
:
60
61
62
63
64
65
66
67
94
1
Gate
ML=1 ML=0
67
66
65
64
63
62
61
60
59
58
57
56
:
:
:
:
:
:
7
6
5
4
3
2
1
0
G1
G2
G3
G4
G5
G6
G7
G8
G9
G10
G11
G12
:
:
:
:
:
:
G61
G62
G63
G64
G65
G66
G67
G68
ML=1
G68
G67
G66
G65
G64
G63
G62
G61
G60
G59
G58
G57
:
:
:
:
:
:
G8
G7
G6
G5
G4
G3
G2
G1
95
0
Note: RA = Row Address,
CA = Column Address,
SA = Scan Address,
MX = Mirror X-axis (Column address direction parameter), DB6 parameter of MADCTL command
MY = Mirror Y-axis (Row address direction parameter), DB7 parameter of MADCTL command
ML = Scan direction parameter, DB4 parameter of MADCTL command
RGB= Red, Green and Blue pixel position change, DB3 parameter of MADCTL command
Figure 6.10 Memory map, 96 x 68 GRAM resolution, display resolution 96RGB x 68
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.60Apr, 2010
HX8353-D
132RGB x 162 dots, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
6.3.7 When using 96 x 64 GRAM resolution, display resolution 96RGB x 64
(RSO[2:0]=3’b101)
Pixel1
Source Out
S55
S56
Pixel2
S57
S58
S59
Pixel95
S337
S60
S338
Pixel 96
S339
S340
S341
S342
RGB Order
RA
MY=0
MY=1
0
1
2
3
4
5
6
7
8
9
10
11
:
:
:
:
:
:
56
57
58
59
60
61
62
63
63
62
61
60
59
58
57
56
55
54
53
52
:
:
:
:
:
:
7
6
5
4
3
2
1
0
CA
MX=0
MX= 1
SA
:RGB=0
:RGB=1
R0 5-0
G0
:
:
:
:
:
:
5-0
:
:
:
:
:
:
B0 5-0
:
:
:
:
:
:
R1 5-0
:
:
:
:
:
:
G1 5-0
:
:
:
:
:
:
B15-0
:
:
:
:
:
:
--
-------------
ML=0
R94 5-0 G94 5-0 B94 5-0 R95 5-0 G95 5-0 B95
3
4
5
6
7
8
9
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
Display Pattern Data
1
94
0
1
2
:
:
:
:
:
:
--------0
95
5-0
94
1
:
:
:
:
:
:
10
11
:
:
:
:
:
:
56
57
58
59
60
61
62
63
Gate
ML=1 ML=0
63
62
61
60
G1
59
58
57
56
G5
G6
55
54
53
52
:
:
:
:
:
:
7
6
5
4
3
2
1
0
G2
G3
G4
G7
G8
G9
G10
G11
G12
:
:
:
:
:
:
G57
G58
G59
G60
G61
G62
G63
G64
ML=1
G64
G63
G62
G61
G60
G59
G58
G57
G56
G55
G54
G53
:
:
:
:
:
:
G8
G7
G6
G5
G4
G3
G2
G1
95
0
Note: RA = Row Address,
CA = Column Address,
SA = Scan Address,
MX = Mirror X-axis (Column address direction parameter), DB6 parameter of MADCTL command
MY = Mirror Y-axis (Row address direction parameter), DB7 parameter of MADCTL command
ML = Scan direction parameter, DB4 parameter of MADCTL command
RGB= Red, Green and Blue pixel position change, DB3 parameter of MADCTL command
Figure 6.11 Memory map, 96 x 64 GRAM resolution, display resolution 96RGB x 64
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.61Apr, 2010
HX8353-D
132RGB x 162 dots, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
6.3.8 Normal display on or partial display on
The HX8353-D has an internal GRAM that store 48,114 bytes pattern data, where one
pixel is expressed by 18 bits.
6.3.8.1 132X162 GRAM resolution (size) (display resolution 132RGB x 162
(RSO[2:0]=3’b000 & STE_SEL=0)
(a) Normal display on
In this mode, contents of the frame memory within an area where column pointer is
00h to 83h and page pointer is 00h to A1h is displayed. To display a dot on leftmost
top corner, store the dot data at (column pointer, row pointer) = (0, 0).
9C01H
9D01H
9E01H
9F01H
A001H
A101H
9C02H
9D02H
9E02H
9F02H
A002H
A102H
---------------------------------------------------------
80h
DB---DB
17 ---0
0080H
0180H
0280H
0380H
0480H
0580H
81h
DB---DB
17 ---0
0081H
0181H
0281H
0381H
0481H
0581H
82h
DB---DB
17 ---0
0082H
0182H
0282H
0382H
0482H
0582H
83h
DB---DB
17 ---0
0083H
0183H
0283H
0383H
0483H
0583H
---------
-------
-------
9C00H
9D00H
9E00H
9F00H
A000H
A100H
---------
-------
-------
03h
DB---DB
17 ---0
0003H
0103H
0203H
0303H
0403H
0503H
-------
-------
9Ch
9Dh
9Eh
9Fh
A0h
A1h
9C03H
9D03H
9E03H
9F03H
A003H
A103H
-------------------------------------------------
9C80H
9D80H
9E80H
9F80H
A080H
A180H
9C81H
9D81H
9E81H
9F81H
A081H
A181H
9C82H
9D82H
9E82H
9F82H
A082H
A182H
9C83H
9D83H
9E83H
9F83H
A083H
A183H
S396
S395
---------
S394
S3
S2
S1
LCD panel
S/G pins
02h
DB---DB
17 ---0
0002H
0102H
0202H
0302H
0402H
0502H
-------
-------
01h
DB---DB
17 ---0
0001H
0101H
0201H
0301H
0401H
0501H
-------
00h
01h
02h
03h
04h
05h
00h
DB---DB
17 ---0
0000H
0100H
0200H
0300H
0400H
0500H
GRAM
G1
G2
G3
G4
G5
G6
0000H
0100H
0200H
0300H
0400H
0500H
-------------------------------------------------
-------
-------
---------
-------
G157
G158
G159
G160
G161
G162
9C00H
9D00H
9E00H
9F00H
A000H
A100H
-------------------------------------------------
9C83H
9D83H
9E83H
9F83H
A083H
A183H
0083H
0183H
0283H
0383H
0483H
0583H
Table 6.5 132X162 GRAM resolution
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.62Apr, 2010
HX8353-D
132RGB x 162 dots, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
(b) Partial display on
PSL[15:0]=02h, PEL[15:0]=9Fh, ML=0.
---------------------------------------------------------
-------
---------
G1
G2
G3
G4
G5
G6
0000H
0100H
0200H
0300H
0400H
0500H
---------------------------------------------------------
-------
Non-display
area 2 lines
9C83H
9D83H
9E83H
9F83H
A083H
A183H
-------
Display area
158 lines
9C82H
9D82H
9E82H
9F82H
A082H
A182H
-------
Non-displa
y area 2
lines
9C81H
9D81H
9E81H
9F81H
A081H
A181H
S396
LCD panel
S/G pins
9C80H
9D80H
9E80H
9F80H
A080H
A180H
S395
-------------------------------------------------
83h
DB---DB
17 ---0
0083H
0183H
0283H
0383H
0483H
0583H
-------
9C03H
9D03H
9E03H
9F03H
A003H
A103H
82h
DB---DB
17 ---0
0082H
0182H
0282H
0382H
0482H
0582H
S394
9C02H
9D02H
9E02H
9F02H
A002H
A102H
81h
DB---DB
17 ---0
0081H
0181H
0281H
0381H
0481H
0581H
-------
9C01H
9D01H
9E01H
9F01H
A001H
A101H
80h
DB---DB
17 ---0
0080H
0180H
0280H
0380H
0480H
0580H
-------
9C00H
9D00H
9E00H
9F00H
A000H
A100H
S3
---------
S2
-------
------9Ch
9Dh
9Eh
9Fh
A0h
A1h
---------
S1
03h
DB---DB
17 ---0
0003H
0103H
0203H
0303H
0403H
0503H
-------
02h
DB---DB
17 ---0
0002H
0102H
0202H
0302H
0402H
0502H
-------
01h
DB---DB
17 ---0
0001H
0101H
0201H
0301H
0401H
0501H
-------
00h
01h
02h
03h
04h
05h
00h
DB---DB
17 ---0
0000H
0100H
0200H
0300H
0400H
0500H
GRAM
G157
G158
G159
G160
G161
G162
9C00H
9D00H
9E00H
9F00H
A000H
A100H
-------------------------------------------------
9C83H
9D83H
9E83H
9F83H
A083H
A183H
0083H
0183H
0283H
0383H
0483H
0583H
Table 6.6 Partial area of 132X162 GRAM resolution
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.63Apr, 2010
HX8353-D
132RGB x 162 dots, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
6.3.8.2 132X162 GRAM resolution (size) (display resolution 128RGB x 160
(RSO[2:0]=3’b000 & STE_SEL=1)
(a) Normal display on
In this mode, contents of the frame memory within an area where column pointer is
00h to 83h and page pointer is 00h to A1h is displayed. To display a dot on leftmost
top corner, store the dot data at (column pointer, row pointer) = (0, 0).
9C01H
9D01H
9E01H
9F01H
A001H
A101H
9C02H
9D02H
9E02H
9F02H
A002H
A102H
---------------------------------------------------------
80h
DB---DB
17 ---0
0080H
0180H
0280H
0380H
0480H
0580H
81h
DB---DB
17 ---0
0081H
0181H
0281H
0381H
0481H
0581H
82h
DB---DB
17 ---0
0082H
0182H
0282H
0382H
0482H
0582H
83h
DB---DB
17 ---0
0083H
0183H
0283H
0383H
0483H
0583H
---------
-------
-------
9C00H
9D00H
9E00H
9F00H
A000H
A100H
---------
-------
-------
03h
DB---DB
17 ---0
0003H
0103H
0203H
0303H
0403H
0503H
-------
-------
9Ch
9Dh
9Eh
9Fh
A0h
A1h
9C03H
9D03H
9E03H
9F03H
A003H
A103H
-------------------------------------------------
9C80H
9D80H
9E80H
9F80H
A080H
A180H
9C81H
9D81H
9E81H
9F81H
A081H
A181H
9C82H
9D82H
9E82H
9F82H
A082H
A182H
9C83H
9D83H
9E83H
9F83H
A083H
A183H
S390
S389
---------
S388
S9
S8
S7
LCD panel
S/G pins
02h
DB---DB
17 ---0
0002H
0102H
0202H
0302H
0402H
0502H
-------
-------
01h
DB---DB
17 ---0
0001H
0101H
0201H
0301H
0401H
0501H
-------
00h
01h
02h
03h
04h
05h
00h
DB---DB
17 ---0
0000H
0100H
0200H
0300H
0400H
0500H
GRAM
G2
G3
G4
G5
G6
G7
0000H
0100H
0200H
0300H
0400H
0500H
-------------------------------------------------
-------
-------
---------
-------
G158
G159
G160
G161
9C00H
9D00H
9E00H
9F00H
---------------------------------
9D81H
9E81H
9F81H
A081H
0181H
0281H
0381H
0481H
0581H
0681H
Table 6.7 132X162 GRAM resolution and 128X160 display resolution
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.64Apr, 2010
HX8353-D
132RGB x 162 dots, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
(b) Partial display on
PSL[15:0]=03h, PEL[15:0]=9Eh, ML=0.
---------------------------------------------------------
-------
---------
G2
G3
G4
G5
G6
G7
0102H
0202H
0302H
0402H
0502H
0602H
---------------------------------------------------------
-------
Non-display
area 2 lines
9C83H
9D83H
9E83H
9F83H
A083H
A183H
-------
Display area
156 lines
9C82H
9D82H
9E82H
9F82H
A082H
A182H
-------
Non-display
area 2 lines
9C81H
9D81H
9E81H
9F81H
A081H
A181H
S390
LCD panel
S/G pins
9C80H
9D80H
9E80H
9F80H
A080H
A180H
S389
-------------------------------------------------
83h
DB---DB
17 ---0
0083H
0183H
0283H
0383H
0483H
0583H
-------
9C03H
9D03H
9E03H
9F03H
A003H
A103H
82h
DB---DB
17 ---0
0082H
0182H
0282H
0382H
0482H
0582H
S388
9C02H
9D02H
9E02H
9F02H
A002H
A102H
81h
DB---DB
17 ---0
0081H
0181H
0281H
0381H
0481H
0581H
-------
9C01H
9D01H
9E01H
9F01H
A001H
A101H
80h
DB---DB
17 ---0
0080H
0180H
0280H
0380H
0480H
0580H
-------
9C00H
9D00H
9E00H
9F00H
A000H
A100H
S9
---------
S8
-------
------9Ch
9Dh
9Eh
9Fh
A0h
A1h
---------
S7
03h
DB---DB
17 ---0
0003H
0103H
0203H
0303H
0403H
0503H
-------
02h
DB---DB
17 ---0
0002H
0102H
0202H
0302H
0402H
0502H
-------
01h
DB---DB
17 ---0
0001H
0101H
0201H
0301H
0401H
0501H
-------
00h
01h
02h
03h
04h
05h
00h
DB---DB
17 ---0
0000H
0100H
0200H
0300H
0400H
0500H
GRAM
G158
G159
G160
G161
9D02H
9E02H
9F02H
A002H
---------------------------------
9D81H
9E81H
9F81H
A081H
0181H
0281H
0381H
0481H
0581H
0681H
Table 6.8 Partial area of 132X162 GRAM resolution and 128X160 display resolution
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.65Apr, 2010
HX8353-D
132RGB x 162 dots, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
6.3.8.3 128X128 GRAM resolution (size) (display resolution 128RGB x 128 RSO[2:0]=3’b001)
(a) Normal display on
In this mode, contents of the frame memory within an area where column pointer is
00h to 7Fh and page pointer is 00h to 7Fh is displayed. To display a dot on leftmost
top corner, store the dot data at (column pointer, row pointer) = (0, 0).
00h
01h
02h
03h
04h
05h
00h
DB---DB
17 ---0
0000H
0100H
0200H
0300H
0400H
0500H
01h
DB---DB
17 ---0
0001H
0101H
0201H
0301H
0401H
0501H
02h
DB---DB
17 ---0
0002H
0102H
0202H
0302H
0402H
0502H
03h
DB---DB
17 ---0
0003H
0103H
0203H
0303H
0403H
0503H
GRAM
---------
-------------------------------------------------
7Fh
DB---DB
17 ---0
007FH
017FH
027FH
037FH
047FH
057FH
---------
-----------------------------------------------------------------
81h
DB---DB
17 ---0
0081H
0181H
0281H
0381H
0481H
0581H
82h
DB---DB
17 ---0
0082H
0182H
0282H
0382H
0482H
0582H
83h
DB---DB
17 ---0
0083H
0183H
0283H
0383H
0483H
0583H
-------
-------
-------
7E00H
7F00H
7E01H
7F01H
7E02H
7F02H
7E03H
7F03H
-----------------
7E7FH
7E7FH
-----------------
-------
-------
-------
-------
-------
---------
-------
---------
-------
-------
-------
9Ch
9Dh
9Eh
9Fh
A0h
A1h
9C00H
9D00H
9E00H
9F00H
A000H
A100H
9C01H
9D01H
9E01H
9F01H
A001H
A101H
9C02H
9D02H
9E02H
9F02H
A002H
A102H
9C03H
9D03H
9E03H
9F03H
A003H
A103H
-------------------------------------------------
9C7FH
9D7FH
9E7FH
9F7FH
A07FH
A17FH
-------------------------------------------------
9C81H
9D81H
9E81H
9F81H
A081H
A181H
9C82H
9D82H
9E82H
9F82H
A082H
A182H
9C83H
9D83H
9E83H
9F83H
A083H
A183H
7E82H
7F82H
7E83H
7F83H
S390
S389
---------
7E81H
7F81H
S388
S9
S8
S7
LCD panel
S/G pins
-------
-------
7Eh
7Fh
-------
-------
---------
-------
-------
---------
G2
G3
G4
G5
G6
G7
0000H
0100H
0200H
0300H
0400H
0500H
-------------------------------------------------
-------
-------
---------
-------
G126
G127
G128
G129
7C00H
7D00H
7E00H
7F00H
---------------------------------
7C7FH
7D7FH
7E7FH
7F7FH
007FH
017FH
027FH
037FH
047FH
057FH
Table 6.9 128X128 GRAM resolution
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.66Apr, 2010
HX8353-D
132RGB x 162 dots, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
(b) Partial display on
PSL[15:0]=02h, PEL[15:0]=7Dh, ML=0.
00h
01h
02h
03h
04h
05h
00h
DB---DB
17 ---0
0000H
0100H
0200H
0300H
0400H
0500H
01h
DB---DB
17 ---0
0001H
0101H
0201H
0301H
0401H
0501H
02h
DB---DB
17 ---0
0002H
0102H
0202H
0302H
0402H
0502H
03h
DB---DB
17 ---0
0003H
0103H
0203H
0303H
0403H
0503H
GRAM
---------
-------------------------------------------------
7Fh
DB---DB
17 ---0
007FH
017FH
027FH
037FH
047FH
057FH
---------
-----------------------------------------------------------------
81h
DB---DB
17 ---0
0081H
0181H
0281H
0381H
0481H
0581H
82h
DB---DB
17 ---0
0082H
0182H
0282H
0382H
0482H
0582H
83h
DB---DB
17 ---0
0083H
0183H
0283H
0383H
0483H
0583H
-------
-------
-------
7E00H
7F00H
7E01H
7F01H
7E02H
7F02H
7E03H
7F03H
-----------------
7E7FH
7E7FH
-----------------
-------
-------
-------
-------
-------
---------
-------
---------
-------
-------
-------
9Ch
9Dh
9Eh
9Fh
A0h
A1h
9C00H
9D00H
9E00H
9F00H
A000H
A100H
9C01H
9D01H
9E01H
9F01H
A001H
A101H
9C02H
9D02H
9E02H
9F02H
A002H
A102H
9C03H
9D03H
9E03H
9F03H
A003H
A103H
-------------------------------------------------
9C7FH
9D7FH
9E7FH
9F7FH
A07FH
A17FH
-------------------------------------------------
9C81H
9D81H
9E81H
9F81H
A081H
A181H
9C82H
9D82H
9E82H
9F82H
A082H
A182H
9C83H
9D83H
9E83H
9F83H
A083H
A183H
7E82H
7F82H
7E83H
7F83H
S390
S389
S387
S9
G2
G3
G4
G5
G6
G7
0000H
0100H
0200H
0300H
0400H
0500H
-------------------------------------------------
-------
---------
-------
Non-display
area 2 lines
S8
Display area
124 lines
---------
7E81H
7F81H
-------
Non-display
area 2 lines
S7
LCD panel
S/G pins
-------
-------
7Eh
7Fh
-------
-------
---------
-------
-------
---------
G126
G127
G128
G129
7C00H
7D00H
7E00H
7F00H
---------------------------------
7C7FH
7D7FH
7E7FH
7F7FH
007FH
017FH
027FH
037FH
047FH
057FH
Table 6.10 Partial area of 128X128 GRAM resolution
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.67Apr, 2010
HX8353-D
132RGB x 162 dots, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
6.3.8.4 120X160 GRAM resolution (size) (display resolution 120RGB x 160 RSO[2:0]=3’b010)
(a) Normal display on
In this mode, contents of the frame memory within an area where column pointer is
00h to 77h and page pointer is 00h to 9Fh is displayed. To display a dot on leftmost
top corner, store the dot data at (column pointer, row pointer) = (0, 0).
-------
-------
-------
---------
9C00H
9D00H
9E00H
9F00H
A000H
A100H
9C01H
9D01H
9E01H
9F01H
A001H
A101H
9C02H
9D02H
9E02H
9F02H
A002H
A102H
9C03H
9D03H
9E03H
9F03H
A003H
A103H
-------------------------------------------------
---------
-----------------------------------------------------------------
81h
DB---DB
17 ---0
0081H
0181H
0281H
0381H
0481H
0581H
82h
DB---DB
17 ---0
0082H
0182H
0282H
0382H
0482H
0582H
83h
DB---DB
17 ---0
0083H
0183H
0283H
0383H
0483H
0583H
---------
-------
------9Ch
9Dh
9Eh
9Fh
A0h
A1h
---------
-------
03h
DB---DB
17 ---0
0003H
0103H
0203H
0303H
0403H
0503H
-------
02h
DB---DB
17 ---0
0002H
0102H
0202H
0302H
0402H
0502H
-------
01h
DB---DB
17 ---0
0001H
0101H
0201H
0301H
0401H
0501H
9C77H
9D77H
9E77H
9F77H
A077H
A177H
-------------------------------------------------
9C81H
9D81H
9E81H
9F81H
A081H
A181H
9C82H
9D82H
9E82H
9F82H
A082H
A182H
9C83H
9D83H
9E83H
9F83H
A083H
A183H
S366
S365
---------
S364
S9
S8
S7
LCD panel
S/G pins
-------------------------------------------------
77h
DB---DB
17 ---0
0077H
0177H
0277H
0377H
0477H
0577H
-------
00h
01h
02h
03h
04h
05h
00h
DB---DB
17 ---0
0000H
0100H
0200H
0300H
0400H
0500H
GRAM
G2
G3
G4
G5
G6
G7
0000H
0100H
0200H
0300H
0400H
0500H
-------------------------------------------------
-------
-------
---------
-------
G158
G159
G160
G161
9C00H
9D00H
9E00H
9F00H
---------------------------------
9C77H
9D77H
9E77H
9F77H
0077H
0177H
0277H
0377H
0477H
0577H
Table 6.11 120X160 GRAM resolution
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.68Apr, 2010
HX8353-D
132RGB x 162 dots, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
(b) Partial display on
PSL[15:0]=02h, PEL[15:0]=9Dh, ML=0.
-------
-------
-------
9C00H
9D00H
9E00H
9F00H
A000H
A100H
9C01H
9D01H
9E01H
9F01H
A001H
A101H
9C02H
9D02H
9E02H
9F02H
A002H
A102H
-------------------------------------------------
-------------------------------------------------
82h
DB---DB
17 ---0
0082H
0182H
0282H
0382H
0482H
0582H
83h
DB---DB
17 ---0
0083H
0183H
0283H
0383H
0483H
0583H
---------
9C77H
9D77H
9E77H
9F77H
A077H
A177H
-------------------------------------------------
9C81H
9D81H
9E81H
9F81H
A081H
A181H
9C82H
9D82H
9E82H
9F82H
A082H
A182H
9C83H
9D83H
9E83H
9F83H
A083H
A183H
S366
S365
---------
S364
S9
S8
G2
G3
G4
G5
G6
G7
0000H
0100H
0200H
0300H
0400H
0500H
-------------------------------------------------
-------
---------
-------
Non-display
area 2 lines
S7
Display area
156 lines
9C03H
9D03H
9E03H
9F03H
A003H
A103H
---------
81h
DB---DB
17 ---0
0081H
0181H
0281H
0381H
0481H
0581H
-------
Non-display
area 2 lines
---------
---------
---------
-------
------9Ch
9Dh
9Eh
9Fh
A0h
A1h
---------
-------
03h
DB---DB
17 ---0
0003H
0103H
0203H
0303H
0403H
0503H
-------
02h
DB---DB
17 ---0
0002H
0102H
0202H
0302H
0402H
0502H
-------
01h
DB---DB
17 ---0
0001H
0101H
0201H
0301H
0401H
0501H
LCD panel
S/G pins
-------------------------------------------------
77h
DB---DB
17 ---0
0077H
0177H
0277H
0377H
0477H
0577H
-------
00h
01h
02h
03h
04h
05h
00h
DB---DB
17 ---0
0000H
0100H
0200H
0300H
0400H
0500H
GRAM
G158
G159
G160
G161
9C00H
9D00H
9E00H
9F00H
---------------------------------
9C77H
9D77H
9E77H
9F77H
0077H
0177H
0277H
0377H
0477H
0577H
Table 6.12 Partial area of 120X160 GRAM resolution
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.69Apr, 2010
HX8353-D
132RGB x 162 dots, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
6.3.8.5 128X160 GRAM resolution (size) (display resolution 128RGB x 160
(RSO[2:0]=3’b011)
(a) Normal display on
In this mode, contents of the frame memory within an area where column pointer is
00h to 7Fh and page pointer is 00h to 9Fh is displayed. To display a dot on leftmost
top corner, store the dot data at (column pointer, row pointer) = (0, 0).
-------
-------
9C01H
9D01H
9E01H
9F01H
A001H
A101H
9C02H
9D02H
9E02H
9F02H
A002H
A102H
81h
DB---DB
17 ---0
0081H
0181H
0281H
0381H
0481H
0581H
82h
DB---DB
17 ---0
0082H
0182H
0282H
0382H
0482H
0582H
83h
DB---DB
17 ---0
0083H
0183H
0283H
0383H
0483H
0583H
---------
9C03H
9D03H
9E03H
9F03H
A003H
A103H
-------------------------------------------------
9C7FH
9D7FH
9E7FH
9F7FH
A07FH
A17FH
9C80H
9D80H
9E80H
9F80H
A080H
A180H
9C81H
9D81H
9E81H
9F81H
A081H
A181H
9C82H
9D82H
9E82H
9F82H
A082H
A182H
9C83H
9D83H
9E83H
9F83H
A083H
A183H
S390
S389
---------
S388
S9
S8
S7
LCD panel
S/G pins
80h
DB---DB
17 ---0
0080H
0180H
0280H
0380H
0480H
0580H
-------
------9C00H
9D00H
9E00H
9F00H
A000H
A100H
---------------------------------------------------------
7Fh
DB---DB
17 ---0
007FH
017FH
027FH
037FH
047FH
057FH
-------
------9Ch
9Dh
9Eh
9Fh
A0h
A1h
---------
-------
03h
DB---DB
17 ---0
0003H
0103H
0203H
0303H
0403H
0503H
-------
02h
DB---DB
17 ---0
0002H
0102H
0202H
0302H
0402H
0502H
-------
01h
DB---DB
17 ---0
0001H
0101H
0201H
0301H
0401H
0501H
-------
00h
01h
02h
03h
04h
05h
00h
DB---DB
17 ---0
0000H
0100H
0200H
0300H
0400H
0500H
GRAM
G2
G3
G4
G5
G6
G7
0000H
0100H
0200H
0300H
0400H
0500H
-------------------------------------------------
-------
-------
---------
-------
G158
G159
G160
G161
9C00H
9D00H
9E00H
9F00H
---------------------------------
9C7FH
9D7FH
9E7FH
9F7FH
007FH
017FH
027FH
037FH
047FH
057FH
Table 6.13 128X160 GRAM resolution
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.70Apr, 2010
HX8353-D
132RGB x 162 dots, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
(b) Partial display on
PSL[15:0]=02h, PEL[15:0]=9Dh, ML=0.
-------
-------
9C01H
9D01H
9E01H
9F01H
A001H
A101H
9C02H
9D02H
9E02H
9F02H
A002H
A102H
83h
DB---DB
17 ---0
0083H
0183H
0283H
0383H
0483H
0583H
9C03H
9D03H
9E03H
9F03H
A003H
A103H
-------------------------------------------------
9C7FH
9D7FH
9E7FH
9F7FH
A07FH
A17FH
9C80H
9D80H
9E80H
9F80H
A080H
A180H
9C81H
9D81H
9E81H
9F81H
A081H
A181H
9C82H
9D82H
9E82H
9F82H
A082H
A182H
9C83H
9D83H
9E83H
9F83H
A083H
A183H
S390
S389
---------
S388
S9
G2
G3
G4
G5
G6
G7
0000H
0100H
0200H
0300H
0400H
0500H
-------------------------------------------------
-------
---------
-------
Non-displa
y area 2
lines
82h
DB---DB
17 ---0
0082H
0182H
0282H
0382H
0482H
0582H
---------
S8
Display area
156 lines
81h
DB---DB
17 ---0
0081H
0181H
0281H
0381H
0481H
0581H
-------
Non-display
area 2 lines
S7
LCD panel
S/G pins
80h
DB---DB
17 ---0
0080H
0180H
0280H
0380H
0480H
0580H
-------
------9C00H
9D00H
9E00H
9F00H
A000H
A100H
---------------------------------------------------------
7Fh
DB---DB
17 ---0
007FH
017FH
027FH
037FH
047FH
057FH
-------
------9Ch
9Dh
9Eh
9Fh
A0h
A1h
---------
-------
03h
DB---DB
17 ---0
0003H
0103H
0203H
0303H
0403H
0503H
-------
02h
DB---DB
17 ---0
0002H
0102H
0202H
0302H
0402H
0502H
-------
01h
DB---DB
17 ---0
0001H
0101H
0201H
0301H
0401H
0501H
-------
00h
01h
02h
03h
04h
05h
00h
DB---DB
17 ---0
0000H
0100H
0200H
0300H
0400H
0500H
GRAM
G158
G159
G160
G161
9C00H
9D00H
9E00H
9F00H
---------------------------------
9C7FH
9D7FH
9E7FH
9F7FH
007FH
017FH
027FH
037FH
047FH
057FH
Table 6.14 Partial area of 128X160 GRAM resolution
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.71Apr, 2010
HX8353-D
132RGB x 162 dots, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
6.3.8.6 96x68 Resolution (RSO[2:0]=3’b100)
(a) Normal display on
In this mode, contents of the frame memory within an area where column pointer is
00h to 5Fh and page pointer is 00h to 43h is displayed. To display a dot on leftmost
top corner, store the dot data at (column pointer, row pointer) = (0, 0).
00h
01h
02h
03h
GRAM DB---DB DB---DB DB---DB DB---DB
17 ---0 17 ---0 17 ---0 17 ---0
0000H
0001H
0002H
0003H
00h
0100H
0101H
0102H
0103H
01h
0200H
0201H
0202H
0203H
02h
0300H
0301H
0302H
0303H
03h
0400H
0401H
0402H
0403H
04h
0500H
0501H
0502H
0503H
05h
-----------
9C5FH
9D5FH
9E5FH
9F5FH
A05FH
A15FH
-------------------------------------------------
4181H
4281H
4381H
4182H
4282H
4382H
4183H
4283H
4383H
---
9C80H
9D80H
9E80H
9F80H
A080H
A180H
9C81H
9D81H
9E81H
9F81H
A081H
A181H
9C82H
9D82H
9E82H
9F82H
A082H
A182H
9C83H
9D83H
9E83H
9F83H
A083H
A183H
---
-------------
S342
0500H
---
S341
0000H
0100H
0200H
0300H
0400H
---
S340
S57
S56
G1
G2
G3
G4
G5
G6
9C5EH
9D5EH
9E5EH
9F5EH
A05EH
A15EH
S55
LCD panel
S/G pins
9C5DH
9D5DH
9E5DH
9F5DH
A05DH
A15DH
4180H
4280H
4380H
---
-------
---
415FH
425FH
435FH
---
0083H
0183H
0283H
0383H
0483H
0583H
-------
---
415EH
425EH
435EH
---
0082H
0182H
0282H
0382H
0482H
0582H
-------
---
415DH
425DH
435DH
---
0081H
0181H
0281H
0381H
0481H
0581H
-------
---
---
0080H
0180H
0280H
0380H
0480H
0580H
-------
------9C03H
9D03H
9E03H
9F03H
A003H
A103H
---
---
-------
------9C02H
9D02H
9E02H
9F02H
A002H
A102H
---
---
80h
81h
82h
83h
DB---DB DB---DB DB---DB DB---DB
17 ---0
17 ---0
17 ---0
17 ---0
-------
------9C01H
9D01H
9E01H
9F01H
A001H
A101H
---
005FH
015FH
025FH
035FH
045FH
055FH
---
-------
------9C00H
9D00H
9E00H
9F00H
A000H
A100H
---
005EH
015EH
025EH
035EH
045EH
055EH
-------
------9Ch
9Dh
9Eh
9Fh
A0h
A1h
---
005DH
015DH
025DH
035DH
045DH
055DH
-------
------4103H
4103H
4303H
---
---
-------
------4102H
4102H
4302H
---
5Fh
DB---DB
17 ---0
-------
------4101H
4201H
4301H
---
5Eh
DB---DB
17 ---0
-------
------4100H
4200H
4300H
---
5Dh
DB---DB
17 ---0
-------
------41h
42h
43h
---
005FH
015FH
025FH
035FH
045FH
055FH
-------
-------
-------
-------
G67
G68
4200H
4300H
-----------------
425FH
435FH
Table 6.15 96X68 GRAM resolution
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.72Apr, 2010
HX8353-D
132RGB x 162 dots, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
(b) Partial display on
PSL[15:0]=02, PEL[15:0]=41, ML=0.
00h
01h
02h
03h
GRAM DB---DB DB---DB DB---DB DB---DB
17 ---0
17 ---0
17 ---0
17 ---0
0000H
0001H
0002H
0003H
00h
0100H
0101H
0102H
0103H
01h
0200H
0201H
0202H
0203H
02h
0300H
0301H
0302H
0303H
03h
0400H
0401H
0402H
0403H
04h
0500H
0501H
0502H
0503H
05h
---
---
---------
9C5DH
9D5DH
9E5DH
9F5DH
A05DH
A15DH
9C5EH
9D5EH
9E5EH
9F5EH
A05EH
A15EH
9C5FH
9D5FH
9E5FH
9F5FH
A05FH
A15FH
-------
---
-------------
4180H
4280H
4380H
4181H
4281H
4381H
4182H
4282H
4382H
4183H
4283H
4383H
9C80H
9D80H
9E80H
9F80H
A080H
A180H
9C81H
9D81H
9E81H
9F81H
A081H
A181H
9C82H
9D82H
9E82H
9F82H
A082H
A182H
9C83H
9D83H
9E83H
9F83H
A083H
A183H
S342
0500H
-------------------------------------------------
---
S341
S340
S57
0000H
0100H
0200H
0300H
0400H
---
0083H
0183H
0283H
0383H
0483H
0583H
-------
---
415FH
425FH
435FH
S56
G1
G2
G3
G4
G5
G6
---
415EH
425EH
435EH
---
0082H
0182H
0282H
0382H
0482H
0582H
-------
---
415DH
425DH
435DH
---
0081H
0181H
0281H
0381H
0481H
0581H
-------
---
---
0080H
0180H
0280H
0380H
0480H
0580H
-------
---
S55
005FH
015FH
025FH
035FH
045FH
055FH
-------
-------
-------
Non-display
area 2 lines
---
-------
Display area
64 lines
---
---
LCD panel
S/G pins
Non-display
area 2 lines
---
---
-------
------9C03H
9D03H
9E03H
9F03H
A003H
A103H
---
81h
82h
83h
DB---DB DB---DB DB---DB
17 ---0
17 ---0
17 ---0
-------
------9C02H
9D02H
9E02H
9F02H
A002H
A102H
005FH
015FH
025FH
035FH
045FH
055FH
80h
DB---DB
17 ---0
-------
------9C01H
9D01H
9E01H
9F01H
A001H
A101H
005EH
015EH
025EH
035EH
045EH
055EH
---
---
-------
------9C00H
9D00H
9E00H
9F00H
A000H
A100H
005DH
015DH
025DH
035DH
045DH
055DH
---
-------
------9Ch
9Dh
9Eh
9Fh
A0h
A1h
---
-------
------4103H
4203H
4303H
5Fh
DB---DB
17 ---0
-------
------4102H
4202H
4302H
5Eh
DB---DB
17 ---0
-------
------4101H
4201H
4301H
5Dh
DB---DB
17 ---0
-------
------4100H
4200H
4300H
---
-------
------41h
42h
43h
---
G66
G67
G68
4100H
4200H
4300H
-------------------------
415FH
425FH
435FH
Table 6.16 Partial area of 96X68 GRAM resolution
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.73Apr, 2010
HX8353-D
132RGB x 162 dots, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
6.3.8.7 96x64 resolution (RSO[2:0]=3’b101)
(a) Normal display on
In this mode, contents of the frame memory within an area where column pointer is
00h to 5Fh and page pointer is 00h to 43h is displayed. To display a dot on leftmost
top corner, store the dot data at (column pointer, row pointer) = (0, 0).
00h
01h
02h
03h
GRAM DB---DB DB---DB DB---DB DB---DB
17 ---0 17 ---0 17 ---0 17 ---0
0000H
0001H
0002H
0003H
00h
0100H
0101H
0102H
0103H
01h
0200H
0201H
0202H
0203H
02h
0300H
0301H
0302H
0303H
03h
0400H
0401H
0402H
0403H
04h
0500H
0501H
0502H
0503H
05h
-----------
9C5FH
9D5FH
9E5FH
9F5FH
A05FH
A15FH
-------------------------------------------------
3F81H
4081H
4181H
3F82H
4082H
4182H
3F83H
4083H
4183H
---
9C80H
9D80H
9E80H
9F80H
A080H
A180H
9C81H
9D81H
9E81H
9F81H
A081H
A181H
9C82H
9D82H
9E82H
9F82H
A082H
A182H
9C83H
9D83H
9E83H
9F83H
A083H
A183H
---
-------------
S342
0500H
---
S341
0000H
0100H
0200H
0300H
0400H
---
S340
S57
S56
G1
G2
G3
G4
G5
G6
9C5EH
9D5EH
9E5EH
9F5EH
A05EH
A15EH
S55
LCD panel
S/G pins
9C5DH
9D5DH
9E5DH
9F5DH
A05DH
A15DH
3F80H
4080H
4180H
---
-------
---
3F5FH
405FH
415FH
---
0083H
0183H
0283H
0383H
0483H
0583H
-------
---
3F5EH
405EH
415EH
---
0082H
0182H
0282H
0382H
0482H
0582H
-------
---
3F5DH
405DH
415DH
---
0081H
0181H
0281H
0381H
0481H
0581H
-------
---
---
0080H
0180H
0280H
0380H
0480H
0580H
-------
------9C03H
9D03H
9E03H
9F03H
A003H
A103H
---
---
-------
------9C02H
9D02H
9E02H
9F02H
A002H
A102H
---
---
80h
81h
82h
83h
DB---DB DB---DB DB---DB DB---DB
17 ---0
17 ---0
17 ---0
17 ---0
-------
------9C01H
9D01H
9E01H
9F01H
A001H
A101H
---
005FH
015FH
025FH
035FH
045FH
055FH
---
-------
------9C00H
9D00H
9E00H
9F00H
A000H
A100H
---
005EH
015EH
025EH
035EH
045EH
055EH
-------
------9Ch
9Dh
9Eh
9Fh
A0h
A1h
---
005DH
015DH
025DH
035DH
045DH
055DH
-------
------3F03H
4003H
4103H
---
---
-------
------3F02H
4002H
4102H
---
5Fh
DB---DB
17 ---0
-------
------3F01H
4001H
4101H
---
5Eh
DB---DB
17 ---0
-------
------3F00H
4000H
4100H
---
5Dh
DB---DB
17 ---0
-------
------3Fh
40h
41h
---
005FH
015FH
025FH
035FH
045FH
055FH
-------
-------
-------
-------
G63
G64
3E00H
3F00H
-----------------
3E5FH
3F5FH
Table 6.17 96X64 GRAM resolution
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.74Apr, 2010
HX8353-D
132RGB x 162 dots, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
(b) Partial display on
PSL[15:0]=02, PEL[15:0]=3D, ML=0.
00h
01h
02h
03h
GRAM DB---DB DB---DB DB---DB DB---DB
17 ---0 17 ---0 17 ---0 17 ---0
0000H
0001H
0002H
0003H
00h
0100H
0101H
0102H
0103H
01h
0200H
0201H
0202H
0203H
02h
0300H
0301H
0302H
0303H
03h
0400H
0401H
0402H
0403H
04h
0500H
0501H
0502H
0503H
05h
-----------
-----
3F82H
4082H
4182H
3F83H
4083H
4183H
-----
9C80H
9D80H
9E80H
9F80H
A080H
A180H
9C81H
9D81H
9E81H
9F81H
A081H
A181H
9C82H
9D82H
9E82H
9F82H
A082H
A182H
9C83H
9D83H
9E83H
9F83H
A083H
A183H
---------
S342
-------------------------------------------------
3F81H
4081H
4181H
---
S341
0500H
---
S340
S57
005FH
015FH
025FH
035FH
045FH
055FH
-------
-------
-------
Non-display
area 2 lines
0000H
0100H
0200H
0300H
0400H
3F80H
4080H
4180H
---
-------
Display area
60 lines
G1
G2
G3
G4
G5
G6
9C5FH
9D5FH
9E5FH
9F5FH
A05FH
A15FH
S56
Non-display
area 2 lines
9C5EH
9D5EH
9E5EH
9F5EH
A05EH
A15EH
S55
LCD panel
S/G pins
9C5DH
9D5DH
9E5DH
9F5DH
A05DH
A15DH
---
0083H
0183H
0283H
0383H
0483H
0583H
-------
---
3F5FH
405FH
415FH
---
0082H
0182H
0282H
0382H
0482H
0582H
-------
---
3F5EH
405EH
415EH
---
0081H
0181H
0281H
0381H
0481H
0581H
-------
---
3F5DH
405DH
415DH
---
0080H
0180H
0280H
0380H
0480H
0580H
-------
---
---
-------
------9C03H
9D03H
9E03H
9F03H
A003H
A103H
---
---
-------
------9C02H
9D02H
9E02H
9F02H
A002H
A102H
---
005FH
015FH
025FH
035FH
045FH
055FH
80h
81h
82h
83h
DB---DB DB---DB DB---DB DB---DB
17 ---0
17 ---0
17 ---0
17 ---0
-------
------9C01H
9D01H
9E01H
9F01H
A001H
A101H
---
005EH
015EH
025EH
035EH
045EH
055EH
---
-------
------9C00H
9D00H
9E00H
9F00H
A000H
A100H
---
005DH
015DH
025DH
035DH
045DH
055DH
-------
------9Ch
9Dh
9Eh
9Fh
A0h
A1h
---
---
-------
------3F03H
4003H
4103H
---
5Fh
DB---DB
17 ---0
-------
------3F02H
4002H
4102H
---
5Eh
DB---DB
17 ---0
-------
------3F01H
4001H
4101H
---
5Dh
DB---DB
17 ---0
-------
------3F00H
4000H
4100H
---
-------
------3Fh
40h
41h
---
G63
G64
3E00H
3F00H
-----------------
3E5FH
3F5FH
Table 6.18 Partial area of 96X64 GRAM resolution
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.75Apr, 2010
HX8353-D
132RGB x 162 dots, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
6.4 Vertical scrolling display
The vertical scrolling display is specified by SCRLAR instruction (R33h) and VSCSAD
instruction (R37h). The Vertical scrolling is only enable when using 132 x 162 GRAM
resolution, display resolution 132RGB x 162
(RSO[2:0]=3’b000 & STE_SEL=0) and display resolution 128RGB x 160
(RSO[2:0]=3’b011)
Original
Scrolling
TFA
VSA
BFA
Figure 6.12 Vertical scrolling display
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.76Apr, 2010
HX8353-D
132RGB x 162 dots, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
When RSO[2:0]=3’b000(132RGB x 162) and Vertical Scrolling Definition Parameters
(TFA+VSA+BFA)=162 (other setting is prohibited). In this case, scrolling is applied as
shown below.
Example 1: RSO=3’b000(132RGB x 162), TFA =3, VSA=157, BFA=2, VSP=4,
MADCTR(ML)=0: Scrolling
TFA
01
02
03
04
01h
01h
10
11
12
13
14
02h
02h
20
21
22
23
32
03h
03h
30
31
04h
04h
40
41
05h
05h
50
0V 0W 0X 0Y 0Z
1st
0
G1
00
01
02
03
04
1W 1X 1Y 1Z
2nd
1
G2
10
11
12
13
14
2X 2Y 2Z
3nd
2
G3
20
21
22
23
42
3Y 3Z
160th
160th
3
G4
40
41
4Y 4Z
4th
4
G5
50
51
5Z
5th
5
G6
60
VSP
05
0V 0W 0X 0Y 0Z
1W 1X 1Y 1Z
5Y 5Z
6Z
132 x 162 LCD Panel
UZ 156th
156th 156
9Ch
U0
G157
V0 V1
VY VZ
9Dh
V0 V1
VY VZ 157th
157th 157
G158
W0 W1
WY WZ
9Eh
W0 W1
WY WZ 158th
158th
158
G159
X0 X1 X2
9Fh
X0 X1 X2
XX XY XZ 159th
159th 159
G160
30
A0h
Y0 Y1 Y2 Y3
A1h
Z0 Z1 Z2 Z3 Z4 Z5
31
TFA
2X 2Y 2Z
4X 4Y 4Z
132 x 162 x 18 bit
Frame memory
VSA
BFA
80h
80h 81h
81h 82h
82h 83h
83h
05
XX XY XZ
32
3X 3Y 3Z
YW YX YY YZ 161th
161th
160
G161
Y0 Y1 Y2 Y3
ZV ZW ZX ZY ZZ 162th
162th
161
G162
Z0 Z1 Z2 Z3 Z4 Z5
YW YX YY YZ
ZV ZW ZX ZY ZZ
Scroll area = 157 lines
00
S1
00h
00h 01h
01h 02h
02h 03h
03h 04h
04h
00h
00h
S396
Scan order
BFA
Scan Address
Figure 6.13 Example1 of scrolling
Example 2: RSO=3’b000(132RGB x 162), TFA =3, VSA=157, BFA=2, VSP=4,
MADCTR (ML)=1: Scrolling (TFA and BFA are exchanged)
BFA
01
02
03
04
01h
01h
10
11
12
13
14
02h
02h
20
21
22
23
03h
03h
30
31
32
04h
04h
40
41
05h
05h
50
VSA
TFA
80h
80h 81h
81h 82h
82h 83h
83h
05
0V 0W 0X 0Y 0Z 162th
162th
0
G1
00
01
02
03
04
1W 1X 1Y 1Z 161th
161th
1
G2
10
11
12
13
14
2X 2Y 2Z 159th
159th
2
G3
W0 W1
3Y 3Z 158th
158th
3
G4
20 21
22
23
4Y 4Z 157th
157th
4
G5
30
31
32
5Z 156th
156th
5
G6
40
41
U0
9Dh
V0 V1
9Eh
W0 W1
9Fh
X0 X1 X2
A0h
Y0 Y1 Y2 Y3
A1h
Z0
Z1
Z3
Z4
Z5
1W 1X 1Y 1Z
2X 2Y 2Z
3X 3Y 3Z
4Y 4Z
132 x 162 LCD Panel
UZ
5th
156
VY VZ
4th
157
G157 T0
VSP
WY WZ 160th
160th 158
Z2
0V 0W 0X 0Y 0Z
WY WZ
132 x 162 x 18 bit
Frame memory
9Ch
05
XX XY XZ
3nd
159
YW YX YY YZ
2nd
160
1st
161
ZV ZW ZX
ZY
ZZ
G158 U0 U1
G159 V0 V1
G160 X0 X1 X2
G161 Y0 Y1 Y2 Y3
G162 Z0 Z1 Z2 Z3 Z4 Z5
TZ
UY UZ
VY VZ
BFA
Scroll area = 157 lines
00
S1
00h
00h 01h
01h 02h
02h 03h
03h 04h
04h
00h
00h
S396
Scan order
XX XY XZ
YW YX YY YZ
TFA
ZV ZW ZX ZY ZZ
Scan Address
Figure 6.14 Example2 of scrolling
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.77Apr, 2010
HX8353-D
132RGB x 162 dots, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
7. Functional Description
7.1 Internal Oscillator
The HX8353-D can oscillate an internal R-C oscillator for internal operation. Because
the tolerance of internal oscillator frequency is ±5%, it can be adjusted by the RADJ
[1:0] bits for initial 1.46MHz internal clock generation. With other dividers setting, the
1.46MHz internal clock can be used to generate clock for other part of the chip using.
Figure 7.1 HX8353-D internal clock circuit
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.78Apr, 2010
HX8353-D
132RGB x 162 dots, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
7.2 Gamma characteristic correction function
The HX8353-D incorporates gamma adjustment function for the 262,144-color display
(64 grayscale for each R, G, B color). Gamma adjustment operation is implemented
by deciding the 8 grayscale levels firstly in gamma adjustment control registers to
match the LCD panel. These registers are available for both polarities.
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.79Apr, 2010
HX8353-D
132RGB x 162 dots, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
Graphics
RAM
( GRAM)
RRRRRR GGGGGG BB B B BB
5 4 32 1 0 5 43 2 1 0 54 3 2 1 0
OP03 OP02 OP01 OP00
OP14 OP13 OP12 OP11 OP10
CP03 CP02 CP01 CP00
CP13 CP12 CP11 CP10
6
6
6
6-bit Grayscale
6- bit Grayscale
6- bit Grayscale
D/ A Converter
D/ A Converter
D/ A Converter
V0
V1
Grayscale
Voltage
Output Driver Output Driver
R
G
Output Driver
V63
CP23 CP22 CP21 CP20
CP33 CP32 CP31 CP30
CP43 CP42 CP41 CP40
MP02 MP01 MP00
MP MP11 MP10
Positive 12
polarity MP22 MP21 MP20
Register MP32 MP31 MP30
MP42 MP41 MP40
MP52 MP51 MP50
Generator
B
LCD
ON03ON02 ON01ON00
ON14 ON13 ON12 ON11 ON10
CN03 CN02 CN01CN00
CN03 CN12 CN11CN10
CN23 CN22 CN21CN20
CN33 CN32 CN31CN30
CN43 CN42 CN41 CN40
MN02 MN01MN00
Negative
polarity MN12 MN11MN10
Registre MN22MN21MN20
MN32MN31MN30
MN42 MN41MN40
MN52 MN51MN50
Figure 7.2 Grayscale control
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.80Apr, 2010
HX8353-D
132RGB x 162 dots, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
7.2.1 Structure of grayscale voltage generator
Eight reference gamma voltages VgP/N(0, 1, 8, 20, 43, 55, 62, 63) for positive and
negative polarity are specified by the center adjustment, the micro adjustment and the
offset adjustment registers firstly. With those eight voltage injected into specified node
of grayscale voltage generator, totally 64 grayscale voltages (V0-V63) can be
generated from grayscale amplifier for LCD panel.
Micro Adjust Register ( 6x3 bits)
VREG1
MP/N5 MP/N4 MP/N3 MP/N2
3
3
3
3
MP/N1 MP/N0
3
3
RVP/N0
CP/
CP/N0
V0P/N
4
8 to 1
select
RVP/N1
V1P/N
V2P/N
CP/
CP/N1
4
8 to 1
select
4
OP/
OP/N0
Offset
Adjust
Register
OP/
OP/N1
8 to 1
select
CP/
CP/N2
RVP/N8
RVP/N20
4
8 to 1
select
V8 P/N
V9 P/N
RVP/N43
V20 P/N
V21P/N
Gray Scale
Voltage
Generator
5
8 to 1
select
CP/
CP/N3
V55 P/N
V56 P/N
4
8 to 1
select
CP/
CP/N4
RVP/N55
V43P/N
V44P/N
4
RVP/N62
V62 P/N
RVP/N63
V63 P/N
VSSA
Figure 7.3 Structure of grayscale voltage generator
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.81Apr, 2010
HX8353-D
132RGB x 162 dots, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
7.2.2 Gamma-characteristics adjustment register
This HX8353-D has register groups for specifying a series grayscale voltage that
meets the Gamma-characteristics for the LCD panel. These registers are divided into
two groups, which correspond to the gradient, amplitude, and macro adjustment of
the voltage for the grayscale characteristics. The polarity of each register can be
specified independently. (R, G, and B are common.)
7.2.2.1 Offset adjustment registers 0/1
The offset adjustment variable registers are used to adjust the amplitude of the
grayscale voltage. This function is implemented by controlling these variable resisters
in the top and bottom of the gamma resister stream for reference gamma voltage
generation. These registers are available for both positive and negative polarities
7.2.2.2 Gamma center adjustment registers
The gamma center adjustment registers are used to adjust the reference gamma
voltage in the middle level of grayscale without changing the dynamic range. This
function is implemented by controlling these variable resisters in center of the gamma
resister stream for reference gamma voltage generation. These registers are available
for both positive and negative polarities.
7.2.2.3 Gamma macro adjustment registers
The gamma macro adjustment registers can be used for fine adjustment of the
reference gamma voltage. This function is implemented by controlling the 8-to-1
selectors (MP/N0~5), each of which has 8 inputs and generate one reference voltage
output (RVP/N 0, 1, 8, 20, 44, 56, 63, 64). These registers are available for both positive
and negative polarities.
Register
Groups
Center
Adjustment
Macro
Adjustment
Offset
Adjustment
Positive
Polarity
CP/N0 3-0
CP/N1 3-0
CP/N2 3-0
CP/N3 3-0
CP/N4 3-0
MP/N0 2-0
MP/N1 2-0
MP/N2 2-0
MP/N3 2-0
MP/N4 2-0
MP/N5 2-0
OP/N0 3-0
OP/N1 4-0
Description
Variable resistor (VRTP/N) for center adjustment
Variable resistor (VRCP/N0)for center adjustment
Variable resistor (VRMP/N) for center adjustment
Variable resistor (VRCP/N1)for center adjustment
Variable resistor (VRBP/N)for center adjustment
8-to-1 selector (reference voltage level of grayscale 1)
8-to-1 selector (reference voltage level of grayscale 8)
8-to-1 selector (reference voltage level of grayscale 20)
8-to-1 selector (reference voltage level of grayscale 43)
8-to-1 selector (reference voltage level of grayscale 55)
8-to-1 selector (reference voltage level of grayscale 62)
Variable resistor (VRP/N0)for offset adjustment
Variable resistor (VRP/N1)for offset adjustment
Table 7.1 Gamma-adjustment registers
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.82Apr, 2010
HX8353-D
132RGB x 162 dots, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
7.2.3 Gamma resister stream and 8 to 1 selector
The block consists of two gamma resister streams, one is for positive polarity and the
other is for negative polarity, each one includes eight gamma reference voltages
(Vg(P/N)0, 1, 8, 20, 43, 55, 62, 63).
OP/
OP/N1
VREG1
VP/N0
0-60R
60R
0-93R
93R
VRP/N1 VRTP/N
2R
2R*7
VRCP/N0
0-45R
45R
2R*7
20R
20R
2R*7
VRMP/N
0-30R
2R*7
20R
20R
2R
2R*7
VRCP/N1 0-45R
2R
2R*7
VgP/N0
Center adjustment CP/N0
V0 P/N
KVP/N1
VP/N1
KVP/N2
VP/N2
KVP/N3
VP/N3
KVP/N4
VP/N4
KVP/N5
VP/N5
KVP/N6
VP/N6
KVP/N7
VP/N7
KVP/N8
VgP/N1
V1 P/N
Buffer
KVP/N9
VP/N8
KVP/N10
VP/N9
KVP/N11
VP/N10
KVP/N12
VP/N11
KVP/N13
VP/N12
KVP/N14
VP/N13
KVP/N15
VP/N14
KVP/N16
VP/N15
CGM0
R1
1
3R
R2
0
1R
1R
1R
1R
1R
1R
1R
Center adjustment CP/N1
VgP/N2
2
3
5R 2R
1.5R 3.33R 1.83R
2R 2.67R1.67R
1R 1R 1.5R
1R 1R 1.33R
1R 1R 1.17R
1R 1R 1R
V2 P/N
V3 P/N
R3
V4 P/N
R4
V5 P/N
R5
V6 P/N
R6
V7 P/N
R7
V9 P/N
R9
KVP/N18
VP/N17
KVP/N19
VP/N18
KVP/N20
V10 P/N
VP/N19
KVP/N21
VP/N20
KVP/N22
VP/N21
KVP/N23
VP/N22
KVP/N24
V19 P/N
VgP/N3
R19
V20 P/N
R20
Buffer
V21 P/N
R21
V22 P/N
Center adjustment CP/N2
KVP/N25
VP/N23
KVP/N26
VP/N24
KVP/N27
VP/N26
KVP/N28
VP/N27
KVP/N29
VP/N28
KVP/N30
VP/N29
KVP/N31
VP/N30
KVP/N32
VP/N31
V41 P/N
R41
VgP/N4
V42 P/N
V43 P/N
R42
R43
Buffer
V44 P/N
R44
V45 P/N
KVP/N33
VP/N32
KVP/N34
VP/N33
KVP/N35
VP/N34
KVP/N36
VP/N35
KVP/N37
VP/N36
KVP/N38
VP/N37
KVP/N39
VP/N38
KVP/N40
R53
VgP/N5
Buffer
Center adjustment CP/N3
KVP/N41
VP/N39
KVP/N42
VP/N40
KVP/N43
VP/N41
KVP/N44
VP/N42
KVP/N45
VP/N43
KVP/N46
VP/N44
KVP/N47
V54 P/N
R54
VgP/N6
CGM1
0
1R
1R
1R
1R
1R
1R
1R
1
1R
1R
1R
1R
2R
V55 P/N
R55
2
3
1R 1R
1R 1.17R
1R 1.33R
1R 1.5R
2.67R1.67R
1.5R 3.33R 1.83R
3R 5R 2R
V56 P/N
R56
V57 P/N
R57
V58 P/N
R58
V59 P/N
R59
V60 P/N
R60
V61 P/N
R61
V62 P/N
Buffer
KVP/N48
Center adjustment CP/N4
VgP/N7
KVP/N49
45R
VRP/N0 00--45R
VSSA
V8 P/N
R8
Buffer
KVP/N17
VP/N16
VP/N45
VRBP/N 0-60R
KVP/N0
OP/
OP/N0
V63 P/N
Figure 7.4 Gamma resister stream and gamma reference voltage
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.83Apr, 2010
HX8353-D
132RGB x 162 dots, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
7.2.4 Variable resister
There are two types of variable resistors, one is for center adjustment and the other is
for offset adjustment. The resistances are decided by setting values in the center
adjustment, offset adjustment registers. Their relationship is shown as below.
Value in Register
OP/N0 3-0
0000
0001
0010
•
•
1101
1110
1111
Resistance
VRP/N0
0R
3R
6R


39R
42R
45R
Value in Register
OP/N1 4-0
00000
00001
00010
•
•
11101
11110
11111
Resistance
VRP/N1
0R
3R
6R


87R
90R
93R
Table 7.2 Offset adjustment
Value in Register
CP/N0 3-0
0000
0001
0010
•
•
1100
1101
1110
1111
Resistance
VRTP/N
0R
4R
8R


52R
56R
60R
Value in Register
CP/N3 3-0
0000
0001
0010
•
•
1100
1101
1110
1111
Value in Register
CP/N4 3-0
0000
0001
0010
•
•
1100
1101
1110
1111
Resistance
VRCP/N1
0R
3R
6R
•
•
36R
39R
42R
45R
Resistance
VRBP/N
0R
4R
8R
•
•
48R
52R
56R
60R
Value in Register
CP/N2 3-0
0000
0001
0010
•
•
1100
1101
1110
1111
Value in Register
CP/N1 3-0
0000
0001
0010
•
•
1100
1101
1110
1111
Resistance
VRMP/N0
0R
2R
4R
•
•
24R
26R
28R
30R
Resistance
VRCP/N0
0R
3R
6R
•
•
36R
39R
42R
45R
Table 7.3 Center adjustment
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.84Apr, 2010
HX8353-D
132RGB x 162 dots, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
8 to 1 selector
The 8 to 1 selector has eight input voltages generated by gamma resister stream, and
outputs one reference voltages selected from inputs for gamma reference voltage
generation by setting value in macro adjustment register. There are six 8 to 1
selectors and the relationship is shown as below.
Value in Register
M(P/N) 2-0
000
001
010
011
100
101
110
111
Vg(P/N) 1
VP(N)1
VP(N)2
VP(N)3
VP(N)4
VP(N)5
VP(N)6
VP(N)7
VP(N)8
Vg(P/N) 2
VP(N)9
VP(N)10
VP(N)11
VP(N)12
VP(N)13
VP(N)14
VP(N)15
VP(N)16
Voltage level
Vg(P/N) 3
Vg(P/N) 4
VP(N)17
VP(N)25
VP(N)18
VP(N)26
VP(N)19
VP(N)27
VP(N)20
VP(N)28
VP(N)21
VP(N)29
VP(N)22
VP(N)30
VP(N)23
VP(N)31
VP(N)24
VP(N)32
Vg(P/N) 5
VP(N)33
VP(N)34
VP(N)35
VP(N)36
VP(N)37
VP(N)38
VP(N)39
VP(N)40
Vg(P/N) 6
VP(N)41
VP(N)42
VP(N)43
VP(N)44
VP(N)45
VP(N)46
VP(N)47
VP(N)48
Table 7.4 Output voltage of 8 to 1 selector
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.85Apr, 2010
HX8353-D
132RGB x 162 dots, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
The grayscale levels are determined by the following formulas.
Reference
Voltage
VgP/N0
VgP1/VgN7
VgP2/VgN2
VgP3/VgN3
VgP4/VgN4
VgP5/VgN5
VgP6/VgN6
Formula
MP/N0 2-0=000
MP/N0 2-0=001
MP/N0 2-0=010
MP/N0 2-0=011
MP/N0 2-0=100
MP/N0 2-0=101
MP/N0 2-0=110
MP/N0 2-0=111
MP/N1 2-0=000
MP/N1 2-0=001
MP/N1 2-0=010
MP/N1 2-0=011
MP/N1 2-0=100
MP/N1 2-0=101
MP/N1 2-0=110
MP/N1 2-0=111
MP/N2 2-0=000
MP/N2 2-0=001
MP/N2 2-0=010
MP/N2 2-0=011
MP/N2 2-0=100
MP/N2 2-0=101
MP/N2 2-0=110
MP/N2 2-0=111
MP/N3 2-0=000
MP/N3 2-0=001
MP/N3 2-0=010
MP/N3 2-0=011
MP/N3 2-0=100
MP/N3 2-0=101
MP/N3 2-0=110
MP/N3 2-0=111
MP/N4 2-0=000
MP/N4 2-0=001
MP/N4 2-0=010
MP/N4 2-0=011
MP/N4 2-0=100
MP/N4 2-0=101
MP/N4 2-0=110
MP/N4 2-0=111
MP/N5 2-0=000
MP/N5 2-0=001
MP/N5 2-0=010
MP/N5 2-0=011
MP/N5 2-0=100
MP/N5 2-0=101
MP/N5 2-0=110
MP/N5 2-0=111
VgP7/VgN7
-
VREG1-VD*VRP/N1 /sumRP/N
VREG1 –VD((VRP/N1+VRTP/N) /sumRP/N
VREG1 –VD((VRP/N1+ VRTP/N +2R) /sumRP/N
VREG1 –VD((VRP/N1+ VRTP/N +4R) /sumRP/N
VREG1 –VD((VRP/N1+ VRTP/N +6R) /sumRP/N
VREG1 –VD((VRP/N1+ VRTP/N +8R) /sumRP/N
VREG1 –VD((VRP/N1+ VRTP/N +10R) /sumRP/N
VREG1 –VD((VRP/N1+ VRTP/N +12R) /sumRP/N
VREG1 –VD((VRP/N1+ VRTP/N +14R) /sumRP/N
VREG1 –VD((VRP/N1+ VRTP/N +14R+VRCP/N0) /sumRP/N
VREG1 –VD((VRP/N1+ VRTP/N +16R+VRCP/N0) /sumRP/N
VREG1 –VD((VRP/N1+ VRTP/N +18R+VRCP/N0) /sumRP/N
VREG1 –VD((VRP/N1+ VRTP/N +20R+VRCP/N0) /sumRP/N
VREG1 –VD((VRP/N1+ VRTP/N +22R+VRCP/N0) /sumRP/N
VREG1 –VD((VRP/N1+ VRTP/N +24R+VRCP/N0) /sumRP/N
VREG1 –VD((VRP/N1+ VRTP/N +26R+VRCP/N0) /sumRP/N
VREG1 –VD((VRP/N1+ VRTP/N +28R+VRCP/N0) /sumRP/N
VREG1 –VD((VRP/N1+ VRTP/N+48R+VRCP/N0) /sumRP/N
VREG1 –VD((VRP/N1+ VRTP/N+50R+VRCP/N0) /sumRP/N
VREG1 –VD((VRP/N1+ VRTP/N+52R+VRCP/N0) /sumRP/N
VREG1 –VD((VRP/N1+ VRTP/N+54R+VRCP/N0) /sumRP/N
VREG1 –VD((VRP/N1+ VRTP/N+56R+VRCP/N0) /sumRP/N
VREG1 –VD((VRP/N1+ VRTP/N+58R+VRCP/N0) /sumRP/N
VREG1 –VD((VRP/N1+ VRTP/N+60R+VRCP/N0) /sumRP/N
VREG1 –VD((VRP/N1+ VRTP/N+62R+VRCP/N0) /sumRP/N
VREG1 –VD((VRP/N1+ VRTP/N+ VRMP/N +62R+VRCP/N0) /sumRP/N
VREG1 –VD((VRP/N1+ VRTP/N+ VRMP/N +64R+VRCP/N0) /sumRP/N
VREG1 –VD((VRP/N1+ VRTP/N+ VRMP/N +66R+VRCP/N0) /sumRP/N
VREG1 –VD((VRP/N1+ VRTP/N+ VRMP/N +68R+VRCP/N0) /sumRP/N
VREG1 –VD((VRP/N1+ VRTP/N+ VRMP/N +70R+VRCP/N0) /sumRP/N
VREG1 –VD((VRP/N1+ VRTP/N+ VRMP/N +72R+VRCP/N0) /sumRP/N
VREG1 –VD((VRP/N1+ VRTP/N+ VRMP/N +74R+VRCP/N0) /sumRP/N
VREG1 –VD((VRP/N1+ VRTP/N+ VRMP/N +76R+VRCP/N0) /sumRP/N
VREG1 –VD((VRP/N1+ VRTP/N+ VRMP/N +96R+VRCP/N0) /sumRP/N
VREG1 –VD((VRP/N1+ VRTP/N+ VRMP/N +98R+VRCP/N0) /sumRP/N
VREG1 –VD((VRP/N1+ VRTP/N+ VRMP/N +100R+VRCP/N0) /sumRP/N
VREG1 –VD((VRP/N1+ VRTP/N+ VRMP/N +102R+VRCP/N0) /sumRP/N
VREG1 –VD((VRP/N1+ VRTP/N+ VRMP/N +104R+VRCP/N0) /sumRP/N
VREG1 –VD((VRP/N1+ VRTP/N+ VRMP/N +106R+VRCP/N0) /sumRP/N
VREG1 –VD((VRP/N1+ VRTP/N+ VRMP/N +108R+VRCP/N0) /sumRP/N
VREG1 –VD((VRP/N1+ VRTP/N+ VRMP/N +110R+VRCP/N0) /sumRP/N
VREG1 –VD((VRP/N1+ VRTP/N+ VRMP/N+110R+VRCP/N0 +VRCP/N1) /sumRP/N
VREG1 –VD((VRP/N1+ VRTP/N+ VRMP/N +112R+VRCP/N0+VRCP/N1) /sumRP/N
VREG1 –VD((VRP/N1+ VRTP/N+ VRMP/N +114R+VRCP/N0+VRCP/N1) /sumRP/N
VREG1 –VD((VRP/N1+ VRTP/N+ VRMP/N +116R+VRCP/N0+VRCP/N1) /sumRP/N
VREG1 –VD((VRP/N1+ VRTP/N+ VRMP/N +118R+VRCP/N0+VRCP/N1) /sumRP/N
VREG1 –VD((VRP/N1+ VRTP/N+ VRMP/N +120R+VRCP/N0+VRCP/N1) /sumRP/N
VREG1 –VD((VRP/N1+ VRTP/N+ VRMP/N +122R+VRCP/N0+VRCP/N1) /sumRP/N
VREG1 –VD((VRP/N1+ VRTP/N+ VRMP/N +124R+VRCP/N0+VRCP/N1) /sumRP/N
VREG1 –VD((VRP/N1+ VRBP/N+ VRTP/N+ VRMP/N +104R+VRCP/N0+VRCP/N1)
/sumRP/N
SumRP=124R+VRP0+ VRP1+ VRTP+ VRCP0+VRMP+VRCP1+VRBP
SumRN=124R+ VRN0+ VRN1+ VRTN+ VRCN0+VRMN+VRCN1+VRBN
VD=(VREG1–VSSA)
Table 7.5 Voltage calculation formula
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.86Apr, 2010
HX8353-D
132RGB x 162 dots, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
Grayscale
Voltage
V0P/V63N
V1P/V62N
V2P/V61N
V3P/V60N
V4P/V59N
V5P/V58N
V6P/V57N
V7P/V56N
V8P/V55N
V9P/V54N
V10P/V53N
V11P/V52N
V12P/V51N
V13P/V50N
V14P/V49N
V15P/V48N
V16P/V47N
V17P/V46N
V18P/V45N
V19P/V44N
V20P/V43N
V21P/V42N
V22P/V41N
V23P/V40N
V24P/V39N
V25P/V38N
V26P/V37N
V27P/V36N
V28P/V35N
V29P/V34N
V30P/V33N
V31P/V32N
Formula
VgP/N0
VgP/N1
VgP/N2+(VgP/N1-VgP/N2)*CT1
VgP/N2+(VgP/N1-VgP/N2)*CT2
VgP/N2+(VgP/N1-VgP/N2)*CT3
VgP/N2+(VgP/N1-VgP/N2)*CT4
VgP/N2+(VgP/N1-VgP/N2)*CT5
VgP/N2+(VgP/N1-VgP/N2)*CT6
VgP/N2
VgP/N3+(VgP/N2-VgP/N3)*(22/24)
VgP/N3+(VgP/N2-VgP/N3)*(20/24)
VgP/N3+(VgP/N2-VgP/N3)*(18/24)
VgP/N3+(VgP/N2-VgP/N3)*(16/24)
VgP/N3+(VgP/N2-VgP/N3)*(14/24)
VgP/N3+(VgP/N2-VgP/N3)*(12/24)
VgP/N3+(VgP/N2-VgP/N3)*(10/24)
VgP/N3+(VgP/N2-VgP/N3)*(8/24)
VgP/N3+(VgP/N2-VgP/N3)*(6/24)
VgP/N3+(VgP/N2-VgP/N3)*(4/24)
VgP/N3+(VgP/N2-VgP/N3)*(2/24)
VgP/N3
VgP/N4+(VgP/N3-VgP/N4)*(22/23)
VgP/N4+(VgP/N3-VgP/N4)*(21/23)
VgP/N4+(VgP/N3-VgP/N4)*(20/23)
VgP/N4+(VgP/N3-VgP/N4)*(19/23)
VgP/N4+(VgP/N3-VgP/N4)*(18/23)
VgP/N4+(VgP/N3-VgP/N4)*(17/23)
VgP/N4+(VgP/N3-VgP/N4)*(16/23)
VgP/N4+(VgP/N3-VgP/N4)*(15/23)
VgP/N4+(VgP/N3-VgP/N4)*(14/23)
VgP/N4+(VgP/N3-VgP/N4)*(13/23)
VgP/N4+(VgP/N3-VgP/N4)*(12/23)
Grayscale
Voltage
V32P/V31N
V33P/V30N
V34P/V29N
V35P/V28N
V36P/V27N
V37P/V26N
V38P/V25N
V39P/V24N
V40P/V23N
V41P/V22N
V42P/V21N
V43P/V20N
V44P/V19N
V45P/V18N
V46P/V17N
V47P/V16N
V48P/V15N
V49P/V14N
V50P/V13N
V51P/V12N
V52P/V11N
V53P/V10N
V54P/V9N
V55P/V8N
V56P/V7N
V57P/V6N
V58P/V5N
V59P/V4N
V60P/V3N
V61P/V2N
V62P/V1N
V63P/V0N
Formula
VgP/N4+(VgP/N3-VgP/N4)*(11/23)
VgP/N4+(VgP/N3-VgP/N4)*(10/23)
VgP/N4+(VgP/N3-VgP/N4)*(9/23)
VgP/N4+(VgP/N3-VgP/N4)*(8/23)
VgP/N4+(VgP/N3-VgP/N4)*(7/23)
VgP/N4+(VgP/N3-VgP/N4)*(6/23)
VgP/N4+(VgP/N3-VgP/N4)*(5/23)
VgP/N4+(VgP/N3-VgP/N4)*(4/23)
VgP/N4+(VgP/N3-VgP/N4)*(3/23)
VgP/N4+(VgP/N3-VgP/N4)*(2/23)
VgP/N4+(VgP/N3-VgP/N4)*(1/23)
VgP/N4
VgP/N5+(VgP/N4-VgP/N5)*(22/24)
VgP/N5+(VgP/N4-VgP/N5)*(20/24)
VgP/N5+(VgP/N4-VgP/N5)*(18/24)
VgP/N5+(VgP/N4-VgP/N5)*(16/24)
VgP/N5+(VgP/N4-VgP/N5)*(14/24)
VgP/N5+(VgP/N4-VgP/N5)*(12/24)
VgP/N5+(VgP/N4-VgP/N5)*(10/24)
VgP/N5+(VgP/N4-VgP/N5)*(8/24)
VgP/N5+(VgP/N4-VgP/N5)*(6/24)
VgP/N5+(VgP/N4-VgP/N5)*(4/24)
VgP/N5+(VgP/N4-VgP/N5)*(2/24)
VgP/N5
VgP/N6+(VgP/N5-VgP/N6)*CB1
VgP/N6+(VgP/N5-VgP/N6)*CB2
VgP/N6+(VgP/N5-VgP/N6)*CB3
VgP/N6+(VgP/N5-VgP/N6)*CB4
VgP/N6+(VgP/N5-VgP/N6)*CB5
VgP/N6+(VgP/N5-VgP/N6)*CB6
VgP/N6
VgP/N7
Table 7.6 Voltage calculation formula of grayscale voltage
CGM0[1:0]
“00”
“01”
“10”
“11”
CGM1[1:0]
“00”
“01”
“10”
“11”
CT1
6/7
7.5/10.5 10/15
8.5/10.5
CB1
6/7
9.5/10.5
14/15
9.5/10.5
CT2
5/7
6/10.5 6.67/15 6.67/10.5
CB2
5/7
8.5/10.5
13/15 8.33/10.5
CT3
4/7
4/10.5
4/15
5.0/10.5
CB3
4/7
7.5/10.5
12/15
7.0/10.5
CT4
3/7
3/10.5
3/15
3.5/10.5
CB4
3/7
6.5/10.5
11/15
5.5/10.5
CT5
2/7
2/10.5
2/15
2.17/10.5
CB5
2/7
4.5/10.5 8.33/15 3.83/10.5
CT6
1/7
1/10.5
1/15
1/10.5
CB6
1/7
3.0/10.5
5/15
2.0/10.5
Note: Negative gamma don’t have CGM0/CGM1 setting, the ratio V2~V7 and V56~V61 is automatically mapping from
positive side.
Table 7.7 Voltage calculation formula of grayscale voltage V2~V7 and V56~V61
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DATA SHEET Preliminary V01
Relationship between GRAM Data and Output Level (“Normally White Panel”,
GRAM data=0)
Figure 7.5 Relationship between source output and VCOM
V0
Output Level
Positive polarity
Negative polarity
V63
000000
RAM Data
111111
(Same characteristic for each RGB)
Figure 7.6 Relationship between GRAM data and output level (normal white panel REV_Panel=“0”)
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DATA SHEET Preliminary V01
Four-characteristic gamma curve selection
There are four kind of Gamma Curve is selected by GAMSET command. The
parameter GC[7:0] is stored in internal register and used to select one set of gamma
correction register.
GC_SEL=“L”:
Figure 7.7 Gamma curve according to GC0 to GC3 bit (GC_SEL=”L”)
GC_SEL=“H”:
Figure 7.8 Gamma curve according to GC0 to GC3 bit (GC_SEL=”H”)
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DATA SHEET Preliminary V01
7.3 Tearing effect output line
The Tearing Effect output line supplies to the MPU a Panel synchronization signal.
This signal can be enabled or disabled by the Tearing Effect Line off & on commands.
The mode of the Tearing Effect signal is defined by the parameter of the Tearing
Effect Line On command. The signal can be used by the MPU to synchronize Frame
Memory Writing when displaying video images.
7.3.1 Tearing effect line modes
Mode 1: The Tearing Effect Output signal consists of V-Blanking Information only:
tVdh= The LCD display is not updated from the Frame Memory
tvdl = The LCD display is updated from the Frame Memory (except Invisible Line – see below)
Figure 7.9 TE mode 1 output
Mode 2: The Tearing Effect Output signal consists of V-Blanking and H-Blanking
Information, there is one V-sync and N H-sync pulses per field on different
resolution.
128RGBx160: N=160
132RGBx162: N=162
96x68: N=68
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96x64: N=64
Figure 7.10 TE mode 2 output
thdh= The LCD display is not updated from the Frame Memory
thdl= The LCD display is updated from the Frame Memory (except Invisible Line – see above.)
Note: During Sleep In Mode, the Tearing Output Pin is active Low.
Figure 7.11 TE output waveform
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DATA SHEET Preliminary V01
7.3.2 Tearing effect line timing
The Tearing Effect signal is described below.
Figure 7.12 Waveform of tearing effect signal
Symbol
tvdl
tvdh
thdl
thdh
Idle Mode Off (Frame Rate=60Hz)
Parameter
Min.
Max.
Unit
Description
Vertical Timing Low Duration
TBD
ms
Vertical Timing High Duration
1000
µs
Horizontal Timing Low Duration
TBD
µs
Horizontal Timing High Duration
TBD
500
µs
Table 7.8 AC characteristics of tearing effect signal
The signal’s rise and fall times (tf, tr) are stipulated to be equal to or less than 15ns.
Figure 7.13 Timing of tearing effect signal
The Tearing Effect Output Line is fed back to the MPU and should be used as shown
below to avoid Tearing Effect:
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DATA SHEET Preliminary V01
7.3.3 Example 1: MPU write is faster than panel read
Figure 7.14 Timing of MPU write is faster than panel read
Data write to frame memory is now synchronized to the panel scan. It should be
written during the vertical sync pulse of the tearing effect output line. This ensures
that data is always written ahead of the panel scan and each panel frame refresh has
a complete new image:
Figure 7.15 Display of MPU write is faster than panel read
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DATA SHEET Preliminary V01
7.3.4 Example 2: MPU write is slower than panel read
Figure 7.16 Timing of MPU write is slower than panel read
The MPU to frame memory write begins just after panel read has commenced i.e.
after one horizontal sync pulse of the tearing effect output line. This allows time for the
image to download behind the panel read pointer and finishing download during the
subsequent frame before the read pointer “catches” the MPU to frame memory write
position.
Figure 7.17 Display of MPU write is slower than panel read
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7.4 Scan Mode Setting
HX8353-D can set internal register GS_PANEL bit to determine the pin assignment of gate. The
GS_PANEL setting allows changing the shift direction of gate outputs by connecting LCD panel
with the HX8353-D.
G2 to G162
G1 to G161
G162 to G2
G161 to G1
Figure 7.18 Gate Scan Mode
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DATA SHEET Preliminary V01
7.5 LCD power generation circuit
7.5.1 Power supply circuit
The power circuit of HX8353-D is used to generate supply voltages for LCD panel
driving.
C11A
C11B
C12A
Step up
Circuit 1
C12B
VCL
DDVDH
VCI
VSSA
Reference
Voltage
Generation
Circuit
VSSD
IOVCC
VDDD
VREG1
Reference
Voltage
Generation
Circuit
C21A
C21B
Step up
Circuit 2
C22A
C22B
VGH
VGL
Figure 7.19 Block diagram of HX8353-D power circuit
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DATA SHEET Preliminary V01
Specification of Connected Passive Component
Capacitor
C1 (DDVDH)
C2 (C11)
C3 (VGL)
Recommended voltage
Capacity
6.3V
1 µF (B characteristics)
6.3V
1 µF (B characteristics)
16V
1 µF (B characteristics)
Table 7.9 The adoptability of Capacitor
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DATA SHEET Preliminary V01
7.5.2 LCD power generation scheme
The boost voltage generated is shown as below.
VGH
VGH (2DDVDH ~
3DDVDH)
DC/DC
DDVDH
DDVDH
DC/DC
VREG1
VREG1 (3.3 ~ 4.8V)
VCOMH
VCI (2.5 ~ 3.3V)
.
VDDD
VCOMH
VDDD (1.6V)
VSSA, VSSD (0V)
VCOML
DC/DC
x (-1)
VCL
VCOML
DC/DC
VGL VGL (-VCI-2DDVDH ~
-VCI-DDVDH)
NOTE:Register / Voltage mapping
VRH[4:0]
VREG1
VMH[6:0]
VCOMH
VML[6:0]
VCOML
BT[2:0]
VGH, VGL
Figure 7.20 LCD power generation scheme
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DATA SHEET Preliminary V01
7.6 Power function
7.6.1 Power on/off sequence
Power source IOVCC, VCI can be applied and powered down in any order.
IOVCC, VCI can be powered down in any order.
During power off, if LCD is in the Sleep Out mode, IOVCC, VCI must be powered
down minimum 120msec after NRESET has been released.
During power off, if LCD is in the Sleep In mode, IOVCC, VCI can be powered down
minimum 0msec after NRESET has been released.
NCS can be applied at any timing or can be permanently grounded. NRESET has
priority over NCS.
Note: (1) There will be no damage to the display module if the power sequences are not met.
(2) There will be no abnormal visible effects on the display panel during the Power On/Off Sequences.
(3) There will be no abnormal visible effects on the display between end of Power on Sequence and before
receiving Sleep Out command. Also between receiving Sleep In command and Power Off Sequence.
(4) If NRESET line is not held stable by host during Power on Sequence as defined in Sections 7.5.1.1 and
7.5.1.2, then it will be necessary to apply a Hardware Reset (NRESET) after Host Power on Sequence
to ensure correct operation. Otherwise correct function is not guaranteed.
If NRESET line is not held stable by host during Power on Sequence as defined in
Sections 7.5.1.1 and 7.5.1.2, then it will be necessary to apply a Hardware Reset
(NRESET) after Host Power on Sequence is complete to ensure correct operation,
otherwise correct functionality is not guaranteed. The power on/off sequence is
illustrated as below.
7.6.1.1 Case 1 – NRESET line is held high or unstable by host at power on
If NRESET line is held high or unstable by the host during Power On, then a
Hardware Reset must be applied after both IOVCC, VCI have been applied,
otherwise correct functionality is not guaranteed. There is no timing restriction upon
this hardware reset.
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DATA SHEET Preliminary V01
tRPW= +/- no limit
tFPW= +/- no limit
IOVCC
VCI
Time when the latter signal rises up to 90% of its typical .
value
Time when the former signal falls down to 90% of its
Typical value
tRPWNCS = +/- no limit
NCS
tFPWNCS = +/- no limit
H or L
tRPWNRES= + no limit
tFPWNRES1 = min120ms
NRESET
(Power down in
sleep out mode)
tRPWNRES = + no limit
NRESET
( Power down in
sleep in mode)
tFPWNRES2 = min0ns
tFPWNRES1 is applied to NRESET falling in the Sleep Out Mode
tFPWNRES2 is applied to NRESET falling in the Sleep In Mode
Note:
Note: Unless otherwise specified, timings herein show cross point at 50% of signal/power level.
Figure 7.21 Case 1 – NRESET line is held high or unstable by host at power on
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7.6.1.2 Case 2 – NRESET line is held low by host at power on
If NRESET line is held Low (and stable) by the host during Power On, then the
NRESET must be held low for minimum 10µsec after VCI have been applied.
tRPW= +/- no limit
tFPW= +/- no limit
IOVCC
VCI
Time when the latter signal rises up to 90% of its typical value
.
Time when the former signal falls down to 90% of its Typical
value
tRPWNCS= +/- no limit
tRPWNCS= +/- no limit
NCS
H or L
tFPWNRES1 = min120ms
tRPWNRES = min10us
NRESET
( Power down in
Sleep Out mode)
tRPWNRES= min10us
NRESET
tFPWNRES 2 = min0 ns
( Power down in
Sleep In mode )
tFPWNRES1 is applied to NREST falling in the Sleep Out Mode
tFPWNRES2 is applied to NREST falling in the Sleep In Mode
Note:
Note: Unless otherwise specified, timings herein show cross point at 50% of signal/power level.
Figure 7.22 NRESET Line is Held Low by Host at Power On
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7.6.2 Power levels definition
7.6.2.1 General definition for power levels on system interface
Figure 7.23 Power flow chart for different power modes
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7.6.3 Deep standby mode set up flow
Display off flow
SLEEP IN
Set deep
SETEXTC
(RB9h=FFh,83h,53h)
Set deep standby
(DP_STB_S = "1", RB1h=01h)
Set deep standby
(DP_STB = "1",RB1h=03h)
Set deep standby
(DP_STB = "0",RB1h=01h)
Wait >20ms
Set deep standby
(DP_STB_S = "0",RB1h=00h)
standby
Release
deep
standby
SLEEP OUT
Display on
Figure 7.24 Deep standby mode setting flow
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7.7 Sleep out – command and self-diagnostic functions of display module
7.7.1 Register loading detection
Sleep Out-command (See section 8.2.12 “Sleep Out (11h)”) is a trigger for an internal
function of the display module, which indicates, if the display module loading function
of factory default values from EEPROM (or similar device) to registers of the display
controller is working properly.
There are compared factory values of the EEPROM and register values of the display
controller by the display controller. If those both values (EEPROM and register values)
are the same, there is an inverted (=increased by 1) bit, which is defined in section
8.2.10 “Read Display Self-Diagnostic Result (0Fh)” (=RDDSDR) (The bit used for this
command is D7). If those both values are not the same, this bit (D7) is not inverted (=
increased by 1). The flow chart for this internal function is shown as below.
Power on sequence
HW reset
SW reset
Sleep In (10h)
Sleep Out
Mode
Sleep In
Mode
RDDSDR`s D7=0
Sleep Out (11h)
Compares EEPROM and register
values
Load
EEPROM to
register
NO
Are EEPROM and
register values the
same
YES
D7 inverted
Note: There is not compared and loaded register values, which can be changed by User (User area commands:
00h to AFh and DAh to DDh), by the display module.
Figure 7.25 RDDSDR register loading detection flow
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7.7.2 Functionality detection
Sleep Out-command (See section 8.2.12 “Sleep Out (11h)”) is a trigger for an internal
function of the display module, which indicates, if the display module is still running
and meets functionality requirements.
The internal function (= the display controller) is comparing, if the display module is
still meeting functionality requirements (e.g. booster voltage levels, timings, etc.) If
functionality requirement is met, there is an inverted (= increased by 1) bit, which
defined in section 8.2.10 “Read Display Self- Diagnostic Result (0Fh)” (= RDDSDR)
(The used bit of this command is D6). If functionality requirement is not same, this bit
(D6) is not inverted (= increased by 1). The flow chart for this internal function is
shown as below.
Note: There is needed 120msec after Sleep Out -command, when there is changing from Sleep In –mode to Sleep
Out -mode, before there is possible to check if User’s functionality requirements are met and a value of
RDDSDR’s D6 is valid. Otherwise, there is 5msec delay for D6’s value, when Sleep Out –command is sent in
Sleep Out -mode.
Figure 7.26 Functionality detection flow
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DATA SHEET Preliminary V01
7.8
Input / output pin state
7.8.1 Output pins
Output or Bi-directional
pins
TE
DB17 to DB0
(Output driver)
VTESTOUT
Low
After Hardware
Reset
Low
High-Z (Inactive)
High-Z (Inactive)
After Power On
After Software Reset
Low
High-Z (Inactive)
Low
Low
Table 7.10 Characteristics of output pins
Low
7.8.2 Input pins
Input pins
NRESET
NCS
SPI_SEL
GC_SEL
LC_SEL0, LC_SEL1
DNC_SCL
NWR_RNW
NRD_E
DB17 to DB0
OSC,P68,BS1,BS2,BS0
EXTC
TEST1
TEST2
RSO0
RSO1
RSO2
During
After
After
Power
Power
Hardware
On Process
On
Reset
Input valid
Input valid
Input valid
Input valid
Input valid
Input valid
Input valid
Input valid
Input valid
Input valid
Input valid
Input valid
Input valid
Input valid
Input valid
Input valid
Input valid
Input valid
Input valid
Input valid
Input valid
Input valid
Input valid
Input valid
Input valid
Input valid
Input valid
Input valid
Input valid
Input valid
Input valid
Input valid
Input valid
Input valid
Input valid
Input valid
Input valid
Input valid
Input valid
Input valid
Input valid
Input valid
Input valid
Input valid
Input valid
Input valid
Input valid
Input valid
Table 7.11 Characteristics of input pins
After
Software
Reset
Input valid
Input valid
Input valid
Input valid
Input valid
Input valid
Input valid
Input valid
Input valid
Input valid
Input valid
Input valid
Input valid
Input valid
Input valid
Input valid
During
Power
Off Process
Input valid
Input valid
Input valid
Input valid
Input valid
Input valid
Input valid
Input valid
Input valid
Input valid
Input valid
Input valid
Input valid
Input valid
Input valid
Input valid
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DATA SHEET Preliminary V01
8. Command Set
8.1 Command set list
(Hex)
Operation
Code
00
01
NOP
SWRESET
04
09
0A
RDDIDIF
RDDST
RDDPM
0B
RDDMADCTL
0C
RDDCOLM
OD
0D
0E
0F
RDDIM
RDDSM
DNC NWR NRD
D7
D6
D5
D4
D3
D2
D1
D0
Function
0
0
↑
↑
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
↑
1
0
0
0
0
0
1
0
0
1
1
1
1
0
1
1
1
1
1
1
1
1
1
↑
1
1
1
1
1
↑
↑
↑
↑
1
↑
↑
↑
↑
↑
-
-
-
-
-
-
0
D31
0
D15
D7
0
D30
D22
0
D6
0
D29
D21
D13
D5
0
D26
D18
D10
0
0
D25
D17
D9
0
1
0
D16
D8
0
No operation
Software reset
Read display
identification
information
Dummy read
ID1 read
ID2 read
ID3 read
Read display status
Dummy read
0
↑
1
0
0
0
0
1
0
1
0
1
1
1
1
↑
↑
D7
D6
D5
D4
D3
D2
0
0
0
↑
1
0
0
0
0
1
0
1
1
1
1
1
1
↑
↑
D7
D6
D5
D4
D3
D2
0
0
0
↑
1
0
0
0
0
1
1
0
0
1
1
1
1
↑
↑
0
0
0
0
0
D2
D1
D0
0
↑
1
0
0
0
0
1
1
0
1
1
1
1
1
↑
↑
D7
0
D5
0
0
D2
D1
D0
0
↑
1
0
0
0
0
1
1
1
0
1
1
1
1
↑
↑
D7
D6
0
0
0
0
0
0
0
↑
1
0
0
0
0
1
1
1
1
1
1
1
1
↑
↑
D7
D6
D5
D4
0
0
0
0
ID1[7:0]
ID2[7:0]
ID3[7:0]
0
1
D28
D27
D20
D19
0
0
0
0
RDDSDR
10
SLPIN
0
↑
1
0
0
0
1
0
0
0
0
11
SLPOUT
0
↑
1
0
0
0
1
0
0
0
1
12
PTLON
0
↑
1
0
0
0
1
0
0
1
0
13
NORON
0
↑
1
0
0
0
1
0
0
1
1
20
INVOFF
0
↑
1
0
0
1
0
0
0
0
0
21
INVON
0
↑
1
0
0
1
0
0
0
0
1
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
Read display power
mode
Dummy read
Read display
MADCTL
Dummy read
Read display pixel
format
Dummy read
Read display image
mode
Dummy read
Read display signal
mode
Dummy read
Read display
self-diagnostic
result
Dummy read
Sleep in and
charge-pump off
Sleep out and
charge-pump on
Partial mode on
Normal display
mode on
Display inversion
off
Display inversion
on
-P.107Apr, 2010
HX8353-D
132RGB x 162 dots, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
(Hex)
Operation
Code
26
GAMSET
28
29
DISPOFF
DISPON
2A
CASET
2B
PASET
2C
RAMWR
2D
RGBSET
2E
RAMRD
30
33
PLTAR
VSCRDEF
34
TEOFF
35
TEON
DNC NWR NRD
D7
D6
D5
0
1
0
0
0
↑
↑
↑
↑
↑
1
1
1
1
1
0
0
1
0
0
0
0
0
0
1
1
1
1
↑
1
SC[15:8]
1
↑
1
SC[7:0]
1
↑
1
EC[15:8]
1
↑
1
EC[7:0]
0
1
1
1
1
0
1
0
1
↑
↑
↑
↑
↑
↑
↑
↑
↑
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
↑
↑
0
↑
1
1
1
1
1
0
1
1
↑
↑
↑
↑
↑
↑
↑
1
1
1
1
1
1
1
1
↑
1
1
1
1
0
0
1
↑
↑
↑
↑
↑
↑
1
1
1
1
1
1
0
0
1
0
0
1
0
:
:
:
:
:
:
0
-
0
:
:
:
:
:
:
0
-
1
R005
:
Rnn5
:
R315
G005
:
Gnn5
:
G635
B005
:
Bnn5
:
B315
1
-
0
0
1
0
TFA15
TFA7
VSA
15
VSA7
BFA15
BFA7
0
0
-
0
TFA14
TFA6
VSA
14
VSA6
BFA14
BFA6
0
0
-
1
TFA13
TFA5
VSA
13
VSA5
BFA13
BFA5
1
1
-
D4
D3
0
0
GC[7:0]
0
1
0
1
0
1
0
1
SP[15:8]
SP[7:0]
EP[15:8]
EP[7:0]
0
1
D[17:0]
0
1
R004 R003
:
:
Rnn4 Rnn3
:
:
R314 R313
G004 G003
:
:
Gnn4 Gnn3
:
:
G634 G633
B004 B003
:
:
Bnn4 Bnn3
:
:
B314 B313
0
1
D[15:0]
1
0
SR[15:8]
SR[7:0]
ER[15:8]
ER[7:0]
1
0
TFA12 TFA11
TFA4 TFA3
VSA VSA
12
11
VSA4 VSA3
BFA12 BFA11
BFA4 BFA3
1
0
1
0
-
D2
D1
D0
1
1
0
0
0
0
0
0
1
0
1
0
0
1
1
0
1
R002
:
Rnn2
:
R312
G002
:
Gnn2
:
G632
B002
:
Bnn2
:
B312
1
-
0
R001
:
Rnn1
:
R311
G001
:
Gnn1
:
G631
B001
:
Bnn1
:
B311
1
-
0
0
0
TFA10
TFA2
VSA
10
VSA2
BFA10
BFA2
1
1
-
1
TFA9
TFA1
VSA9
VSA1
BFA9
BFA1
0
0
-
Function
Gamma set
Display off
Display on
Column setting
Column address
start
Column address
start
Column address
end
Column address
end
1
Row address set
Row address start
Row address start
Row address end
Row address end
0
Memory write
Write GRAM data
1
LUT parameter
R000 Red tone
:
Rnn0 Red tone
:
R310 Red tone
G000 Green tone
:
Gnn0 Green tone
:
G630 Green tone
B000 Blue tone
:
Bnn0 Blue tone
:
B310 Blue tone
0
Memory read
Dummy read
Read GRAM data
Partial start end
0
address set
Start row
Start row
End row
End row
1
TFA8
TFA0
Vertical Scrolling
VSA8
Definition
VSA0
BFA8
BFA0
0
Tear effect Off
1
Tear effect mode
TEMODE
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.108Apr, 2010
HX8353-D
132RGB x 162 dots, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
(Hex)
Operation
Code
36
MADCTL
37
VSCRSADD
38
39
IDMOFF
IDMON
3A
COLMOD
DA
RDID1
DB
RDID2
DC
RDID3
DNC NWR NRD
D7
D6
D5
D4
D3
D2
D1
D0
0
↑
1
0
0
1
1
0
1
1
0
1
↑
1
MY
MX
MV
ML
BGR
SS
0
0
0
↑
1
0
0
1
1
0
1
1
1
1
↑
1
1
0
0
↑
↑
↑
1
1
1
0
↑
1
1
0
1
1
0
1
1
0
1
1
↑
↑
1
1
↑
1
1
↑
1
1
1
1
↑
↑
1
↑
↑
1
↑
↑
Function
Memory access
control
Vertical scrolling
start address
VSP VSP VSP VSP VSP VSP
VSP9 VSP8
15
14
13
12
11
10
VSP7 VSP6 VSP5 VSP4 VSP3 VSP2 VSP1 VSP0
0
0
1
1
1
0
0
0
Idle mode off
0
0
1
1
1
0
0
1
Idle mode on
Interface pixel
0
0
1
1
1
0
1
0
format
0
0
0
0
0
D2
D1
D0
1
1
0
1
1
0
1
0
Read ID1
Dummy read
module’s manufacturer[7:0]
1
1
0
1
1
0
1
1
Read ID2
Dummy read
1
LCD module/driver version [6:0]
1
1
0
1
1
1
0
0
Read ID3
Dummy read
LCD module/driver ID[7:0]
Table 8.1 System interface command set
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.109Apr, 2010
HX8353-D
132RGB x 162 dots, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
Extended command set
(Hex)
Operation
DNC NWR NRD D15-8
Code
0
B0
B1
B2
1
D6
D5
-
1
0
-
1
↑
1
-
I_RAD
J[1:0]
(11)
1
↑
1
-
-
-
0
↑
1
-
1
0
1
↑
1
-
-
-
1
1
1
1
1
1
↑
↑
↑
↑
↑
↑
1
1
1
1
1
1
-
-
-
-
-
SETOSC
SETPWCTR
SETDISPLAY
B4
SETCYC
B5
SETBGP
B6
SETVCOM
B9
SETEXTC
BB
↑
D7
SETOTP
1
↑
1
-
0
1
↑
↑
1
1
-
1
↑
1
-
1
↑
1
-
0
1
1
1
1
1
1
1
1
0
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
1
1
1
1
1
1
1
1
1
1
-
1
↑
1
-
1
1
0
1
1
1
0
1
1
1
0
1
1
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
1
1
1
1
1
1
1
1
1
1
1
1
1
-
1
↑
1
-
1
↑
1
-
1
1
↑
D4
D3
D2
D1
D0
1
1
0
0
0
0
-
N_RA
DJ[1:0
]
(10)
-
-
Function
Set internal
Oscillator
OSC_
EN
(0)
1
1
0
0
0
1
DP_S DP_S
TB
TB_S
(0)
(0)
BT[2:0](001)
VRH[5:0](01_1011)
Set power control
AP[2:0](011)
FS0[7:0](0000_0100)
FS1[7:0](0000_1000)
-
-
-
-
-
-
-
-
-
-
-
GAS VCOM
EN(1) G(0)
1
0
-
PON
STB
DK(1)
(0)
(1)
1
1
0
0
1
0
ISC[3:0] (0001)
PTG REF Set display
PT[1:0] (10) PTV[1:0](01)
(1)
(1) control
GON DTE
D[1:0] (00)
(1)
(0)
1
0
1
1
0
1
0
0
I_NW[2:0](000)
N_NW[2:0](001)
I_RTN[3:0](0000)
N_RTN[3:0](0100)
I_DIV[3:0](1111)
N_DIV[3:0](1111)
N_DUM[7:0] (0000_1100)
Set display cycle
I_DUM[7:0] (0000_1100)
GDON[7:0] (0000_1101)
GDOF[7:0] (0101_0011)
L_BASE[7:0](0101_1001)
1
0
1
1
0
1
0
1
DDVD
FBOF
H_TRI
VVDHS_SEL[3:0] (1011)
F(0)
Set power control
(0)
VREF[3:0] (1011)
VR_TRIM[3:0] (1000)
1
0
1
1
0
1
1
0
Set VCOM
VMF[7:0](1001_1110)
voltage
VMH[7:0](0110_1100)
VML[7:0](0101_0100)
1
0
1
1
1
0
0
1
Enter extension
EXTC1[7:0] (0000_0000)
EXTC2[7:0] (0000_0000)
command
EXTC3[7:0] (0000_0000)
1
0
1
1
1
0
1
1
Set OTP
OTP_MASK[7:0] (0000_0000)
OTP_INDEX[7:0] (0000_0000)
OTP_L DCCLK
OTP_ OTP_P OTP_E OTPTE
OTP_P
OAD_
_
VPP_S
WE
N
ST_EN
ROG(0
DISAB DISAB POR
EL(0)
(0)
(0)
(0)
(0)
)
LE
LE
(0)
(0)
-
-
OTP_PTM OTP_VRADJ
[1:0](00)
[1:0](00)
OTP_DATA[7:0] (0000_0000)
-
-
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.110Apr, 2010
HX8353-D
132RGB x 162 dots, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
(Hex)
C0
Operation
DNC NWR NRD D15-8
Code
SETSTBA
C3
SETID
C6
SETUADJ
SETCLOCK
D7
D6
1
0
1
1
1
1
1
↑
↑
↑
↑
↑
↑
1
1
1
1
1
1
-
1
1
↑
1
-
-
-
-
0
1
1
1
0
1
0
1
↑
↑
↑
↑
↑
↑
↑
↑
1
1
1
1
1
1
1
1
-
1
1
0
1
↑
1
0
↑
1
-
1
1
↑
1
-
-
0
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
CB
CC
SETPANEL
D0
GETHID
E0
E3
SETGAMMA
SETEQ
D5
-
1
-
1
1
D4
D3
D2
0
0
0
0
N_OPON[7:0] (0001_1000)
I_OPON[7:0] (0000_1000)
STBA[15:8] (0000_1100)
STBA[7:0] (1100_0100)
GENON[7:0] (0001_0000)
-
-
-
D1
D0
0
0
Function
Set Source option
-
OTPS
1B (0)
1
0
0
0
1
ID1[7:0] (0000_0000)
ID2[7:0] (1000_0000)
ID3[7:0] (0000_0000)
1
0
0
0
1
1
0
I_UADJ[2:0](011)
N_UADJ[2:0](001)
1
0
0
1
0
1
1
CADJ[3:0] (0010)
DCCL
K_SY
NC(1)
1
0
0
1
1
0
0
SS_P GS_P REV_ BGR_
ANEL ANEL PANE PANE
(0)
(0)
L(0)
L(0)
1
0
1
0
0
0
0
Dummy Read
Product ID[7:0] (0110_0100)
1
1
0
0
0
0
0
MP1[2:0](000)
MP0[2:0](000)
MP3[2:0](110)
MP2[2:0](101)
MP5[2:0](111)
MP4[2:0](001)
CP0[3:0](1010)
CP2[3:0](1111)
CP1[3:0](0111)
CP3[3:0](0001)
CP4[3:0](1100)
OP0[3:0](1111)
OP1[4:0](0_0000)
CGM1[1:0](11) CGM0[1:0](00)
MN1[2:0](101)
MN0[2:0](000)
MN3[2:0](010)
MN2[2:0](001)
MN5[2:0](111)
MN4[2:0](111)
CN0[3:0](1100)
CN2[3:0](1111)
CN1[3:0](0001)
CN3[3:0](0111)
CN4[3:0](1010)
ON0[3:0](0000)
ON1[4:0](0_1111)
1
1
0
0
0
1
1
EQVCI_M1[7:0] (0001_0000)
EQGND_M1[7:0](0000_1000)
EQVCI_M0[7:0](0000_1000)
EQGND_M0[7:0](0001_0000)
PREOE_M0[7:0](0000_0000)
PREOE_M1[7:0](0000_0000)
Set ID
Set UADJ to
trimming Freq
Set Panel
characteristics
Read Product ID
Set Gamma
Set EQ
Table 8.2 System Interface In-House Command Set
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.111Apr, 2010
HX8353-D
132RGB x 162 dots, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
8.2 Command description
8.2.1 NOP
00 H
Command
Parameter
Description
NOP (No Operation)
DNC NWR NRD D17-8 D7
D6
D5
D4
D3
D2
D1
D0
HEX
0
↑
1
0
0
0
0
0
0
0
0
00
NO PARAMETER
This command is an empty command; it does not have any effect on the display module.
However it can be used to terminate Frame Memory Write as described in RAMWR (Memory
Write) or RAMRD (Memory Read) command.
Restriction
Register
Availability
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In or Booster Off
Availability
Yes
Yes
Yes
Yes
Yes
Status
Power On Sequence
S/W Reset
H/W Reset
Default Value
N/A
N/A
N/A
Default
Flow Chart
-
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.112Apr, 2010
HX8353-D
132RGB x 162 dots, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
8.2.2 Software reset (01h)
01 H
Command
Parameter
Description
Restriction
Register
Availability
SWRESET (Software Reset)
DNC NWR NRD D17-8 D7
D6
D5
D4
D3
D2
D1
D0
HEX
0
↑
1
0
0
0
0
0
0
0
1
01
NO PARAMETER
When the Software Reset command is written, it causes a software reset. It resets the
commands and parameters to their S/W Reset default values. (See default tables in each
command description.)
The display is blank immediately.
Note: The GRAM contents are unaffected by this command.
It will be necessary to wait 5m sec before sending new command following software reset.
The display module loads all display suppliers’ factory default values to the registers during
this 5m sec.
If SW Reset is applied during Sleep Out mode, it will be necessary to wait 120m sec before
sending Sleep Out command.
SW Reset command cannot be sent during Sleep Out sequence.
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In or Booster Off
Availability
Yes
Yes
Yes
Yes
Yes
Status
Power On Sequence
S/W Reset
H/W Reset
Default Value
N/A
N/A
N/A
Default
Legend
Parameter
Flow Chart
Displa
y
Action
Mode
Sequential
transfer
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.113Apr, 2010
HX8353-D
132RGB x 162 dots, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
8.2.3 Read display identification information (04h)
04 H
Command
1st parameter
nd
2 parameter
rd
3 parameter
th
4 parameter
Description
Restriction
Register
Availability
RDDIDIF (Read Display Identification Information)
DNC NWR NRD D17-8 D7
D6
D5
D4
D3
D2
D1
D0
HEX
0
↑
1
0
0
0
0
0
1
0
0
04
1
1
↑
1
1
↑
ID17 ID16 ID15 ID14 ID13 ID12 ID11 ID10
1
1
↑
ID27 ID26 ID25 ID24 ID23 ID22 ID21 ID20
1
1
↑
ID37 ID36 ID35 ID34 ID33 ID32 ID31 ID30
This read byte returns 24-bit display identification information.
The 1st Parameter is dummy read. The 2nd ~ 4th Parameter identifies the LCD module’s
manufacturer.
It is defined by display supplier and it changes each time a revision is made to the display,
material or construction specifications. See Table:
ID Byte Value ID2[7:0]
Version
Changes
80h
81h
82h
83h
84h
85h
The 4th parameter identifies the LCD module/driver.
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In or Booster Off
Availability
Yes
Yes
Yes
Yes
Yes
Status
Power On Sequence
S/W Reset
H/W Reset
Default Value
See Description
See Description
See Description
Default
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.114Apr, 2010
HX8353-D
132RGB x 162 dots, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
Flow Chart
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.115Apr, 2010
HX8353-D
132RGB x 162 dots, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
8.2.4 Read display status (09h)
09 H
Command
1st parameter
nd
2 parameter
rd
3 parameter
th
4 parameter
th
5 parameter
Description
RDDST (Read Display Status)
DNC NWR NRD D17-8 D7
D6
D5
D4
D3
D2
D1
D0
HEX
0
↑
1
0
0
0
0
1
0
0
1
09
1
1
↑
1
1
↑
D31 D30 D29 D28 D27 D26 D25
0
1
1
↑
0
D22 D21 D20 D19 D18 D17 D16
1
1
↑
D15
0
D13
0
0
D10
D9
D8
1
1
↑
D7
D6
D5
D4
D3
D2
D1
0
This command indicates the current status of the display as described in the table below:
Bit
Description
D31
Booster Voltage Status
D30
Page Address Order (MY)
D29
Column Address Order (MX)
D28
Page/Column Order (MV)
D27
Line Address Order (ML)
D26
RGB/BGR Order
D25
Display Data Latch Order
D24
Switching between Segment outputs and RAM
D23
Switching between Common outputs and RAM
D22
Interface Color Pixel Format Definition
D21
D20
D19
Idle Mode On/Off
D18
Partial Mode On/Off
D17
Sleep In/Out
D16
Display Normal Mode On/Off
D15
Vertical Scrolling Status
D14
Horizontal Scrolling Status
D13
Inversion Status
D12
All Pixels On
D11
All Pixels Off
D10
Display On/Off
D9
Tearing Effect Line On/Off
D8
Gamma Curve Selection
D7
D6
D5
Tearing Effect Output Line Mode
D4
Horizontal Sync. (HS, RGB I/F)
D3
Vertical Sync. (VS,RGB I/F)
D2
Pixel Clock (DOTCLK,RGB I/F))
D1
Data Enable (DE,RGB I/F)
D0
Parity Error
Bit Values are explained overleaf.
Bit D31 – Booster Voltage Status
‘0’ = Booster Off or has a fault.
‘1’ = Booster On and working OK.
Bit D30 – Page Address Order
‘0’ = Top to Bottom (When MADCTL B7(MY) = ’0’).
‘1’ = Bottom to Top (When MADCTL B7(MY) =’1’).
Bit D29 – Column Address Order
‘0’ = Left to Right (When MADCTL B6(MX) = ’0’).
‘1’ = Right to Left (When MADCTL B6(MX) = ’1’).
Bit D28 –Page / Column Order
‘0’ = Normal Mode (When MADCTL B5(MV) = ’0’).
Comment
Set to ‘0’
Set to ‘0’
Set to ‘0’
Set to ‘0’
Set to ‘0’
Set to ‘0’
Set to ‘0’
Set to ‘0’
Set to ‘0’
Set to ‘0’
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.116Apr, 2010
HX8353-D
132RGB x 162 dots, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
‘1’ = Reverse Mode (When MADCTL B5(MV) = ’1’).
Bit D27 – Line Address Order
‘0’ = LCD Refresh Top to Bottom (When MADCTL B4(ML) = ’0’).
‘1’ = LCD Refresh Bottom to Top (When MADCTL B4(ML) = ’1’).
Bit D26 – RGB/BGR Order
‘0’ = RGB (When MADCTL B3 = ’0’).
‘1’ = BGR (When MADCTL B3 = ’1’).
Bit D25 – Display Data Latch Order
‘0’ = LCD Refresh Left to Right (When MADCTL B2 = ’0’).
‘1’ = LCD Refresh Right to Left (When MADCTL B2 = ’1’).
Note : For bits D27, D26 and D25 also refer to 8.3.29 Memory Access Control (R36h)
Bit D24 – Switching Between Segment Outputs and RAM
This bit is not applicable for this project, so it is set to ‘0’.
Bit D23 – Switching Between Common Outputs and RAM
This bit is not applicable for this project, so it is set to ‘0’.
Bits D22, D21, D20 –Interface Color Pixel Format Definition
Interface Format
D22
D21
D20
Not Defined
0
0
0
Not Defined
0
0
1
Not Defined
0
1
0
12 bit/pixel
0
1
1
Not Defined
1
0
0
16 bit/pixel
1
0
1
18 bit/pixel
1
1
0
Not Defined
1
1
1
Bit D19 – Idle Mode On/Off
‘0’ = Idle Mode Off.
‘1’ = Idle Mode On.
Bit D18 – Partial Mode On/Off
‘0’ = Partial Mode Off.
‘1’ = Partial Mode On.
Bit D17 – Sleep In/Out
‘0’ = Sleep In Mode.
‘1’ = Sleep Out Mode.
Bit D16 – Display Normal Mode On/Off
‘0’ = Display Normal Mode Off.
‘1’ = Display Normal Mode On.
Bit D15 – Vertical Scrolling On/Off
‘0’ = Vertical Scrolling is Off.
‘1’ = Vertical Scrolling is On.
Bit D14 – Horizontal Scrolling Status
This bit is not applicable for this project, so it is set to ‘0’.
Bit D13 – Inversion On/Off
‘0’ = Inversion is Off.
‘1’ = Inversion is On.
Bit D12 – All Pixels On
This bit is not applicable for this project, so it is set to ‘0’.
Bit D11 – All Pixels Off
This bit is not applicable for this project, so it is set to ‘0’.
Bit D10 – Display On/Off
‘0’ = Display is Off.
‘1’ = Display is On.
Bit D9 – Tearing Effect Line On/Off
‘0’ =Tearing Effect Line Off.
‘1’ = Tearing Effect On.
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.117Apr, 2010
HX8353-D
132RGB x 162 dots, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
Bits D8, D7, D6 – Gamma Curve Selection
Gamma Curve Selected
B8 B7 B6
Gamma Curve 1
0
0
0
Gamma Curve 2
0
0
1
Gamma Curve 3
0
1
0
Gamma Curve 4
0
1
1
Not Defined
1
0
0
Not Defined
1
0
1
Not Defined
1
1
0
Not Defined
1
1
1
Gamma Set (26h) Parameter
GC0
GC1
GC2
GC3
Not Defined
Not Defined
Not Defined
Not Defined
Bit D5 – Tearing Effect Line Output Mode.
‘0’ = Mode 1, V-Blanking only.
‘1’ = Mode 2, both H-Blanking and V-Blanking.
Bit D4 – Horizontal Sync. (HS) RGB I/F On/Off, Note
This bit is not applicable for this project, so it is set to ‘0’.
Bit D3 – Vertical Sync. (VS) RGB I/F On/Off, Note
This bit is not applicable for this project, so it is set to ‘0’.
Bit D2 – Pixel Clock (DOTCLK) RGB I/F On/Off, Note
This bit is not applicable for this project, so it is set to ‘0’.
Bit D1 – Data Enable (DE) RGB I/F On/Off, Note
This bit is not applicable for this project, so it is set to ‘0’.
Bit D0 – Parity Error
This bit is not applicable for this project, so it is set to ‘0’.
Restriction
Register
Availability
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In or Booster Off
Availability
Yes
Yes
Yes
Yes
Yes
Status
Power On Sequence
S/W Reset
H/W Reset
Default Value
See Description
See Description
See Description
Default
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.118Apr, 2010
HX8353-D
132RGB x 162 dots, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
Flow Chart
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.119Apr, 2010
HX8353-D
132RGB x 162 dots, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
8.2.5 Read display power mode (0Ah)
0A H
RDDPM (Read Display Power Mode)
DNC NWR NRD D15-8 D7
D6
D5
D4
D3
D2
D1
D0
HEX
Command
0
↑
1
0
0
0
0
1
0
1
0
0A
st
1 parameter
1
1
↑
nd
2 parameter 1
1
↑
D7
D6
D5
D4
D3
D2
0
0
xx
This command indicates the current status of the display as described in the table below:
Description
Restrictions
Register
Availability
Bit
Description
Comment
D7
Booster Voltage Status
D6
Idle Mode On/Off
D5
Partial Mode On/Off
D4
Sleep In/Out
D3
Display Normal Mode On/Off
D2
Display On/Off
D1
Not Defined
Set to ‘0’
D0
Not Defined
Set to ‘0’
Bit D7 – Booster Voltage Status
‘0’ = Booster Off or has a fault.
‘1’ = Booster On and working OK (Meets display supplier’s optical requirements).
Bit D6 – Idle Mode On/Off
‘0’ = Idle Mode Off.
‘1’ = Idle Mode On.
Bit D5 – Partial Display Mode On/Off
‘0’ = Partial Mode Off.
‘1’ = Partial Mode On.
Bit D4 – Sleep In/Out
‘0’ = Sleep In Mode.
‘1’ = Sleep Out Mode.
Bit D3 – Normal Display Mode On/Off
‘0’ = Display Normal Mode Off.
‘1’ = Display Normal Mode On.
Bit D2 – Display On/Off
‘0’ = Display is Off.
‘1’ = Display is On.
Bit D1 – Not Defined
This bit is not applicable for this project, so it is set to ‘0’.
Bit D0 – Not Defined
This bit is not applicable for this project, so it is set to ‘0’.
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In or Booster Off
Availability
Yes
Yes
Yes
Yes
Yes
Status
Power On Sequence
S/W Reset
H/W Reset
Default Value
08h
08h
08h
Default
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.120Apr, 2010
HX8353-D
132RGB x 162 dots, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
Flow Chart
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.121Apr, 2010
HX8353-D
132RGB x 162 dots, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
8.2.6 Read display MADCTL (0Bh)
0B H
Command
st
1 parameter
nd
2 parameter
RDDMADCTL (Read Display MADCTL)
DNC NWR NRD D15-8 D7
D6
D5
D4
D3
D2
D1
D0
0
↑
1
0
0
0
0
1
0
1
1
1
1
↑
1
1
↑
D7
D6
D5
D4
D3
D2
0
0
This command indicates the current status of the display as described in the table below:
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Description
Description
Page Address Order
Column Address Order
Page/Column Order
Line Address Order
RGB/BGR Order
Display Data Latch Order
Switching between Segment outputs and RAM
Switching between Common outputs and RAM
HEX
0B
xx
Comment
Set to ‘0’
Set to ‘0’
Bit D7 – Page Address Order
‘0’ = Top to Bottom (When MADCTL B7(MY) = ’0’).
‘1’ = Bottom to Top (When MADCTL B7(MY) =’1’).
Bit D6 – Column Address Order
‘0’ = Left to Right (When MADCTL B6(MX) = ’0’).
‘1’ = Right to Left (When MADCTL B6(MX) = ’1’).
Bit D5 –Page / Column Order
‘0’ = Normal Mode (When MADCTL B5(MV) = ’0’).
‘1’ = Reverse Mode (When MADCTL B5(MV) = ’1’).
Bit D4 – Line Address Order
‘0’ = LCD Refresh Top to Bottom (When MADCTL B4(ML) = ’0’).
‘1’ = LCD Refresh Bottom to Top (When MADCTL B4(ML) = ’1’).
Bit D3 – RGB/BGR Order
‘0’ = RGB (When MADCTL B3 = ’0’).
‘1’ = BGR (When MADCTL B3 = ’1’).
Note: For bits D4, D3 and D2 also refer to 8.2.29 Memory Access Control (R36h)
Restrictions
Register
Availability
Bit D2 – Display Data Latch Order
Display Data Latch Data Order
‘0’ = LCD Refresh Left to Right (When MADCTL B2=’0’).
‘1’ = LCD Refresh Right to Left (When MADCTL B2=’1’).
Bit D1 – Switching Between Segment Outputs and RAM
This bit is not applicable for this project, so it is set to ‘0’.
Bit D0 – Switching Between Common Outputs and RAM
This bit is not applicable for this project, so it is set to ‘0’.
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In or Booster Off
Availability
Yes
Yes
Yes
Yes
Yes
Status
Power On Sequence
S/W Reset
H/W Reset
Default Value
00h
No Change
00h
Default
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.122Apr, 2010
HX8353-D
132RGB x 162 dots, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
Flow Chart
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.123Apr, 2010
HX8353-D
132RGB x 162 dots, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
8.2.7 Read display pixel format (0Ch)
0C H
Command
st
1 parameter
nd
2 parameter
RDDCOLMOD (Read Display COLMOD)
DNC NWR NRD D15-8 D7
D6
0
↑
1
0
0
1
1
↑
1
1
↑
0
D6
D5
0
D5
D4
0
D4
D3
1
0
D2
1
D2
D1
0
D1
D0
0
D0
HEX
0C
xx
This command indicates the current status of the display as described in the table below:
Bit
Description
Comment
D7
Set to ‘0’
D6
Set to ‘0’
RGB Interface Color Format
D5
Set to ‘0’
D4
Set to ‘0’
D3
Set to ‘0’
D2
System Interface Color Format
D1
D0
Bit D7 – RGB Interface Color Format Selection
This bit is not applicable for this project, so it is set to ‘0’.
Bits D6, D5, D4 – RGB Interface Color Pixel Format Definition
These bits are not applicable for this project, so they are set to ‘0’s.
Description
Bit D3 – System Interface Color Format Selection
This bit is not applicable for this project, so it is set to ‘0’.
Bit D2, D1, D0 – Control Interface Color Pixel Format Definition.
See section“8.2.33 Interface Pixel Format (R3Ah)”.
System Interface Color Format
Not Defined
Not Defined
Not Defined
Not Defined
Not Defined
16 bit/pixel
18 bit/pixel
Not Defined
Restrictions
Register
Availability
D2
0
0
0
0
1
1
1
1
D1
0
0
1
1
0
0
1
1
D0
0
1
0
1
0
1
0
1
-
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In or Booster Off
Availability
Yes
Yes
Yes
Yes
Yes
Status
Power On Sequence
S/W Reset
H/W Reset
Default Value
18-bit/pixel
No Change
18-bit/pixel
Default
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.124Apr, 2010
HX8353-D
132RGB x 162 dots, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
Flow Chart
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.125Apr, 2010
HX8353-D
132RGB x 162 dots, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
8.2.8 Read display image mode (0Dh)
0D H
Command
st
1 parameter
nd
2 parameter
RDDIM (Read Display Image Mode)
DNC NWR NRD D15-8 D7
0
↑
1
0
1
1
↑
1
1
↑
D7
D6
0
0
D5
0
D5
D4
0
0
D3
1
0
D2
1
D2
D1
0
D1
D0
1
D0
HEX
0D
xx
Description
This command indicates the current status of the display as described in the table below:
Bit D7 – Vertical Scrolling On/Off
‘0’ = Vertical Scrolling is Off.
‘1’ = Vertical Scrolling is On.
Bit D6 – Horizontal Scrolling Status
This bit is not applicable for this project, so it is set to ‘0’
Bit D5 – Inversion On/Off
‘0’ = Inversion is Off.
‘1’ = Inversion is On.
This bit is not applicable for this project, so it is set to ‘0’
Bit D4 – All Pixels On
This bit is not applicable for this project, so it is set to ‘0’
Bit D3 – All Pixels Off
This bit is not applicable for this project, so it is set to ‘0’
Bits D2, D1, D0 – Gamma Curve Selection
Gamma Curve Selected
D2 D1 D0 Gamma Set (R26h) Parameter
Gamma Curve 1
0
0
0
GC0
Gamma Curve 2
0
0
1
GC1
Gamma Curve 3
0
1
0
GC2
Gamma Curve 4
0
1
1
GC3
Not Defined
1
0
0
Not Defined
Not Defined
1
0
1
Not Defined
Not Defined
1
1
0
Not Defined
Not Defined
1
1
1
Not Defined
Restrictions
-
Register
Availability
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In or Booster Off
Availability
Yes
Yes
Yes
Yes
Yes
Status
Power On Sequence
S/W Reset
H/W Reset
Default Value
00h
00h
00h
Default
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.126Apr, 2010
HX8353-D
132RGB x 162 dots, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
Flow Chart
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.127Apr, 2010
HX8353-D
132RGB x 162 dots, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
8.2.9 Read display signal mode (0Eh)
0E H
Command
st
1 parameter
nd
2 parameter
Description
Restrictions
Register
Availability
RDDSM (Read Display Signal Mode)
DNC NWR NRD D15-8 D7
D6
D5
D4
D3
D2
D1
D0 HEX
0
↑
1
0
0
0
0
1
1
1
0
0E
1
1
↑
1
1
↑
D7
D6
D5
D4
D3
D2
0
0
xx
This command indicates the current status of the display as described in the table below:
Bit D7 – Tearing Effect Line On/Off
‘0’ = Tearing Effect Line Off.
‘1’ = Tearing Effect On.
Bit D6 – Tearing Effect Line Output Mode, see section 7.3 for mode definitions.
‘0’ = Mode 1.
‘1’ = Mode 2.
Bit D5 – Horizontal Sync. (VSYNC, RGB I/F) On/Off
This bit is not applicable for this project, so it is set to ‘0’
Bit D4 – Vertical Sync. (HSYNC, RGB I/F) On/Off
This bit is not applicable for this project, so it is set to ‘0’
Bit D3 – Pixel Clock (DCLK, RGB I/F) On/Off
This bit is not applicable for this project, so it is set to ‘0’
Bit D2 – Data Enable (ENABLE, RGB I/F)) On/Off
This bit is not applicable for this project, so it is set to ‘0’
D1 are D0 - are for future use and are set to ‘0’.
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In or Booster Off
Default
Status
Power On Sequence
S/W Reset
H/W Reset
Availability
Yes
Yes
Yes
Yes
Yes
Default Value
00h
00h
00h
Flow Chart
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.128Apr, 2010
HX8353-D
132RGB x 162 dots, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
8.2.10 Read display self-diagnostic result (0Fh)
0F H
Command
st
1 parameter
nd
2 parameter
Description
Restrictions
Register
Availability
RDDSDR (Read Display Self-Diagnostic Result)
DNC NWR NRD D15-8 D7
D6
D5
D4
D3
D2
D1
0
↑
1
0
0
0
0
1
1
1
1
1
↑
1
1
↑
D7
D6
D5
D4
0
0
0
This command indicates the status of the display self-diagnostic results after
Sleep Out -command as described in the table below:
Bit D7 – Register Loading Detection
See section 7.6.1.
Bit D6 – Functionality Detection
See section 7.6.2.
Bit D5 – Chip Attachment Detection
Set bit D5 to ‘0’, if this function is not implemented.
Bit D4 – Display Glass Break Detection
Set bit D4 to ‘0’, if this function is not implemented.
Bits D3, D2, D1 and D0 are for future use and are set to ‘0’.
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In or Booster Off
Default
Status
Power On Sequence
S/W Reset
H/W Reset
D0
1
0
HEX
0F
-
Availability
Yes
Yes
Yes
Yes
Yes
Default Value
00h
00h
00h
Flow Chart
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.129Apr, 2010
HX8353-D
132RGB x 162 dots, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
8.2.11 Sleep in (10h)
10 H
Command
Parameter
SLPIN (Sleep In)
DNC NWR NRD D15-8 D7
D6
D5
D4
D3
D2
D1
D0 HEX
0
↑
1
0
0
0
1
0
0
0
0
10
NO PARAMETER
This command causes the LCD module to enter the minimum power consumption mode.
In this mode the DC/DC converter is stopped, Internal oscillator is stopped, and panel
scanning is stopped.
Description
Restriction
Register
Availability
MCU interface and memory are still working and the memory keeps its contents.
This command has no effect when module is already in sleep in mode. Sleep In Mode can
only be left by the Sleep Out Command (11h).
It will be necessary to wait 5msec before sending next command, this is to allow time
for the supply voltages and clock circuits to stabilize.
It will be necessary to wait 120msec after sending Sleep Out command (when in Sleep
In Mode) before Sleep In command can be sent.
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In or Booster Off
Default
Status
Power On Sequence
S/W Reset
H/W Reset
Availability
Yes
Yes
Yes
Yes
Yes
Default Value
Sleep In Mode
Sleep In Mode
Sleep In Mode
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.130Apr, 2010
HX8353-D
132RGB x 162 dots, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
It takes 120msec to get into Sleep In mode after SLPIN command issued.
Flow Chart
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.131Apr, 2010
HX8353-D
132RGB x 162 dots, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
8.2.12 Sleep out (11h)
11 H
Command
Parameter
SLPOUT (Sleep Out)
DNC NWR NRD D15-8 D7
D6
D5
D4
D3
D2
D1
D0 HEX
0
↑
1
0
0
0
1
0
0
0
1
11
NO PARAMETER
This command turns off sleep mode.
In this mode the DC/DC converter is enabled, Internal oscillator is started, and panel
scanning is started.
Description
Restriction
Register
Availability
This command has no effect when module is already in sleep out mode. Sleep Out
Mode can only be left by the Sleep In Command (10h).
It will be necessary to wait 5msec before sending next command, this is to allow time
for the supply voltages and clock circuits to stabilize.
The display module loads all display suppliers’ factory default values to the registers
during this 5msec and there cannot be any abnormal visual effect on the display image.
If factory default and register values are same when this load is done and when the
display module is already Sleep Out –mode.
The display module is doing self-diagnostic functions during this 5msec.
It will be necessary to wait 120msec after sending Sleep In command (when in Sleep
Out mode) before Sleep Out command can be sent.
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In or Booster Off
Default
Status
Power On Sequence
S/W Reset
H/W Reset
Availability
Yes
Yes
Yes
Yes
Yes
Default Value
Sleep In Mode
Sleep In Mode
Sleep In Mode
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.132Apr, 2010
HX8353-D
132RGB x 162 dots, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
It takes 120msec to become Sleep Out mode after SLPOUT command issued.
SLPOUT
Legend
Start Internal
Oscillator
Flow Chart
Start
DC-DC
Converter
Command
Display whole blank
screen for 2 frames
(Automatic No effect to
DISP ON/OFF
Commands)
Parameter
Display
Action
Mode
Charge Offset
voltage for LCD
Panel
Display Memory
contents in accordance
with the current
command table settings
Sequential
transfer
Sleep Out Mode
Himax Confidential
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in whole or in part without prior written permission of Himax.
-P.133Apr, 2010
HX8353-D
132RGB x 162 dots, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
8.2.13 Partial mode on (12h)
12 H
Command
Parameter
Description
Restrictions
Register
Availability
PTLON (Partial Mode On)
DNC NWR NRD D15-8 D7
D6
D5
D4
D3
D2
D1
D0 HEX
0
↑
1
0
0
0
1
0
0
1
0
12
NO PARAMETER
This command turns on partial mode The partial mode window is described by the Partial
Area command (30H). To leave Partial mode, the Normal Display Mode On command
(13H) should be written.
See also section 6.3.8
This command has no effect when Partial mode is active.
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In or Booster Off
Status
Power On Sequence
S/W Reset
H/W Reset
Default
Flow Chart
Availability
Yes
Yes
Yes
Yes
Yes
Default Value
Normal Display Mode On
Normal Display Mode On
Normal Display Mode On
See Partial Area (30h)
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.134Apr, 2010
HX8353-D
132RGB x 162 dots, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
8.2.14 Normal display mode on (13h)
13 H
Command
Parameter
Description
Restriction
NORON (Normal Display Mode On)
DNC NWR NRD D15-8 D7
D6
D5
D4
D3
D2
D1
D0 HEX
0
↑
1
0
0
0
1
0
0
1
1
13
NO PARAMETER
This command returns the display to normal mode. Normal display mode on means
Partial mode off, Scroll mode Off.
See also section 6.2.1.
This command has no effect when Normal mode is active.
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In or Booster Off
Register
Availability
Status
Power On Sequence
S/W Reset
H/W Reset
Default
Flow Chart
Availability
Yes
Yes
Yes
Yes
Yes
Default Value
Normal Display Mode On
Normal Display Mode On
Normal Display Mode On
See Partial Area and Vertical Scrolling Definition Descriptions for details of when to use this
command.
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.135Apr, 2010
HX8353-D
132RGB x 162 dots, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
8.2.15 Display inversion off (20h)
20 H
Command
Parameter
INVOFF (Display Inversion Off)
DNC NRD NWR D15-8 D7
D6
D5
D4
D3
D2
0
1
↑
0
0
1
0
0
0
NO PARAMETER
This command is used to recover from display inversion mode.
This command makes no change of contents of frame memory.
This command does not change any other status.
D1
0
D0
0
HEX
20
Description
Restriction
-
Register
Availability
Default
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In or Booster Off
Status
Power On Sequence
S/W Reset
H/W Reset
Availability
Yes
Yes
Yes
Yes
Yes
Default Value
Display Inversion Off
Display Inversion Off
Display Inversion Off
Flow Chart
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.136Apr, 2010
HX8353-D
132RGB x 162 dots, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
8.2.16 Display inversion on (21h)
21 H
Command
Parameter
INVON (Display Inversion On)
DNC NRD NWR D15-8 D7
D6
D5
D4
D3
D2
D1
D0 HEX
0
1
↑
0
0
1
0
0
0
0
1
21
NO PARAMETER
This command is used to enter into display inversion mode.
This command makes no change of contents of frame memory. Every bit is inverted
from the frame memory to the display.
This command does not change any other status.
Description
Restriction
Register
Availability
Default
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In or Booster Off
Status
Power On Sequence
S/W Reset
H/W Reset
Availability
Yes
Yes
Yes
Yes
Yes
Default Value
Display Inversion Off
Display Inversion Off
Display Inversion Off
Flow Chart
Himax Confidential
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in whole or in part without prior written permission of Himax.
-P.137Apr, 2010
HX8353-D
132RGB x 162 dots, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
8.2.17 Gamma set (26h)
26 H
Command
Parameter
GAMSET (Gamma Set)
D6
D5
D4
D3
D2
D1
D0 HEX
DNC NWR NRD D15-8 D7
0
↑
1
0
0
1
0
0
1
1
0
26
1
↑
1
GC7 GC6 GC5 GC4 GC3 GC2 GC1 GC0
This command is used to select the desired Gamma curve for the current display. A
maximum of 4 fixed gamma curves can be selected. The curve is selected by setting the
appropriate bit in the parameter as described in the table:
GC[7..0]
01h
02h
04h
08h
Description
Parameter
GC0
GC1
GC2
GC3
Curve Selected
Gamma Curve 1
Gamma Curve 2
Gamma Curve 3
Gamma Curve 4
Note: All other values are undefined.
Restriction
Register
Availability
Values of GC[7..0] not shown in table above are invalid and will not change the
Current selected Gamma curve until valid value is received.
Status
Availability
Normal Mode On, Idle Mode Off, Sleep Out
Yes
Normal Mode On, Idle Mode On, Sleep Out
Yes
Partial Mode On, Idle Mode Off, Sleep Out
Yes
Partial Mode On, Idle Mode On, Sleep Out
Yes
Sleep In or Booster Off
Yes
Default
Status
Power On Sequence
S/W Reset
H/W Reset
Default Value
01h
01h
01h
Legend
GAMSET
Command
Parameter
Flow Chart
GC [7:0]
Display
Action
New Gamma
Mode
Curve Loaded
Sequential
transfer
Himax Confidential
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in whole or in part without prior written permission of Himax.
-P.138Apr, 2010
HX8353-D
132RGB x 162 dots, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
8.2.18 Display off (28h)
28 H
Command
Parameter
DISPOFF (Display Off)
DNC NWR NRD D15-8 D7
D6
D5
D4
D3
D2
D1
D0 HEX
0
↑
1
0
0
1
0
1
0
0
0
28
NO PARAMETER
This command is used to enter into DISPLAY OFF mode. In this mode, the output from
Frame Memory is disabled and blank page inserted.
This command makes no change of contents of frame memory.
This command does not change any other status.
There will be no abnormal visible effect on the display.
Description
Restriction
Register
Availability
This command has no effect when module is already in display off mode.
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In or Booster Off
Default
Status
Power On Sequence
S/W Reset
H/W Reset
Availability
Yes
Yes
Yes
Yes
Yes
Default Value
Display Off
Display Off
Display Off
Flow Chart
Himax Confidential
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in whole or in part without prior written permission of Himax.
-P.139Apr, 2010
HX8353-D
132RGB x 162 dots, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
8.2.19 Display on (29h)
29 H
DISPON (Display On)
D6
D5
D4
D3
D2
D1
D0 HEX
DNC NWR NRD D15-8 D7
Command
0
↑
1
0
0
1
0
1
0
0
1
29
Parameter NO PARAMETER
This command is used to recover from DISPLAY OFF mode. Output from the Frame
Memory is enabled.
This command makes no change of contents of frame memory.
This command does not change any other status.
Description
Restriction
Register
Availability
This command has no effect when module is already in display on mode.
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In or Booster Off
Default
Status
Power On Sequence
S/W Reset
H/W Reset
Availability
Yes
Yes
Yes
Yes
Yes
Default Value
Display Off
Display Off
Display Off
Flow Chart
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.140Apr, 2010
HX8353-D
132RGB x 162 dots, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
8.2.20 Column address set (2Ah)
2A H
Command
1st parameter
2nd parameter
3rd parameter
4th parameter
CASET (Column Address Set)
DNC NWR NRD D15-8 D7
D6
D5
D4
D3
D2
D1
D0
HEX
0
↑
1
0
0
1
0
1
0
1
0
2A
1
↑
1
SC15 SC14 SC13 SC12 SC11 SC10 SC9 SC8
Note
1
↑
1
SC7 SC6 SC5 SC4 SC3 SC2 SC1 SC0
1
↑
1
EC15 EC14 EC13 EC12 EC11 EC10 EC9 EC8
Note
1
↑
1
EC7 EC6 EC5 EC4 EC3 EC2 EC1 EC0
This command is used to define area of frame memory where MCU can access.
This command makes no change on the other driver status.
The values of SC[15:0] and EC[15:0] are referred when RAMWR command comes. Each
value represents one column line in the Frame Memory.
Description
SC[15:0] always must be equal to or less than EC[15:0]
Restriction
Note: When SC[15:0] or EC[15:0] is greater than maximum address like below, data out of range
will be ignored
0000h<=SC[15:0]<=EC[15:0] <=0083h ,when MADCTL’s B5=0
0000h<=SC[15:0]<=EC[15:0] <=00A1h ,when MADCTL’s B5=1
Register
Availability
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In or Booster Off
Status
Power On Sequence
Default
S/W Reset
H/W Reset
Availability
Yes
Yes
Yes
Yes
Yes
Default Value
SC[15:0]=0000h
EC[15:0]=0083h
When MADCTL’s B5=0:
SC[15:0]=0000h
EC[15:0]=0083h
When MADCTL’s B5=1:
SC[15:0]=0000h
EC[15:0]=00A1h
SC[15:0]=0000h
EC[15:0]=0083h
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.141Apr, 2010
HX8353-D
132RGB x 162 dots, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
Flow Chart
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.142Apr, 2010
HX8353-D
132RGB x 162 dots, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
8.2.21 Page address set (2Bh)
2B H
Command
1st parameter
2nd parameter
3rd parameter
4th parameter
PASET (Page Address Set)
DNC NWR NRD D15-8 D7
D6
D5
D4
D3
D2
D1
D0
HEX
0
↑
1
0
0
1
0
1
0
1
1
2B
1
↑
1
SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8
Note
1
↑
1
SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0
1
↑
1
EP15 EP14 EP13 EP12 EP11 EP10 EP9 EP8
Note
1
↑
1
EP7 EP6 EP5 EP4 EP3 EP2 EP1 EP0
This command is used to define area of frame memory where MCU can access.
This command makes no change on the other driver status.
The values of SP[15:0] and EP[15:0] are referred when RAMWR command comes.
Each value represents one Page line in the Frame Memory.
Description
SP[15:0] always must be equal to or less than EP[15:0]
Restriction
Note: When SP[15:0] or EP[15:0] is greater than maximum row address like below, data of out of
range will be ignored
0000h<=SP[15:0]<=EP[15:0]<=00A1h (When MADCTL’s B5=0)
0000h<=SP[15:0]<=EP[15:0]<=0083h (When MADCTL’s B5=1)
Register
Availability
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In or Booster Off
Status
Power On Sequence
Default
S/W Reset
H/W Reset
Availability
Yes
Yes
Yes
Yes
Yes
Default Value
SP[15:0]=0000h
EP[15:0]=00A1h
When MADCTL’s B5=0:
SP[15:0]=0000h
EP[15:0]=00A1h
When MADCTL’s B5=1:
SP[15:0]=0000h
EP[15:0]=0083h
SP[15:0]=0000h
EP[15:0]=00A1h
Himax Confidential
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in whole or in part without prior written permission of Himax.
-P.143Apr, 2010
HX8353-D
132RGB x 162 dots, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
CASET
nd
parameter SC [15:0]
parameter EC [15:0]
IF Needed
st
1 &2
rd
th
3 &4
Legend
Command
Parameter
RASET
Display
Action
st
nd
parameter SP [15:0]
rd
th
parameter EP [15:0]
1 &2
Flow Chart
3 &4
Mode
Sequential
transfer
RAMWR
D1[17:0],D2[17:0],
...,Dn[17:0]
IF Needed
Image Data
Any Command
Himax Confidential
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in whole or in part without prior written permission of Himax.
-P.144Apr, 2010
HX8353-D
132RGB x 162 dots, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
8.2.22 Memory write (2Ch)
2C H
Command
1st parameter
:
nth parameter
RAMWR (Memory Write)
DNC NWR NRD D15-8
0
↑
1
1
↑
1
1
↑
1
1
↑
1
D7
0
D6
0
D5
1
D4
D3
0
1
D1[15:0]
Dx[15:0]
Dn[15:0]
D2
1
D1
0
D0
0
HEX
2C
00..FF
00..FF
00..FF
Description
This command is used to transfer data from MCU to frame memory.
This command makes no change to the other driver status.
When this command is accepted, the column register and the page register are reset to
the Start Column/Start Page positions.
The Start Column/Start Page positions are different in accordance with MADCTL setting.
(See 6.2)
Then D[7:0] is stored in frame memory and the column register and the page register
incremented.
Sending any other command can stop frame Write.
Restriction
In all color modes, there is no restriction on length of parameters.
Register
Availability
Default
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In or Booster Off
Status
Power On Sequence
S/W Reset
H/W Reset
Availability
Yes
Yes
Yes
Yes
Yes
Default Value
Contents of memory is set randomly
Contents of memory is not cleared
Contents of memory is not cleared
Flow Chart
Himax Confidential
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in whole or in part without prior written permission of Himax.
-P.145Apr, 2010
HX8353-D
132RGB x 162 dots, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
8.2.23 Color set (2Dh)
2D H
Command
1st parameter
:
th
32 parameter
33rd parameter
:
th
96 parameter
th
97 parameter
:
128th parameter
Description
Restriction
Register
Availability
RGBSET (Color Set)
DNC NRD NWR DB7 DB6 DB5
DB4
DB3
DB2
DB1
DB0
HEX
0
1
↑
0
0
1
0
1
1
0
1
2D
1
1
↑
X
X
R005 R004 R003 R002 R001 R000 00..FF
1
1
↑
X
X
Rnn5 Rnn4 Rnn3 Rnn2 Rnn1 Rnn0 00..FF
1
1
↑
X
X
R315 R314 R313 R312 R311 R310 00..FF
1
1
↑
X
X
G005 G004 G003 G002 G001 G000 00..FF
1
1
↑
X
X
Gnn5 Gnn4 Gnn3 Gnn2 Gnn1 Gnn0 00..FF
1
1
↑
X
X
G635 G634 G633 G632 G631 G630 00..FF
1
1
↑
X
X
B005 B004 B003 B002 B001 B000 00..FF
1
1
↑
X
X
Bnn5 Bnn4 Bnn3 Bnn2 Bnn1 Bnn0 00..FF
1
1
↑
X
X
B315 B314 B313 B312 B311 B310 00..FF
This command is used to define the LUT for 12bit-to-18bit/16bit-to-18bit color depth
conversions. (See also section 5.2) 128 bytes must be written to the LUT regardless of the
color mode. This command has no effect on other commands/parameters and Contents of
frame memory. Visible change takes effect next time the Frame Memory is written to.
Status
Availability
Normal Mode On, Idle Mode Off, Sleep Out
Yes
Normal Mode On, Idle Mode On, Sleep Out
Yes
Partial Mode On, Idle Mode Off, Sleep Out
Yes
Partial Mode On, Idle Mode On, Sleep Out
Yes
Sleep In or Booster Off
Yes
Default
Status
Power On Sequence
S/W Reset
H/W Reset
Default Value
Random values
Contents of the look-up table protected
Random values
Flow Chart
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.146Apr, 2010
HX8353-D
132RGB x 162 dots, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
8.2.24 Memory read (2Eh)
2E H
Command
1st parameter
2nd parameter
:
(n+1)th
parameter
Description
Restriction
Register
Availability
RAMRD (Memory Read)
DNC NWR NRD D15-8
0
↑
1
1
↑
1
-
D7
0
-
D6
0
-
D5
1
-
1
↑
1
1
↑
1
D4
D3
0
1
D1[15:0]
Dx[15:0]
1
↑
1
Dn[15:0]
D2
1
-
D1
1
-
D0
0
-
HEX
2E
00..FF
00..FF
00..FF
This command is used to transfer data from frame memory to MCU. This command makes
no change to the other driver status.
When this command is accepted, the column register and the page register are reset to the
Start Column/Start Page positions.
The Start Column/Start Page positions are different in accordance with MADCTL setting.
(See 6.2)
Then D[7:0] is read back from the frame memory and the column register and the page
register incremented
Frame Read can be stopped by sending any other command.
Status
Availability
Normal Mode On, Idle Mode Off, Sleep Out
Yes
Normal Mode On, Idle Mode On, Sleep Out
Yes
Partial Mode On, Idle Mode Off, Sleep Out
Yes
Partial Mode On, Idle Mode On, Sleep Out
Yes
Sleep In or Booster Off
Yes
Default
Status
Power On Sequence
S/W Reset
H/W Reset
Default Value
Contents of memory is set randomly
Contents of memory is not cleared
Contents of memory is not cleared
Flow Chart
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.147Apr, 2010
HX8353-D
132RGB x 162 dots, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
8.2.25 Partial area (30h)
30 H
Command
1st parameter
2nd parameter
3rd parameter
4th parameter
PLTAR (Partial Area)
DNC NWR NRD D15-8
0
↑
1
-
D7
D6
D5
D4
D3
D2
D1
D0
HEX
0
0
1
1
0
0
0
0
30
1
↑
1
SR15 SR14 SR13 SR12 SR11 SR10 SR9 SR8 0000:
1
↑
1
SR7 SR6 SR5 SR4 SR3 SR2 SR1 SR0 013F
1
↑
1
ER15 ER14 ER13 ER12 ER11 ER10 ER9 ER8 0000:
1
↑
1
ER7 ER6 ER5 ER4 ER3 ER2 ER1 ER0 013F
This command defines the partial mode’s display area. There are 4 parameters associated
with this command, the first defines the Start Row (SR) and the second the End Row (ER),
as illustrated in the figures below. SR and ER refer to the Frame Memory Line Pointer.
If End Row > Start Row when MADCTL B4(ML) = 0:
If End Row > Start Row when MADCTL B4(ML) = 1:
Description
If End Row<Start Row when MADCTL’s B4(ML) = 0:
End Row
ER[15:0]
Partial
Area
SR[15:0]
Start Row
If End Row = Start Row then the Partial Area will be one row deep.
Restriction
SR[15:0] and ER[15:0] cannot be exceeding than 00A1h.
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.148Apr, 2010
HX8353-D
132RGB x 162 dots, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In or Booster Off
Register
Availability
Status
Power On Sequence
S/W Reset
H/W Reset
Default
Availability
Yes
Yes
Yes
Yes
Yes
Default Value
SR[15:0]=0000h
ER[15:0]=00A1h
SR[15:0]=0000h
ER[15:0]=00A1h
SR[15:0]=0000h
ER[15:0]=00A1h
1. To Enter Partial Display Mode:
Flow Chart
2. To Leave Partial Display Mode
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.149Apr, 2010
HX8353-D
132RGB x 162 dots, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
8.2.26 Vertical scrolling definition (33h)
33 H
Command
1st parameter
2nd parameter
3rd parameter
4th parameter
th
5 parameter
th
6 parameter
VSCRDEF (Vertical Scrolling Definition)
D6
DNC NWR NRD D15-8 D7
0
↑
1
0
0
1
↑
1
-
1
↑
1
-
1
↑
1
-
1
↑
1
-
1
↑
1
-
1
↑
1
-
D5
1
D4
1
D3
0
D2
0
D1
1
D0
1
HEX
33
TFA 15 TFA 14 TFA 13 TFA 12 TFA 11 TFA 10 TFA 9 TFA 8 0000:
TFA 7 TFA 6 TFA 5 TFA 4 TFA 3 TFA 2 TFA 1 TFA 0 00A2
VSA 15 VSA 14 VSA 13 VSA 12 VSA 11 VSA 10 VSA 9 VSA 8 0000:
VSA 7 VSA 6 VSA 5 VSA 4 VSA 3 VSA 2 VSA 1 VSA 0 00A2
BFA 15 BFA 14 BFA 13 BFA 12 BFA 11 BFA 10 BFA 9 BFA 8 0000:
BFA 7 BFA 6 BFA 5 BFA 4 BFA 3 BFA 2 BFA 1 BFA 0 00A2
This command defines the Vertical Scrolling Area of the display. When MADCTL B4=0, the
st
nd
1 & 2 parameter TFA[15:0] describes the Top Fixed Area (in No. of lines from top of the
rd
th
Frame Memory and Display). The 3 & 4 parameter VSA[15:0] describes the height of the
Vertical Scrolling Area (in No. of lines of the Frame Memory [not the display] from the
Vertical Scrolling Start Address). The first line read from Frame Memory appears
th
th
immediately after the bottom most line of the Top Fixed Area. The 5 & 6 parameter
BFA[15:0] describes the Bottom Fixed Area (in No. of lines from Bottom of the Frame
Memory and Display). TFA, VSA and BFA refer to the Frame Memory Line Pointer.
Description
When MADCTL B4=1
st
nd
The 1 & 2 parameter TFA[15:0] describes the Top Fixed Area (in No. of lines from
rd
th
bottom of the Frame Memory and Display). The 3 & 4 parameter VSA[15:0] describes
the height of the Vertical Scrolling Area (in No. of lines of the Frame Memory [not the
display] from the Vertical Scrolling Start Address). The first line read from Frame Memory
th
th
appears immediately after the top most line of the Top Fixed Area. The 5 & 6 parameter
BFA[15:0] describes the Bottom Fixed Area (in No. of lines from Top of the Frame Memory
and Display).
Restriction
The condition is (TFA+VSA+BFA)=162, otherwise Scrolling mode is undefined. In Vertical Scroll
Mode, MADCTL B5 should be set to ‘0’ – this only affects the Frame Memory Write.
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.150Apr, 2010
HX8353-D
132RGB x 162 dots, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
Register
Availability
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In or Booster Off
Default
Status
Power On Sequence
S/W Reset
H/W Reset
TFA[15:0]=0000
TFA[15:0]=0000
TFA[15:0]=0000
Availability
Yes
Yes
Yes
Yes
Yes
Default Value
VSA[15:0]=00A2h
VSA[15:0]=00A2h
VSA[15:0]=00A2h
BFA[15:0]=0000
BFA[15:0]=0000
BFA[15:0]=0000
1. To enter Vertical Scroll Mode:
Flow Charts
Note: The Frame Memory Window size must be defined correctly otherwise undesirable image will be
displayed.
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.151Apr, 2010
HX8353-D
132RGB x 162 dots, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
2. Continuous Scroll:
Legend
Scroll Mode
CASET
1st & 2nd Parameter SC[15..0]
Command
Parameter
Display
Action
3rd & 4th Parameter EC[15..0]
Mode
PASET
1st & 2nd Parameter SP[15..0]
Sequential
transfer
3rd & 4th Parameter EP[15..0]
RAMRW
Scroll Image
Data
VSCRSADD
1st & 2nd Parameter VSP[15..0]
3. To Leave Vertical Scroll Mode:
Scroll Mode
DISPOFF
(Optional)
To prevent
Tearing Effect
Image Displayed
NORON/PTLON
Scroll Mode OFF
RAMRW
Image Data
D1[17:0],D2[17:0]
...,Dn[17:0]
DISPON
Note: Scroll Mode can be left by both the Normal Display Mode On (13h) and Partial Mode On (12h)
commands.
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.152Apr, 2010
HX8353-D
132RGB x 162 dots, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
8.2.27 Tearing effect line off (34h)
34 H
TEOFF (Tearing Effect Line OFF)
Command
Parameter
DNC NWR NRD D15-8
0
↑
1
No Parameter
Description
This command is used to turn OFF the Tearing Effect output signal from the TE signal line.
Restriction
This command has no effect when Tearing Effect output is already OFF.
Register
Availability
Default
D7
0
D6
0
D5
1
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In or Booster Off
Status
Power On Sequence
S/W Reset
H/W Reset
D4
1
D3
0
D2
1
D1
0
D0
0
HEX
34
Availability
Yes
Yes
Yes
Yes
Yes
Default Value
Tearing Effect Off
Tearing Effect Off
Tearing Effect Off
Legend
Command
TE Line Output ON
Parameter
TEOFF
Flow Chart
Display
Action
TE Line Output OFF
Mode
Sequential
transfer
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.153Apr, 2010
HX8353-D
132RGB x 162 dots, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
8.2.28 Tearing effect line on (35h)
35 H
Command
1stparameter
TEON (Tearing Effect Line ON)
DNC NWR NRD D15-8 D7
D6
D5
D4
D3
D2
D1
D0
HEX
0
↑
1
0
0
1
1
0
1
0
1
35
TEMODE
0
↑
1
This command is used to turn ON the Tearing Effect output signal from the TE signal
line. This output is not affected by changing MADCTL bit B4.
The Tearing Effect Line On has one parameter which describes the mode of the
Tearing Effect Output Line. (X=Don’t Care).
When TEMODE=0:
The Tearing Effect Output line consists of V-Blanking information only:
tvdl
tvdh
Vertical Time
Scale
Description
When TEMODE=1:
The Tearing Effect Output Line consists of both V-Blanking and H-Blanking
information:
Note: During Sleep In Mode with Tearing Effect Line On, Tearing Effect Output pin
will be active Low.
Restriction
Register
Availability
Default
This command has no effect when Tearing Effect output is already ON.
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In or Booster Off
Status
Power On Sequence
S/W Reset
H/W Reset
Availability
Yes
Yes
Yes
Yes
Yes
Default Value
Tearing Effect Off
Tearing Effect Off
Tearing Effect Off
Legend
TE Line Output OFF
Command
Parameter
TEON
Flow Chart
M
Display
Action
Mode
TE Line Output ON
Sequential
transfer
Himax Confidential
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in whole or in part without prior written permission of Himax.
-P.154Apr, 2010
HX8353-D
132RGB x 162 dots, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
8.2.29 Memory access control (36h)
36 H
Command
1st parameter
MADCTL (Memory Access Control)
DNC NWR NRD D15-8 D7
D6
D5
D4
D3
D2
0
↑
1
0
0
1
1
0
1
1
↑
1
MY
MX
MV
ML BGR
SS
This command defines read/write sc oning direction of frame memory.
This command makes no change on the other driver status.
Bit Assignment
Bit
MY
MX
Name
PAGE ADDRESS ORDER
COLUMN ADDRESS ORDER
MV
PAGE/COLUMN SELECTION
ML
Vertical ORDER
BG
R
RGB-BGR ORDER
SS
Horizontal ORDER
D1
1
-
D0
0
-
HEX
36
-
Description
These 3 bits controls MCU to
memory write/read direction. See
Section 6.2.1 “MCU to memory
write/read direction”
LCD vertical refresh direction
control
Color selector switch control
(0=RGB color filter panel, 1=BGR
color filter panel)
LCD horizontal refresh direction
control
ML- Vertical Updating order
Description
ML="0"
ML="1"
Top- Left(0,0)
Top- Left ( 0,0)
Memory
Display
Sent First (1)
Sent 2nd
Sent 3rd
Sent last (162)
Top- Left(0,0)
Top- Left ( 0,0)
Memory
Display
Sent last (162)
Sent 3rd
Sent 2nd
Sent First (1)
Himax Confidential
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in whole or in part without prior written permission of Himax.
-P.155Apr, 2010
HX8353-D
132RGB x 162 dots, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
SS- Horizontal Updating order
SS="0"
SS="1"
Top-Left (0,0)
Top- Left (0,0)
Display
Display
Sent 3rd
Top-Left( 0,0)
Memory
Memory
Sent First(1)
Sent 2nd
Sent 3rd
Sent last (132)
Sent last (132)
Sent 3rd
Sent 2nd
Sent First(1)
Top-Left( 0,0)
Note: Top-Left (0,0) means a physical memory location.
Restriction
D1 and D0 are set to ‘00’ internally. D2 is implemented if the LCD is updating pixel-by pixel.
D2 is set to ‘0’ internally if the LCD is updating line-by-line.
Register
Availability
Default
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In or Booster Off
Status
Power On Sequence
S/W Reset
H/W Reset
Availability
Yes
Yes
Yes
Yes
Yes
Default Value
00h
No Change
00h
Flow Chart
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.156Apr, 2010
HX8353-D
132RGB x 162 dots, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
8.2.30 Vertical scrolling start address (37h)
37 H
Command
st
1 parameter
nd
2 parameter
VSCRSADD (Vertical Scrolling Start Address)
DNC NRD NWR D15-8
D7
D6
D5
D4
D3
D2
D1
D0
HEX
0
1
↑
0
0
1
1
0
1
1
1
37
VSP 15 VSP 14 VSP 13 VSP 12 VSP 11 VSP 10 VSP 9 VSP 8
1
1
↑
01.
3F
VSP 7 VSP 6 VSP 5 VSP 4 VSP 3 VSP 2 VSP 1 VSP 0
1
1
↑
This command is used together with Vertical Scrolling Definition (33h). These two commands
describe the scrolling area and the scrolling mode. The Vertical Scrolling Start Address
command has one parameter which describes the address of the line in the Frame Memory
that will be written as the first line after the last line of the Top Fixed Area on the display as
illustrated below:
When MADCTL B4=’0’
Example:
When Top Fixed Area = Bottom Fixed Area = 00, Vertical Scrolling Area = 162 and
When MADCTL B4=1
Example:
When Top Fixed Area = Bottom Fixed Area = 00, Vertical Scrolling Area = 162 and
Restriction
When new Pointer position and Picture Data are sent, the result on the display will
happen at the next Panel Scan to avoid tearing effect.
VSP refers to the Frame Memory line Pointer.
Since the value of the Vertical Scrolling Start Address is absolute (with reference to the Frame
Memory), it must not enter the fixed area (defined by Vertical Scrolling Definition (33h) – otherwise
undesirable image will be displayed on the Panel.
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In or Booster Off
Register
Availability
Status
Power On Sequence
S/W Reset
H/W Reset
Default
Flow Chart
Availability
Yes
Yes
Yes
Yes
Yes
Default Value
00h
00h
00h
See Vertical Scrolling Definition (33h) description.
Himax Confidential
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in whole or in part without prior written permission of Himax.
-P.157Apr, 2010
HX8353-D
132RGB x 162 dots, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
8.2.31 Idle mode off (38h)
38 H
Command
Parameter
IDMOFF (Idle Mode Off)
DNC NWR NRD D15-8
0
↑
1
NO PARAMETER
D7
0
D6
0
D5
1
D4
1
D3
1
D2
0
D1
0
D0
0
HEX
38
Description This command is used to recover from Idle mode on.
In the idle off mode, LCD can display maximum 262,144 colors.
Restriction
Register
Availability
1. This command has no effect when module is already in idle off mode.
2. RGB I/F enable, this command is working as a NOP (00h) command.
Status
Availability
Normal Mode On, Idle Mode Off, Sleep Out
Yes
Normal Mode On, Idle Mode On, Sleep Out
Yes
Partial Mode On, Idle Mode Off, Sleep Out
Yes
Partial Mode On, Idle Mode On, Sleep Out
Yes
Sleep In or Booster Off
Yes
Default
Status
Power On Sequence
S/W Reset
H/W Reset
Default Value
Idle Mode Off
Idle Mode Off
Idle Mode Off
Flow Chart
Himax Confidential
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in whole or in part without prior written permission of Himax.
-P.158Apr, 2010
HX8353-D
132RGB x 162 dots, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
8.2.32 Idle mode on (39h)
39 H
Command
Parameter
IDMON (Idle Mode On)
DNC NWR NRD D15-8
D7
D6
D5
D4
D3
D2
D1
D0
HEX
0
↑
1
0
0
1
1
1
0
0
1
39
NO PARAMETER
This command is used to enter into Idle mode on.
In the idle on mode, color expression is reduced. The primary and the secondary colors using
MSB of each R, G and B in the Frame Memory, 8 color depth data is displayed.
Description
Memory contents vs. Display Color
R5 R4 R3 R2 R1 R0
Black
0XXXXX
Blue
0XXXXX
Red
1XXXXX
Magenta
1XXXXX
Green
0XXXXX
Cyan
0XXXXX
Yellow
1XXXXX
White
1XXXXX
Restriction
Register
Availability
G5 G4 G3 G2 G1 G0
0XXXXX
0XXXXX
0XXXXX
0XXXXX
1XXXXX
1XXXXX
1XXXXX
1XXXXX
B5 B4 B3 B2 B1 B0
0XXXXX
1XXXXX
0XXXXX
1XXXXX
0XXXXX
1XXXXX
0XXXXX
1XXXXX
This command has no effect when module is already in idle off mode.
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In or Booster Off
Default
Status
Power On Sequence
S/W Reset
H/W Reset
Availability
Yes
Yes
Yes
Yes
Yes
Default Value
Idle Mode Off
Idle Mode Off
Idle Mode Off
Himax Confidential
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in whole or in part without prior written permission of Himax.
-P.159Apr, 2010
HX8353-D
132RGB x 162 dots, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
Flow Chart
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.160Apr, 2010
HX8353-D
132RGB x 162 dots, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
8.2.33 Interface pixel format (3Ah)
3A H
Command
COLMOD (Interface Pixel Format)
DNC NWR NRD D15-8 D7
0
↑
1
0
st
1 parameter
1
↑
1
-
-
D6
0
D5
1
D4
1
D3
1
D2
0
D1
1
D0
0
-
-
-
-
D2
D1
D0
HEX
3A
011,
101,
110
Description
This command is used to define the format of RGB picture data, which is to be transfer via the
system interface. The formats are shown in the table:
Interface Format
D2
D1
D0
Not Defined
0
0
0
Not Defined
0
0
1
Not Defined
0
1
0
12 Bit/Pixel
0
1
1
Not Defined
1
0
0
16 Bit/Pixel
1
0
1
18 Bit/Pixel
1
1
0
Not Defined
1
1
1
Restriction
-
Register
Availability
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In or Booster Off
Default
Status
Power On Sequence
S/W Reset
H/W Reset
Availability
Yes
Yes
Yes
Yes
Yes
Default Value
18-bit/pixel
No Change
18-bit/pixel
Flow Chart
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.161Apr, 2010
HX8353-D
132RGB x 162 dots, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
8.2.34 Read ID1 (DAh)
DA H
Command
st
1 parameter
RDID1 (Read ID1)
NWR
NRD
DNC
0
↑
1
1
1
↑
nd
2 parameter
1
1
↑
D15-8
-
D7
1
-
-
D6
1
-
D5
0
-
This read byte identifies the LCD module’s manufacturer.
Restriction
-
Default
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In or Booster Off
Status
Power On Sequence
S/W Reset
H/W Reset
D3
1
-
D2
0
-
D1
1
-
module’s manufacturer m[7:0]
Description
Register
Availability
D4
1
-
D0
0
-
HEX
DA
-
-
Availability
Yes
Yes
Yes
Yes
Yes
Default Value
xxHEX
xxHEX
xxHEX
Flow Chart
Himax Confidential
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in whole or in part without prior written permission of Himax.
-P.162Apr, 2010
HX8353-D
132RGB x 162 dots, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
8.2.35 Read ID2 (DBh)
DB H
RDID2 (Read ID2)
DNC NWR NRD D15-8
Command
0
↑
1
st
1 parameter
1
1
↑
nd
2 parameter 1
1
↑
-
Description
D7
1
1
D6
1
V6
D5
0
V5
D4
1
V4
D3
1
V3
D2
0
V2
D1
1
V1
D0
1
V0
HEX
DB
-
This read byte is used to track the LCD module/driver version. It is defined by display
supplier and changes each time a revision is made to the
display, material or construction specifications. See the following table.
ID Byte Value
Version
Changes
V[7:0]
80h
81h
82h
83h
84h
85h
-
Restrictions
Register
Availability
Default
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In or Booster Off
Status
Power On Sequence
S/W Reset
H/W Reset
Availability
Yes
Yes
Yes
Yes
Yes
Default Value
See Description
See Description
See Description
Flow Chart
Himax Confidential
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in whole or in part without prior written permission of Himax.
-P.163Apr, 2010
HX8353-D
132RGB x 162 dots, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
8.2.36 Read ID3 (DCh)
DC H
RDID3 (Read ID3)
DN
NWR NRD D15-8 D7
D6
D5
C
Command
0
↑
1
1
1
0
st
1 parameter
1
1
↑
nd
2 parameter
1
1
↑
ID7
ID6
ID5
This read byte identifies the LCD module/driver.
Description
D4
D3
D2
D1
D0
HEX
1
ID4
1
ID3
1
ID2
0
ID1
0
ID0
DC
-
Restrictions
Register
Availability
Default
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In or Booster Off
Status
Power On Sequence
S/W Reset
H/W Reset
Availability
Yes
Yes
Yes
Yes
Yes
Default Value
xxHEX
xxHEX
xxHEX
Serial I/F Mode
Parallel I/F Mode
Read ID3
Read ID3
Legend
Command
Flow Chart
Send ID[7:0]
Dummy read
Host
Display
Parameter
Display
Action
Mode
Send ID[7:0]
Sequential
transfer
Himax Confidential
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in whole or in part without prior written permission of Himax.
-P.164Apr, 2010
HX8353-D
132RGB x 162 dots, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
8.2.37 SETOSC: set internal oscillator (B0h)
B0 H
Command
st
1
parameter
nd
2
parameter
SETOSC( Set Internal Oscillator)
DNC NWR NRD D17-8 D7
0
↑
1
1
1
↑
1
-
1
↑
1
-
D6
0
D5
1
D4
1
I_RADJ[1:0]
-
-
D3
0
D2
0
D1
0
D0
0
HEX
B0
N_RADJ[1:0]
-
-
-
-
C4
-
OSC_EN
00
These command is used to set internal oscillator related setting
OSC_EN: Enable internal oscillator, OSC_EN = ‘1’, internal oscillator start to oscillate.
OSC_EN = ‘0’, internal oscillator stop.
N_RADJ[1:0]: Internal oscillator frequency adjusts in Normal / Partial mode.
I_RADJ[1:0]: Internal oscillator frequency adjusts in Idle(8-color) / Partial Idle mode.
Description
For details, please refer to “7.1 Internal Oscillator” section.
RADJ1 RADJ0
0
0
1
1
Restrictions
0
1
0
1
If EXTC is high or enable SETEXTC command (even EXTC = low) can enable this
command
Register
Availability
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In or Booster Off
Default
Status
Power On Sequence
S/W Reset
H/W Reset
Flow Chart
Internal Oscillator
Frequency
147.4%
127.1%
111.7%
100%
Availability
Yes
Yes
Yes
Yes
Yes
Default Value
I_RADJ[1:0]=11, N_RADJ[1:0]=10, OSC_EN=0
OSC_EN=0, others no change
I_RADJ[1:0]=11, N_RADJ[1:0]=10, OSC_EN=0
-
Himax Confidential
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in whole or in part without prior written permission of Himax.
-P.165Apr, 2010
HX8353-D
132RGB x 162 dots, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
8.2.38 SETPOWER: set power (B1h)
B1 H
Command
st
1 parameter
nd
2 parameter
rd
3 parameter
th
4 parameter
th
5 parameter
th
6 parameter
th
7 parameter
th
8 parameter
SETPOWER (Set Power )
DNC NWR NRD
D17-8
D7
D6
D5
D4
D3
D2
D1
↑
-
1
0
1
1
0
0
0
1
DP_
STB
DP_
STB
_S
0
↑
1
1
1
-
-
-
-
-
-
-
D0
HE
X
B1
00
BT[2:0]
1
↑
1
01
VRH[5:0]
1
↑
1
1B
AP[2:0]
1
↑
1
03
FS0[7:0]
1
↑
1
04
FS1[7:0]
1
↑
1
04
1
↑
1
11
GASEN VCOMG
PON DK
STB
1
↑
1
89
DP_STB, DP_STB_S : These two bits can let the driver into the deep standby mode. And
when into deep standby, all display operation stops, including the internal R-C oscillator. In
the deep standby mode, the GRAM data and register content are not retained.
VRH[5:0]: Specify the VREG1 voltage adjusting. VREG1 voltage is for gamma voltage
setting.VREG1=Decimal(VRH[5:0])x0.05+3.3.
Description
VRH5
VRH4
VRH3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
:
:
:
0
0
0
1
1
1
1
0
:
1
1
1
1
VRH2 VRH1
VRH0
VREG1
0
0
1
1
0
0
0
1
0
1
0
1
3.30
3.35
3.40
3.45
3.50
3.55
:
:
:
:
1
1
1
0
1
1
1
0
0
1
1
0
1
0
1
0
4.75
4.80
STOP
STOP
:
:
:
:
:
:
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
STOP
STOP
STOP
STOP
:
:
:
:
:
:
1
1
1
1
1
0
1
1
1
1
1
1
:
STOP
Internal circuit operations stop.
The gamma voltage can be
adjusted from external VREG1
input.
Note: (1) Internal reference voltage VREF=4.8V ( Please set DDVDH_TRI=0)
(2) Internal VREF can be modified by Custom’s special request.
VREG1={Decimal(VRH[5:0])x0.05+3.3 }*(VREF/4.8) ( Please set DDVDH_TRI=0)
Himax Confidential
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in whole or in part without prior written permission of Himax.
-P.166Apr, 2010
HX8353-D
132RGB x 162 dots, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
BT[2:0]: Switch the output factor of step-up circuit 2 for VGH and VGL voltage generation.
The LCD drive voltage level can be selected according to the characteristic of
liquid crystal which panel used. Lower amplification of the step-up circuit
consumes less current and then the power consumption can be reduced.
BT2
BT1
BT0
DDVDH
VCL
VGH
VGL
0
0
0
5.0V
-VCI
11V ~ 14.5V
-8V ~ -12.5V
0
0
1
5.0V
-VCI
11V ~ 14.5V
-6V ~ -10V
0
1
0
5.0V
-VCI
11V ~ 14.5V
-5V ~ -7V
0
1
1
5.0V
-VCI
9V ~ 12.5V
-8V ~ -12.5V
1
0
0
5.0V
-VCI
9V ~ 12.5V
-6V ~ -10V
1
0
1
5.0V
-VCI
9V ~ 12.5V
-5V ~ -7V
1
1
0
5.0V
-VCI
8V ~ 10V
-6V ~ -10V
1
1
1
5.0V
-VCI
8V ~ 10V
-5V ~ -7V
Note1: When VCI = 2.8V and DDVDH_TRI=0
Note2: The “VGH” & “VGL” value depend on panel
Note3: The VGH v.s Ivgh and VGL v.s. Ivgl ,please reference the chapter 11.3 DC characteristic
AP[2:0]: Adjust the amount of current driving for the operational amplifier in the power supply
circuit. When the amount of fixed current is increased, the LCD driving capacity and the
display quality are high, but the current consumption is increased. Adjust the fixed current by
considering both the display quality and the current consumption.
AP2
0
0
0
0
1
1
1
1
AP1
0
0
1
1
0
0
1
1
AP0
0
1
0
1
0
1
0
1
Constant Current of Operational Amplifier
Operation of the operational amplifier stops
Small
Small
Small
Medium
Medium High
Large
Small
Himax Confidential
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in whole or in part without prior written permission of Himax.
-P.167Apr, 2010
HX8353-D
132RGB x 162 dots, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
FS0[7:0]: Set the operating frequency for DDVDH and VCL voltage generation.
For details, please refer to “7.1 Internal Oscillator” section.
FS07
FS06
FS05
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
:
:
:
1
1
1
1
1
1
Note : TIMING_CLK =
FS04
FS03
FS02
FS01
FS00
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
0
1
1
0
0
1
0
0
0
0
1
0
1
:
:
:
:
:
1
1
1
1
0
1
1
1
1
1
TIMING_CLK/(2*X) ; X = FS0’s Value.
Operation Frequency
for DDVDH and VCL
TIMING_CLK/2
TIMING_CLK/2
TIMING_CLK/4
TIMING_CLK/6
TIMING_CLK/8
TIMING_CLK/10
:
TIMING_CLK/508
TIMING_CLK/510
FS1[7:0]: Set the operating frequency for VGH and VGL voltage generation.
For details, please refer to “7.1 Internal Oscillator” section.
FS17
FS16
FS15
FS14
FS13
FS12
FS11
FS10
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
:
:
:
:
:
:
:
:
1
1
1
1
1
1
1
1
1
Note: TIMING_CLK =
1
1
1
0
1
1
1
1
1
0
1
1
1
1
1
TIMING_CLK/X ; X = FS1’s Value.
Operation Frequency
for VGH and VGL
TIMING_CLK/1
TIMING_CLK/1
TIMING_CLK/2
TIMING_CLK/3
:
TIMING_CLK/253
TIMING_CLK/254
TIMING_CLK/255
Ensure that the operation frequency of FS0 ≧ FS1.
STB: When STB = “1”, the HX8353-D into the standby mode, where all display operation stops,
suspend all the internal operations including the internal R-C oscillator. During the standby mode,
only the following process can be executed.
a. Exit the Standby mode (STB = “0”) ,
b. Start the oscillation
In the standby mode, the GRAM data and register content will be keeping.
GASEN: This stands for abnormal power-off monitor function when the power is off.
DK: Specify on/off control of step-up circuit 1 for DDVDH voltage generation. For detail,
see the Power Supply Setting Sequence.
DK
Operation of step-up circuit 1
0
ON
1
OFF
PON: Specify on/off control of step-up circuit 2 for VCL, VGL voltage generation.
For detail, see the Power Supply Setting Sequence.
PON
0
1
Operation of step-up circuit 2
OFF
ON
VCOMG: When VCOMG = ‘1’, VCOML voltage can output to negative voltage. When
Himax Confidential
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in whole or in part without prior written permission of Himax.
-P.168Apr, 2010
HX8353-D
132RGB x 162 dots, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
VCOMG = ‘0’, VCOML = GND.
DK: set “0” => DDVDH Enable, set “1” => DDVDH Disable.
Restrictions
If EXTC is high or enable SETEXTC command (even EXTC = low) can enable this command
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In or Booster Off
Register
Availability
Status
Power On Sequence
Default
S/W Reset
H/W Reset
Flow Chart
Availability
Yes
Yes
Yes
Yes
Yes
Default Value
DP_STB=0, DP_STB_S=0, BT[2:0]=3’b011,
VRH[5:0]=6’b011011, AP[2:0]=3’b011, FS0[7:0]=8’h01,
FS1[7:0]=8’h10, BLANK_FS0[3:0]=4’b0001, BLANK_FS1[3:0]=
4’b0001, GASEN=1, VCOMG=0, PON=0, DK=1, STB=1
VCOMG=0, PON=0, DK=1, STB=1, others no change
DP_STB=0, DP_STB_S=0, BT[2:0]=3’b011,
VRH[5:0]=6’b011011, AP[2:0]=3’b011, FS0[7:0]=8’h01,
FS1[7:0]=8’h10, BLANK_FS0[3:0]=4’b0001, BLANK_FS1[3:0]=
4’b0001, GASEN=1, VCOMG=0, PON=0, DK=1, STB=1
-
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.169Apr, 2010
HX8353-D
132RGB x 162 dots, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
8.2.39 SETDISPLAY: set display related register (B2h)
B2H
Command
st
1 parameter
nd
2 parameter
rd
3 parameter
SETDISPLAY( Set Display Control )
DNC NWR NRD D17-8 D7
D6
D5
D4
0
↑
1
1
0
1
1
1
↑
1
1
↑
1
PT[1:0]
PTV[1:0]
1
↑
1
GON DTE
This command is used to set display related register
D3
0
D1
D2
D1
0
1
ISC[3:0]
PTG
D0
-
D0
0
REF
-
HEX
B2
01
93
20
D[1:0]: When D1 = ‘1’, display is on; when D1 = ‘0’, display is off. When display is off, the
display data is retained in the GRAM and the entire source outputs are set to the VSSD
level.
When D[1:0]= ‘01’, the internal display of the HX8353-D is performed although the actual
display is off. When D[1:0]= ‘00’, the internal display operation halts and the display is off.
D1
0
0
1
1
D0
0
1
0
1
Source Output
VSSD
VSSD
=PT(0,0)
Display
Internal Display Operations
Halt
Operate
Operate
Operate
Gate-Driver Control Signals
Halt
Operate
Operate
Operate
GON, DTE:
GON
1
1
DTE
0
1
Gate Output
Fixed to VGL
Normal Operation
(VGH/VGL)
PT[1:0] : Specify the Non-display area source output in partial display mode.
Source Output Level
Non-display Area
Description
REV_Panel
1
(Normally
Black Panel)
0
(Normally
White Panel)
GRAM
Data
18’h00000
:
18’h3FFFF
18’h00000
:
18’h3FFFF
Display area
PT1-0=(0,*)
PT1-0=(1,0)
PT1-0=(1,1)
VCOM = VCOM = VCOM = VCOM = VCOM = VCOM = VCOM =
“L”
“H”
“L”
“H”
“L”
“H”
“L”
V63P
V0N
:
:
V63P
V0N
GND
GND
Hi-z
V0P
V63N
V0P
V63N
:
:
V63P
V0N
GND
GND
Hi-z
V63P
V0N
VCOM
= “H”
Hi-z
Hi-z
REF: Refresh display in non-display area in Partial mode enable bit.
REF = ‘0’: Refresh display operation is disabling.
REF = ‘1’: Refresh display operation is enable.
PTG: Specify the scan mode of gate driver in non-display area.
PTG
0
1
Gate Outputs in Non-display Area
Normal Drive
Fixed VGL
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.170Apr, 2010
HX8353-D
132RGB x 162 dots, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
PTV[1:0]: Specify the scan mode of VCOM in non-display area.
PTV1
0
0
1
1
PTV0
0
1
0
1
VCOM Outputs in Non-display Area
Normal Drive
Fixed to VCOML
Fixed to GND
Setting Inhibited
ISC[3:0]: Specify the scan cycle of gate driver when REF = ‘1’ in non-display area. Then
scan cycle is set to Decimal(ISC[3:0])x4+1.The polarity is inverted every scan cycle.
ISC3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
PT1
0
1
ISC2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
PT0 REF
x
0
Restrictions
1
ISC0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
ISC[3:0]
x
--
0
-Non-refresh cycle
1
0
1
ISC1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
Refresh cycle
-Non-refresh cycle
Refresh cycle
Scan Cycle
1 frame
5 frames
9 frames
13 frames
17 frames
21 frames
25 frames
29 frames
33 frames
37 frames
41 frames
45 frames
49 frames
53 frames
57 frames
61 frames
Source Output
Black Display
( REV_PANEL = ‘1’)
White Display
(REV_PANEL = ‘0’)
GND
GND
Black Display
(REV_PANEL = ‘1’)
White Display
(REV_PANEL = ‘0’)
Hi-z
Hi-z
Black Display
(REV_PANEL = ‘1’)
White Display
(REV_PANEL = ‘0’)
fFLM = 60Hz
17ms
83ms
150ms
217ms
283ms
350ms
417ms
483ms
550ms
616ms
683ms
750ms
816ms
883ms
950ms
1017ms
VCOM Output
Gate Output
Normal Driving
Normal Driving
PTV[1:0]
PTV[1:0]
PTG
PTG
Normal Driving
Normal Driving
PTV[1:0]
PTV[1:0]
PTG
PTG
Normal Driving
Normal Driving
If EXTC is high or enable SETEXTC command (even EXTC = low) can enable this command
Himax Confidential
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in whole or in part without prior written permission of Himax.
-P.171Apr, 2010
HX8353-D
132RGB x 162 dots, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In or Booster Off
Register
Availability
Status
Power On Sequence
Default
S/W Reset
H/W Reset
Flow Chart
Availability
Yes
Yes
Yes
Yes
Yes
Default Value
ISC[3:0]=4’b0001, PT[1:0]=2’b10, PTV[1:0]=2’b01, PTG=1,
REF=1, GON=1, DTE=0, D[1:0]=2’b00
GON=1, D0=0, others no change
ISC[3:0]=4’b0001, PT[1:0]=2’b10, PTV[1:0]=2’b10, PTG=1,
REF=1, GON=1, DTE=0, D[1:0]=2’b00
-
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.172Apr, 2010
HX8353-D
132RGB x 162 dots, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
8.2.40 SETCYC: set display cycle register (B4h)
B4 H
Command
st
1 parameter
nd
2 parameter
rd
3 parameter
th
4 parameter
th
5 parameter
th
6 parameter
th
7 parameter
th
8 parameter
SETCYC ( Set display cycle )
DNC NWR NRD D17-8 D7
D6
D5
D4
D3
0
↑
1
1
0
1
1
0
1
↑
1
I/_NW[2:0]
1
↑
1
I_RTN[3:0]
1
↑
1
I_DIV[3:0]
1
↑
1
N_DUM[7:0]
1
↑
1
I_DUM[7:0]
1
↑
1
GDON[7:0]
1
↑
1
GDOF[7:0]
1
↑
1
L_BASE[7:0]
This command is used to set display related register
D2
1
D1
D0
0
0
N_NW[2:0]
N_RTN[3:0]
N_DIV[3:0]
HEX
B4
01
04
FF
0C
0C
0D
53
59
N_ NW[2:0]: Specify LCD driving inversion type in Normal/ Partial mode.
I_ NW[2:0]: Specify LCD driving inversion type in Idle / Partial Idle mode.
NW[2:0]
0d
1d
2d
3d
:
6d
7d
LCD driving Inversion Type
Frame inversion
1-line inversion
2-line inversion
3-line inversion
:
6-line inversion
7-line inversion
N_DIV[3:0]: Specify the division ratio of internal clocks in Normal / Partial mode for
internal operation. When used internal clock for the display operation, frame frequency
can be adjusted with the N_RTN[3:0] bits (1H period clock cycle), N_DIV[3:0], and
N_DUM[7:0] bits.
Description
I_DIV[3:0]: Specify the division ratio of internal clocks in Idle (8-color) / Partial Idle mode
for internal operation. When used internal clock for the display operation, frame frequency
can be adjusted with the I_RTN[3:0] bits(1H period clock cycle), I_DIV[3:0], and
I_DUM[7:0] bits.
fosc = R-C oscillation frequency
DIV3
DIV2
DIV1
DIV0
0
0
0
0
0
0
0
:
1
1
1
0
0
0
0
1
1
1
:
1
1
1
0
0
1
1
0
0
1
:
0
1
1
0
1
0
1
0
1
0
:
1
0
1
Division
Ratio
1
1
1.5
2
2.5
3
3.5
:
7
7.5
1.5
Internal Display Operation
Clock Frequency
fosc / 1
fosc / 1
fosc / 1.5
fosc / 2
fosc / 2.5
fosc / 3
fosc / 3.5
:
fosc / 7
fosc / 7.5
fosc / 1.5 (defaule)
N_RTN[3:0]: Specify clock number of one line period in Normal / Partial mode for internal
operation.
Himax Confidential
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in whole or in part without prior written permission of Himax.
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HX8353-D
132RGB x 162 dots, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
I_ RTN[3:0]: Specify clock number of one line period in Idle (8-color) / Partial Idle mode for
internal operation.
Clock cycles=1/internal operation clock frequency(fosc)
RTN[3:0]
Clock number per Line
4’b0000
89
4’b0001
90
4’b0010
91
4’b0011
92
4’b0100
93
:
:
4’b1110
103
4’b1111
104
N_DUM[7:0]: Specify dummy line number in blanking area of one frame in Normal / Partial
mode for internal operation.
I_DUM[7:0]: Specify dummy line number in blanking area of one frame in Idle (8-color) /
Partial Idle mode for internal operation.
DUM[7:0]
000d
001d
002d
003d
004d
:
190d
others
Line number in blanking period
Setting Inhibited
Setting Inhibited
2
3
4
:
190
Setting Inhibited
Formula for the Frame Frequency during internal display mode:
Frame frequency = fosc/( RTN × DIV × (162+DUM) ) [Hz]
fosc: RC oscillation frequency
GDON[7:0]: Specify the valid gate output start time in 1-line driving period. The period
time value is defined as SYSCLK number in internal clock display mode. The
period time value is defined as DOTCLK number in 18/16-bit bus width RGB
display mode and is defined as DOTCLK/3 number in 6-bit bus width RGB display
mode. (Please note that the setting “00h”, “01h”, “02h” is inhibited).
GDOF[7:0]: Specify the gate output end time in 1-line driving period. The period time value
is defined as SYSCLK number in internal clock display mode. The period time value
is defined as DOTCLK number in 18/16-bit bus width RGB display mode and is
defined as DOTCLK/3 number in 6-bit bus width RGB display mode. (Please note
that the GDON[7:0] + 1≤ GDOF[7:0] ≤ RTN-1).
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.174Apr, 2010
HX8353-D
132RGB x 162 dots, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
1- Line Period
S 1 – S720
Source Output Period
GDON
GDOF
Gate Output Period
VCOM
G(N)
Nth Gate Output Period
G(N+1)
N+1 th Gate Output Period
Restrictions
Register
Availability
L_BASE[7:0]: Basic line clock number. Internal line clock=L_BASE[7:0] + RTN[3:0].
If EXTC is high or enable SETEXTC command (even EXTC = low) can enable this command
Status
Availability
Normal Mode On, Idle Mode Off, Sleep Out
Yes
Normal Mode On, Idle Mode On, Sleep Out
Yes
Partial Mode On, Idle Mode Off, Sleep Out
Yes
Partial Mode On, Idle Mode On, Sleep Out
Yes
Sleep In or Booster Off
Yes
Status
Power On Sequence
Default
S/W Reset
H/W Reset
Flow Chart
Default Value
I_NW[2:0]=3’b000, N_NW[2:0]=3’b001,
I_RTN[3:0]=4’b0000, N_RTN[3:0]=4’b0000,
N_DUM[7:0]=8’b00001100, I_DUM[7:0]=8’b00001100,
GDON[7:0]=8’b00001101, GDOF[7:0]=8’b01110000,
RSO[2:0]=000:
I_DIV[3:0]=N_DIV[3:0]=4’b0110, L_BASE[7:0]=8’h59
RSO[2:0]=001:
I_DIV[3:0]=N_DIV[3:0]=4’b1000, L_BASE[7:0]=8’h53
RSO[2:0]=010:
I_DIV[3:0]=N_DIV[3:0]=4’b0110, L_BASE[7:0]=8’h5A
RSO[2:0]=011:
I_DIV[3:0]=N_DIV[3:0]=4’b0110, L_BASE[7:0]=8’h5A
RSO[2:0]=100:
I_DIV[3:0]=N_DIV[3:0]=4’b1000, L_BASE[7:0]=8’h91
RSO[2:0]=011:
I_DIV[3:0]=N_DIV[3:0]=4’b1000, L_BASE[7:0]=8’h98
No change
I_NW[2:0]=3’b000, N_NW[2:0]=3’b001,
I_RTN[3:0]=4’b0000, N_RTN[3:0]=4’b0000,
N_DUM[7:0]=8’b00001100, I_DUM[7:0]=8’b00001100,
GDON[7:0]=8’b00001101, GDOF[7:0]=8’b01110000,
RSO[2:0]=000:
I_DIV[3:0]=N_DIV[3:0]=4’b0110, L_BASE[7:0]=8’h59
RSO[2:0]=001:
I_DIV[3:0]=N_DIV[3:0]=4’b1000, L_BASE[7:0]=8’h53
RSO[2:0]=010:
I_DIV[3:0]=N_DIV[3:0]=4’b0110, L_BASE[7:0]=8’h5A
RSO[2:0]=011:
I_DIV[3:0]=N_DIV[3:0]=4’b0110, L_BASE[7:0]=8’h5A
RSO[2:0]=100:
I_DIV[3:0]=N_DIV[3:0]=4’b1000, L_BASE[7:0]=8’h91
RSO[2:0]=011:
I_DIV[3:0]=N_DIV[3:0]=4’b1000, L_BASE[7:0]=8’h98
-
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.175Apr, 2010
HX8353-D
132RGB x 162 dots, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
8.2.41 SETBGP: set BGP voltage related register (B5h)
B5 H
Command
st
1 parameter
nd
2 parameter
rd
3 parameter
SETBGP( Set VBGP Voltage)
DNC NWR NRD D17-8
D7
0
↑
1
1
D6
0
D5
1
D4
1
-
-
DDVDH_TRI
-
FBOFF
1
↑
1
1
↑
1
1
↑
1
The DDVDH setting table:
Set VREF @
Description
D2
1
D1
0
D0
1
VVDHS_SEL[3:0]
VREF[3:0]
VR_TRIM[3:0]
HEX
B5
0B
0B
07
DDVDH_TRI=0
VVDHS_SEL[3:0]
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1.8 V
D3
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
DDVDH
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
4.068
4.176
4.284
4.392
4.5
4.608
4.716
4.824
4.932
5.04
5.148
5.256
5.364
5.472
5.58
5.688
The VREF setting table:
DDVDH_TRI=0
VREF[3:0]
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
VREF
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
4.1
4.2
4.3
4.4
4.45
4.5
4.55
4.6
4.65
4.7
4.75
4.8
4.85
4.9
4.95
5
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.176Apr, 2010
HX8353-D
132RGB x 162 dots, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
The VR_TRIM setting table:
VR_TRIM[3:0]
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
VR
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
2.04
2
1.96
1.93
1.9
1.86
1.83
1.8
1.77
1.74
1.71
1.69
1.66
1.64
1.61
1.59
The DDVDH_TRI is setting to “0“ only .
Restrictions
If EXTC is high or enable SETEXTC command (even EXTC = low) can enable this command
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In or Booster Off
Register
Availability
Status
Power On Sequence
Default
S/W Reset
H/W Reset
Flow Chart
Availability
Yes
Yes
Yes
Yes
Yes
Default Value
FBOFF=0, DDVDH_TRI=0,
VVDHS_SEL[3:0]=4’b1001, VREF[3:0]=4’b1011,
VR_TRIM[5:0]=6’b001000
No change
FBOFF=0, DDVDH_TRI=0,
VVDHS_SEL[3:0]=4’b1001, VREF[3:0]=4’b1011,
VR_TRIM[5:0]=6’b001000
-
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.177Apr, 2010
HX8353-D
132RGB x 162 dots, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
8.2.42 SETCOM: set VCOM voltage related register (B6h)
B6 H
Command
st
1 parameter
nd
2 parameter
rd
3 parameter
SETCOM ( Set VCOM Voltage)
DNC NWR NRD D17-8
D7
0
↑
1
1
D6
0
D5
1
D4
1
D3
0
D2
1
D1
1
D0
0
1
↑
1
VMF7 VMF6 VMF5 VMF4 VMF3 VMF2 VMF1 VMF0
1
↑
1
VMH7 VMH6 VMH5 VMH4 VMH3 VMH2 VMH1 VMH0
1
↑
1
VML7 VML6 VML5 VML4 VML3 VML2 VML1 VML0
This command is used to set VCOM Voltage include VCOM Low and VCOM High Voltage
VMH[7:0]:
HEX
B6
9E
6C
54
Set the VCOMH voltage (High level voltage of VCOM). VCOM High voltage =
Decimal(VMH[7:0])x0.015+2.5.
Description
VMH
7
0
0
0
0
0
0
VMH
6
0
0
0
0
0
0
VMH
5
0
0
0
0
0
0
VMH
4
0
0
0
0
0
0
VMH
3
0
0
0
0
0
0
VMH
2
0
0
0
0
1
1
VMH
1
0
0
1
1
0
0
VMH
0
0
1
0
1
0
1
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
1
1
1
1
1
1
0
1
1
1
1
0
0
0
0
1
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
4.705
4.720
4.735
4.750
4.765
4.780
4.795
4.800
4.800
4.800
4.800
4.800
4.800
4.800
4.800
4.800
Setting inhibited
:
:
:
:
:
:
:
:
1
1
1
1
0
0
1
1
1
1
0
1
1
0
1
0
:
:
:
:
:
:
:
:
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
VCOMH
(DDVDH_TRI=0)
2.500
2.515
2.530
2.545
2.560
2.575
Note: Internal VREF can be modified by customer’s request. default VREF=4.8V (DDVDH_TRI=0 )
VCOMH= {Decimal(VMH[7:0])x0.015+2.5 }*(VREF/4.8) (DDVDH_TRI=0)
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.178Apr, 2010
HX8353-D
132RGB x 162 dots, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
VML[7:0]: Set the VCOML voltage (Low level voltage of VCOM). VCOM Low voltage =
Decimal(VML[7:0])x0.015-2.5.
VML7 VML6 VML5 VML4 VML3 VML2 VML1 VML0
VCOML
0
0
0
0
0
0
0
0
-2.500
0
0
0
0
0
0
0
1
-2.485
0
0
0
0
0
0
1
0
-2.470
0
0
0
0
0
1
0
1
-2.455
:
:
:
:
:
:
:
:
:
1
1
1
1
1
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
1
1
1
0
1
0
1
-0.055
-0.040
-0.025
-0.010
VSSA
:
:
:
:
:
:
:
:
1
1
1
1
1
1
1
1
VSSA
Note: Internal VREF can be modified by customer’s request. default VREF=4.8V (DDVDH_TRI=0)
VCOML= { Decimal( VML[7:0])x0.015-2.5 }*(VREF/4.8) ( DDVDH_TRI=0)
VMF[7:0]: Set the VCOM offset voltage. VMH+1d/VML+1d means VMH/VML from original
setting move up one step (15mV). VMH-1d/VML-1d means VMH/VML from original setting
move down one step (15mV)
VMF[7:0]
VCOMH
VCOML
0
“VMH” – 128d
“VMH” – 128d
1
“VMH” – 127d
“VMH” – 127d
2
“VMH” – 126d
“VMH” – 126d
3
“VMH” – 125d
“VMH” – 125d
:
:
:
126
“VMH” – 2d
“VMH” – 2d
127
“VMH” – 1d
“VMH” – 1d
128
“VMH”
“VML”
129
“VMH” + 1d
“VMH” + 1d
130
“VMH” + 2d
“VMH” + 2d
:
:
:
254
“VMH” + 126d
“VMH” + 126d
255
“VMH” + 127d
“VMH” + 127d
Note1 : VMH[7:0]-128+VMF[7:0]>=0 and VML[7:0]-128+VMF[7:0]>=0
Note2：When Setting the VMF, be careful the VCOMH & VCOML voltage’s range.
Restrictions
If EXTC is high or enable SETEXTC command (even EXTC = low) can enable this command
Register
Availability
Default
Flow Chart
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In or Booster Off
Availability
Yes
Yes
Yes
Yes
Yes
Status
Power On Sequence
S/W Reset
H/W Reset
Default Value
OTP value
No change
OTP value
-
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.179Apr, 2010
HX8353-D
132RGB x 162 dots, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
8.2.43 SETEXTC: enable extension command (B9h)
B9 H
SETEXTC ( Set Extended Command Set)
DNC NWR NRD D17-8 D7
D6
D5
D4
D3
D2
Command
0
↑
1
1
0
1
1
1
0
st
1 parameter
1
↑
1
EXTC1[7:0]
nd
2 parameter
1
↑
1
EXTC2[7:0]
rd
3 parameter
1
↑
1
EXTC3[7:0]
This command is used to set extended command set access enable.
Extend cmd
Description
Enable
Disable(default)
Restrictions
D0
1
HEX
B9
00
00
00
Command description
After command (B9h), must write 3 parameters
(FFh,83h,53h) by order
After command(B9h), write 3 parameters (xxh,xxh,xxh) any
value is all right, but can not be (FFh,83h,53h)
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In or Booster Off
Register
Availability
Status
Power On Sequence
S/W Reset
H/W Reset
Default
Flow Chart
D1
0
Availability
Yes
Yes
Yes
Yes
Yes
Default Value
EXTC1[7:0]=8’h00, EXTC2[7:0]=8’h00, EXTC3[7:0]=8’h00
No change
EXTC1[7:0]=8’h00, EXTC2[7:0]=8’h00, EXTC3[7:0]=8’h00
-
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.180Apr, 2010
HX8353-D
132RGB x 162 dots, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
8.2.44 SETOTP: set OTP setting (BBh)
BB H
SETOTP ( Set OTP related setting)
DNC NWR NRD D17-8 D7
D6
Command
0
↑
1
1
0
st
1 parameter
1
↑
1
nd
2 parameter
1
↑
1
rd
3 parameter
th
4 parameter
th
5 parameter
Description
Restrictions
1
↑
1
-
DCCL
K_DI
SABL
E
OTP_
POR
D4
D3
D2
1
1
0
OTP_MASK[7:0]
OTP_INDEX[7:0]
OTP_
PWE
OTP_
EN
OTPT
EST_
EN
D1
1
D0
1
VPP_
SEL
OTP_
PRO
G
HEX
BB
00
00
00
OTP_PTM[ OTP_VRAD
00
1:0]
J[1:0]
1
1
↑
OTP_DATA[7:0]
00
This command is used to set the OTP related setting.
OTP_MASK7~OTP_MASK0: Bit programming mask, if 1, means don’t programming this bit
OTP_INDEX7~OTP_INDEX0: Set location of OTP to be programmed
OTP_EN: When written to 1, internal register begin written to OTP
VPP_SEL: When written to 1, PVSS voltage is fed to OTP
OTP_LOAD_DISABLE: When written to 1, auto load from OTP to internal register when
SLPOUT command received is disabled, this is used when OTP is not yet programmed
DCCLK_DISABLE: Disable Pumping Clock
OTPTEST_EN:
0 : normal mode, automatic OTP programming mode (by internal state machine)
1 : manual mode
0 is the default value
OTP_POR: for OTP read/write timing control
OTP_PPROG : 1’b1 to turn on OTP write mode.
OTP_PWE : 1’b1 to write OTP.
OTP_PTM[1:0] : OTP Test mode register, In-house use.
OTP_VRADJ[1:0] : OTP VPP2 adjusts register, In-house use.
OTP_DATA[7:0] : OTP read data.
If EXTC is high or enable SETEXTC command (even EXTC = low) can enable this
command
1
↑
1
-
-
-
-
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In or Booster Off
Register
Availability
Status
Power On Sequence
Default
S/W Reset
H/W Reset
Flow Chart
OTP_
LOA
D_DI
SABL
E
D5
1
-
Availability
Yes
Yes
Yes
Yes
Yes
Default Value
OTP_MASK[7:0]=8’h00, OTP_INDEX[7:0]=8’h00,
OTP_LOAD_DISABLE=0, DCCLK_DISABLE=0, OTP_POR=0,
OTP_PWE=0, OTP_EN=0, OTPTEST_EN=0, VPP_SEL=0,
OTP_PROG=0, OTP_PTM[1:0]=2’b00,
OTP_VRADJ[1:0]=2’b00
OTP_MASK[7:0]=8’h00, OTP_INDEX[7:0]=8’h00,
OTP_LOAD_DISABLE=0, DCCLK_DISABLE=0, OTP_POR=0,
OTP_PWE=0, OTP_EN=0, OTPTEST_EN=0, VPP_SEL=0,
OTP_PROG=0, OTP_PTM[1:0]=2’b00,
OTP_VRADJ[1:0]=2’b00
OTP_MASK[7:0]=8’h00, OTP_INDEX[7:0]=8’h00,
OTP_LOAD_DISABLE=0, DCCLK_DISABLE=0, OTP_POR=0,
OTP_PWE=0, OTP_EN=0, OTPTEST_EN=0, VPP_SEL=0,
OTP_PROG=0, OTP_PTM[1:0]=2’b00,
OTP_VRADJ[1:0]=2’b00
-
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.181Apr, 2010
HX8353-D
132RGB x 162 dots, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
8.2.45 SETVDC: set internal digital and GRAM voltage (BCh)
BC H
Command
st
1 parameter
Description
Restrictions
SETVDC (set internal digital and GRAM voltage)
DNC NWR NRD D17-8 D7
D6
D5
D4
D3
D2
D1
D0
HEX
0
↑
1
1
0
1
1
1
1
0
0
BC
1
↑
1
VDC_SEL[2:0] (100)
08
This command is used to set internal digital and GRAM voltage.
The VDC_SEL setting table:
Set VREF @ VDC_SEL[2:0] VDDD
0
0
0
1.28
0
0
1
1.34
0
1
0
1.38
0
1
1
1.44
1.8 V
1
0
0
1.5
1
0
1
1.6
1
1
0
1.7
1
1
1
1.8
If EXTC is high or enable SETEXTC command (even EXTC = low) can enable this command
Register
Availability
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In or Booster Off
Default
Status
Power On Sequence
S/W Reset
H/W Reset
Flow Chart
Availability
Yes
Yes
Yes
Yes
Yes
Default Value
VDC_SEL[2:0]=100
No change
VDC_SEL[2:0]=100
-
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.182Apr, 2010
HX8353-D
132RGB x 162 dots, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
8.2.46 SETSTBA: set source option (C0h)
C0 H
Command
st
1 parameter
nd
2 parameter
rd
3 parameter
th
4 parameter
th
5 parameter
th
6 parameter
Description
Restrictions
SETSTBA ( Set Source Option)
DNC NWR NRD D17-8 D7
D6
D5
D4
D3
D2
D1
D0
HEX
0
↑
1
1
1
0
0
0
0
0
0
C0
1
↑
1
N_OPON[7:0]
18
1
↑
1
I_OPON[7:0]
08
1
↑
1
STBA[15:8]
0C
1
↑
1
STBA[7:0]
C4
1
↑
1
GENON[7:0]
10
OTP_S1B 00
1
↑
1
This command is used to set source option setting.
Internal used, not open.
If EXTC is high or enable SETEXTC command (even EXTC = low) can enable this command
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In or Booster Off
Register
Availability
Status
Power On Sequence
Default
S/W Reset
H/W Reset
Flow Chart
Availability
Yes
Yes
Yes
Yes
Yes
Default Value
N_OPON[7:0]=8’h20, I_OPON[7:0]=8’h10,
STBA[15:0]=16’h0000, GENON[7:0]=8’h16, OTP_S1B=0
No change
N_OPON[7:0]=8’h20, I_OPON[7:0]=8’h10,
STBA[15:0]=16’h0000, GENON[7:0]=8’h16, OTP_S1B=0
-
Himax Confidential
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in whole or in part without prior written permission of Himax.
-P.183Apr, 2010
HX8353-D
132RGB x 162 dots, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
8.2.47 SETTID: set ID (C3h)
C3 H
SETID ( Set ID)
DNC NWR NRD D17-8 D7
D6
D5
D4
D3
D2
D1
D0
HEX
Command
0
↑
1
1
1
0
0
0
0
1
1
C3
st
1 parameter
1
↑
1
ID1[7:0]
00
nd
2 parameter
1
↑
1
ID2[7:0]
80
rd
1
↑
1
ID3[7:0]
00
3 parameter
Description This command is used to set ID.
Restrictions If EXTC is high or enable SETEXTC command (even EXTC = low) can enable this command
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In or Booster Off
Register
Availability
Status
Power On Sequence
S/W Reset
H/W Reset
Default
Flow Chart
Availability
Yes
Yes
Yes
Yes
Yes
Default Value
OTP value
No Change
OTP value
-
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.184Apr, 2010
HX8353-D
132RGB x 162 dots, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
8.2.48 SETUADJ: (C6h)
C6 H
Command
st
1 parameter
Description
Restrictions
SETUADJ
DNC NWR NRD D17-8 D7
D6
D5
D4
D3
D2
D1
D0
HEX
0
↑
1
1
1
0
0
0
1
1
0
C6
1
↑
1
I_UADJ[2:0]
N_UADJ[2:0]
33
This command is used to set UADJ.
If EXTC is high or enable SETEXTC command (even EXTC = low) can enable this command
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In or Booster Off
Register
Availability
Status
Power On Sequence
S/W Reset
H/W Reset
Default
Flow Chart
Availability
Yes
Yes
Yes
Yes
Yes
Default Value
I_UADJ[2:0]=03 ; N_UADJ[2:0]=03
No Change
I_UADJ[2:0]=03 ; N_UADJ[2:0]=03
-
UADJ
Trimming Freq
0 0 0
228.6%
0 0 1
123.9%
0 1 0
112.0%
0 1 1
100.0%
1 0 0
87.9%
1 0 1
75.8%
1 1 0
63.6%
1 1 1
51.3%
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.185Apr, 2010
HX8353-D
132RGB x 162 dots, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
8.2.49 SETCLOCK: (CBh)
CB H
SETECO
DNC NWR NRD D17-8
Command
0
↑
1
st
1 parameter
1
↑
1
nd
2 parameter
1
↑
1
Description
Restrictions
-
D6
D5
1
0
CADJ[3:0]
-
D4
0
D3
1
-
D2
0
-
D1
1
-
D0
1
-
HEX
CB
20
-
-
-
-
DCCLK_
SYNC
01
-
This command is used to set CLOCK.
If EXTC is high or enable SETEXTC command (even EXTC = low) can enable this command
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In or Booster Off
Register
Availability
Status
Power On Sequence
S/W Reset
H/W Reset
Default
Flow Chart
D7
1
Availability
Yes
Yes
Yes
Yes
Yes
Default Value
CADJ[3:0] (1000) ; DCCLK_SYNC(1)
No Change
CADJ[3:0] (1000) ; DCCLK_SYNC(1)
CADJ[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Trimming Freq
111.9%
110.3%
108.7%
107.1%
105.7%
104.1%
102.7%
101.3%
100.0%
98.6%
97.4%
96.2%
94.9%
93.7%
92.6%
91.5%
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.186Apr, 2010
HX8353-D
132RGB x 162 dots, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
8.2.50 SETPANEL: set panel characteristic (CCh)
CCH
Command
st
1 parameter
Description
Restrictions
SETPANEL( Set Panel Characteristic Register)
DNC NWR NRD D17-8 D7
D6
D5
0
↑
1
1
1
0
D3
D2
D1
D0
HEX
1
1
0
0
CC
SS_
REV_
GS_P
BGR_
1
↑
1
PAN
PANE
00
ANEL
PANEL
EL
L
This command is used to set Panel characteristic related register
REV_PANEL: The source output data polarity selected. When REV_PANEL=0, normally
white panel is selected. When REV_PANEL = 1, normally black panel is selected.
BGR_PANEL: The color filter order direction selected. When BGR_PANEL=0, don’t reverse
the SRGB setting. When BGR_PANEL = 1, the color filter order will be reversed.
GS_PANEL: The gate driver output shift direction selected. When GS_PANEL=0, the shift
direction don’t reverse. When GS_PANEL = 1, the shift direction will be reversed.
SS_PANEL: The source driver output shift direction selected. When SS_PANEL=0, the shift
direction don’t reverse. When SS_PANEL = 1, the shift direction will be reversed.
If EXTC is high or enable SETEXTC command (even EXTC = low) can enable this command
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In or Booster Off
Register
Availability
Status
Power On Sequence
Default
S/W Reset
H/W Reset
Flow Chart
D4
0
Availability
Yes
Yes
Yes
Yes
Yes
Default Value
SS_PANEL=0, GS_PANEL=0,
REV_PANEL=0, BGR_PANEL=0
No change
SS_PANEL=0, GS_PANEL=0,
REV_PANEL=0, BGR_PANEL=0
-
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.187Apr, 2010
HX8353-D
132RGB x 162 dots, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
8.2.51 GETHID: Read Product ID (D0h)
D0H
Command
st
1 parameter
st
2 parameter
Description
Restrictions
GETHID (Read Product ID)
DNC NWR NRD D17-8 D7
D6
D5
D4
D3
D2
D1
D0
HEX
0
↑
1
1
1
0
1
0
0
0
0
D0
1
↑
1
Dummy Read
xx
1
↑
1
Product ID [7:0] (0110_0100)
64
This command is used to Read Product ID
If EXTC is high or enable SETEXTC command (even EXTC = low) can enable this command
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In or Booster Off
Register
Availability
Status
Power On Sequence
S/W Reset
H/W Reset
Default
Flow Chart
Availability
Yes
Yes
Yes
Yes
Yes
Default Value
Product ID [7:0]=64H
No change
Product ID [7:0]=64H
-
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.188Apr, 2010
HX8353-D
132RGB x 162 dots, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
8.2.52 SETGAMMA: set gamma curve (E0h)
E0H
Command
st
1 parameter
nd
2 parameter
rd
3 parameter
th
4 parameter
th
5 parameter
th
6 parameter
th
7 parameter
th
8 parameter
th
9 parameter
th
10 parameter
st
11 parameter
nd
12 parameter
rd
13 parameter
th
14 parameter
th
15 parameter
th
16 parameter
th
17 parameter
th
18 parameter
th
19 parameter
SETGAMMA ( Set Gamma Curve Related Setting)
DNC NWR NRD D17-8 D7
D6
D5
D4
↑
1
1
1
1
0
0
1
↑
1
MP1[2:0]
1
↑
1
MP3[2:0]
1
↑
1
MP5[2:0]
1
↑
1
1
↑
1
CP2[3:0]
1
↑
1
1
↑
1
1
↑
1
1
↑
1
1
↑
1
1
↑
1
MN1[2:0]
1
↑
1
MN3[2:0]
1
↑
1
MN5[2:0]
1
↑
1
1
↑
1
CN2[3:0]
1
↑
1
1
↑
1
1
↑
1
1
↑
1
-
D3
0
-
D2
0
D1
D0
0
0
MP0[2:0]
MP2[2:0]
MP4[2:0]
CP0[3:0]
CP1[3:0]
CP3[3:0]
CP4[3:0]
OP0[3:0]
OP1[4:0]
CGM1[1:0]
CGM0[1:0]
MN0[2:0]
MN2[2:0]
MN4[2:0]
CN0[3:0]
CN1[3:0]
CN3[3:0]
CN4[3:0]
ON0[3:0]
ON1[4:0]
Description
This command is used for Gamma Curve related Setting.
For details, please refer to Section 7.2.
Restrictions
If EXTC is high or enable SETEXTC command (even EXTC = low) can enable this command
Register
Availability
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In or Booster Off
Default
Status
Power On Sequence
S/W Reset
H/W Reset
Flow Chart
HEX
E0
77
73
00
0D
4F
08
09
00
0F
0A
77
40
00
09
48
0F
0D
0F
00
Availability
Yes
Yes
Yes
Yes
Yes
Default Value
GC0 value
No change
GC0 value
-
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.189Apr, 2010
HX8353-D
132RGB x 162 dots, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
8.2.53 SETEQ: set EQ (E3h)
E3H
SETEQ( Set EQ)
DNC NWR NRD D17-8
D7
D6
D5
D4
D3
D2
D1
D0
HEX
Command
0
↑
1
1
1
1
0
0
0
1
1
E3
st
1
↑
1
EQVCI_M1[7:0]
18
1 parameter
nd
1
↑
1
EQGND_M1[7:0]
08
2 parameter
rd
1
↑
1
EQVCI_M0[7:0]
00
3 parameter
th
1
↑
1
EQGND_M0[7:0]
08
4 parameter
th
1
↑
1
PREOE_M0[7:0]
00
5 parameter
th
1
↑
1
PREOE_M1[7:0]
00
6 parameter
Description Internal used, not open.
Restrictions If EXTC is high or enable SETEXTC command (even EXTC = low) can enable this command
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In or Booster Off
Register
Availability
Status
Power On Sequence
Default
S/W Reset
H/W Reset
Flow Chart
Availability
Yes
Yes
Yes
Yes
Yes
Default Value
EQVCI_M1[7:0]=8’h10, EQGND_M1[7:0]=8’h08,
EQVCI_M0[7:0]=8’h08, EQGND_M0[7:0]=8’h10,
PREOE_M0[7:0]=8’h00, PREOE_M1[7:0]=8’h00
No change
EQVCI_M1[7:0]=8’h10, EQGND_M1[7:0]=8’h08,
EQVCI_M0[7:0]=8’h08, EQGND_M0[7:0]=8’h10,
PREOE_M0[7:0]=8’h00, PREOE_M1[7:0]=8’h00
-
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.190Apr, 2010
HX8353-D
132RGB x 162 dots, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
9. Layout Recommendation
Alignmentmark
(-4841,-220)
DUMMY
No. 759
DUMMY
G161
G159
G157
G155
G153
G151
G149
No.1
10 ohm
EXTC
100 ohm
BS0
100 ohm
BS1
100 ohm
10 ohm
100 ohm
10 ohm
10 ohm
10 ohm
P68
10 ohm
10 ohm
BGR_PANEL
100 ohm
SS_PANEL
100 ohm
GS_PANEL
100 ohm
REV_PANEL
10 ohm
100 ohm
10 ohm
10 ohm
10 ohm
10 ohm
10 ohm
10 ohm
10 ohm
LC_SEL0
100 ohm
LC_SEL1
100 ohm
10 ohm
RSO2
10 ohm
100 ohm
RSO1
10 ohm
100 ohm
RSO0
10 ohm
100 ohm
10 ohm
GC_SEL
SPI_SEL
100 ohm
100 ohm
10 ohm
TEST1
OSC
VCI
100 ohm
100 ohm
10 ohm
10 ohm
NRD_E
DNC_SEL
STE_SEL
100 ohm
100 ohm
100 ohm
10 ohm
DB17
DB16
DB15
DB14
DB13
DB12
DB11
DB10
DB9
DB8
DB1
DB3
DB5
DB7
TE
NRESET
NCS
DB6
DB4
DB2
BS2
DB0_SDA
NWR_NWR
100 ohm
100 ohm
100 ohm
100 ohm
100 ohm
100 ohm
100 ohm
100 ohm
100 ohm
100 ohm
100 ohm
100 ohm
100 ohm
100 ohm
100 ohm
100 ohm
100 ohm
100 ohm
100 ohm
100 ohm
100 ohm
100 ohm
100 ohm
10 ohm
TS7
IOVCC
EXTC
VSSD
BS0
IOVCC
BS1
VSSD
P68
IOVCC
DUMMY
VSSD
DUMMY
IOVCC
BGR_ PANEL
VSSD
SS_ PANEL
IOVCC
GS_ PANEL
VSSD
DUMMY
IOVCC
REV_ PANEL
VSSD
DUMMY
IOVCC
DUMMY
VSSD
DUMMY
IOVCC
LC_SEL0
VSSD
LC_SEL1
IOVCC
RSO2
VSSD
RSO1
IOVCC
RSO0
VSSD
DUMMY
GC_SEL
SPI_SEL
IOVCC
TS6
TS5
TS4
TS3
TEST1
OSC
VCI
VCI
VCI
VCI
VCI
VCI
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
NRD_E
DNC_SCL
STE_SCL
VSSD
DB17
DB16
DB15
DB14
DB13
DB12
DB11
DB10
DB9
DB8
DB1
DB3
DB5
DB7
TE
NRESET
NCS
DB6
DB4
DB2
BS2
DB0_SDA
NWR_RNW
DUMMY
DUMMY
DUMMY
DUMMY
TS2
TS1
TS0
VSSD
VSSD
VSSD
VSSD
VSSD
VSSD
IOVCC
IOVCC
IOVCC
IOVCC
IOVCC
IOVCC
VDDD
VDDD
VDDD
DUMMY
DUMMY
DUMMY
IOVCC
10 ohm
VDDD
10 ohm
VBGP
100 ohm
VBGP
VBGP
100 ohm
TEST2
VTESTOUT
G147
Display Panel
G7
G5
G3
G1
DUMMY
DUMMY
DUMMY
DUMMY
S1
S2
S3
S4
Face Up
(Bump view)
HX8353-D
Pin Assignment
S195
S196
S197
S198
DUMMY
DUMMY
(0,0)
Y
DUMMY
DUMMY
S199
S200
X
S201
S202
VBGP
TEST2
VTESTOUT
100 ohm
DDVDH
DDVDH
DDVDH
10 ohm
VREG1
100 ohm
DDVDH
DDVDH
VREG1
VREG1
VREG1
DUMMYR1
100 ohm
DUMMYR2
10 ohm
C11A
C11A
C11A
10 ohm
C11A
C11B
C11B
C11B
50 ohm
C11B
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
VSSA
VSSA
10 ohm
S393
S394
VSSA
VCL
VCL
VCL
10 ohm
S395
S396
DUMMY
DUMMY
DUMMY
DUMMY
10 ohm
DUMMY
G2
10 ohm
G4
G6
G8
10 ohm
10 ohm
10 ohm
10 ohm
DUMMY
VGL
VGH
VCOMH
VCOML
VGL
VGL
VGL
VGH
VGH
VGH
10 ohm
10 ohm
VCOMH
VCOMH
VCOMH
100 ohm
VCOML
VCOML
100 ohm
VCOML
VCOM
VCOM
VCOM
No. 185
G148
G150
G152
G154
G156
DUMMY
G158
G160
G162
DUMMY
DUMMY
No. 186
Alignmentmark
(4841,-220)
Figure 9.1 Layout recommendation of HX8353-D
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.191Apr, 2010
HX8353-D
132RGB x 162 dots, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
Maximum layout resistance
Name
Type
VCI
Power supply
IOVCC
Power supply
VSSA
Power supply
VSSD
Power supply
OSC
Input
EXTC
Input
P68, BS2, BS1, BS0
Input
STE_SEL, GC_SEL, SPI_SEL
Input
RSO0, RSO1, RSO2
Input
LC_SEL0, LC_SEL1
Input
NRESET, NCS, DNC_SCL
Input
NWR_RNW, NRD_E
Input
TEST2, TEST1
Input
SS_PANEL, GS_PANEL, REV_PANEL,
Input
BGR_PANEL
DUMMYR1,DUMMYR2,
Input
DB0_SDA, DB17 ~ DB1
Input / Output
VGH
Output
VGL
Output
C11A, C11B
Output
C12A, C12B
Output
C22A, C22B
Output
C21A, C21B
Output
VDDD
Output
DDVDH
Output
VCL
Output
TE
Output
VCOMH, VCOML
Output
VREG1
Output
VBGP
Output
VTESTOUT
Output
Table 9.1 Maximum layout resistance
Maximum Series
Resistance
10
10
10
10
100
100
100
100
100
100
100
100
100
Unit
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Ω
100
Ω
100
100
10
10
10
10
10
10
10
10
10
100
100
100
100
100
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Ω
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in whole or in part without prior written permission of Himax.
-P.192Apr, 2010
HX8353-D
132RGB x 162 dots, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
10. OTP Programming
OTP_INDEX
D7
00h
ID17
01h
ID27
02h
ID37
03h
VMF17
04h
VMF27
05h
VMF37
D6
ID16
ID26
ID36
VMF16
VMF26
VMF36
D5
ID15
ID25
ID35
VMF15
VMF25
VMF35
D4
ID14
ID24
ID34
VMF14
VMF24
VMF34
D3
ID13
ID23
ID33
VMF13
VMF23
VMF33
06h
-
-
-
-
-
07h
Valid_ID
-
-
-
-
D2
D1
ID12
ID11
ID22
ID21
ID32
ID31
VMF12 VMF11
VMF22 VMF21
VMF32 VMF31
Valid_VM Valid_VM
F3
F2
-
D0
Non-Program
ID10
00h
ID20
00h
ID30
00h
VMF10
00h
VMF20
00h
VMF30
00h
Valid_VM
00h
F1
00h
Table 10.1 OTP address mapping
Note: (1) The default value of OTP memory bits are all “0”.
(2) “Valid_ID” bit decide the OTP reload Enable/Disable, the default value is “0”. If the OTP index of Valid bit
had been programmed, the Valid bit will be changed to “1” automatically and execute the OTP reload.
(3) Please set the 00h(ID1) & 01h(ID2) & 02h(ID3) at the same time.
(4) VMF can be programmed three times. When programming index 03h first time, VMF1 and
Valid_VMF1 will be programmed automatically. If programming index 03h second time, VMF2 and
Valid_VMF2 will be programmed automatically. If programming index 03h third time, VMF3 and
Valid_VMF3 will be programmed automatically.
(5) The OTP programming (External 6.5V to VGH) current limit must ≧20mA.
For example:
Condition 1: Programmed all index of 0X00h, 0X01h and 0X02h
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-P.193Apr, 2010
HX8353-D
132RGB x 162 dots, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
Condition 2: Do not program all index of 0X00h, 0X01h and 0X02h
(4) There are some conditions that HX8353-D can reload OTP.
1.Hardware reset
2.Software reset
3.SLPOUT command.
(5) User can use GETOTP command to read back the OTP values. Similarly, the user also can use
GETOTP to read the index 0x06h that is defined the VALID bit for VMF1, VMF2 and VMF3
(Valid_VMF1, Valid_VMF2 and Valid_VMF3) to know how many times of VMF had programmed on
OTP.
Valid_VMF3
Valid_VMF2
Valid_VMF1
Programmed 0 time
0
0
0
Programmed 1 time
0
0
1
Programmed 2 times
0
1
1
Programmed 3 times
1
1
1
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-P.194Apr, 2010
HX8353-D
132RGB x 162 dots, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
10.1 Programming flow
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-P.195Apr, 2010
HX8353-D
132RGB x 162 dots, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
10.2 OTP Programming example for VMF1
VMF1 Program Flow
Power On
Set DCCLK_Disable = 1
(RBBH = 0x00H、0x00H、
0x40H、0x00H、0x00H)
H/W Reset
Wait 5mS
Connect external power 6.5V to VGH
SLPOUT (R11H)
Set OTP_EN = 1
(RBBH = 0x00H、0x03H、
0x48H)
Wait 120mS
Set OTP_EN = 0
(RBBH = 0x00H、0x03H、
0x40H)
Remove external power 6.5V to VGH
SETEXTC
Delay 1mS for OTP program
(RB9H = 0xFFH、0x83H、0x53H)
Reset IC to reload OTP data
SET VMF
(RB6H = 0x??H、VMH、VML)
Yes
Program another VMF value
No
END
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-P.196Apr, 2010
HX8353-D
132RGB x 162 dots, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
10.3 Programming sequence
Step
1
2
3
4
5
6
7
8
9
10
11
12
13
Operation
Power on and reset the module
Set OTP_LOAD_DISABLE=1, disable the auto-loading function.
SLPOUT command (11h)
Wait 120ms
Write optimized value to related register.
Set OSC_EN=0, disable internal pumping clock.
Connect external power 6.5V to VGH pin
Wait 100ms for external power 6.5V to stabilize.
Specify OTP_index. Reference OTP address mapping table
Set OTP_Mask=0x00h, programming the entire bit of one parameter.
Set OTP_EN=1, Internal register begin write to OTP according to OTP_index.
Wait 1 ms
Complete programming one parameter to OTP. If continue to programming other parameter, return to
step (9). Otherwise, power off the module and remove the external power on VGH pin.
10.4 OTP Read flow and example
Power On
H/W Reset
Wait 5mS
SLPOUT (R11H)
Wait 120mS
Display On (R29H)
SETEXTC
(RB9H = 0xFFH、0x83H、0x53H)
Read VMF OTP value
(RB6H = VMF、VMH、VML)
0x??H
VMF
Programmed
0x9EH
or
Initial code setting
VMF not
Programmed
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-P.197Apr, 2010
HX8353-D
132RGB x 162 dots, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
10.5 Programming circuitry
Himax Confidential
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-P.198Apr, 2010
HX8353-D
132RGB x 162 dots, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
11. Electrical Characteristic
11.1 Absolute maximum ratings
Item
Power Supply Voltage 1
Power Supply Voltage 2
Power Supply Voltage 3
Power Supply Voltage 4
Power Supply Voltage 5
Power Supply Voltage 6
Power Supply Voltage 7
Logic Input Voltage
Logic Output Voltage
Operating Temperature
Storage Temperature
Symbol
IOVCC~VSSD
VCI ~ VSSA
DDVDH ~ VSSA
VSSA ~ VCL
DDVDH ~ VCL
VGH ~ VSSA
VSSA ~ VGL
VIN
Vo
Topr
Tstg
Unit
V
V
V
V
V
V
V
V
V
℃
℃
Value
-0.3 to +4.6
-0.3 to +4.6
-0.3 to +6.6
-0.3 to +4.6
-0.3 to +9
-0.3 to +18.5
0 to -16
-0.3 to IOVCC+0.5
-0.3 to IOVCC+0.5
-30 to +80
-55 to +110
Note
(1),(2)
Note
(3)
Note
(4)
Note
(5)
Note
(6)
Note
(7)
Note
(8)
Note
(9),(10)
Note
(9),(10)
Note
Note: (1) IOVCC, VSSD must be maintained.
(2) To make sure IOVCC ≥ VSSD.
(3) To make sure VCI ≥ VSSA.
(4) To make sure DDVDH ≥ VSSA.
(5) To make sure VSSA ≥ VCL.
(6) To make sure DDVDH ≥ VCL.
(7) To make sure VGH ≥ VSSA.
(8) To make sure VSSA ≥ VGL
VGH +|VGL| < 32V
(9) For die and wafer products, specified up to +80℃.
Table 11.1 Absolute maximum ratings
11.2 ESD protection level
Mode
Human Body Model
Machine Model
Test Condition
Protection Level
±2.0K
C=100pF, R=1.5kΩ
±200
C=200pF, R=0.0Ω
Table 11.2 ESD protection level
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Unit
V
V
-P.199Apr, 2010
HX8353-D
132RGB x 162 dots, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
11.3 DC characteristics
Parameter
Symbol
Power & Operating Voltages
IO Operating voltage
IOVCC
Driver Operating
VCI
voltage
Source Drive Voltage
VREG1
Min.
Spec.
Typ.
Max.
I/O supply voltage
1.65
1.8
3.3
Operation voltage
2.5
2.8
3.3
Dual Pump
3.3
4.65
4.8
-
-
-
9.5
10.3
11.25
11.75
12.25
13
10
10.8
11.5
12
12.5
13.25
10.5
11.3
11.75
12.25
12.75
13.5
Conditions
Unit
Gate Drive Low Voltage
VGL
Drive Supply Voltage
Input / Output
High level input voltage
Low level input voltage
High level output
voltage
Low level output voltage
Input leakage current
|VGH-VGL|
VCI=2.8 Dual Pump
(Typ:BT=000)
IVGH=30µA
IVGH=25µA
IVGH=20µA
IVGH=15µA
IVGH=10µA
IVGH=5µA
VCI=2.8 Dual Pump
(Typ:BT=000)
IVGL=30µA
IVGL=25µA
IVGL=20µA
IVGL=15µA
IVGL=10µA
IVGL=5µA
-
VIH
VIL
-
0.7*IOVCC
VSSD
-
IOVCC
0.3*IOVCC
VOH
IOH = -1.0mA
0.8*IOVCC
-
IOVCC
VOL
IIL
IOL = +1.0mA
Frame rate at
75hz,default Vs and
Hs setting
TA=25℃
VSSD
-1
-
0.2*IOVCC
1
µA
1.387
1.46
1.533
MHz
Gate Drive High
Voltage
Oscillator frequency
VGH
fOSC
-
-
-
-8.05
-8.75
-9.25
-9.75
-10.35
-10.85
-
-8.2
-8.9
-9.4
-9.9
-10.5
-11
-
-8.35
-9.05
-9.55
-10.05
-10.65
-11.15
30
V
V
Booster (VCI=2.8V)
DDVDH boost voltage1
DDVDH
VCL boost voltage
VCL
VCOM Generator (VCI=2.8V)
Dual Pump
IDDVDH=300µA
ICL=-100µA
4.8
5.0
5.2
-2.5
-2.65
2.75
V
VCOM amplitude
VCOM
No load, Dual Pump
2.5
4.4
7.3
V
VCOM high level
VCOMH
No load, Dual Pump
2.5
3.205
4.8
V
No load
-2.5
-1.195
VSSD
V
VCOM low level
VCOML
Source Driver (Typ:TA=25℃ VCI=2.8V)
VSSD+1.0 ~
+/- 10
+/- 20
VREG1-1.0
VSSD+0.1V ~
DVOS
VSSD+1.0
+/- 30
+/- 50
VREG1-1.0 ~
VREG1-0.1V
Output voltage range
VOS
0.1
DDVDH-0.1
Output offset voltage
Voff
+/-30
+/-50
Note: VREG1/VCOMH/VCOML conditions: When Internal Voltage VREF=4.8V for dual pump
Output voltage
deviation
(mean value)
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mV
mV
V
mV
-P.200Apr, 2010
HX8353-D
132RGB x 162 dots, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
Measurement point
FPC
Measurement point
LCD Panel
Connector pin or flex side
Himax Confidential
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in whole or in part without prior written permission of Himax.
-P.201Apr, 2010
HX8353-D
132RGB x 162 dots, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
11.3.1 Current consumption
Host
I/F
Mode of
operation
Frame
Frequency
Inversion
Mode
1-line
Host interface active
Host interface NOT active
- Normal Mode
On
- Partial Mode Off
- Idle Mode Off
- Sleep Out Mode
- Normal Mode
On
- Partial Mode Off
- Idle Mode On
- Sleep Out Mode
- Normal Mode
Off
- Partial Mode On
(32 lines)
- Idle Mode Off
- Sleep Out Mode
- Normal Mode
Off
- Partial Mode On
(32 lines)
- Idle Mode On
- Sleep Out Mode
- Sleep In Mode
- Deep Sleep In
Mode
- Normal Mode
On
- Partial Mode Off
- Idle Mode Off
- Sleep Out Mode
Image
Memory
Data
Access
Control
(MY:MX:MV)
X;X;X
Current consumption
Typical
Worst case
VCI
(mA)
IOVCC
(uA)
VCI
(mA)
IOVC
C(uA)
1.2
2.5
1.48
3
X;X;X
1.17
2.5
1.45
3
X;X;X
1.25
2.5
1.46
3
X;X;X
1.18
2.5
1.4
3
X;X;X
1.14
2.5
1.3
3
1-line
Black
1x1 checker
board
4x4 checker
board
Grayscale
Top to
Bottom
20B80W
60Hz
1-line
20B80W
X;X;X
0.67
2.5
0.77
3
60Hz
1-line
Grey
Levels
X;X;X
0.72
2.5
0.82
3
1-line
8x8 checker
board
X;X;X
0.52
2.5
0.58
3
1-line
Worst
pattern
X;X;X
0.55
2.5
0.62
3
N/A
N/A
N/A
X;X;X
2µA
2.5
80µA
10
N/A
N/A
N/A
X;X;X
0.1µA
0.1
1µA
1
0;0;0
0;0;1
0;1;0
0;1;1
1;0;0
1;0;1
1;1;0
1;1;1
0;0;0
0;0;1
0;1;0
0;1;1
1;0;0
1;0;1
1;1;0
1;1;1
1.28
1.28
1.28
1.28
1.28
1.28
1.28
1.28
1.3
1.3
1.3
1.3
1.3
1.3
1.3
1.3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.55
1.55
1.55
1.55
1.55
1.55
1.55
1.55
7
7
7
7
7
7
7
7
12
12
12
12
12
12
12
12
1-line
60Hz
1-line
1-line
60Hz
262k Colors
Worst
pattern
CPU
Access
@ 15fps
60Hz
1-line
262k Colors
Worst
pattern
CPU
Access
@ 25fps
Table 11.3 Current consumption
Typical Case:
TA = 25°C
IOVCC=1.8V
VCI = 2.8V
Worst Case:
TA = -30 to80°C
IOVCC = 1.65V to 1.95V
VCI = 2.5V to 3.3V
Includes Process Variance.
Himax Confidential
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-P.202Apr, 2010
HX8353-D
132RGB x 162 dots, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
11.4 AC characteristics
11.4.1 Parallel interface characteristics (8080-series MPU)
Figure 11.1 Parallel interface characteristics (8080-series MPU)
(VSSA=0V, IOVCC=1.65V to 3.3V, VCI=2.5V to 3.3 V, TA = -30 to 70°C)
Signal
Symbol
Parameter
Min. Max.
Unit
tAST
Address setup time
0
DNC_SCL
ns
tAHT
Address hold time (Write/Read)
10
tCHW
Chip select “H” pulse width
0
tCS
Chip select setup time (Write)
15
tRCS
Chip select setup time (Read ID)
45
NCS
ns
tRCSFM
Chip select setup time (Read FM)
355
Chip select wait time (Write/Read)
tCSF
10
tCSH
Chip select hold time
10
tWC
Write cycle
66
Control pulse “H” duration
15
ns
NWR_SCL
tWRH
tWRL
Control pulse “L” duration
15
tRC
Read cycle (ID)
160
NRD_E (ID)
tRDH
Control pulse “H” duration (ID)
90
ns
tRDL
Control pulse “L” duration (ID)
45
tRCFM
Read cycle (FM)
450
NRD_E (FM)
tRDHFM
Control pulse “H” duration (FM)
90
ns
tRDLFM
Control pulse “L” duration (FM)
355
tDST
Data setup time
10
tDHT
Data hold time
10
D17 to D0
tRAT
Read access time (ID)
40
ns
tRATFM
Read access time (FM)
340
tODH
Output disable time
20
80
Note: The input signal rise time and fall time (tr, tf) is specified at 15 ns or less.
Logic high and low levels are specified as 30% and 70% of IOVCC for Input signals.
tr
tf
tr
Description
-
-
-
When read ID data
When read from frame
memory
For maximum CL=30pF
For minimum CL=8pF
tf
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-P.203Apr, 2010
HX8353-D
132RGB x 162 dots, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
Figure 11.2 Chip select timing
Figure 11.3 Write to read and read to write timing
Himax Confidential
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-P.204Apr, 2010
HX8353-D
132RGB x 162 dots, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
11.4.2 Serial interface characteristics
Figure 11.4 Serial interface characteristics
(VSSA=0V, IOVCC=1.65V to 3.3V, VCI=2.5V to 3.3 V, TA= -30 to 70°C)
Parameter
Serial clock cycle (Write)
DNC_SCL ”H” pulse width (Write)
DNC_SCL ”L” pulse width (Write)
Data setup time (Write)
Data hold time (Write)
Serial clock cycle (Read)
DNC_SCL ”H” pulse width (Read)
DNC_SCL ”L” pulse width (Read)
Symbol
tSCYCW
tSHW
tSLW
tSDS
tSDH
tSCYCR
tSHR
tSLR
Access Time
tACC
Output disable time
tOH
DNC_SCL to Chip select
NCS “H” pulse width
Chip select setup time
Chip select hold time
tSCC
tCHW
tCSS
tCSH
Conditions
DNC_SCL
SDA
DNC_SCL
SDI for maximum
CL=30pF
For minimum CL=8pF
SDO For maximum
CL=30pF
For minimum CL=8pF
DNC_SCL, NCS
NCS
NCS
Min.
66
15
15
10
10
150
60
60
Typ.
Max.
-
Unit
10
-
50
ns
15
-
50
ns
15
40
60
65
-
-
ns
ns
-
-
ns
ns
ns
ns
Note: The input signal rise time and fall time (tr, tf) is specified at 15 ns or less.
Logic high and low levels are specified as 30% and 70% of IOVCC for Input signals.
tr
tf
tr
tf
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-P.205Apr, 2010
HX8353-D
132RGB x 162 dots, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
11.4.3 Reset input timing
Figure 11.5 Reset input timing
Symbol
tRESW
Parameter
(1)
Reset low pulse width
Related
Pins
NRESET
Min.
10
Spec.
Typ. Max.
-
Note
Unit
-
µs
When reset applied during
5
ms
Sleep In mode
(2)
tREST
Reset complete time
When reset applied during
ms
120 Sleep Out mode
Note: (1) Spike due to an electrostatic discharge on !RES line does not cause irregular system reset according to the
following table.
NRESET Pulse
Shorter than 5 µs
Longer than 10 µs
Between 5 µs and 10 µs
Action
Reset Rejected
Reset
Reset Start
(2) During the resetting period, the display will be blanked (The display is entering blanking sequence, which
Maximum time is 120 ms, when Reset Starts in Sleep Out –mode. The display remains the blank state in Sleep
In –mode) and then return to Default condition for H/W reset.
(3) During Reset Complete Time, ID2 and VCOMOF value in OTP will be latched to internal register during this
period. This loading is done every time when there is H/W reset complete time (tREST) within 5ms after a rising
edge of NRESET.
(4) Spike Rejection also applies during a valid reset pulse as shown as below:
10us
Reset is accepted
10us
Less than 20ns width positive spike will be rejected.
(5) It is necessary to wait 5msec after releasing NRESET before sending commands. Also Sleep Out command
cannot be sent for 120msec.
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-P.206Apr, 2010
HX8353-D
132RGB x 162 dots, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
11.5 tACC, tOH Measurement Condition
Measurement condition set-up
Oscilloscope
See “NOTE”
Data Generator
Connector
LCD Panel
FPC
External components for test condition
(pull-down and pull-up cases) which are
removed after test:
Resistor: 3kOhm ± 5%
Capacitor: 8 or 30pF ± 10%
Connector Pin / Measurement Point
See “NOTE”
Note: Capacitances and resistances of the oscilloscope’s probe must be included externals components in
these measurements
Figure 11.6 tACC and tOH measurement condition set-up
Minimum value measurement
Figure 11.7 tACC and tOH minimum value measurement
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-P.207Apr, 2010
HX8353-D
132RGB x 162 dots, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
Maximum value measurement
Figure 11.8 tACC and tOH maximum value measurement
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-P.208Apr, 2010
HX8353-D
132RGB x 162 dots, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
12. Reference Application
12.1 I80 system
G158
G160
G162
DUMMY
DUMMY
S394
S395
S396
DUMMY
DUMMY
DUMMY
DUMMY
G2
G4
G6
DUMMY
DUMMY
S199
S200
S197
S198
DUMMY
DUMMY
G5
G3
G1
DUMMY
DUMMY
DUMMY
DUMMY
S1
S2
S3
DUMMY
DUMMY
G161
G159
G157
HIMAX
EXTC
BS0
BS1
P68
BGR_PANEl
SS_PANEL
GS_PANEL
REV_PANEL
LC_SEL0
LC_SEL1
RSO2
RSO1
RSO0
GC_SEL
SPI_SEL
TEST1
OSC
VCI
VSSA
NRD_E
DNC_SCL
STE_SEL
DB17
DB16
DB15
DB14
DB13
DB12
DB11
DB10
DB9
DB8
DB1
DB3
DB5
DB7
TE
NRESET
NCS
DB6
DB4
DB2
BS2
DB0_SDA
NWR_RNW
VSSD
IOVCC
VDDD
VBGP
TEST2
VTESTOUT
DDVDH
VREG1
C11A
C11B
VSSA
VCL
C21A
C21B
C22A
C22B
C12A
C12B
VGL
VGH
VCOMH
VCOML
VCOM
i80 Interface
VGL
VGH
VCOMH
VCOML
VCOM
VSSA
VCL
VTESTOUT
DDVDH
VREG1
C2
1uF/16V
VSSD
C1
1uF/6.3V
C3
1uF/6.3V
IOVCC
VDDD
VBGP
NRD_E
DNC_SCL
STE_SEL
DB17
DB16
DB15
DB14
DB13
DB12
DB11
DB10
DB9
DB8
DB1
DB3
DB5
DB7
TE
NRESET
NCS
DB6
DB4
DB2
BS2
DB0_SDA
NWR_RNW
VCI
VSSA
EXTC
BS0
BS1
P68
BGR_PANEL
SS_PANEL
GS_PANEL
REV_PANEL
LC_SEL0
LC_SEL1
RSO2
RSO1
RSO0
GC_SEL
SPI_SEL
HX8353-D (BUMP UP)
Name
VCI
IOVCC
VSSA
VSSD
OSC
EXTC
P68, BS2, BS1, BS0
STE_SEL, GC_SEL, SPI_SEL
RSO0, RSO1, RSO2
LC_SEL0, LC_SEL1
NRESET, NCS, DNC_SCL
NWR_RNW, NRD_E
TEST2, TEST1
SS_PANEL, GS_PANEL
REV_PANEL, BGR_PANEL
DUMMYR1,DUMMYR2
DB0_SDA, DB17 ~ DB1
VGH
VGL
C11A, C11B
C12A, C12B
C22A, C22B
C21A, C21B
VDDD
DDVDH
VCL
TE
VCOMH, VCOML
VREG1
VBGP
VTESTOUT
Type
Power supply
Power supply
Power supply
Power supply
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input / Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Maximum Series Resistance
10
10
10
10
100
100
100
100
100
100
100
100
100
100
100
100
100
10
10
10
10
10
10
10
10
10
100
100
100
100
100
Unit
Ohm
Ohm
Ohm
Ohm
Ohm
Ohm
Ohm
Ohm
Ohm
Ohm
Ohm
Ohm
Ohm
Ohm
Ohm
Ohm
Ohm
Ohm
Ohm
Ohm
Ohm
Ohm
Ohm
Ohm
Ohm
Ohm
Ohm
Ohm
Ohm
Ohm
Ohm
IOVCC
R2 0402/0R(OPEN)
R1 0402/0R(OPEN)
EXTC
R4 0402/0R(OPEN)
R3 0402/0R(OPEN)
BS0
R6 0402/0R(OPEN)
R5 0402/0R(OPEN)
BS1
R8 0402/0R(OPEN)
R7 0402/0R(OPEN)
BS2
R10 0402/0R(OPEN)
R9 0402/0R(OPEN)
P68
R11 0402/0R(OPEN)
BGR_PANEL
RGB_PANEL
SS_PANEL
GS_PANEL
REV_PANEL
P68
BS2
BS1
BS0
RSO2
RSO1
RSO0
STE_SEL
LC_SEL0
LC_SEL1
GC_SEL
DB17
DB16
DB15
DB14
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
NRD_E
NWR_RNW
DNC_SCL
NCS
TE
IOVCC
NRESET
GND
VCI
R12 0402/0R(OPEN)
R14 0402/0R(OPEN)
R13 0402/0R(OPEN)
SS_PANEL
R16 0402/0R(OPEN)
R15 0402/0R(OPEN)
GS_PANEL
R18 0402/0R(OPEN)
R17 0402/0R(OPEN)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
REV_PANEL
VCI
VCI
GND
VCC
IOVCC
NRESET
DB23
DB22
DB21
DB20
DB19
DB18
DB17
DB16
DB15
DB14
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
NRD_E
NWR_RNW
DNC_SCL
NCS
FLM
GND
NC
NC
NC
LC_SEL0
LC_SEL1
GC_SEL
SDA
RSO2
RSO1
RSO0
STE_SEL
NC
NC
RGB_PANEL
SS_PANEL
GS_PANEL
REV_PANEL
P68
BS2
BS1
BS0
GND
BL+/NC
BL_GND/NC
J2
R20 0402/0R(OPEN)
R19 0402/0R(OPEN)
LC_SEL0
R22 0402/0R(OPEN)
R21 0402/0R(OPEN)
LC_SEL1
R24 0402/0R(OPEN)
R23 0402/0R(OPEN)
RSO2
FPC60-0.5-4.0L
R26 0402/0R(OPEN)
R25 0402/0R(OPEN)
RSO1
R28 0402/0R(OPEN)
R27 0402/0R(OPEN)
RSO0
R30 0402/0R(OPEN)
VCI1 IOVCC1
VCI
IOVCC
TE1
TE
DDVDH1 VBGP1
DDVDH VBGP
VREG2 VDDD1 VCL1
VREG1 VDDD
VCL
VGH1
VGH
VGL1
VGL
VCOMH1 VCOML1 VCOM1 VTESTOUT1 BL+1
VCOMH VCOML VCOM VTESTOUT BL+1
BL_GND1 BL+2
BL_GND1 BL+2
R29 0402/0R(OPEN)
GC_SEL
BL_GND2
BL_GND2
R32 0402/0R(OPEN)
R31 0402/0R(OPEN)
SPI_SEL
R34 0402/0R(OPEN)
R33 0402/0R(OPEN)
BL+
BL+
VTESTOUT
VCOM
VCOML
VCOMH
VGL
VGH
VCL
VDDD
VREG1
VBGP
DDVDH
TE
IOVCC
VCI
STE_SEL
Figure 12.1 80-/68- system FPC reference circuit
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.209Apr, 2010
HX8353-D
132RGB x 162 dots, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
12.2 SPI system
IOVCC
R1 0402/0R(OPEN)
R2 0402/0R(OPEN)
G158
G160
G162
DUMMY
DUMMY
S394
S395
S396
DUMMY
DUMMY
DUMMY
DUMMY
G2
G4
G6
DUMMY
DUMMY
S199
S200
S197
S198
DUMMY
DUMMY
G5
G3
G1
DUMMY
DUMMY
DUMMY
DUMMY
S1
S2
S3
DUMMY
DUMMY
G161
G159
G157
EXTC
R3 0402/0R(OPEN)
R4 0402/0R(OPEN)
BGR_PANEL
R5 0402/0R(OPEN)
R6 0402/0R(OPEN)
SS_PANEL
R7 0402/0R(OPEN)
SPI Interface
R8 0402/0R(OPEN)
GS_PANEL
R9 0402/0R(OPEN)
R10 0402/0R(OPEN)
EXTC
BS0
BS1
P68
BGR_PANEl
SS_PANEL
GS_PANEL
REV_PANEL
LC_SEL0
LC_SEL1
RSO2
RSO1
RSO0
GC_SEL
SPI_SEL
TEST1
OSC
VCI
VSSA
NRD_E
DNC_SCL
STE_SEL
DB17
DB16
DB15
DB14
DB13
DB12
DB11
DB10
DB9
DB8
DB1
DB3
DB5
DB7
TE
NRESET
NCS
DB6
DB4
DB2
BS2
DB0_SDA
NWR_RNW
VSSD
IOVCC
VDDD
VBGP
TEST2
VTESTOUT
DDVDH
VREG1
C11A
C11B
VSSA
VCL
C21A
C21B
C22A
C22B
C12A
C12B
VGL
VGH
VCOMH
VCOML
VCOM
REV_PANEL
R11 0402/0R(OPEN)
R12 0402/0R(OPEN)
LC_SEL0
R13 0402/0R(OPEN)
R14 0402/0R(OPEN)
LC_SEL1
Himax
HX8353-D (BUMP UP)
R15 0402/0R(OPEN)
R16 0402/0R(OPEN)
R17 0402/0R(OPEN)
VTESTOUT
DDVDH
VREG1
R18 0402/0R(OPEN)
VGL
VGH
VCOMH
VCOML
VCOM
RSO1
VSSA
VCL
DB0_SDA
NWR_RNW
VSSD
IOVCC
VDDD
VBGP
TE
NRESET
NCS
OSC
VCI
VSSA
IOVCC
DNC_SCL
STE_SEL
R19 0402/0R(OPEN)
R20 0402/0R(OPEN)
RSO0
R21 0402/0R(OPEN)
R22 0402/0R(OPEN)
GC_SEL
C3
1uF/16V
C1
1uF/6.3V
C2
1uF/6.3V
EXTC
BGR_PANEL
SS_PANEL
GS_PANEL
REV_PANEL
LC_SEL0
LC_SEL1
RSO2
RSO1
RSO0
GC_SEL
SPI_SEL
RSO2
R23 0402/0R(OPEN)
R24 0402/0R(OPEN)
SPI_SEL
R25 0402/0R(OPEN)
R26 0402/0R(OPEN)
RGB_PANEL
SS_PANEL
GS_PANEL
REV_PANEL
GND
LC_SEL0
LC_SEL1
GC_SEL
SPI_SEL
DB0_SDA
RSO2
RSO1
RSO0
STE_SEL
NWR_RNW
DNC_SCL
NCS
TE
GND
IOVCC
NRESET
GND
SPI_SEL: "0":3-Wire ; "1":4-Wire
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
VCI
STE_SEL
VCI
VCI
GND
VCC
IOVCC
NRESET
DB23
DB22
DB21
DB20
DB19
DB18
DB17
DB16
DB15
DB14
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
NRD_E
NWR_RNW
DNC_SCL
NCS
FLM
GND
NC
NC
LC_SEL0
LC_SEL1
GC_SEL
SPI_SEL
SDA
RSO2
RSO1
RSO0
STE_SEL
NC
NC
RGB_PANEL
SS_PANEL
GS_PANEL
REV_PANEL
P68
BS2
BS1
BS0
GND
BL+/NC
BL_GND/NC
J3
RSO2
RSO1
RSO0
0
0
0
0
132RGB X 162 (Display 132RGB X 162)
0
0
0
1
132RGB X 162 (Display 128RGB X 160)
0
0
1
X
128RGB X 128 (Display 128RGB X 128)
0
1
0
X
120RGB X 160(Display 120RGB X 160)
0
1
1
X
128RGB X 160(Display 128RGB X 160)
1
0
0
X
96RGB X 68(Display 96RGB X 68)
1
0
1
X
96RGB X 64(Display 96RGB X 64)
GND3 GND4
GND GND
TE2
TE
OSC1
OSC
TE
OSC
NCS
DNC_SCL
NWR_RNW
VCOMH
NRD_E1 NWR_RNW1 DNC_SCL1 NCS1
NRD_E NWR_RNW DNC_SCL NCS
NRD_E
VGH
NRESET1
NRESET
NRESET
VGL
VCOM
VCOMH2 VCOML2 VCOM2
VCOMH VCOML VCOM
VCOML
VGH2
VGH
VCL
VGL2
VGL
VREG1
DDVDH2 VREG3 VCL2
DDVDH VREG1 VCL
DDVDH
VBGP
VDDD
VTESTOUT2VDDD2 VBGP2
VTESTOUT VDDD VBGP
VTESTOUT
IOVCC
1
BGR_PANEL
R -> G -> B
B -> G -> R
SS_PANEL
S1 -> S396
S396 -> S1
GS_PANEL
G1 -> G162
REV_PANEL
Normally White Panel
G162 -> G1
Normally Black Panel
Note: SS_PANEL and GS_PANEL is base on RSO[2:0]="000", other
RSO[2:0] setting please reference "Pin Description"
FPC60-0.5-4.0L
VCI
GRAM Resolution
0
1. VCI, IOVCC are separated from different power source
to get better display quality.
2. The input pin must be fixed IOVCC or GND when no use. Refer to "Pin Description".
VCI2 IOVCC2
VCI
IOVCC
STE_SEL
Figure 12.2 SPI FPC reference circuit
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.210Apr, 2010
HX8353-D
132RGB x 162 dots, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
12.3 1st Pixel is at right-bottom of the panel & RGB filter order = RGB
G161
G160
Driver IC (Bump down)
G3
S390
S7
00H 01H
02H
----------------------------------------------------------------------------------- 7DH 7EH
G2
7FH
G1
G2
Direction default setting (H/W)
G3
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G4
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00H
G157
SMX = 1
SMY = 1
SRGB = 0
S1 = Filter B
S2 = Filter G
S3 = Filter R
Display direction control (S/W)
X – Mirror control by MX
Y – Mirror control by MY
XY – Exchange control by MV
G158
G159
G160
1st Pixel
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.211Apr, 2010
HX8353-D
132RGB x 162 dots, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
12.4 1st Pixel is at left-top of the panel & RGB filter order = BGR
G161
G160
Driver IC (Bump down)
G3
S390
S7
00H 01H
02H
----------------------------------------------------------------------------------- 7DH 7EH
G2
7FH
G1
G2
Direction default setting (H/W)
G3
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G4
1st Pixel
G157
00H
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SMX = 0
SMY = 0
SRGB = 1
S1 = Filter B
S2 = Filter G
S3 = Filter R
Display direction control (S/W)
X – Mirror control by MX
Y – Mirror control by MY
XY – Exchange control by MV
G158
G159
G160
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.212Apr, 2010
HX8353-D
132RGB x 162 dots, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
12.5 Application of connection with Different resolution
Case 1 of resolution (128RGB x 160) (RSO[2:0] = 011) RAM size = 128 x 160 x 18-bits (Used)
Display size = 128RGB x 160
Example for SMX = SMY = 0
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.213Apr, 2010
HX8353-D
132RGB x 162 dots, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
Example for SMX = SMY = 1
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.214Apr, 2010
HX8353-D
132RGB x 162 dots, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
Case 2 of resolution (120RGB x 160) (RSO[2:0] = 010) RAM size = 120 x 160 x 18-bits (Used)
Display size = 120RGB x 160
Example for SMX = SMY = 0
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.215Apr, 2010
HX8353-D
132RGB x 162 dots, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
Example for SMX = SMY = 1
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.216Apr, 2010
HX8353-D
132RGB x 162 dots, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
Case 3 of resolution (128RGB x 128) (RSO[2:0] = 001) RAM size = 128 x 128 x 18-bits (Used)
Display size = 128RGB x 128
Example for SMX = SMY = 0
G128
G129
Driver IC (Bump down)
G3
S7
S390
G2
GRAM size (128 x 128 x 18bit)
00H
01H
02H
-------------------------------- 7DH
7EH
7FH
00H
01H
02H
-------------------------------- 7DH
7EH
7FH
G1
G2
1st Pixel
(0,0)
G3
(127,127)
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G4
00H
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G126
G127
(127,127)
G128
G129
Display direction control (S/W)
X - Mirror control MX
Y - Mirror control by MY
XY - Exchange control by MV
Direction default setting (H/W)
SMX = 0
SMY = 0
SRGB = 0
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.217Apr, 2010
HX8353-D
132RGB x 162 dots, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
Example for SMX = SMY = 1
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.218Apr, 2010
HX8353-D
132RGB x 162 dots, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
Case 4 of resolution (132RGB x 162) (RSO[2:0] = 000) RAM size = 132 x 162 x 18-bits (Used)
Display size = 132RGB x 162 ~ Type 1
(P.S : STE_SEL = 0 Type1 ; STE_SEL = 1 Type 2)
Example for SMX = SMY = 0
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.219Apr, 2010
HX8353-D
132RGB x 162 dots, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
Example for SMX = SMY = 1
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.220Apr, 2010
HX8353-D
132RGB x 162 dots, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
Display size = 132RGB x 162 ~ Type 2
(P.S : STE_SEL = 0 Type1 ; STE_SEL = 1 Type 2)
Example for SMX = SMY = 0
G160
G161
Driver IC (Bump down)
G3
S7
S390
G2
GRAM size (132 x 162 x 18bit)
00H
01H
02H
-------------------------------- 7DH
7EH
7FH
(0,0)
00H
01H
02H
-------------------------------- 7DH
7EH
7FH
G1
G2
G3
(2,1)
(129,160)
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1st Pixel
G4
00H
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G158
G159
(127,159)
(131,161)
Display direction control (S/W)
X - Mirror control MX
Y - Mirror control by MY
XY - Exchange control by MV
G160
G161
Direction default setting (H/W)
SMX = 0
SMY = 0
SRGB = 0
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.221Apr, 2010
HX8353-D
132RGB x 162 dots, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
Example for SMX = SMY = 0
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.222Apr, 2010
HX8353-D
132RGB x 162 dots, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
Case 5 of resolution (96RGB x 68) (RSO[2:0] = 100) RAM size = 96 x 68 x 18-bits (Used)
Display size = 96RGB x 68
Example for SMX = SMY = 0
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.223Apr, 2010
HX8353-D
132RGB x 162 dots, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
Example for SMX = SMY = 1
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.224Apr, 2010
HX8353-D
132RGB x 162 dots, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
Case 6 of resolution (96RGB x 64) (RSO[2:0] = 101) RAM size = 96 x 64 x 18-bits (Used)
Display size = 96RGB x 64
Example for SMX = SMY = 0
G64
G63
Driver IC (Bump down)
G1
S55
S342
G2
GRAM size (96 x 64 x 18bit)
00H
01H
02H
-------------------------------- 5DH
5EH
5FH
00H
01H
02H
-------------------------------- 7DH
7EH
7FH
G1
1st Pixel
(0,0)
G2
G3
(95,63)
|
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G4
00H
|
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G61
G62
G63
(95,63)
G64
Display direction control (S/W)
X - Mirror control MX
Y - Mirror control by MY
XY - Exchange control by MV
Direction default setting (H/W)
SMX = 0
SMY = 0
SRGB = 0
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.225Apr, 2010
HX8353-D
132RGB x 162 dots, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
Example for SMX = SMY = 1
G64
G63
Driver IC (Bump down)
G1
S55
S342
G2
GRAM size (96 x 64 x 18bit)
00H
01H
02H
-------------------------------- 5DH
5EH
5FH
00H
01H
02H
-------------------------------- 7DH
7EH
7FH
G1
(95,63)
(0,0)
G2
G3
(95,63)
|
|
|
|
|
|
|
|
|
|
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|
G4
00H
|
|
|
|
|
|
|
|
|
|
|
|
G61
G62
G63
1st Pixel
G64
Display direction control (S/W)
X - Mirror control MX
Y - Mirror control by MY
XY - Exchange control by MV
Direction default setting (H/W)
SMX = 1
SMY = 1
SRGB = 0
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.226Apr, 2010
HX8353-D
132RGB x 162 dots, 262K Color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
13. Ordering Information
Part No.
HX8353-D000 PDxxx
Package
PD : mean COG
xxx : mean chip thickness (µm), (default: 250 µm)
14. Revision History
Version
Date
2009/02/25
2009/03/27
2009/04/20
2009/04/23
2009/05/25
2009/05/25
2009/05/25
2009/06/17
2009/06/29
01
2009/08/06
2009/08/12
2009/09/02
2009/11/02
2009/12/21
2009/12/23
2010/01/22
2010/02/02
2010/02/09
2010/02/10
2010/04/12
2010/04/23
Description of Changes
New setup
Remove VPNL_EN in P.166
Add In-House Register Command Setting
Modify RB5H => VR_TRIM(From [5:0] to [3:0])
Remove B1H Blank FS1[3:0] & FS0[3:0]
Modify B1H => PON is control VCL and VGL on/off
Modify BFH => PTBA[15] is control VGH on/off
Add application of connection with Different resolution
Modify VCI voltage form 2.3V to 2.5V
Modify In-house register function.
Modify OTP table.
Modify Chip Size and pad coordinates.
Modify CAP application (1uF at DDVDH, VGL, C11)
New Setup HX8353D ES1.0
Modify C1:16V 6.3V ; C2:16V 6.3V
Modify Au Bump Height 15um 12um
Modify ES1.3 IC default value
Modify OTP_index table and the N_RTN default value.
Modify chip thickness from 300um to 250um
Modify Pin assignment
update VGH & VGL voltage spec (P7,P11,P166)
Modify Fosc setting table
Define OTP current limit ≧20mA
Add VMF setting Note2(When Setting the VMF, be careful the
VCOMH & VCOML voltage’s range.)
Add RB0H、RC0H、RCBH、RE3H Register Command Set
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.227Apr, 2010