M0216SD‐162SDAR2-1 Vacuum Fluorescent Display Module RoHS Compliant Newhaven Display International, Inc. 2511 Technology Drive, Suite 101 Elgin IL, 60124 Ph: 847‐844‐8795 Fax: 847‐844‐8796 www.newhavendisplay.com [email protected] [email protected] 1.0 SCOPE This specification applies to VFD module (Model NO: M0216SD-162SDAR2-1) . 2.0 FEATURES *Since a DC/DC converter is used, only +5Vdc power source is required to operate the module. *5x8 dot matrix display, DC-DC/AC converter, and controller/driver circuitry. *High quality display and luminance. *ASCII and Japanese characters (CG-ROM font). *The module can be configured for a Motorola M68-type parallel interface, an Intel I80-type parallel interface, or synchronous serial ainterface. STANDARD NAME DOCUMENT NO. REV. NO. PAGE M0216SD-162SDAR2-1 04 2/24 3.0 SPECIFICATIONS 3.1 GENERAL SPECIFICATIONS ITEM Number of characters (char x line) Character configuration Character height (mm) Character width (mm) Character pitch (mm) Line pitch (mm) width Dot size (mm) height width Dot pitch (mm) height Peak wavelength of illumination min. Luminance (cd/m2 / fL) typ. STANDARD NAME VALUE 16 x 2 5 x 8 dot matrix 5.34 2.10 3.30 6.16 0.34 0.58 0.44 0.68 Green (505 nm) x = 0.235, y = 0.405 350 / 102 500 / 146 DOCUMENT NO. M0216SD-162SDAR2-1 REV. NO. PAGE 04 3/24 3.2 MECHANICAL DRAWINGS STANDARD NAME S DOCUMENT NO. M0216SD-162SDAR2-1 REV. NO. 04 PAGE 4/24 3.3 SYSTEM BLOCK DIAGRAM NC_RST/_SI/SO VACUUM DOT MATRIX RS_STB VFD R/W_WR/ FLUORESCENT CONTROLLER E_RD/_SCK GRID AND DRIVER DB0-DB7 DRIVER DISPLAY (IF NEEDED) (SEE SECTION 2.0) Vcc DC-DC/AC CONVERTER GND 3.4 ENVIRONMENTAL SPECIFICATIONS Item Operating temperature Storage temperature Operating humidity Storage humidity Symbol Topr Tstg Hopr Hstg Min. -40 -50 20 20 Max. +85 +95 85 90 Unit o C o C %RH %RH Vibration -- -- 4 G Shock -- -- 40 G Comment Without condensation Without condensation Total amplitude: 1.5mm Freq: 10 - 55 Hz sine wave Sweep time: 1 min./cycle Duration: 2 hrs./axis (X,Y,Z) Duration: 11ms Waveform: half sine wave 3 times/axis (X,Y,Z,-X,-Y,-Z) 3.5 ABSOLUTE MAXIMUM SPECIFICATIONS Item Supply voltage Input signal voltage STANDARD NAME Symbol VCC VIN Min. -0.3 -0.3 Max. 6.5 VCC+0.3 DOCUMENT NO. M0216SD-162SDAR2-1 Unit V V REV. NO. PAGE 04 5/24 3.6 DC ELECTRICAL SPECIFICATIONS Item Symbol Min. Typ. Max. Unit Supply voltage VCC 4.5 5.0 5.5 V Supply current ICC - 170 220 mA High-level input voltage (see Note) VIH1 0.8*VCC VCC (E,RD/,SCK,RST/) Low-level input voltage (see Note) VIL1 0.0 0.2*VCC (E,RD/,SCK,RST/) High-level input voltage (see Note) VIH2 0.7*VCC VCC (all inputs except E,RD/,SCK,RST/) Low-level input voltage (see Note) VIL2 0.0 0.3*VCC (all inputs except E,RD/,SCK,RST/) High-level output voltage VOH VCC-0.5 (IOH = -0.1mA) Low-level output voltage VOL 0.5 (IOL = 0.1mA) Input current (see Note) II -500 1.0 Note: A 10K ohm pull-up resistor is provided on each input for TTL compatibility. V V V V V V uA 3.7 AC ELECTRICAL SPECIFICATIONS 3.7.1 RESET TIMING (See Figures 1 and 2) Item Symbol Min. Max. VCC rise time tRVCC 10 VCC off time tOFF 1 Delay time after power-up reset tIRSTD 100 Delay time after external reset tERSTD 100 RST/ pulse width low tRSTL 500 Input signal fall time tf 15 Input signal rise time tr 15 Note: All timing is specified using 20% and 80% of V CC as the reference points. STANDARD NAME DOCUMENT NO. M0216SD-162SDAR2-1 Unit ms ms us us ns ns ns REV. NO. PAGE 04 6/24 t RVCC 4.5V Vcc 0.2V t OFF t IRSTD RS, STB Figure 1. Power-up Internal Reset Timing tf tr RST/ t RSTL t ERSTD RS, STB Figure 2. External Reset Timing 3.7.2 MOTOROLA M68-TYPE PARALLEL INTERFACE TIMING (See Figures 3 and 4) Item Symbol Min. Max. RS, R/W setup time tAS 20 RS, R/W hold time tAH 10 Input signal rise time tr 15 Input signal fall time tf 15 E pulse width high PWEH 230 E pulse width low PWEL 230 Write data setup time tDS 80 Write data hold time tDH 10 E cycle time tCYCE 500 Read data delay time tDD 160 Read data hold time tDHR 5 Note: All timing is specified using 20% and 80% of V CC as the reference points. Unit ns ns ns ns ns ns ns ns ns ns ns DOCUMENT NO. REV. NO. PAGE 04 7/24 STANDARD NAME M0216SD-162SDAR2-1 RS t AS tAH R/W tr tf PW EH E PW t DS EL tDH DB0-DB7 t CYCE Figure 3. Motorola M68-Type Parallel Interface Write Cycle Timing RS t AS tAH R/W tr tf PW EH E PW t DD EL t DHR DB0-DB7 t CYCE Figure 4. Motorola M68-Type Parallel Interface Read Cycle Timing STANDARD NAME DOCUMENT NO. REV. NO. M0216SD-162SDAR2-1 04 PAGE 8/24 3.7.3 INTEL I80-TYPE PARALLEL INTERFACE TIMING (See Figures 5 and 6) Item Symbol Min. Max. RS setup time tRSS 10 RS hold time tRSH 10 Input signal fall time tf 15 Input signal rise time tr 15 WR/ pulse width low tWRL 30 WR/ pulse width high tWRH 100 Write data setup time tDSi 30 Write data hold time tDHi 10 WR/ cycle time tCYCWR 166 RD/ cycle time tCYCRD 166 RD/ pulse width low tRDL 70 RD/ pulse width high tRDH 70 Read data delay time tDDi 70 Read data hold time tDHRi 5 50 Note: All timing is specified using 20% and 80% of V CC as the reference points. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns RS t RSS tf t RSH tr t WRH WR/ t WRL t DHi t DSi DB0-DB7 t CYCWR Figure 5. Intel I80-Type Parallel Interface Write Cycle Timing STANDARD NAME DOCUMENT NO. M0216SD-162SDAR2-1 REV. NO. PAGE 04 9/24 RS t RSS tf t RSH tr t RDH RD/ t RDL t DDi t DHRi DB0-DB7 t CYCRD Figure 6. Intel I80-Type Parallel Interface Read Cycle Timing 3.7.4 SYNCHRONOUS SERIAL INTERFACE TIMING (See Figures 7, 8 and 12) Item Symbol Min. Max. STB setup time tSTBS 100 STB hold time tSTBH 500 Input signal fall time tf 15 Input signal rise time tr 15 STB pulse width high tWSTB 500 SCK pulse width high tSCKH 200 SCK pulse width low tSCKL 200 SI data setup time tDSs 100 SI data hold time tDHs 100 SCK cycle time tCYCSCK 500 SCK wait time between bytes tWAIT 1 SO data delay time tDDs 150 SO data hold time tDHRs 5 Note: All timing is specified using 20% and 80% of V CC as the reference points. STANDARD NAME DOCUMENT NO. M0216SD-162SDAR2-1 Unit ns ns ns ns ns ns ns ns ns ns us ns ns REV. NO. PAGE 04 10/24 t WSTB STB t CYCSCK t STBS t STBH t SCKH SCK tf tr t SCKL t DHs t DSs SI/SO Figure 7. Synchronous Serial Interface Write Cycle Timing t WSTB STB t CYCSCK t STBS t STBH t SCKH SCK tf t SCKL tr t DHRs t DDs SI/SO Figure 8. Synchronous Serial Interface Read Cycle Timing STANDARD NAME DOCUMENT NO. REV. NO. PAGE M0216SD-162SDAR2-1 04 11/24 4.0 MODES OF OPERATION The following modes of operation are selectable via jumpers (see section 8.0 Jumper Settings). 4.1 PARALLEL INTERFACE MODES In the parallel interface mode, 8-bit instructions and data are sent between the host and the modules using either 4-bit nibbles or 8-bit bytes. Nibbles are transmitted high nibble first on DB4-DB7 (DB0DB3 are ignored) whereas bytes are transmitted on DB0-DB7. The Register Select (RS) control signal is used to identify DB0-DB7 as an instruction (low) or data (high). 4.1.1 MOTOROLA M68-TYPE MODE This mode uses the Read/Write (R/W) and Enable (E) control signals to transfer information. Instructions/data are written to the modules on the falling edge of E when R/W is low and are read from the modules after the rising edge of E when R/W is high. RS R/W E DB7 IB7 IB3 IB7 IB3 BF= ' 0 ' IB3 DB7 DB3 DB6 IB6 IB2 IB6 IB2 IB6 IB2 DB6 DB2 DB5 IB5 IB1 IB5 IB1 IB5 IB1 DB5 DB1 DB4 IB4 IB0 IB4 IB0 IB4 IB0 DB4 DB0 Write instruction Write instruction Read instruction Write data Figure 9. Typical 4-Bit Parallel Interface Sequence Using M68-Type Mode STANDARD NAME DOCUMENT NO. REV. NO. PAGE M0216SD-162SDAR2-1 04 12/24 4.1.2 INTEL I80-TYPE MODE This mode uses the Read (RD/) and Write (WR/) control signals to transfer information. Instructions/data are written to the modules on the rising edge of WR/ and are read from the modules after the falling edge of RD/. RS WR/ RD/ DB7 IB7 IB7 BF= ' 0 ' DB7 DB6 IB6 IB6 IB6 DB6 DB0 IB0 IB0 IB0 DB0 Write instruction Write instruction Read instruction Write data Figure 10. Typical 8-Bit Parallel Interface Sequence Using I80-Type Mode 4.2 SYNCHRONOUS SERIAL INTERFACE MODE In the synchronous serial interface mode, instructions and data are sent between the host and the modules using 8-bit bytes. Two bytes are required per read/write cycle and are transmitted MSB first. The start byte contains 5 high bits, the Read/Write (R/W) control bit, the Register Select (RS) control bit, and a low bit. The following byte contains the instruction/data bits. The R/W bit determines whether the cycle is a read (high) or a write (low) cycle. The RS bit is used to identify the second byte as an instruction (low) or data (high). This mode uses the Strobe (STB) control signal, Serial Clock (SCK) input, and Serial I/O (SI/SO) line to transfer information. In a write cycle, bits are clocked into the modules on the rising edge of SCK. In a read cycle, bits in the start byte are clocked into the modules on the rising edge of SCK. After the minimum wait time, each bit in the instruction/data byte can be read from the modules after each falling edge of SCK. Each read/write cycle begins on the falling edge of STB and ends on the rising edge. To be a valid read/write cycle, the STB must go high at the end of the cycle. STANDARD NAME DOCUMENT NO. REV. NO. PAGE M0216SD-162SDAR2-1 04 13/24 STB 1 2 3 4 5 6 7 8 9 10 '1' '1' '1' '1' '1' R/W RS '0' B7 11 12 13 14 15 16 SCK SI/SO B6 B5 Start byte B4 B3 B2 B1 B0 Instruction / Data Figure 11. Typical Synchronous Serial Interface Write Cycle STB 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 SCK tWAIT SI/SO '1' '1' '1' '1' '1' Start byte R/W RS '0' B7 B6 B5 B4 B3 B2 B1 B0 Instruction / Data Figure 12. Typical Synchronous Serial Interface Read Cycle 4.3 RESET MODES The modules are reset automatically at power-up by an internal R-C circuit. However, an external reset mode can also be selected when using one of the parallel interface modes (this option is not available when using the synchronous serial interface mode). This mode allows the modules to be reset by setting the Reset (RST/) input low. STANDARD NAME DOCUMENT NO. REV. NO. PAGE M0216SD-162SDAR2-1 04 14/24 5.0 CHARACTER FONT TABLES UPPER NIBBLE 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 LOWER NIBBLE STANDARD NAME 0000 CG RAM (1) 0001 CG RAM (2) 0010 CG RAM (3) 0011 CG RAM (4) 0100 CG RAM (5) 0101 CG RAM (6) 0110 CG RAM (7) 0111 CG RAM (8) 1000 CG RAM (1) 1001 CG RAM (2) 1010 CG RAM (3) 1011 CG RAM (4) 1100 CG RAM (5) 1101 CG RAM (6) 1110 CG RAM (7) 1111 CG RAM (8) DOCUMENT NO. M0216SD-162SDAR2-1 REV. NO. 04 PAGE 15/24 6.0 FUNCTIONAL DESCRIPTION 6.1 ADDRESS COUNTER (AC) 6.1.1 SINGLE LINE DISPLAYS The AC stores the address of the data being written to and read from DDRAM or CGRAM. The AC increments by 1 (overflows from 4FH to 00H) or decrements by 1 (underflows from 00H to 4FH) after each DDRAM access. The AC increments by 1 (overflows from 3FH to 00H) or decrements by 1 (underflows from 00H to 3FH) after each CGRAM access. When addressing DDRAM, the value in the AC also represents the cursor position. 6.1.2 MULTIPLE LINE DISPLAYS The AC stores the address of the data being written to and read from DDRAM or CGRAM. The AC increments by 1 (overflows from 27H to 40H and from 67H to 00H) or decrements by 1 (underflows from 40H to 27H and from 00H to 67H) after each DDRAM access. The AC increments by 1 (overflows from 3FH to 00H) or decrements by 1 (underflows from 00H to 3FH) after each CGRAM access. When addressing DDRAM, the value in the AC also represents the cursor position. 6.2 DISPLAY DATA RAM (DDRAM) 6.2.1 SINGLE LINE DISPLAYS The DDRAM stores the character code of each character being displayed on the VFD. Valid DDRAM addresses are 00H to 4FH. DDRAM not being used for display characters can be used as general purpose RAM. The tables below show the relationship between the DDRAM address and the character position on the VFD before and after a display shift (with the number of display lines set to 1). 6.2.2 MULTIPLE LINE DISPLAYS The DDRAM stores the character code of each character being displayed on the VFD. Valid DDRAM addresses are 00H to 27H and 40H to 67H. DDRAM not being used for display characters can be used as general purpose RAM. The tables below show the relationship between the DDRAM address and the character position on the VFD before and after a display shift (with the number of display lines set to 2). STANDARD NAME DOCUMENT NO. M0216SD-162SDAR2-1 REV. NO. PAGE 04 16/24 6.3 DISPLAY SHIFT DETAIL Relationship before a display shift (non-shifted): 1 1 2 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F Relationship after a display shift to the left: 1 1 2 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 Relationship after a display shift to the right: 1 1 2 STANDARD NAME 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 27 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 67 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E DOCUMENT NO. M0216SD-162SDAR2-1 REV. NO. PAGE 04 17/24 6.4 CHARACTER GENERATOR RAM (CGRAM) The CGRAM stores the pixel information (1 = pixel on, 0 = pixel off) for the eight userdefinable 5x8 characters. Valid CGRAM addresses are 00H to 3FH. CGRAM not being used to define characters can be used as general purpose RAM (lower 5 bits only). Character codes 00H to 07H (or 08H to 0FH) are assigned to the user-definable characters (see section 5.0 Character Font Tables). The table below shows the relationship between the character codes, CGRAM addresses, and CGRAM data for each user-definable character. Character code D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 X 0 0 0 0 0 0 0 0 0 0 0 X X 0 1 0 1 1 1 CGRAM address A5 A4 A3 A2 A1 A0 0 0 0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 0 0 1 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 CGRAM data D7 D6 D5 D4 D3 D2 X X X 1 1 1 0 0 0 0 0 0 0 0 1 0 1 0 1 0 0 1 1 1 0 0 0 X X X 1 1 1 1 0 0 1 0 0 1 1 1 1 0 0 1 0 0 1 1 1 0 0 0 X X X 0 1 1 1 1 1 1 0 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 D1 1 0 1 0 0 0 1 0 1 0 0 1 0 0 1 0 D0 1 1 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 0 0 0 0 0 1 0 1 0 0 0 0 1 0 CGRAM (1) CGRAM (2) CGRAM (8) x = don't care 6.5 INSTRUCTIONS Instruction Clear display Cursor home Entry mode set Display on/off control Cursor/display shift Function set CGRAM address set DDRAM address set Address counter read DDRAM or CGRAM write DDRAM or CGRAM read x = don’t care STANDARD NAME: RS 0 0 0 0 0 0 0 0 0 1 1 R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 x 0 0 0 0 0 0 1 I/D S 0 0 0 0 0 1 D C B 0 0 0 0 1 S/C R/L x x 0 0 0 1 DL N x BR1 BR0 0 0 1 CGRAM address 0 1 DDRAM address 1 BF=0 AC contents 0 Write data 1 Read data DOCUMENT NO. M0216SD-162SDAR2-1 REV. NO. PAGE 04 18/24 6.5.1 CLEAR DISPLAY RS 0 R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 0 0 1 This instruction clears the display (without affecting the contents of CGRAM) by performing the following: 1) 2) 3) 4) Fills all DDRAM locations with character code 20H (character code for a space). Sets the AC to DDRAM address 00H (i.e. sets cursor position to 00H). Returns the display to the non-shifted position. Sets the I/D bit to 1. 6.5.2 CURSOR HOME RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 0 0 1 x x = don’t care This instruction returns the cursor to the home position (without affecting the contents of DDRAM or CGRAM) by performing the following: 1) Sets the AC to DDRAM address 00H (i.e. sets cursor position to 00H). 2) Returns the display to the non-shifted position. 6.5.3 ENTRY MODE SET RS 0 R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 1 I/D S This instruction selects whether the AC (cursor position) increments or decrements after each DDRAM or CGRAM access and determines the direction the information on the display shifts after each DDRAM write. The instruction also enables or disables display shifts after each DDRAM write (information on the display does not shift after a DDRAM read or CGRAM access). DDRAM, CGRAM, and AC contents are not affected by this instruction. I/D = 0: The AC decrements after each DDRAM or CGRAM access. If S = 1, the information on the display shifts to the right by one character position after each DDRAM write. I/D = 1: The AC increments after each DDRAM or CGRAM access. If S = 1, the information on the display shifts to the left by one character position after each DDRAM write. S = 0: S = 1: STANDARD NAME The display shift function is disabled. The display shift function is enabled. DOCUMENT NO. M0216SD-162SDAR2-1 REV. NO. PAGE 04 19/24 6.5.4 DISPLAY ON/OFF CONTROL RS 0 R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 1 D C B This instruction selects whether the display and cursor are on or off and selects whether or not the character at the current cursor position blinks. DDRAM, CGRAM, and AC contents are not affected by this instruction. D = 0: D = 1: The display is off (display blank). The display is on (contents of DDRAM displayed). C = 0: C = 1: The cursor is off. The cursor is on (8 th row of pixels). B = 0: B = 1: The blinking character function is disabled. The blinking character function is enabled (a character with all pixels on will alternate with the character displayed at the current cursor position at about a 1Hz rate with a 50% duty cycle). 6.5.5 CURSOR/DISPLAY SHIFT RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 1 S/C R/L x x x = don’t care This instruction increments or decrements the AC (cursor position) and shifts the information on the display one character position to the left or right without accessing DDRAM or CGRAM. DDRAM and CGRAM contents are not affected by this instruction. If the AC was addressing CGRAM prior to this instruction, the AC will be addressing DDRAM after this instruction. However, if the AC was addressing DDRAM prior to this instruction, the AC will still be addressing DDRAM after this instruction. S/C 0 0 1 1 STANDARD NAME R/L 0 1 0 1 AC contents (cursor position) Decrements by one Increments by one Decrements by one Increments by one Information on the display No change No change Shifts one character position to the left Shifts one character position to the right DOCUMENT NO. M0216SD-162SDAR2-1 REV. NO. PAGE 04 20/24 6.5.6 FUNCTION SET RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 1 DL N x BR1 BR0 x = don’t care This instruction sets the width of the data bus for the parallel interface modes, the number of display lines, and the luminance level (brightness) of the VFD. It must be the first command sent after any reset. DDRAM, CGRAM, and AC contents are not affected by this instruction. DL = 0: Sets the data bus width for the parallel interface modes to 4-bit (DB7-DB4). DL = 1: Sets the data bus width for the parallel interface modes to 8-bit (DB7-DB0). N = 0: N = 1: Sets the number of display lines to 1 (this setting is not recommended for multiple line displays). Sets the number of display lines to 2 (this setting is not recommended for single line displays). BR1,BR0 = 0,0: 0,1: 1,0: 1,1: Sets the luminance level to 100%. Sets the luminance level to 75% . Sets the luminance level to 50%. Sets the luminance level to 25%. 6.5.7 CGRAM ADDRESS SET RS 0 R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 1 CGRAM address This instruction places the 6-bit CGRAM address specified by DB5-DB0 into the AC (cursor position). Subsequent data writes (reads) will be to (from) CGRAM. DDRAM and CGRAM contents are not affected by this instruction. 6.5.8 DDRAM ADDRESS SET RS 0 R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 1 DDRAM address This instruction places the 7-bit DDRAM address specified by DB6-DB0 into the AC (cursor position). Subsequent data writes (reads) will be to (from) DDRAM. DDRAM and CGRAM contents are not affected by this instruction. STANDARD NAME DOCUMENT NO. M0216SD-162SDAR2-1 REV. NO. PAGE 04 21/24 6.5.9 ADDRESS COUNTER READ RS 0 R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 1 BF=0 AC contents This instruction reads the current 7-bit address from the AC on DB6-DB0 and the busy flag (BF) bit (always 0) on DB7. DDRAM, CGRAM, and AC contents are not affected by this instruction. Because the BF is always 0, the host never has to read the BF bit to determine if the modules are busy before sending data or instructions. Therefore, data and instructions can be sent to the modules continuously according to the E, WR/, and SCK cycle times specified in section 3.7 AC Timing Specifications. Due to this feature, the execution times for each instruction are not specified. 6.5.10 DDRAM OR CGRAM WRITE RS 1 R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 Write data This instruction writes the 8-bit data byte on DB7-DB0 into the DDRAM or CGRAM location addressed by the AC. The most recent DDRAM or CGRAM Address Set instruction determines whether the write is to DDRAM or CGRAM. This instruction also increments or decrements the AC and shifts the display according to the I/D and S bits set by the Entry Mode Set instruction. 6.5.11 DDRAM OR CGRAM READ RS 1 R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 1 Read data This instruction reads the 8-bit data byte from the DDRAM or CGRAM location addressed by the AC on DB7-DB0. The most recent DDRAM or CGRAM Address Set instruction determines whether the read is from DDRAM or CGRAM. This instruction also increments or decrements the AC and shifts the display according to the I/D and S bits set by the Entry Mode Set instruction. Before sending this instruction, a DDRAM or CGRAM Address Set instruction should be executed to set the AC to the desired DDRAM or CGRAM address to be read. STANDARD NAME DOCUMENT NO. M0216SD-162SDAR2-1 REV. NO. PAGE 04 22/24 6.6 RESET CONDITIONS After either a power-up reset or an external reset, the modules initialize to the following conditions: 1) All DDRAM locations are set to 20H (character code for a space). 2) The AC is set to DDRAM address 00H (i.e. sets cursor position to 00H). 3) The relationship between DDRAM addresses and character positions on t he VFD is set to the nonshifted position. 4) Entry Mode Set instruction bits: I/D = 1: The AC increments after each DDRAM or CGRAM access. S = 0: The display shift function is disabled. 5) Display On/Off Control instruction bits: D = 0: The display is off (display blank). C = 0: The cursor is off. B = 0: The blinking character function is disabled. 6) Function Set instruction bits: DL = 1: Sets the data bus width for the parallel interface modes to 8-bit (DB7-DB0). N = 1(0): Number of display lines set to 2 for multiple line displays (number of display lines set to 1 for single line displays). BR1,BR0 = 0,0: Sets the luminance level to 100%. Note that the function set command must be the first instruction sent to the module after any reset. 6.6.1 INITIALIZATION The modules can be initialized by using instructions if the modules are not reset according to the reset timing detailed in Section 3.7.1 (Reset Timing). After any reset, the function set command must be the first instruction sent to the module. STANDARD NAME DOCUMENT NO. M0216SD-162SDAR2-1 REV. NO. PAGE 04 23/24 7.0 CONNECTOR INTERFACE Pin NO. Serial Paralle (Intel) Parallel (Motorola) Pin NO. Serial Paralle (Intel) Parallel (Motorola) 1 GND GND GND 2 VCC VCC VCC 3 SI/SO NC or RST/ NC or RST/ 4 STB RS RS 5 NC WR/ R/W 6 SCK RD/ E 7 NC DB0 DB0 8 NC DB1 DB1 9 NC DB2 DB2 10 NC DB3 DB3 11 NC DB4 DB4 12 NC DB5 DB5 13 NC DB6 DB6 14 NC DB7 DB7 8.0 Soldering Land Function Some soldering lands are prepared on the tear side of PCB, to set operating mond of the Display module. A soldering iron is required to short soldering lands. 1. parallel data transfer mode is selected J6 J7 J2 J3 FUNCTION Open Short * Open i80 type Short Open * Open M68 type Open Open Pin #3: No connection Short Open Pin #3: /RESET MPU type Selection External Reset Section 2. serial data or parallel data transfer mode set J5 J3 Open Open Short Short STANDARD NAME J2 FUNCTION Parallel data Transfer mode Open Serial data Transfer mode DOCUMENT NO. REV. NO. PAGE M0216SD-162SDAR2-1 04 24/24