NTE4583B Integrated Circuit CMOS − Dual Schmitt Trigger Description: The NTE4583B is a dual Schmitt trigger constructed with complementary P−channel and N−channel MOS devices on a monolithic silicon substrate. Each Schmitt trigger is functionally independent except for a common 3−state input and an internally−connected Exclusive OR output for use in line receiver applications. Trigger levels are adjustable through the positive, negative, and common terminals with the use of external resistors. Applications include the speed−up of a slow waveform edge in interface receivers, level detectors, etc. Features: D Diode Protection on All Inputs D Supply Voltage Range: 3V to 18V D Single Supply Operation D Capable of Driving Two Low−Power TTL Loads or One Low−Power Schottky TTL Load Over the Rated Temperature Range D Resistor Adjustable Trigger Levels Absolute Maximum Ratings: (Voltages Referenced to VSS, Note 1) DC Supply Voltage, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 to +18.0V Input or Output Voltage (DC or Transient), Vin, Vout . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 to VDD+0.5V Input or Output Current, per Pin (DC or Transient), Iin, Iout . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±10mA Power Dissipation, per Package, PD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500mW Derate Above +65°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12mW/°C Operating Temperature Range, Topr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40° to +85°C Storage Temperature Range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65° to +150°C Lead Temperature (During Soldering, 8sec), TL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +260°C Note 1. Maximum Ratings are those values beyond which damage to the device may occur. Note 2. This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high−impedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS ≤ (Vin or Vout) ≤ VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open. Electrical Characteristics: (Voltages Referenced to VSS, Note 3) −40°C Parameter Symbol VDD +25°C +85°C Min Max Min Typ Max Min Max Unit 5 − 0.05 − 0 0.05 − 0.05 V 10 − 0.05 − 0 0.05 − 0.05 V 15 − 0.05 − 0 0.05 − 0.05 V 5 4.95 − 4.95 5 − 4.95 − V 10 9.95 − 9.95 10 − 9.95 − V 15 14.95 − 14.95 15 − 14.95 − V 5 − 1.5 − 2.25 1.5 − 1.5 V VO = 9.0V or 1.0V 10 − 3.0 − 4.50 3.0 − 3.0 V VO = 13.5V or 1.5V 15 − 4.0 − 6.75 4.0 − 4.0 V 5 3.5 − 3.5 2.75 − 3.5 − V VO = 1.0V or 9.0V 10 7.0 − 7.0 5.50 − 7.0 − V VO = 1.5V or 13.5V 15 11.0 − 11.0 8.25 − 11.0 − V 5 −1.0 − −0.8 −1.7 − −0.6 − mA VOH = 4.6V 5 −0.2 − −0.16 −0.36 − −0.12 − mA VOH = 9.5V 10 −0.5 − −0.4 −0.9 − −0.3 − mA VOH = 13.5V 15 −1.4 − −1.2 −3.5 − −1.0 − mA 5 0.52 − 0.44 0.88 − 0.36 − mA VOL = 0.5V 10 1.3 − 1.1 2.25 − 0.9 − mA VOL = 1.5V 15 3.6 − 3.0 8.8 − 2.4 − mA Output “0” Level Voltage Vin = VDD or 0 VOL Output “1” Level Voltage Vin = 0 or VDD VOH Input “0” Level Voltage, A and B VO = 4.5V or 0.5V VIL Input “1” Level Voltage, A and B VO = 0.5V or 4.5V VIH Output Drive Source Current VOH = 2.5V IOH Output Drive Sink Current VOL = 0.4V IOL Input Current Iin 15 − ±0.3 − ±0.00001 ±0.3 − ±1.0 μA Input Capacitance, Vin = 0 Cin − − − − 5.0 7.5 − − pF Quiescent Current, Per Package IDD 5 − 1.0 − 0.0005 1.0 − 7.5 μA 10 − 2.0 − 0.0010 2.0 − 15.0 μA 15 − 4.0 − 0.0015 4.0 − 30.0 μA Total Supply Current Dynamic plus Quiescent, Per Package CL = 50pF on all outputs, all buffers switching (Note 4) IT Three−State Leakage Current ITL 5 IT = (1.33μA/kHz) f + IDD μA 10 IT = (2.65μA/kHz) f + IDD μA 15 IT = (3.98μA/kHz) f + IDD μA 15 − ±1.0 − ±0.0001 ±1.0 − ±7.5 μA Note 3. Data labeled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance. Note 4. The formulas given are for the typical characteristics only at +25°C. To calculate total supply current at loads other than 50pF: IT(CL) = IT(50pF) + (CL −50) Vfk where: IT is in μA, CL in pF, V = (VDD − VSS) in volts, f in kHz is input frequency, and k = 0.005. Switching Characteristics: (CL = 50pF, TA = +25°C, Note 3, Note 5) Parameter Symbol VDD Min Typ Max Unit tTLH 5 − 180 360 ns tTLH = (1.5ns/pF) CL +15ns 10 − 90 180 ns tTLH = (1.1ns/pF) CL + 10ns 15 − 65 130 ns 5 − 100 200 ns tTHL = (0.75ns/Pf) CL + 12.5ns 10 − 50 100 ns tTHL = (0.55ns/pF) CL + 9.5ns 15 − 40 80 ns 5 − 650 1300 ns tPLH, tPHL = (0.66ns/pF) CL + 197ns 10 − 230 460 ns tPLH, tPHL = (0.5ns/pF) CL + 125ns 15 − 150 300 ns 5 − 1100 2200 ns tPLH, tPHL = (0.66ns/pF) CL + 347ns 10 − 380 760 ns tPLH, tPHL = (0.5ns/pF) CL + 235ns 15 − 260 520 ns 5 − 750 1500 ns tPLH, tPHL = (0.66ns/pF) CL + 257ns 10 − 280 560 ns tPLH, tPHL = (0.5ns/pF) CL + 145ns 15 − 170 340 ns 5 − 225 450 ns ton, toff = (0.66ns/pF) CL + 57ns 10 − 90 180 ns ton, toff = (0.5ns/pF) CL + 30ns 15 − 55 110 ns 5 − 3.30 − V 10 − 5.70 − V 15 − 8.20 − V 5 − 1.70 − V 10 − 4.30 − V 15 − 6.80 − V 5 0.85 1.70 3.40 V 10 0.70 1.40 2.80 V 15 0.70 1.40 2.80 V 5 − 1.10 − V 10 − 0.15 − V 15 − 0.20 − V Output Rise Time tTLH = (3.0ns/pF) CL + 30ns Output Fall Time tTHL = (1.5ns/pF) CL + 25ns Propagation Delay Time, Ain, Bin to Aout, Bout tPLH, tPHL = (1.7ns/pF) CL + 565ns Propagation Delay Time, Ain, Bin to Aout, Bout tPLH, tPHL = (1.7ns/pF) CL + 1015ns Propagation Delay Time, Ain, Bin to Exclusive OR tPLH, tPHL = (1.7ns/pF) CL + 665ns 3−State Enable, Disable Delay Time ton, toff = (1.7ns/pF) CL + 140ns Positive Threshold Voltage R1, R2 = 5.0kΩ Negative Threshold Voltage R1, R2 = 5.0kΩ Hysteresis Voltage R1, R2 = 5.0kΩ Threshold Voltage Variation, A to B R1, R2 = 5.0kΩ tTHL tPLH, tPHL tPLH, tPHL tPLH, tPHL ton, toff VT+ VT− VH ΔVT Note 3. Data labeled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance. Note 5. The formulas given are for the typical characteristics only at +25°C. Truth Table Inputs Outputs A B Dis Aout Aout Bout Bout Exclusive OR 0 0 0 0 Z 0 Z 0 0 0 1 0 1 0 1 0 0 1 0 0 Z 1 Z 1 0 1 1 0 1 1 0 1 1 0 0 1 Z 0 Z 1 1 0 1 1 0 0 1 1 1 1 0 1 Z 1 Z 0 1 1 1 1 0 1 0 0 Z = High impedance at output Logic Diagram Positive A 6 5 Negative A 7 Common A Ain 9 4 Aout 11 Aout 3−State Output Disable 13 14 Exclusive OR Bin 15 10 Bout 12 Bout 1 Common B Positive B2 2 3 Negative B VDD = Pin16 VSS = Pin8 Pin Connection Diagram Common B 1 16 VCC Positive B2 2 15 B In Negative B 3 14 Exclusive OR A Out 4 13 Disable Negative A 5 12 B Out Positive A 6 11 A Out Common A 7 10 B Out GND 8 9 A In 16 9 1 8 .260 (6.6) Max .870 (22.0) Max .200 (5.08) Max .100 (2.54) .700 (17.78) .099 (2.5) Min