NTE4510B & NTE4510BT Integrated Circuit CMOS, Presettable Up/Down BCD Counter Description: The NTE4510B (16−Lead DIP) and NTE4510BT (SOIC−16) are up/down counters constructed with MOS P−channel and N−channel enhancement mode devices in a single monolithic structure. The counter consists of type D flip−flop stages with a gating structure to provide type T flip−flop capability. The counter can be cleared by applying a high level on the Reset line. These complementary MOS counters find primary use in up/down and difference counting and frequency synthesizer applications where low power and/or high noise immunity is desired. They are also useful in A/D and D/A conversion for magnitude and sign generation. Features: D Noise Immunity = 45% of VDD (Typ) D Diode Protection on All Inputs D Supply Voltage Range = 3Vdc to 10Vdc D Low Input Capacitance = 5pF (Typ) D Internally Synchronous for High Speed D Logic Edge−Clocked Design − Count Occurs on Positive Going Edge of Clock D 5Mhz Counting Rate D Asynchronous Preset Enable Operation D Capable of Driving Two Low−Power TTL Loads, One Low−Power Schottky TTL Load or Two HTL Loads Over the Rated Temperature Range Absolute Maximum Ratings: (Voltages Referenced to VSS, Note 1) DC Supply Voltage, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 to +18.0V Input Voltage (All Inputs), Vin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 to VDD + 0.5V DC Current Drain (Per Pin), I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10mA Operating Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −55 to +125°C Storage Temperature Range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65 to +150°C Note 1. These devices contain circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high impedance circuit. For proper operation is is recommended that Vin and Vout be constrained to the range VSS ≤ (Vin or Vout) ≤ VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Electrical Characteristics: (Voltages referenced to VSS, Note 2) −555C +255C +1255C VDD Vdc 5.0 Min Max Min Typ Max Min Max − 0.05 − 0 0.05 − 0.05 Unit Vdc 10 − 0.05 − 0 0.05 − 0.05 Vdc 15 − 0.05 − 0 0.05 − 0.05 Vdc 5.0 4.95 − 4.95 5.0 − 4.95 − Vdc 10 9.95 − 9.95 10 − 9.95 − Vdc 15 14.95 − 14.95 15 − 14.95 − Vdc 5.0 − 1.5 − 2.25 1.5 − 1.5 Vdc (VO = 9.0 or 1.0Vdc) 10 − 3.0 − 4.50 3.0 − 3.0 Vdc (VO = 13.5 or 1.5Vdc) 15 − 4.0 − 6.75 4.0 − 4.0 Vdc 5.0 3.5 − 3.5 2.75 − 3.5 − Vdc (VO = 1.0 or 9.0Vdc) 10 7.0 − 7.0 5.50 − 7.0 − Vdc (VO = 1.5 or 13.5Vdc) 15 11.0 − 11.0 8.25 − 11.0 − Vdc 5.0 −1.2 − −1.0 −1.7 − −0.7 − mAdc (VOH = 4.6Vdc) 5.0 −0.25 − −0.2 −0.36 − −0.14 − mAdc (VOH = 9.5Vdc) 10 −0.62 − −0.5 −0.9 − −0.35 − mAdc (VOH = 13.5Vdc) 15 −1.8 − −1.5 −3.5 − −1.1 − mAdc 5.0 0.64 − 0.51 0.88 − 0.36 − mAdc (VOL = 0.5Vdc) 10 1.6 − 1.3 2.25 − 0.9 − mAdc (VOL = 1.5Vdc) 15 4.2 − 3.4 8.8 − 2.4 − mAdc Parameter Output Voltage Vin = VDD or 0 Symbol “0” Level VOL “1” Level VOH Vin = 0 or VDD Input Voltage (Note 4) “0” Level (VO = 4.5 or 0.5Vdc) (VO = 0.5 or 4.5Vdc) Output Drive Current (VOH = 2.5Vdc) “1” Level Source (VOL = 0.4Vdc) Sink VIL VIH IOH IOL Input Current Iin 15 − ±0.1 − ±0.00001 ±0.1 − ±0.1 μAdc Input Capacitance (VIN = 0) Cin − − − − 5.0 7.5 − − pF Quiescent Current (Per Package) IDD 5.0 − 5.0 − 0.005 5.0 − 150 μAdc 10 − 10 − 0.010 10 − 300 μAdc 15 − 15 − 0.015 15 − 600 μAdc Total Supply Current (Dynamic plus Quiescent, Per Package, CL = 50pF on All Outputs, All Buffers Switching Note 3, Note 5) IT 5.0 IT = (0.58μA/kHz) f + IDD μAdc 10 IT = (1.2μA/kHz) f + IDD μAdc 15 IT = (1.7μA/kHz) f + IDD μAdc Note 2. Data labeled “Typ” is not to be used for design purposes but is intended as an indication of the device’s potential performance. Note 3. The formulas given are for the typical characteristics only at +25°C. Note 4. Noise immunity specified for worst−case input combination. Noise margin for both “1” and “0” = 1.0Vdc min @ VDD = 5Vdc 2.0Vdc min @ VDD = 10Vdc 2.5Vdc min @ VDD = 15Vdc Note 5. To calculate total supply current at loads other than 50pF: IT(CL) = IT(50pF) + 1 x 10−3(CL −50) VDDf where: IT is in μA (per package), CL in pF, VDD in volts and f in kHz is input frequency. Switching Characteristics: (CL = 50pF, TA = +25°C, Note 2) Parameter Output Rise Time tTLH = (3.0ns/pf) CL + 30ns tTLH = (1.5ns/pf) CL + 15ns tTLH = (1.1ns/pf) CL + 10ns Output Fall Time tTHL = (1.5ns/pf) CL + 25ns tTHL = (0.75ns/pf) CL + 12.5ns tTHL = (0.55ns/pf) CL + 9.5ns Propagation Delay Time Clock to Q tPLH, tPHL = (1.7ns/pf) CL + 230ns tPLH, tPHL = (0.66ns/pf) CL + 97ns tPLH, tPHL = (0.5ns/pf) CL + 75ns Clock to Carry Out tPLH, tPHL = (1.7ns/pf) CL + 230ns tPLH, tPHL = (0.66ns/pf) CL + 97ns tPLH, tPHL = (0.5ns/pf) CL + 75ns Carry In to Carry Out tPLH, tPHL = (1.7ns/pf) CL + 95ns tPLH, tPHL = (0.66ns/pf) CL + 47ns tPLH, tPHL = (0.5ns/pf) CL + 35ns Preset or Reset to Q tPLH, tPHL = (1.7ns/pf) CL + 230ns tPLH, tPHL = (0.66ns/pf) CL + 97ns tPLH, tPHL = (0.5ns/pf) CL + 75ns Preset or Reset to Carry Out tPLH, tPHL = (1.7ns/pf) CL + 465ns tPLH, tPHL = (0.66ns/pf) CL + 192ns tPLH, tPHL = (0.6ns/pf) CL + 125ns Clock Pulse Width Clock Pulse Frequency Symbol tTLH, tTHL tPLH. tPHL tWH fcl Preset or Reset Removal Time (Note 6) trem Clock Rise and Fall Time tTLH, tTHL VDD Vdc Min Typ Max Unit 5.0 10 15 − − − 180 90 65 360 180 130 ns ns ns 5.0 10 15 − − − 100 50 40 200 100 80 ns ns ns 5.0 10 15 − − − 315 130 100 630 260 200 ns ns ns 5.0 10 15 − − − 315 130 100 630 260 200 ns ns ns 5.0 10 15 − − − 180 80 60 360 160 120 ns ns ns 5.0 10 15 − − − 315 130 100 630 260 200 ns ns ns 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 − − − 350 170 140 − − − 650 230 180 − − − 550 225 150 200 100 75 3.0 6.0 8.0 325 115 90 − − − 1100 ns 450 ns 300 ns − ns − ns − ns 1.5 MHz 3.0 MHz 4.0 MHz − ns − ns − ns 15 μs 15 μs 15 μs Note 2. Data labeled “Typ” is not to be used for design purposes but is intended as an indication of the device’s potential performance. Note 3. The formulas given are for the typical characteristics only at +25°C. Note 6. The Preset or Reset Signal must be low prior to a positive−going transition of the clock. Switching Characteristics (Cont’d): (CL = 50pF, TA = +25°C, Note 2) Parameter Carry In Setup Time Symbol tsu Up/Down Setup Time tsu Preset Enable Pulse Width tWH VDD Vdc 5.0 10 15 5.0 10 15 5.0 10 15 Min 200 120 100 500 200 175 200 100 80 Typ 130 60 50 250 100 75 100 50 40 Max − − − − − − − − − Unit ns ns ns ns ns ns ns ns ns Note 2. Data labeled “Typ” is not to be used for design purposes but is intended as an indication of the device’s potential performance. Note 3. The formulas given are for the typical characteristics only at +25°C. Note 6. The Preset or Reset Signal must be low prior to a positive−going transition of the clock. Truth Table: Carry In 1 0 0 X X Up/Down X 1 0 X X Preset Enable 0 0 0 1 X Reset 0 0 0 0 1 X = Don’t Care Pin Connection Diagram Preset Enable 1 16 VDD Q4 2 P4 3 15 Clock 14 Q3 P1 4 13 P3 Carry In 5 12 P2 Q1 6 Carry Out 7 11 Q2 VSS 8 10 Up/Down 9 Reset Action No Count Count Up Count Down Preset Reset NTE4510B 16 9 1 8 .870 (22.0) Max .260 (6.6) Max .200 (5.08) Max .100 (2.54) .099 (2.5) Min .700 (17.78) NTE4510BT .390 (9.9) 16 9 1 8 .050 (1.27) .236 (5.99) .154 (3.91) 016 (.406) 061 (1.53) .006 (.152) NOTE: Pin1 on Beveled Edge .198 (5.03)