RENESAS R5F6461FJFP

R32C/161 Group Datasheet
R32C/161 Group
RENESAS MCU
1.
REJ03B0241-0101
Rev.1.01
Dec 07, 2009
Overview
1.1
Features
The M16C Family offers a robust platform of 32-/16-bit CISC microcomputers (MCUs) featuring high ROM
code efficiency, extensive EMI/EMS noise immunity, ultra-low power consumption, high-speed processing
in actual applications, and numerous and varied integrated peripherals. Extensive device scalability from
low- to high-end, featuring a single architecture as well as compatible pin assignments and peripheral
functions, provides support for a vast range of application fields.
The R32C/100 Series is a high-end microcontroller series in the M16C Family. With a 4-Gbyte memory
space, it achieves maximum code efficiency and high-speed processing with 32-bit CISC architecture,
multiplier, multiply-accumulate unit, and floating point unit. The selection from the broadest choice of onchip peripheral devices — UART, CRC, DMAC, A/D converter, timers, I2C, and WDT enables to minimize
external components.
The R32C/100 Series, in particular, provides the R32C/161 Group, a product specific to vehicle network.
This product, provided as 80-pin plastic molded LQFP package, configures two channels of CAN, one
channel of LIN, and standard peripherals.
1.1.1
Applications
Automotive, audio, communication equipment, industrial equipment etc.
REJ03B0241-0101 Rev.1.01 Dec 07, 2009
Page 1 of 105
R32C/161 Group
1.1.2
1. Overview
Performance Overview
Table 1.1 and Table 1.2 show the performance overview of the R32C/161 Group.
Table 1.1
R32C/161 Group Performance (1/2)
Unit
CPU
Function
Performance
Central processing R32C/100 Series CPU Core
unit
• Basic instructions: 108
• Minimum instruction execution time: 20.83 ns (f(CPU) = 48 MHz)
• Multiplier: 32-bit × 32-bit 64-bit
• Multiply-accumulate unit: 32-bit × 32-bit + 64-bit 64-bit
• IEEE-754 floating point standard: Single precision
• 32-bit barrel shifter
• Operating mode: Single-chip mode
Memory
Flash memory: 128/256 Kbytes
RAM: 12/20 Kbytes
Data flash: 4 Kbytes × 2 blocks
E2dataFlash: none (1)/4 Kbytes
Refer to Table 1.3 for details
Voltage
Detector
Low voltage
detector
Optional (2)
Low voltage detection interrupt
Clock
Clock generator
• 4 circuits (main clock, sub clock, PLL, on-chip oscillator)
• Oscillation stop detector: Main clock oscillator stop/re-oscillation
detection
• Frequency divide circuit: Divide-by-2 to divide-by-24 selectable
• Low power modes: Wait mode, stop mode
Interrupts
Interrupt vectors: 261
External interrupt inputs: NMI, INT × 6
Interrupt priority levels: 7 levels
Watchdog Timer
15 bits × 1 (selectable input frequency from prescaler output)
Automatic timer start function is available
DMA
DMAC
4 channels
• Cycle-steal transfer mode
• Request sources: 44
• 2 transfer modes: Single transfer, repeat transfer
DMAC II
• Can be activated by any peripheral interrupt source
• 3 transfer functions: Immediate data transfer, calculation transfer,
chained transfer
Programmable
I/O ports
• 2 input-only ports
• 64 CMOS inputs/outputs
• A pull-up resistor is selectable for every 4 input ports
I/O Ports
Notes:
1. Please contact a Renesas sales office to use the non-E2dataFlash version.
2. Please contact a Renesas sales office to use the optional feature.
REJ03B0241-0101 Rev.1.01 Dec 07, 2009
Page 2 of 105
R32C/161 Group
Table 1.2
1. Overview
R32C/161 Group Performance (2/2)
Unit
Timer
Function
Performance
Timer A
16-bit timer × 5
Timer mode, event counter mode, one-shot timer mode, pulse-width
modulation (PWM) mode
Two-phase pulse signal processing in event counter mode (twophase encoder input) × 3
Timer B
16-bit timer × 6
Timer mode, event counter mode, pulse frequency measurement
mode, pulse-width measurement mode
Three-phase motor Three-phase motor control timer × 1 (timers A1, A2, A4, and B2 used)
control timer
8-bit programmable dead time timer
Serial
Interface
UART0 to UART4
Asynchronous/synchronous serial interface × 5 channels
• I2C-bus (UART0 to UART2)
• Special mode 2 (UART0 to UART2)
A/D Converter
10-bit resolution × 23 channels
Sample and hold functionality integrated
Self Test/Open-Circuit Detection Assist
CRC Calculator
CRC-CCITT (X16 + X12 + X5 + 1)
X-Y Converter
16 bits × 16 bits
Intelligent I/O
Time measurement (input capture): 16 bits × 8
Digital debounce circuit contained
Waveform generation (output compare): 16 bits × 8
Phase shift waveform output mode contained
Serial Bus Interface (SBI)
1 channel
• Synchronous serial communication mode
• 4-wire serial bus mode
Programmable character length: 8 to 16 bits
LIN Module
1 channel
CAN Module
2 channels
CAN functionality compliant with ISO11898-1
32 mailboxes
Flash Memory
Programming and erasure supply voltage: VCC = 3.0 to 5.5 V
Minimum endurance: 1,000 program/erase cycles
Security protection: ROM code protect, ID code protect
Debugging: On-chip debug, on-board flash programming
E2dataFlash
Minimum endurance: 100,000 program/erase cycles
Operating Frequency/Supply
Voltage
48 MHz/VCC = 3.0 to 5.5 V
Operating Temperature
-40°C to 85°C (version J)
-40°C to 105°C (version L) (1)
-40°C to 125°C (version K)
Current Consumption
31 mA (VCC = 5.0 V, f(CPU) = 48 MHz)
8 µA (VCC = 3.3 V, f(XCIN) = 32.768 kHz, wait mode)
Package
80-pin plastic molded LQFP (PLQP0080KB-A)
Note:
1. Please contact a Renesas sales office to use the version L products.
REJ03B0241-0101 Rev.1.01 Dec 07, 2009
Page 3 of 105
R32C/161 Group
1.2
1. Overview
Product Information
Table 1.3 lists the product information and Figure 1.1 shows the details of the part number.
Table 1.3
R32C/161 Group Product List
As of December, 2009
Package Code (1) ROM Capacity (2) RAM Capacity
Part Number
E2dataFlash
Remarks
Version J
R5F64610JFP
R5F64610LFP
(D)
R5F64610KFP
(D)
R5F6461EJFP
(D)
R5F6461ELFP
(D)
R5F6461EKFP
(D)
R5F64611JFP
(D)
R5F64611LFP
(D)
R5F64611KFP
(D)
R5F6461FJFP
(D)
R5F6461FLFP
(D)
R5F6461FKFP
(D)
4 Kbytes
128 Kbytes
+ 8 Kbytes
Version L (3)
Version K
12 Kbytes
Version J
NA (3)
Version L (3)
Version K
PLQP0080KB-A
Version J
4 Kbytes
256 Kbytes
+ 8 Kbytes
Version L (3)
Version K
20 Kbytes
Version J
NA
(3)
Version L (3)
Version K
(D): Under development
Notes:
1. The old package code is as follows:PLQP0080KB-A: 80P6Q-A
2. Data flash memory provides an additional 8 Kbytes of ROM capacity.
3. Please contact a Renesas sales office to use the non-E2dataFlash version or the version L products.
REJ03B0241-0101 Rev.1.01 Dec 07, 2009
Page 4 of 105
R32C/161 Group
1. Overview
Part Number
R5 F 64 61 1 J XXX FP
Package Code
FP : PLQP0080KB-A
ROM Number
Omitted in the flash memory version
Temperature Code
J : -40°C to 85°C
L : -40°C to 105°C
K : -40°C to 125°C
ROM/RAM/E2dataFlash Capacity
0 : 128 KB / 12 KB / 4 KB
1 : 256 KB / 20 KB / 4 KB
E : 128 KB / 12 KB / none
F : 256 KB / 20 KB / none
R32C/161 Group
R32C/100 Series
Memory Type
F : Flash memory version
Figure 1.1
Part Numbering
REJ03B0241-0101 Rev.1.01 Dec 07, 2009
Page 5 of 105
R32C/161 Group
1.3
1. Overview
Block Diagram
Figure 1.2 shows a block diagram of the R32C/161 Group.
8
8
8
8
8
8
2
Port P0
Port P1
Port P2
Port P3
Port P4
Port P5
Port P6
Three-phase motor
controller
Watchdog timer:
Serial interface:
Serial bus interface:
1 channel
E2dataFlash
X-Y converter:
16 bits × 16 bits
DMAC
CRC calculator (CCITT)
Intelligent I/O
Time measurement: 8
Wave generation: 8
LIN Module:
1 channel
Figure 1.2
R32C/161 Group Block Diagram
REJ03B0241-0101 Rev.1.01 Dec 07, 2009
Page 6 of 105
FLG
INTB
ISP
USP
PC
SVF
SVP
VCT
Memory
ROM
RAM
Multiplier
Floating-point unit
5
2 channels
R2R0
R2R0
R3R1
R3R1
R6R4
R6R4
R7R5
R7R5
A0
A0
A1
A1
A2
A2
A3
A3
FB
FB
SB
SB
Port P9
CAN Module:
R32C/100 Series CPU Core
DMAC II
P9_1
X16 + X12 + X5 + 1
P8_5
5 channels
15 bits
5
Clock generator:
4 circuits
- XIN-XOUT
- XCIN-XCOUT
- On-chip oscillator
- PLL frequency synthesizer
4
A/D converter:
10 bits × 1 circuit
23 inputs
Port P8
Timer:
Timer A 16 bits × 5 timers
Timer B 16 bits × 6 timers
Port P7
Peripheral functions
R32C/161 Group
1.4
1. Overview
Pin Assignment
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
61
40
62
39
63
38
64
37
65
36
66
35
67
34
R32C/161 GROUP
68
69
33
32
70
31
71
30
PLQP0080KB-A
(80P6Q-A)
(Top view)
72
73
74
75
29
28
27
26
20
19
18
17
16
15
14
13
12
11
10
9
8
P3_7 / TA4IN / U / TB1IN / CTS4 / RTS4
P4_0 / CTS3 / RTS3 / SCS0
P4_1 / CLK3 / SSCK0
P4_2 / RXD3 / SSI0
P4_3 / TXD3 / SSO0
P4_4 / CTS1 / RTS1 / SS1 / LIN0OUT
P4_5 / CLK1 / LIN0IN
P4_6 / RXD1 / SCL1 / STXD1
P4_7 / TXD1 / SDA1 / SRXD1
P5_0 / IIO0_0
P5_1 / IIO0_1
P5_2 / IIO0_2
P5_3 / CLKOUT / IIO0_3
P5_4 / CTS0 / RTS0 / SS0 / IIO0_4
P5_5 / CLK0 / IIO0_5
P5_6 / RXD0 / SCL0 / STXD0 / IIO0_6
P5_7 / TXD0 / SDA0 / SRXD0 / IIO0_7
P6_5 / TA0IN / TB5IN
P6_7 / TA3IN
P7_0 / TXD2 / SDA2 / SRXD2
TB3IN / P9_3
VDC0
P9_1
VDC1
NSD
CNVSS
XCIN / P8_7
XCOUT / P8_6
RESET
XOUT
VSS
XIN
VCC
NMI / P8_5
INT2 / P8_4
CAN0WU / CAN0IN / CAN1WU / CAN1IN / INT1 / P8_3
CAN0OUT / CAN1OUT / INT0 / P8_2
CAN0OUT / SS2 / RTS2 / CTS2 / P7_6
CAN0WU / CAN0IN / LIN0IN / CLK2 / P7_5
LIN0OUT / STXD2 / SCL2 / RXD2 / P7_4
(Note 1)
7
21
6
22
80
5
23
79
4
24
78
3
25
77
2
76
1
IIO0_4 / TB0IN / AN_4 / P1_4
IIO0_3 / SCS0 / AN_3 / P1_3
IIO0_2 / SSI0 / AN_2 / P1_2
IIO0_1 / SSCK0 / AN_1 / P1_1
IIO0_0 / SSO0 / AN_0 / P1_0
AN0_7 / P0_7
AN0_6 / P0_6
AN0_5 / P0_5
AN0_4 / P0_4
AN0_3 / P0_3
AN0_2 / P0_2
AN0_1 / P0_1
AN0_0 / P0_0
RXD4 / TB2IN / ADTRG / P9_7
AVSS
CAN1OUT / TXD4 / ANEX1 / P9_6
VREF
AVCC / VCC
CAN1WU / CAN1IN / CLK4 / ANEX0 / P9_5
RTS4 / CTS4 / TB4IN / P9_4
59
60
P1_5 / INT3 / IIO0_5
P1_6 / INT4 / IIO0_6
P1_7 / INT5 / IIO0_7
P2_0 / AN2_0
P2_1 / AN2_1
P2_2 / AN2_2
P2_3 / AN2_3
P2_4 / AN2_4
P2_5 / AN2_5
P2_6 / AN2_6
P2_7 / AN2_7
VSS
P3_0 / TA0OUT / LIN0OUT / UD0A
VCC
P3_1 / TA3OUT / LIN0IN / UD0B
P3_2 / TA1OUT / V
P3_3 / TA1IN / V
P3_4 / TA2OUT / W / CLK4
P3_5 / TA2IN / W / RXD4
P3_6 / TA4OUT / U / TXD4
Figure 1.3 shows the pin assignment (top view) and Table 1.4 and Table 1.5 show the pin characteristics.
Note:
1. The position of pin number 1 varies by product. Refer to the index mark in attached “Package Dimensions”.
Figure 1.3
Pin Assignment (top view)
REJ03B0241-0101 Rev.1.01 Dec 07, 2009
Page 7 of 105
R32C/161 Group
Table 1.4
Pin
No.
Control
Pin
1
2
1. Overview
Pin Characteristics (1/2)
Port
Interrupt
Pin
P9_3
Timer Pin
UART / SBI Pin
Intelligent I/O
Pin
LIN /
CAN Module Pin
TB3IN
VDC0
3
P9_1
4
VDC1
5
NSD
6
CNVSS
7
XCIN
P8_7
8
XCOUT
P8_6
9
RESET
10
XOUT
11
VSS
12
XIN
13
VCC
14
P8_5
NMI
15
P8_4
INT2
16
P8_3
INT1
CAN0IN/CAN0WU/
CAN1IN/CAN1WU
17
P8_2
INT0
CAN0OUT/
CAN1OUT
18
P7_6
CTS2/RTS2/SS2
CAN0OUT
19
P7_5
CLK2
LIN0IN/CAN0IN/
CAN0WU
20
P7_4
RXD2/SCL2/STXD2
LIN0OUT
21
P7_0
22
P6_7
TA3IN
23
P6_5
TA0IN/
TB5IN
24
P5_7
TXD0/SDA0/SRXD0
IIO0_7
25
P5_6
RXD0/SCL0/STXD0
IIO0_6
26
P5_5
CLK0
IIO0_5
27
P5_4
CTS0/RTS0/SS0
IIO0_4
28
CLKOUT P5_3
IIO0_3
29
P5_2
IIO0_2
30
P5_1
IIO0_1
31
P5_0
IIO0_0
32
P4_7
TXD1/SDA1/SRXD1
33
P4_6
RXD1/SCL1/STXD1
34
P4_5
CLK1
LIN0IN
35
P4_4
CTS1/RTS1/SS1
LIN0OUT
36
P4_3
TXD3/SSO0
37
P4_2
RXD3/SSI0
38
P4_1
CLK3/SSCK0
39
P4_0
CTS3/RTS3/SCS0
TXD2/SDA2/SRXD2
REJ03B0241-0101 Rev.1.01 Dec 07, 2009
Page 8 of 105
Analog
Pin
R32C/161 Group
Table 1.5
Pin
No.
Control
Pin
1. Overview
Pin Characteristics (2/2)
Port
Interrupt
Pin
Timer Pin
UART / SBI Pin
Intelligent I/O
Pin
LIN /
CAN Module Pin
CTS4/RTS4
40
P3_7
TA4IN/U/
TB1IN
41
P3_6
TA4OUT/U TXD4
42
P3_5
TA2IN/W
43
P3_4
TA2OUT/W CLK4
44
P3_3
TA1IN/V
45
P3_2
TA1OUT/V
P3_1
TA3OUT
UD0B
LIN0IN
P3_0
TA0OUT
UD0A
LIN0OUT
46
47
RXD4
VCC
48
49
Analog
Pin
VSS
50
P2_7
AN2_7
51
P2_6
AN2_6
52
P2_5
AN2_5
53
P2_4
AN2_4
54
P2_3
AN2_3
55
P2_2
AN2_2
56
P2_1
AN2_1
57
P2_0
AN2_0
58
P1_7
INT5
IIO0_7
59
P1_6
INT4
IIO0_6
60
P1_5
INT3
IIO0_5
61
P1_4
TB0IN
IIO0_4
AN_4
62
P1_3
SCS0
IIO0_3
AN_3
63
P1_2
SSI0
IIO0_2
AN_2
64
P1_1
SSCK0
IIO0_1
AN_1
65
P1_0
SSO0
IIO0_0
AN_0
66
P0_7
AN0_7
67
P0_6
AN0_6
68
P0_5
AN0_5
69
P0_4
AN0_4
70
P0_3
AN0_3
71
P0_2
AN0_2
72
P0_1
AN0_1
73
P0_0
AN0_0
74
75
P9_7
TB2IN
ADTRG
RXD4
AVSS
76
P9_6
TXD4
CAN1OUT
ANEX1
79
P9_5
CLK4
CAN1IN/CAN1WU
ANEX0
80
P9_4
77
VREF
78
AVCC/
VCC
TB4IN
REJ03B0241-0101 Rev.1.01 Dec 07, 2009
Page 9 of 105
CTS4/RTS4
R32C/161 Group
1.5
1. Overview
Pin Definitions and Functions
Table 1.6 and Table 1.7 shows the pin definitions and functions.
Table 1.6
Pin Definitions and Functions (1/2)
Function
Symbol
Power supply
VCC, VSS
Connecting pins
for decoupling
capacitor
VDC0, VDC1
Analog power
supply
AVCC, AVSS
Reset input
I/O
Description
I
Applicable as follows: VCC = 3.0 to 5.5 V, VSS = 0 V
—
A decoupling capacitor for internal voltage should be
connected between VDC0 and VDC1
I
Power supply for the A/D converter. AVSS should be
connected to VSS
RESET
I
The MCU is reset when this pin is driven low
CNVSS
CNVSS
I
This pin should be connected to VSS via a resistor
Debug port
NSD
Main clock input
XIN
Main clock output XOUT
Sub clock input
XCIN
Sub clock output
XCOUT
Clock output
CLKOUT
External interrupt INT0 to INT5
input
NMI input
P8_5/NMI
I/O ports
P0_0 to P0_7
P1_0 to P1_7
P2_0 to P2_7
P3_0 to P3_7
P4_0 to P4_7
P5_0 to P5_7
P6_5, P6_7
P7_0, P7_4 to P7_6
P8_2 to P8_4
P8_6, P8_7
P9_3 to P9_7
Input port
P9_1
REJ03B0241-0101 Rev.1.01 Dec 07, 2009
Page 10 of 105
I/O
I
O
I
O
O
I
I
I/O
I
This pin is to communicate with a debugger. It should
be connected to VCC via a resistor of 1 to 4.7 kΩ
Input/output for the main clock oscillator. A crystal, or
a ceramic resonator should be connected between
pins XIN and XOUT. An external clock should be
input at the XIN while leaving the XOUT open
Input/output for the sub clock oscillator. A crystal
oscillator should be connected between pins XCIN
and XCOUT. An external clock should be input at the
XCIN while leaving the XCOUT open
Output of the clock with the same frequency as fC,
f8, or f32
Input for external interrupts
Input for NMI
I/O ports in CMOS. Each port can be programmed to
input or output under the control of the direction
register.
Pull-up resistors are selected for following 4-pin
units, but are enabled only for the input pins: Pi_0 to
Pi_3 and Pi_4 to Pi_7 (i = 0 to 9)
Input port in CMOS. Pull-up resistors are selectable
for P9_1 and P9_3
R32C/161 Group
Table 1.7
1. Overview
Pin Definitions and Functions (2/2)
Function
Timer A
Symbol
TA0OUT to TA4OUT
I/O
I/O
Description
Timers A0 to A4 input/output
TA0IN to TA4IN
I
Timers A0 to A4 input
Timer B
TB0IN to TB5IN
I
Timers B0 to B5 input
Three-phase
motor control
timer output
U, U, V, V, W, W
Serial interface
CTS0 to CTS4
I
Handshake input
RTS0 to RTS4
O
Handshake output
CLK0 to CLK4
I/O
Transmit/receive clock input/output
RXD0 to RXD4
I
Serial data input
TXD0 to TXD4
O
Serial data output
I2C bus
(simplified)
SDA0 to SDA2
I/O
Serial data input/output
SCL0 to SCL2
I/O
Transmit/receive clock input/output
Serial interface
special functions
STXD0 to STXD2
O
Serial data output in slave mode
SRXD0 to SRXD2
I
Serial data input in slave mode
SS0 to SS2
I
Input to control serial interface special functions
A/D converter
AN_0 to AN_4
AN0_0 to AN0_7
AN2_0 to AN2_7
I
ADTRG
I
ANEX0
ANEX1
Reference voltage VREF
input
Intelligent I/O
IIO0_0 to IIO0_7
UD0A, UD0B
Serial bus
interface
SSO0
I/O
External trigger input for the A/D converter
Expanded analog input for the A/D converter and
output in external op-amp connection mode
I
Expanded analog input for the A/D converter
I
Reference voltage input for the A/D converter and D/
A converter
I/O
I
Input/output for the Intelligent I/O group 0. Either
input capture or output compare is selectable
Input for the two-phase encoder
Serial data output. Functions as serial data input/
output in 4-wire serial bus mode
I/O
Serial data input. Functions as serial data input/
output in 4-wire serial bus mode
I/O
Transmit/receive clock input/output
I/O
Input/output to control the synchronous serial
interface
LIN0OUT
O
Transmit data output for the LIN communications
LIN0IN
I
Receive data input for the LIN communications
CAN0IN, CAN1IN
I
Receive data input for the CAN communications
CAN0OUT, CAN1OUT
O
Transmit data output for the CAN communications
CAN0WU, CAN1WU
I
Input for the CAN wake-up interrupt
SSCK0
SCS0
CAN module
Analog input for the A/D converter
I/O
SSI0
LIN module
Three-phase motor control timer output
O
REJ03B0241-0101 Rev.1.01 Dec 07, 2009
Page 11 of 105
R32C/161 Group
2.
2. Central Processing Unit (CPU)
Central Processing Unit (CPU)
The CPU contains registers as shown below. There are two register banks each consisting of registers
R2R0, R3R1, R6R4, R7R5, A0 to A3, SB, and FB.
General purpose
registers
b31
R2R0
R2H
R3R1
R3H
b23
R6R4
R6
R7R5
R7
b15
b7
R2L
R0H
R3L
R1H
b0
R0L
R1L
Data registers (1)
R4
R5
A0
A1
Address registers (1)
A2
A3
SB
Static base register (1)
FB
Frame base register (1)
USP
User stack pointer
ISP
Interrupt stack pointer
Interrupt vector table base register
INTB
b31
PC
Program counter
FLG
Flag register
b24 b23
b16 b15
RND
b8 b7
IPL
DP
FU
FO
Fast interrupt
registers
DMAC-associated
registers (2)
b31
b31
Blank fields represent reserved.
b0
SVF
Save flag register
SVP
Save PC register
VCT
Vector register
b0
b23
DMD0
DMD0
DMD0
DMD0
DCT0
DCT0
DCT0
DCT0
DCR0
DCR0
DCR0
DCR0
DSA0
DSA0
DSA0
DSA0
DSR0
DSR0
DSR0
DSR0
DDA0
DDA0
DDA0
DDA0
DDR0
DDR0
DDR0
DDR0
DMA mode register
DMA terminal count register
DMA terminal count reload register
DMA source address register
DMA source address reload register
DMA destination address register
DMA destination address reload register
Notes:
1. There are two banks of these registers.
2. There are four identical sets of DMAC-associated registers.
Figure 2.1
b0
U I O B S Z D C
CPU Registers
REJ03B0241-0101 Rev.1.01 Dec 07, 2009
Page 12 of 105
R32C/161 Group
2.1
2. Central Processing Unit (CPU)
General Purpose Registers
2.1.1
Data Registers (R2R0, R3R1, R6R4, and R7R5)
These 32-bit registers are primarily used for transfers and arithmetic/logic operations.
Each of the registers can be divided into upper and lower 16-bit registers, e.g. R2R0 can be divided into
R2 and R0, R3R0 can be divided into R3 and R1, etc.
Moreover, data registers R2R0 and R3R1 can be divided into four 8-bit data registers: upper (R2H and
R3H), mid-upper (R2L and R3L), mid-lower (R0H and R1H), and lower (R0L and R1L).
2.1.2
Address Registers (A0, A1, A2, and A3)
These 32-bit registers have functions similar to data registers. They are also used for address register
indirect addressing and address register relative addressing.
2.1.3
Static Base Register (SB)
This 32-bit register is used for SB relative addressing.
2.1.4
Frame Base Register (FB)
This 32-bit register is used for FB relative addressing.
2.1.5
Program Counter (PC)
This 32-bit counter indicates the address of the instruction to be executed next.
2.1.6
Interrupt Vector Table Base Register (INTB)
This 32-bit register indicates the start address of a relocatable vector table.
2.1.7
User Stack Pointer (USP) and Interrupt Stack Pointer (ISP)
Two types of 32-bit stack pointers (SPs) are provided: user stack pointer (USP) and interrupt stack
pointer (ISP).
Use the stack pointer select flag (U flag) to select either the user stack pointer (USP) or the interrupt
stack pointer (ISP). The U flag is bit 7 in the flag register (FLG). Refer to 2.1.8 “Flag Register (FLG)” for
details.
To minimize the overhead of interrupt sequence due to less memory access, set the user stack pointer
(USP) or the interrupt stack pointer (ISP) to a multiple of 4.
2.1.8
Flag Register (FLG)
This 32-bit register indicates the CPU status.
2.1.8.1
Carry Flag (C flag)
This flag becomes 1 when any of the carry, borrow, shifted-out bit, etc. is generated in the arithmetic
logic unit (ALU).
2.1.8.2
Debug Flag (D flag)
This flag is only for debugging. Only set this bit to 0.
2.1.8.3
Zero Flag (Z flag)
This flag becomes 1 when the result of an operation is 0; otherwise it is 0.
2.1.8.4
Sign Flag (S flag)
This flag becomes 1 when the result of an operation is a negative value; otherwise it is 0.
REJ03B0241-0101 Rev.1.01 Dec 07, 2009
Page 13 of 105
R32C/161 Group
2.1.8.5
2. Central Processing Unit (CPU)
Register Bank Select Flag (B flag)
This flag selects a register bank. It indicates 0 when the register bank 0 is selected, and 1 when the
register bank 1 is selected.
2.1.8.6
Overflow Flag (O flag)
This flag becomes 1 if an overflow occurs in an operation; otherwise it is 0.
2.1.8.7
Interrupt Enable Flag (I flag)
This flag enables maskable interrupts. To disable maskable interrupts, set this flag to 0. To enable
them, set this flag to 1. When an interrupt is accepted, the flag becomes 0.
2.1.8.8
Stack Pointer Select Flag (U flag)
To select the interrupt stack pointer (ISP), set this flag to 0. To select the user stack pointer (USP), set
this flag to 1.
It becomes 0 when a hardware interrupts is accepted or when an INT instruction designated by a
software interrupt number from 0 to 127 is executed.
2.1.8.9
Floating-point Underflow Flag (FU flag)
This flag becomes 1 when an underflow occurs in a floating-point operation; otherwise it is 0. It also
becomes 1 when the operand has invalid numbers (subnormal numbers).
2.1.8.10
Floating-point Overflow Flag (FO flag)
This flag becomes 1 when an overflow occurs in a floating-point operation; otherwise it is 0. It also
becomes 1 when the operand has invalid numbers (subnormal numbers).
2.1.8.11
Processor Interrupt Priority Level (IPL)
The processor interrupt priority level (IPL), consisting of three bits, selects a processor interrupt priority
level from level 0 to 7. An interrupt is acceptable when the interrupt request level is higher than the
selected IPL.
When the processor interrupt priority level (IPL) is set to 111b (level 7), all interrupts are disabled.
2.1.8.12
Fixed-point Radix Point Designation Bit (DP bit)
This bit designates the radix point. It also specifies which portion of the fixed-point multiplication result
to take. It is used in the MULX instruction.
2.1.8.13
Floating-point Rounding Mode (RND)
The 2-bit floating-point rounding mode selects a rounding mode for floating-point calculation results.
2.1.8.14
Reserved
Only set this bit to 0. The read value is undefined.
REJ03B0241-0101 Rev.1.01 Dec 07, 2009
Page 14 of 105
R32C/161 Group
2.2
2. Central Processing Unit (CPU)
Fast Interrupt Registers
The following three registers are provided to minimize the overhead of interrupt sequence.
2.2.1
Save Flag Register (SVF)
This 32-bit register is used to save the flag register when a fast interrupt is generated.
2.2.2
Save PC Register (SVP)
This 32-bit register is used to save the program counter when a fast interrupt is generated.
2.2.3
Vector Register (VCT)
This 32-bit register is used to indicate a jump address when a fast interrupt is generated.
2.3
DMAC-associated Registers
There are seven types of DMAC-associated registers.
2.3.1
DMA Mode Registers (DMD0, DMD1, DMD2, and DMD3)
These 32-bit registers are used to set DMA transfer mode, bit rate etc.
2.3.2
DMA Terminal Count Registers (DCT0, DCT1, DCT2, and DCT3)
These 24-bit registers are used to set DMA transfer counting.
2.3.3
DMA Terminal Count Reload Registers (DCR0, DCR1, DCR2, and DCR3)
These 24-bit registers are used to set the reloaded values for DMA terminal count registers.
2.3.4
DMA Source Address Registers (DSA0, DSA1, DSA2, and DSA3)
These 32-bit registers are used to set DMA source addresses.
2.3.5
DMA Source Address Reload Registers (DSR0, DSR1, DSR2, and DSR3)
These 32-bit registers are used to set the reloaded value for DMA source address register.
2.3.6
DMA Destination Address Registers (DDA0, DDA1, DDA2, and DDA3)
These 32-bit registers are used to set DMA destination address.
2.3.7
DMA Destination Address Reload Registers (DDR0, DDR1, DDR2, and
DDR3)
These 32-bit registers are used to set reloaded values for DMA destination address registers.
REJ03B0241-0101 Rev.1.01 Dec 07, 2009
Page 15 of 105
R32C/161 Group
3.
3. Memory
Memory
Figure 3.1 shows the memory map of the R32C/161 Group.
The R32C/161 Group provides a 4-Gbyte address space from 00000000h to FFFFFFFFh.
The internal ROM is mapped to the end of the memory map with the ending address fixed at FFFFFFFFh.
Therefore, the 256-Kbyte internal ROM is mapped from FFFC0000h to FFFFFFFFh.
The fixed interrupt vector table which contains each start address of interrupt handlers is mapped from
FFFFFFDCh to FFFFFFFFh.
The internal RAM is mapped to the beginning of the memory map with the starting address fixed at
00000400h. Therefore, the 20-Kbyte internal RAM is mapped from 00000400h to 000053FFh. Besides
being used for data storage, the internal RAM functions as a stack(s) for subroutines and/or interrupt
handlers.
Special Function Registers (SFRs), which are control registers for peripheral functions, are mapped from
00000000h to 000003FFh, and from 00040000h to 0004FFFFh. Unoccupied SFR locations are reserved.
No access is allowed.
00000000h
SFR1
00000400h
Internal RAM
Internal RAM
Capacity
XXXXXXXXh
12 Kbytes
00003400h
20 Kbytes
00005400h
XXXXXXXXh
Reserved
00040000h
SFR2
00050000h
Reserved
00060000h
Internal ROM
(Data space) (1)
00062000h
Internal ROM
Capacity
YYYYYYYYh
128 Kbytes
FFFE0000h
256 Kbytes
FFFC0000h
Reserved
YYYYYYYYh
Internal ROM
FFFFFFFFh
FFFFFFDCh Undefined instruction
Overflow
BRK instruction
Reserved
Reserved
Watchdog timer (2)
Reserved
NMI
Reset
FFFFFFFFh
Notes:
1. Additional two 4-Kbyte spaces (blocks A and B) for storing data are provided in the flash memory version.
2. The watchdog timer interrupt shares the vector table with the oscillator stop detection interrupt and low
voltage detection interrupt.
Figure 3.1
Memory Map
REJ03B0241-0101 Rev.1.01 Dec 07, 2009
Page 16 of 105
R32C/161 Group
4.
4. Special Function Registers (SFRs)
Special Function Registers (SFRs)
SFRs are memory-mapped peripheral registers that control the operation of peripherals. Table 4.1 SFR List
(1) to Table 4.53 SFR List (53) list the SFR details.
Table 4.1
SFR List (1)
Address
Register
000000h
000001h
000002h
000003h
000004h Clock Control Register
000005h
000006h Flash Memory Control Register
000007h Protect Release Register
000008h
000009h
00000Ah
00000Bh
00000Ch
00000Dh
00000Eh
00000Fh
000010h
000011h
000012h
000013h
000014h
000015h
000016h
000017h
000018h
000019h
00001Ah
00001Bh
00001Ch Flash Memory Rewrite Bus Control Register
00001Dh
00001Eh Peripheral Bus Control Register
00001Fh
000020h to
00005Fh
X: Undefined
Blanks are reserved. No access is allowed.
REJ03B0241-0101 Rev.1.01 Dec 07, 2009
Page 17 of 105
Symbol
Reset Value
CCR
0001 1000b
FMCR
PRR
0000 0001b
00h
FEBC
0000h
PBC
0504h
R32C/161 Group
Table 4.2
Address
000060h
000061h
000062h
000063h
000064h
000065h
000066h
000067h
000068h
000069h
00006Ah
00006Bh
00006Ch
00006Dh
00006Eh
00006Fh
000070h
000071h
000072h
000073h
000074h
000075h
000076h
000077h
000078h
000079h
00007Ah
00007Bh
00007Ch
00007Dh
00007Eh
00007Fh
000080h
000081h
000082h
000083h
000084h
000085h
000086h
000087h
4. Special Function Registers (SFRs)
SFR List (2)
Register
Symbol
Reset Value
Timer B5 Interrupt Control Register
TB5IC
XXXX X000b
UART2 Receive/ACK Interrupt Control Register
S2RIC
XXXX X000b
DMA0 Transfer Complete Interrupt Control Register
UART0 Start Condition/Stop Condition Detection Interrupt
Control Register
DMA2 Transfer Complete Interrupt Control Register
A/D Converter 0 Convert Completion Interrupt Control Register
Timer A0 Interrupt Control Register
Intelligent I/O Interrupt Control Register 0
Timer A2 Interrupt Control Register
Intelligent I/O Interrupt Control Register 2
Timer A4 Interrupt Control Register
Intelligent I/O Interrupt Control Register 4
UART0 Receive/ACK Interrupt Control Register
Intelligent I/O Interrupt Control Register 6
UART1 Receive/ACK Interrupt Control Register
Intelligent I/O Interrupt Control Register 8
Timer B1 Interrupt Control Register
Intelligent I/O Interrupt Control Register 10
Timer B3 Interrupt Control Register
DM0IC
BCN0IC
XXXX X000b
XXXX X000b
DM2IC
AD0IC
TA0IC
IIO0IC
TA2IC
IIO2IC
TA4IC
IIO4IC
S0RIC
IIO6IC
S1RIC
IIO8IC
TB1IC
IIO10IC
TB3IC
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
INT5 Interrupt Control Register
CAN0 Wake-up Interrupt Control Register
INT3 Interrupt Control Register
INT5IC
C0WIC
INT3IC
XX00 X000b
XXXX X000b
XX00 X000b
INT1 Interrupt Control Register
LIN Low Detection Interrupt Control Register
INT1IC
LLDIC
XX00 X000b
XXXX X000b
UART2 Transmit/NACK Interrupt Control Register
S2TIC
XXXX X000b
BCN2IC
XXXX X000b
UART2 Start Condition/Stop Condition Detection Interrupt
Control Register
X: Undefined
Blanks are reserved. No access is allowed.
REJ03B0241-0101 Rev.1.01 Dec 07, 2009
Page 18 of 105
R32C/161 Group
Table 4.3
4. Special Function Registers (SFRs)
SFR List (3)
Address
Register
000088h DMA1 Transfer Complete Interrupt Control Register
000089h UART1 Start Condition/Stop Condition Detection Interrupt
Control Register
00008Ah DMA3 Transfer Complete Interrupt Control Register
00008Bh
00008Ch Timer A1 Interrupt Control Register
00008Dh Intelligent I/O Interrupt Control Register 1
00008Eh Timer A3 Interrupt Control Register
00008Fh Intelligent I/O Interrupt Control Register 3
000090h UART0 Transmit/NACK Interrupt Control Register
000091h Intelligent I/O Interrupt Control Register 5
000092h UART1 Transmit/NACK Interrupt Control Register
000093h Intelligent I/O Interrupt Control Register 7
000094h Timer B0 Interrupt Control Register
000095h Intelligent I/O Interrupt Control Register 9
000096h Timer B2 Interrupt Control Register
000097h Intelligent I/O Interrupt Control Register 11
000098h Timer B4 Interrupt Control Register
000099h
00009Ah INT4 Interrupt Control Register
00009Bh CAN1 Wake-up Interrupt Control Register
00009Ch INT2 Interrupt Control Register
00009Dh
00009Eh INT0 Interrupt Control Register
00009Fh
0000A0h Intelligent I/O Interrupt Request Register 0
0000A1h Intelligent I/O Interrupt Request Register 1
0000A2h Intelligent I/O Interrupt Request Register 2
0000A3h Intelligent I/O Interrupt Request Register 3
0000A4h Intelligent I/O Interrupt Request Register 4
0000A5h Intelligent I/O Interrupt Request Register 5
0000A6h Intelligent I/O Interrupt Request Register 6
0000A7h Intelligent I/O Interrupt Request Register 7
0000A8h Intelligent I/O Interrupt Request Register 8
0000A9h Intelligent I/O Interrupt Request Register 9
0000AAh Intelligent I/O Interrupt Request Register 10
0000ABh Intelligent I/O Interrupt Request Register 11
0000ACh
0000ADh
0000AEh
0000AFh
X: Undefined
Blanks are reserved. No access is allowed.
REJ03B0241-0101 Rev.1.01 Dec 07, 2009
Page 19 of 105
Symbol
DM1IC
BCN1IC
Reset Value
XXXX X000b
XXXX X000b
DM3IC
XXXX X000b
TA1IC
IIO1IC
TA3IC
IIO3IC
S0TIC
IIO5IC
S1TIC
IIO7IC
TB0IC
IIO9IC
TB2IC
IIO11IC
TB4IC
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
INT4IC
C1WIC
INT2IC
XX00 X000b
XXXX X000b
XX00 X000b
INT0IC
XX00 X000b
IIO0IR
IIO1IR
IIO2IR
IIO3IR
IIO4IR
IIO5IR
IIO6IR
IIO7IR
IIO8IR
IIO9IR
IIO10IR
IIO11IR
0000 00X1b
0000 00X1b
0000 0001b
0000 00X1b
0000 00X1b
0000 00X1b
0000 00X1b
000X 00X1b
0000 0001b
0000 0001b
0000 0001b
0000 00X1b
R32C/161 Group
Table 4.4
4. Special Function Registers (SFRs)
SFR List (4)
Address
Register
0000B0h Intelligent I/O Interrupt Enable Register 0
0000B1h Intelligent I/O Interrupt Enable Register 1
0000B2h Intelligent I/O Interrupt Enable Register 2
0000B3h Intelligent I/O Interrupt Enable Register 3
0000B4h Intelligent I/O Interrupt Enable Register 4
0000B5h Intelligent I/O Interrupt Enable Register 5
0000B6h Intelligent I/O Interrupt Enable Register 6
0000B7h Intelligent I/O Interrupt Enable Register 7
0000B8h Intelligent I/O Interrupt Enable Register 8
0000B9h Intelligent I/O Interrupt Enable Register 9
0000BAh Intelligent I/O Interrupt Enable Register 10
0000BBh Intelligent I/O Interrupt Enable Register 11
0000BCh
0000BDh
0000BEh
0000BFh
0000C0h Serial Bus Interface 0 Interrupt Control Register
0000C1h CAN0 Transmit Interrupt Control Register
0000C2h
0000C3h CAN0 Error Interrupt Control Register
0000C4h
0000C5h CAN1 Receive Interrupt Control Register
0000C6h
0000C7h
0000C8h
0000C9h
0000CAh
0000CBh
0000CCh
0000CDh
0000CEh
0000CFh
0000D0h CAN0 Transmit FIFO Interrupt Control Register
0000D1h
0000D2h CAN1 Transmit FIFO Interrupt Control Register
0000D3h
0000D4h
0000D5h LIN0 Interrupt Control Register
0000D6h
0000D7h
0000D8h E2dataFlash Interrupt Control Register
0000D9h
0000DAh
0000DBh
0000DCh
0000DDh UART3 Transmit Interrupt Control Register
0000DEh
0000DFh UART4 Transmit Interrupt Control Register
X: Undefined
Blanks are reserved. No access is allowed.
REJ03B0241-0101 Rev.1.01 Dec 07, 2009
Page 20 of 105
Symbol
IIO0IE
IIO1IE
IIO2IE
IIO3IE
IIO4IE
IIO5IE
IIO6IE
IIO7IE
IIO8IE
IIO9IE
IIO10IE
IIO11IE
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
Reset Value
SS0IC
C0TIC
XXXX X000b
XXXX X000b
C0EIC
XXXX X000b
C1RIC
XXXX X000b
C0FTIC
XXXX X000b
C1FTIC
XXXX X000b
L0IC
XXXX X000b
E2FIC
XXXX X000b
S3TIC
XXXX X000b
S4TIC
XXXX X000b
R32C/161 Group
Table 4.5
4. Special Function Registers (SFRs)
SFR List (5)
Address
Register
0000E0h
0000E1h CAN0 Receive Interrupt Control Register
0000E2h
0000E3h CAN1 Transmit Interrupt Control Register
0000E4h
0000E5h CAN1 Error Interrupt Control Register
0000E6h
0000E7h
0000E8h
0000E9h
0000EAh
0000EBh
0000ECh
0000EDh
0000EEh
0000EFh
0000F0h CAN0 Receive FIFO Interrupt Control Register
0000F1h
0000F2h CAN1 Receive FIFO Interrupt Control Register
0000F3h
0000F4h
0000F5h
0000F6h
0000F7h
0000F8h
0000F9h
0000FAh
0000FBh
0000FCh
0000FDh UART3 Receive Interrupt Control Register
0000FEh
0000FFh UART4 Receive Interrupt Control Register
000100h
000101h
000102h
000103h
000104h
000105h
000106h
000107h
X: Undefined
Blanks are reserved. No access is allowed.
REJ03B0241-0101 Rev.1.01 Dec 07, 2009
Page 21 of 105
Symbol
Reset Value
C0RIC
XXXX X000b
C1TIC
XXXX X000b
C1EIC
XXXX X000b
C0FRIC
XXXX X000b
C1FRIC
XXXX X000b
S3RIC
XXXX X000b
S4RIC
XXXX X000b
R32C/161 Group
Table 4.6
4. Special Function Registers (SFRs)
SFR List (6)
Address
Register
000108h to
00016Fh
000170h
000171h
000172h
000173h
000174h
000175h
000176h
000177h
000178h
000179h
00017Ah
00017Bh
00017Ch
00017Dh
00017Eh
00017Fh
000180h Group 0 Time Measurement/Waveform Generation Register 0
000181h
000182h Group 0 Time Measurement/Waveform Generation Register 1
000183h
000184h Group 0 Time Measurement/Waveform Generation Register 2
000185h
000186h Group 0 Time Measurement/Waveform Generation Register 3
000187h
000188h Group 0 Time Measurement/Waveform Generation Register 4
000189h
00018Ah Group 0 Time Measurement/Waveform Generation Register 5
00018Bh
00018Ch Group 0 Time Measurement/Waveform Generation Register 6
00018Dh
00018Eh Group 0 Time Measurement/Waveform Generation Register 7
00018Fh
000190h Group 0 Waveform Generation Control Register 0
000191h Group 0 Waveform Generation Control Register 1
000192h Group 0 Waveform Generation Control Register 2
000193h Group 0 Waveform Generation Control Register 3
000194h Group 0 Waveform Generation Control Register 4
000195h Group 0 Waveform Generation Control Register 5
000196h Group 0 Waveform Generation Control Register 6
000197h Group 0 Waveform Generation Control Register 7
000198h Group 0 Time Measurement Control Register 0
000199h Group 0 Time Measurement Control Register 1
00019Ah Group 0 Time Measurement Control Register 2
00019Bh Group 0 Time Measurement Control Register 3
00019Ch Group 0 Time Measurement Control Register 4
00019Dh Group 0 Time Measurement Control Register 5
00019Eh Group 0 Time Measurement Control Register 6
00019Fh Group 0 Time Measurement Control Register 7
X: Undefined
Blanks are reserved. No access is allowed.
REJ03B0241-0101 Rev.1.01 Dec 07, 2009
Page 22 of 105
Symbol
Reset Value
G0TM0/G0PO0
XXXXh
G0TM1/G0PO1
XXXXh
G0TM2/G0PO2
XXXXh
G0TM3/G0PO3
XXXXh
G0TM4/G0PO4
XXXXh
G0TM5/G0PO5
XXXXh
G0TM6/G0PO6
XXXXh
G0TM7/G0PO7
XXXXh
G0POCR0
G0POCR1
G0POCR2
G0POCR3
G0POCR4
G0POCR5
G0POCR6
G0POCR7
G0TMCR0
G0TMCR1
G0TMCR2
G0TMCR3
G0TMCR4
G0TMCR5
G0TMCR6
G0TMCR7
0000 X000b
0X00 X000b
0X00 X000b
0X00 X000b
0X00 X000b
0X00 X000b
0X00 X000b
0X00 X000b
00h
00h
00h
00h
00h
00h
00h
00h
R32C/161 Group
Table 4.7
4. Special Function Registers (SFRs)
SFR List (7)
Address
Register
0001A0h Group 0 Base Timer Register
0001A1h
0001A2h Group 0 Base Timer Control Register 0
0001A3h Group 0 Base Timer Control Register 1
0001A4h Group 0 Timer Measurement Prescaler Register 6
0001A5h Group 0 Timer Measurement Prescaler Register 7
0001A6h Group 0 Function Enable Register
0001A7h Group 0 Function Select Register
0001A8h
0001A9h
0001AAh
0001ABh
0001ACh
0001ADh
0001AEh
0001AFh
0001B0h
0001B1h
0001B2h
0001B3h
0001B4h
0001B5h
0001B6h
0001B7h
0001B8h
0001B9h
0001BAh
0001BBh
0001BCh
0001BDh
0001BEh
0001BFh
0001C0h
0001C1h
0001C2h
0001C3h
0001C4h
0001C5h
0001C6h
0001C7h
0001C8h
0001C9h
0001CAh
0001CBh
0001CCh
0001CDh
0001CEh
0001CFh
X: Undefined
Blanks are reserved. No access is allowed.
REJ03B0241-0101 Rev.1.01 Dec 07, 2009
Page 23 of 105
G0BT
Symbol
Reset Value
XXXXh
G0BCR0
G0BCR1
G0TPR6
G0TPR7
G0FE
G0FS
00h
0000 0000b
00h
00h
00h
00h
R32C/161 Group
Table 4.8
4. Special Function Registers (SFRs)
SFR List (8)
Address
Register
0001D0h
0001D1h
0001D2h
0001D3h
0001D4h
0001D5h
0001D6h
0001D7h
0001D8h
0001D9h
0001DAh
0001DBh
0001DCh
0001DDh
0001DEh
0001DFh
0001E0h UART3 Transmit/Receive Mode Register
0001E1h UART3 Bit Rate Register
0001E2h UART3 Transmit Buffer Register
0001E3h
0001E4h UART3 Transmit/Receive Control Register 0
0001E5h UART3 Transmit/Receive Control Register 1
0001E6h UART3 Receive Buffer Register
0001E7h
0001E8h UART4 Transmit/Receive Mode Register
0001E9h UART4 Bit Rate Register
0001EAh UART4 Transmit Buffer Register
0001EBh
0001ECh UART4 Transmit/Receive Control Register 0
0001EDh UART4 Transmit/Receive Control Register 1
0001EEh UART4 Receive Buffer Register
0001EFh
0001F0h UART3, UART4 Transmit/Receive Control Register 2
0001F1h
0001F2h
0001F3h
0001F4h
0001F5h
0001F6h
0001F7h
0001F8h
0001F9h
0001FAh
0001FBh
0001FCh
0001FDh
0001FEh
0001FFh
X: Undefined
Blanks are reserved. No access is allowed.
REJ03B0241-0101 Rev.1.01 Dec 07, 2009
Page 24 of 105
Symbol
Reset Value
U3MR
U3BRG
U3TB
00h
XXh
XXXXh
U3C0
U3C1
U3RB
00X0 1000b
XXXX 0010b
XXXXh
U4MR
U4BRG
U4TB
00h
XXh
XXXXh
U4C0
U4C1
U4RB
00X0 1000b
XXXX 0010b
XXXXh
U34CON
X000 0000b
R32C/161 Group
Table 4.9
4. Special Function Registers (SFRs)
SFR List (9)
Address
Register
000200h Group0 Phase Shift Waveform Output Mode Clock Division
Setting Register
000201h Group0 Phase Shift Waveform Output Mode Control Register
000202h
000203h
000204h
000205h
000206h
000207h
000208h Timer B Event Clock Select Register
000209h
00020Ah
00020Bh
00020Ch
00020Dh
00020Eh
00020Fh
000210h IIO0_7 Digital Debounce Register
000211h
000212h
000213h
000214h
000215h
000216h
000217h
000218h
000219h
00021Ah
00021Bh
00021Ch
00021Dh
00021Eh
00021Fh
000220h Timer A1 Mirror Register
000221h
000222h Timer A1-1 Mirror Register
000223h
000224h Timer A2 Mirror Register
000225h
000226h Timer A2-1 Mirror Register
000227h
000228h Timer A4 Mirror Register
000229h
00022Ah Timer A4-1 Mirror Register
00022Bh
00022Ch
00022Dh
00022Eh
00022Fh
X: Undefined
Blanks are reserved. No access is allowed.
REJ03B0241-0101 Rev.1.01 Dec 07, 2009
Page 25 of 105
Symbol
G0SDR
00h
Reset Value
G0PSCR
00h
TBECKS
0000 0000b
IC07DDR
FFh
TA1M
XXXXh
TA11M
XXXXh
TA2M
XXXXh
TA21M
XXXXh
TA4M
XXXXh
TA41M
XXXXh
R32C/161 Group
Table 4.10
4. Special Function Registers (SFRs)
SFR List (10)
Address
Register
000230h to
0002BFh
0002C0h X0 Register/Y0 Register
0002C1h
0002C2h X1 Register/Y1 Register
0002C3h
0002C4h X2 Register/Y2 Register
0002C5h
0002C6h X3 Register/Y3 Register
0002C7h
0002C8h X4 Register/Y4 Register
0002C9h
0002CAh X5 Register/Y5 Register
0002CBh
0002CCh X6 Register/Y6 Register
0002CDh
0002CEh X7 Register/Y7 Register
0002CFh
0002D0h X8 Register/Y8 Register
0002D1h
0002D2h X9 Register/Y9 Register
0002D3h
0002D4h X10 Register/Y10 Register
0002D5h
0002D6h X11 Register/Y11 Register
0002D7h
0002D8h X12 Register/Y12 Register
0002D9h
0002DAh X13 Register/Y13 Register
0002DBh
0002DCh X14 Register/Y14 Register
0002DDh
0002DEh X15 Register/Y15 Register
0002DFh
0002E0h XY Control Register
0002E1h
0002E2h
0002E3h
0002E4h UART1 Special Mode Register 4
0002E5h UART1 Special Mode Register 3
0002E6h UART1 Special Mode Register 2
0002E7h UART1 Special Mode Register
0002E8h UART1 Transmit/Receive Mode Register
0002E9h UART1 Bit Rate Register
0002EAh UART1 Transmit Buffer Register
0002EBh
0002ECh UART1 Transmit/Receive Control Register 0
0002EDh UART1 Transmit/Receive Control Register 1
0002EEh UART1 Receive Buffer Register
0002EFh
X: Undefined
Blanks are reserved. No access is allowed.
REJ03B0241-0101 Rev.1.01 Dec 07, 2009
Page 26 of 105
Symbol
Reset Value
X0R/Y0R
XXXXh
X1R/Y1R
XXXXh
X2R/Y2R
XXXXh
X3R/Y3R
XXXXh
X4R/Y4R
XXXXh
X5R/Y5R
XXXXh
X6R/Y6R
XXXXh
X7R/Y7R
XXXXh
X8R/Y8R
XXXXh
X9R/Y9R
XXXXh
X10R/Y10R
XXXXh
X11R/Y11R
XXXXh
X12R/Y12R
XXXXh
X13R/Y13R
XXXXh
X14R/Y14R
XXXXh
X15R/Y15R
XXXXh
XYC
XXXX XX00b
U1SMR4
U1SMR3
U1SMR2
U1SMR
U1MR
U1BRG
U1TB
00h
00h
00h
00h
00h
XXh
XXXXh
U1C0
U1C1
U1RB
0000 1000b
0000 0010b
XXXXh
R32C/161 Group
Table 4.11
4. Special Function Registers (SFRs)
SFR List (11)
Address
Register
0002F0h
0002F1h
0002F2h
0002F3h
0002F4h
0002F5h
0002F6h
0002F7h
0002F8h
0002F9h
0002FAh
0002FBh
0002FCh
0002FDh
0002FEh
0002FFh
000300h Count Start Register for Timers B3, B4 and B5
000301h
000302h Timer A1-1 Register
000303h
000304h Timer A2-1 Register
000305h
000306h Timer A4-1 Register
000307h
000308h Three-phase PWM Control Register 0
000309h Three-phase PWM Control Register 1
00030Ah Three-phase Output Buffer Register 0
00030Bh Three-phase Output Buffer Register 1
00030Ch Dead Time Timer
00030Dh Timer B2 Interrupt Generating Frequency Set Counter
00030Eh
00030Fh
000310h Timer B3 Register
000311h
000312h Timer B4 Register
000313h
000314h Timer B5 Register
000315h
000316h
000317h
000318h
000319h
00031Ah
00031Bh Timer B3 Mode Register
00031Ch Timer B4 Mode Register
00031Dh Timer B5 Mode Register
00031Eh
00031Fh
X: Undefined
Blanks are reserved. No access is allowed.
REJ03B0241-0101 Rev.1.01 Dec 07, 2009
Page 27 of 105
Symbol
Reset Value
TBSR
000X XXXXb
TA11
XXXXh
TA21
XXXXh
TA41
XXXXh
INVC0
INVC1
IDB0
IDB1
DTT
ICTB2
00h
00h
XX11 1111b
XX11 1111b
XXh
XXh
TB3
XXXXh
TB4
XXXXh
TB5
XXXXh
TB3MR
TB4MR
TB5MR
00XX 0000b
00XX 0000b
00XX 0000b
R32C/161 Group
Table 4.12
4. Special Function Registers (SFRs)
SFR List (12)
Address
Register
000320h
000321h
000322h
000323h
000324h
000325h
000326h
000327h
000328h
000329h
00032Ah
00032Bh
00032Ch
00032Dh
00032Eh
00032Fh
000330h
000331h
000332h
000333h
000334h UART2 Special Mode Register 4
000335h UART2 Special Mode Register 3
000336h UART2 Special Mode Register 2
000337h UART2 Special Mode Register
000338h UART2 Transmission/Receive Mode Register
000339h UART2 Bit Rate Register
00033Ah UART2 Transmit Buffer Register
00033Bh
00033Ch UART2 Transmit/Receive Control Register 0
00033Dh UART2 Transmit/Receive Control Register 1
00033Eh UART2 Receive Buffer Register
00033Fh
000340h Count Start Register
000341h Clock Prescaler Reset Register
000342h One-shot Start Register
000343h Trigger Select Register
000344h Increment/Decrement Counting Select Register
000345h
000346h Timer A0 Register
000347h
000348h Timer A1 Register
000349h
00034Ah Timer A2 Register
00034Bh
00034Ch Timer A3 Register
00034Dh
00034Eh Timer A4 Register
00034Fh
X: Undefined
Blanks are reserved. No access is allowed.
REJ03B0241-0101 Rev.1.01 Dec 07, 2009
Page 28 of 105
Symbol
Reset Value
U2SMR4
U2SMR3
U2SMR2
U2SMR
U2MR
U2BRG
U2TB
00h
00h
00h
00h
00h
XXh
XXXXh
U2C0
U2C1
U2RB
0000 1000b
0000 0010b
XXXXh
TABSR
CPSRF
ONSF
TRGSR
UDF
00h
0XXX XXXXb
00h
00h
0000 0000b
TA0
XXXXh
TA1
XXXXh
TA2
XXXXh
TA3
XXXXh
TA4
XXXXh
R32C/161 Group
Table 4.13
4. Special Function Registers (SFRs)
SFR List (13)
Address
Register
000350h Timer B0 Register
000351h
000352h Timer B1 Register
000353h
000354h Timer B2 Register
000355h
000356h Timer A0 Mode Register
000357h Timer A1 Mode Register
000358h Timer A2 Mode Register
000359h Timer A3 Mode Register
00035Ah Timer A4 Mode Register
00035Bh Timer B0 Mode Register
00035Ch Timer B1 Mode Register
00035Dh Timer B2 Mode Register
00035Eh Timer B2 Special Mode Register
00035Fh Count Source Prescaler Register
000360h
000361h
000362h
000363h
000364h UART0 Special Mode Register 4
000365h UART0 Special Mode Register 3
000366h UART0 Special Mode Register 2
000367h UART0 Special Mode Register
000368h UART0 Transmit/Receive Mode Register
000369h UART0 Bit Rate Register
00036Ah UART0 Transmit Buffer Register
00036Bh
00036Ch UART0 Transmit/Receive Control Register 0
00036Dh UART0 Transmit/Receive Control Register 1
00036Eh UART0 Receive Buffer Register
00036Fh
000370h
000371h
000372h
000373h
000374h
000375h
000376h
000377h
000378h
000379h
00037Ah
00037Bh
00037Ch CRC Data Register
00037Dh
00037Eh CRC Input Register
00037Fh
X: Undefined
Blanks are reserved. No access is allowed.
REJ03B0241-0101 Rev.1.01 Dec 07, 2009
Page 29 of 105
TB0
Symbol
Reset Value
XXXXh
TB1
XXXXh
TB2
XXXXh
TA0MR
TA1MR
TA2MR
TA3MR
TA4MR
TB0MR
TB1MR
TB2MR
TB2SC
TCSPR
0000 0000b
0000 0000b
0000 0000b
0000 0000b
0000 0000b
00XX 0000b
00XX 0000b
00XX 0000b
XXXX XXX0b
0000 0000b
U0SMR4
U0SMR3
U0SMR2
U0SMR
U0MR
U0BRG
U0TB
00h
00h
00h
00h
00h
XXh
XXXXh
U0C0
U0C1
U0RB
0000 1000b
0000 0010b
XXXXh
CRCD
XXXXh
CRCIN
XXh
R32C/161 Group
Table 4.14
4. Special Function Registers (SFRs)
SFR List (14)
Address
Register
000380h A/D0 Register 0
000381h
000382h A/D0 Register 1
000383h
000384h A/D0 Register 2
000385h
000386h A/D0 Register 3
000387h
000388h A/D0 Register 4
000389h
00038Ah A/D0 Register 5
00038Bh
00038Ch A/D0 Register 6
00038Dh
00038Eh A/D0 Register 7
00038Fh
000390h
000391h
000392h
000393h A/D0 Control Register 5
000394h A/D0 Control Register 2
000395h A/D0 Control Register 3
000396h A/D0 Control Register 0
000397h A/D0 Control Register 1
000398h
000399h
00039Ah
00039Bh
00039Ch
00039Dh
00039Eh
00039Fh
0003A0h
0003A1h
0003A2h
0003A3h
0003A4h
0003A5h
0003A6h
0003A7h
0003A8h
0003A9h
0003AAh
0003ABh
0003ACh
0003ADh
0003AEh
0003AFh
X: Undefined
Blanks are reserved. No access is allowed.
REJ03B0241-0101 Rev.1.01 Dec 07, 2009
Page 30 of 105
AD00
Symbol
Reset Value
00XXh
AD01
00XXh
AD02
00XXh
AD03
00XXh
AD04
00XXh
AD05
00XXh
AD06
00XXh
AD07
00XXh
AD0CON5
AD0CON2
AD0CON3
AD0CON0
AD0CON1
00h
X00X X000b
XXXX X000b
00h
00h
R32C/161 Group
Table 4.15
4. Special Function Registers (SFRs)
SFR List (15)
Address
Register
0003B0h
0003B1h
0003B2h
0003B3h
0003B4h
0003B5h
0003B6h
0003B7h
0003B8h
0003B9h
0003BAh
0003BBh
0003BCh
0003BDh
0003BEh
0003BFh
0003C0h Port P0 Register
0003C1h Port P1 Register
0003C2h Port P0 Direction Register
0003C3h Port P1 Direction Register
0003C4h Port P2 Register
0003C5h Port P3 Register
0003C6h Port P2 Direction Register
0003C7h Port P3 Direction Register
0003C8h Port P4 Register
0003C9h Port P5 Register
0003CAh Port P4 Direction Register
0003CBh Port P5 Direction Register
0003CCh Port P6 Register
0003CDh Port P7 Register
0003CEh Port P6 Direction Register
0003CFh Port P7 Direction Register
0003D0h Port P8 Register
0003D1h Port P9 Register
0003D2h Port P8 Direction Register
0003D3h Port P9 Direction Register
0003D4h
0003D5h
0003D6h
0003D7h
0003D8h
0003D9h
0003DAh
0003DBh
0003DCh
0003DDh
0003DEh
0003DFh
X: Undefined
Blanks are reserved. No access is allowed.
REJ03B0241-0101 Rev.1.01 Dec 07, 2009
Page 31 of 105
Symbol
P0
P1
PD0
PD1
P2
P3
PD2
PD3
P4
P5
PD4
PD5
P6
P7
PD6
PD7
P8
P9
PD8
PD9
Reset Value
XXh
XXh
0000 0000b
0000 0000b
XXh
XXh
0000 0000b
0000 0000b
XXh
XXh
0000 0000b
0000 0000b
XXh
XXh
0000 0000b
0000 0000b
XXh
XXh
00X0 0000b
0000 0000b
R32C/161 Group
Table 4.16
4. Special Function Registers (SFRs)
SFR List (16)
Address
Register
0003E0h
0003E1h
0003E2h
0003E3h
0003E4h
0003E5h
0003E6h
0003E7h
0003E8h
0003E9h
0003EAh
0003EBh
0003ECh
0003EDh
0003EEh
0003EFh
0003F0h Pull-up Control Register 0
0003F1h Pull-up Control Register 1
0003F2h Pull-up Control Register 2
0003F3h
0003F4h
0003F5h
0003F6h
0003F7h
0003F8h
0003F9h
0003FAh
0003FBh
0003FCh
0003FDh
0003FEh
0003FFh Port Control Register
X: Undefined
Blanks are reserved. No access is allowed.
REJ03B0241-0101 Rev.1.01 Dec 07, 2009
Page 32 of 105
Symbol
Reset Value
PUR0
PUR1
PUR2
0000 0000b
XXXX 0000b
0000 0000b
PCR
XXXX XXX0b
R32C/161 Group
Table 4.17
4. Special Function Registers (SFRs)
SFR List (17)
Address
Register
040000h Flash Memory Control Register 0
040001h Flash Memory Status Register 0
040002h
040003h
040004h
040005h
040006h
040007h
040008h Flash Register Protection Unlock Register 0
040009h Flash Memory Control Register 1
04000Ah Block Protect Bit Monitor Register 0
04000Bh Block Protect Bit Monitor Register 1
04000Ch
04000Dh
04000Eh
04000Fh
040010h
040011h
040012h
040013h
040014h
040015h
040016h
040017h
040018h
040019h
04001Ah
04001Bh
04001Ch
04001Dh
04001Eh
04001Fh
040020h PLL Control Register 0
040021h PLL Control Register 1
040022h
040023h
040024h PLL Status Register
040025h
040026h
040027h
040028h
040029h
04002Ah
04002Bh
04002Ch
04002Dh
04002Eh
04002Fh
X: Undefined
Blanks are reserved. No access is allowed.
Note:
1. The status of protect bit of each block in flash memory is reflected.
REJ03B0241-0101 Rev.1.01 Dec 07, 2009
Page 33 of 105
Symbol
FMR0
FMSR0
Reset Value
0X01 XX00b
1000 0000b
FPR0
FMR1
FBPM0
FBPM1
00h
0000 0010b
X?X? ????b (1)
XXX? ?XXXb (1)
PLC0
PLC1
0000 0001b
0001 1111b
PLS
1XXX XX00b
R32C/161 Group
Table 4.18
4. Special Function Registers (SFRs)
SFR List (18)
Address
Register
040030h to
04003Fh
040040h
040041h
040042h
040043h
040044h Processor Mode Register 0
040045h
040046h System Clock Control Register 0
040047h System Clock Control Register 1
040048h Processor Mode Register 3
040049h
04004Ah Protect Register
04004Bh
04004Ch Protect Register 3
04004Dh Oscillator Stop Detection Register
04004Eh
04004Fh
040050h
040051h
040052h
040053h Processor Mode Register 2
040054h
040055h
040056h
040057h
040058h
040059h
04005Ah Low Speed Mode Clock Control Register
04005Bh
04005Ch
04005Dh
04005Eh
04005Fh
040060h Voltage Regulator Control Register
040061h
040062h Low Voltage Detector Control Register
040063h
040064h Detection Voltage Configuration Register
040065h
040066h
040067h
040068h to
040093h
X: Undefined
Blanks are reserved. No access is allowed.
REJ03B0241-0101 Rev.1.01 Dec 07, 2009
Page 34 of 105
Symbol
Reset Value
PM0
1000 0000b
CM0
CM1
PM3
0000 1000b
0010 0000b
00h
PRCR
XXXX X000b
PRCR3
CM2
0000 0000b
00h
PM2
00h
CM3
XXXX XX00b
VRCR
0000 0000b
LVDC
0000 XX00b
DVCR
0000 XXXXb
R32C/161 Group
Table 4.19
4. Special Function Registers (SFRs)
SFR List (19)
Address
Register
040094h
040095h
040096h
040097h Three-phase Output Buffer Control Register
040098h Input Function Select Register 0
040099h Input Function Select Register 1
04009Ah Input Function Select Register 2
04009Bh
04009Ch
04009Dh Input Function Select Register 5
04009Eh Input Function Select Register 6
04009Fh
0400A0h Port P0_0 Function Select Register
0400A1h Port P1_0 Function Select Register
0400A2h Port P0_1 Function Select Register
0400A3h Port P1_1 Function Select Register
0400A4h Port P0_2 Function Select Register
0400A5h Port P1_2 Function Select Register
0400A6h Port P0_3 Function Select Register
0400A7h Port P1_3 Function Select Register
0400A8h Port P0_4 Function Select Register
0400A9h Port P1_4 Function Select Register
0400AAh Port P0_5 Function Select Register
0400ABh Port P1_5 Function Select Register
0400ACh Port P0_6 Function Select Register
0400ADh Port P1_6 Function Select Register
0400AEh Port P0_7 Function Select Register
0400AFh Port P1_7 Function Select Register
0400B0h Port P2_0 Function Select Register
0400B1h Port P3_0 Function Select Register
0400B2h Port P2_1 Function Select Register
0400B3h Port P3_1 Function Select Register
0400B4h Port P2_2 Function Select Register
0400B5h Port P3_2 Function Select Register
0400B6h Port P2_3 Function Select Register
0400B7h Port P3_3 Function Select Register
0400B8h Port P2_4 Function Select Register
0400B9h Port P3_4 Function Select Register
0400BAh Port P2_5 Function Select Register
0400BBh Port P3_5 Function Select Register
0400BCh Port P2_6 Function Select Register
0400BDh Port P3_6 Function Select Register
0400BEh Port P2_7 Function Select Register
0400BFh Port P3_7 Function Select Register
X: Undefined
Blanks are reserved. No access is allowed.
REJ03B0241-0101 Rev.1.01 Dec 07, 2009
Page 35 of 105
Symbol
Reset Value
IOBC
IFS0
IFS1
IFS2
0XXX XX0Xb
X000 X000b
XXXX X0X0b
0000 0000b
IFS5
IFS6
XXX0 X0X0b
XXXX 0000b
P0_0S
P1_0S
P0_1S
P1_1S
P0_2S
P1_2S
P0_3S
P1_3S
P0_4S
P1_4S
P0_5S
P1_5S
P0_6S
P1_6S
P0_7S
P1_7S
P2_0S
P3_0S
P2_1S
P3_1S
P2_2S
P3_2S
P2_3S
P3_3S
P2_4S
P3_4S
P2_5S
P3_5S
P2_6S
P3_6S
P2_7S
P3_7S
0XXX X000b
0XXX X000b
0XXX X000b
0XXX X000b
0XXX X000b
0XXX X000b
0XXX X000b
0XXX X000b
0XXX X000b
0XXX X000b
0XXX X000b
XXXX X000b
0XXX X000b
XXXX X000b
0XXX X000b
XXXX X000b
0XXX X000b
XXXX X000b
0XXX X000b
XXXX X000b
0XXX X000b
XXXX X000b
0XXX X000b
XXXX X000b
0XXX X000b
XXXX X000b
0XXX X000b
XXXX X000b
0XXX X000b
XXXX X000b
0XXX X000b
XXXX X000b
R32C/161 Group
Table 4.20
4. Special Function Registers (SFRs)
SFR List (20)
Address
Register
0400C0h Port P4_0 Function Select Register
0400C1h Port P5_0 Function Select Register
0400C2h Port P4_1 Function Select Register
0400C3h Port P5_1 Function Select Register
0400C4h Port P4_2 Function Select Register
0400C5h Port P5_2 Function Select Register
0400C6h Port P4_3 Function Select Register
0400C7h Port P5_3 Function Select Register
0400C8h Port P4_4 Function Select Register
0400C9h Port P5_4 Function Select Register
0400CAh Port P4_5 Function Select Register
0400CBh Port P5_5 Function Select Register
0400CCh Port P4_6 Function Select Register
0400CDh Port P5_6 Function Select Register
0400CEh Port P4_7 Function Select Register
0400CFh Port P5_7 Function Select Register
0400D0h
0400D1h Port P7_0 Function Select Register
0400D2h
0400D3h
0400D4h
0400D5h
0400D6h
0400D7h
0400D8h
0400D9h Port P7_4 Function Select Register
0400DAh Port P6_5 Function Select Register
0400DBh Port P7_5 Function Select Register
0400DCh
0400DDh Port P7_6 Function Select Register
0400DEh Port P6_7 Function Select Register
0400DFh
0400E0h
0400E1h
0400E2h
0400E3h
0400E4h Port P8_2 Function Select Register
0400E5h
0400E6h Port P8_3 Function Select Register
0400E7h Port P9_3 Function Select Register
0400E8h Port P8_4 Function Select Register
0400E9h Port P9_4 Function Select Register
0400EAh
0400EBh Port P9_5 Function Select Register
0400ECh Port P8_6 Function Select Register
0400EDh Port P9_6 Function Select Register
0400EEh Port P8_7 Function Select Register
0400EFh Port P9_7 Function Select Register
X: Undefined
Blanks are reserved. No access is allowed.
REJ03B0241-0101 Rev.1.01 Dec 07, 2009
Page 36 of 105
Symbol
P4_0S
P5_0S
P4_1S
P5_1S
P4_2S
P5_2S
P4_3S
P5_3S
P4_4S
P5_4S
P4_5S
P5_5S
P4_6S
P5_6S
P4_7S
P5_7S
Reset Value
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
P7_0S
XXXX X000b
P7_4S
P6_5S
P7_5S
XXXX X000b
XXXX X000b
XXXX X000b
P7_6S
P6_7S
XXXX X000b
XXXX X000b
P8_2S
XXXX X000b
P8_3S
P9_3S
P8_4S
P9_4S
XXXX X000b
0XXX X000b
XXXX X000b
0XXX X000b
P9_5S
P8_6S
P9_6S
P8_7S
P9_7S
0XXX X000b
XXXX X000b
0XXX X000b
XXXX X000b
XXXX X000b
R32C/161 Group
Table 4.21
4. Special Function Registers (SFRs)
SFR List (21)
Address
Register
0400F0h to
04403Fh
044040h
044041h
044042h
044043h
044044h
044045h
044046h
044047h
044048h
044049h
04404Ah
04404Bh
04404Ch Protect Register 4
04404Dh Watchdog Timer Clock Control Register
04404Eh Watchdog Timer Start Register
04404Fh Watchdog Timer Control Register
044050h
044051h
044052h
044053h
044054h
044055h
044056h
044057h
044058h
044059h
04405Ah
04405Bh
04405Ch
04405Dh
04405Eh
04405Fh Protect Register 2
X: Undefined
Blanks are reserved. No access is allowed.
REJ03B0241-0101 Rev.1.01 Dec 07, 2009
Page 37 of 105
Symbol
Reset Value
PRCR4
WDK
WDTS
WDC
0000 0000b
0000 0000b
XXXX XXXXb
000X XXXXb
PRCR2
0XXX XXXXb
R32C/161 Group
Table 4.22
4. Special Function Registers (SFRs)
SFR List (22)
Address
Register
044060h
044061h
044062h
044063h
044064h
044065h
044066h
044067h
044068h
044069h
04406Ah
04406Bh
04406Ch
04406Dh
04406Eh
04406Fh External Interrupt Source Select Register 0
044070h DMA0 Request Source Select Register 2
044071h DMA1 Request Source Select Register 2
044072h DMA2 Request Source Select Register 2
044073h DMA3 Request Source Select Register 2
044074h
044075h
044076h
044077h
044078h DMA0 Request Source Select Register
044079h DMA1 Request Source Select Register
04407Ah DMA2 Request Source Select Register
04407Bh DMA3 Request Source Select Register
04407Ch
04407Dh Wake-up IPL Setting Register 2
04407Eh
04407Fh Wake-up IPL Setting Register 1
044080h External Interrupt Input Filter Select Register 0
044081h
044082h External Interrupt Input Filter Select Register 1
044083h
044084h
044085h
044086h
044087h
044088h
044089h
04408Ah
04408Bh
04408Ch
04408Dh
04408Eh
04408Fh
X: Undefined
Blanks are reserved. No access is allowed.
REJ03B0241-0101 Rev.1.01 Dec 07, 2009
Page 38 of 105
Symbol
Reset Value
IFSR0
DM0SL2
DM1SL2
DM2SL2
DM3SL2
0000 0000b
XX00 0000b
XX00 0000b
XX00 0000b
XX00 0000b
DM0SL
DM1SL
DM2SL
DM3SL
XXX0 0000b
XXX0 0000b
XXX0 0000b
XXX0 0000b
RIPL2
XX0X 0000b
RIPL1
INTF0
XX0X 0000b
0000 0000b
INTF1
0000 0000b
R32C/161 Group
Table 4.23
4. Special Function Registers (SFRs)
SFR List (23)
Address
Register
044090h to
044DFFh
044E00h LIN Channel Window Select/Input Signal Low Detection Status
Register
044E01h LIN Baud Rate Generator Control Register
044E02h LIN Baud Rate Prescaler 0
044E03h LIN Baud Rate Prescaler 1
044E04h LIN Mode Register 0
044E05h LIN Mode Register 1
044E06h LIN Wake-up Setting Register
044E07h
044E08h LIN Break Field Setting Register
044E09h LIN Space Setting Register
044E0Ah LIN Response Field Setting Register
044E0Bh LIN ID Buffer Register
044E0Ch LIN Status Control Register
044E0Dh LIN Transmission Control Register
044E0Eh LIN Status Register
044E0Fh LIN Error Status Register
044E10h LIN Data 1 Buffer Register
044E11h LIN Data 2 Buffer Register
044E12h LIN Data 3 Buffer Register
044E13h LIN Data 4 Buffer Register
044E14h LIN Data 5 Buffer Register
044E15h LIN Data 6 Buffer Register
044E16h LIN Data 7 Buffer Register
044E17h LIN Data 8 Buffer Register
044E18h
044E19h
044E1Ah
044E1Bh
044E1Ch
044E1Dh
044E1Eh
044E1Fh
X: Undefined
Blanks are reserved. No access is allowed.
REJ03B0241-0101 Rev.1.01 Dec 07, 2009
Page 39 of 105
Symbol
Reset Value
LCW
0000 0000b
LBRG
LBRP0
LBRP1
LMD0
LMD1
LWUP
0000 0000b
00h
00h
0000 0000b
00h
00h
LBRK
LSPC
LRFC
LIDB
LSC
LTC
LST
LEST
LDB1
LDB2
LDB3
LDB4
LDB5
LDB6
LDB7
LDB8
0000 0000b
0000 0000b
0000 0000b
00h
0000 0000b
0000 0000b
0000 0000b
0000 0000b
00h
00h
00h
00h
00h
00h
00h
00h
R32C/161 Group
Table 4.24
4. Special Function Registers (SFRs)
SFR List (24)
Address
Register
044E20h to
044EFFh
044F00h
044F01h
044F02h
044F03h
044F04h
044F05h
044F06h SS0 Receive Data Register
044F07h SS0 Receive Data Register (H)
044F08h SS0 Control Register H
044F09h SS0 Control Register L
044F0Ah SS0 Mode Register
044F0Bh SS0 Enable Register
044F0Ch SS0 Status Register
044F0Dh SS0 Mode Register 2
044F0Eh SS0 Transmit Data Register
044F0Fh SS0 Transmit Data Register (H)
044F10h
044F11h
044F12h
044F13h
044F14h
044F15h
044F16h
044F17h
044F18h
044F19h
044F1Ah
044F1Bh
044F1Ch
044F1Dh
044F1Eh
044F1Fh
044F20h
044F21h
044F22h
044F23h
044F24h
044F25h
044F26h
044F27h
X: Undefined
Blanks are reserved. No access is allowed.
REJ03B0241-0101 Rev.1.01 Dec 07, 2009
Page 40 of 105
Symbol
SS0RDR
SS0RDR (H)
SS0CRH
SS0CRL
SS0MR
SS0ER
SS0SR
SS0MR2
SS0TDR
SS0TDR (H)
Reset Value
FFh
FFh
00h
0111 1101b
0001 0000b
00h
00h
00h
FFh
FFh
R32C/161 Group
Table 4.25
4. Special Function Registers (SFRs)
SFR List (25)
Address
Register
044F28h to
044FDFh
044FE0h E2dataFlash Address Register
044FE1h
044FE2h
044FE3h
044FE4h
044FE5h
044FE6h
044FE7h
044FE8h E2dataFlash Instruction Register
044FE9h
044FEAh
044FEBh
044FECh E2dataFlash Data Register
044FEDh
044FEEh
044FEFh
044FF0h E2dataFlash Mode Register
044FF1h
044FF2h E2dataFlash Control Register
044FF3h
044FF4h E2dataFlash Status Register 1
044FF5h
044FF6h
044FF7h
044FF8h
044FF9h
044FFAh
044FFBh
044FFCh
044FFDh
044FFEh
044FFFh
045000h
045001h E2dataFlash Status Register 0
045002h
045003h
045004h
045005h
045006h
045007h
045008h to
045FFFh
046000h to
0467FFh
X: Undefined
Blanks are reserved. No access is allowed.
REJ03B0241-0101 Rev.1.01 Dec 07, 2009
Page 41 of 105
Symbol
Reset Value
E2FA
XXXX 0000h
E2FI
XX00h
E2FD
XXXXh
E2FM
0000 0000b
E2FC
XXXX XXX0b
E2FS1
XXXX XXX0b
E2FS0
XXXX XXXXb
R32C/161 Group
Table 4.26
4. Special Function Registers (SFRs)
SFR List (26)
Address
Register
046800h to
0477FFh
047800h CAN1 Mailbox 0: Message Identifier
047801h
047802h
047803h
047804h
047805h CAN1 Mailbox 0: Data Length
047806h CAN1 Mailbox 0: Data Field
047807h
047808h
047809h
04780Ah
04780Bh
04780Ch
04780Dh
04780Eh CAN1 Mailbox 0: Time Stamp
04780Fh
047810h CAN1 Mailbox 1: Message Identifier
047811h
047812h
047813h
047814h
047815h CAN1 Mailbox 1: Data Length
047816h CAN1 Mailbox 1: Data Field
047817h
047818h
047819h
04781Ah
04781Bh
04781Ch
04781Dh
04781Eh CAN1 Mailbox 1: Time Stamp
04781Fh
047820h CAN1 Mailbox 2: Message Identifier
047821h
047822h
047823h
047824h
047825h CAN1 Mailbox 2: Data Length
047826h CAN1 Mailbox 2: Data Field
047827h
047828h
047829h
04782Ah
04782Bh
04782Ch
04782Dh
04782Eh CAN1 Mailbox 2: Time Stamp
04782Fh
X: Undefined
Blanks are reserved. No access is allowed.
REJ03B0241-0101 Rev.1.01 Dec 07, 2009
Page 42 of 105
Symbol
C1MB0
Reset Value
XXXX XXXXh
XXh
XXXX XXXX
XXXX XXXXh
XXXXh
C1MB1
XXXX XXXXh
XXh
XXXX XXXX
XXXX XXXXh
XXXXh
C1MB2
XXXX XXXXh
XXh
XXXX XXXX
XXXX XXXXh
XXXXh
R32C/161 Group
Table 4.27
4. Special Function Registers (SFRs)
SFR List (27)
Address
Register
047830h CAN1 Mailbox 3: Message Identifier
047831h
047832h
047833h
047834h
047835h CAN1 Mailbox 3: Data Length
047836h CAN1 Mailbox 3: Data Field
047837h
047838h
047839h
04783Ah
04783Bh
04783Ch
04783Dh
04783Eh CAN1 Mailbox 3: Time Stamp
04783Fh
047840h CAN1 Mailbox 4: Message Identifier
047841h
047842h
047843h
047844h
047845h CAN1 Mailbox 4: Data Length
047846h CAN1 Mailbox 4: Data Field
047847h
047848h
047849h
04784Ah
04784Bh
04784Ch
04784Dh
04784Eh CAN1 Mailbox 4: Time Stamp
04784Fh
047850h CAN1 Mailbox 5: Message Identifier
047851h
047852h
047853h
047854h
047855h CAN1 Mailbox 5: Data Length
047856h CAN1 Mailbox 5: Data Field
047857h
047858h
047859h
04785Ah
04785Bh
04785Ch
04785Dh
04785Eh CAN1 Mailbox 5: Time Stamp
04785Fh
X: Undefined
Blanks are reserved. No access is allowed.
REJ03B0241-0101 Rev.1.01 Dec 07, 2009
Page 43 of 105
Symbol
C1MB3
Reset Value
XXXX XXXXh
XXh
XXXX XXXX
XXXX XXXXh
XXXXh
C1MB4
XXXX XXXXh
XXh
XXXX XXXX
XXXX XXXXh
XXXXh
C1MB5
XXXX XXXXh
XXh
XXXX XXXX
XXXX XXXXh
XXXXh
R32C/161 Group
Table 4.28
4. Special Function Registers (SFRs)
SFR List (28)
Address
Register
047860h CAN1 Mailbox 6: Message Identifier
047861h
047862h
047863h
047864h
047865h CAN1 Mailbox 6: Data Length
047866h CAN1 Mailbox 6: Data Field
047867h
047868h
047869h
04786Ah
04786Bh
04786Ch
04786Dh
04786Eh CAN1 Mailbox 6: Time Stamp
04786Fh
047870h CAN1 Mailbox 7: Message Identifier
047871h
047872h
047873h
047874h
047875h CAN1 Mailbox 7: Data Length
047876h CAN1 Mailbox 7: Data Field
047877h
047878h
047879h
04787Ah
04787Bh
04787Ch
04787Dh
04787Eh CAN1 Mailbox 7: Time Stamp
04787Fh
047880h CAN1 Mailbox 8: Message Identifier
047881h
047882h
047883h
047884h
047885h CAN1 Mailbox 8: Data Length
047886h CAN1 Mailbox 8: Data Field
047887h
047888h
047889h
04788Ah
04788Bh
04788Ch
04788Dh
04788Eh CAN1 Mailbox 8: Time Stamp
04788Fh
X: Undefined
Blanks are reserved. No access is allowed.
REJ03B0241-0101 Rev.1.01 Dec 07, 2009
Page 44 of 105
Symbol
C1MB6
Reset Value
XXXX XXXXh
XXh
XXXX XXXX
XXXX XXXXh
XXXXh
C1MB7
XXXX XXXXh
XXh
XXXX XXXX
XXXX XXXXh
XXXXh
C1MB8
XXXX XXXXh
XXh
XXXX XXXX
XXXX XXXXh
XXXXh
R32C/161 Group
Table 4.29
4. Special Function Registers (SFRs)
SFR List (29)
Address
Register
047890h CAN1 Mailbox 9: Message Identifier
047891h
047892h
047893h
047894h
047895h CAN1 Mailbox 9: Data Length
047896h CAN1 Mailbox 9: Data Field
047897h
047898h
047899h
04789Ah
04789Bh
04789Ch
04789Dh
04789Eh CAN1 Mailbox 9: Time Stamp
04789Fh
0478A0h CAN1 Mailbox 10: Message Identifier
0478A1h
0478A2h
0478A3h
0478A4h
0478A5h CAN1 Mailbox 10: Data Length
0478A6h CAN1 Mailbox 10: Data Field
0478A7h
0478A8h
0478A9h
0478AAh
0478ABh
0478ACh
0478ADh
0478AEh CAN1 Mailbox 10: Time Stamp
0478AFh
0478B0h CAN1 Mailbox 11: Message Identifier
0478B1h
0478B2h
0478B3h
0478B4h
0478B5h CAN1 Mailbox 11: Data Length
0478B6h CAN1 Mailbox 11: Data Field
0478B7h
0478B8h
0478B9h
0478BAh
0478BBh
0478BCh
0478BDh
0478BEh CAN1 Mailbox 11: Time Stamp
0478BFh
X: Undefined
Blanks are reserved. No access is allowed.
REJ03B0241-0101 Rev.1.01 Dec 07, 2009
Page 45 of 105
Symbol
C1MB9
Reset Value
XXXX XXXXh
XXh
XXXX XXXX
XXXX XXXXh
XXXXh
C1MB10
XXXX XXXXh
XXh
XXXX XXXX
XXXX XXXXh
XXXXh
C1MB11
XXXX XXXXh
XXh
XXXX XXXX
XXXX XXXXh
XXXXh
R32C/161 Group
Table 4.30
4. Special Function Registers (SFRs)
SFR List (30)
Address
Register
0478C0h CAN1 Mailbox 12: Message Identifier
0478C1h
0478C2h
0478C3h
0478C4h
0478C5h CAN1 Mailbox 12: Data Length
0478C6h CAN1 Mailbox 12: Data Field
0478C7h
0478C8h
0478C9h
0478CAh
0478CBh
0478CCh
0478CDh
0478CEh CAN1 Mailbox 12: Time Stamp
0478CFh
0478D0h CAN1 Mailbox 13: Message Identifier
0478D1h
0478D2h
0478D3h
0478D4h
0478D5h CAN1 Mailbox 13: Data Length
0478D6h CAN1 Mailbox 13: Data Field
0478D7h
0478D8h
0478D9h
0478DAh
0478DBh
0478DCh
0478DDh
0478DEh CAN1 Mailbox 13: Time Stamp
0478DFh
0478E0h CAN1 Mailbox 14: Message Identifier
0478E1h
0478E2h
0478E3h
0478E4h
0478E5h CAN1 Mailbox 14: Data Length
0478E6h CAN1 Mailbox 14: Data Field
0478E7h
0478E8h
0478E9h
0478EAh
0478EBh
0478ECh
0478EDh
0478EEh CAN1 Mailbox 14: Time Stamp
0478EFh
X: Undefined
Blanks are reserved. No access is allowed.
REJ03B0241-0101 Rev.1.01 Dec 07, 2009
Page 46 of 105
Symbol
C1MB12
Reset Value
XXXX XXXXh
XXh
XXXX XXXX
XXXX XXXXh
XXXXh
C1MB13
XXXX XXXXh
XXh
XXXX XXXX
XXXX XXXXh
XXXXh
C1MB14
XXXX XXXXh
XXh
XXXX XXXX
XXXX XXXXh
XXXXh
R32C/161 Group
Table 4.31
4. Special Function Registers (SFRs)
SFR List (31)
Address
Register
0478F0h CAN1 Mailbox 15: Message Identifier
0478F1h
0478F2h
0478F3h
0478F4h
0478F5h CAN1 Mailbox 15: Data Length
0478F6h CAN1 Mailbox 15: Data Field
0478F7h
0478F8h
0478F9h
0478FAh
0478FBh
0478FCh
0478FDh
0478FEh CAN1 Mailbox 15: Time Stamp
0478FFh
047900h CAN1 Mailbox 16: Message Identifier
047901h
047902h
047903h
047904h
047905h CAN1 Mailbox 16: Data Length
047906h CAN1 Mailbox 16: Data Field
047907h
047908h
047909h
04790Ah
04790Bh
04790Ch
04790Dh
04790Eh CAN1 Mailbox 16: Time Stamp
04790Fh
047910h CAN1 Mailbox 17: Message Identifier
047911h
047912h
047913h
047914h
047915h CAN1 Mailbox 17: Data Length
047916h CAN1 Mailbox 17: Data Field
047917h
047918h
047919h
04791Ah
04791Bh
04791Ch
04791Dh
04791Eh CAN1 Mailbox 17: Time Stamp
04791Fh
X: Undefined
Blanks are reserved. No access is allowed.
REJ03B0241-0101 Rev.1.01 Dec 07, 2009
Page 47 of 105
Symbol
C1MB15
Reset Value
XXXX XXXXh
XXh
XXXX XXXX
XXXX XXXXh
XXXXh
C1MB16
XXXX XXXXh
XXh
XXXX XXXX
XXXX XXXXh
XXXXh
C1MB17
XXXX XXXXh
XXh
XXXX XXXX
XXXX XXXXh
XXXXh
R32C/161 Group
Table 4.32
4. Special Function Registers (SFRs)
SFR List (32)
Address
Register
047920h CAN1 Mailbox 18: Message Identifier
047921h
047922h
047923h
047924h
047925h CAN1 Mailbox 18: Data Length
047926h CAN1 Mailbox 18: Data Field
047927h
047928h
047929h
04792Ah
04792Bh
04792Ch
04792Dh
04792Eh CAN1 Mailbox18: Time Stamp
04792Fh
047930h CAN1 Mailbox 19: Message Identifier
047931h
047932h
047933h
047934h
047935h CAN1 Mailbox 19: Data Length
047936h CAN1 Mailbox 19: Data Field
047937h
047938h
047939h
04793Ah
04793Bh
04793Ch
04793Dh
04793Eh CAN1 Mailbox 19: Time Stamp
04793Fh
047940h CAN1 Mailbox 20: Message Identifier
047941h
047942h
047943h
047944h
047945h CAN1 Mailbox 20: Data Length
047946h CAN1 Mailbox 20: Data Field
047947h
047948h
047949h
04794Ah
04794Bh
04794Ch
04794Dh
04794Eh CAN1 Mailbox 20: Time Stamp
04794Fh
X: Undefined
Blanks are reserved. No access is allowed.
REJ03B0241-0101 Rev.1.01 Dec 07, 2009
Page 48 of 105
Symbol
C1MB18
Reset Value
XXXX XXXXh
XXh
XXXX XXXX
XXXX XXXXh
XXXXh
C1MB19
XXXX XXXXh
XXh
XXXX XXXX
XXXX XXXXh
XXXXh
C1MB20
XXXX XXXXh
XXh
XXXX XXXX
XXXX XXXXh
XXXXh
R32C/161 Group
Table 4.33
4. Special Function Registers (SFRs)
SFR List (33)
Address
Register
047950h CAN1 Mailbox 21: Message Identifier
047951h
047952h
047953h
047954h
047955h CAN1 Mailbox 21: Data Length
047956h CAN1 Mailbox 21: Data Field
047957h
047958h
047959h
04795Ah
04795Bh
04795Ch
04795Dh
04795Eh CAN1 Mailbox 21: Time Stamp
04795Fh
047960h CAN1 Mailbox 22: Identifier
047961h
047962h
047963h
047964h
047965h CAN1 Mailbox 22: Data Length
047966h CAN1 Mailbox 22: Data Field
047967h
047968h
047969h
04796Ah
04796Bh
04796Ch
04796Dh
04796Eh CAN1 Mailbox 22: Time Stamp
04796Fh
047970h CAN1 Mailbox 23: Message Identifier
047971h
047972h
047973h
047974h
047975h CAN1 Mailbox 23: Data Length
047976h CAN1 Mailbox 23: Data Field
047977h
047978h
047979h
04797Ah
04797Bh
04797Ch
04797Dh
04797Eh CAN1 Mailbox 23: Time Stamp
04797Fh
X: Undefined
Blanks are reserved. No access is allowed.
REJ03B0241-0101 Rev.1.01 Dec 07, 2009
Page 49 of 105
Symbol
C1MB21
Reset Value
XXXX XXXXh
XXh
XXXX XXXX
XXXX XXXXh
XXXXh
C1MB22
XXXX XXXXh
XXh
XXXX XXXX
XXXX XXXXh
XXXXh
C1MB23
XXXX XXXXh
XXh
XXXX XXXX
XXXX XXXXh
XXXXh
R32C/161 Group
Table 4.34
4. Special Function Registers (SFRs)
SFR List (34)
Address
Register
047980h CAN1 Mailbox 24: Message Identifier
047981h
047982h
047983h
047984h
047985h CAN1 Mailbox 24: Data Length
047986h CAN1 Mailbox 24: Data Field
047987h
047988h
047989h
04798Ah
04798Bh
04798Ch
04798Dh
04798Eh CAN1 Mailbox 24: Time Stamp
04798Fh
047990h CAN1 Mailbox 25: Message Identifier
047991h
047992h
047993h
047994h
047995h CAN1 Mailbox 25: Data Length
047996h CAN1 Mailbox 25: Data Field
047997h
047998h
047999h
04799Ah
04799Bh
04799Ch
04799Dh
04799Eh CAN1 Mailbox 25: Time Stamp
04799Fh
0479A0h CAN1 Mailbox 26: Message Identifier
0479A1h
0479A2h
0479A3h
0479A4h
0479A5h CAN1 Mailbox 26: Data Length
0479A6h CAN1 Mailbox 26: Data Field
0479A7h
0479A8h
0479A9h
0479AAh
0479ABh
0479ACh
0479ADh
0479AEh CAN1 Mailbox 26: Time Stamp
0479AFh
X: Undefined
Blanks are reserved. No access is allowed.
REJ03B0241-0101 Rev.1.01 Dec 07, 2009
Page 50 of 105
Symbol
C1MB24
Reset Value
XXXX XXXXh
XXh
XXXX XXXX
XXXX XXXXh
XXXXh
C1MB25
XXXX XXXXh
XXh
XXXX XXXX
XXXX XXXXh
XXXXh
C1MB26
XXXX XXXXh
XXh
XXXX XXXX
XXXX XXXXh
XXXXh
R32C/161 Group
Table 4.35
4. Special Function Registers (SFRs)
SFR List (35)
Address
Register
0479B0h CAN1 Mailbox 27: Message Identifier
0479B1h
0479B2h
0479B3h
0479B4h
0479B5h CAN1 Mailbox 27: Data Length
0479B6h CAN1 Mailbox 27: Data Field
0479B7h
0479B8h
0479B9h
0479BAh
0479BBh
0479BCh
0479BDh
0479BEh CAN1 Mailbox 27: Time Stamp
0479BFh
0479C0h CAN1 Mailbox 28: Message Identifier
0479C1h
0479C2h
0479C3h
0479C4h
0479C5h CAN1 Mailbox 28: Data Length
0479C6h CAN1 Mailbox 28: Data Field
0479C7h
0479C8h
0479C9h
0479CAh
0479CBh
0479CCh
0479CDh
0479CEh CAN1 Mailbox 28: Time Stamp
0479CFh
0479D0h CAN1 Mailbox 29: Message Identifier
0479D1h
0479D2h
0479D3h
0479D4h
0479D5h CAN1 Mailbox 29: Data Length
0479D6h CAN1 Mailbox 29: Data Field
0479D7h
0479D8h
0479D9h
0479DAh
0479DBh
0479DCh
0479DDh
0479DEh CAN1 Mailbox 29: Time Stamp
0479DFh
X: Undefined
Blanks are reserved. No access is allowed.
REJ03B0241-0101 Rev.1.01 Dec 07, 2009
Page 51 of 105
Symbol
C1MB27
Reset Value
XXXX XXXXh
XXh
XXXX XXXX
XXXX XXXXh
XXXXh
C1MB28
XXXX XXXXh
XXh
XXXX XXXX
XXXX XXXXh
XXXXh
C1MB29
XXXX XXXXh
XXh
XXXX XXXX
XXXX XXXXh
XXXXh
R32C/161 Group
Table 4.36
4. Special Function Registers (SFRs)
SFR List (36)
Address
Register
0479E0h CAN1 Mailbox 30: Message Identifier
0479E1h
0479E2h
0479E3h
0479E4h
0479E5h CAN1 Mailbox 30: Data Length
0479E6h CAN1 Mailbox 30: Data Field
0479E7h
0479E8h
0479E9h
0479EAh
0479EBh
0479ECh
0479EDh
0479EEh CAN1 Mailbox 30: Time Stamp
0479EFh
0479F0h CAN1 Mailbox 31: Message Identifier
0479F1h
0479F2h
0479F3h
0479F4h
0479F5h CAN1 Mailbox 31: Data Length
0479F6h CAN1 Mailbox 31: Data Field
0479F7h
0479F8h
0479F9h
0479FAh
0479FBh
0479FCh
0479FDh
0479FEh CAN1 Mailbox 31: Time Stamp
0479FFh
047A00h CAN1 Acceptance Mask Register 0
047A01h
047A02h
047A03h
047A04h CAN1 Acceptance Mask Register 1
047A05h
047A06h
047A07h
047A08h CAN1 Acceptance Mask Register 2
047A09h
047A0Ah
047A0Bh
047A0Ch CAN1 Acceptance Mask Register 3
047A0Dh
047A0Eh
047A0Fh
X: Undefined
Blanks are reserved. No access is allowed.
REJ03B0241-0101 Rev.1.01 Dec 07, 2009
Page 52 of 105
Symbol
C1MB30
Reset Value
XXXX XXXXh
XXh
XXXX XXXX
XXXX XXXXh
XXXXh
C1MB31
XXXX XXXXh
XXh
XXXX XXXX
XXXX XXXXh
XXXXh
C1MKR0
XXXX XXXXh
C1MKR1
XXXX XXXXh
C1MKR2
XXXX XXXXh
C1MKR3
XXXX XXXXh
R32C/161 Group
Table 4.37
4. Special Function Registers (SFRs)
SFR List (37)
Address
Register
047A10h CAN1 Acceptance Mask Register 4
047A11h
047A12h
047A13h
047A14h CAN1 Acceptance Mask Register 5
047A15h
047A16h
047A17h
047A18h CAN1 Acceptance Mask Register 6
047A19h
047A1Ah
047A1Bh
047A1Ch CAN1 Acceptance Mask Register 7
047A1Dh
047A1Eh
047A1Fh
047A20h CAN1 FIFO Received ID Compare Register 0
047A21h
047A22h
047A23h
047A24h CAN1 FIFO Received ID Compare Register 1
047A25h
047A26h
047A27h
047A28h CAN1 Mask Invalid Register
047A29h
047A2Ah
047A2Bh
047A2Ch CAN1 Mailbox Interrupt Enable Register
047A2Dh
047A2Eh
047A2Fh
047A30h
047A31h
047A32h
047A33h
047A34h
047A35h
047A36h
047A37h
047A38h
047A39h
047A3Ah
047A3Bh
047A3Ch
047A3Dh
047A3Eh
047A3Fh
047A40h to
047B1Fh
X: Undefined
Blanks are reserved. No access is allowed.
REJ03B0241-0101 Rev.1.01 Dec 07, 2009
Page 53 of 105
Symbol
C1MKR4
Reset Value
XXXX XXXXh
C1MKR5
XXXX XXXXh
C1MKR6
XXXX XXXXh
C1MKR7
XXXX XXXXh
C1FIDCR0
XXXX XXXXh
C1FIDCR1
XXXX XXXXh
C1MKIVLR
XXXX XXXXh
C1MIER
XXXX XXXXh
R32C/161 Group
Table 4.38
4. Special Function Registers (SFRs)
SFR List (38)
Address
Register
047B20h CAN1 Message Control Register 0
047B21h CAN1 Message Control Register 1
047B22h CAN1 Message Control Register 2
047B23h CAN1 Message Control Register 3
047B24h CAN1 Message Control Register 4
047B25h CAN1 Message Control Register 5
047B26h CAN1 Message Control Register 6
047B27h CAN1 Message Control Register 7
047B28h CAN1 Message Control Register 8
047B29h CAN1 Message Control Register 9
047B2Ah CAN1 Message Control Register 10
047B2Bh CAN1 Message Control Register 11
047B2Ch CAN1 Message Control Register 12
047B2Dh CAN1 Message Control Register 13
047B2Eh CAN1 Message Control Register 14
047B2Fh CAN1 Message Control Register 15
047B30h CAN1 Message Control Register 16
047B31h CAN1 Message Control Register 17
047B32h CAN1 Message Control Register 18
047B33h CAN1 Message Control Register 19
047B34h CAN1 Message Control Register 20
047B35h CAN1 Message Control Register 21
047B36h CAN1 Message Control Register 22
047B37h CAN1 Message Control Register 23
047B38h CAN1 Message Control Register 24
047B39h CAN1 Message Control Register 25
047B3Ah CAN1 Message Control Register 26
047B3Bh CAN1 Message Control Register 27
047B3Ch CAN1 Message Control Register 28
047B3Dh CAN1 Message Control Register 29
047B3Eh CAN1 Message Control Register 30
047B3Fh CAN1 Message Control Register 31
X: Undefined
Blanks are reserved. No access is allowed.
REJ03B0241-0101 Rev.1.01 Dec 07, 2009
Page 54 of 105
Symbol
C1MCTL0
C1MCTL1
C1MCTL2
C1MCTL3
C1MCTL4
C1MCTL5
C1MCTL6
C1MCTL7
C1MCTL8
C1MCTL9
C1MCTL10
C1MCTL11
C1MCTL12
C1MCTL13
C1MCTL14
C1MCTL15
C1MCTL16
C1MCTL17
C1MCTL18
C1MCTL19
C1MCTL20
C1MCTL21
C1MCTL22
C1MCTL23
C1MCTL24
C1MCTL25
C1MCTL26
C1MCTL27
C1MCTL28
C1MCTL29
C1MCTL30
C1MCTL31
Reset Value
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
R32C/161 Group
Table 4.39
4. Special Function Registers (SFRs)
SFR List (39)
Address
Register
047B40h CAN1 Control Register
047B41h
047B42h CAN1 Status Register
047B43h
047B44h CAN1 Bit Configuration Register
047B45h
047B46h
047B47h CAN1 Clock Select Register
047B48h CAN1 Receive FIFO Control Register
047B49h CAN1 Receive FIFO Pointer Control Register
047B4Ah CAN1 Transmit FIFO Control Register
047B4Bh CAN1 Transmit FIFO Pointer Control Register
047B4Ch CAN1 Error Interrupt Enable Register
047B4Dh CAN1 Error Interrupt Factor Judge Register
047B4Eh CAN1 Reception Error Count Register
047B4Fh CAN1 Transmission Error Count Register
047B50h CAN1 Error Code Store Register
047B51h CAN1 Channel Search Support Register
047B52h CAN1 Mailbox Search Status Register
047B53h CAN1 Mailbox Search Mode Register
047B54h CAN1 Time Stamp Register
047B55h
047B56h CAN1 Acceptance Filter Support Register
047B57h
047B58h CAN1 Test Control Register
047B59h
047B5Ah
047B5Bh
047B5Ch
047B5Dh
047B5Eh
047B5Fh
047B60h to
047BFFh
X: Undefined
Blanks are reserved. No access is allowed.
REJ03B0241-0101 Rev.1.01 Dec 07, 2009
Page 55 of 105
Symbol
C1CTLR
C1BCR
Reset Value
0000 0101b
0000 0000b
0000 0101b
0000 0000b
00 0000h
C1CLKR
C1RFCR
C1RFPCR
C1TFCR
C1TFPCR
C1EIER
C1EIFR
C1RECR
C1TECR
C1ECSR
C1CSSR
C1MSSR
C1MSMR
C1TSR
000X 0000b
1000 0000b
XXh
1000 0000b
XXh
00h
00h
00h
00h
00h
XXh
1000 0000b
XXXX XX00b
0000h
C1AFSR
XXXXh
C1TCR
00h
C1STR
R32C/161 Group
Table 4.40
4. Special Function Registers (SFRs)
SFR List (40)
Address
Register
047C00h CAN0 Mailbox 0: Message Identifier
047C01h
047C02h
047C03h
047C04h
047C05h CAN0 Mailbox 0: Data Length
047C06h CAN0 Mailbox 0: Data Field
047C07h
047C08h
047C09h
047C0Ah
047C0Bh
047C0Ch
047C0Dh
047C0Eh CAN0 Mailbox 0: Time Stamp
047C0Fh
047C10h CAN0 Mailbox 1: Message Identifier
047C11h
047C12h
047C13h
047C14h
047C15h CAN0 Mailbox 1: Data Length
047C16h CAN0 Mailbox 1: Data Field
047C17h
047C18h
047C19h
047C1Ah
047C1Bh
047C1Ch
047C1Dh
047C1Eh CAN0 Mailbox 1: Time Stamp
047C1Fh
047C20h CAN0 Mailbox 2: Message Identifier
047C21h
047C22h
047C23h
047C24h
047C25h CAN0 Mailbox 2: Data Length
047C26h CAN0 Mailbox 2: Data Field
047C27h
047C28h
047C29h
047C2Ah
047C2Bh
047C2Ch
047C2Dh
047C2Eh CAN0 Mailbox 2: Time Stamp
047C2Fh
X: Undefined
Blanks are reserved. No access is allowed.
REJ03B0241-0101 Rev.1.01 Dec 07, 2009
Page 56 of 105
Symbol
C0MB0
Reset Value
XXXX XXXXh
XXh
XXXX XXXX
XXXX XXXXh
XXXXh
C0MB1
XXXX XXXXh
XXh
XXXX XXXX
XXXX XXXXh
XXXXh
C0MB2
XXXX XXXXh
XXh
XXXX XXXX
XXXX XXXXh
XXXXh
R32C/161 Group
Table 4.41
4. Special Function Registers (SFRs)
SFR List (41)
Address
Register
047C30h CAN0 Mailbox 3: Message Identifier
047C31h
047C32h
047C33h
047C34h
047C35h CAN0 Mailbox 3: Data Length
047C36h CAN0 Mailbox 3: Data Field
047C37h
047C38h
047C39h
047C3Ah
047C3Bh
047C3Ch
047C3Dh
047C3Eh CAN0 Mailbox 3: Time Stamp
047C3Fh
047C40h CAN0 Mailbox 4: Message Identifier
047C41h
047C42h
047C43h
047C44h
047C45h CAN0 Mailbox 4: Data Length
047C46h CAN0 Mailbox 4: Data Field
047C47h
047C48h
047C49h
047C4Ah
047C4Bh
047C4Ch
047C4Dh
047C4Eh CAN0 Mailbox 4: Time Stamp
047C4Fh
047C50h CAN0 Mailbox 5: Message Identifier
047C51h
047C52h
047C53h
047C54h
047C55h CAN0 Mailbox 5: Data Length
047C56h CAN0 Mailbox 5: Data Field
047C57h
047C58h
047C59h
047C5Ah
047C5Bh
047C5Ch
047C5Dh
047C5Eh CAN0 Mailbox 5: Time Stamp
047C5Fh
X: Undefined
Blanks are reserved. No access is allowed.
REJ03B0241-0101 Rev.1.01 Dec 07, 2009
Page 57 of 105
Symbol
C0MB3
Reset Value
XXXX XXXXh
XXh
XXXX XXXX
XXXX XXXXh
XXXXh
C0MB4
XXXX XXXXh
XXh
XXXX XXXX
XXXX XXXXh
XXXXh
C0MB5
XXXX XXXXh
XXh
XXXX XXXX
XXXX XXXXh
XXXXh
R32C/161 Group
Table 4.42
4. Special Function Registers (SFRs)
SFR List (42)
Address
Register
047C60h CAN0 Mailbox 6: Message Identifier
047C61h
047C62h
047C63h
047C64h
047C65h CAN0 Mailbox 6: Data Length
047C66h CAN0 Mailbox 6: Data Field
047C67h
047C68h
047C69h
047C6Ah
047C6Bh
047C6Ch
047C6Dh
047C6Eh CAN0 Mailbox 6: Time Stamp
047C6Fh
047C70h CAN0 Mailbox 7: Message Identifier
047C71h
047C72h
047C73h
047C74h
047C75h CAN0 Mailbox 7: Data Length
047C76h CAN0 Mailbox 7: Data Field
047C77h
047C78h
047C79h
047C7Ah
047C7Bh
047C7Ch
047C7Dh
047C7Eh CAN0 Mailbox 7: Time Stamp
047C7Fh
047C80h CAN0 Mailbox 8: Message Identifier
047C81h
047C82h
047C83h
047C84h
047C85h CAN0 Mailbox 8: Data Length
047C86h CAN0 Mailbox 8: Data Field
047C87h
047C88h
047C89h
047C8Ah
047C8Bh
047C8Ch
047C8Dh
047C8Eh CAN0 Mailbox 8: Time Stamp
047C8Fh
X: Undefined
Blanks are reserved. No access is allowed.
REJ03B0241-0101 Rev.1.01 Dec 07, 2009
Page 58 of 105
Symbol
C0MB6
Reset Value
XXXX XXXXh
XXh
XXXX XXXX
XXXX XXXXh
XXXXh
C0MB7
XXXX XXXXh
XXh
XXXX XXXX
XXXX XXXXh
XXXXh
C0MB8
XXXX XXXXh
XXh
XXXX XXXX
XXXX XXXXh
XXXXh
R32C/161 Group
Table 4.43
4. Special Function Registers (SFRs)
SFR List (43)
Address
Register
047C90h CAN0 Mailbox 9: Message Identifier
047C91h
047C92h
047C93h
047C94h
047C95h CAN0 Mailbox 9: Data Length
047C96h CAN0 Mailbox 9: Data Field
047C97h
047C98h
047C99h
047C9Ah
047C9Bh
047C9Ch
047C9Dh
047C9Eh CAN0 Mailbox 9: Time Stamp
047C9Fh
047CA0h CAN0 Mailbox 10: Message Identifier
047CA1h
047CA2h
047CA3h
047CA4h
047CA5h CAN0 Mailbox 10: Data Length
047CA6h CAN0 Mailbox 10: Data Field
047CA7h
047CA8h
047CA9h
047CAAh
047CABh
047CACh
047CADh
047CAEh CAN0 Mailbox 10: Time Stamp
047CAFh
047CB0h CAN0 Mailbox 11: Message Identifier
047CB1h
047CB2h
047CB3h
047CB4h
047CB5h CAN0 Mailbox 11: Data Length
047CB6h CAN0 Mailbox 11: Data Field
047CB7h
047CB8h
047CB9h
047CBAh
047CBBh
047CBCh
047CBDh
047CBEh CAN0 Mailbox 11: Time Stamp
047CBFh
X: Undefined
Blanks are reserved. No access is allowed.
REJ03B0241-0101 Rev.1.01 Dec 07, 2009
Page 59 of 105
Symbol
C0MB9
Reset Value
XXXX XXXXh
XXh
XXXX XXXX
XXXX XXXXh
XXXXh
C0MB10
XXXX XXXXh
XXh
XXXX XXXX
XXXX XXXXh
XXXXh
C0MB11
XXXX XXXXh
XXh
XXXX XXXX
XXXX XXXXh
XXXXh
R32C/161 Group
Table 4.44
4. Special Function Registers (SFRs)
SFR List (44)
Address
Register
047CC0h CAN0 Mailbox 12: Message Identifier
047CC1h
047CC2h
047CC3h
047CC4h
047CC5h CAN0 Mailbox 12: Data Length
047CC6h CAN0 Mailbox 12: Data Field
047CC7h
047CC8h
047CC9h
047CCAh
047CCBh
047CCCh
047CCDh
047CCEh CAN0 Mailbox 12: Time Stamp
047CCFh
047CD0h CAN0 Mailbox 13: Message Identifier
047CD1h
047CD2h
047CD3h
047CD4h
047CD5h CAN0 Mailbox 13: Data Length
047CD6h CAN0 Mailbox 13: Data Field
047CD7h
047CD8h
047CD9h
047CDAh
047CDBh
047CDCh
047CDDh
047CDEh CAN0 Mailbox 13: Time Stamp
047CDFh
047CE0h CAN0 Mailbox 14: Message Identifier
047CE1h
047CE2h
047CE3h
047CE4h
047CE5h CAN0 Mailbox 14: Data Length
047CE6h CAN0 Mailbox 14: Data Field
047CE7h
047CE8h
047CE9h
047CEAh
047CEBh
047CECh
047CEDh
047CEEh CAN0 Mailbox 14: Time Stamp
047CEFh
X: Undefined
Blanks are reserved. No access is allowed.
REJ03B0241-0101 Rev.1.01 Dec 07, 2009
Page 60 of 105
Symbol
C0MB12
Reset Value
XXXX XXXXh
XXh
XXXX XXXX
XXXX XXXXh
XXXXh
C0MB13
XXXX XXXXh
XXh
XXXX XXXX
XXXX XXXXh
XXXXh
C0MB14
XXXX XXXXh
XXh
XXXX XXXX
XXXX XXXXh
XXXXh
R32C/161 Group
Table 4.45
4. Special Function Registers (SFRs)
SFR List (45)
Address
Register
047CF0h CAN0 Mailbox 15: Message Identifier
047CF1h
047CF2h
047CF3h
047CF4h
047CF5h CAN0 Mailbox 15: Data Length
047CF6h CAN0 Mailbox 15: Data Field
047CF7h
047CF8h
047CF9h
047CFAh
047CFBh
047CFCh
047CFDh
047CFEh CAN0 Mailbox 15: Time Stamp
047CFFh
047D00h CAN0 Mailbox 16: Message Identifier
047D01h
047D02h
047D03h
047D04h
047D05h CAN0 Mailbox 16: Data Length
047D06h CAN0 Mailbox 16: Data Field
047D07h
047D08h
047D09h
047D0Ah
047D0Bh
047D0Ch
047D0Dh
047D0Eh CAN0 Mailbox 16: Time Stamp
047D0Fh
047D10h CAN0 Mailbox 17: Message Identifier
047D11h
047D12h
047D13h
047D14h
047D15h CAN0 Mailbox 17: Data Length
047D16h CAN0 Mailbox 17: Data Field
047D17h
047D18h
047D19h
047D1Ah
047D1Bh
047D1Ch
047D1Dh
047D1Eh CAN0 Mailbox 17: Time Stamp
047D1Fh
X: Undefined
Blanks are reserved. No access is allowed.
REJ03B0241-0101 Rev.1.01 Dec 07, 2009
Page 61 of 105
Symbol
C0MB15
Reset Value
XXXX XXXXh
XXh
XXXX XXXX
XXXX XXXXh
XXXXh
C0MB16
XXXX XXXXh
XXh
XXXX XXXX
XXXX XXXXh
XXXXh
C0MB17
XXXX XXXXh
XXh
XXXX XXXX
XXXX XXXXh
XXXXh
R32C/161 Group
Table 4.46
4. Special Function Registers (SFRs)
SFR List (46)
Address
Register
047D20h CAN0 Mailbox 18: Message Identifier
047D21h
047D22h
047D23h
047D24h
047D25h CAN0 Mailbox 18: Data Length
047D26h CAN0 Mailbox 18: Data Field
047D27h
047D28h
047D29h
047D2Ah
047D2Bh
047D2Ch
047D2Dh
047D2Eh CAN0 Mailbox 18: Time Stamp
047D2Fh
047D30h CAN0 Mailbox 19: Message Identifier
047D31h
047D32h
047D33h
047D34h
047D35h CAN0 Mailbox 19: Data Length
047D36h CAN0 Mailbox 19: Data Field
047D37h
047D38h
047D39h
047D3Ah
047D3Bh
047D3Ch
047D3Dh
047D3Eh CAN0 Mailbox 19: Time Stamp
047D3Fh
047D40h CAN0 Mailbox 20: Message Identifier
047D41h
047D42h
047D43h
047D44h
047D45h CAN0 Mailbox 20: Data Length
047D46h CAN0 Mailbox 20: Data Field
047D47h
047D48h
047D49h
047D4Ah
047D4Bh
047D4Ch
047D4Dh
047D4Eh CAN0 Mailbox 20: Time Stamp
047D4Fh
X: Undefined
Blanks are reserved. No access is allowed.
REJ03B0241-0101 Rev.1.01 Dec 07, 2009
Page 62 of 105
Symbol
C0MB18
Reset Value
XXXX XXXXh
XXh
XXXX XXXX
XXXX XXXXh
XXXXh
C0MB19
XXXX XXXXh
XXh
XXXX XXXX
XXXX XXXXh
XXXXh
C0MB20
XXXX XXXXh
XXh
XXXX XXXX
XXXX XXXXh
XXXXh
R32C/161 Group
Table 4.47
4. Special Function Registers (SFRs)
SFR List (47)
Address
Register
047D50h CAN0 Mailbox 21: Message Identifier
047D51h
047D52h
047D53h
047D54h
047D55h CAN0 Mailbox 21: Data Length
047D56h CAN0 Mailbox 21: Data Field
047D57h
047D58h
047D59h
047D5Ah
047D5Bh
047D5Ch
047D5Dh
047D5Eh CAN0 Mailbox 21: Time Stamp
047D5Fh
047D60h CAN0 Mailbox 22: Message Identifier
047D61h
047D62h
047D63h
047D64h
047D65h CAN0 Mailbox 22: Data Length
047D66h CAN0 Mailbox 22: Data Field
047D67h
047D68h
047D69h
047D6Ah
047D6Bh
047D6Ch
047D6Dh
047D6Eh CAN0 Mailbox 22: Time Stamp
047D6Fh
047D70h CAN0 Mailbox 23: Message Identifier
047D71h
047D72h
047D73h
047D74h
047D75h CAN0 Mailbox 23: Data Length
047D76h CAN0 Mailbox 23: Data Field
047D77h
047D78h
047D79h
047D7Ah
047D7Bh
047D7Ch
047D7Dh
047D7Eh CAN0 Mailbox 23: Time Stamp
047D7Fh
X: Undefined
Blanks are reserved. No access is allowed.
REJ03B0241-0101 Rev.1.01 Dec 07, 2009
Page 63 of 105
Symbol
C0MB21
Reset Value
XXXX XXXXh
XXh
XXXX XXXX
XXXX XXXXh
XXXXh
C0MB22
XXXX XXXXh
XXh
XXXX XXXX
XXXX XXXXh
XXXXh
C0MB23
XXXX XXXXh
XXh
XXXX XXXX
XXXX XXXXh
XXXXh
R32C/161 Group
Table 4.48
4. Special Function Registers (SFRs)
SFR List (48)
Address
Register
047D80h CAN0 Mailbox 24: Message Identifier
047D81h
047D82h
047D83h
047D84h
047D85h CAN0 Mailbox 24: Data Length
047D86h CAN0 Mailbox 24: Data Field
047D87h
047D88h
047D89h
047D8Ah
047D8Bh
047D8Ch
047D8Dh
047D8Eh CAN0 Mailbox 24: Time Stamp
047D8Fh
047D90h CAN0 Mailbox 25: Message Identifier
047D91h
047D92h
047D93h
047D94h
047D95h CAN0 Mailbox 25: Data Length
047D96h CAN0 Mailbox 25: Data Field
047D97h
047D98h
047D99h
047D9Ah
047D9Bh
047D9Ch
047D9Dh
047D9Eh CAN0 Mailbox 25: Time Stamp
047D9Fh
047DA0h CAN0 Mailbox 26: Message Identifier
047DA1h
047DA2h
047DA3h
047DA4h
047DA5h CAN0 Mailbox 26: Data Length
047DA6h CAN0 Mailbox 26: Data Field
047DA7h
047DA8h
047DA9h
047DAAh
047DABh
047DACh
047DADh
047DAEh CAN0 Mailbox 26: Time Stamp
047DAFh
X: Undefined
Blanks are reserved. No access is allowed.
REJ03B0241-0101 Rev.1.01 Dec 07, 2009
Page 64 of 105
Symbol
C0MB24
Reset Value
XXXX XXXXh
XXh
XXXX XXXX
XXXX XXXXh
XXXXh
C0MB25
XXXX XXXXh
XXh
XXXX XXXX
XXXX XXXXh
XXXXh
C0MB26
XXXX XXXXh
XXh
XXXX XXXX
XXXX XXXXh
XXXXh
R32C/161 Group
Table 4.49
4. Special Function Registers (SFRs)
SFR List (49)
Address
Register
047DB0h CAN0 Mailbox 27: Message Identifier
047DB1h
047DB2h
047DB3h
047DB4h
047DB5h CAN0 Mailbox 27: Data Length
047DB6h CAN0 Mailbox 27: Data Field
047DB7h
047DB8h
047DB9h
047DBAh
047DBBh
047DBCh
047DBDh
047DBEh CAN0 Mailbox 27: Time Stamp
047DBFh
047DC0h CAN0 Mailbox 28: Message Identifier
047DC1h
047DC2h
047DC3h
047DC4h
047DC5h CAN0 Mailbox 28: Data Length
047DC6h CAN0 Mailbox 28: Data Field
047DC7h
047DC8h
047DC9h
047DCAh
047DCBh
047DCCh
047DCDh
047DCEh CAN0 Mailbox 28: Time Stamp
047DCFh
047DD0h CAN0 Mailbox 29: Message Identifier
047DD1h
047DD2h
047DD3h
047DD4h
047DD5h CAN0 Mailbox 29: Data Length
047DD6h CAN0 Mailbox 29: Data Field
047DD7h
047DD8h
047DD9h
047DDAh
047DDBh
047DDCh
047DDDh
047DDEh CAN0 Mailbox 29: Time Stamp
047DDFh
X: Undefined
Blanks are reserved. No access is allowed.
REJ03B0241-0101 Rev.1.01 Dec 07, 2009
Page 65 of 105
Symbol
C0MB27
Reset Value
XXXX XXXXh
XXh
XXXX XXXX
XXXX XXXXh
XXXXh
C0MB28
XXXX XXXXh
XXh
XXXX XXXX
XXXX XXXXh
XXXXh
C0MB29
XXXX XXXXh
XXh
XXXX XXXX
XXXX XXXXh
XXXXh
R32C/161 Group
Table 4.50
4. Special Function Registers (SFRs)
SFR List (50)
Address
Register
047DE0h CAN0 Mailbox 30: Message Identifier
047DE1h
047DE2h
047DE3h
047DE4h
047DE5h CAN0 Mailbox 30: Data Length
047DE6h CAN0 Mailbox 30: Data Field
047DE7h
047DE8h
047DE9h
047DEAh
047DEBh
047DECh
047DEDh
047DEEh CAN0 Mailbox 30: Time Stamp
047DEFh
047DF0h CAN0 Mailbox 31: Message Identifier
047DF1h
047DF2h
047DF3h
047DF4h
047DF5h CAN0 Mailbox 31: Data Length
047DF6h CAN0 Mailbox 31: Data Field
047DF7h
047DF8h
047DF9h
047DFAh
047DFBh
047DFCh
047DFDh
047DFEh CAN0 Mailbox 31: Time Stamp
047DFFh
047E00h CAN0 Acceptance Mask Register 0
047E01h
047E02h
047E03h
047E04h CAN0 Acceptance Mask Register 1
047E05h
047E06h
047E07h
047E08h CAN0 Acceptance Mask Register 2
047E09h
047E0Ah
047E0Bh
047E0Ch CAN0 Acceptance Mask Register 3
047E0Dh
047E0Eh
047E0Fh
X: Undefined
Blanks are reserved. No access is allowed.
REJ03B0241-0101 Rev.1.01 Dec 07, 2009
Page 66 of 105
Symbol
C0MB30
Reset Value
XXXX XXXXh
XXh
XXXX XXXX
XXXX XXXXh
XXXXh
C0MB31
XXXX XXXXh
XXh
XXXX XXXX
XXXX XXXXh
XXXXh
C0MKR0
XXXX XXXXh
C0MKR1
XXXX XXXXh
C0MKR2
XXXX XXXXh
C0MKR3
XXXX XXXXh
R32C/161 Group
Table 4.51
4. Special Function Registers (SFRs)
SFR List (51)
Address
Register
047E10h CAN0 Acceptance Mask Register 4
047E11h
047E12h
047E13h
047E14h CAN0 Acceptance Mask Register 5
047E15h
047E16h
047E17h
047E18h CAN0 Acceptance Mask Register 6
047E19h
047E1Ah
047E1Bh
047E1Ch CAN0 Acceptance Mask Register 7
047E1Dh
047E1Eh
047E1Fh
047E20h CAN0 FIFO Receive ID Compare Register 0
047E21h
047E22h
047E23h
047E24h CAN0 FIFO Receive ID Compare Register 1
047E25h
047E26h
047E27h
047E28h CAN0 Mask Invalid Register
047E29h
047E2Ah
047E2Bh
047E2Ch CAN0 Mailbox Interrupt Enable Register
047E2Dh
047E2Eh
047E2Fh
047E30h
047E31h
047E32h
047E33h
047E34h
047E35h
047E36h
047E37h
047E38h
047E39h
047E3Ah
047E3Bh
047E3Ch
047E3Dh
047E3Eh
047E3Fh
047E40h to
047F1Fh
X: Undefined
Blanks are reserved. No access is allowed.
REJ03B0241-0101 Rev.1.01 Dec 07, 2009
Page 67 of 105
Symbol
C0MKR4
Reset Value
XXXX XXXXh
C0MKR5
XXXX XXXXh
C0MKR6
XXXX XXXXh
C0MKR7
XXXX XXXXh
C0FIDCR0
XXXX XXXXh
C0FIDCR1
XXXX XXXXh
C0MKIVLR
XXXX XXXXh
C0MIER
XXXX XXXXh
R32C/161 Group
Table 4.52
4. Special Function Registers (SFRs)
SFR List (52)
Address
Register
047F20h CAN0 Message Control Register 0
047F21h CAN0 Message Control Register 1
047F22h CAN0 Message Control Register 2
047F23h CAN0 Message Control Register 3
047F24h CAN0 Message Control Register 4
047F25h CAN0 Message Control Register 5
047F26h CAN0 Message Control Register 6
047F27h CAN0 Message Control Register 7
047F28h CAN0 Message Control Register 8
047F29h CAN0 Message Control Register 9
047F2Ah CAN0 Message Control Register 10
047F2Bh CAN0 Message Control Register 11
047F2Ch CAN0 Message Control Register 12
047F2Dh CAN0 Message Control Register 13
047F2Eh CAN0 Message Control Register 14
047F2Fh CAN0 Message Control Register 15
047F30h CAN0 Message Control Register 16
047F31h CAN0 Message Control Register 17
047F32h CAN0 Message Control Register 18
047F33h CAN0 Message Control Register 19
047F34h CAN0 Message Control Register 20
047F35h CAN0 Message Control Register 21
047F36h CAN0 Message Control Register 22
047F37h CAN0 Message Control Register 23
047F38h CAN0 Message Control Register 24
047F39h CAN0 Message Control Register 25
047F3Ah CAN0 Message Control Register 26
047F3Bh CAN0 Message Control Register 27
047F3Ch CAN0 Message Control Register 28
047F3Dh CAN0 Message Control Register 29
047F3Eh CAN0 Message Control Register 30
047F3Fh CAN0 Message Control Register 31
X: Undefined
Blanks are reserved. No access is allowed.
REJ03B0241-0101 Rev.1.01 Dec 07, 2009
Page 68 of 105
Symbol
C0MCTL0
C0MCTL1
C0MCTL2
C0MCTL3
C0MCTL4
C0MCTL5
C0MCTL6
C0MCTL7
C0MCTL8
C0MCTL9
C0MCTL10
C0MCTL11
C0MCTL12
C0MCTL13
C0MCTL14
C0MCTL15
C0MCTL16
C0MCTL17
C0MCTL18
C0MCTL19
C0MCTL20
C0MCTL21
C0MCTL22
C0MCTL23
C0MCTL24
C0MCTL25
C0MCTL26
C0MCTL27
C0MCTL28
C0MCTL29
C0MCTL30
C0MCTL31
Reset Value
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
R32C/161 Group
Table 4.53
4. Special Function Registers (SFRs)
SFR List (53)
Address
Register
047F40h CAN0 Control Register
047F41h
047F42h CAN0 Status Register
047F43h
047F44h CAN0 Bit Configuration Register
047F45h
047F46h
047F47h CAN0 Clock Select Register
047F48h CAN0 Receive FIFO Control Register
047F49h CAN0 Receive FIFO Pointer Control Register
047F4Ah CAN0 Transmit FIFO Control Register
047F4Bh CAN0 Transmit FIFO Pointer Control Register
047F4Ch CAN0 Error Interrupt Enable Register
047F4Dh CAN0 Error Interrupt Factor Judge Register
047F4Eh CAN0 Reception Error Count Register
047F4Fh CAN0 Transmission Error Count Register
047F50h CAN0 Error Code Store Register
047F51h CAN0 Channel Search Support Register
047F52h CAN0 Mailbox Search Status Register
047F53h CAN0 Mailbox Search Mode Register
047F54h CAN0 Time Stamp Register
047F55h
047F56h CAN0 Acceptance Filter Support Register
047F57h
047F58h CAN0 Test Control Register
047F59h
047F5Ah
047F5Bh
047F5Ch
047F5Dh
047F5Eh
047F5Fh
047F60h to
047FFFh
048000h to
04FFFFh
X: Undefined
Blanks are reserved. No access is allowed.
REJ03B0241-0101 Rev.1.01 Dec 07, 2009
Page 69 of 105
Symbol
C0CTLR
C0BCR
Reset Value
0000 0101b
0000 0000b
0000 0101b
0000 0000b
00 0000h
C0CLKR
C0RFCR
C0RFPCR
C0TFCR
C0TFPCR
C0EIER
C0EIFR
C0RECR
C0TECR
C0ECSR
C0CSSR
C0MSSR
C0MSMR
C0TSR
000X 0000b
1000 0000b
XXh
1000 0000b
XXh
00h
00h
00h
00h
00h
XXh
1000 0000b
XXXX XX00b
0000h
C0AFSR
XXXXh
C0TCR
00h
C0STR
R32C/161 Group
5.
5. Electrical Characteristics
Electrical Characteristics
Table 5.1
Absolute Maximum Ratings (1)
Symbol
Characteristic
Condition
Value
Unit
VCC
Supply voltage
VCC = AVCC
-0.3 to 6.0
V
AVCC
Analog supply voltage
VCC = AVCC
-0.3 to 6.0
V
VI
Input voltage
XIN, RESET, CNVSS, NSD, VREF,
P0_0 to P0_7, P1_0 to P1_7,
P2_0 to P2_7, P3_0 to P3_7,
P4_0 to P4_7, P5_0 to P5_7, P6_5,
P6_7, P7_0, P7_4 to P7_6,
P8_2 to P8_7, P9_1, P9_3 to P9_7
-0.3 to VCC + 0.3
V
XOUT, P0_0 to P0_7, P1_0 to P1_7,
P2_0 to P2_7, P3_0 to P3_7,
P4_0 to P4_7, P5_0 to P5_7, P6_5,
P6_7, P7_0, P7_4 to P7_6,
P8_2 to P8_4, P8_6, P8_7,
P9_3 to P9_7
-0.3 to VCC + 0.3
V
500
mW
Operating temperature range
-40 to 125
°C
Storage temperature range
-65 to 150
°C
VO
Output
voltage
Pd
Power consumption
—
Tstg
Ta = 25°C
Note:
1. Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to
the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
REJ03B0241-0101 Rev.1.01 Dec 07, 2009
Page 70 of 105
R32C/161 Group
Table 5.2
5. Electrical Characteristics
Operating Conditions (1/6) (1)
Symbol
Characteristic
Value
Min.
Typ.
Max.
3.0
5.0
5.5
Unit
VCC
Digital supply voltage
AVCC
Analog supply voltage
VREF
Reference voltage
VSS
Digital ground voltage
0
V
AVSS
Analog ground voltage
0
V
dVCC/dt VCC ramp up rate (VCC < 2.0 V)
VIH
VIL
Topr
VCC
V
VCC
3.0
V
0.05
V
V/ms
High level
input
voltage
XIN, RESET, CNVSS, NSD
0.8 × VCC
VCC
V
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_5, P6_7, P7_0, P7_4 to P7_6,
P8_2 to P8_7 (2), P9_1, P9_3 to P9_7
0.7 × VCC
VCC
V
Low level
input
voltage
XIN, RESET, CNVSS, NSD
0
0.2 × VCC
V
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_5, P6_7, P7_0, P7_4 to P7_6,
P8_2 to P8_7 (2), P9_1, P9_3 to P9_7
0
0.3 × VCC
V
Operating Version J
temperature
range
-40
85
°C
Version L
-40
105
°C
Version K
-40
125
°C
Notes:
1. The device is operationally guaranteed under these operating conditions.
2. VIH and VIL for P8_7 are specified for P8_7 as a programmable port. These values are not applicable
to P8_7 as XCIN.
REJ03B0241-0101 Rev.1.01 Dec 07, 2009
Page 71 of 105
R32C/161 Group
Table 5.3
Symbol
CVDC
5. Electrical Characteristics
Operating Conditions (2/6)
(VCC = 3.0 to 5.5 V, VSS = 0 V, and Ta = Topr, unless otherwise noted) (1)
Value (2)
Characteristic
Decoupling capacitance for voltage
regulator
Min. Typ. Max.
Inter-pin voltage: 1.5 V
2.4
10.0
Unit
µF
Notes:
1. The device is operationally guaranteed under these operating conditions.
2. This value should be satisfied with due consideration of every condition as follows: operating
temperature, DC bias, aging, etc.
REJ03B0241-0101 Rev.1.01 Dec 07, 2009
Page 72 of 105
R32C/161 Group
Table 5.4
5. Electrical Characteristics
Operating Conditions (3/6)
(VCC = 3.0 to 5.5 V, VSS = 0 V, and Ta = Topr, unless otherwise noted) (1)
Symbol
Characteristic
Value
Min.
Typ.
Max.
Unit
IOH(peak) High level
peak
output
current (2)
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_5,
P6_7, P7_0, P7_4 to P7_6, P8_2 to P8_4, P8_6,
P8_7, P9_3 to P9_7
-10.0
mA
IOH(avg)
High level
average
output
current (3)
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_5,
P6_7, P7_0, P7_4 to P7_6, P8_2 to P8_4, P8_6,
P8_7, P9_3 to P9_7
-5.0
mA
IOL(peak) Low level
peak
output
current (2)
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_5,
P6_7, P7_0, P7_4 to P7_6, P8_2 to P8_4, P8_6,
P8_7, P9_3 to P9_7
10.0
mA
IOL(avg)
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_5,
P6_7, P7_0, P7_4 to P7_6, P8_2 to P8_4, P8_6,
P8_7, P9_3 to P9_7
5.0
mA
Low level
average
output
current (3)
Notes:
1. The device is operationally guaranteed under these operating conditions.
2. The following conditions should be satisfied:
• The sum of IOL(peak) of ports P0, P1, P2, P8_6, P8_7, and P9 is 80 mA or less.
• The sum of IOL(peak) of ports P3, P4, P5, P6, P7, and P8_2 to P8_4 is 80 mA or less.
• The sum of IOH(peak) of ports P1 and P2 is -40 mA or less.
• The sum of IOH(peak) of ports P0, P9_6, and P9_7 is -40 mA or less.
• The sum of IOH(peak) of ports P3, P4, P5, and P6 is -40 mA or less.
• The sum of IOH(peak) of ports P7, P8, and P9_3 to P9_5 is -40 mA or less.
3. Average value within 100 ms.
REJ03B0241-0101 Rev.1.01 Dec 07, 2009
Page 73 of 105
R32C/161 Group
Table 5.5
5. Electrical Characteristics
Operating Conditions (4/6)
(VCC = 3.0 to 5.5 V, VSS = 0 V, and Ta = Topr, unless otherwise noted) (1)
Symbol
Value
Characteristic
Min.
Typ.
Max.
Unit
f(XIN)
Main clock oscillator frequency
4
8
MHz
f(XRef)
Reference clock frequency
2
4
MHz
f(PLL)
PLL clock oscillator frequency
96
144
MHz
f(Base)
Base clock frequency
48
MHz
tc(Base)
Base clock cycle time
f(CPU)
CPU operating frequency
tc(CPU)
CPU clock cycle time
f(BCLK)
Peripheral bus clock operating frequency
tc(BCLK)
Peripheral bus clock cycle time
f(PER)
Peripheral clock source frequency
f(XCIN)
Sub clock oscillator frequency
20.83
48
20.83
41.67
Base clock
(Internal signal)
t c(CPU)
CPU clock
(Internal signal)
t c(BCLK)
Figure 5.1
Clock Cycle Time
REJ03B0241-0101 Rev.1.01 Dec 07, 2009
Page 74 of 105
MHz
ns
32.768
t c(Base)
MHz
ns
24
Note:
1. The device is operationally guaranteed under these operating conditions.
Peripheral bus clock
(Internal signal)
ns
24
MHz
50
kHz
R32C/161 Group
Table 5.6
5. Electrical Characteristics
Operating Conditions (5/6)
(VCC = 3.0 to 5.5 V, VSS = 0 V, and Ta = Topr, unless otherwise noted) (1, 2)
Symbol
IIC(H)
IIC(L)
Σ|IIC|
Characteristic
Value
Measurement
Unit
Condition
Min. Typ. Max.
High input
injection
current
P0_0 to P0_7, P1_0 to P1_7,
P2_0 to P2_7, P3_0 to P3_7,
P4_0 to P4_7, P5_0 to P5_7, P6_5,
P6_7, P7_0, P7_4 to P7_6,
P8_2 to P8_5, P9_3 to P9_7
VI > VCC
2
mA
Low input
injection
current
P0_0 to P0_7, P1_0 to P1_7,
P2_0 to P2_7, P3_0 to P3_7,
P4_0 to P4_7, P5_0 to P5_7, P6_5,
P6_7, P7_0, P7_4 to P7_6,
P8_2 to P8_5, P9_3 to P9_7
VI < VSS
-2
mA
20
mA
Total injection current
Notes:
1. The device is operationally guaranteed under these operating conditions.
2. These conditions are applicable when each port is designated as input.
REJ03B0241-0101 Rev.1.01 Dec 07, 2009
Page 75 of 105
R32C/161 Group
Table 5.7
5. Electrical Characteristics
Operating Conditions (6/6)
(VCC = 3.0 to 5.5 V, VSS = 0 V, and Ta = Topr, unless otherwise noted) (1)
Symbol
Vr(VCC)
Allowable ripple voltage
dVr(VCC)/dt Ripple voltage gradient
fr(VCC)
Value
Characteristic
Min.
Typ.
Max.
VCC = 5.0 V
0.5
Vp-p
VCC = 3.0 V
0.3
Vp-p
VCC = 5.0 V
±0.3
V/ms
VCC = 3.0 V
±0.3
V/ms
10
kHz
Allowable ripple frequency
Note:
1. The device is operationally guaranteed under these operating conditions.
1 / f r(VCC)
VCC
Figure 5.2
Ripple Waveform
REJ03B0241-0101 Rev.1.01 Dec 07, 2009
Page 76 of 105
Unit
V r(VCC)
R32C/161 Group
Table 5.8
5. Electrical Characteristics
Flash Memory Electrical Characteristics
(VCC = 3.0 to 5.5 V, VSS = 0 V, and Ta = Topr, unless otherwise noted)
Symbol
—
—
—
—
—
Value
Characteristic
Min.
Programming and erasure endurance of flash Program area
memory (1)
Data area
4-word program time
Lock bit-program time
Block erasure time
Data retention
(2)
Typ.
Max.
Unit
1000
times
10000
times
Program area
150
900
µs
Data area
300
1700
µs
Program area
70
500
µs
Data area
140
1000
µs
4 Kbyte block
0.12
3.0
s
32 Kbyte block
0.17
3.0
s
64 Kbyte block
0.20
3.0
s
Ta = 55°C
(3, 4)
20
years
Notes:
1. Program/erase definition
This value represents the number of erasures per block.
If the flash memory is programmed/erased n times, each block can be erased n times.
i.e. If 4-word write is performed in 512 different addresses in the block A of 4 Kbyte and then the
block is erased, it is considered the programming/erasure is performed just once.
However a write in the same address more than once for one erasure is disabled. (overwrite
disabled).
2. The data retention time includes the periods when the supply voltage is not applied and no clock is
provided.
3. This data retention includes 3000 hours in Ta = 125°C and 7000 hours in Ta = 85°C.
4.
Please contact a Renesas sales office regarding data retention time other than the above.
REJ03B0241-0101 Rev.1.01 Dec 07, 2009
Page 77 of 105
R32C/161 Group
Table 5.9
5. Electrical Characteristics
E2dataFlash Electrical Characteristics
(VCC = 3.0 to 5.5 V, VSS = 0 V, and Ta = Topr, unless otherwise noted)
Value
Symbol
Characteristic
—
Programming and erasure endurance of flash memory (1)
—
Word program time
—
Block erasure time
Min.
32 byte block
Data retention (2)
—
Unit
Max.
100000
Flash memory circuit start-up stabilization time
tPS
Typ.
Ta = 55°C (3, 4)
times
100
2000
µs
15
200
ms
35
50
µs
20
years
Notes:
1. Program/erase definition
This value represents the number of erasure per block.
If the flash memory is programmed/erased n times, each block can be erased n times.
i.e. If a word write is performed in different 16 addresses in a block and then the block is erased, it
is considered the programming/erasure is performed just once. However a write in the same
address more than once for one erasure is disabled. (overwrite disabled).
2. The data retention time includes the periods when the supply voltage is not applied and no clock is
provided.
3. This data retention includes 3000 hours in Ta = 125°C and 7000 hours in Ta = 85°C.
4.
Please contact a Renesas sales office regarding data retention time other than the above.
Table 5.10
Power Supply Circuit Timing Characteristics
(VCC = 3.0 to 5.5 V, VSS = 0 V, and Ta = Topr, unless otherwise noted)
Symbol
td(P-R)
Measurement
condition
Characteristic
Internal power supply start-up stabilization
time after the main power supply is turned on
t d(P-R)
Internal power supply start-up
stabilization time after the main
power supply is turned on
V CC
t d(P-R)
PLL oscillatoroutput waveform
Figure 5.3
Power Supply Circuit Timing
REJ03B0241-0101 Rev.1.01 Dec 07, 2009
Page 78 of 105
Min. Typ. Max.
2
Recommended
operating voltage
Supply voltage for
internal logic
Value
Unit
ms
R32C/161 Group
Table 5.11
Symbol
5. Electrical Characteristics
Electrical Characteristics of Voltage Regulator for Internal Logic
(VCC = 3.0 to 5.5 V, VSS = 0 V, and Ta = Topr, unless otherwise noted)
Measurement
condition
Characteristics
Value
Min.
Typ.
Output voltage
VVDC1
Table 5.12
Symbol
ΔVdet
Max.
1.5
V
Electrical Characteristics of Low Voltage Detector
(VCC = 4.2 to 5.5 V, VSS = 0 V, and Ta = Topr, unless otherwise noted)
Characteristics
Measurement
condition
Value
Min.
Typ.
Max.
Detected voltage error
±0.2
Vdet(R)-Vdet(F) Hysteresis width
—
td(E-A)
Table 5.13
Symbol
Unit
Self-consuming current
0
Unit
V
V
VCC = 5.0 V, low voltage
detector enabled
4
µA
Operation start time of low voltage detector
150
µs
Electrical Characteristics of Oscillator
(VCC = 3.0 to 5.5 V, VSS = 0 V, and Ta = Topr, unless otherwise noted)
Characteristics
fSO(PLL)
PLL clock self-oscillation frequency
tLOCK(PLL)
PLL lock time (1, 2)
tjitter(p-p)
PLL jitter period (p-p)
f(OCO)
On-chip oscillator frequency
Measurement
condition
Unit
Min.
Typ.
Max.
35
50
80
MHz
1
ms
2.0
ns
156
kHz
f(XRef) = 4MHz
Notes:
1. This value is applicable only when the main clock oscillation is stable.
2. This value is the time until the PLF1 bit in the PLS register becomes 1.
REJ03B0241-0101 Rev.1.01 Dec 07, 2009
Page 79 of 105
Value
94
125
R32C/161 Group
Table 5.14
Symbol
5. Electrical Characteristics
Electrical Characteristics of Clock Circuitry
(VCC = 3.0 to 5.5 V, VSS = 0 V, and Ta = Topr, unless otherwise noted)
Characteristics
Measurement
condition
Value
Min.
Typ.
Max.
Unit
trec(WAIT)
Recovery time from wait mode to low power mode
225
µs
trec(STOP)
Recovery time from stop mode (1)
225
µs
Note:
1. This recovery time does not include the period until the main clock oscillator is stabilized. The CPU
starts operating before the oscillator is stabilized.
t rec(WAIT)
Recovery time from wait mode
to low power mode
Interrupt for exiting
wait mode
Sub clock oscillator
output
On-chip oscillator
output
CPU clock
t rec(WAIT)
t rec(STOP)
Recovery time from stop mode
Interrupt for exiting
stop mode
Main clock oscillator
output
On-chip oscillator
output
CPU clock
t rec(STOP)
Figure 5.4
Clock Circuit Timing
REJ03B0241-0101 Rev.1.01 Dec 07, 2009
Page 80 of 105
R32C/161 Group
5. Electrical Characteristics
Timing Requirements (VCC = 3.0 to 5.5 V, VSS = 0 V, and Ta = Topr, unless otherwise noted)
Table 5.15
Flash Memory CPU Rewrite Mode Timing
Symbol
Value
Characteristics
Min.
Max.
Unit
tcR
Read cycle time
200
ns
tsu(S-R)
Chip-select setup time for read
200
ns
th(R-S)
Chip-select hold time after read
0
ns
tsu(A-R)
Address setup time for read
200
ns
th(R-A)
Address hold time after read
0
ns
tw(R)
Read pulse width
100
ns
tcW
Write cycle time
200
ns
tsu(S-W)
Chip-select setup time for write
0
ns
th(W-S)
Chip-select hold time after write
30
ns
tsu(A-W)
Address setup time for write
0
ns
th(W-A)
Address hold time after write
30
ns
tw(W)
Write pulse width
50
ns
Read cycle
t cR
t su(S-R)
t h(R-S)
t su(A-R)
t h(R-A)
CS0
A23 to A0, BC0 to BC3
t w(R)
RD
Write cycle
t cW
t su(S-W)
t h(W-S)
t su(A-W)
t h(W-A)
CS0 to CS3
A23 to A0, BC0 to BC3
t w(W)
WR
Figure 5.5
Flash Memory CPU Rewrite Mode Timing
REJ03B0241-0101 Rev.1.01 Dec 07, 2009
Page 81 of 105
R32C/161 Group
5. Electrical Characteristics
VCC = 5 V
Table 5.16
Electrical Characteristics (1/3)
(VCC = 4.2 to 5.5 V, VSS = 0 V, Ta = Topr, and f(CPU) = 48 MHz, unless otherwise noted)
Symbol
VOH
VOL
High
level
output
voltage
Low
level
output
voltage
Value
Measurement
condition
Min.
IOH = -5 mA
VCC - 2.0
VCC
V
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
IOH = -200 µA VCC - 0.3
P6_5, P6_7, P7_0, P7_4 to P7_6,
P8_2 to P8_4, P8_6, P8_7, P9_3 to P9_7
VCC
V
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_5, P6_7, P7_0, P7_4 to P7_6,
P8_2 to P8_4, P8_6, P8_7, P9_3 to P9_7
IOL = 5 mA
2.0
V
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_5, P6_7, P7_0, P7_4 to P7_6,
P8_2 to P8_4, P8_6, P8_7, P9_3 to P9_7
IOL = 200 µA
0.45
V
Characteristic
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_5, P6_7, P7_0, P7_4 to P7_6,
P8_2 to P8_4, P8_6, P8_7, P9_3 to P9_7
REJ03B0241-0101 Rev.1.01 Dec 07, 2009
Page 82 of 105
Typ. Max.
Unit
R32C/161 Group
5. Electrical Characteristics
VCC = 5 V
Table 5.17
Electrical Characteristics (2/3) (VCC = 4.2 to 5.5 V, VSS = 0 V, Ta = Topr, and
f(CPU) = 48 MHz, unless otherwise noted)
Symbol
Characteristic
Value
Measurement
Unit
condition
Min. Typ. Max.
VT+ - VT- Hysteresis NMI, INT0 to INT5, TA0IN to TA4IN,
TA0OUT to TA4OUT, TB0IN to TB5IN,
CTS0 to CTS4, CLK0 to CLK4,
RXD0 to RXD4, SCL0 to SCL2,
SDA0 to SDA2, SS0 to SS2,
SRXD0 to SRXD2, ADTRG,
IIO0_0 to IIO0_7, UD0A, UD0B, SCS0,
SSCK0, SSI0, SSO0, LININ, CAN0IN,
CAN1IN, CAN0WU, CAN1WU
RESET
IIH
IIL
0.2
1.0
V
0.2
1.8
V
High level
input
current
XIN, RESET, CNVSS, NSD,
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_5, P6_7, P7_0, P7_4 to P7_6,
P8_2 to P8_7, P9_1, P9_3 to P9_7
VI = 5 V
1.0
µA
Low level
input
current
XIN, RESET, CNVSS, NSD,
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_5, P6_7, P7_0, P7_4 to P7_6,
P8_2 to P8_7, P9_1, P9_3 to P9_7
VI = 0 V
-1.0
µA
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_5, P6_7, P7_0, P7_4 to P7_6,
P8_2 to P8_4, P8_6, P8_7, P9_1,
P9_3 to P9_7
VI = 0 V
170
kΩ
RPULLUP Pull-up
resistor
RfXIN
Feedback
resistor
XIN
RfXCIN
Feedback
resistor
XCIN
REJ03B0241-0101 Rev.1.01 Dec 07, 2009
Page 83 of 105
30
50
1.5
MΩ
15
MΩ
R32C/161 Group
5. Electrical Characteristics
VCC = 5 V
Table 5.18
Symbol
ICC
Electrical Characteristics (3/3)
(VCC = 4.2 to 5.5 V, VSS = 0 V, and Ta = Topr, unless otherwise noted)
Characte
ristic
Power
supply
current
Measurement condition
Value
Min. Typ. Max.
Unit
In single-chip mode,
output pins are left open
and others are
connected to VSS
f(CPU) = 48 MHz, f(BCLK) = 24 MHz,
f(XIN) = 8 MHz,
Active: XIN, PLL,
Stopped: XCIN, OCO
31
XIN-XOUT
Drive power: low
f(CPU) = fSO(PLL)/24 MHz,
Active: PLL (self-oscillation),
Stopped: XIN, XCIN, OCO
7
mA
XCIN-XCOUT
Drive power: low
f(CPU) = f(BCLK) = f(XIN)/256 MHz,
f(XIN) = 8 MHz,
Active: XIN,
Stopped: PLL, XCIN, OCO
1.2
mA
f(CPU) = f(BCLK) = 32.768 kHz,
Active: XCIN,
Stopped: XIN, PLL, OCO,
Main regulator: shutdown
220
µA
f(CPU) = f(BCLK) = f(OCO)/4 kHz,
Active: OCO,
Stopped: XIN, PLL, XCIN,
Main regulator: shutdown
230
µA
f(CPU) = f(BCLK) = f(XIN)/256 MHz,
f(XIN) = 8 MHz,
Active: XIN,
Stopped: PLL, XCIN, OCO,
Ta = 25°C, Wait mode
960
1600
µA
f(CPU) = f(BCLK) = 32.768 kHz,
Active: XCIN,
Stopped: XIN, PLL, OCO,
Main regulator: shutdown,
Ta = 25°C, Wait mode
8
140
µA
f(CPU) = f(BCLK) = f(OCO)/4 kHz,
Active: OCO,
Stopped: XIN, PLL, XCIN,
Main regulator: shutdown,
Ta = 25°C, Wait mode
10
150
µA
Stopped: all clocks,
Main regulator: shutdown,
Ta = 25°C
5
70
µA
Stopped: all clocks,
Main regulator: shutdown,
Ta = 85°C
400
µA
Stopped: all clocks,
Main regulator: shutdown,
Ta = 105°C
1200
µA
Stopped: all clocks,
Main regulator: shutdown,
Ta = 125°C
2000
µA
REJ03B0241-0101 Rev.1.01 Dec 07, 2009
Page 84 of 105
48
mA
R32C/161 Group
5. Electrical Characteristics
VCC = 5 V
Table 5.19
Symbol
A/D Conversion Characteristics (VCC = AVCC = VREF = 4.2 to 5.5 V, VSS = AVSS = 0 V,
Ta = Topr, and f(BCLK) = 24 MHz, unless otherwise noted)
Characteristic
Measurement condition
Resolution
VREF = VCC
Absolute error
VREF = VCC = 5 V
Value
Min.
Typ.
Max.
Unit
10
Bits
AN_0 to AN_4,
AN0_0 to AN0_7,
AN2_0 to AN2_7,
ANEX0, ANEX1
±3
LSB
External op-amp
connection mode
±7
LSB
AN_0 to AN_4,
AN0_0 to AN0_7,
AN2_0 to AN2_7,
ANEX0, ANEX1
±3
LSB
External op-amp
connection mode
±7
LSB
Differential non-linearity
error
±1
LSB
—
Offset error
±3
LSB
—
Gain error
±3
LSB
20
kΩ
—
—
INL
Integral non-linearity
error
DNL
VREF = VCC = 5 V
RLADDER
Resistor ladder
VREF = VCC
tCONV
Conversion time
(10 bits)
φAD = 16 MHz, with sample and hold
function
2.06
µs
φAD = 16 MHz, without sample and hold
function
3.69
µs
φAD = 16 MHz, with sample and hold
function
1.75
µs
φAD = 16 MHz, without sample and hold
function
3.06
µs
φAD = 16 MHz
0.188
µs
tCONV
Conversion time
(8 bits)
tSAMP
Sampling time
VIA
Analog input voltage
φAD
Operating clock
frequency
without sample and hold function
with sample and hold function
4
0
VREF
V
0.25
16
MHz
1
16
MHz
RPU(AST)
Pull-up resistor for opencircuit detection
5
10
15
kΩ
RPD(AST)
Pull-down resistor for
open-circuit detection
5
10
15
kΩ
REJ03B0241-0101 Rev.1.01 Dec 07, 2009
Page 85 of 105
R32C/161 Group
5. Electrical Characteristics
VCC = 5 V
Timing Requirements (VCC = 4.2 to 5.5 V, VSS = 0 V, and Ta = Topr, unless otherwise noted)
Table 5.20
Symbol
External Clock Input
Characteristic
Value
Min.
Max.
250
Unit
tc(X)
External clock input period
125
tw(XH)
External clock input high level pulse width
50
ns
tw(XL)
External clock input low level pulse width
50
ns
tr(X)
External clock input rise time
5
ns
tf(X)
External clock input fall time
5
ns
tw / tc
External clock input duty
60
%
REJ03B0241-0101 Rev.1.01 Dec 07, 2009
Page 86 of 105
40
ns
R32C/161 Group
5. Electrical Characteristics
VCC = 5 V
Timing Requirements (VCC = 4.2 to 5.5 V, VSS = 0 V, and Ta = Topr, unless otherwise noted)
Table 5.21
Timer A Input (Counting input in event counter mode)
Symbol
Characteristic
Value
Min.
Max.
Unit
tc(TA)
TAiIN input clock period
200
ns
tw(TAH)
TAiIN input high level pulse width
80
ns
tw(TAL)
TAiIN input low level pulse width
80
ns
Table 5.22
Timer A Input (Gating input in timer mode)
Symbol
Characteristic
Value
Min.
Max.
Unit
tc(TA)
TAiIN input clock period
400
ns
tw(TAH)
TAiIN input high level pulse width
180
ns
tw(TAL)
TAiIN input low level pulse width
180
ns
Table 5.23
Timer A Input (External trigger input in one-shot timer mode)
Symbol
Characteristic
Value
Min.
Max.
Unit
tc(TA)
TAiIN input clock period
200
ns
tw(TAH)
TAiIN input high level pulse width
80
ns
tw(TAL)
TAiIN input low level pulse width
80
ns
Table 5.24
Timer A Input (External trigger input in pulse-width modulation mode)
Symbol
Characteristic
Value
Min.
Max.
Unit
tw(TAH)
TAiIN input high level pulse width
80
ns
tw(TAL)
TAiIN input low level pulse width
80
ns
Table 5.25
Timer A Input (Increment/decrement count switching input in event counter mode)
Symbol
Characteristic
Value
Min.
Max.
Unit
tc(UP)
TAiOUT input clock period
2000
ns
tw(UPH)
TAiOUT input high level pulse width
1000
ns
tw(UPL)
TAiOUT input low level pulse width
1000
ns
tsu(UP-TIN)
TAiOUT input setup time
400
ns
th(TIN-UP)
TAiOUT input hold time
400
ns
REJ03B0241-0101 Rev.1.01 Dec 07, 2009
Page 87 of 105
R32C/161 Group
5. Electrical Characteristics
VCC = 5 V
Timing Requirements (VCC = 4.2 to 5.5 V, VSS = 0 V, and Ta = Topr, unless otherwise noted)
Table 5.26
Symbol
Timer B Input (Counting input in event counter mode)
Characteristic
Value
Min.
Max.
Unit
tc(TB)
TBiIN input clock period (one edge counting)
200
ns
tw(TBH)
TBiIN input high level pulse width (one edge counting)
80
ns
tw(TBL)
TBiIN input low level pulse width (one edge counting)
80
ns
tc(TB)
TBiIN input clock period (both edges counting)
200
ns
tw(TBH)
TBiIN input high level pulse width (both edges counting)
80
ns
tw(TBL)
TBiIN input low level pulse width (both edges counting)
80
ns
Table 5.27
Symbol
Timer B Input (Pulse period measure mode)
Characteristic
Value
Min.
Max.
Unit
tc(TB)
TBiIN input clock period
400
ns
tw(TBH)
TBiIN input high level pulse width
180
ns
tw(TBL)
TBiIN input low level pulse width
180
ns
Table 5.28
Symbol
Timer B Input (Pulse-width measure mode)
Characteristic
Value
Min.
Max.
Unit
tc(TB)
TBiIN input clock period
400
ns
tw(TBH)
TBiIN input high level pulse width
180
ns
tw(TBL)
TBiIN input low level pulse width
180
ns
REJ03B0241-0101 Rev.1.01 Dec 07, 2009
Page 88 of 105
R32C/161 Group
5. Electrical Characteristics
VCC = 5 V
Timing Requirements (VCC = 4.2 to 5.5 V, VSS = 0 V, and Ta = Topr, unless otherwise noted)
Table 5.29
Serial Interface
Symbol
Characteristic
Value
Min.
Max.
Unit
tc(CK)
CLKi input clock period
200
ns
tw(CKH)
CLKi input high level pulse width
80
ns
tw(CKL)
CLKi input low level pulse width
80
ns
tsu(D-C)
RXDi input setup time
80
ns
th(C-D)
RXDi input hold time
90
ns
Table 5.30
Symbol
A/D Trigger Input
Characteristic
Value
Min.
Max.
Unit
tw(ADH)
ADTRG input high level pulse width
Hardware trigger input high level pulse width
3--------φ AD
ns
tw(ADL)
ADTRG input low level pulse width
Hardware trigger input high level pulse width
125
ns
Table 5.31
Symbol
tw(INH)
tw(INL)
External Interrupt INTi Input
Value
Characteristic
INTi input high level pulse width (1)
INTi input low level pulse width (1)
Min.
Unit
Edge sensitive
250
ns
Level sensitive
tc(CPU) + 200
ns
Edge sensitive
250
ns
Level sensitive
tc(CPU) + 200
ns
Note:
1. The values are applied in case filtering function is disabled.
REJ03B0241-0101 Rev.1.01 Dec 07, 2009
Page 89 of 105
Max.
R32C/161 Group
5. Electrical Characteristics
VCC = 5 V
Timing Requirements (VCC = 4.2 to 5.5 V, VSS = 0 V, and Ta = Topr, unless otherwise noted)
Table 5.32
Symbol
Serial Bus Interface
Characteristic
Value
Min.
Max.
Unit
f(SSCK)
SSCKi frequency
tc(SSCK)
SSCKi clock period
tw(SSCKH)
SSCKi input high level pulse width
0.35 × tc(SSCK) 0.6 × tc(SSCK)
ns
tw(SSCKL)
SSCKi input low level pulse width
0.35 × tc(SSCK) 0.6 × tc(SSCK)
ns
tr(SSCK)
SSCKi input rising time
1
µs
tf(SSCK)
SSCKi input falling time
1
µs
tsu(SCS-SSCK)
SCSi input setup time
tc(BCLK) + 50
ns
th(SSCK-SCS)
SCSi input hold time
tc(BCLK) + 50
ns
tsu(SSI-SSCK)
SSI input setup time
80
ns
th(SSCK-SSI)
SSI input hold time
10
ns
tsu(SSO-SSCK)
SSO input setup time
80
ns
th(SSCK-SSO)
SSO input hold time
20
ns
REJ03B0241-0101 Rev.1.01 Dec 07, 2009
Page 90 of 105
4
250
MHz
ns
R32C/161 Group
5. Electrical Characteristics
VCC = 5 V
Switching Characteristics (VCC = 4.2 to 5.5 V, VSS = 0 V, and Ta = Topr, unless otherwise noted)
Table 5.33
Symbol
Serial Interface
td(C-Q)
TXDi output delay time
th(C-Q)
TXDi output hold time
Table 5.34
Symbol
Measurement
condition
Characteristic
Value
Min.
Refer to
Figure 5.6
Max.
Unit
80
0
ns
ns
Serial Bus Interface
Characteristic
Measurement
condition
Value
Min.
Max.
Unit
tw(SSCKH)
SSCKi output high level pulse width
0.35 × tc(SSCK)
0.6 × tc(SSCK)
ns
tw(SSCKL)
SSCKi output low level pulse width
0.35 × tc(SSCK)
0.6 × tc(SSCK)
ns
tr(SSCK)
SSCKi output rising time
20
ns
tf(SSCK)
SSCKi output falling time
20
ns
0.5 × tc(SSCK) + 20
ns
td(SCS-SSCK) SSCKi output delay time for SCSi
td(SSCK-SCS) SCSi output delay time for SSCKi
ten(SCS-SSO) SSOi output enable time
tdis(SCS-SSO) SSOi output disable time
0.5 × tc(SSCK) - 20
Refer to
Figure 5.6
ns
1.5 × tc(BCLK) + 100 ns
1.5 × tc(BCLK) + 100 ns
SSIi output enable time
1.5 × tc(BCLK) + 100 ns
tdis(SCS-SSI) SSIi output disable time
1.5 × tc(BCLK) + 100 ns
ten(SCS-SSI)
td(SSCK-SSO) SSOi output delay time for SSCKi
30
ns
td(SSCK-SSI) SSIi output delay time for SSCKi
85
ns
0.625 × tc(SSCK)
ns
trec(SCS)
SCSi output high level period in
continuous transmission
REJ03B0241-0101 Rev.1.01 Dec 07, 2009
Page 91 of 105
R32C/161 Group
5. Electrical Characteristics
VCC = 3.3 V
Table 5.35
Electrical Characteristics (1/3) (VCC = 3.0 to 3.6 V, VSS = 0 V, Ta = Topr, and
f(CPU) = 48 MHz, unless otherwise noted)
Symbol
VOH
VOL
Characteristic
Min.
VCC - 0.6
High
level
output
voltage
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_5, P6_7, P7_0, P7_4 to P7_6,
P8_2 to P8_4, P8_6, P8_7, P9_3 to P9_7
IOH = -1 mA
Low
level
output
voltage
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_5, P6_7, P7_0, P7_4 to P7_6,
P8_2 to P8_4, P8_6, P8_7, P9_3 to P9_7
IOL = 1 mA
REJ03B0241-0101 Rev.1.01 Dec 07, 2009
Page 92 of 105
Value
Measurement
condition
Typ. Max.
Unit
VCC
V
0.5
V
R32C/161 Group
5. Electrical Characteristics
VCC = 3.3 V
Table 5.36
Symbol
Electrical Characteristics (2/3) (VCC = 3.0 to 3.6 V, VSS = 0 V, Ta = Topr, and
f(CPU) = 48 MHz, unless otherwise noted)
Characteristic
VT+ - VT- Hysteresis NMI, INT0 to INT5, TA0IN to TA4IN,
TA0OUT to TA4OUT, TB0IN to TB5IN,
CTS0 to CTS4, CLK0 to CLK4,
RXD0 to RXD4, SCL0 to SCL2,
SDA0 to SDA2, SS0 to SS2,
SRXD0 to SRXD2, ADTRG,
IIO0_0 to IIO0_7, UD0A, UD0B, SCS0,
SSCK0, SSI0, SSO0, LININ, CAN0IN,
CAN1IN, CAN0WU, CAN1WU
RESET
High level XIN, RESET, CNVSS, NSD,
IIH
input
P0_0 to P0_7, P1_0 to P1_7,
current
P2_0 to P2_7, P3_0 to P3_7,
P4_0 to P4_7, P5_0 to P5_7, P6_5, P6_7,
P7_0, P7_4 to P7_6, P8_2 to P8_7, P9_1,
P9_3 to P9_7
Low level XIN, RESET, CNVSS, NSD,
IIL
input
P0_0 to P0_7, P1_0 to P1_7,
current
P2_0 to P2_7, P3_0 to P3_7,
P4_0 to P4_7, P5_0 to P5_7, P6_5, P6_7,
P7_0, P7_4 to P7_6, P8_2 to P8_7, P9_1,
P9_3 to P9_7
P0_0 to P0_7, P1_0 to P1_7,
RPULLUP Pull-up
resistor
P2_0 to P2_7, P3_0 to P3_7,
P4_0 to P4_7, P5_0 to P5_7, P6_5, P6_7,
P7_0, P7_4 to P7_6, P8_2 to P8_4, P8_6,
P8_7, P9_1, P9_3 to P9_7
RfXIN
Feedback XIN
resistor
RfXCIN
Feedback XCIN
resistor
REJ03B0241-0101 Rev.1.01 Dec 07, 2009
Page 93 of 105
Value
Measurement
Unit
condition
Min. Typ. Max.
0.2
1.0
V
0.2
1.8
V
VI = 3.3 V
1.0
µA
VI = 0 V
-1.0
µA
500
kΩ
VI = 0 V
50
100
3
MΩ
25
MΩ
R32C/161 Group
5. Electrical Characteristics
VCC = 3.3 V
Table 5.37
Symbol
ICC
Electrical Characteristics (3/3)
(VCC = 3.0 to 3.6 V, VSS = 0 V, and Ta = Topr, unless otherwise noted)
Characte
ristic
Power
supply
current
Measurement condition
Value
Min. Typ. Max.
Unit
In single-chip mode,
output pins are left open
and others are
connected to VSS
f(CPU) = 48 MHz, f(BCLK) = 24 MHz,
f(XIN) = 8 MHz,
Active: XIN, PLL,
Stopped: XCIN, OCO
31
XIN-XOUT
Drive power: low
f(CPU) = fSO(PLL)/24 MHz,
Active: PLL (self-oscillation),
Stopped: XIN, XCIN, OCO
7
mA
XCIN-XCOUT
Drive power: low
f(CPU) = f(BCLK) = f(XIN)/256 MHz,
f(XIN) = 8 MHz,
Active: XIN,
Stopped: PLL, XCIN, OCO
670
µA
f(CPU) = f(BCLK) = 32.768 kHz,
Active: XCIN,
Stopped: XIN, PLL, OCO,
Main regulator: shutdown
180
µA
f(CPU) = f(BCLK) = f(OCO)/4 kHz,
Active: OCO,
Stopped: XIN, PLL, XCIN,
Main regulator: shutdown
190
µA
f(CPU) = f(BCLK) = f(XIN)/256 MHz,
f(XIN) = 8 MHz,
Active: XIN,
Stopped: PLL, XCIN, OCO,
Ta = 25°C, Wait mode
500
900
µA
f(CPU) = f(BCLK) = 32.768 kHz,
Active: XCIN,
Stopped: XIN, PLL, OCO,
Main regulator: shutdown,
Ta = 25°C, Wait mode
8
140
µA
f(CPU) = f(BCLK) = f(OCO)/4 kHz,
Active: OCO,
Stopped: XIN, PLL, XCIN,
Main regulator: shutdown,
Ta = 25°C, Wait mode
10
150
µA
Stopped: all clocks,
Main regulator: shutdown,
Ta = 25°C
5
70
µA
Stopped: all clocks,
Main regulator: shutdown,
Ta = 85°C
400
µA
Stopped: all clocks,
Main regulator: shutdown,
Ta = 105°C
1200
µA
Stopped: all clocks,
Main regulator: shutdown,
Ta = 125°C
2000
µA
REJ03B0241-0101 Rev.1.01 Dec 07, 2009
Page 94 of 105
48
mA
R32C/161 Group
5. Electrical Characteristics
VCC = 3.3 V
Table 5.38
Symbol
—
A/D Conversion Characteristics (VCC= AVCC = VREF = 3.0 to 3.6 V, VSS = AVSS = 0 V,
Ta = Topr, and f(BCLK) = 24 MHz, unless otherwise noted)
Characteristic
Min.
Typ.
Max.
Unit
VREF = VCC
10
Bits
Absolute error
VREF = VCC = 3.3 V AN_0 to AN_4,
AN0_0 to AN0_7,
AN2_0 to AN2_7,
ANEX0, ANEX1
±5
LSB
External op-amp
connection mode
±7
LSB
VREF = VCC = 3.3 V AN_0 to AN_4,
AN0_0 to AN0_7,
AN2_0 to AN2_7,
ANEX0, ANEX1
±5
LSB
External op-amp
connection mode
±7
LSB
±1
LSB
Integral non-linearity
error
DNL
Value
Resolution
—
INL
Measurement condition
Differential nonlinearity error
VREF = VCC = 3.3 V
—
Offset error
±3
LSB
—
Gain error
±3
LSB
20
kΩ
RLADDER
Resistor ladder
VREF = VCC
tCONV
Conversion time
(10 bits)
φAD = 10 MHz,
with sample and hold function
3.3
µs
tCONV
Conversion time
(8 bits)
φAD = 10 MHz,
with sample and hold function
2.8
µs
tSAMP
Sampling time
φAD = 10 MHz
0.3
µs
VIA
Analog input voltage
φAD
Operating clock
frequency
without sample and hold function
with sample and hold function
4
0
VREF
V
0.25
10
MHz
1
10
MHz
RPU(AST)
Pull-up resistor for
open-circuit detection
5
10
15
kΩ
RPD(AST)
Pull-down resistor for
open-circuit detection
5
10
15
kΩ
REJ03B0241-0101 Rev.1.01 Dec 07, 2009
Page 95 of 105
R32C/161 Group
5. Electrical Characteristics
VCC = 3.3 V
Timing Requirements (VCC = 3.0 to 3.6 V, VSS = 0 V, and Ta = Topr, unless otherwise noted)
Table 5.39
Symbol
External Clock Input
Characteristic
Value
Min.
Max.
250
Unit
tc(X)
External clock input period
125
tw(XH)
External clock input high level pulse width
50
ns
tw(XL)
External clock input low level pulse width
50
ns
tr(X)
External clock input rise time
5
ns
tf(X)
External clock input fall time
5
ns
tw / tc
External clock input duty
60
%
REJ03B0241-0101 Rev.1.01 Dec 07, 2009
Page 96 of 105
40
ns
R32C/161 Group
5. Electrical Characteristics
VCC = 3.3 V
Timing Requirements (VCC = 3.0 to 3.6 V, VSS = 0 V, and Ta = Topr, unless otherwise noted)
Table 5.40
Timer A Input (Counting input in event counter mode)
Symbol
Characteristic
Value
Min.
Max.
Unit
tc(TA)
TAiIN input clock period
200
ns
tw(TAH)
TAiIN input high level pulse width
80
ns
tw(TAL)
TAiIN input low level pulse width
80
ns
Table 5.41
Timer A Input (Gating input in timer mode)
Symbol
Characteristic
Value
Min.
Max.
Unit
tc(TA)
TAiIN input clock period
400
ns
tw(TAH)
TAiIN input high level pulse width
180
ns
tw(TAL)
TAiIN input low level pulse width
180
ns
Table 5.42
Timer A Input (External trigger input in one-shot timer mode)
Symbol
Characteristic
Value
Min.
Max.
Unit
tc(TA)
TAiIN input clock period
200
ns
tw(TAH)
TAiIN input high level pulse width
80
ns
tw(TAL)
TAiIN input low level pulse width
80
ns
Table 5.43
Timer A Input (External trigger input in pulse-width modulation mode)
Symbol
Characteristic
Value
Min.
Max.
Unit
tw(TAH)
TAiIN input high level pulse width
80
ns
tw(TAL)
TAiIN input low level pulse width
80
ns
Table 5.44
Timer A Input (Increment/decrement count switching input in event counter mode)
Symbol
Characteristic
Value
Min.
Max.
Unit
tc(UP)
TAiOUT input clock period
2000
ns
tw(UPH)
TAiOUT input high level pulse width
1000
ns
tw(UPL)
TAiOUT input low level pulse width
1000
ns
tsu(UP-TIN)
TAiOUT input setup time
400
ns
th(TIN-UP)
TAiOUT input hold time
400
ns
REJ03B0241-0101 Rev.1.01 Dec 07, 2009
Page 97 of 105
R32C/161 Group
5. Electrical Characteristics
VCC = 3.3 V
Timing Requirements (VCC = 3.0 to 3.6 V, VSS = 0 V, and Ta = Topr, unless otherwise noted)
Table 5.45
Symbol
Timer B Input (Counting input in event counter mode)
Characteristic
Value
Min.
Max.
Unit
tc(TB)
TBiIN input clock period (one edge counting)
200
ns
tw(TBH)
TBiIN input high level pulse width (one edge counting)
80
ns
tw(TBL)
TBiIN input low level pulse width (one edge counting)
80
ns
tc(TB)
TBiIN input clock period (both edges counting)
200
ns
tw(TBH)
TBiIN input high level pulse width (both edges counting)
80
ns
tw(TBL)
TBiIN input low level pulse width (both edges counting)
80
ns
Table 5.46
Symbol
Timer B Input (Pulse period measure mode)
Characteristic
Value
Min.
Max.
Unit
tc(TB)
TBiIN input clock period
400
ns
tw(TBH)
TBiIN input high level pulse width
180
ns
tw(TBL)
TBiIN input low level pulse width
180
ns
Table 5.47
Symbol
Timer B Input (Pulse-width measure mode)
Characteristic
Value
Min.
Max.
Unit
tc(TB)
TBiIN input clock period
400
ns
tw(TBH)
TBiIN input high level pulse width
180
ns
tw(TBL)
TBiIN input low level pulse width
180
ns
REJ03B0241-0101 Rev.1.01 Dec 07, 2009
Page 98 of 105
R32C/161 Group
5. Electrical Characteristics
VCC = 3.3 V
Timing Requirements (VCC = 3.0 to 3.6 V, VSS = 0 V, and Ta = Topr, unless otherwise noted)
Table 5.48
Serial Interface
Symbol
Characteristic
Value
Min.
Max.
Unit
tc(CK)
CLKi input clock period
200
ns
tw(CKH)
CLKi input high level pulse width
80
ns
tw(CKL)
CLKi input low level pulse width
80
ns
tsu(D-C)
RXDi input setup time
80
ns
th(C-D)
RXDi input hold time
90
ns
Table 5.49
Symbol
A/D Trigger Input
Characteristic
Value
Min.
Max.
Unit
tw(ADH)
ADTRG input high level pulse width
Hardware trigger input high level pulse width
3--------φ AD
ns
tw(ADL)
ADTRG input low level pulse width
Hardware trigger input high level pulse width
125
ns
Table 5.50
Symbol
tw(INH)
tw(INL)
External Interrupt INTi Input
Value
Characteristic
INTi input high level pulse width (1)
INTi input low level pulse width (1)
Min.
Unit
Edge sensitive
250
ns
Level sensitive
tc(CPU) + 200
ns
Edge sensitive
250
ns
Level sensitive
tc(CPU) + 200
ns
Note:
1. The values are applied in case filtering function is disabled.
REJ03B0241-0101 Rev.1.01 Dec 07, 2009
Page 99 of 105
Max.
R32C/161 Group
5. Electrical Characteristics
VCC = 3.3 V
Timing Requirements (VCC = 3.0 to 3.6 V, VSS = 0 V, and Ta = Topr, unless otherwise noted)
Table 5.51
Serial Bus Interface
Symbol
Characteristic
Value
Min.
Max.
Unit
f(SSCK)
SSCKi frequency
tc(SSCK)
SSCKi clock period
tw(SSCKH)
SSCKi input high level pulse width
0.35 × tc(SSCK) 0.6 × tc(SSCK)
ns
tw(SSCKL)
SSCKi input low level pulse width
0.35 × tc(SSCK) 0.6 × tc(SSCK)
ns
tr(SSCK)
SSCKi input rising time
1
µs
tf(SSCK)
SSCKi input falling time
1
µs
4
250
MHz
ns
tsu(SCS-SSCK) SCSi input setup time
tc(BCLK) + 50
ns
th(SSCK-SCS)
SCSi input hold time
tc(BCLK) + 50
ns
tsu(SSI-SSCK)
SSI input setup time
100
ns
th(SSCK-SSI)
SSI input hold time
10
ns
100
ns
20
ns
tsu(SSO-SSCK) SSO input setup time
th(SSCK-SSO)
SSO input hold time
REJ03B0241-0101 Rev.1.01 Dec 07, 2009
Page 100 of 105
R32C/161 Group
5. Electrical Characteristics
VCC = 3.3 V
Switching Characteristics (VCC = 3.0 to 3.6 V, VSS = 0 V, and Ta = Topr, unless otherwise noted)
Table 5.52
Symbol
Serial Interface
td(C-Q)
TXDi output delay time
th(C-Q)
TXDi output hold time
Table 5.53
Serial Bus Interface
Symbol
Measurement
condition
Characteristic
Characteristic
Value
Min.
Unit
80
Refer to
Figure 5.6
Measurement
condition
Max.
0
ns
ns
Value
Min.
Max.
Unit
tw(SSCKH)
SSCKi output high level pulse
width
0.35 × tc(SSCK)
0.6 × tc(SSCK)
ns
tw(SSCKL)
SSCKi output low level pulse
width
0.35 × tc(SSCK)
0.6 × tc(SSCK)
ns
tr(SSCK)
SSCKi output rising time
35
ns
tf(SSCK)
SSCKi output falling time
35
ns
0.5 × tc(SSCK) + 40
ns
td(SCS-SSCK) SSCKi output delay time for SCSi
td(SSCK-SCS) SCSi output delay time for SSCKi
ten(SCS-SSO) SSOi output enable time
tdis(SCS-SSO) SSOi output disable time
Refer to
Figure 5.6
0.5 × tc(SSCK) - 40
ns
1.5 × tc(BCLK) + 100 ns
1.5 × tc(BCLK) + 100 ns
SSIi output enable time
1.5 × tc(BCLK) + 100 ns
tdis(SCS-SSI) SSIi output disable time
1.5 × tc(BCLK) + 100 ns
ten(SCS-SSI)
td(SSCK-SSO) SSOi output delay time for SSCKi
50
ns
td(SSCK-SSI) SSIi output delay time for SSCKi
120
ns
0.625 × tc(SSCK)
ns
trec(SCS)
SCSi output high level period in
continuous transmission
REJ03B0241-0101 Rev.1.01 Dec 07, 2009
Page 101 of 105
R32C/161 Group
5. Electrical Characteristics
MCU
Pin to be
measured
Figure 5.6
30 pF
Switching Characteristic Measurement Circuit
t c(X)
XIN
t w(XH)
t r(X)
Figure 5.7
External Clock Input Timing
REJ03B0241-0101 Rev.1.01 Dec 07, 2009
Page 102 of 105
t w(XL)
t f(X)
R32C/161 Group
5. Electrical Characteristics
t c(TA)
t w(TAH)
t w(TAL)
TAiIN input
t c(UP)
t w(UPH)
t w(UPL)
TAiOUT input
In event counter mode
TAiOUT input (input for increment/
decrement count switching)
t su(UP-TIN)
t h(TIN-UP)
TAiIN input (in falling edge counting)
TAiIN input (in rising edge counting)
t c(TB)
t w(TBH)
t w(TBL)
TBiIN input
t c(CK)
t w(CKH)
t w(CKL)
CLKi
t d(C-Q)
t h(C-Q)
TXDi
t su(D-C)
t h(C-D)
RXDi
t w(ADL)
t w(ADH)
t w(INL)
t w(INH)
ADTRG input
INTi input
2 CPU clock cycles +
300 ns or more
NMI input
Figure 5.8
Timing of Peripheral Functions
REJ03B0241-0101 Rev.1.01 Dec 07, 2009
Page 103 of 105
2 CPU clock cycles +
300 ns or more
R32C/161 Group
5. Electrical Characteristics
t c(SSCK)
SSCKi
t w(SSCKH)
t r(SSCK)
t w(SSCKL)
t f(SSCK)
SCSi (output)
SSCKi (output)
t d(SCS-SSCK)
t rec(SCS)
t d(SSCK-SCS)
CPOS = 1
CPOS = 0
t en(SCS-SSO)
t dis(SCS-SSO)
SSOi (output)
SCSi (input)
SSCKi (input)
t su(SCS-SSCK)
t h(SSCK-SCS)
CPOS = 1
CPOS = 0
t en(SCS-SSI)
t dis(SCS-SSI)
SSIi (output)
SSCKi
CPOS = 1
CPOS = 0
t d(SSCK-SSI)
t d(SSCK-SSO)
SSIi / SSOi (output)
CPHS = 1
t d(SSCK-SSI)
t d(SSCK-SSO)
CPHS = 0
t su(SSI-SSCK)
t su(SSO-SSCK)
SSIi / SSOi (input)
CPHS = 1
t su(SSI-SSCK)
t su(SSO-SSCK)
CPHS = 0
Figure 5.9
Timing of Serial Bus Interface
REJ03B0241-0101 Rev.1.01 Dec 07, 2009
Page 104 of 105
t h(SSCK-SSI)
t h(SSCK-SSO)
t h(SSCK-SSI)
t h(SSCK-SSO)
R32C/161 Group
Appendix 1. Package Dimensions
Appendix 1. Package Dimensions
JEITA Package Code
P-LQFP80-12x12-0.50
RENESAS Code
PLQP0080KB-A
Previous Code
80P6Q-A
MASS[Typ.]
0.5g
HD
*1
D
60
41
NOTE)
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
40
61
bp
E
c
*2
HE
c1
b1
Reference
Symbol
ZE
Terminal cross section
80
21
1
20
ZD
Index mark
bp
c
A
*3
A1
y
e
A2
F
L
x
L1
Detail F
REJ03B0241-0101 Rev.1.01 Dec 07, 2009
Page 105 of 105
D
E
A2
HD
HE
A
A1
bp
b1
c
c1
e
x
y
ZD
ZE
L
L1
Dimension in Millimeters
Min Nom Max
11.9 12.0 12.1
11.9 12.0 12.1
1.4
13.8 14.0 14.2
13.8 14.0 14.2
1.7
0.1 0.2
0
0.15 0.20 0.25
0.18
0.09 0.145 0.20
0.125
0°
10°
0.5
0.08
0.08
1.25
1.25
0.3 0.5 0.7
1.0
REVISION HISTORY
Rev.
0.10
1.01
Date
Feb 14, 2008
Dec 07, 2009
Page
—
—
1
3
4
5
6
8
10, 11
—
12, 13
—
—
17
18, 19
24
26
30
31
33
35, 36
R32C/161 Group Datasheet
Description
Summary
Initial release
Second edition released
Chapter 1. Overview
• Added “(MCUs)” to line 1 of 1.1
• Changed the following expressions in Table 1.2: “sample & hold” to
“sample and hold”, “erase/program” to “program/erase”, “Read
protection” to “Security protection”, “ID code check” to “ID code
protect”, and “on-board flash reprogramming” to “on-board flash
programming”
• Added “(SBI)” to unit “Serial Bus Interface” in Table 1.2; Specified
values for current consumption
• Completed “under development” phase of part number R5F64610JFP
in Table 1.3; Updated the table
• Deleted hyphen before ROM number in Figure 1.1
• Changed Figure 1.2
• Moved four SBI signal lines (pin numbers 36 to 39) in Table 1.4 to
column “UART / SBI Pin”
• Changed descriptions “Functional Category” and “Function” in Tables
1.6 and 1.7 to “Function” and “Description”, respectively
Chapter 2. Central Processing Unit
• Made major text modifications to this chapter
• Changed description “interrupt table register” in Figure 2.1 and 2.1.6
to “interrupt vector table base register”
Chapter 3. Memory
• Made major text modifications to this chapter
Chapter 4. Special Function Registers
• Changed expression “Start/Stop Condition” to “Start Condition/Stop
Condition”
• Changed hexadecimal format of reset values for registers CCR and
FMCR in Table 4.1 to binary
• Changed expression “DMAi Interrupt” in Tables 4.2 and 4.3 to “DMAi
Transfer Complete Interrupt”
• Changed binary format of reset values for U3RB and U4RB in Table
4.8 to hexadecimal
• Changed expression of register name “Xi Register Yi Register” and
symbol “XiR, YiR” in Table 4.10 to “Xi Register/Yi Register” and to
“XiR/YiR”, respectively
• Deleted ADC0N4 in Table 4.14
• Changed reset value for PDi register in Table 4.15 to binary
• Modified reset value for PLS in Table 4.17 to “1XXX XX00b”
• Modified register name “Port Pi_j Port Function Select Register” in
Table 4.19 and 4.20 to “Port Pi_j Function Select Register”
A- 1
REVISION HISTORY
Rev.
Date
Page
38
39
55, 69
—
R32C/161 Group Datasheet
Description
Summary
• Modified register names in Table 4.22 “DMAi Source Select Register
1” to “DMAi Request Source Select Register” and “DMAi Source
Select Register 2” to “DMAi Request Source Select Register 2”;
Changed expression “Wake-up/Interrupt Priority Level Control
Register” to “Wake-up IPL Setting Register”
• Modified “X” in reset values for unassigned bits to “0” for the following
registers in Table 4.23: LCW, LBRG, LMD0, LBRK, LSPC, LRFC, LSC,
LTC, LST, and LEST
• Modified reset value “00h” for C1CLKR in Table 4.39 and C0CLKR in
Table 4.53 to “000X 0000b”; Added addresses “047F60h to 047FFFh”
and “048000h to 04FFFFh”
Chapter 5. Electrical Characteristics
• Added initially
All trademarks and registered trademarks are the property of their respective owners.
A- 2
Sales Strategic Planning Div.
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
Notes:
1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes
warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property
rights or any other rights of Renesas or any third party with respect to the information in this document.
2. Renesas shall have no liability for damages or infringement of any intellectual property or other rights arising out of the use of any information in this document, including,
but not limited to, product data, diagrams, charts, programs, algorithms, and application circuit examples.
3. You should not use the products or the technology described in this document for the purpose of military applications such as the development of weapons of mass
destruction or for the purpose of any other military use. When exporting the products or technology described herein, you should follow the applicable export control laws
and regulations, and procedures required by such laws and regulations.
4. All information included in this document such as product data, diagrams, charts, programs, algorithms, and application circuit examples, is current as of the date this
document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas products listed in this document,
please confirm the latest product information with a Renesas sales office. Also, please pay regular and careful attention to additional and different information to be
disclosed by Renesas such as that disclosed through our website. (http://www.renesas.com )
5. Renesas has used reasonable care in compiling the information included in this document, but Renesas assumes no liability whatsoever for any damages incurred as a
result of errors or omissions in the information included in this document.
6. When using or otherwise relying on the information in this document, you should evaluate the information in light of the total system before deciding about the applicability
of such information to the intended application. Renesas makes no representations, warranties or guaranties regarding the suitability of its products for any particular
application and specifically disclaims any liability arising out of the application and use of the information in this document or Renesas products.
7. With the exception of products specified by Renesas as suitable for automobile applications, Renesas products are not designed, manufactured or tested for applications
or otherwise in systems the failure or malfunction of which may cause a direct threat to human life or create a risk of human injury or which require especially high quality
and reliability such as safety systems, or equipment or systems for transportation and traffic, healthcare, combustion control, aerospace and aeronautics, nuclear power, or
undersea communication transmission. If you are considering the use of our products for such purposes, please contact a Renesas sales office beforehand. Renesas shall
have no liability for damages arising out of the uses set forth above.
8. Notwithstanding the preceding paragraph, you should not use Renesas products for the purposes listed below:
(1) artificial life support devices or systems
(2) surgical implantations
(3) healthcare intervention (e.g., excision, administration of medication, etc.)
(4) any other purposes that pose a direct threat to human life
Renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who elect to use Renesas products in any of the foregoing
applications shall indemnify and hold harmless Renesas Technology Corp., its affiliated companies and their officers, directors, and employees against any and all
damages arising out of such applications.
9. You should use the products described herein within the range specified by Renesas, especially with respect to the maximum rating, operating supply voltage range,
movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas shall have no liability for malfunctions or damages
arising out of the use of Renesas products beyond such specified ranges.
10. Although Renesas endeavors to improve the quality and reliability of its products, IC products have specific characteristics such as the occurrence of failure at a certain
rate and malfunctions under certain use conditions. Please be sure to implement safety measures to guard against the possibility of physical injury, and injury or damage
caused by fire in the event of the failure of a Renesas product, such as safety design for hardware and software including but not limited to redundancy, fire control and
malfunction prevention, appropriate treatment for aging degradation or any other applicable measures. Among others, since the evaluation of microcomputer software
alone is very difficult, please evaluate the safety of the final products or system manufactured by you.
11. In case Renesas products listed in this document are detached from the products to which the Renesas products are attached or affixed, the risk of accident such as
swallowing by infants and small children is very high. You should implement safety measures so that Renesas products may not be easily detached from your products.
Renesas shall have no liability for damages arising out of such detachment.
12. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written approval from Renesas.
13. Please contact a Renesas sales office if you have any questions regarding the information contained in this document, Renesas semiconductor products, or if you have
any other inquiries.
http://www.renesas.com
RENESAS SALES OFFICES
Refer to "http://www.renesas.com/en/network" for the latest and detailed information.
Renesas Technology America, Inc.
450 Holger Way, San Jose, CA 95134-1368, U.S.A
Tel: <1> (408) 382-7500, Fax: <1> (408) 382-7501
Renesas Technology Europe Limited
Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K.
Tel: <44> (1628) 585-100, Fax: <44> (1628) 585-900
Renesas Technology (Shanghai) Co., Ltd.
Unit 204, 205, AZIACenter, No.1233 Lujiazui Ring Rd, Pudong District, Shanghai, China 200120
Tel: <86> (21) 5877-1818, Fax: <86> (21) 6887-7858/7898
Renesas Technology Hong Kong Ltd.
7th Floor, North Tower, World Finance Centre, Harbour City, Canton Road, Tsimshatsui, Kowloon, Hong Kong
Tel: <852> 2265-6688, Fax: <852> 2377-3473
Renesas Technology Taiwan Co., Ltd.
10th Floor, No.99, Fushing North Road, Taipei, Taiwan
Tel: <886> (2) 2715-2888, Fax: <886> (2) 3518-3399
Renesas Technology Singapore Pte. Ltd.
1 Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632
Tel: <65> 6213-0200, Fax: <65> 6278-8001
Renesas Technology Korea Co., Ltd.
Kukje Center Bldg. 18th Fl., 191, 2-ka, Hangang-ro, Yongsan-ku, Seoul 140-702, Korea
Tel: <82> (2) 796-3115, Fax: <82> (2) 796-2145
Renesas Technology Malaysia Sdn. Bhd
Unit 906, Block B, Menara Amcorp, Amcorp Trade Centre, No.18, Jln Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, Malaysia
Tel: <603> 7955-9390, Fax: <603> 7955-9510
© 2009. Renesas Technology Corp., All rights reserved. Printed in Japan.
Colophon .7.2