NJG1699MD7 High Isolation SP4T SWITCH

NJG1699MD7
High Isolation SP4T SWITCH
GENERAL DESCRIPTION
The NJG1699MD7 is a GaAs high isolation SP4T switch MMIC. It
features low insertion loss and very high isolation. It has integrated
DC blocking capacitor at PC port.
The ESD protection circuits are integrated in the IC to achieve
high ESD tolerance.
The ultra-small and ultra-thin EQFN14-D7 package is adopted.
PACKAGE OUTLINE
NJG1699MD7
APPLICATIONS
Suitable for multi-mode 2G/3G and LTE application receive system
Rx signal switching
FEATURES
Low operation voltage
Low control voltage
High isolation
VDD=+2.7V typ.
VCTL(H)=+1.8V typ.
50dB typ. @f=1.0GHz, PIN=0dBm
48dB typ. @f=2.0GHz, PIN=0dBm
43dB typ. @f=2.7GHz, PIN=0dBm
Low insertion loss
0.55dB typ. @f=1.0GHz, PIN=0dBm
0.55dB typ. @f=2.0GHz, PIN=0dBm
0.65dB typ. @f=2.7GHz, PIN=0dBm
Small package
EQFN14-D7 (Package size: 1.6x1.6x0.397mm typ.)
RoHS compliant and Halogen Free
MSL 1
PIN CONFIGURATION
(Top View)
P1
GND
P2
GND
GND
PC
VCTL1
VDD
VCTL2
GND
GND
P4
GND
Pin connection
1. GND
8. GND
2. PC
9. VCTL2
3. VDD
10. VCTL1
4. GND
11. GND
5. P4
12. P2
6. GND
13. GND
7. P3
14. P1
Exposed PAD: GND
P3
TRUTH TABLE
“H”=VCTL(H), “L”=VCTL(L)
ON PATH
PC-P1
PC-P2
PC-P3
PC-P4
VCTL1
H
L
L
H
VCTL2
L
L
H
H
NOTE: Please note that any information on this catalog will be subject to change.
Ver.2013-11-15
-1-
NJG1699MD7
ABSOLUTE MAXIMUM RATINGS
PARAMETER
(Ta=+25°C, Zs=Zl=50Ω)
RATINGS
UNITS
CONDITIONS
SYMBOL
RF Input Power
PIN
VDD =2.7V
28
dBm
Supply Voltage
VDD
VDD terminal
5.0
V
Control Voltage
VCTL
VCTL1, VCTL2 terminal
5.0
V
1300
mW
Four-layer FR4 PCB with through-hole
(76.2x114.3mm), Tj=150°C
Power Dissipation
PD
Operating Temp.
Topr
-40~+90
°C
Storage Temp.
Tstg
-55~+150
°C
ELECTRICAL CHARACTERISTICS
(General conditions: Ta=+25°C, Zs=Zl=50Ω, VDD=2.7V, VCTL(L)=0V, VCTL(H)=1.8V, with application circuit)
PARAMETERS
SYMBOL
Supply Voltage
VDD
Operating Current
IDD
CONDITIONS
VDD terminal
MIN
TYP
MAX
UNITS
1.5
2.7
4.5
V
-
20
40
µA
Control Voltage (LOW)
VCTL(L)
VCTL1, VCTL2 terminal
0
0
0.45
V
Control Voltage (HIGH)
VCTL(H)
VCTL1, VCTL2 terminal
1.35
1.8
4.5
V
VCTL(H) =1.8V
-
5
10
µA
Control Current
ICTL
Insertion Loss 1
LOSS1
f=1.0GHz, PIN=0dBm
-
0.55
0.75
dB
Insertion Loss 2
LOSS2
f=2.0GHz, PIN=0dBm
-
0.55
0.75
dB
Insertion Loss 3
LOSS3
f=2.7GHz, PIN=0dBm
-
0.60
0.80
dB
Isolation 1
ISL1
PC-P1, P2, P3, P4
f=1.0GHz, PIN=0dBm
45
50
-
dB
Isolation 2
ISL2
PC-P1, P2, P3, P4
f=2.0GHz, PIN=0dBm
45
48
-
dB
Isolation 3
ISL3
PC-P1, P2, P3, P4
f=2.7GHz, PIN=0dBm
40
43
-
dB
Input power at 0.2dB
Compression Point
P-0.2dB
f=2.0GHz
18
22
-
dBm
VSWR
VSWR
f=2.0GHz, On port
-
1.3
1.5
-
50% VCTL to 10/90% RF
-
2
5
µs
Switching time
-2-
TSW
NJG1699MD7
TERMINAL INFORMATION
No.
SYMBOL
DESCRIPTION
1
GND
Ground terminal. Please connect this terminal with ground plane as close as
possible for excellent RF performance.
2
PC
RF input/output port. No DC blocking capacitor is required for this port
because of internal capacitor.
3
VDD
Positive voltage supply terminal. The positive voltage (+1.5~+4.5V) has to be
supplied. Please connect a bypass capacitor with GND terminal for excellent
RF performance.
4
GND
Ground terminal. Please connect this terminal with ground plane as close as
possible for excellent RF performance.
5
P4
RF input / output port. External capacitor is required to block the DC bias
voltage of internal circuit.
6
GND
Ground terminal. Please connect this terminal with ground plane as close as
possible for excellent RF performance.
7
P3
RF input / output port. External capacitor is required to block the DC bias
voltage of internal circuit.
8
GND
Ground terminal. Please connect this terminal with ground plane as close as
possible for excellent RF performance.
9
VCTL2
Control signal input terminal. This terminal is set to High-Level (+1.35~+4.5V)
or Low-Level (0~+0.45V).
10
VCTL1
Control signal input terminal. This terminal is set to High-Level (+1.35~+4.5V)
or Low-Level (0~+0.45V).
11
GND
Ground terminal. Please connect this terminal with ground plane as close as
possible for excellent RF performance.
12
P2
RF input / output port. External capacitor is required to block the DC bias
voltage of internal circuit.
13
GND
Ground terminal. Please connect this terminal with ground plane as close as
possible for excellent RF performance.
14
P1
RF input / output port. External capacitor is required to block the DC bias
voltage of internal circuit.
Exposed
Pad
GND
Ground terminal.
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NJG1699MD7
ELECTRICAL CHARACTERISTICS (With Application circuit, Loss of external circuit are excluded)
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NJG1699MD7
ELECTRICAL CHARACTERISTICS (With Application circuit, Loss of external circuit are excluded)
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NJG1699MD7
ELECTRICAL CHARACTERISTICS (With Application circuit, Loss of external circuit are excluded)
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NJG1699MD7
ELECTRICAL CHARACTERISTICS (With Application circuit, Loss of external circuit are excluded)
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NJG1699MD7
ELECTRICAL CHARACTERISTICS (With Application circuit, Loss of external circuit are excluded)
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NJG1699MD7
ELECTRICAL CHARACTERISTICS (With Application circuit, Loss of external circuit are excluded)
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NJG1699MD7
ELECTRICAL CHARACTERISTICS (With Application circuit, Loss of external circuit are excluded)
- 10 -
NJG1699MD7
APPLICATION CIRCUIT
P1
P2
56pF
56pF
14
PC
13
12
1
11
2
10
0/1.8V
3
2.7V
9
1000pF
0/1.8V
DECODER
4
5
6
8
7
56pF
56pF
P4
P3
No external DC blocking capacitor at PC terminal is required because of the internal capacitor in IC.
PARTS LIST
Part ID
Value
Notes
C1~C4
56pF
MURATA (GRM15)
C5
1000pF
MURATA (GRM15)
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NJG1699MD7
VCTL1
VCTL2
APPLIED CIRCUIT BOARD EXAMPLES
(TOP VIEW)
P2
P3
C2
C3
C1
C4
VDD
C5
P1
PCB:
FR-4, t=0.2mm
Capacitor Size: 1005 (1.0 x 0.5 mm)
Strip Line Width: 0.4mm
PCB Size:
25.8 x 25.8mm
Through Hole Diameter: 0.2mm
Losses of PCB, capacitors and connectors
Paths
P4
PC-P1
PC-P2
PC-P3
PC-P4
Frequency
(GHz)
1.0
2.0
Loss
(dB)
0.31
0.44
2.7
0.55
PC
<PCB LAYOUT GUIDELINE>
PCB
PKG Terminal
PKG Outline
GND Via Hole
Diameter φ= 0.2mm
PRECAUTIONS
[1] The DC current at RF ports must be equal to zero, which can be achieved with DC blocking capacitors
(C1~C4).
(However, in case there is no possibility that DC current flows, the DC blocking capacitors are unnecessary, i.e. the
RF signals are fed by SAW filters that block DC current by nature, etc.)
[2] To reduce stripline influence on RF characteristics, please locate the bypass capacitor (C5) close to VDD
terminal.
[3] For good isolation, the GND terminals must be connected to the PCB ground plane of substrate, and the
through-holes connecting the backside ground plane should be placed near by the pin connection.
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NJG1699MD7
RECOMMENDED FOOTPRINT PATTERN (EQFN14-D7 PACKAGE Reference)
:Land
:Mask (Open area) *Metal mask thickness : 100um
PKG:
1.6mm x 1.6mm
Pin pitch: 0.4mm
:Resist(Open area)
Detail A
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NJG1699MD7
PACKAGE OUTLINE (EQFN14-D7)
Units
Board
Terminal treat
Molding material
Weight
: mm
: Cu
: SnBi
: Epoxy resin
: 3.4mg
Exposed PAD
Ground connection is required.
Cautions on using this product
This product contains Gallium-Arsenide (GaAs) which is a harmful material.
• Do NOT eat or put into mouth.
• Do NOT dispose in fire or break up this product.
• Do NOT chemically make gas or powder with this product.
• To waste this product, please obey the relating law of your country.
This product may be damaged with electric static discharge (ESD) or spike voltage. Please handle
with care to avoid these damages.
- 14 -
[CAUTION]
The specifications on this databook are only
given for information , without any guarantee
as regards either mistakes or omissions. The
application circuits in this databook are
described only to show representative usages
of the product and not intended for the
guarantee or permission of any right including
the industrial rights.