The very best design for design in 74 GHz Series Logic

74 GHz Series Logic
INDEX PAGE
The very best design for design in
03/27/07
The world fastest 74 Series GHz Logic
PO74G00A
1.125GHz QUADRUPLE 2-INPUT POSITIVE-NAND GATE
PO74G02A
900MHz QUADRUPLE 2-INPUT POSITIVE-NOR GATE
PO74G04A
1.125GHz HEX INVERTER
PO74GU04A 1.125GHz HEX INVERTER
PO74G08A
1.125GHz QUADRUPLE 2-INPUT POSITIVE-AND GATES
PO74G10A
1GHz TRIPLE 3-INPUT POSITIVE-NAND GATES
PO74G27A
800MHz TRIPLE 3-INPUT POSITIVE-NOR GATE
PO74G32A
1.125GHz QUADRUPLE 2-INPUT POSITIVE-OR GATES
PO74G74A
600MHz DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS
PO74G86A
1.125GHz QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES
PO74G125A 1.125GHz QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS
PO74G126A 1.125GHz QUADRUPLE BUS BUFFER GATE
PO74G139A
1.125GHz DUAL 2-LINE TO 4-LINE DECODER/ DEMULTIPLEXER
GHz Translator
PO100HSTL22A
1.65GHz Dual LVTTL/LVCMOS to Differential HSTL Translator
PO100HSTL23A
1GHz Dual Differential HSTL/LVDS to LVTTL Translator
All 74 Series Logic are Pin to Pin & Package to Package Compatible with TI, Philips, Toshiba, fairchild etc.
Copyright © 2005-2007, Potato Semiconductor Corporation
PO74G00A
QUADRUPLE 2-INPUT POSITIVE-NAND GATE
07/26/06
74 GHz Series Logic
DESCRIPTION:
FEATURES:
. Patented technology
. Operating frequency up to 1.125GHz with 2pf load
. Operating frequency up to 750MHz with 5pf load
. Operating frequency up to 350MHz with 15pf load
. VCC Operates from 1.65V to 3.6V
. Propagation delay < 1.5ns max with 15pf load
. Low input capacitance: 4pf typical
. Available in 14pin 150mil wide SOIC package
Potato Semiconductor’s PO74G00A is designed for
world top performance using submicron CMOS
technology to achieve 1.125GHz TTL/CMOS output
frequency with less than 1.5ns propagation delay.
This quadruple 2-input positive-NAND gate is
designed for 1.65-V to 3.6-V VCC operation.
The PO74G00A performs the Boolean function
Y= A · B or Y= A + B in positive logic.
Inputs can be driven from either 3.3V or 5V devices.
This feature allows the use of these devices as
translators in a mixed 3.3V/5V system environment.
Pin Configuration
Logic Block Diagram
1A
1
14
V CC
1B
2
13
4B
1Y
3
12
4A
A
2A
4
11
4Y
B
2B
5
10
3B
2Y
6
9
3A
GND
7
8
3Y
Y
Pin Description
INPUTS
OUTPUT
Y
A
B
H
H
L
L
X
H
X
L
H
1
Copyright © 2005-2006, Potato Semiconductor Corporation
PO74G00A
QUADRUPLE 2-INPUT POSITIVE-NAND GATE
07/26/06
74 GHz Series Logic
Maximum Ratings
Description
Max
Unit
Storage Temperature
-65 to 150
°C
Operation Temperature
-40 to 85
°C
Operation Voltage
-0.5 to +4.6
V
Input Voltage
-0.5 to +5.5
V
Output Voltage
-0.5 to Vcc+0.5
V
Note:
stresses greater than listed under
Maximum
Ratings
may
cause
permanent damage to the device. This
is a stress rating only and functional
operation of the device at these or any
other conditions above those indicated
in the operational sections of this
specification is not implied. Exposure
to absolute maximum rating conditions
for extended periods may affect
reliability specification is not implied.
DC Electrical Characteristics
Symbol
Description
VOH
Output High voltage
VOL
Test Conditions
Min
Typ
Max
Unit
Vcc=3V Vin=VIH or VIL, IOH= -12mA
2.4
3
-
V
Output Low voltage
Vcc=3V Vin=VIH or VIL, IOH=12mA
-
0.3
0.5
V
VIH
Input High voltage
Guaranteed Logic HIGH Level (Input Pin)
2
-
5.5
V
VIL
Input Low voltage
Guaranteed Logic LOW Level (Input Pin)
-0.5
-
0.8
V
IIH
Input High current
Vcc = 3.6V and Vin = 5.5V
-
-
50
uA
IIL
Input Low current
Vcc = 3.6V and Vin = 0V
-
-
-50
uA
VIK
Clamp diode voltage
Vcc = Min. And IIN = -18mA
-
-0.7
-1.2
V
Notes:
1.
2.
3.
4.
5.
For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
Typical values are at Vcc = 3.3V, 25 °C ambient.
This parameter is guaranteed but not tested.
Not more than one output should be shorted at one time. Duration of the test should not exceed one second.
VoH = Vcc – 0.6V at rated current
2
Copyright © 2005-2006, Potato Semiconductor Corporation
PO74G00A
QUADRUPLE 2-INPUT POSITIVE-NAND GATE
07/27/06
74 GHz Series Logic
Power Supply Characteristics
Symbol
Description
Test Conditions (1)
Min
Typ
Max
Unit
IccQ
Quiescent Power Supply Current
Vcc=Max, Vin=Vcc or GND
-
0.1
30
uA
∆Icc
Power Supply Current per Input High
Vcc=Max, Vin= Vcc-0.6V
-
50
300
uA
Notes:
1.
2.
3.
4.
5.
For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
Typical values are at Vcc = 3.3V, 25°C ambient.
This parameter is guaranteed but not tested.
Not more than one output should be shorted at one time. Duration of the test should not exceed one second.
VoH = Vcc – 0.6V at rated current
Capacitance
Parameters (1)
Cin
Cout
Description
Test Conditions
Typ
Unit
Input Capacitance
Vin = 0V
4
pF
Output Capacitance
Vout = 0V
6
pF
Test Conditions (1)
M ax
Unit
Notes:
1 This parameter is determined by device characterization but not production tested.
Switching Characteristics
Symbol
Description
tPLH
Propagation Delay A, B to Y
CL = 15pF
1.5
ns
tPHL
Propagation Delay A, B to Y
CL = 15pF
1.5
ns
tr/tf
Rise/Fall Time
0.8V – 2.0V
0.8
ns
fmax
Input Frequency
CL =15pF
350
MHz
fmax
Input Frequency
CL = 5pF
750
MHz
fmax
Input Frequency
CL = 2pF
1125
MHz
Notes:
1. See test circuits and waveforms.
2. tpLH, tpHL, tsk(p), and tsk(o) are production tested. All other parameters guaranteed but not production tested.
3. Airflow of 1m/s is recommended for frequencies above 133MHz
3
Copyright © 2005-2006, Potato Semiconductor Corporation
PO74G00A
QUADRUPLE 2-INPUT POSITIVE-NAND GATE
07/26/06
74 GHz Series Logic
Test Waveforms
Propagation Delay
3V
1.5V
Input
0V
tPHL
tPLH
VoH
2.0V
1.5V
0.8V
VoL
Output
tf
tR
Test Circuit
Vcc
Pulse
Generator
50Ω
D.U.T.
15pF
to
2pF
4
Copyright © 2005-2006, Potato Semiconductor Corporation
PO74G00A
QUADRUPLE 2-INPUT POSITIVE-NAND GATE
07/26/06
74 GHz Series Logic
Packaging Mechanical Drawing: 14 pin 150mil SOIC
0.244 6.20
0.228 5.80
0.010
0.007
0.050 1.27
0.016 0.40
0.25
0.17
X.XX Denotes dimensions in inches
X.XX
X.XX
Denotes dimensions in millimenters
X.XX
5
Copyright © 2005-2006, Potato Semiconductor Corporation
PO74G00A
QUADRUPLE 2-INPUT POSITIVE-NAND GATE
07/27/06
74 GHz Series Logic
Ordering Information
Ordering Code
Package
Top-Marking
TA
PO74G00ASU
14pin SOIC
Tube
Pb-free & Green
PO74G00AS
-40°C to 85°C
PO74G00ASR
14pin SOIC
Tape and reel
Pb-free & Green
PO74G00AS
-40°C to 85°C
6
Copyright © 2005-2006, Potato Semiconductor Corporation
PO74G02A
QUADRUPLE 2-INPUT POSITIVE-NOR GATES
02/06/07
74 GHz Series Logic
DESCRIPTION:
FEATURES:
. Patented technology
. Operating frequency up to 900MHz with 2pf load
. Operating frequency up to 700MHz with 5pf load
. Operating frequency up to 400MHz with 15pf load
. VCC Operates from 1.65V to 3.6V
. Propagation delay < 1.5ns max with 15pf load
. Low input capacitance: 4pf typical
. Available in 14pin 150mil wide SOIC package
Potato Semiconductor’s PO74G02A is designed for
world top performance using submicron CMOS
technology to achieve 900MHz TTL /CMOS output
frequency with less than 1.5ns propagation delay.
This quadruple 2-input positive-NOR gate is designed
for 1.65-V to 3.6-V VCC operation.
The PO74G02A performs the Boolean function
Y= A + B or Y= A · B in positive logic.
Inputs can be driven from either 3.3V or 5V devices.
This feature allows the use of these devices as
translators in a mixed 3.3V/5V system environment.
Pin Configuration
1Y
1A
1B
2Y
2A
2B
GND
1
14
2
13
3
12
4
11
5
10
6
9
7
8
Logic Block Diagram
VCC
4Y
4B
4A
3Y
3B
3A
A
B
Y
Pin Description
INPUTS
A
B
OUTPUT
Y
H
X
L
X
H
L
L
L
H
1
Copyright © Potato Semiconductor Corporation
PO74G02A
QUADRUPLE 2-INPUT POSITIVE-NOR GATES
02/06/07
74 GHz Series Logic
Maximum Ratings
Description
Max
Unit
Storage Temperature
-65 to 150
°C
Operation Temperature
-40 to 85
°C
Operation Voltage
-0.5 to +4.6
V
Input Voltage
-0.5 to +5.5
V
Output Voltage
-0.5 to Vcc+0.5
V
Note:
stresses greater than listed under
Maximum
Ratings
may
cause
permanent damage to the device. This
is a stress rating only and functional
operation of the device at these or any
other conditions above those indicated
in the operational sections of this
specification is not implied. Exposure
to absolute maximum rating conditions
for extended periods may affect
reliability specification is not implied.
DC Electrical Characteristics
Symbol
Description
VOH
Output High voltage
VOL
Test Conditions
Min
Typ
Max
Unit
Vcc=3V Vin=VIH or VIL, IOH= -12mA
2.4
3
-
V
Output Low voltage
Vcc=3V Vin=VIH or VIL, IOH=12mA
-
0.3
0.5
V
VIH
Input High voltage
Guaranteed Logic HIGH Level (Input Pin)
2
-
5.5
V
VIL
Input Low voltage
Guaranteed Logic LOW Level (Input Pin)
-0.5
-
0.8
V
IIH
Input High current
Vcc = 3.6V and Vin = 5.5V
-
-
1
uA
IIL
Input Low current
Vcc = 3.6V and Vin = 0V
-
-
-1
uA
VIK
Clamp diode voltage
Vcc = Min. And IIN = -18mA
-
-0.7
-1.2
V
Notes:
1.
2.
3.
4.
5.
For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
Typical values are at Vcc = 3.3V, 25 °C ambient.
This parameter is guaranteed but not tested.
Not more than one output should be shorted at one time. Duration of the test should not exceed one second.
VoH = Vcc – 0.6V at rated current
2
Copyright © Potato Semiconductor Corporation
PO74G02A
QUADRUPLE 2-INPUT POSITIVE-NOR GATES
02/06/07
74 GHz Series Logic
Power Supply Characteristics
Symbol
Description
Test Conditions (1)
Min
Typ
Max
Unit
IccQ
Quiescent Power Supply Current
Vcc=Max, Vin=Vcc or GND
-
0.1
30
uA
∆Icc
Power Supply Current per Input High
Vcc=Max, Vin= Vcc-0.6V
-
50
300
uA
Notes:
1.
2.
3.
4.
5.
For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
Typical values are at Vcc = 3.3V, 25°C ambient.
This parameter is guaranteed but not tested.
Not more than one output should be shorted at one time. Duration of the test should not exceed one second.
VoH = Vcc – 0.6V at rated current
Capacitance
Parameters (1)
Cin
Cout
Description
Test Conditions
Typ
Unit
Input Capacitance
Vin = 0V
4
pF
Output Capacitance
Vout = 0V
6
pF
Test Conditions (1)
M ax
Unit
Notes:
1 This parameter is determined by device characterization but not production tested.
Switching Characteristics
Symbol
Description
tPLH
Propagation Delay A, B to Y
CL = 15pF
1.5
ns
tPHL
Propagation Delay A, B to Y
CL = 15pF
1.5
ns
tr/tf
Rise/Fall Time
0.8V – 2.0V
0.8
ns
fmax
Input Frequency
CL =15pF
400
MHz
fmax
Input Frequency
CL = 5pF
700
MHz
fmax
Input Frequency
CL = 2pF
900
MHz
Notes:
1. See test circuits and waveforms.
2. tpLH, tpHL, tsk(p), and tsk(o) are production tested. All other parameters guaranteed but not production tested.
3. Airflow of 1m/s is recommended for frequencies above 133MHz
3
Copyright © Potato Semiconductor Corporation
PO74G02A
QUADRUPLE 2-INPUT POSITIVE-NOR GATES
02/06/07
74 GHz Series Logic
Test Waveforms
Propagation Delay
3V
1.5V
Input
0V
tPHL
tPLH
VoH
2.0V
1.5V
0.8V
VoL
Output
tf
tR
Test Circuit
Vcc
Pulse
Generator
50Ω
D.U.T.
15pF
to
2pF
4
Copyright © Potato Semiconductor Corporation
PO74G02A
QUADRUPLE 2-INPUT POSITIVE-NOR GATES
02/06/07
74 GHz Series Logic
Packaging Mechanical Drawing: 14 pin 150mil SOIC
0.244 6.20
0.228 5.80
0.010
0.007
0.050 1.27
0.016 0.40
0.25
0.17
X.XX Denotes dimensions in inches
X.XX
X.XX
Denotes dimensions in millimenters
X.XX
5
Copyright © 2005-2006, Potato Semiconductor Corporation
PO74G02A
QUADRUPLE 2-INPUT POSITIVE-NOR GATES
02/06/07
74 GHz Series Logic
Ordering Information
Ordering Code
Package
Top-Marking
TA
PO74G02ASU
14pin SOIC
Tube
Pb-free & Green
PO74G02AS
-40°C to 85°C
PO74G02ASR
14pin SOIC
Tape and reel
Pb-free & Green
PO74G02AS
-40°C to 85°C
6
Copyright © Potato Semiconductor Corporation
PO74G04A
HEX INVERTER
07/26/06
74 GHz Series Logic
FEATURES:
DESCRIPTION:
. Patented technology
. Operating frequency up to 1.125GHz with 2pf load
. Operating frequency up to 700MHz with 5pf load
. Operating frequency up to 270MHz with 15pf load
. VCC Operates from 1.65V to 3.6V
. Propagation delay < 1.4ns max with 15pf load
. Low input capacitance: 4pf typical
. Available in 14pin 150mil wide SOIC package
Potato Semiconductor’s PO74G04A is designed for
world top performance using submicron CMOS
technology to achieve 1.125GHz TTL /CMOS output
frequency with less than 1.4ns propagation delay.
This hex inverter contains six independent inverters
designed for 1.65-V to 3.6-V VCC operation.
The PO74U04A performs the Boolean function Y= A.
Inputs can be driven from either 3.3V or 5V devices.
This feature allows the use of these devices as
translators in a mixed 3.3V/5V system environment.
Pin Configuration
Logic Block Diagram
1A
1
14
V CC
1Y
2
13
6A
2A
3
12
6Y
2Y
4
11
5A
3A
5
10
5Y
3Y
6
9
4A
GND
7
8
4Y
A
Y
Pin Description
INPUT
A
OUTPUT
Y
H
L
L
H
1
Copyright © 2005-2006, Potato Semiconductor Corporation
PO74G04A
HEX INVERTER
07/26/06
74 GHz Series Logic
Maximum Ratings
Description
Max
Unit
Storage Temperature
-65 to 150
°C
Operation Temperature
-40 to 85
°C
Operation Voltage
-0.5 to +4.6
V
Input Voltage
-0.5 to +5.5
V
Output Voltage
-0.5 to Vcc+0.5
V
Note:
stresses greater than listed under
Maximum
Ratings
may
cause
permanent damage to the device. This
is a stress rating only and functional
operation of the device at these or any
other conditions above those indicated
in the operational sections of this
specification is not implied. Exposure
to absolute maximum rating conditions
for extended periods may affect
reliability specification is not implied.
DC Electrical Characteristics
Symbol
Description
VOH
Output High voltage
VOL
Test Conditions
Min
Typ
Max
Unit
Vcc=3V Vin=VIH or VIL, IOH= -12mA
2.4
3
-
V
Output Low voltage
Vcc=3V Vin=VIH or VIL, IOH=12mA
-
0.3
0.5
V
VIH
Input High voltage
Guaranteed Logic HIGH Level (Input Pin)
2
-
5.5
V
VIL
Input Low voltage
Guaranteed Logic LOW Level (Input Pin)
-0.5
-
0.8
V
IIH
Input High current
Vcc = 3.6V and Vin = 5.5V
-
-
50
uA
IIL
Input Low current
Vcc = 3.6V and Vin = 0V
-
-
-50
uA
VIK
Clamp diode voltage
Vcc = Min. And IIN = -18mA
-
-0.7
-1.2
V
Notes:
1.
2.
3.
4.
5.
For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
Typical values are at Vcc = 3.3V, 25 °C ambient.
This parameter is guaranteed but not tested.
Not more than one output should be shorted at one time. Duration of the test should not exceed one second.
VoH = Vcc – 0.6V at rated current
2
Copyright © 2005-2006, Potato Semiconductor Corporation
PO74G04A
HEX INVERTER
07/27/06
74 GHz Series Logic
Power Supply Characteristics
Symbol
Description
Test Conditions (1)
Min
Typ
Max
Unit
IccQ
Quiescent Power Supply Current
Vcc=Max, Vin=Vcc or GND
-
0.1
30
uA
∆Icc
Power Supply Current per Input High
Vcc=Max, Vin= Vcc-0.6V
-
50
300
uA
Notes:
1.
2.
3.
4.
5.
For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
Typical values are at Vcc = 3.3V, 25°C ambient.
This parameter is guaranteed but not tested.
Not more than one output should be shorted at one time. Duration of the test should not exceed one second.
VoH = Vcc – 0.6V at rated current
Capacitance
Parameters (1)
Cin
Cout
Description
Test Conditions
Typ
Unit
Input Capacitance
Vin = 0V
4
pF
Output Capacitance
Vout = 0V
6
pF
Test Conditions (1)
M ax
Unit
Notes:
1 This parameter is determined by device characterization but not production tested.
Switching Characteristics
Symbol
Description
tPLH
Propagation Delay A, B to Y
CL = 15pF
1.4
ns
tPHL
Propagation Delay A, B to Y
CL = 15pF
1.4
ns
tr/tf
Rise/Fall Time
0.8V – 2.0V
0.8
ns
fmax
Input Frequency
CL =15pF
270
MHz
fmax
Input Frequency
CL = 5pF
700
MHz
fmax
Input Frequency
CL = 2pF
1125
MHz
Notes:
1. See test circuits and waveforms.
2. tpLH, tpHL, tsk(p), and tsk(o) are production tested. All other parameters guaranteed but not production tested.
3. Airflow of 1m/s is recommended for frequencies above 133MHz
3
Copyright © 2005-2006, Potato Semiconductor Corporation
PO74G04A
HEX INVERTER
07/26/06
74 GHz Series Logic
Test Waveforms
Propagation Delay
3V
1.5V
Input
0V
tPHL
tPLH
VoH
2.0V
1.5V
0.8V
VoL
Output
tf
tR
Test Circuit
Vcc
Pulse
Generator
50Ω
D.U.T.
15pF
to
2pF
4
Copyright © 2005-2006, Potato Semiconductor Corporation
PO74G04A
HEX INVERTER
07/26/06
74 GHz Series Logic
Packaging Mechanical Drawing: 14 pin 150mil SOIC
0.244 6.20
0.228 5.80
0.010
0.007
0.050 1.27
0.016 0.40
0.25
0.17
X.XX Denotes dimensions in inches
X.XX
X.XX
Denotes dimensions in millimenters
X.XX
5
Copyright © 2005-2006, Potato Semiconductor Corporation
PO74G04A
HEX INVERTER
07/27/06
74 GHz Series Logic
Ordering Information
Ordering Code
Package
Top-Marking
TA
PO74G04ASU
14pin SOIC
Tube
Pb-free & Green
PO74G04AS
-40°C to 85°C
PO74G04ASR
14pin SOIC
Tape and reel
Pb-free & Green
PO74G04AS
-40°C to 85°C
6
Copyright © 2005-2006, Potato Semiconductor Corporation
PO74GU04A
HEX INVERTER
07/26/06
74 GHz Series Logic
FEATURES:
DESCRIPTION:
. Patented technology
. Operating frequency up to 1.125GHz with 2pf load
. Operating frequency up to 700MHz with 5pf load
. Operating frequency up to 270MHz with 15pf load
. VCC Operates from 1.65V to 3.6V
. Propagation delay < 1.4ns max with 15pf load
. Low input capacitance: 4pf typical
. Available in 14pin 150mil wide SOIC package
Potato Semiconductor’s PO74GU04A is designed for
world top performance using submicron CMOS
technology to achieve 1.125GHz TTL /CMOS output
frequency with less than 1.4ns propagation delay.
This hex inverter contains six independent inverters
designed for 1.65-V to 3.6-V VCC operation.
The PO74GU04A performs the Boolean function Y= A.
Inputs can be driven from either 3.3V or 5V devices.
This feature allows the use of these devices as
translators in a mixed 3.3V/5V system environment.
Pin Configuration
Logic Block Diagram
1A
1
14
V CC
1Y
2
13
6A
2A
3
12
6Y
2Y
4
11
5A
3A
5
10
5Y
3Y
6
9
4A
GND
7
8
4Y
A
Y
Pin Description
INPUT
A
OUTPUT
Y
H
L
L
H
1
Copyright © 2005-2006, Potato Semiconductor Corporation
PO74GU04A
HEX INVERTER
07/26/06
74 GHz Series Logic
Maximum Ratings
Description
Max
Unit
Storage Temperature
-65 to 150
°C
Operation Temperature
-40 to 85
°C
Operation Voltage
-0.5 to +4.6
V
Input Voltage
-0.5 to +5.5
V
Output Voltage
-0.5 to Vcc+0.5
V
Note:
stresses greater than listed under
Maximum
Ratings
may
cause
permanent damage to the device. This
is a stress rating only and functional
operation of the device at these or any
other conditions above those indicated
in the operational sections of this
specification is not implied. Exposure
to absolute maximum rating conditions
for extended periods may affect
reliability specification is not implied.
DC Electrical Characteristics
Symbol
Description
VOH
Output High voltage
VOL
Test Conditions
Min
Typ
Max
Unit
Vcc=3V Vin=VIH or VIL, IOH= -12mA
2.4
3
-
V
Output Low voltage
Vcc=3V Vin=VIH or VIL, IOH=12mA
-
0.3
0.5
V
VIH
Input High voltage
Guaranteed Logic HIGH Level (Input Pin)
2
-
5.5
V
VIL
Input Low voltage
Guaranteed Logic LOW Level (Input Pin)
-0.5
-
0.8
V
IIH
Input High current
Vcc = 3.6V and Vin = 5.5V
-
-
50
uA
IIL
Input Low current
Vcc = 3.6V and Vin = 0V
-
-
-50
uA
VIK
Clamp diode voltage
Vcc = Min. And IIN = -18mA
-
-0.7
-1.2
V
Notes:
1.
2.
3.
4.
5.
For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
Typical values are at Vcc = 3.3V, 25 °C ambient.
This parameter is guaranteed but not tested.
Not more than one output should be shorted at one time. Duration of the test should not exceed one second.
VoH = Vcc – 0.6V at rated current
2
Copyright © 2005-2006, Potato Semiconductor Corporation
PO74GU04A
HEX INVERTER
07/27/06
74 GHz Series Logic
Power Supply Characteristics
Symbol
Description
Test Conditions (1)
Min
Typ
Max
Unit
IccQ
Quiescent Power Supply Current
Vcc=Max, Vin=Vcc or GND
-
0.1
30
uA
∆Icc
Power Supply Current per Input High
Vcc=Max, Vin= Vcc-0.6V
-
50
300
uA
Notes:
1.
2.
3.
4.
5.
For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
Typical values are at Vcc = 3.3V, 25°C ambient.
This parameter is guaranteed but not tested.
Not more than one output should be shorted at one time. Duration of the test should not exceed one second.
VoH = Vcc – 0.6V at rated current
Capacitance
Parameters (1)
Cin
Cout
Description
Test Conditions
Typ
Unit
Input Capacitance
Vin = 0V
4
pF
Output Capacitance
Vout = 0V
6
pF
Test Conditions (1)
M ax
Unit
Notes:
1 This parameter is determined by device characterization but not production tested.
Switching Characteristics
Symbol
Description
tPLH
Propagation Delay A, B to Y
CL = 15pF
1.4
ns
tPHL
Propagation Delay A, B to Y
CL = 15pF
1.4
ns
tr/tf
Rise/Fall Time
0.8V – 2.0V
0.8
ns
fmax
Input Frequency
CL =15pF
270
MHz
fmax
Input Frequency
CL = 5pF
700
MHz
fmax
Input Frequency
CL = 2pF
1125
MHz
Notes:
1. See test circuits and waveforms.
2. tpLH, tpHL, tsk(p), and tsk(o) are production tested. All other parameters guaranteed but not production tested.
3. Airflow of 1m/s is recommended for frequencies above 133MHz
3
Copyright © 2005-2006, Potato Semiconductor Corporation
PO74GU04A
HEX INVERTER
07/26/06
74 GHz Series Logic
Test Waveforms
Propagation Delay
3V
1.5V
Input
0V
tPHL
tPLH
VoH
2.0V
1.5V
0.8V
VoL
Output
tf
tR
Test Circuit
Vcc
Pulse
Generator
50Ω
D.U.T.
15pF
to
2pF
4
Copyright © 2005-2006, Potato Semiconductor Corporation
PO74GU04A
HEX INVERTER
07/26/06
74 GHz Series Logic
Packaging Mechanical Drawing: 14 pin 150mil SOIC
0.244 6.20
0.228 5.80
0.010
0.007
0.050 1.27
0.016 0.40
0.25
0.17
X.XX Denotes dimensions in inches
X.XX
X.XX
Denotes dimensions in millimenters
X.XX
5
Copyright © 2005-2006, Potato Semiconductor Corporation
PO74GU04A
HEX INVERTER
07/27/06
74 GHz Series Logic
Ordering Information
Ordering Code
Package
Top-Marking
TA
PO74GU04ASU
14pin SOIC
Tube
Pb-free & Green
PO74GU04AS
-40°C to 85°C
PO74GU04ASR
14pin SOIC
Tape and reel
Pb-free & Green
PO74GU04AS
-40°C to 85°C
6
Copyright © 2005-2006, Potato Semiconductor Corporation
PO74G08A
QUADRUPLE 2-INPUT POSITIVE-AND GATES
07/25/06
74 GHz Series Logic
FEATURES:
DESCRIPTION:
. Patented technology
. Operating frequency up to 1.125GHz with 2pf load
. Operating frequency up to 750MHz with 5pf load
. Operating frequency up to 350MHz with 15pf load
. VCC Operates from 1.65V to 3.6V
. Propagation delay < 1.5ns max with 15pf load
. Low input capacitance: 4pf typical
. Available in 14pin 150mil wide SOIC package
Potato Semiconductor’s PO74G08A is designed for
world top performance using submicron CMOS
technology to achieve 1.125GHz TTL /CMOS output
frequency with less than 1.5ns propagation delay.
This quadruple 2-input positive-AND gate is designed
for 1.65-V to 3.6-V VCC operation.
The PO74G08A performs the Boolean function
Y= A · B or Y= A + B in positive logic.
Inputs can be driven from either 3.3V or 5V devices.
This feature allows the use of these devices as translators in a mixed 3.3V/5V system environment.
Pin Configuration
Logic Block Diagram
1A
1
14
V CC
1B
2
13
4B
1Y
3
12
4A
2A
4
11
4Y
2B
5
10
3B
2Y
6
9
3A
7
8
3Y
GND
A
B
Y
Pin Description
INPUTS
A
B
OUTPUT
Y
H
H
H
L
X
L
X
L
L
1
Copyright © 2005-2006, Potato Semiconductor Corporation
PO74G08A
QUADRUPLE 2-INPUT POSITIVE-AND GATES
07/26/06
74 GHz Series Logic
Maximum Ratings
Description
Max
Unit
Storage Temperature
-65 to 150
°C
Operation Temperature
-40 to 85
°C
Operation Voltage
-0.5 to +4.6
V
Input Voltage
-0.5 to +5.5
V
Output Voltage
-0.5 to Vcc+0.5
V
Note:
stresses greater than listed under
Maximum
Ratings
may
cause
permanent damage to the device. This
is a stress rating only and functional
operation of the device at these or any
other conditions above those indicated
in the operational sections of this
specification is not implied. Exposure
to absolute maximum rating conditions
for extended periods may affect
reliability specification is not implied.
DC Electrical Characteristics
Symbol
Description
VOH
Output High voltage
VOL
Test Conditions
Min
Typ
Max
Unit
Vcc=3V Vin=VIH or VIL, IOH= -12mA
2.4
3
-
V
Output Low voltage
Vcc=3V Vin=VIH or VIL, IOH=12mA
-
0.3
0.5
V
VIH
Input High voltage
Guaranteed Logic HIGH Level (Input Pin)
2
-
5.5
V
VIL
Input Low voltage
Guaranteed Logic LOW Level (Input Pin)
-0.5
-
0.8
V
IIH
Input High current
Vcc = 3.6V and Vin = 5.5V
-
-
50
uA
IIL
Input Low current
Vcc = 3.6V and Vin = 0V
-
-
-50
uA
VIK
Clamp diode voltage
Vcc = Min. And IIN = -18mA
-
-0.7
-1.2
V
Notes:
1.
2.
3.
4.
5.
For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
Typical values are at Vcc = 3.3V, 25 °C ambient.
This parameter is guaranteed but not tested.
Not more than one output should be shorted at one time. Duration of the test should not exceed one second.
VoH = Vcc – 0.6V at rated current
2
Copyright © 2005-2006, Potato Semiconductor Corporation
PO74G08A
QUADRUPLE 2-INPUT POSITIVE-AND GATES
07/27/06
74 GHz Series Logic
Power Supply Characteristics
Symbol
Description
Test Conditions (1)
Min
Typ
Max
Unit
IccQ
Quiescent Power Supply Current
Vcc=Max, Vin=Vcc or GND
-
0.1
30
uA
∆Icc
Power Supply Current per Input High
Vcc=Max, Vin= Vcc-0.6V
-
50
300
uA
Notes:
1.
2.
3.
4.
5.
For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
Typical values are at Vcc = 3.3V, 25°C ambient.
This parameter is guaranteed but not tested.
Not more than one output should be shorted at one time. Duration of the test should not exceed one second.
VoH = Vcc – 0.6V at rated current
Capacitance
Parameters (1)
Cin
Cout
Description
Test Conditions
Typ
Unit
Input Capacitance
Vin = 0V
4
pF
Output Capacitance
Vout = 0V
6
pF
Test Conditions (1)
M ax
Unit
Notes:
1 This parameter is determined by device characterization but not production tested.
Switching Characteristics
Symbol
Description
tPLH
Propagation Delay A, B to Y
CL = 15pF
1.5
ns
tPHL
Propagation Delay A, B to Y
CL = 15pF
1.5
ns
tr/tf
Rise/Fall Time
0.8V – 2.0V
0.8
ns
fmax
Input Frequency
CL =15pF
350
MHz
fmax
Input Frequency
CL = 5pF
750
MHz
fmax
Input Frequency
CL = 2pF
1125
MHz
Notes:
1. See test circuits and waveforms.
2. tpLH, tpHL, tsk(p), and tsk(o) are production tested. All other parameters guaranteed but not production tested.
3. Airflow of 1m/s is recommended for frequencies above 133MHz
3
Copyright © 2005-2006, Potato Semiconductor Corporation
PO74G08A
QUADRUPLE 2-INPUT POSITIVE-AND GATES
07/26/06
74 GHz Series Logic
Test Waveforms
Propagation Delay
3V
1.5V
Input
0V
tPLH
tPHL
VoH
2.0V
1.5V
0.8V
VoL
Output
tR
tf
Test Circuit
Vcc
Pulse
Generator
50Ω
D.U.T.
15pF
to
2pF
4
Copyright © 2005-2006, Potato Semiconductor Corporation
PO74G08A
QUADRUPLE 2-INPUT POSITIVE-AND GATES
07/26/06
74 GHz Series Logic
Packaging Mechanical Drawing: 14 pin 150mil SOIC
0.244 6.20
0.228 5.80
0.010
0.007
0.050 1.27
0.016 0.40
0.25
0.17
X.XX Denotes dimensions in inches
X.XX
X.XX
Denotes dimensions in millimenters
X.XX
5
Copyright © 2005-2006, Potato Semiconductor Corporation
PO74G08A
QUADRUPLE 2-INPUT POSITIVE-AND GATES
07/27/06
74 GHz Series Logic
Ordering Information
Ordering Code
Package
Top-Marking
TA
PO74G08ASU
14pin SOIC
Tube
Pb-free & Green
PO74G08AS
-40°C to 85°C
PO74G08ASR
14pin SOIC
Tape and reel
Pb-free & Green
PO74G08AS
-40°C to 85°C
6
Copyright © 2005-2006, Potato Semiconductor Corporation
PO74G10A
TRIPLE 3-INPUT POSITIVE-NAND GATES
02/06/07
74 GHz Series Logic
FEATURES:
DESCRIPTION:
. Patented technology
. Operating frequency up to 1GHz with 2pf load
. Operating frequency up to 800MHz with 5pf load
. Operating frequency up to 350MHz with 15pf load
. VCC Operates from 1.65V to 3.6V
. Propagation delay < 1.7ns max with 15pf load
. Low input capacitance: 4pf typical
. Available in 14pin 150mil wide SOIC package
Potato Semiconductor’s PO74G10A is designed for
world top performance using submicron CMOS
technology to achieve 1GHz TTL /CMOS output
frequency with less than 1.7ns propagation delay.
This quadruple 2-input positive-NOR gate is designed
for 1.65-V to 3.6-V VCC operation.
The PO74G10A performs the Boolean function
Y= A · B · C or Y= A + B + C in positive logic.
Inputs can be driven from either 3.3V or 5V devices.
This feature allows the use of these devices as
translators in a mixed 3.3V/5V system environment.
Pin Configuration
1A
1B
2A
2B
2C
2Y
GND
1
14
2
13
3
12
4
11
5
10
6
9
7
8
Logic Block Diagram
VCC
1C
1Y
3C
3B
3A
3Y
1A
1B
1C
1Y
2A
2B
2C
2Y
3A
3B
3C
3Y
Pin Description
INPUTS
A
B
C
OUTPUT
Y
H
H
H
L
L
X
X
H
X
L
X
H
X
L
X
H
1
Copyright © Potato Semiconductor Corporation
PO74G10A
TRIPLE 3-INPUT POSITIVE-NAND GATES
02/06/07
74 GHz Series Logic
Maximum Ratings
Description
Max
Unit
Storage Temperature
-65 to 150
°C
Operation Temperature
-40 to 85
°C
Operation Voltage
-0.5 to +4.6
V
Input Voltage
-0.5 to +5.5
V
Output Voltage
-0.5 to Vcc+0.5
V
Note:
stresses greater than listed under
Maximum
Ratings
may
cause
permanent damage to the device. This
is a stress rating only and functional
operation of the device at these or any
other conditions above those indicated
in the operational sections of this
specification is not implied. Exposure
to absolute maximum rating conditions
for extended periods may affect
reliability specification is not implied.
DC Electrical Characteristics
Symbol
Description
VOH
Output High voltage
VOL
Test Conditions
Min
Typ
Max
Unit
Vcc=3V Vin=VIH or VIL, IOH= -12mA
2.4
3
-
V
Output Low voltage
Vcc=3V Vin=VIH or VIL, IOH=12mA
-
0.3
0.5
V
VIH
Input High voltage
Guaranteed Logic HIGH Level (Input Pin)
2
-
5.5
V
VIL
Input Low voltage
Guaranteed Logic LOW Level (Input Pin)
-0.5
-
0.8
V
IIH
Input High current
Vcc = 3.6V and Vin = 5.5V
-
-
1
uA
IIL
Input Low current
Vcc = 3.6V and Vin = 0V
-
-
-1
uA
VIK
Clamp diode voltage
Vcc = Min. And IIN = -18mA
-
-0.7
-1.2
V
Notes:
1.
2.
3.
4.
5.
For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
Typical values are at Vcc = 3.3V, 25 °C ambient.
This parameter is guaranteed but not tested.
Not more than one output should be shorted at one time. Duration of the test should not exceed one second.
VoH = Vcc – 0.6V at rated current
2
Copyright © Potato Semiconductor Corporation
PO74G10A
TRIPLE 3-INPUT POSITIVE-NAND GATES
02/06/07
74 GHz Series Logic
Power Supply Characteristics
Symbol
Description
Test Conditions (1)
Min
Typ
Max
Unit
IccQ
Quiescent Power Supply Current
Vcc=Max, Vin=Vcc or GND
-
0.1
30
uA
∆Icc
Power Supply Current per Input High
Vcc=Max, Vin= Vcc-0.6V
-
50
300
uA
Notes:
1.
2.
3.
4.
5.
For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
Typical values are at Vcc = 3.3V, 25°C ambient.
This parameter is guaranteed but not tested.
Not more than one output should be shorted at one time. Duration of the test should not exceed one second.
VoH = Vcc – 0.6V at rated current
Capacitance
Parameters (1)
Cin
Cout
Description
Test Conditions
Typ
Unit
Input Capacitance
Vin = 0V
4
pF
Output Capacitance
Vout = 0V
6
pF
Test Conditions (1)
M ax
Unit
Notes:
1 This parameter is determined by device characterization but not production tested.
Switching Characteristics
Symbol
Description
tPLH
Propagation Delay A, B to Y
CL = 15pF
1.7
ns
tPHL
Propagation Delay A, B to Y
CL = 15pF
1.7
ns
tr/tf
Rise/Fall Time
0.8V – 2.0V
0.8
ns
fmax
Input Frequency
CL =15pF
350
MHz
fmax
Input Frequency
CL = 5pF
800
MHz
fmax
Input Frequency
CL = 2pF
1000
MHz
Notes:
1. See test circuits and waveforms.
2. tpLH, tpHL, tsk(p), and tsk(o) are production tested. All other parameters guaranteed but not production tested.
3. Airflow of 1m/s is recommended for frequencies above 133MHz
3
Copyright © Potato Semiconductor Corporation
PO74G10A
TRIPLE 3-INPUT POSITIVE-NAND GATES
02/06/07
74 GHz Series Logic
Test Waveforms
Propagation Delay
3V
1.5V
Input
0V
tPHL
tPLH
VoH
2.0V
1.5V
0.8V
VoL
Output
tf
tR
Test Circuit
Vcc
Pulse
Generator
50Ω
D.U.T.
15pF
to
2pF
4
Copyright © Potato Semiconductor Corporation
PO74G10A
TRIPLE 3-INPUT POSITIVE-NAND GATES
02/06/07
74 GHz Series Logic
Packaging Mechanical Drawing: 14 pin 150mil SOIC
0.244 6.20
0.228 5.80
0.010
0.007
0.050 1.27
0.016 0.40
0.25
0.17
X.XX Denotes dimensions in inches
X.XX
X.XX
Denotes dimensions in millimenters
X.XX
5
Copyright © 2005-2006, Potato Semiconductor Corporation
PO74G10A
TRIPLE 3-INPUT POSITIVE-NAND GATES
02/06/07
74 GHz Series Logic
Ordering Information
Ordering Code
Package
Top-Marking
TA
PO74G10ASU
14pin SOIC
Tube
Pb-free & Green
PO74G10AS
-40°C to 85°C
PO74G10ASR
14pin SOIC
Tape and reel
Pb-free & Green
PO74G10AS
-40°C to 85°C
6
Copyright © Potato Semiconductor Corporation
PO74G27A
TRIPLE 3-INPUT POSITIVE-NOR GATES
02/06/07
74 GHz Series Logic
FEATURES:
DESCRIPTION:
. Patented technology
. Operating frequency up to 800MHz with 2pf load
. Operating frequency up to 700MHz with 5pf load
. Operating frequency up to 400MHz with 15pf load
. VCC Operates from 1.65V to 3.6V
. Propagation delay < 1.7ns max with 15pf load
. Low input capacitance: 4pf typical
. Available in 14pin 150mil wide SOIC package
Potato Semiconductor’s PO74G27A is designed for
world top performance using submicron CMOS
technology to achieve 800MHz TTL /CMOS output
frequency with less than 1.7ns propagation delay.
This triple 3-input positive-NOR gate is designed for
1.65-V to 3.6-V VCC operation.
The PO74G27A performs the Boolean function
Y= A + B + C or Y= A · B · C in positive logic.
Inputs can be driven from either 3.3V or 5V devices.
This feature allows the use of these devices as
translators in a mixed 3.3V/5V system environment.
Pin Configuration
1A
1B
2A
2B
2C
2Y
GND
1
14
2
13
3
12
4
11
5
10
6
9
7
8
Logic Block Diagram
VCC
1C
1Y
3C
3B
3A
3Y
1A
1B
1C
1Y
2A
2B
2C
2Y
3A
3B
3C
3Y
Pin Description
INPUTS
A
B
C
OUTPUT
Y
H
X
X
L
X
H
X
L
X
X
H
L
L
L
L
H
1
Copyright © Potato Semiconductor Corporation
PO74G27A
TRIPLE 3-INPUT POSITIVE-NOR GATES
02/06/07
74 GHz Series Logic
Maximum Ratings
Description
Max
Unit
Storage Temperature
-65 to 150
°C
Operation Temperature
-40 to 85
°C
Operation Voltage
-0.5 to +4.6
V
Input Voltage
-0.5 to +5.5
V
Output Voltage
-0.5 to Vcc+0.5
V
Note:
stresses greater than listed under
Maximum
Ratings
may
cause
permanent damage to the device. This
is a stress rating only and functional
operation of the device at these or any
other conditions above those indicated
in the operational sections of this
specification is not implied. Exposure
to absolute maximum rating conditions
for extended periods may affect
reliability specification is not implied.
DC Electrical Characteristics
Symbol
Description
VOH
Output High voltage
VOL
Test Conditions
Min
Typ
Max
Unit
Vcc=3V Vin=VIH or VIL, IOH= -12mA
2.4
3
-
V
Output Low voltage
Vcc=3V Vin=VIH or VIL, IOH=12mA
-
0.3
0.5
V
VIH
Input High voltage
Guaranteed Logic HIGH Level (Input Pin)
2
-
5.5
V
VIL
Input Low voltage
Guaranteed Logic LOW Level (Input Pin)
-0.5
-
0.8
V
IIH
Input High current
Vcc = 3.6V and Vin = 5.5V
-
-
1
uA
IIL
Input Low current
Vcc = 3.6V and Vin = 0V
-
-
-1
uA
VIK
Clamp diode voltage
Vcc = Min. And IIN = -18mA
-
-0.7
-1.2
V
Notes:
1.
2.
3.
4.
5.
For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
Typical values are at Vcc = 3.3V, 25 °C ambient.
This parameter is guaranteed but not tested.
Not more than one output should be shorted at one time. Duration of the test should not exceed one second.
VoH = Vcc – 0.6V at rated current
2
Copyright © Potato Semiconductor Corporation
PO74G27A
TRIPLE 3-INPUT POSITIVE-NOR GATES
02/06/07
74 GHz Series Logic
Power Supply Characteristics
Symbol
Description
Test Conditions (1)
Min
Typ
Max
Unit
IccQ
Quiescent Power Supply Current
Vcc=Max, Vin=Vcc or GND
-
0.1
30
uA
∆Icc
Power Supply Current per Input High
Vcc=Max, Vin= Vcc-0.6V
-
50
300
uA
Notes:
1.
2.
3.
4.
5.
For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
Typical values are at Vcc = 3.3V, 25°C ambient.
This parameter is guaranteed but not tested.
Not more than one output should be shorted at one time. Duration of the test should not exceed one second.
VoH = Vcc – 0.6V at rated current
Capacitance
Parameters (1)
Cin
Cout
Description
Test Conditions
Typ
Unit
Input Capacitance
Vin = 0V
4
pF
Output Capacitance
Vout = 0V
6
pF
Test Conditions (1)
M ax
Unit
Notes:
1 This parameter is determined by device characterization but not production tested.
Switching Characteristics
Symbol
Description
tPLH
Propagation Delay A, B to Y
CL = 15pF
1.7
ns
tPHL
Propagation Delay A, B to Y
CL = 15pF
1.7
ns
tr/tf
Rise/Fall Time
0.8V – 2.0V
0.8
ns
fmax
Input Frequency
CL =15pF
400
MHz
fmax
Input Frequency
CL = 5pF
700
MHz
fmax
Input Frequency
CL = 2pF
800
MHz
Notes:
1. See test circuits and waveforms.
2. tpLH, tpHL, tsk(p), and tsk(o) are production tested. All other parameters guaranteed but not production tested.
3. Airflow of 1m/s is recommended for frequencies above 133MHz
3
Copyright © Potato Semiconductor Corporation
PO74G27A
TRIPLE 3-INPUT POSITIVE-NOR GATES
02/06/07
74 GHz Series Logic
Test Waveforms
Propagation Delay
3V
1.5V
Input
0V
tPHL
tPLH
VoH
2.0V
1.5V
0.8V
VoL
Output
tf
tR
Test Circuit
Vcc
Pulse
Generator
50Ω
D.U.T.
15pF
to
2pF
4
Copyright © Potato Semiconductor Corporation
PO74G27A
TRIPLE 3-INPUT POSITIVE-NOR GATES
02/06/07
74 GHz Series Logic
Packaging Mechanical Drawing: 14 pin 150mil SOIC
0.244 6.20
0.228 5.80
0.010
0.007
0.050 1.27
0.016 0.40
0.25
0.17
X.XX Denotes dimensions in inches
X.XX
X.XX
Denotes dimensions in millimenters
X.XX
5
Copyright © 2005-2006, Potato Semiconductor Corporation
PO74G27A
TRIPLE 3-INPUT POSITIVE-NOR GATES
02/06/07
74 GHz Series Logic
Ordering Information
Ordering Code
Package
Top-Marking
TA
PO74G27ASU
14pin SOIC
Tube
Pb-free & Green
PO74G27AS
-40°C to 85°C
PO74G27ASR
14pin SOIC
Tape and reel
Pb-free & Green
PO74G27AS
-40°C to 85°C
6
Copyright © Potato Semiconductor Corporation
PO74G32A
QUADRUPLE 2-INPUT POSITIVE-OR GATES
07/27/06
74 GHz Series Logic
FEATURES:
DESCRIPTION:
. Patented technology
. Operating frequency up to 1.125GHz with 2pf load
. Operating frequency up to 750MHz with 5pf load
. Operating frequency up to 350MHz with 15pf load
. VCC Operates from 1.65V to 3.6V
. Propagation delay < 1.5ns max with 15pf load
. Low input capacitance: 4pf typical
. Available in 14pin 150mil wide SOIC package
Potato Semiconductor’s PO74G32A is designed for
world top performance using submicron CMOS
technology to achieve 1.125GHz TTL /CMOS output
frequency with less than 1.5ns propagation delay.
This quadruple 2-input positive-OR gate is designed
for 1.65-V to 3.6-V VCC operation.
The PO74G32A performs the Boolean function
Y= A · B or Y= A + B in positive logic.
Inputs can be driven from either 3.3V or 5V devices.
This feature allows the use of these devices as
translators in a mixed 3.3V/5V system environment.
Pin Configuration
Logic Block Diagram
1A
1
14
V CC
1B
2
13
4B
1Y
3
12
4A
2A
4
11
4Y
2B
5
10
3B
2Y
6
9
3A
GND
7
8
3Y
A
B
Y
Pin Description
INPUTS
A
B
OUTPUT
Y
H
X
H
X
H
H
L
L
L
1
Copyright © 2005-2006, Potato Semiconductor Corporation
PO74G32A
QUADRUPLE 2-INPUT POSITIVE-OR GATES
07/26/06
74 GHz Series Logic
Maximum Ratings
Description
Max
Unit
Storage Temperature
-65 to 150
°C
Operation Temperature
-40 to 85
°C
Operation Voltage
-0.5 to +4.6
V
Input Voltage
-0.5 to +5.5
V
Output Voltage
-0.5 to Vcc+0.5
V
Note:
stresses greater than listed under
Maximum
Ratings
may
cause
permanent damage to the device. This
is a stress rating only and functional
operation of the device at these or any
other conditions above those indicated
in the operational sections of this
specification is not implied. Exposure
to absolute maximum rating conditions
for extended periods may affect
reliability specification is not implied.
DC Electrical Characteristics
Symbol
Description
VOH
Output High voltage
VOL
Test Conditions
Min
Typ
Max
Unit
Vcc=3V Vin=VIH or VIL, IOH= -12mA
2.4
3
-
V
Output Low voltage
Vcc=3V Vin=VIH or VIL, IOH=12mA
-
0.3
0.5
V
VIH
Input High voltage
Guaranteed Logic HIGH Level (Input Pin)
2
-
5.5
V
VIL
Input Low voltage
Guaranteed Logic LOW Level (Input Pin)
-0.5
-
0.8
V
IIH
Input High current
Vcc = 3.6V and Vin = 5.5V
-
-
50
uA
IIL
Input Low current
Vcc = 3.6V and Vin = 0V
-
-
-50
uA
VIK
Clamp diode voltage
Vcc = Min. And IIN = -18mA
-
-0.7
-1.2
V
Notes:
1.
2.
3.
4.
5.
For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
Typical values are at Vcc = 3.3V, 25 °C ambient.
This parameter is guaranteed but not tested.
Not more than one output should be shorted at one time. Duration of the test should not exceed one second.
VoH = Vcc – 0.6V at rated current
2
Copyright © 2005-2006, Potato Semiconductor Corporation
PO74G32A
QUADRUPLE 2-INPUT POSITIVE-OR GATES
07/27/06
74 GHz Series Logic
Power Supply Characteristics
Symbol
Description
Test Conditions (1)
Min
Typ
Max
Unit
IccQ
Quiescent Power Supply Current
Vcc=Max, Vin=Vcc or GND
-
0.1
30
uA
∆Icc
Power Supply Current per Input High
Vcc=Max, Vin= Vcc-0.6V
-
50
300
uA
Notes:
1.
2.
3.
4.
5.
For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
Typical values are at Vcc = 3.3V, 25°C ambient.
This parameter is guaranteed but not tested.
Not more than one output should be shorted at one time. Duration of the test should not exceed one second.
VoH = Vcc – 0.6V at rated current
Capacitance
Parameters (1)
Cin
Cout
Description
Test Conditions
Typ
Unit
Input Capacitance
Vin = 0V
4
pF
Output Capacitance
Vout = 0V
6
pF
Test Conditions (1)
M ax
Unit
Notes:
1 This parameter is determined by device characterization but not production tested.
Switching Characteristics
Symbol
Description
tPLH
Propagation Delay A, B to Y
CL = 15pF
1.5
ns
tPHL
Propagation Delay A, B to Y
CL = 15pF
1.5
ns
tr/tf
Rise/Fall Time
0.8V – 2.0V
0.8
ns
fmax
Input Frequency
CL =15pF
350
MHz
fmax
Input Frequency
CL = 5pF
750
MHz
fmax
Input Frequency
CL = 2pF
1125
MHz
Notes:
1. See test circuits and waveforms.
2. tpLH, tpHL, tsk(p), and tsk(o) are production tested. All other parameters guaranteed but not production tested.
3. Airflow of 1m/s is recommended for frequencies above 133MHz
3
Copyright © 2005-2006, Potato Semiconductor Corporation
PO74G32A
QUADRUPLE 2-INPUT POSITIVE-OR GATES
07/26/06
74 GHz Series Logic
Test Waveforms
Propagation Delay
3V
1.5V
Input
0V
tPLH
tPHL
VoH
2.0V
1.5V
0.8V
VoL
Output
tR
tf
Test Circuit
Vcc
Pulse
Generator
50Ω
D.U.T.
15pF
to
2pF
4
Copyright © 2005-2006, Potato Semiconductor Corporation
PO74G32A
QUADRUPLE 2-INPUT POSITIVE-OR GATES
07/26/06
74 GHz Series Logic
Packaging Mechanical Drawing: 14 pin 150mil SOIC
0.244 6.20
0.228 5.80
0.010
0.007
0.050 1.27
0.016 0.40
0.25
0.17
X.XX Denotes dimensions in inches
X.XX
X.XX
Denotes dimensions in millimenters
X.XX
5
Copyright © 2005-2006, Potato Semiconductor Corporation
PO74G32A
QUADRUPLE 2-INPUT POSITIVE-OR GATES
07/27/06
74 GHz Series Logic
Ordering Information
Ordering Code
Package
Top-Marking
TA
PO74G32ASU
14pin SOIC
Tube
Pb-free & Green
PO74G32AS
-40°C to 85°C
PO74G32ASR
14pin SOIC
Tape and reel
Pb-free & Green
PO74G32AS
-40°C to 85°C
6
Copyright © 2005-2006, Potato Semiconductor Corporation
PO74G74A
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH CLEAR AND PRESET
03/07/07
74 GHz Series Logic
FEATURES:
DESCRIPTION:
. Patented technology
. Operating frequency is faster than 600MHz
Potato Semiconductor’s PO74G74A is designed for
world top performance using submicron CMOS
technology to achieve higher than 600MHz TTL
/CMOS output frequency with less than 2ns propagation delay.
This dual D flip-flop is designed for 1.65-V to 3.6-V
VCC operation.
. VCC Operates from 1.65V to 3.6V
. Propagation delay < 2ns max with 15pf load
. Low input capacitance: 4pf typical
. Available in 14pin 150mil wide SOIC package
Logic Block Diagram
Pin Configuration
1CLR
1
14
VCC
1D
2
13
2CLR
1CLK
3
12
2D
1PRE
4
11
2CLK
1Q
5
10
2PRE
1Q
6
9
2Q
GND
7
8
2Q
1CLR
1
1D
2
D
PRE
1
Pin Description
INPUTS
Inputs can be driven from either 3.3V or 5V devices.
This feature allows the use of these devices as
translators in a mixed 3.3V/5V system environment.
OUTPUTS
PRE
CLR
CLK
D
Q
Q
L
H
X
X
H
L
H
L
X
X
L
H
H (1)
L
L
X
X
H (1)
H
H
↑
H
H
L
H
H
↑
L
L
H
H
H
L
X
Q0
Q0
1CLR
3
1PRE
4
1Q
5
1Q
6
14
Vcc
13
2CLR
12
2D
11
2CLK
Q
10
2PRE
Q
9
2Q
8
2Q
Q
Q
CLR
D
PRE
2
CLR
GND
7
1
Copyright © Potato Semiconductor Corporation
PO74G74A
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH CLEAR AND PRESET
03/06/07
74 GHz Series Logic
Maximum Ratings
Description
Max
Unit
Storage Temperature
-65 to 150
°C
Operation Temperature
-40 to 85
°C
Operation Voltage
-0.5 to +4.6
V
Input Voltage
-0.5 to +5.5
V
Output Voltage
-0.5 to Vcc+0.5
V
Note:
stresses greater than listed under
Maximum
Ratings
may
cause
permanent damage to the device. This
is a stress rating only and functional
operation of the device at these or any
other conditions above those indicated
in the operational sections of this
specification is not implied. Exposure
to absolute maximum rating conditions
for extended periods may affect
reliability specification is not implied.
DC Electrical Characteristics
Symbol
Description
VOH
Output High voltage
VOL
Test Conditions
Min
Typ
Max
Unit
Vcc=3V Vin=VIH or VIL, IOH= -12mA
2.4
3
-
V
Output Low voltage
Vcc=3V Vin=VIH or VIL, IOH=12mA
-
0.3
0.5
V
VIH
Input High voltage
Guaranteed Logic HIGH Level (Input Pin)
2
-
5.5
V
VIL
Input Low voltage
Guaranteed Logic LOW Level (Input Pin)
-0.5
-
0.8
V
IIH
Input High current
Vcc = 3.6V and Vin = 5.5V
-
-
1
uA
IIL
Input Low current
Vcc = 3.6V and Vin = 0V
-
-
-1
uA
VIK
Clamp diode voltage
Vcc = Min. And IIN = -18mA
-
-0.7
-1.2
V
Notes:
1.
2.
3.
4.
5.
For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
Typical values are at Vcc = 3.3V, 25 °C ambient.
This parameter is guaranteed but not tested.
Not more than one output should be shorted at one time. Duration of the test should not exceed one second.
VoH = Vcc – 0.6V at rated current
2
Copyright © Potato Semiconductor Corporation
PO74G74A
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH CLEAR AND PRESET
03/07/07
74 GHz Series Logic
Power Supply Characteristics
Symbol
Description
Test Conditions (1)
Min
Typ
Max
Unit
IccQ
Quiescent Power Supply Current
Vcc=Max, Vin=Vcc or GND
-
0.1
30
uA
∆Icc
Power Supply Current per Input High
Vcc=Max, Vin= Vcc-0.6V
-
50
300
uA
Notes:
1.
2.
3.
4.
5.
For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
Typical values are at Vcc = 3.3V, 25°C ambient.
This parameter is guaranteed but not tested.
Not more than one output should be shorted at one time. Duration of the test should not exceed one second.
VoH = Vcc – 0.6V at rated current
Capacitance
Parameters (1)
Cin
Cout
Description
Test Conditions
Typ
Input Capacitance
Vin = 0V
Output Capacitance
Vout = 0V
4
6
Unit
pF
pF
Notes:
1 This parameter is determined by device characterization but not production tested.
Switching Characteristics
Symbol
Description
Test Conditions (1)
M ax
-
tsu
th
Setup time before CLK
tPLH
Propagation Delay CLK to Q
CL = 15pF
2
t PHL
Propagation Delay CLK to Q
CL = 15pF
2
tr/tf
Rise/Fall Time
0.8V – 2.0V
0.8
fmax
Input Frequency
CL=2pF - 15pF
Hold time, data after CLK
-
Min
Unit
0.5
ns
0.5
ns
-
ns
ns
ns
600
MHz
Notes:
1. See test circuits and waveforms.
2. tPLH, tPHL, tsu, and th are production tested. All other parameters guaranteed but not production tested.
3. Airflow of 1m/s is recommended for frequencies above 500MHz
3
Copyright © Potato Semiconductor Corporation
PO74G74A
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH CLEAR AND PRESET
03/07/07
74 GHz Series Logic
Test Waveforms
VI
Timing Input
VM
0V
tw
tsu
VI
Input
VM
VM
th
VI
Data Input
VM
VM
0V
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATION
VI
VM
Input
VM
0V
tPLH
tPHL
VOH
VM
Output
VM
VOL
tPHL
Output
Waveform 1
S1 at V LOAD
(see Note B)
tPLH
VM
VM
VM
0V
tPZL
tPLZ
VLOAD/2
VM
tPZH
VOH
Output
VI
Output
Control
VM
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
Output
Waveform 2
S1 at GND
(see Note B)
VOL + VΔ
VOL
tPHZ
VM
VOH - VΔ
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
Test Circuit
Vcc
Pulse
Generator
50Ω
D.U.T
15pF
to
2pF
4
Copyright © Potato Semiconductor Corporation
PO74G74A
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH CLEAR AND PRESET
02/13/07
74 GHz Series Logic
Packaging Mechanical Drawing: 14 pin 150mil SOIC
0.244 6.20
0.228 5.80
0.010
0.007
0.050 1.27
0.016 0.40
0.25
0.17
X.XX Denotes dimensions in inches
X.XX
X.XX
Denotes dimensions in millimenters
X.XX
5
Copyright © Potato Semiconductor Corporation
PO74G74A
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH CLEAR AND PRESET
02/13/07
74 GHz Series Logic
Ordering Information
Ordering Code
Package
Top-Marking
TA
PO74G74ASU
14 pin SOIC
Tube
Pb-free & Green
PO74G74AS
-40°C to 85°C
PO74G74ASR
14 pin SOIC
Tape and reel
Pb-free & Green
PO74G74AS
-40°C to 85°C
6
Copyright © Potato Semiconductor Corporation
PO74G86A
QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES
07/25/06
74 GHz Series Logic
FEATURES:
DESCRIPTION:
. Patented technology
. Operating frequency up to 1.125GHz with 2pf load
. Operating frequency up to 750MHz with 5pf load
. Operating frequency up to 350MHz with 15pf load
. VCC Operates from 1.65V to 3.6V
. Propagation delay < 1.5ns max with 15pf load
. Low input capacitance: 4pf typical
. Available in 14pin 150mil wide SOIC package
Potato Semiconductor’s PO74G86A is designed for
world top performance using submicron CMOS
technology to achieve 1.125GHz TTL /CMOS output
frequency with less than 1.5ns propagation delay.
This quadruple 2-input exclusive-OR gate is designed
for 1.65-V to 3.6-V VCC operation.
The PO74G86A performs the Boolean function
Y= A ⊕ B or Y= AB + AB in positive logic.
Inputs can be driven from either 3.3V or 5V devices.
This feature allows the use of these devices as
translators in a mixed 3.3V/5V system environment.
Pin Configuration
Logic Block Diagram
1A
1
14
V CC
1B
2
13
4B
1Y
3
12
4A
A
2A
4
11
4Y
B
2B
5
10
3B
2Y
6
9
3A
GND
7
8
3Y
Y
Pin Description
INPUTS
A
B
OUTPUT
Y
L
L
L
L
H
H
H
L
H
H
H
L
1
Copyright © 2005-2006, Potato Semiconductor Corporation
PO74G86A
QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES
07/26/06
74 GHz Series Logic
Maximum Ratings
Description
Max
Unit
Storage Temperature
-65 to 150
°C
Operation Temperature
-40 to 85
°C
Operation Voltage
-0.5 to +4.6
V
Input Voltage
-0.5 to +5.5
V
Output Voltage
-0.5 to Vcc+0.5
V
Note:
stresses greater than listed under
Maximum
Ratings
may
cause
permanent damage to the device. This
is a stress rating only and functional
operation of the device at these or any
other conditions above those indicated
in the operational sections of this
specification is not implied. Exposure
to absolute maximum rating conditions
for extended periods may affect
reliability specification is not implied.
DC Electrical Characteristics
Symbol
Description
VOH
Output High voltage
VOL
Test Conditions
Min
Typ
Max
Unit
Vcc=3V Vin=VIH or VIL, IOH= -12mA
2.4
3
-
V
Output Low voltage
Vcc=3V Vin=VIH or VIL, IOH=12mA
-
0.3
0.5
V
VIH
Input High voltage
Guaranteed Logic HIGH Level (Input Pin)
2
-
5.5
V
VIL
Input Low voltage
Guaranteed Logic LOW Level (Input Pin)
-0.5
-
0.8
V
IIH
Input High current
Vcc = 3.6V and Vin = 5.5V
-
-
50
uA
IIL
Input Low current
Vcc = 3.6V and Vin = 0V
-
-
-50
uA
VIK
Clamp diode voltage
Vcc = Min. And IIN = -18mA
-
-0.7
-1.2
V
Notes:
1.
2.
3.
4.
5.
For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
Typical values are at Vcc = 3.3V, 25 °C ambient.
This parameter is guaranteed but not tested.
Not more than one output should be shorted at one time. Duration of the test should not exceed one second.
VoH = Vcc – 0.6V at rated current
2
Copyright © 2005-2006, Potato Semiconductor Corporation
PO74G86A
QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES
07/27/06
74 GHz Series Logic
Power Supply Characteristics
Symbol
Description
Test Conditions (1)
Min
Typ
Max
Unit
IccQ
Quiescent Power Supply Current
Vcc=Max, Vin=Vcc or GND
-
0.1
30
uA
∆Icc
Power Supply Current per Input High
Vcc=Max, Vin= Vcc-0.6V
-
50
300
uA
Notes:
1.
2.
3.
4.
5.
For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
Typical values are at Vcc = 3.3V, 25°C ambient.
This parameter is guaranteed but not tested.
Not more than one output should be shorted at one time. Duration of the test should not exceed one second.
VoH = Vcc – 0.6V at rated current
Capacitance
Parameters (1)
Cin
Cout
Description
Test Conditions
Typ
Unit
Input Capacitance
Vin = 0V
4
pF
Output Capacitance
Vout = 0V
6
pF
Test Conditions (1)
M ax
Unit
Notes:
1 This parameter is determined by device characterization but not production tested.
Switching Characteristics
Symbol
Description
tPLH
Propagation Delay A, B to Y
CL = 15pF
1.5
ns
tPHL
Propagation Delay A, B to Y
CL = 15pF
1.5
ns
tr/tf
Rise/Fall Time
0.8V – 2.0V
0.8
ns
fmax
Input Frequency
CL =15pF
350
MHz
fmax
Input Frequency
CL = 5pF
750
MHz
fmax
Input Frequency
CL = 2pF
1125
MHz
Notes:
1. See test circuits and waveforms.
2. tpLH, tpHL, tsk(p), and tsk(o) are production tested. All other parameters guaranteed but not production tested.
3. Airflow of 1m/s is recommended for frequencies above 133MHz
3
Copyright © 2005-2006, Potato Semiconductor Corporation
PO74G86A
QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES
07/26/06
74 GHz Series Logic
Test Waveforms
Propagation Delay
3V
1.5V
Input
0V
tPLH
tPHL
VoH
2.0V
1.5V
0.8V
VoL
Output
tR
tf
Propagation Delay
3V
1.5V
Input
0V
tPHL
tPLH
VoH
2.0V
1.5V
0.8V
VoL
Output
tf
tR
Test Circuit
Vcc
Pulse
Generator
50Ω
D.U.T.
15pF
to
2pF
4
Copyright © 2005-2006, Potato Semiconductor Corporation
PO74G86A
QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES
07/26/06
74 GHz Series Logic
Packaging Mechanical Drawing: 14 pin 150mil SOIC
0.244 6.20
0.228 5.80
0.010
0.007
0.050 1.27
0.016 0.40
0.25
0.17
X.XX Denotes dimensions in inches
X.XX
X.XX
Denotes dimensions in millimenters
X.XX
5
Copyright © 2005-2006, Potato Semiconductor Corporation
PO74G86A
QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES
07/27/06
74 GHz Series Logic
Ordering Information
Ordering Code
Package
Top-Marking
TA
PO74G86ASU
14pin SOIC
Tube
Pb-free & Green
PO74G86AS
-40°C to 85°C
PO74G86ASR
14pin SOIC
Tape and reel
Pb-free & Green
PO74G86AS
-40°C to 85°C
6
Copyright © 2005-2006, Potato Semiconductor Corporation
PO74G125A
QUADRUPLE BUS BUFFER GATES
WITH 3-STATE OUTPUTS
07/26/06
74 GHz Series Logic
FEATURES:
DESCRIPTION:
. Patented technology
. Operating frequency up to 1.125GHz with 2pf load
. Operating frequency up to 550MHz with 5pf load
. Operating frequency up to 300MHz with 15pf load
. VCC Operates from 1.65V to 3.6V
. Propagation delay < 1.5ns max with 15pf load
. Low input capacitance: 4pf typical
. Available in 14pin 150mil wide SOIC package
Potato Semiconductor’s PO74G125A is designed for
world top performance using submicron CMOS
technology to achieve 1.125GHz TTL /CMOS output
frequency with less than 1.5ns propagation delay.
This quadruple bus buffer gate is designed for 1.65-V
to 3.6-V VCC operation.
The PO74G125A features independent line drivers with
3-state outputs. Each output is disabled when the
associated output-enable (OE) input is high. To ensure
the high-impedance state during power up or power
down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is
determined by the current-sinking capability of
the driver.
Inputs can be driven from either 3.3V or 5V devices.
This feature allows the use of these devices as
translators in a mixed 3.3V/5V system environment.
Pin Configuration
Logic Block Diagram
1OE
1
14
VCC
1A
2
13
4OE
1Y
3
12
4A
4
11
4Y
2A
5
10
3OE
2Y
6
9
3A
GND
7
8
3Y
2OE
1OE
1A
2OE
2A
3OE
Pin Description
INPUTS
3A
OE
A
OUTPUT
Y
L
H
H
L
L
L
H
X
Z
4OE
4A
1
2
3
1Y
4
5
6
2Y
10
9
8
3Y
13
12
11
4Y
1
Copyright © 2005-2006, Potato Semiconductor Corporation
PO74G125A
QUADRUPLE BUS BUFFER GATES
WITH 3-STATE OUTPUTS
07/26/06
74 GHz Series Logic
Maximum Ratings
Description
Max
Unit
Storage Temperature
-65 to 150
°C
Operation Temperature
-40 to 85
°C
Operation Voltage
-0.5 to +4.6
V
Input Voltage
-0.5 to +5.5
V
Output Voltage
-0.5 to Vcc+0.5
V
Note:
stresses greater than listed under
Maximum
Ratings
may
cause
permanent damage to the device. This
is a stress rating only and functional
operation of the device at these or any
other conditions above those indicated
in the operational sections of this
specification is not implied. Exposure
to absolute maximum rating conditions
for extended periods may affect
reliability specification is not implied.
DC Electrical Characteristics
Symbol
Description
VOH
Output High voltage
VOL
Test Conditions
Min
Typ
Max
Unit
Vcc=3V Vin=VIH or VIL, IOH= -12mA
2.4
3
-
V
Output Low voltage
Vcc=3V Vin=VIH or VIL, IOH=12mA
-
0.3
0.5
V
VIH
Input High voltage
Guaranteed Logic HIGH Level (Input Pin)
2
-
5.5
V
VIL
Input Low voltage
Guaranteed Logic LOW Level (Input Pin)
-0.5
-
0.8
V
IIH
Input High current
Vcc = 3.6V and Vin = 5.5V
-
-
50
uA
IIL
Input Low current
Vcc = 3.6V and Vin = 0V
-
-
-50
uA
VIK
Clamp diode voltage
Vcc = Min. And IIN = -18mA
-
-0.7
-1.2
V
Notes:
1.
2.
3.
4.
5.
For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
Typical values are at Vcc = 3.3V, 25 °C ambient.
This parameter is guaranteed but not tested.
Not more than one output should be shorted at one time. Duration of the test should not exceed one second.
VoH = Vcc – 0.6V at rated current
2
Copyright © 2005-2006, Potato Semiconductor Corporation
PO74G125A
QUADRUPLE BUS BUFFER GATES
WITH 3-STATE OUTPUTS
07/27/06
74 GHz Series Logic
Power Supply Characteristics
Symbol
Description
Test Conditions (1)
Min
Typ
Max
Unit
IccQ
Quiescent Power Supply Current
Vcc=Max, Vin=Vcc or GND
-
0.1
30
uA
∆Icc
Power Supply Current per Input High
Vcc=Max, Vin= Vcc-0.6V
-
50
300
uA
Notes:
1.
2.
3.
4.
5.
For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
Typical values are at Vcc = 3.3V, 25°C ambient.
This parameter is guaranteed but not tested.
Not more than one output should be shorted at one time. Duration of the test should not exceed one second.
VoH = Vcc – 0.6V at rated current
Capacitance
Parameters (1)
Cin
Cout
Description
Test Conditions
Typ
Unit
Input Capacitance
Vin = 0V
pF
Output Capacitance
Vout = 0V
4
6
Test Conditions (1)
M ax
Unit
pF
Notes:
1 This parameter is determined by device characterization but not production tested.
Switching Characteristics
Symbol
Description
tPLH
Propagation Delay A, B to Y
CL = 15pF
1.5
ns
tPHL
Propagation Delay A, B to Y
CL = 15pF
1.5
ns
tr/tf
Rise/Fall Time
0.8V – 2.0V
fmax
Input Frequency
CL =15pF
0.8
300
ns
MHz
fmax
fmax
Input Frequency
CL = 5pF
550
MHz
Input Frequency
CL = 2pF
1125
MHz
Notes:
1. See test circuits and waveforms.
2. tpLH, tpHL, tsk(p), and tsk(o) are production tested. All other parameters guaranteed but not production tested.
3. Airflow of 1m/s is recommended for frequencies above 133MHz
3
Copyright © 2005-2006, Potato Semiconductor Corporation
PO74G125A
QUADRUPLE BUS BUFFER GATES
WITH 3-STATE OUTPUTS
07/27/06
74 GHz Series Logic
Test Waveforms
Test Circuit
500 Ω
50Ω
15pF
to
2pF
50 Ω
500 Ω
4
Copyright © 2005-2006, Potato Semiconductor Corporation
PO74G125A
QUADRUPLE BUS BUFFER GATES
WITH 3-STATE OUTPUTS
07/26/06
74 GHz Series Logic
Packaging Mechanical Drawing: 14 pin 150mil SOIC
0.244 6.20
0.228 5.80
0.010
0.007
0.050 1.27
0.016 0.40
0.25
0.17
X.XX Denotes dimensions in inches
X.XX
X.XX
Denotes dimensions in millimenters
X.XX
5
Copyright © 2005-2006, Potato Semiconductor Corporation
PO74G125A
QUADRUPLE BUS BUFFER GATES
WITH 3-STATE OUTPUTS
07/27/06
74 GHz Series Logic
Ordering Information
Ordering Code
Package
Top-Marking
TA
PO74G125ASU
14pin SOIC
Tube
Pb-free & Green
PO74G125AS
-40°C to 85°C
PO74G125ASR
14pin SOIC
Tape and reel
Pb-free & Green
PO74G125AS
-40°C to 85°C
6
Copyright © 2005-2006, Potato Semiconductor Corporation
PO74G126A
QUADRUPLE BUS BUFFER GATE
WITH 3-STATE OUTPUTS
02/07/07
74 GHz Series Logic
FEATURES:
DESCRIPTION:
. Patented technology
. Operating frequency up to 1.125GHz with 2pf load
. Operating frequency up to 700MHz with 5pf load
. Operating frequency up to 400MHz with 15pf load
. VCC Operates from 1.65V to 3.6V
. Propagation delay < 1.5ns max with 15pf load
. Low input capacitance: 4pf typical
. Available in 14pin 150mil wide SOIC package
Potato Semiconductor’s PO74G126A is designed for
world top performance using submicron CMOS
technology to achieve 1.125GHz TTL /CMOS output
frequency with less than 1.5ns propagation delay.
This quadruple bus buffer gate is designed for 1.65-V
to 3.6-V VCC operation.
The PO74G126A featuresindependent
linedriverswith3-stateoutputs. Eachoutput isdisabledwhenthe associatedoutput-enable(OE)input islow.
Inputs can be driven from either 3.3V or 5V devices.
This feature allows the use of these devices as
translators in a mixed 3.3V/5V system environment.
Pin Configuration
Logic Block Diagram
1OE
1
14
VCC
1A
2
13
4OE
1Y
3
12
4A
4
11
4Y
2A
5
10
3OE
2Y
6
9
3A
GND
7
8
3Y
2OE
1OE
1A
2OE
2A
3OE
Pin Description
INPUTS
3A
OE
A
OUTPUT
Y
H
H
H
H
L
L
L
X
Z
4OE
4A
1
2
3
1Y
4
5
6
2Y
10
9
8
3Y
13
12
11
4Y
1
Copyright © Potato Semiconductor Corporation
PO74G126A
QUADRUPLE BUS BUFFER GATE
WITH 3-STATE OUTPUTS
02/07/07
74 GHz Series Logic
Maximum Ratings
Description
Max
Unit
Storage Temperature
-65 to 150
°C
Operation Temperature
-40 to 85
°C
Operation Voltage
-0.5 to +4.6
V
Input Voltage
-0.5 to +5.5
V
Output Voltage
-0.5 to Vcc+0.5
V
Note:
stresses greater than listed under
Maximum
Ratings
may
cause
permanent damage to the device. This
is a stress rating only and functional
operation of the device at these or any
other conditions above those indicated
in the operational sections of this
specification is not implied. Exposure
to absolute maximum rating conditions
for extended periods may affect
reliability specification is not implied.
DC Electrical Characteristics
Symbol
Description
VOH
Output High voltage
VOL
Test Conditions
Min
Typ
Max
Unit
Vcc=3V Vin=VIH or VIL, IOH= -12mA
2.4
3
-
V
Output Low voltage
Vcc=3V Vin=VIH or VIL, IOH=12mA
-
0.3
0.5
V
VIH
Input High voltage
Guaranteed Logic HIGH Level (Input Pin)
2
-
5.5
V
VIL
Input Low voltage
Guaranteed Logic LOW Level (Input Pin)
-0.5
-
0.8
V
IIH
Input High current
Vcc = 3.6V and Vin = 5.5V
-
-
1
uA
IIL
Input Low current
Vcc = 3.6V and Vin = 0V
-
-
-1
uA
VIK
Clamp diode voltage
Vcc = Min. And IIN = -18mA
-
-0.7
-1.2
V
Notes:
1.
2.
3.
4.
5.
For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
Typical values are at Vcc = 3.3V, 25 °C ambient.
This parameter is guaranteed but not tested.
Not more than one output should be shorted at one time. Duration of the test should not exceed one second.
VoH = Vcc – 0.6V at rated current
2
Copyright © Potato Semiconductor Corporation
PO74G126A
QUADRUPLE BUS BUFFER GATE
WITH 3-STATE OUTPUTS
02/07/07
74 GHz Series Logic
Power Supply Characteristics
Symbol
Description
Test Conditions (1)
Min
Typ
Max
Unit
IccQ
Quiescent Power Supply Current
Vcc=Max, Vin=Vcc or GND
-
0.1
30
uA
∆Icc
Power Supply Current per Input High
Vcc=Max, Vin= Vcc-0.6V
-
50
300
uA
Notes:
1.
2.
3.
4.
5.
For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
Typical values are at Vcc = 3.3V, 25°C ambient.
This parameter is guaranteed but not tested.
Not more than one output should be shorted at one time. Duration of the test should not exceed one second.
VoH = Vcc – 0.6V at rated current
Capacitance
Parameters (1)
Cin
Cout
Description
Test Conditions
Typ
Unit
Input Capacitance
Vin = 0V
pF
Output Capacitance
Vout = 0V
4
6
Test Conditions (1)
M ax
Unit
pF
Notes:
1 This parameter is determined by device characterization but not production tested.
Switching Characteristics
Symbol
Description
tPLH
Propagation Delay A, B to Y
CL = 15pF
1.5
ns
tPHL
Propagation Delay A, B to Y
CL = 15pF
1.5
ns
tr/tf
Rise/Fall Time
0.8V – 2.0V
fmax
Input Frequency
CL =15pF
0.8
400
ns
MHz
fmax
fmax
Input Frequency
CL = 5pF
750
MHz
Input Frequency
CL = 2pF
1125
MHz
Notes:
1. See test circuits and waveforms.
2. tpLH, tpHL, tsk(p), and tsk(o) are production tested. All other parameters guaranteed but not production tested.
3. Airflow of 1m/s is recommended for frequencies above 133MHz
3
Copyright © 2005-2006, Potato Semiconductor Corporation
PO74G126A
QUADRUPLE BUS BUFFER GATE
WITH 3-STATE OUTPUTS
02/07/07
74 GHz Series Logic
Test Waveforms
Test Circuit
500 Ω
50Ω
15pF
to
2pF
50 Ω
500 Ω
4
Copyright © Potato Semiconductor Corporation
PO74G126A
QUADRUPLE BUS BUFFER GATE
WITH 3-STATE OUTPUTS
02/07/07
74 GHz Series Logic
Packaging Mechanical Drawing: 14 pin 150mil SOIC
0.244 6.20
0.228 5.80
0.010
0.007
0.050 1.27
0.016 0.40
0.25
0.17
X.XX Denotes dimensions in inches
X.XX
X.XX
Denotes dimensions in millimenters
X.XX
5
Copyright © Potato Semiconductor Corporation
PO74G126A
QUADRUPLE BUS BUFFER GATE
WITH 3-STATE OUTPUTS
02/07/07
74 GHz Series Logic
Ordering Information
Ordering Code
Package
Top-Marking
TA
PO74G126ASU
14pin SOIC
Tube
Pb-free & Green
PO74G126AS
-40°C to 85°C
PO74G126ASR
14pin SOIC
Tape and reel
Pb-free & Green
PO74G126AS
-40°C to 85°C
6
Copyright © Potato Semiconductor Corporation
PO74G139A
DUAL2-LINETO4-LINEDECODER/DEMULTIPLEXER
02/07/07
74 GHz Series Logic
FEATURES:
DESCRIPTION:
. Patented technology
. Operating frequency up to 1.125GHz with 2pf load
. Operating frequency up to 800MHz with 5pf load
. Operating frequency up to 350MHz with 15pf load
. VCC Operates from 1.65V to 3.6V
. Propagation delay < 1.7ns max with 15pf load
. Low input capacitance: 4pf typical
. Available in 16 pin SOIC package
Potato Semiconductor’s PO74G139A is designed for
world top performance using submicron CMOS
technology to achieve 1.125GHz TTL /CMOS output
frequency with less than 1.7ns propagation delay.
This quadruple bus buffer gate is designed for 1.65-V
to 3.6-V VCC operation.
The PO74G139A comprises two individual 2-line to
4-line decoders in a single package. Theactivelowenable (G) input can be used as a data line in
demultiplexing applications. This decoder/ demultiplexer features fully buffered
inputs, each of which represents only one normalizedload to itsdriving circuit.
Inputs can be driven from either 3.3V or 5V devices.
This feature allows the use of these devices as
translators in a mixed 3.3V/5V system environment.
Pin Configuration
Logic Block Diagram
4
1G
1A
1B
1Y0
1Y1
1Y2
1Y3
GND
1
16
2
15
3
14
4
13
5
12
6
11
7
10
8
9
VCC
2G
2A
2B
2Y0
2Y1
2Y2
2Y3
1G
5
6
1A
Select
Inputs
1B
1Y0
1
1Y1
1Y2
2
7
3
1Y3
Data
Outputs
12
2G
11
10
2A
Select
Inputs
2B
2Y0
15
2Y1
2Y2
14
9
13
2Y3
Pin Description
INPUTS
G
OUTPUTS
SELECT
B
A
Y3
Y2
Y1
Y0
L
L
L
H
H
H
L
L
L
H
H
H
L
H
L
H
L
H
L
H
H
L
H
H
L
H
H
H
H
X
X
H
H
H
H
1
Copyright © Potato Semiconductor Corporation
PO74G139A
DUAL2-LINETO4-LINEDECODER/DEMULTIPLEXER
02/07/07
74 GHz Series Logic
Maximum Ratings
Description
Max
Unit
Storage Temperature
-65 to 150
°C
Operation Temperature
-40 to 85
°C
Operation Voltage
-0.5 to +4.6
V
Input Voltage
-0.5 to +5.5
V
Output Voltage
-0.5 to Vcc+0.5
V
Note:
stresses greater than listed under
Maximum
Ratings
may
cause
permanent damage to the device. This
is a stress rating only and functional
operation of the device at these or any
other conditions above those indicated
in the operational sections of this
specification is not implied. Exposure
to absolute maximum rating conditions
for extended periods may affect
reliability specification is not implied.
DC Electrical Characteristics
Symbol
Description
VOH
Output High voltage
VOL
Test Conditions
Min
Typ
Max
Unit
Vcc=3V Vin=VIH or VIL, IOH= -12mA
2.4
3
-
V
Output Low voltage
Vcc=3V Vin=VIH or VIL, IOH=12mA
-
0.3
0.5
V
VIH
Input High voltage
Guaranteed Logic HIGH Level (Input Pin)
2
-
5.5
V
VIL
Input Low voltage
Guaranteed Logic LOW Level (Input Pin)
-0.5
-
0.8
V
IIH
Input High current
Vcc = 3.6V and Vin = 5.5V
-
-
1
uA
IIL
Input Low current
Vcc = 3.6V and Vin = 0V
-
-
-1
uA
VIK
Clamp diode voltage
Vcc = Min. And IIN = -18mA
-
-0.7
-1.2
V
Notes:
1.
2.
3.
4.
5.
For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
Typical values are at Vcc = 3.3V, 25 °C ambient.
This parameter is guaranteed but not tested.
Not more than one output should be shorted at one time. Duration of the test should not exceed one second.
VoH = Vcc – 0.6V at rated current
2
Copyright © Potato Semiconductor Corporation
PO74G139A
DUAL2-LINETO4-LINEDECODER/DEMULTIPLEXER
02/07/07
74 GHz Series Logic
Power Supply Characteristics
Symbol
Description
Test Conditions (1)
Min
Typ
Max
Unit
IccQ
Quiescent Power Supply Current
Vcc=Max, Vin=Vcc or GND
-
0.1
30
uA
∆Icc
Power Supply Current per Input High
Vcc=Max, Vin= Vcc-0.6V
-
50
300
uA
Notes:
1.
2.
3.
4.
5.
For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
Typical values are at Vcc = 3.3V, 25°C ambient.
This parameter is guaranteed but not tested.
Not more than one output should be shorted at one time. Duration of the test should not exceed one second.
VoH = Vcc – 0.6V at rated current
Capacitance
Parameters (1)
Cin
Cout
Description
Test Conditions
Typ
Unit
Input Capacitance
Vin = 0V
pF
Output Capacitance
Vout = 0V
4
6
Test Conditions (1)
M ax
Unit
pF
Notes:
1 This parameter is determined by device characterization but not production tested.
Switching Characteristics
Symbol
Description
tPLH
Propagation Delay A, B to Y
CL = 15pF
1.7
ns
tPHL
Propagation Delay A, B to Y
CL = 15pF
1.7
ns
Rise/Fall Time
0.8V – 2.0V
CL = 15pF, 125MHz
0.8
0.25
ns
ns
tr/tf
tsk(o)
Output Pin to Pin Skew
fmax
Input Frequency
CL =15pF
350
MHz
fmax
fmax
Input Frequency
CL = 5pF
800
MHz
Input Frequency
CL = 2pF
1125
MHz
Notes:
1. See test circuits and waveforms.
2. tpLH, tpHL, tsk(p), and tsk(o) are production tested. All other parameters guaranteed but not production tested.
3. Airflow of 1m/s is recommended for frequencies above 133MHz
3
Copyright © 2005-2006, Potato Semiconductor Corporation
PO74G139A
DUAL2-LINETO4-LINEDECODER/DEMULTIPLEXER
02/07/07
74 GHz Series Logic
Test Waveforms
Test Circuit
500 Ω
50Ω
15pF
to
2pF
50 Ω
500 Ω
4
Copyright © Potato Semiconductor Corporation
PO74G139A
DUAL2-LINETO4-LINEDECODER/DEMULTIPLEXER
02/07/07
74 GHz Series Logic
Packaging Mechanical Drawing: 16 pin SOIC
16
.149
.157
.2284
.2440
3.78
3.99
1
.0075
.0098
.386
.393
9.80
10.00
.016
.050
5.80
6.20
0.41
1.27
0.19
0.25
.0155 0.393
.0260 0.660
.053
.068
.050
BSC
1.27
.013
.020
0.330
0.508
.0040
.0098
1.35
1.75
0.10
0.25
X.XX DENOTES DIMENSIONS
X.XX IN MILLIMETERS
Packaging Mechanical Drawing: 16 pin TSSOP
X.XX DENOTES DIMENSIONS
X.XX IN MILLIMETERS
5
Copyright © Potato Semiconductor Corporation
PO74G139A
DUAL2-LINETO4-LINEDECODER/DEMULTIPLEXER
02/07/07
74 GHz Series Logic
Ordering Information
Ordering Code
Package
Top-Marking
TA
PO74G139ASU
16-pin SOIC
Tube
Pb-free & Green
PO74G139AS
-40°C to 85°C
PO74G139ASR
16-pin SOIC
Tape and reel
Pb-free & Green
PO74G139AS
-40°C to 85°C
PO74G139ATU
16-pin TSSOP
Tube
Pb-free & Green
PO74G139AT
-40°C to 85°C
PO74G139ATR
16-pin TSSOP
Tape and reel
Pb-free & Green
PO74G139AT
-40°C to 85°C
6
Copyright © Potato Semiconductor Corporation
PO100HSTL22A
02/13/07
Dual LVTTL/LVCMOS to Differential HSTL Translator
DESCRIPTION:
FEATURES:
• Patented Technology
• HSTL differential outputs
• LVTTL/LVCMOS to Differential HSTL Translator
• Operating frequency up to 1.65GHz with 5pf load
• Operating frequency up to 500MHz with 15pf load
• Very low output pin to pin skew < 100ps
• Propagation delay < 1.4ns max with 15pf load
• 1.65V to 3.6V power supply
• Industrial temperature range: –40°C to 85°C
• Available in 8-pin SOIC package
• Available in 8-pin TSSOP package
Pin Configuration
Potato Semiconductor’s PO100HSTL22A is
designed for world top performance using
submicron CMOS technology to achieve
1.65GHz HSTL output frequency with less than
1.4ns propagation delay.
The PO100HSTL22A is a low-skew,
LVTTL/LVCMOS to Differential HSTL
Translator. The small outline 8 pin package and
the low skew design to make it ideal for applications which require the translation of a clock or a
data signal.
Logic Block Diagram
Q0
Q0
1
8
VCC
Q0
2
7
D0
Q0
D0
HSTL
Q1
3
6
D1
5
GND
Q1
Q1
4
LVTTL/
LVCMOS
D1
Q1
Pin Description
PIN
Qn, Qn
D0, D1
VCC
GND
FUNCTION
HSTL Differential Outputs
LVTTL/LVCMOS Inputs
Positive Supply
Ground
1
Copyright © Potato Semiconductor Corporation
PO100HSTL22A
02/13/07
Dual LVTTL/LVCMOS to Differential HSTL Translator
Maximum Ratings
Description
Max
Unit
Storage Temperature
-65 to 150
°C
Operation Temperature
-40 to 85
°C
Operation Voltage
-0.5 to +4.6
V
Input Voltage
-0.5 to +5.5
V
Output Voltage
-0.5 to Vcc+0.5
V
Note:
stresses greater than listed under
Maximum
Ratings
may
cause
permanent damage to the device. This
is a stress rating only and functional
operation of the device at these or any
other conditions above those indicated
in the operational sections of this
specification is not implied. Exposure
to absolute maximum rating conditions
for extended periods may affect
reliability specification is not implied.
DC Electrical Characteristics
Symbol
Description
VOH
Output High voltage
VOL
Test Conditions
Min
Typ
Max
Unit
Vcc=3V Vin=VIH or VIL, IOH= -12mA
2.4
3
-
V
Output Low voltage
Vcc=3V Vin=VIH or VIL, IOH=12mA
-
0.3
0.5
V
VIH
Input High voltage
Guaranteed Logic HIGH Level (Input Pin)
2
-
Vcc
V
VIL
Input Low voltage
Guaranteed Logic LOW Level (Input Pin)
-0.5
-
0.8
V
IIH
Input High current
Vcc = 3.6V and Vin = 5.5V
-
-
1
uA
IIL
Input Low current
Vcc = 3.6V and Vin = 0V
-
-
-1
uA
VIK
Clamp diode voltage
Vcc = Min. And IIN = -18mA
-0.7
-1.2
-
V
Notes:
1.
2.
3.
4.
5.
For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
Typical values are at Vcc = 3.3V, 25 °C ambient.
This parameter is guaranteed but not tested.
Not more than one output should be shorted at one time. Duration of the test should not exceed one second.
VoH = Vcc – 0.6V at rated current
2
Copyright © Potato Semiconductor Corporation
PO100HSTL22A
02/13/07
Dual LVTTL/LVCMOS to Differential HSTL Translator
Power Supply Characteristics
Symbol
Description
Test Conditions (1)
Min
Typ
Max
Unit
IccQ
Quiescent Power Supply Current
Vcc=Max, Vin=Vcc or GND
-
0.1
50
uA
∆Icc
Power Supply Current per Input High
Vcc=Max, Vin= Vcc-0.6V
-
50
300
uA
Notes:
1.
2.
3.
4.
5.
For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
Typical values are at Vcc = 3.3V, 25°C ambient.
This parameter is guaranteed but not tested.
Not more than one output should be shorted at one time. Duration of the test should not exceed one second.
VoH = Vcc – 0.6V at rated current
Switching Characteristics
Symbol
tPD
Description
Test Conditions (1)
M ax
Unit
CL = 15pF
1.4
ns
0.8V – 2.0V
Output Pin to Pin Skew (Same Package)
CL = 15pF, 125MHz
0.8
100
ns
ps
Output Skew (Different Package)
CL = 15pF, 125MHz
250
ps
Input Frequency
CL =15pF
MHz
Input Frequency
CL = 5pF
500
250
1.65
300
Propagation Delay D to Output pair
tr/tf
tsk(o)
tsk(pp)
fmax
fmax
Rise/Fall Time
GHz
Notes:
1. See test circuits and waveforms.
2. tpLH, tpHL, tsk(p), and tsk(o) are production tested. All other parameters guaranteed but not production tested.
3. Airflow of 1m/s is recommended for frequencies above 133MHz
Test Circuit
Vcc
Pulse
Generator
15pF
to
2pF
D.U.T
50Ω
15pF
to
2pF
3
Copyright © Potato Semiconductor Corporation
PO100HSTL22A
02/13/07
Dual LVTTL/LVCMOS to Differential HSTL Translator
Test Waveforms
FIGURE 1.
LVTTL/LVCMOS INPUT WAVEFORM DEFINITION
3V
1.5V
Input
0V
FIGURE 2.
HSTL OUTPUT
tr,tf,
20-80%
VO
FIGURE 3.
Propogation Delay, Output pulse skew, and output-to-output skew for D to output pair
INPUT
CLOCK
TPLH
TPD
TPHL
OUTPUT
CLOCK
VO
tSK(O)
ANOTHER
OUTPUT
CLOCK
4
Copyright © Potato Semiconductor Corporation
PO100HSTL22A
Dual LVTTL/LVCMOS to Differential HSTL Translator
02/13/07
Packaging Mechanical Drawing: 8 pin SOIC
8
0-8˚
.149
.157
3.78
3.99
.0099
.0196
0.25
x 45˚
0.50
.016
.050
0.40
1.27
.2284
.2440
5.80
6.20
1
.189
.196
4.80
5.00
.053
.068
.016
.026
0.406
0.660
.0075
.0098
1.35
1.75
0.19
0.25
SEATING PLANE
REF
.050
BSC
1.27
.0040 0.10
.0098 0.25
.013 0.330
.020 0.508
X.XX DENOTES DIMENSIONS
X.XX IN MILLIMETERS
Packaging Mechanical Drawing: 8 pin TSSOP
8
SEATING PLANE
X.XX DENOTES DIMENSIONS
X.XX IN MILLIMETERS
5
Copyright © Potato Semiconductor Corporation
PO100HSTL22A
02/13/07
Dual LVTTL/LVCMOS to Differential HSTL Translator
Ordering Information
Ordering Code
Package
Top-Marking
TA
PO100HSTL22ASU
8 pin SOIC
Tube
Pb-free & Green
PO100HSTL22AS
-40°C to 85°C
PO100HSTL22ASR
8 pin SOIC
Tape and reel
Pb-free & Green
PO100HSTL22AS
-40°C to 85°C
PO100HSTL22ATU
8 pin TSSOP
Tube
Pb-free & Green
PO100HSTL22TS
-40°C to 85°C
PO100HSTL22ATR
8 pin TSSOP
Tape and reel
Pb-free & Green
PO100HSTL22TS
-40°C to 85°C
6
Copyright © Potato Semiconductor Corporation
PO100HSTL23A
Dual Differential LVDS/LVPECL/HSTL to LVTTL Translator
02/13/07
DESCRIPTION:
FEATURES:
• Patented Technology
• Differential LVDS/LVPECL/HSTL to LVTTL
Translator
• Operating frequency up to 1GHz with 2pf load
• Operating frequency up to 800MHz with 5pf load
• Operating frequency up to 450MHz with 15pf load
• Very low output pin to pin skew < 150ps
• Propagation delay < 1.8ns max with 15pf load
• 2.4V to 3.6V power supply
• Industrial temperature range: –40°C to 85°C
• Available in 8-pin SOIC package
• Available in 8-pin TSSOP package
Pin Configuration
Potato Semiconductor’s PO100HSTL23A is
designed for world top performance using
submicron CMOS technology to achieve 1GHz
LVTTL output frequency with less than 1.8ns
propagation delay.
The PO100HSTL23A is a low-skew, The small
outline 8 pin package and the low skew design to
make it ideal for applica- tions which require the
translation of a clock or a data signal.
Logic Block Diagram
D0
D0
1
8
VCC
D0
2
7
Q0
Q0
D0
D1
3
6
Q1
D1
4
5
GND
LVDS
LVPEC
HSTL
D1
LVTTL
Q1
D1
Pin Description
Pin
Function
Q0, Q1
LVTTL Outputs
D0, D1
D0, D1
Differential
LVDS/LVPECL/HSTL Inputs
VCC
Positive Supply
GND
Ground
1
Copyright © Potato Semiconductor Corporation
PO100HSTL23A
02/13/07
Dual Differential HSTL/LVDS to LVTTL Translator
Maximum Ratings
Description
Max
Unit
Storage Temperature
-65 to 150
°C
Operation Temperature
-40 to 85
°C
Operation Voltage
-0.5 to +4.6
V
Input Voltage
-0.5 to Vcc
V
Output Voltage
-0.5 to Vcc+0.5
V
Note:
stresses greater than listed under
Maximum
Ratings
may
cause
permanent damage to the device. This
is a stress rating only and functional
operation of the device at these or any
other conditions above those indicated
in the operational sections of this
specification is not implied. Exposure
to absolute maximum rating conditions
for extended periods may affect
reliability specification is not implied.
Pin Characteristics
Symbol
Parameter
CIN
Input Capacitance
RPULLUP
RPULLDOWN
Test Conditions
Minimum
Typical
Maximum
Units
4
pF
Input Pullup Resistor
88
KΩ
Input Pulldown Resistor
88
KΩ
DC Electrical Characteristics
Symbol
Description
VOH
Output High voltage
VOL
Test Conditions
Min
Typ
Max
Unit
Vcc=3V Vin=VIH or VIL, IOH= -12mA
2.4
3
-
V
Output Low voltage
Vcc=3V Vin=VIH or VIL, IOH=12mA
-
0.3
0.5
V
VIH
Input High voltage
Guaranteed Logic HIGH Level (Input Pin)
2
-
Vcc
V
VIL
Input Low voltage
Guaranteed Logic LOW Level (Input Pin)
-0.5
-
0.8
V
IIH
Input High current
Vcc = 3.6V and Vin = Vcc
-
-
1
uA
IIL
Input Low current
Vcc = 3.6V and Vin = 0V
-
-
-1
uA
VIK
Clamp diode voltage
Vcc = Min. And IIN = -18mA
-0.7
-1.2
-
V
Notes:
1.
2.
3.
4.
5.
For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
Typical values are at Vcc = 3.3V, 25 °C ambient.
This parameter is guaranteed but not tested.
Not more than one output should be shorted at one time. Duration of the test should not exceed one second.
VoH = Vcc – 0.6V at rated current
2
Copyright © Potato Semiconductor Corporation
PO100HSTL23A
02/13/07
Dual Differential HSTL/LVDS to LVTTL Translator
Power Supply Characteristics
Symbol
IccQ
Description
Quiescent Power Supply Current
Test Conditions (1)
Min
Typ
Max
Unit
Vcc=Max, Vin=Vcc or GND
-
0.1
30
uA
Notes:
1.
2.
3.
4.
5.
For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
Typical values are at Vcc = 3.3V, 25°C ambient.
This parameter is guaranteed but not tested.
Not more than one output should be shorted at one time. Duration of the test should not exceed one second.
VoH = Vcc – 0.6V at rated current
Switching Characteristics
Symbol
tPD
Description
Propagation Delay D to Output pair
tr/tf
tsk(o)
tsk(pp)
Rise/Fall Time
Test Conditions (1)
M ax
Unit
CL = 15pF
1.8
ns
0.8V – 2.0V
ns
ps
Output Pin to Pin Skew (Same Package)
CL = 15pF, 125MHz
0.8
150
Output Skew (Different Package)
CL = 15pF, 125MHz
300
ps
MHz
MHz
fmax
fmax
Input Frequency
CL =15pF
Input Frequency
CL = 5pF
450
250
800
300
fmax
Input Frequency
CL = 2pF
1000
400
MHz
Notes:
1. See test circuits and waveforms.
2. tpLH, tpHL, tsk(p), and tsk(o) are production tested. All other parameters guaranteed but not production tested.
3. Airflow of 1m/s is recommended for frequencies above 133MHz
Test Circuit
Vcc
50Ω
Pulse
Generator
V+
V+
V-
V-
50Ω
D.U.T
15pF
to
2pF
3
Copyright © Potato Semiconductor Corporation
PO100HSTL23A
02/13/07
Dual Differential HSTL/LVDS to LVTTL Translator
Test Waveforms
FIGURE 1.
LVDS/ PECL/ ECL/ HSTL /DIFFERENTIAL INPUT WAVEFORM DEFINITIONS
VCC
VCC= 3.3V
VIH
VPP
VPP RANGE
0V-VCC
VIL
VEE=0.0V
VEE
FIGURE 2.
LVTTL OUTPUT
tr,tf,
VO
FIGURE 3.
Propogation Delay, Output pulse skew, and output-to-output skew for D to output
INPUT
CLOCK
VPP
TPLH
TPD
TPHL
OUTPUT
CLOCK
VO
tSK(O)
ANOTHER
OUTPUT
CLOCK
4
Copyright © Potato Semiconductor Corporation
PO100HSTL23A
Dual Differential HSTL/LVDS to LVTTL Translator
02/13/07
Packaging Mechanical Drawing: 8 pin SOIC
8
0-8˚
.149
.157
3.78
3.99
.0099
.0196
0.25
x 45˚
0.50
.016
.050
0.40
1.27
.2284
.2440
5.80
6.20
1
.189
.196
4.80
5.00
.053
.068
.016
.026
0.406
0.660
.0075
.0098
1.35
1.75
0.19
0.25
SEATING PLANE
REF
.050
BSC
1.27
.0040 0.10
.0098 0.25
.013 0.330
.020 0.508
X.XX DENOTES DIMENSIONS
X.XX IN MILLIMETERS
Packaging Mechanical Drawing: 8 pin TSSOP
8
SEATING PLANE
X.XX DENOTES DIMENSIONS
X.XX IN MILLIMETERS
5
Copyright © Potato Semiconductor Corporation
PO100HSTL23A
02/13/07
Dual Differential HSTL/LVDS to LVTTL Translator
Ordering Information
Ordering Code
Package
Top-Marking
TA
PO100HSTL23ASU
8 pin SOIC
Tube
Pb-free & Green
PO100HSTL23AS
-40°C to 85°C
PO100HSTL23ASR
8 pin SOIC
Tape and reel
Pb-free & Green
PO100HSTL23AS
-40°C to 85°C
PO100HSTL23ATU
8 pin TSSOP
Tube
Pb-free & Green
PO100HSTL23AT
-40°C to 85°C
PO100HSTL23ATR
8 pin TSSOP
Tape and reel
Pb-free & Green
PO100HSTL23AT
-40°C to 85°C
6
Copyright © Potato Semiconductor Corporation