RENESAS R5F21336DNFP

Datasheet
R8C/33D Group
RENESAS MCU
1.
REJ03B0287-0100
Rev.1.00
Mar 31, 2010
Overview
1.1
Features
The R8C/33D Group of single-chip MCUs incorporates the R8C CPU core, employing sophisticated instructions
for a high level of efficiency. With 1 Mbyte of address space, and it is capable of executing instructions at high
speed. In addition, the CPU core boasts a multiplier for high-speed operation processing.
Power consumption is low, and the supported operating modes allow additional power control. These MCUs are
designed to maximize EMI/EMS performance.
Integration of many peripheral functions, including multifunction timer and serial interface, reduces the number of
system components.
1.1.1
Applications
Electronic household appliances, office equipment, audio equipment, consumer equipment, etc.
REJ03B0287-0100 Rev.1.00
Mar 31, 2010
Page 1 of 42
R8C/33D Group
1.1.2
1. Overview
Specifications
Tables 1.1 and 1.2 outline the Specifications for R8C/33D Group.
Table 1.1
Item
CPU
Specifications for R8C/33D Group (1)
Function
Central processing
unit
Memory
Power Supply
Voltage
Detection
I/O Ports
ROM, RAM
Voltage detection
circuit
Clock
Clock generation
circuits
Programmable I/O
ports
Interrupts
Watchdog Timer
Timer
Timer RA
Timer RB
Timer RC
Timer RE
Serial
Interface
UART0
UART2
A/D Converter
Comparator B
REJ03B0287-0100 Rev.1.00
Mar 31, 2010
Specification
R8C CPU core
• Number of fundamental instructions: 89
• Minimum instruction execution time:
50 ns (f(XIN) = 20 MHz, VCC = 2.7 to 5.5 V)
200 ns (f(XIN) = 5 MHz, VCC = 1.8 to 5.5 V)
• Multiplier: 16 bits × 16 bits → 32 bits
• Multiply-accumulate instruction: 16 bits × 16 bits + 32 bits → 32 bits
• Operation mode: Single-chip mode (address space: 1 Mbyte)
Refer to Table 1.3 Product List for R8C/33D Group.
• Power-on reset
• Voltage detection 3 (detection level of voltage detection 0 and voltage
detection 1 selectable)
• Input-only: 1 pin
• CMOS I/O ports: 27, selectable pull-up resistor
• High current drive ports: 27
• 4 circuits: XIN clock oscillation circuit,
XCIN clock oscillation circuit (32 kHz),
High-speed on-chip oscillator (with frequency adjustment function),
Low-speed on-chip oscillator
• Oscillation stop detection: XIN clock oscillation stop detection function
• Frequency divider circuit: Dividing selectable 1, 2, 4, 8, and 16
• Low power consumption modes:
Standard operating mode (high-speed clock, low-speed clock, high-speed
on-chip oscillator, low-speed on-chip oscillator), wait mode, stop mode
Real-time clock (timer RE)
• Number of interrupt vectors: 69
• External Interrupt: 7 (INT × 3, Key input × 4)
• Priority levels: 7 levels
• 14 bits × 1 (with prescaler)
• Reset start selectable
• Low-speed on-chip oscillator for watchdog timer selectable
8 bits × 1 (with 8-bit prescaler)
Timer mode (period timer), pulse output mode (output level inverted every
period), event counter mode, pulse width measurement mode, pulse period
measurement mode
8 bits × 1 (with 8-bit prescaler)
Timer mode (period timer), programmable waveform generation mode (PWM
output), programmable one-shot generation mode, programmable wait oneshot generation mode
16 bits × 1 (with 4 capture/compare registers)
Timer mode (input capture function, output compare function), PWM mode
(output 3 pins), PWM2 mode (PWM output pin)
8 bits × 1
Real-time clock mode (count seconds, minutes, hours, days of week), output
compare mode
Clock synchronous serial I/O/UART
Clock synchronous serial I/O/UART, I2C mode (I2C-bus),
multiprocessor communication function
10-bit resolution × 12 channels, includes sample and hold function, with sweep
mode
2 circuits
Page 2 of 42
R8C/33D Group
Table 1.2
Item
Flash Memory
1. Overview
Specifications for R8C/33D Group (2)
Function
Operating Frequency/Supply
Voltage
Current Consumption
Operating Ambient Temperature
Package
Specification
• Programming and erasure voltage: VCC = 2.7 to 5.5 V
• Programming and erasure endurance: 1,000 times (program ROM)
• Program security: ROM code protect, ID code check
• Debug functions: On-chip debug, on-board flash rewrite function
f(XIN) = 20 MHz (VCC = 2.7 to 5.5 V)
f(XIN) = 5 MHz (VCC = 1.8 to 5.5 V)
Typ. 6.5 mA (VCC = 5.0 V, f(XIN) = 20 MHz)
Typ. 3.5 mA (VCC = 3.0 V, f(XIN) = 10 MHz)
Typ. 3.5 µA (VCC = 3.0 V, wait mode (f(XCIN) = 32 kHz))
Typ. 2.0 µA (VCC = 3.0 V, stop mode)
-20 to 85°C (N version)
-40 to 85°C (D version) (1)
32-pin LQFP
Package code: PLQP0032GB-A (previous code: 32P6U-A)
Note:
1. Specify the D version if D version functions are to be used.
REJ03B0287-0100 Rev.1.00
Mar 31, 2010
Page 3 of 42
R8C/33D Group
1.2
1. Overview
Product List
Table 1.3 lists Product List for R8C/33D Group, and Figure 1.1 shows a Part Number, Memory Size, and Package
of R8C/33D Group.
Table 1.3
Product List for R8C/33D Group
Part No.
R5F21331DNFP
R5F21332DNFP
R5F21334DNFP
R5F21335DNFP
R5F21336DNFP
R5F21331DDFP (D)
R5F21332DDFP (D)
R5F21334DDFP (D)
R5F21335DDFP (D)
R5F21336DDFP (D)
ROM Capacity
4 Kbytes
8 Kbytes
16 Kbytes
24 Kbytes
32 Kbytes
4 Kbytes
8 Kbytes
16 Kbytes
24 Kbytes
32 Kbytes
Current of Mar. 2010
RAM Capacity
1 Kbyte
1 Kbyte
1 Kbyte
1 Kbyte
1 Kbyte
1 Kbyte
1 Kbyte
1 Kbyte
1 Kbyte
1 Kbyte
Package Type
PLQP0032GB-A
PLQP0032GB-A
PLQP0032GB-A
PLQP0032GB-A
PLQP0032GB-A
PLQP0032GB-A
PLQP0032GB-A
PLQP0032GB-A
PLQP0032GB-A
PLQP0032GB-A
Remarks
N version
D version
(D): Under development
Part No.
R 5 F 21 33 6 D N FP
Package type:
FP: PLQP0032GB-A (0.8 mm pin-pitch, 7 mm square body)
Classification
N: Operating ambient temperature -20°C to 85°C
D: Operating ambient temperature -40°C to 85°C
ROM capacity
1: 4 KB
2: 8 KB
4: 16 KB
5: 24 KB
6: 32 KB
R8C/33D Group
R8C/3x Series
Memory type
F: Flash memory
Renesas MCU
Renesas semiconductor
Figure 1.1
Part Number, Memory Size, and Package of R8C/33D Group
REJ03B0287-0100 Rev.1.00
Mar 31, 2010
Page 4 of 42
R8C/33D Group
1.3
1. Overview
Block Diagram
Figure 1.2 shows a Block Diagram.
I/O ports
8
8
3
5
Port P0
Port P1
Port P2
Port P3
3
1
Port P4
Peripheral functions
Timers
UART or
clock synchronous serial I/O
(8 bits × 2)
System clock generation
circuit
Timer RA (8 bits × 1)
Timer RB (8 bits × 1)
Timer RC (16 bits × 1)
Timer RE (8 bits × 1)
XIN-XOUT
High-speed on-chip oscillator
Low-speed on-chip oscillator
XCIN-XCOUT
Watchdog timer
(14 bits)
Low-speed on-chip oscillator
for watchdog timer
A/D converter
(10 bits × 12 channels)
Voltage detection circuit
Comparator B
Memory
R8C CPU core
R0H
R1H
R0L
R1L
R2
R3
SB
ISP
INTB
A0
A1
FB
ROM (1)
USP
RAM (2)
PC
FLG
Multiplier
Notes:
1. ROM size varies with MCU type.
2. RAM size varies with MCU type.
Figure 1.2
Block Diagram
REJ03B0287-0100 Rev.1.00
Mar 31, 2010
Page 5 of 42
R8C/33D Group
1.4
1. Overview
Pin Assignment
P1_0/AN8/KI0(/TRCIOD)
P1_1/AN9/KI1(/TRCIOA/TRCTRG)
P1_2/AN10/Kl2(/TRCIOB)
P1_3/AN11/Kl3/TRBO(/TRCIOC)
P1_4(/TXD0/TRCCLK)
P1_5(/INT1/RXD0/TRAIO)
P1_6/IVREF1(/CLK0)
P1_7/IVCMP1/INT1(/TRAIO)
Figure 1.3 shows Pin Assignment (Top View). Table 1.4 outlines the Pin Name Information by Pin Number.
24 23 22 21 20 19 18 17
P0_7/AN0(/TRCIOC)
25
16
P0_6/AN1(/TRCIOD)
P0_5/AN2(/TRCIOB)
P0_4/AN3/TREO(/TRCIOB)
P0_3/AN4(/TRCIOB)
P0_2/AN5(/TRCIOA/TRCTRG)
P0_1/AN6(/TRCIOA/TRCTRG)
P0_0/AN7(/TRCIOA/TRCTRG)
26
15
27
14
R8C/33D Group
13
28
29
12
PLQP0032GB-A
(32P6U-A)
(top view)
30
31
11
10
9
32
3
4
5
6
7
8
RESET
P4_7/XOUT(/XCOUT)
VSS/AVSS
P4_6/XIN(/XCIN)
VCC/AVCC
P3_7/TRAO(/RXD2/SCL2/TXD2/SDA2)
2
P4_2/VREF
MODE
1
P4_5/ADTRG/INT0(/RXD2/SCL2)
P3_1(/TRBO)
P2_0(/INT1/TRCIOB)
P2_1(/TRCIOC)
P2_2(/TRCIOD)
P3_3/IVCMP3/INT3(/CTS2/RTS2/TRCCLK)
P3_4/IVREF3(/RXD2/SCL2/TXD2/SDA2/TRCIOC)
P3_5(/CLK2/TRCIOD)
Notes:
1. Can be assigned to the pin in parentheses by a program.
2. Confirm the pin 1 position on the package by referring to the package dimensions.
Figure 1.3
Pin Assignment (Top View)
REJ03B0287-0100 Rev.1.00
Mar 31, 2010
Page 6 of 42
R8C/33D Group
Table 1.4
1. Overview
Pin Name Information by Pin Number
Pin
Number
Control Pin
1
2
3
MODE
4
5
6
7
8
Port
Interrupt
P4_2
RESET
XOUT(/XCOUT)
VSS/AVSS
XIN(/XCIN)
VCC/AVCC
I/O Pin Functions for Peripheral Modules
A/D Converter,
Timer
Serial Interface
Comparator B
VREF
P4_7
P4_6
P3_7
TRAO
9
10
P3_5
P3_4
(TRCIOD)
(TRCIOC)
11
P3_3
12
13
14
P2_2
P2_1
P2_0
15
16
P3_1
P4_5
17
P1_7
18
19
P1_6
P1_5
20
21
P1_4
P1_3
22
INT3
(TRCCLK)
(INT1)
(TRCIOD)
(TRCIOC)
(TRCIOB)
(RXD2/SCL2/
TXD2/SDA2)
(CLK2)
(RXD2/SCL2/
TXD2/SDA2)
IVREF3
(CTS2/RTS2)
IVCMP3
(RXD2/SCL2)
ADTRG
IVCMP1
(CLK0)
(RXD0)
IVREF1
(TRBO)
INT0
INT1
(TRAIO)
(INT1)
(TRAIO)
KI3
(TRCCLK)
TRBO(/TRCIOC)
P1_2
KI2
(TRCIOB)
AN10
23
P1_1
KI1
(TRCIOA/TRCTRG)
AN9
24
P1_0
KI0
(TRCIOD)
AN8
25
26
27
28
29
30
31
32
P0_7
P0_6
P0_5
P0_4
P0_3
P0_2
P0_1
P0_0
(TRCIOC)
(TRCIOD)
(TRCIOB)
TREO(/TRCIOB)
(TRCIOB)
(TRCIOA/TRCTRG)
(TRCIOA/TRCTRG)
(TRCIOA/TRCTRG)
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
(TXD0)
AN11
Note:
1. Can be assigned to the pin in parentheses by a program.
REJ03B0287-0100 Rev.1.00
Mar 31, 2010
Page 7 of 42
R8C/33D Group
1.5
1. Overview
Pin Functions
Table 1.5 lists Pin Functions.
Table 1.5
Pin Functions
Item
Power supply input
Analog power
supply input
Reset input
Pin Name
VCC, VSS
AVCC, AVSS
I/O Type
Description
–
Apply 1.8 V to 5.5 V to the VCC pin. Apply 0 V to the VSS pin.
–
Power supply for the A/D converter.
Connect a capacitor between AVCC and AVSS.
I
Input “L” on this pin resets the MCU.
MODE
XIN clock input
XIN clock output
RESET
MODE
XIN
XOUT
XCIN clock input
XCIN clock output
XCIN
XCOUT
I
O
INT interrupt input
INT0, INT1, INT3
I
Key input interrupt
KI0 to KI3
TRAIO
TRAO
TRBO
TRCCLK
TRCTRG
TRCIOA, TRCIOB,
TRCIOC, TRCIOD
TREO
CLK0, CLK2
RXD0, RXD2
TXD0, TXD2
I
Timer RA
Timer RB
Timer RC
Timer RE
Serial interface
CTS2
Reference voltage
input
A/D converter
Comparator B
I/O port
Input port
I
I
I/O
Connect this pin to VCC via a resistor.
These pins are provided for XIN clock generation circuit I/O.
Connect a ceramic resonator or a crystal oscillator between
the XIN and XOUT pins (1). To use an external clock, input it
to the XOUT pin and leave the XIN pin open.
These pins are provided for XCIN clock generation circuit I/O.
Connect a crystal oscillator between the XCIN and XCOUT
pins (1). To use an external clock, input it to the XCIN pin and
leave the XCOUT pin open.
INT interrupt input pins.
INT0 is timer RB, and RC input pin.
Key input interrupt input pins
I/O
O
O
I
I
I/O
Timer RA I/O pin
Timer RA output pin
Timer RB output pin
External clock input pin
External trigger input pin
Timer RC I/O pins
O
I/O
I
O
I
Divided clock output pin
Transfer clock I/O pins
Serial data input pins
Serial data output pins
Transmission control input pin
RTS2
SCL2
O
Reception control output pin
I/O
I2C mode clock I/O pin
SDA2
I/O
VREF
I
I2C mode data I/O pin
Reference voltage input pin to A/D converter
AN0 to AN11
I
I
Analog input pins to A/D converter
A/D external trigger input pin
ADTRG
IVCMP1, IVCMP3
IVREF1, IVREF3
P0_0 to P0_7,
P1_0 to P1_7,
P2_0 to P2_2,
P3_1,
P3_3 to P3_5,
P3_7,
P4_5 to P4_7
P4_2
I
I
I/O
I
Comparator B analog voltage input pins
Comparator B reference voltage input pins
CMOS I/O ports. Each port has an I/O select direction
register, allowing each pin in the port to be directed for input
or output individually.
Any port set to input can be set to use a pull-up resistor or not
by a program.
All ports can be used as LED drive ports.
Input-only port
I: Input
O: Output
I/O: Input and output
Note:
1. Refer to the oscillator manufacturer for oscillation characteristics.
REJ03B0287-0100 Rev.1.00
Mar 31, 2010
Page 8 of 42
R8C/33D Group
2.
2. Central Processing Unit (CPU)
Central Processing Unit (CPU)
Figure 2.1 shows the CPU Registers. The CPU contains 13 registers. R0, R1, R2, R3, A0, A1, and FB configure a
register bank. There are two sets of register bank.
b31
b15
R2
R3
b8b7
b0
R0H (high-order of R0) R0L (low-order of R0)
R1H (high-order of R1) R1L (low-order of R1)
Data registers (1)
R2
R3
A0
A1
FB
b19
b15
Address registers (1)
Frame base register (1)
b0
Interrupt table register
INTBL
INTBH
The 4 high order bits of INTB are INTBH and
the 16 low order bits of INTB are INTBL.
b19
b0
Program counter
PC
b15
b0
USP
User stack pointer
ISP
Interrupt stack pointer
SB
Static base register
b15
b0
FLG
b15
b8
IPL
b7
Flag register
b0
U I O B S Z D C
Carry flag
Debug flag
Zero flag
Sign flag
Register bank select flag
Overflow flag
Interrupt enable flag
Stack pointer select flag
Reserved bit
Processor interrupt priority level
Reserved bit
Note:
1. These registers comprise a register bank. There are two register banks.
Figure 2.1
CPU Registers
REJ03B0287-0100 Rev.1.00
Mar 31, 2010
Page 9 of 42
R8C/33D Group
2.1
2. Central Processing Unit (CPU)
Data Registers (R0, R1, R2, and R3)
R0 is a 16-bit register for transfer, arithmetic, and logic operations. The same applies to R1 to R3. R0 can be split
into high-order bits (R0H) and low-order bits (R0L) to be used separately as 8-bit data registers. R1H and R1L are
analogous to R0H and R0L. R2 can be combined with R0 and used as a 32-bit data register (R2R0). R3R1 is
analogous to R2R0.
2.2
Address Registers (A0 and A1)
A0 is a 16-bit register for address register indirect addressing and address register relative addressing. It is also
used for transfer, arithmetic, and logic operations. A1 is analogous to A0. A1 can be combined with A0 and as a 32bit address register (A1A0).
2.3
Frame Base Register (FB)
FB is a 16-bit register for FB relative addressing.
2.4
Interrupt Table Register (INTB)
INTB is a 20-bit register that indicates the starting address of an interrupt vector table.
2.5
Program Counter (PC)
PC is 20 bits wide and indicates the address of the next instruction to be executed.
2.6
User Stack Pointer (USP) and Interrupt Stack Pointer (ISP)
The stack pointers (SP), USP and ISP, are each 16 bits wide. The U flag of FLG is used to switch between
USP and ISP.
2.7
Static Base Register (SB)
SB is a 16-bit register for SB relative addressing.
2.8
Flag Register (FLG)
FLG is an 11-bit register indicating the CPU state.
2.8.1
Carry Flag (C)
The C flag retains carry, borrow, or shift-out bits that have been generated by the arithmetic and logic unit.
2.8.2
Debug Flag (D)
The D flag is for debugging only. Set it to 0.
2.8.3
Zero Flag (Z)
The Z flag is set to 1 when an arithmetic operation results in 0; otherwise to 0.
2.8.4
Sign Flag (S)
The S flag is set to 1 when an arithmetic operation results in a negative value; otherwise to 0.
2.8.5
Register Bank Select Flag (B)
Register bank 0 is selected when the B flag is 0. Register bank 1 is selected when this flag is set to 1.
2.8.6
Overflow Flag (O)
The O flag is set to 1 when an operation results in an overflow; otherwise to 0.
REJ03B0287-0100 Rev.1.00
Mar 31, 2010
Page 10 of 42
R8C/33D Group
2.8.7
2. Central Processing Unit (CPU)
Interrupt Enable Flag (I)
The I flag enables maskable interrupts.
Interrupts are disabled when the I flag is set to 0, and are enabled when the I flag is set to 1. The I flag is set to 0
when an interrupt request is acknowledged.
2.8.8
Stack Pointer Select Flag (U)
ISP is selected when the U flag is set to 0; USP is selected when the U flag is set to 1.
The U flag is set to 0 when a hardware interrupt request is acknowledged or the INT instruction of software
interrupt numbers 0 to 31 is executed.
2.8.9
Processor Interrupt Priority Level (IPL)
IPL is 3 bits wide and assigns processor interrupt priority levels from level 0 to level 7.
If a requested interrupt has higher priority than IPL, the interrupt is enabled.
2.8.10
Reserved Bit
If necessary, set to 0. When read, the content is undefined.
REJ03B0287-0100 Rev.1.00
Mar 31, 2010
Page 11 of 42
R8C/33D Group
3.
3. Memory
Memory
3.1
R8C/33D Group
Figure 3.1 is a Memory Map of R8C/33D Group. The R8C/33D Group has a 1-Mbyte address space from addresses
00000h to FFFFFh. The internal ROM (program ROM) is allocated lower addresses, beginning with address
0FFFFh. For example, a 32-Kbyte internal ROM area is allocated addresses 08000h to 0FFFFh.
The fixed interrupt vector table is allocated addresses 0FFDCh to 0FFFFh. The starting address of each interrupt
routine is stored here.
The internal RAM is allocated higher addresses, beginning with address 00400h. For example, a 1-Kbyte internal
RAM area is allocated addresses 00400h to 007FFh. The internal RAM is used not only for data storage but also as
a stack area when a subroutine is called or when an interrupt request is acknowledged.
Special function registers (SFRs) are allocated addresses 00000h to 002FFh. Peripheral function control registers
are allocated here. All unallocated spaces within the SFRs are reserved and cannot be accessed by users.
00000h
002FFh
SFR
(Refer to 4. Special
Function Registers
(SFRs))
00400h
Internal RAM
0FFD8h
0XXXXh
Reserved area
0FFDCh
Undefined instruction
Overflow
BRK instruction
Address match
Single step
Watchdog timer, oscillation stop detection, voltage monitor
0YYYYh
(Reserved)
(Reserved)
Reset
Internal ROM
(program ROM)
0FFFFh
0FFFFh
FFFFFh
Note:
1. The blank areas are reserved and cannot be accessed by users.
Internal ROM
Part Number
Figure 3.1
Internal RAM
Size
Address 0YYYYh
Size
Address 0XXXXh
R5F21331DNFP, R5F21331DDFP
R5F21332DNFP, R5F21332DDFP
4 Kbytes
0F000h
1 Kbyte
007FFh
8 Kbytes
0E000h
1 Kbyte
007FFh
R5F21334DNFP, R5F21334DDFP
R5F21335DNFP, R5F21335DDFP
16 Kbytes
24 Kbytes
0C000h
0A000h
1 Kbyte
1 Kbyte
007FFh
007FFh
R5F21336DNFP, R5F21336DDFP
32 Kbytes
08000h
1 Kbyte
007FFh
Memory Map of R8C/33D Group
REJ03B0287-0100 Rev.1.00
Mar 31, 2010
Page 12 of 42
R8C/33D Group
4.
4. Special Function Registers (SFRs)
Special Function Registers (SFRs)
An SFR (special function register) is a control register for a peripheral function. Tables 4.1 to 4.8 list the special
function registers and Table 4.9 lists the ID Code Areas and Option Function Select Area.
Table 4.1
Address
0000h
0001h
0002h
0003h
0004h
0005h
0006h
0007h
0008h
0009h
000Ah
000Bh
000Ch
000Dh
000Eh
000Fh
0010h
0011h
0012h
0013h
0014h
0015h
0016h
0017h
0018h
0019h
001Ah
001Bh
001Ch
001Dh
001Eh
001Fh
0020h
0021h
0022h
0023h
0024h
0025h
0026h
0027h
0028h
0029h
002Ah
002Bh
002Ch
002Dh
002Eh
002Fh
0030h
0031h
0032h
0033h
0034h
0035h
0036h
0037h
0038h
SFR Information (1) (1)
Register
Symbol
After Reset
Processor Mode Register 0
Processor Mode Register 1
System Clock Control Register 0
System Clock Control Register 1
Module Standby Control Register
System Clock Control Register 3
Protect Register
Reset Source Determination Register
Oscillation Stop Detection Register
Watchdog Timer Reset Register
Watchdog Timer Start Register
Watchdog Timer Control Register
PM0
PM1
CM0
CM1
MSTCR
CM3
PRCR
RSTFR
OCD
WDTR
WDTS
WDTC
00h
00h
00101000b
00100000b
00h
00h
00h
0XXXXXXXb (2)
00000100b
XXh
XXh
00111111b
High-Speed On-Chip Oscillator Control Register 7
FRA7
When shipping
Count Source Protection Mode Register
CSPR
00h
10000000b (3)
High-Speed On-Chip Oscillator Control Register 0
High-Speed On-Chip Oscillator Control Register 1
High-Speed On-Chip Oscillator Control Register 2
On-Chip Reference Voltage Control Register
FRA0
FRA1
FRA2
OCVREFCR
00h
When shipping
00h
00h
Clock Prescaler Reset Flag
High-Speed On-Chip Oscillator Control Register 4
High-Speed On-Chip Oscillator Control Register 5
High-Speed On-Chip Oscillator Control Register 6
CPSRF
FRA4
FRA5
FRA6
00h
When shipping
When shipping
When shipping
High-Speed On-Chip Oscillator Control Register 3
Voltage Monitor Circuit Control Register
Voltage Monitor Circuit Edge Select Register
FRA3
CMPA
VCAC
When shipping
00h
00h
Voltage Detect Register 1
Voltage Detect Register 2
VCA1
VCA2
00001000b
00h (4)
00100000b (5)
Voltage Detection 1 Level Select Register
VD1LS
00000111b
Voltage Monitor 0 Circuit Control Register
VW0C
1100X010b (4)
1100X011b (5)
10001010b
0039h
Voltage Monitor 1 Circuit Control Register
VW1C
X: Undefined
Notes:
1. The blank areas are reserved and cannot be accessed by users.
2. The CWR bit in the RSTFR register is set to 0 after power-on and voltage monitor 0 reset. Hardware reset, Software reset, or watchdog timer
reset does not affect this bit.
3. The CSPROINI bit in the OFS register is set to 0.
4. The LVDAS bit in the OFS register is set to 1.
5. The LVDAS bit in the OFS register is set to 0.
REJ03B0287-0100 Rev.1.00
Mar 31, 2010
Page 13 of 42
R8C/33D Group
Table 4.2
Address
003Ah
003Bh
003Ch
003Dh
003Eh
003Fh
0040h
0041h
0042h
0043h
0044h
0045h
0046h
0047h
0048h
0049h
004Ah
004Bh
004Ch
004Dh
004Eh
004Fh
0050h
0051h
0052h
0053h
0054h
0055h
0056h
0057h
0058h
0059h
005Ah
005Bh
005Ch
005Dh
005Eh
005Fh
0060h
0061h
0062h
0063h
0064h
0065h
0066h
0067h
0068h
0069h
006Ah
006Bh
006Ch
006Dh
006Eh
006Fh
0070h
0071h
0072h
0073h
0074h
0075h
0076h
0077h
0078h
0079h
007Ah
007Bh
007Ch
007Dh
007Eh
007Fh
4. Special Function Registers (SFRs)
SFR Information (2) (1)
Register
Voltage Monitor 2 Circuit Control Register
VW2C
Symbol
After Reset
10000010b
Flash Memory Ready Interrupt Control Register
FMRDYIC
XXXXX000b
Timer RC Interrupt Control Register
TRCIC
XXXXX000b
Timer RE Interrupt Control Register
UART2 Transmit Interrupt Control Register
UART2 Receive Interrupt Control Register
Key Input Interrupt Control Register
A/D Conversion Interrupt Control Register
TREIC
S2TIC
S2RIC
KUPIC
ADIC
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
UART0 Transmit Interrupt Control Register
UART0 Receive Interrupt Control Register
S0TIC
S0RIC
XXXXX000b
XXXXX000b
Timer RA Interrupt Control Register
TRAIC
XXXXX000b
Timer RB Interrupt Control Register
INT1 Interrupt Control Register
INT3 Interrupt Control Register
TRBIC
INT1IC
INT3IC
XXXXX000b
XX00X000b
XX00X000b
INT0 Interrupt Control Register
UART2 Bus Collision Detection Interrupt Control Register
INT0IC
U2BCNIC
XX00X000b
XXXXX000b
Voltage Monitor 1 Interrupt Control Register
Voltage Monitor 2 Interrupt Control Register
VCMP1IC
VCMP2IC
XXXXX000b
XXXXX000b
X: Undefined
Note:
1. The blank areas are reserved and cannot be accessed by users.
REJ03B0287-0100 Rev.1.00
Mar 31, 2010
Page 14 of 42
R8C/33D Group
Table 4.3
Address
0080h
0081h
0082h
0083h
0084h
0085h
0086h
0087h
0088h
0089h
008Ah
008Bh
008Ch
008Dh
008Eh
008Fh
0090h
0091h
0092h
0093h
0094h
0095h
0096h
0097h
0098h
0099h
009Ah
009Bh
009Ch
009Dh
009Eh
009Fh
00A0h
00A1h
00A2h
00A3h
00A4h
00A5h
00A6h
00A7h
00A8h
00A9h
00AAh
00ABh
00ACh
00ADh
00AEh
00AFh
00B0h
00B1h
00B2h
00B3h
00B4h
00B5h
00B6h
00B7h
00B8h
00B9h
00BAh
00BBh
00BCh
00BDh
00BEh
00BFh
4. Special Function Registers (SFRs)
SFR Information (3) (1)
Register
Symbol
After Reset
UART0 Transmit/Receive Mode Register
UART0 Bit Rate Register
UART0 Transmit Buffer Register
U0MR
U0BRG
U0TB
UART0 Transmit/Receive Control Register 0
UART0 Transmit/Receive Control Register 1
UART0 Receive Buffer Register
U0C0
U0C1
U0RB
UART2 Transmit/Receive Mode Register
UART2 Bit Rate Register
UART2 Transmit Buffer Register
U2MR
U2BRG
U2TB
UART2 Transmit/Receive Control Register 0
UART2 Transmit/Receive Control Register 1
UART2 Receive Buffer Register
U2C0
U2C1
U2RB
UART2 Digital Filter Function Select Register
URXDF
00h
XXh
XXh
XXh
00001000b
00000010b
XXh
XXh
00h
XXh
XXh
XXh
00001000b
00000010b
XXh
XXh
00h
UART2 Special Mode Register 5
UART2 Special Mode Register 4
UART2 Special Mode Register 3
UART2 Special Mode Register 2
UART2 Special Mode Register
U2SMR5
U2SMR4
U2SMR3
U2SMR2
U2SMR
00h
00h
000X0X0Xb
X0000000b
X0000000b
X: Undefined
Note:
1. The blank areas are reserved and cannot be accessed by users.
REJ03B0287-0100 Rev.1.00
Mar 31, 2010
Page 15 of 42
R8C/33D Group
Table 4.4
Address
00C0h
00C1h
00C2h
00C3h
00C4h
00C5h
00C6h
00C7h
00C8h
00C9h
00CAh
00CBh
00CCh
00CDh
00CEh
00CFh
00D0h
00D1h
00D2h
00D3h
00D4h
00D5h
00D6h
00D7h
00D8h
00D9h
00DAh
00DBh
00DCh
00DDh
00DEh
00DFh
00E0h
00E1h
00E2h
00E3h
00E4h
00E5h
00E6h
00E7h
00E8h
00E9h
00EAh
00EBh
00ECh
00EDh
00EEh
00EFh
00F0h
00F1h
00F2h
00F3h
00F4h
00F5h
00F6h
00F7h
00F8h
00F9h
00FAh
00FBh
00FCh
00FDh
00FEh
00FFh
4. Special Function Registers (SFRs)
SFR Information (4) (1)
Register
Symbol
After Reset
XXh
000000XXb
XXh
000000XXb
XXh
000000XXb
XXh
000000XXb
XXh
000000XXb
XXh
000000XXb
XXh
000000XXb
XXh
000000XXb
A/D Register 0
AD0
A/D Register 1
AD1
A/D Register 2
AD2
A/D Register 3
AD3
A/D Register 4
AD4
A/D Register 5
AD5
A/D Register 6
AD6
A/D Register 7
AD7
A/D Mode Register
A/D Input Select Register
A/D Control Register 0
A/D Control Register 1
ADMOD
ADINSEL
ADCON0
ADCON1
00h
11000000b
00h
00h
Port P0 Register
Port P1 Register
Port P0 Direction Register
Port P1 Direction Register
Port P2 Register
Port P3 Register
Port P2 Direction Register
Port P3 Direction Register
Port P4 Register
P0
P1
PD0
PD1
P2
P3
PD2
PD3
P4
XXh
XXh
00h
00h
XXh
XXh
00h
00h
XXh
Port P4 Direction Register
PD4
00h
X: Undefined
Note:
1. The blank areas are reserved and cannot be accessed by users.
REJ03B0287-0100 Rev.1.00
Mar 31, 2010
Page 16 of 42
R8C/33D Group
Table 4.5
Address
0100h
0101h
0102h
0103h
0104h
0105h
0106h
0107h
0108h
0109h
010Ah
010Bh
010Ch
010Dh
010Eh
010Fh
0110h
0111h
0112h
0113h
0114h
0115h
0116h
0117h
0118h
0119h
011Ah
011Bh
011Ch
011Dh
011Eh
011Fh
0120h
0121h
0122h
0123h
0124h
0125h
0126h
0127h
0128h
0129h
012Ah
012Bh
012Ch
012Dh
012Eh
012Fh
0130h
0131h
0132h
0133h
0134h
0135h
0136h
0137h
0138h
0139h
013Ah
013Bh
013Ch
013Dh
013Eh
013Fh
Note:
1.
4. Special Function Registers (SFRs)
SFR Information (5) (1)
Timer RA Control Register
Timer RA I/O Control Register
Timer RA Mode Register
Timer RA Prescaler Register
Timer RA Register
Register
Symbol
TRACR
TRAIOC
TRAMR
TRAPRE
TRA
00h
00h
00h
FFh
FFh
After Reset
Timer RB Control Register
Timer RB One-Shot Control Register
Timer RB I/O Control Register
Timer RB Mode Register
Timer RB Prescaler Register
Timer RB Secondary Register
Timer RB Primary Register
TRBCR
TRBOCR
TRBIOC
TRBMR
TRBPRE
TRBSC
TRBPR
00h
00h
00h
00h
FFh
FFh
FFh
Timer RE Second Data Register / Counter Data Register
Timer RE Minute Data Register / Compare Data Register
Timer RE Hour Data Register
Timer RE Day of Week Data Register
Timer RE Control Register 1
Timer RE Control Register 2
Timer RE Count Source Select Register
TRESEC
TREMIN
TREHR
TREWK
TRECR1
TRECR2
TRECSR
00h
00h
00h
00h
00h
00h
00001000b
Timer RC Mode Register
Timer RC Control Register 1
Timer RC Interrupt Enable Register
Timer RC Status Register
Timer RC I/O Control Register 0
Timer RC I/O Control Register 1
Timer RC Counter
TRCMR
TRCCR1
TRCIER
TRCSR
TRCIOR0
TRCIOR1
TRC
Timer RC General Register A
TRCGRA
Timer RC General Register B
TRCGRB
Timer RC General Register C
TRCGRC
Timer RC General Register D
TRCGRD
Timer RC Control Register 2
Timer RC Digital Filter Function Select Register
Timer RC Output Master Enable Register
Timer RC Trigger Control Register
TRCCR2
TRCDF
TRCOER
TRCADCR
01001000b
00h
01110000b
01110000b
10001000b
10001000b
00h
00h
FFh
FFh
FFh
FFh
FFh
FFh
FFh
FFh
00011000b
00h
01111111b
00h
The blank areas are reserved and cannot be accessed by users.
REJ03B0287-0100 Rev.1.00
Mar 31, 2010
Page 17 of 42
R8C/33D Group
Table 4.6
4. Special Function Registers (SFRs)
SFR Information (6) (1)
Address
0140h
0141h
0142h
0143h
0144h
0145h
0146h
0147h
0148h
0149h
014Ah
014Bh
014Ch
014Dh
014Eh
014Fh
0150h
0151h
0152h
0153h
0154h
0155h
0156h
0157h
0158h
0159h
015Ah
015Bh
015Ch
015Dh
015Eh
015Fh
0160h
0161h
0162h
0163h
0164h
0165h
0166h
0167h
0168h
0169h
016Ah
016Bh
016Ch
016Dh
016Eh
016Fh
0170h
0171h
0172h
0173h
0174h
0175h
0176h
0177h
0178h
0179h
017Ah
017Bh
017Ch
017Dh
017Eh
017Fh
Register
Symbol
After Reset
X: Undefined
Note:
1. The blank areas are reserved and cannot be accessed by users.
REJ03B0287-0100 Rev.1.00
Mar 31, 2010
Page 18 of 42
R8C/33D Group
Table 4.7
Address
0180h
0181h
0182h
0183h
0184h
0185h
0186h
0187h
0188h
0189h
018Ah
018Bh
018Ch
018Dh
018Eh
018Fh
0190h
0191h
0192h
0193h
0194h
0195h
0196h
0197h
0198h
0199h
019Ah
019Bh
019Ch
019Dh
019Eh
019Fh
01A0h
01A1h
01A2h
01A3h
01A4h
01A5h
01A6h
01A7h
01A8h
01A9h
01AAh
01ABh
01ACh
01ADh
01AEh
01AFh
01B0h
01B1h
01B2h
01B3h
01B4h
01B5h
01B6h
01B7h
01B8h
01B9h
01BAh
01BBh
01BCh
01BDh
01BEh
01BFh
4. Special Function Registers (SFRs)
SFR Information (7) (1)
Timer RA Pin Select Register
Timer RB/RC Pin Select Register
Timer RC Pin Select Register 0
Timer RC Pin Select Register 1
Register
Symbol
TRASR
TRBRCSR
TRCPSR0
TRCPSR1
00h
00h
00h
00h
After Reset
UART0 Pin Select Register
U0SR
00h
UART2 Pin Select Register 0
UART2 Pin Select Register 1
U2SR0
U2SR1
00h
00h
INT Interrupt Input Pin Select Register
I/O Function Pin Select Register
INTSR
PINSR
00h
00h
Flash Memory Status Register
FST
10000X00b
Flash Memory Control Register 0
Flash Memory Control Register 1
Flash Memory Control Register 2
FMR0
FMR1
FMR2
00h
00h
00h
X: Undefined
Note:
1. The blank areas are reserved and cannot be accessed by users.
REJ03B0287-0100 Rev.1.00
Mar 31, 2010
Page 19 of 42
R8C/33D Group
Table 4.8
Address
01C0h
01C1h
01C2h
01C3h
01C4h
01C5h
01C6h
01C7h
01C8h
01C9h
01CAh
01CBh
01CCh
01CDh
01CEh
01CFh
01D0h
01D1h
01D2h
01D3h
01D4h
01D5h
01D6h
01D7h
01D8h
01D9h
01DAh
01DBh
01DCh
01DDh
01DEh
01DFh
01E0h
01E1h
01E2h
01E3h
01E4h
01E5h
01E6h
01E7h
01E8h
01E9h
01EAh
01EBh
01ECh
01EDh
01EEh
01EFh
01F0h
01F1h
01F2h
01F3h
01F4h
01F5h
01F6h
01F7h
01F8h
01F9h
01FAh
01FBh
01FCh
01FDh
01FEh
01FFh
4. Special Function Registers (SFRs)
SFR Information (8) (1)
Address Match Interrupt Register 0
Register
Symbol
RMAD0
After Reset
XXh
XXh
0000XXXXb
00h
XXh
XXh
0000XXXXb
Address Match Interrupt Enable Register
Address Match Interrupt Register 1
AIER
RMAD1
Pull-Up Control Register 0
Pull-Up Control Register 1
PUR0
PUR1
00h
00h
Port P1 Drive Capacity Control Register
Port P2 Drive Capacity Control Register
Drive Capacity Control Register 0
Drive Capacity Control Register 1
P1DRR
P2DRR
DRR0
DRR1
00h
00h
00h
00h
Input Threshold Control Register 0
Input Threshold Control Register 1
VLT0
VLT1
00h
00h
Comparator B Control Register 0
INTCMP
00h
External Input Enable Register 0
INTEN
00h
INT Input Filter Select Register 0
INTF
00h
Key Input Enable Register 0
KIEN
00h
X: Undefined
Note:
1. The blank areas are reserved and cannot be accessed by users.
REJ03B0287-0100 Rev.1.00
Mar 31, 2010
Page 20 of 42
R8C/33D Group
4. Special Function Registers (SFRs)
Table 4.9
ID Code Areas and Option Function Select Area
Address
:
FFDBh
:
FFDFh
:
FFE3h
:
FFEBh
:
FFEFh
:
FFF3h
:
FFF7h
:
FFFBh
:
FFFFh
Area Name
Notes:
1.
2.
Option Function Select Register 2
Symbol
OFS2
After Reset
(Note 1)
ID1
(Note 2)
ID2
(Note 2)
ID3
(Note 2)
ID4
(Note 2)
ID5
(Note 2)
ID6
(Note 2)
ID7
(Note 2)
Option Function Select Register
OFS
(Note 1)
The option function select area is allocated in the flash memory, not in the SFRs. Set appropriate values as ROM data by a program.
Do not write additions to the option function select area. If the block including the option function select area is erased, the option function select
area is set to FFh.
When blank products are shipped, the option function select area is set to FFh. It is set to the written value after written by the user.
When factory-programming products are shipped, the value of the option function select area is the value programmed by the user.
The ID code areas are allocated in the flash memory, not in the SFRs. Set appropriate values as ROM data by a program.
Do not write additions to the ID code areas. If the block including the ID code areas is erased, the ID code areas are set to FFh.
When blank products are shipped, the ID code areas are set to FFh. They are set to the written value after written by the user.
When factory-programming products are shipped, the value of the ID code areas is the value programmed by the user.
REJ03B0287-0100 Rev.1.00
Mar 31, 2010
Page 21 of 42
R8C/33D Group
5.
5. Electrical Characteristics
Electrical Characteristics
Table 5.1
Absolute Maximum Ratings
Symbol
Parameter
Rated Value
Unit
−0.3 to 6.5
V
Input voltage
−0.3 to VCC + 0.3
V
VO
Output voltage
−0.3 to VCC + 0.3
V
Pd
Power dissipation
500
mW
Topr
Operating ambient temperature
−20 to 85 (N version) /
−40 to 85 (D version)
°C
Tstg
Storage temperature
−65 to 150
°C
VCC/AVCC
Supply voltage
VI
REJ03B0287-0100 Rev.1.00
Mar 31, 2010
Condition
−40°C ≤ Topr ≤ 85°C
Page 22 of 42
R8C/33D Group
Table 5.2
5. Electrical Characteristics
Recommended Operating Conditions
Symbol
Parameter
Conditions
Standard
Unit
Min.
Typ.
Max.
VCC/AVCC Supply voltage
1.8
–
5.5
V
VSS/AVSS Supply voltage
–
0
–
V
0.8 VCC
–
VCC
V
0.5 VCC
–
VCC
V
2.7 V ≤ VCC < 4.0 V 0.55 VCC
–
VCC
V
1.8 V ≤ VCC < 2.7 V 0.65 VCC
–
VCC
V
4.0 V ≤ VCC ≤ 5.5 V
0.65 VCC
–
VCC
V
2.7 V ≤ VCC < 4.0 V
0.7 VCC
–
VCC
V
1.8 V ≤ VCC < 2.7 V
0.8 VCC
–
VCC
V
Input level selection: 4.0 V ≤ VCC ≤ 5.5 V 0.85 VCC
0.7 VCC
2.7 V ≤ VCC < 4.0 V 0.85 VCC
–
VCC
V
–
VCC
V
1.8 V ≤ VCC < 2.7 V 0.85 VCC
–
VCC
V
1.2
–
VCC
V
0
–
0.2 VCC
V
4.0 V ≤ VCC ≤ 5.5 V
0
–
0.2 VCC
V
2.7 V ≤ VCC < 4.0 V
0
–
0.2 VCC
V
1.8 V ≤ VCC < 2.7 V
0
–
0.2 VCC
V
4.0 V ≤ VCC ≤ 5.5 V
0
–
0.4 VCC
V
2.7 V ≤ VCC < 4.0 V
0
–
0.3 VCC
V
1.8 V ≤ VCC < 2.7 V
0
–
0.2 VCC
V
Input level selection: 4.0 V ≤ VCC ≤ 5.5 V
0.7 VCC
2.7 V ≤ VCC < 4.0 V
0
–
0.55 VCC
V
0
–
0.45 VCC
V
1.8 V ≤ VCC < 2.7 V
0
–
0.35 VCC
V
External clock input (XOUT)
0
–
0.4
V
Sum of all pins IOH(peak)
–
–
−160
mA
VIH
Input “H” voltage
Other than CMOS input
CMOS Input level Input level selection:
input
switching 0.35 VCC
function
(I/O port)
Input level selection:
0.5 VCC
4.0 V ≤ VCC ≤ 5.5 V
External clock input (XOUT)
VIL
Input “L” voltage
Other than CMOS input
CMOS Input level Input level selection:
input
switching 0.35 VCC
function
(I/O port)
Input level selection:
0.5 VCC
IOH(sum)
Peak sum output
“H” current
IOH(sum)
Average sum
Sum of all pins IOH(avg)
output “H” current
–
–
−80
mA
IOH(peak)
Peak output “H”
current
Drive capacity Low
–
–
−10
mA
Drive capacity High
–
–
−40
mA
IOH(avg)
Average output
“H” current
Drive capacity Low
–
–
−5
mA
Drive capacity High
–
–
−20
mA
IOL(sum)
Peak sum output
“L” current
Sum of all pins IOL(peak)
–
–
160
mA
IOL(sum)
Average sum
output “L” current
Sum of all pins IOL(avg)
–
–
80
mA
IOL(peak)
Peak output “L”
current
Drive capacity Low
–
–
10
mA
Drive capacity High
–
–
40
mA
Average output
“L” current
Drive capacity Low
–
–
5
mA
Drive capacity High
–
–
20
mA
–
–
20
MHz
MHz
IOL(avg)
f(XIN)
XIN clock input oscillation frequency
2.7 V ≤ VCC ≤ 5.5 V
1.8 V ≤ VCC < 2.7 V
–
–
5
f(XCIN)
XCIN clock input oscillation frequency
1.8 V ≤ VCC ≤ 5.5 V
–
32.768
50
kHz
2.7 V ≤ VCC ≤ 5.5 V
32
–
40
MHz
MHz
fOCO40M When used as the count source for timer RC (3)
fOCO-F
fOCO-F frequency
-
System clock frequency
f(BCLK)
CPU clock frequency
2.7 V ≤ VCC ≤ 5.5 V
–
–
20
1.8 V ≤ VCC < 2.7 V
–
–
5
MHz
2.7 V ≤ VCC ≤ 5.5 V
–
–
20
MHz
1.8 V ≤ VCC < 2.7 V
–
–
5
MHz
2.7 V ≤ VCC ≤ 5.5 V
–
–
20
MHz
1.8 V ≤ VCC < 2.7 V
–
–
5
MHz
Notes:
1. VCC = 1.8 to 5.5 V at Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified.
2. The average output current indicates the average value of current measured during 100 ms.
3. fOCO40M can be used as the count source for timer RC in the range of VCC = 2.7 V to 5.5 V.
REJ03B0287-0100 Rev.1.00
Mar 31, 2010
Page 23 of 42
R8C/33D Group
5. Electrical Characteristics
P0
P1
P2
P3
P4
Figure 5.1
30 pF
Ports P0 to P4 Timing Measurement Circuit
REJ03B0287-0100 Rev.1.00
Mar 31, 2010
Page 24 of 42
R8C/33D Group
Table 5.3
5. Electrical Characteristics
A/D Converter Characteristics (1)
Symbol
Parameter
–
Resolution
–
Absolute accuracy
Vref = AVCC
10-bit mode
8-bit mode
φAD
Standard
Conditions
A/D conversion clock
–
Tolerance level impedance
tCONV
Conversion time
Max.
Unit
–
–
10
Bit
AN0 to AN7 input,
AN8 to AN11 input
–
–
±3
LSB
Vref = AVCC = 3.3 V
AN0 to AN7 input,
AN8 to AN11 input
–
–
±5
LSB
Vref = AVCC = 3.0 V
AN0 to AN7 input,
AN8 to AN11 input
–
–
±5
LSB
Vref = AVCC = 2.2 V
AN0 to AN7 input,
AN8 to AN11 input
–
–
±5
LSB
Vref = AVCC = 5.0 V
AN0 to AN7 input,
AN8 to AN11 input
–
–
±2
LSB
Vref = AVCC = 3.3 V
AN0 to AN7 input,
AN8 to AN11 input
–
–
±2
LSB
Vref = AVCC = 3.0 V
AN0 to AN7 input,
AN8 to AN11 input
–
–
±2
LSB
Vref = AVCC = 2.2 V
AN0 to AN7 input,
AN8 to AN11 input
–
–
±2
LSB
4.0 V ≤ Vref = AVCC ≤ 5.5 V (2)
2
–
20
MHz
3.2 V ≤ Vref = AVCC ≤ 5.5 V
(2)
2
–
16
MHz
2.7 V ≤ Vref = AVCC ≤ 5.5 V (2)
2
–
10
MHz
2.2 V ≤ Vref = AVCC ≤ 5.5 V (2)
2
–
5
MHz
–
3
–
kΩ
10-bit mode
Vref = AVCC = 5.0 V, φAD = 20 MHz
2.15
–
–
µs
8-bit mode
Vref = AVCC = 5.0 V, φAD = 20 MHz
2.15
–
–
µs
0.75
–
–
µs
–
45
–
µA
2.2
–
AVCC
V
0
–
Vref
V
1.19
1.34
1.49
V
Sampling time
φAD = 20 MHz
IVref
Vref current
VCC = 5.0 V, XIN = f1 = φAD = 20 MHz
Vref
Reference voltage
Analog input voltage
Typ.
Vref = AVCC = 5.0 V
tSAMP
VIA
Min.
(3)
OCVREF On-chip reference voltage
2 MHz ≤ φAD ≤ 4 MHz
Notes:
1. VCC/AVCC = Vref = 2.2 to 5.5 V, VSS = 0 V at Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise
specified.
2. The A/D conversion result will be undefined in wait mode, stop mode, when the flash memory stops, and in low-currentconsumption mode. Do not perform A/D conversion in these states or transition to these states during A/D conversion.
3. When the analog input voltage is over the reference voltage, the A/D conversion result will be 3FFh in 10-bit mode and FFh in
8-bit mode.
Table 5.4
Comparator B Electrical Characteristics
Symbol
Parameter
Condition
Vref
IVREF1, IVREF3 input reference voltage
VI
IVCMP1, IVCMP3 input voltage
–
Offset
td
Comparator output delay time (2)
VI = Vref ± 100 mV
ICMP
Comparator operating current
VCC = 5.0 V
Standard
Min.
Typ.
Unit
Max.
0
–
VCC − 1.4
−0.3
–
VCC + 0.3
V
–
5
100
mV
–
0.1
–
µs
–
17.5
–
µA
V
Notes:
1. VCC = 2.7 to 5.5 V, Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified.
2. When the digital filter is disabled.
REJ03B0287-0100 Rev.1.00
Mar 31, 2010
Page 25 of 42
R8C/33D Group
Table 5.5
5. Electrical Characteristics
Flash Memory (Program ROM) Electrical Characteristics
Symbol
Parameter
Conditions
Standard
Min.
Typ.
Max.
Unit
–
Program/erase endurance (2)
1,000 (3)
–
–
times
–
Byte program time
–
80
500
µs
–
Block erase time
–
0.3
–
s
td(SR-SUS)
Time delay from suspend request until
suspend
–
–
5 + CPU clock
× 3 cycles
ms
–
Interval from erase start/restart until
following suspend request
0
–
–
µs
–
Time from suspend until erase restart
–
–
30 + CPU clock
× 1 cycle
µs
td(CMDRST-
Time from when command is forcibly
stopped until reading is enabled
–
–
30 + CPU clock
× 1 cycle
µs
READY)
–
Program, erase voltage
2.7
–
5.5
V
–
Read voltage
1.8
–
5.5
V
–
Program, erase temperature
0
–
60
°C
20
–
–
year
–
Data hold time
(7)
Ambient temperature = 55°C
Notes:
1. VCC = 2.7 to 5.5 V at Topr = 0 to 60°C, unless otherwise specified.
2. Definition of programming/erasure endurance
The programming and erasure endurance is defined on a per-block basis.
If the programming and erasure endurance is n (n = 1,000), each block can be erased n times. For example, if 1,024 1-byte
writes are performed to different addresses in block A, a 1 Kbyte block, and then the block is erased, the
programming/erasure endurance still stands at one.
However, the same address must not be programmed more than once per erase operation (overwriting prohibited).
3. Endurance to guarantee all electrical characteristics after program and erase. (1 to Min. value can be guaranteed).
4. In a system that executes multiple programming operations, the actual erasure count can be reduced by writing to sequential
addresses in turn so that as much of the block as possible is used up before performing an erase operation. For example,
when programming groups of 16 bytes, the effective number of rewrites can be minimized by programming up to 128 groups
before erasing them all in one operation. It is also advisable to retain data on the erasure endurance of each block and limit
the number of erase operations to a certain number.
5. If an error occurs during block erase, attempt to execute the clear status register command, then execute the block erase
command at least three times until the erase error does not occur.
6. Customers desiring program/erase failure rate information should contact their Renesas technical support representative.
7. The data hold time includes time that the power supply is off or the clock is not supplied.
Suspend request
(FMR21 bit)
FST7 bit
FST6 bit
Clock-dependent
time
Fixed time
Access restart
td(SR-SUS)
FST6, FST7: Bits in FST register
FMR21: Bit in FMR2 register
Figure 5.2
Time delay until Suspend
REJ03B0287-0100 Rev.1.00
Mar 31, 2010
Page 26 of 42
R8C/33D Group
Table 5.6
5. Electrical Characteristics
Voltage Detection 0 Circuit Electrical Characteristics
Symbol
Vdet0
Parameter
Condition
Standard
Min.
Typ.
Max.
Unit
1.80
1.90
2.05
V
Voltage detection level Vdet0_1
(2)
2.15
2.35
2.50
V
Voltage detection level Vdet0_2
(2)
2.70
2.85
3.05
V
Voltage detection level Vdet0_3 (2)
3.55
3.80
4.05
V
150
µs
Voltage detection level Vdet0_0 (2)
–
Voltage detection 0 circuit response time (4)
At the falling of VCC from 5 V
to (Vdet0_0 − 0.1) V
–
6
–
Voltage detection circuit self power consumption
VCA25 = 1, VCC = 5.0 V
–
1.5
–
µA
td(E-A)
Waiting time until voltage detection circuit
operation starts (3)
–
–
100
µs
Notes:
1. The measurement condition is VCC = 1.8 V to 5.5 V and Topr = −20 to 85°C (N version) / −40 to 85°C (D version).
2. Select the voltage detection level with bits VDSEL0 and VDSEL1 in the OFS register.
3. Necessary time until the voltage detection circuit operates when setting to 1 again after setting the VCA25 bit in the VCA2
register to 0.
4. Time until the voltage monitor 0 reset is generated after the voltage passes Vdet0.
Table 5.7
Voltage Detection 1 Circuit Electrical Characteristics
Symbol
Vdet1
Parameter
Standard
Min.
Typ.
Max.
Unit
Voltage detection level Vdet1_0 (2)
At the falling of VCC
2.00
2.20
2.40
V
(2)
At the falling of VCC
2.15
2.35
2.55
V
Voltage detection level Vdet1_2 (2)
At the falling of VCC
2.30
2.50
2.70
V
Voltage detection level Vdet1_3 (2)
At the falling of VCC
2.45
2.65
2.85
V
Voltage detection level Vdet1_4
(2)
At the falling of VCC
2.60
2.80
3.00
V
Voltage detection level Vdet1_5
(2)
At the falling of VCC
2.75
2.95
3.15
V
Voltage detection level Vdet1_6 (2)
At the falling of VCC
2.85
3.10
3.40
V
Voltage detection level Vdet1_7 (2)
At the falling of VCC
3.00
3.25
3.55
V
Voltage detection level Vdet1_8 (2)
At the falling of VCC
3.15
3.40
3.70
V
Voltage detection level Vdet1_9
(2)
At the falling of VCC
3.30
3.55
3.85
V
Voltage detection level Vdet1_A
(2)
At the falling of VCC
3.45
3.70
4.00
V
Voltage detection level Vdet1_B (2)
At the falling of VCC
3.60
3.85
4.15
V
Voltage detection level Vdet1_C (2)
At the falling of VCC
3.75
4.00
4.30
V
Voltage detection level Vdet1_D
(2)
At the falling of VCC
3.90
4.15
4.45
V
Voltage detection level Vdet1_E
(2)
At the falling of VCC
4.05
4.30
4.60
V
Voltage detection level Vdet1_F (2)
At the falling of VCC
4.20
4.45
4.75
V
Hysteresis width at the rising of VCC in voltage
detection 1 circuit
Vdet1_0 to Vdet1_5
selected
–
0.07
–
V
Vdet1_6 to Vdet1_F
selected
–
0.10
–
V
150
µs
Voltage detection level Vdet1_1
–
Condition
–
–
Voltage detection 1 circuit response time (3)
At the falling of VCC from
5 V to (Vdet1_0 − 0.1) V
–
60
–
Voltage detection circuit self power consumption
VCA26 = 1, VCC = 5.0 V
–
1.7
–
µA
td(E-A)
Waiting time until voltage detection circuit operation
starts (4)
–
–
100
µs
Notes:
1.
2.
3.
4.
The measurement condition is VCC = 1.8 V to 5.5 V and Topr = −20 to 85°C (N version) / −40 to 85°C (D version).
Select the voltage detection level with bits VD1S0 to VD1S3 in the VD1LS register.
Time until the voltage monitor 1 interrupt request is generated after the voltage passes Vdet1.
Necessary time until the voltage detection circuit operates when setting to 1 again after setting the VCA26 bit in the VCA2
register to 0.
REJ03B0287-0100 Rev.1.00
Mar 31, 2010
Page 27 of 42
R8C/33D Group
Table 5.8
5. Electrical Characteristics
Voltage Detection 2 Circuit Electrical Characteristics
Symbol
Parameter
Standard
Condition
At the falling of VCC
Unit
Min.
Typ.
Max.
3.70
4.00
4.30
V
–
0.10
–
V
150
µs
Vdet2
Voltage detection level Vdet2_0
–
Hysteresis width at the rising of VCC in voltage detection
2 circuit
–
Voltage detection 2 circuit response time (2)
At the falling of VCC from
5 V to (Vdet2_0 − 0.1) V
–
20
–
Voltage detection circuit self power consumption
VCA27 = 1, VCC = 5.0 V
–
1.7
–
µA
td(E-A)
Waiting time until voltage detection circuit operation
starts (3)
–
–
100
µs
Notes:
1. The measurement condition is VCC = 1.8 V to 5.5 V and Topr = −20 to 85°C (N version) / −40 to 85°C (D version).
2. Time until the voltage monitor 2 interrupt request is generated after the voltage passes Vdet2.
3. Necessary time until the voltage detection circuit operates after setting to 1 again after setting the VCA27 bit in the VCA2
register to 0.
Table 5.9
Power-on Reset Circuit (2)
Symbol
Parameter
Condition
External power VCC rise gradient
trth
Standard
Min.
Typ.
Max.
0
–
50000
(1)
Unit
mV/msec
Notes:
1. The measurement condition is Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified.
2. To use the power-on reset function, enable voltage monitor 0 reset by setting the LVDAS bit in the OFS register to 0.
Vdet0 (1)
Vdet0 (1)
trth
trth
External
Power VCC
0.5 V
tw(por) (2)
Voltage detection 0
circuit response time
Internal
reset signal
1
× 32
fOCO-S
1
× 32
fOCO-S
Notes:
1. Vdet0 indicates the voltage detection level of the voltage detection 0 circuit.
2. tw(por) indicates the duration the external power VCC must be held below the valid voltage (0.5 V) to enable
a power-on reset. When turning on the power after it falls with voltage monitor 0 reset disabled, maintain
tw(por) for 1 ms or more.
Figure 5.3
Power-on Reset Circuit Electrical Characteristics
REJ03B0287-0100 Rev.1.00
Mar 31, 2010
Page 28 of 42
R8C/33D Group
Table 5.10
5. Electrical Characteristics
High-speed On-Chip Oscillator Circuit Electrical Characteristics
Symbol
Parameter
Standard
Condition
Unit
Min.
Typ.
Max.
VCC = 1.8 V to 5.5 V
−20°C ≤ Topr ≤ 85°C
38.4
40
41.6
MHz
VCC = 1.8 V to 5.5 V
−40°C ≤ Topr ≤ 85°C
38.0
40
42.0
MHz
High-speed on-chip oscillator frequency when
the FRA4 register correction value is written into
the FRA1 register and the FRA5 register
correction value into the FRA3 register (2)
VCC = 1.8 V to 5.5 V
−20°C ≤ Topr ≤ 85°C
35.389
36.864
38.338
MHz
VCC = 1.8 V to 5.5 V
−40°C ≤ Topr ≤ 85°C
35.020
36.864
38.707
MHz
High-speed on-chip oscillator frequency when
the FRA6 register correction value is written into
the FRA1 register and the FRA7 register
correction value into the FRA3 register
VCC = 1.8 V to 5.5 V
−20°C ≤ Topr ≤ 85°C
30.72
32
33.28
MHz
VCC = 1.8 V to 5.5 V
−40°C ≤ Topr ≤ 85°C
30.40
32
33.60
MHz
–
Oscillation stability time
VCC = 5.0 V, Topr = 25°C
–
0.5
3
ms
–
Self power consumption at oscillation
VCC = 5.0 V, Topr = 25°C
–
400
–
µA
–
High-speed on-chip oscillator frequency after
reset
Notes:
1. VCC = 1.8 V to 5.5 V, Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified.
2. This enables the setting errors of bit rates such as 9600 bps and 38400 bps to be 0% when the serial interface is used in
UART mode.
Table 5.11
Low-speed On-Chip Oscillator Circuit Electrical Characteristics
Symbol
Parameter
Condition
Standard
Min.
Typ.
Max.
Unit
fOCO-S
Low-speed on-chip oscillator frequency
60
125
250
–
Oscillation stability time
VCC = 5.0 V, Topr = 25°C
–
30
100
kHz
µs
–
Self power consumption at oscillation
VCC = 5.0 V, Topr = 25°C
–
2
–
µA
Note:
1. VCC = 1.8 to 5.5 V, Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified.
Table 5.12
Power Supply Circuit Timing Characteristics
Symbol
td(P-R)
Parameter
Condition
Time for internal power supply stabilization during
power-on (2)
Standard
Min.
Typ.
Max.
–
–
2000
Unit
µs
Notes:
1. The measurement condition is VCC = 1.8 to 5.5 V and Topr = 25°C.
2. Waiting time until the internal power supply generation circuit stabilizes during power-on.
REJ03B0287-0100 Rev.1.00
Mar 31, 2010
Page 29 of 42
R8C/33D Group
Table 5.13
5. Electrical Characteristics
Electrical Characteristics (1) [4.2 V ≤ VCC ≤ 5.5 V]
Symbol
VOH
VOL
Parameter
Output “H”
voltage
Output “L”
voltage
Other than XOUT
Standard
Condition
Drive capacity High VCC = 5V IOH = −20 mA
Max.
Unit
VCC − 2.0
–
VCC
V
–
VCC
V
1.0
–
VCC
V
Drive capacity High VCC = 5V IOL = 20 mA
–
–
2.0
V
Drive capacity Low VCC = 5V
IOL = 5 mA
–
–
2.0
V
VCC = 5 V
IOL = 200 µA
IOH = −5 mA
XOUT
VCC = 5 V
IOH = −200 µA
Other than XOUT
VT+-VT-
Hysteresis
IIH
Input “H” current
VI = 5 V, VCC = 5.0 V
IIL
Input “L” current
VI = 0 V, VCC = 5.0 V
VI = 0 V, VCC = 5.0 V
INT0, INT1, INT3,
KI0, KI1, KI2, KI3,
TRAIO, TRBO,
TRCIOA, TRCIOB,
TRCIOC, TRCIOD,
TRCTRG, TRCCLK,
ADTRG,
RXD0, RXD2,
CLK0, CLK2
RESET
RPULLUP Pull-up resistance
Typ.
VCC − 2.0
Drive capacity Low VCC = 5V
XOUT
Min.
–
–
0.5
V
0.1
1.2
–
V
0.1
1.2
–
V
–
–
5.0
µA
–
–
−5.0
µA
25
50
100
kΩ
RfXIN
Feedback
resistance
XIN
–
0.3
–
MΩ
RfXCIN
Feedback
resistance
XCIN
–
8
–
MΩ
VRAM
RAM hold voltage
1.8
–
–
V
During stop mode
Note:
1. 4.2 V ≤ VCC ≤ 5.5 V at Topr = −20 to 85°C (N version) / −40 to 85°C (D version), f(XIN) = 20 MHz, unless otherwise specified.
REJ03B0287-0100 Rev.1.00
Mar 31, 2010
Page 30 of 42
R8C/33D Group
Table 5.14
Symbol
ICC
5. Electrical Characteristics
Electrical Characteristics (2) [3.3 V ≤ VCC ≤ 5.5 V]
(Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified.)
Parameter
Condition
Power supply
High-speed
current
clock mode
(VCC = 3.3 to 5.5 V)
Single-chip mode,
output pins are
open, other pins are
VSS
High-speed
on-chip
oscillator mode
Low-speed
on-chip
oscillator mode
Low-speed
clock mode
Wait mode
Stop mode
REJ03B0287-0100 Rev.1.00
Mar 31, 2010
XIN = 20 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
No division
XIN = 16 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
No division
XIN = 10 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
No division
XIN = 20 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8
XIN = 16 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8
XIN = 10 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8
XIN clock off
High-speed on-chip oscillator on fOCO-F = 20 MHz
Low-speed on-chip oscillator on = 125 kHz
No division
XIN clock off
High-speed on-chip oscillator on fOCO-F = 20 MHz
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8
XIN clock off
High-speed on-chip oscillator on fOCO-F = 4 MHz
Low-speed on-chip oscillator on = 125 kHz
Divide-by-16
MSTTRC = 1
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8, FMR27 = 1, VCA20 = 0
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
XCIN clock oscillator on = 32 kHz
No division
FMR27 = 1, VCA20 = 0
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
XCIN clock oscillator on = 32 kHz
No division
Program operation on RAM
Flash memory off, FMSTP = 1, VCA20 = 0
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
While a WAIT instruction is executed
Peripheral clock operation
VCA27 = VCA26 = VCA25 = 0
VCA20 = 1
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
While a WAIT instruction is executed
Peripheral clock off
VCA27 = VCA26 = VCA25 = 0
VCA20 = 1
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
XCIN clock oscillator on = 32 kHz (peripheral clock off)
While a WAIT instruction is executed
VCA27 = VCA26 = VCA25 = 0
VCA20 = 1
XIN clock off, Topr = 25°C
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
CM10 = 1
Peripheral clock off
VCA27 = VCA26 = VCA25 = 0
XIN clock off, Topr = 85°C
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
CM10 = 1
Peripheral clock off
VCA27 = VCA26 = VCA25 = 0
Min.
–
Standard
Typ.
Max.
6.5
15
Unit
mA
–
5.3
12.5
mA
–
3.6
–
mA
–
3.0
–
mA
–
2.2
–
mA
–
1.5
–
mA
–
7.0
15
mA
–
3.0
–
mA
–
1
–
mA
–
90
400
µA
–
85
400
µA
–
47
–
µA
–
15
100
µA
–
4
90
µA
–
3.5
–
µA
–
2.0
5.0
µA
–
5.0
–
µA
Page 31 of 42
R8C/33D Group
5. Electrical Characteristics
Timing Requirements
(Unless Otherwise Specified: VCC = 5 V, VSS = 0 V at Topr = 25°C)
Table 5.15
External Clock Input (XOUT, XCIN)
Symbol
Standard
Parameter
Min.
Max.
Unit
tc(XOUT)
XOUT input cycle time
50
–
ns
tWH(XOUT)
XOUT input “H” width
24
–
ns
tWL(XOUT)
XOUT input “L” width
24
–
ns
tc(XCIN)
XCIN input cycle time
14
–
µs
tWH(XCIN)
XCIN input “H” width
7
–
µs
tWL(XCIN)
XCIN input “L” width
7
–
µs
VCC = 5 V
tC(XOUT), tC(XCIN)
tWH(XOUT),
tWH(XCIN)
External Clock Input
tWL(XOUT), tWL(XCIN)
Figure 5.4
Table 5.16
External Clock Input Timing Diagram when VCC = 5 V
TRAIO Input
Symbol
Standard
Parameter
Min.
Max.
Unit
tc(TRAIO)
TRAIO input cycle time
100
–
ns
tWH(TRAIO)
TRAIO input “H” width
40
–
ns
tWL(TRAIO)
TRAIO input “L” width
40
–
ns
tC(TRAIO)
VCC = 5 V
tWH(TRAIO)
TRAIO input
tWL(TRAIO)
Figure 5.5
TRAIO Input Timing Diagram when VCC = 5 V
REJ03B0287-0100 Rev.1.00
Mar 31, 2010
Page 32 of 42
R8C/33D Group
Table 5.17
5. Electrical Characteristics
Serial Interface
Symbol
Standard
Parameter
Min.
Max.
Unit
tc(CK)
CLKi input cycle time
200
–
tW(CKH)
CLKi input “H” width
100
–
ns
ns
tW(CKL)
CLKi input “L” width
100
–
ns
td(C-Q)
TXDi output delay time
–
50
ns
th(C-Q)
TXDi hold time
0
–
ns
tsu(D-C)
RXDi input setup time
50
–
ns
th(C-D)
RXDi input hold time
90
–
ns
i = 0, 2
VCC = 5 V
tC(CK)
tW(CKH)
CLKi
tW(CKL)
th(C-Q)
TXDi
td(C-Q)
tsu(D-C)
th(C-D)
RXDi
i = 0, 2
Figure 5.6
Table 5.18
Serial Interface Timing Diagram when VCC = 5 V
External Interrupt INTi (i = 0, 1, 3) Input, Key Input Interrupt KIi (i = 0 to 3)
Symbol
Standard
Parameter
Min.
Max.
Unit
tW(INH)
INTi input “H” width, KIi input “H” width
250 (1)
–
ns
tW(INL)
INTi input “L” width, KIi input “L” width
250 (2)
–
ns
Notes:
1. When selecting the digital filter by the INTi input filter select bit, use an INTi input HIGH width of either (1/digital filter clock
frequency × 3) or the minimum value of standard, whichever is greater.
2. When selecting the digital filter by the INTi input filter select bit, use an INTi input LOW width of either (1/digital filter clock
frequency × 3) or the minimum value of standard, whichever is greater.
VCC = 5 V
INTi input
(i = 0, 1, 3)
tW(INL)
KIi input
(i = 0 to 3)
Figure 5.7
tW(INH)
Input Timing for External Interrupt INTi and Key Input Interrupt KIi when VCC = 5 V
REJ03B0287-0100 Rev.1.00
Mar 31, 2010
Page 33 of 42
R8C/33D Group
Table 5.19
5. Electrical Characteristics
Electrical Characteristics (3) [2.7 V ≤ VCC < 4.2 V]
Symbol
VOH
Parameter
Output “H” voltage
Other than XOUT
Condition
Max.
Drive capacity High IOH = −5 mA
VCC − 0.5
–
VCC
V
IOH = −1 mA
VCC − 0.5
–
VCC
V
1.0
–
VCC
V
Drive capacity High IOL = 5 mA
–
–
0.5
V
Drive capacity Low
IOL = 1 mA
–
–
0.5
V
IOL = 200 µA
–
–
0.5
V
–
V
IOH = −200 µA
XOUT
Output “L” voltage
Other than XOUT
XOUT
VT+-VT-
Hysteresis
IIH
Input “H” current
IIL
Input “L” current
Unit
Typ.
Drive capacity Low
VOL
Standard
Min.
INT0, INT1, INT3,
KI0, KI1, KI2, KI3,
TRAIO, TRBO,
TRCIOA, TRCIOB,
TRCIOC, TRCIOD,
TRCTRG, TRCCLK,
ADTRG,
RXD0, RXD2,
CLK0, CLK2
VCC = 3.0 V
0.1
0.4
RESET
VCC = 3.0 V
0.1
0.5
–
V
–
–
4.0
µA
VI = 3 V, VCC = 3.0 V
RPULLUP Pull-up resistance
VI = 0 V, VCC = 3.0 V
–
–
−4.0
µA
VI = 0 V, VCC = 3.0 V
42
84
168
kΩ
RfXIN
Feedback
resistance
XIN
–
0.3
–
MΩ
RfXCIN
Feedback
resistance
XCIN
–
8
–
MΩ
VRAM
RAM hold voltage
1.8
–
–
V
During stop mode
Note:
1. 2.7 V ≤ VCC < 4.2 V at Topr = −20 to 85°C (N version) / −40 to 85°C (D version), f(XIN) = 10 MHz, unless otherwise specified.
REJ03B0287-0100 Rev.1.00
Mar 31, 2010
Page 34 of 42
R8C/33D Group
Table 5.20
Symbol
ICC
5. Electrical Characteristics
Electrical Characteristics (4) [2.7 V ≤ VCC < 3.3 V]
(Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified.)
Parameter
Condition
Power supply current High-speed
clock mode
(VCC = 2.7 to 3.3 V)
Single-chip mode,
output pins are open,
other pins are VSS
High-speed
on-chip
oscillator
mode
Low-speed
on-chip
oscillator
mode
Low-speed
clock mode
Wait mode
Stop mode
REJ03B0287-0100 Rev.1.00
Mar 31, 2010
XIN = 10 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
No division
XIN = 10 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8
XIN clock off
High-speed on-chip oscillator on fOCO-F = 20 MHz
Low-speed on-chip oscillator on = 125 kHz
No division
XIN clock off
High-speed on-chip oscillator on fOCO-F = 20 MHz
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8
XIN clock off
High-speed on-chip oscillator on fOCO-F = 10 MHz
Low-speed on-chip oscillator on = 125 kHz
No division
XIN clock off
High-speed on-chip oscillator on fOCO-F = 10 MHz
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8
XIN clock off
High-speed on-chip oscillator on fOCO-F = 4 MHz
Low-speed on-chip oscillator on = 125 kHz
Divide-by-16
MSTTRC = 1
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8, FMR27 = 1, VCA20 = 0
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
XCIN clock oscillator on = 32 kHz
No division
FMR27 = 1, VCA20 = 0
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
XCIN clock oscillator on = 32 kHz
No division
Program operation on RAM
Flash memory off, FMSTP = 1, VCA20 = 0
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
While a WAIT instruction is executed
Peripheral clock operation
VCA27 = VCA26 = VCA25 = 0, VCA20 = 1
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
While a WAIT instruction is executed
Peripheral clock off
VCA27 = VCA26 = VCA25 = 0, VCA20 = 1
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
XCIN clock oscillator on = 32 kHz (peripheral clock
off)
While a WAIT instruction is executed
VCA27 = VCA26 = VCA25 = 0, VCA20 = 1
XIN clock off, Topr = 25°C
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
CM10 = 1
Peripheral clock off
VCA27 = VCA26 = VCA25 = 0
XIN clock off, Topr = 85°C
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
CM10 = 1
Peripheral clock off
VCA27 = VCA26 = VCA25 = 0
Min.
–
Standard
Typ.
Max.
3.5
10
Unit
mA
–
1.5
7.5
mA
–
7.0
15
mA
–
3.0
–
mA
–
4.0
–
mA
–
1.5
–
mA
–
1
–
mA
–
90
390
µA
–
80
400
µA
–
40
–
µA
–
15
90
µA
–
4
80
µA
–
3.5
–
µA
–
2.0
5.0
µA
–
5.0
–
µA
Page 35 of 42
R8C/33D Group
5. Electrical Characteristics
Timing requirements
(Unless Otherwise Specified: VCC = 3 V, VSS = 0 V at Topr = 25°C)
Table 5.21
External Clock Input (XOUT, XCIN)
Symbol
Standard
Parameter
Min.
Max.
Unit
tc(XOUT)
XOUT input cycle time
50
–
ns
tWH(XOUT)
XOUT input “H” width
24
–
ns
tWL(XOUT)
XOUT input “L” width
24
–
ns
tc(XCIN)
XCIN input cycle time
14
–
µs
tWH(XCIN)
XCIN input “H” width
7
–
µs
tWL(XCIN)
XCIN input “L” width
7
–
µs
VCC = 3 V
tC(XOUT), tC(XCIN)
tWH(XOUT),
tWH(XCIN)
External Clock Input
tWL(XOUT), tWL(XCIN)
Figure 5.8
External Clock Input Timing Diagram when VCC = 3 V
Table 5.22
TRAIO Input
Symbol
Standard
Parameter
Min.
Max.
Unit
tc(TRAIO)
TRAIO input cycle time
300
–
ns
tWH(TRAIO)
TRAIO input “H” width
120
–
ns
tWL(TRAIO)
TRAIO input “L” width
120
–
ns
tC(TRAIO)
VCC = 3 V
tWH(TRAIO)
TRAIO input
tWL(TRAIO)
Figure 5.9
TRAIO Input Timing Diagram when VCC = 3 V
REJ03B0287-0100 Rev.1.00
Mar 31, 2010
Page 36 of 42
R8C/33D Group
Table 5.23
5. Electrical Characteristics
Serial Interface
Symbol
Standard
Parameter
Min.
Max.
Unit
tc(CK)
CLKi input cycle time
300
–
ns
tW(CKH)
CLKi input “H” width
150
–
ns
tW(CKL)
CLKi Input “L” width
150
–
ns
td(C-Q)
TXDi output delay time
–
80
ns
th(C-Q)
TXDi hold time
0
–
ns
tsu(D-C)
RXDi input setup time
70
–
ns
th(C-D)
RXDi input hold time
90
–
ns
i = 0, 2
VCC = 3 V
tC(CK)
tW(CKH)
CLKi
tW(CKL)
th(C-Q)
TXDi
td(C-Q)
tsu(D-C)
th(C-D)
RXDi
i = 0, 2
Figure 5.10
Table 5.24
Serial Interface Timing Diagram when VCC = 3 V
External Interrupt INTi (i = 0, 1, 3) Input, Key Input Interrupt KIi (i = 0 to 3)
Symbol
tW(INH)
tW(INL)
Standard
Parameter
Unit
Min.
Max.
INTi input “H” width, KIi input “H” width
380 (1)
–
ns
INTi input “L” width, KIi input “L” width
380 (2)
–
ns
Notes:
1. When selecting the digital filter by the INTi input filter select bit, use an INTi input HIGH width of either (1/digital filter clock
frequency × 3) or the minimum value of standard, whichever is greater.
2. When selecting the digital filter by the INTi input filter select bit, use an INTi input LOW width of either (1/digital filter clock
frequency × 3) or the minimum value of standard, whichever is greater.
VCC = 3 V
INTi input
(i = 0, 1, 3)
tW(INL)
KIi input
(i = 0 to 3)
Figure 5.11
tW(INH)
Input Timing for External Interrupt INTi and Key Input Interrupt KIi when VCC = 3 V
REJ03B0287-0100 Rev.1.00
Mar 31, 2010
Page 37 of 42
R8C/33D Group
Table 5.25
5. Electrical Characteristics
Electrical Characteristics (5) [1.8 V ≤ VCC < 2.7 V]
Symbol
VOH
Parameter
Output “H” voltage
Other than XOUT
Condition
Max.
Drive capacity High IOH = −2 mA
VCC − 0.5
–
VCC
V
IOH = −1 mA
VCC − 0.5
–
VCC
V
1.0
–
VCC
V
Drive capacity High IOL = 2 mA
–
–
0.5
V
Drive capacity Low
IOL = 1 mA
–
–
0.5
V
IOL = 200 µA
–
–
0.5
V
0.05
0.20
–
V
0.05
0.20
–
V
–
–
4.0
µA
IOH = −200 µA
XOUT
Output “L” voltage
Other than XOUT
Unit
Typ.
Drive capacity Low
VOL
Standard
Min.
XOUT
VT+-VT-
Hysteresis
IIH
Input “H” current
VI = 2.2 V, VCC = 2.2 V
IIL
Input “L” current
VI = 0 V, VCC = 2.2 V
–
–
−4.0
µA
VI = 0 V, VCC = 2.2 V
70
140
300
kΩ
INT0, INT1, INT3,
KI0, KI1, KI2, KI3,
TRAIO, TRBO,
TRCIOA, TRCIOB,
TRCIOC, TRCIOD,
TRCTRG, TRCCLK,
ADTRG,
RXD0, RXD2,
CLK0, CLK2
RESET
RPULLUP Pull-up resistance
RfXIN
Feedback
resistance
XIN
–
0.3
–
MΩ
RfXCIN
Feedback
resistance
XCIN
–
8
–
MΩ
VRAM
RAM hold voltage
1.8
–
–
V
During stop mode
Note:
1. 1.8 V ≤ VCC < 2.7 V at Topr = −20 to 85°C (N version) / −40 to 85°C (D version), f(XIN) = 5 MHz, unless otherwise specified.
REJ03B0287-0100 Rev.1.00
Mar 31, 2010
Page 38 of 42
R8C/33D Group
Table 5.26
Symbol
ICC
5. Electrical Characteristics
Electrical Characteristics (6) [1.8 V ≤ VCC < 2.7 V]
(Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified.)
Parameter
Condition
Power supply current High-speed
(VCC = 1.8 to 2.7 V)
clock mode
Single-chip mode,
output pins are open,
other pins are VSS
High-speed
on-chip
oscillator
mode
Low-speed
on-chip
oscillator
mode
Low-speed
clock mode
Wait mode
Stop mode
REJ03B0287-0100 Rev.1.00
Mar 31, 2010
XIN = 5 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
No division
XIN = 5 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8
XIN clock off
High-speed on-chip oscillator on fOCO-F = 5 MHz
Low-speed on-chip oscillator on = 125 kHz
No division
XIN clock off
High-speed on-chip oscillator on fOCO-F = 5 MHz
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8
XIN clock off
High-speed on-chip oscillator on fOCO-F = 4 MHz
Low-speed on-chip oscillator on = 125 kHz
Divide-by-16
MSTTRC = 1
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8, FMR27 = 1, VCA20 = 0
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
XCIN clock oscillator on = 32 kHz
No division
FMR27 = 1, VCA20 = 0
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
XCIN clock oscillator on = 32 kHz
No division
Program operation on RAM
Flash memory off, FMSTP = 1, VCA20 = 0
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
While a WAIT instruction is executed
Peripheral clock operation
VCA27 = VCA26 = VCA25 = 0
VCA20 = 1
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
While a WAIT instruction is executed
Peripheral clock off
VCA27 = VCA26 = VCA25 = 0
VCA20 = 1
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
XCIN clock oscillator on = 32 kHz (peripheral
clock off)
While a WAIT instruction is executed
VCA27 = VCA26 = VCA25 = 0
VCA20 = 1
XIN clock off, Topr = 25°C
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
CM10 = 1
Peripheral clock off
VCA27 = VCA26 = VCA25 = 0
XIN clock off, Topr = 85°C
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
CM10 = 1
Peripheral clock off
VCA27 = VCA26 = VCA25 = 0
Min.
–
Standard
Typ.
Max.
2.2
–
Unit
mA
–
0.8
–
mA
–
2.5
10
mA
–
1.7
–
mA
–
1
–
mA
–
90
300
µA
–
80
350
µA
–
40
–
µA
–
15
90
µA
–
4
80
µA
–
3.5
–
µA
–
2.0
5
µA
–
5.0
–
µA
Page 39 of 42
R8C/33D Group
5. Electrical Characteristics
Timing requirements
(Unless Otherwise Specified: VCC = 2.2 V, VSS = 0 V at Topr = 25°C)
Table 5.27
External Clock Input (XOUT, XCIN)
Symbol
Standard
Parameter
Min.
Max.
Unit
tc(XOUT)
XOUT input cycle time
200
–
ns
tWH(XOUT)
XOUT input “H” width
90
–
ns
tWL(XOUT)
XOUT input “L” width
90
–
ns
tc(XCIN)
XCIN input cycle time
14
–
µs
tWH(XCIN)
XCIN input “H” width
7
–
µs
tWL(XCIN)
XCIN input “L” width
7
–
µs
tC(XOUT), tC(XCIN)
VCC = 2.2 V
tWH(XOUT),
tWH(XCIN)
External Clock Input
tWL(XOUT), tWL(XCIN)
Figure 5.12
External Clock Input Timing Diagram when VCC = 2.2 V
Table 5.28
TRAIO Input
Symbol
Standard
Parameter
Min.
Max.
Unit
tc(TRAIO)
TRAIO input cycle time
500
–
ns
tWH(TRAIO)
TRAIO input “H” width
200
–
ns
tWL(TRAIO)
TRAIO input “L” width
200
–
ns
tC(TRAIO)
VCC = 2.2 V
tWH(TRAIO)
TRAIO input
tWL(TRAIO)
Figure 5.13
TRAIO Input Timing Diagram when VCC = 2.2 V
REJ03B0287-0100 Rev.1.00
Mar 31, 2010
Page 40 of 42
R8C/33D Group
Table 5.29
5. Electrical Characteristics
Serial Interface
Symbol
Standard
Parameter
Min.
Max.
Unit
tc(CK)
CLKi input cycle time
800
–
tW(CKH)
CLKi input “H” width
400
–
ns
tW(CKL)
CLKi input “L” width
400
–
ns
td(C-Q)
TXDi output delay time
–
200
ns
th(C-Q)
TXDi hold time
0
–
ns
tsu(D-C)
RXDi input setup time
150
–
ns
th(C-D)
RXDi input hold time
90
–
ns
ns
i = 0, 2
VCC = 2.2 V
tC(CK)
tW(CKH)
CLKi
tW(CKL)
th(C-Q)
TXDi
td(C-Q)
tsu(D-C)
th(C-D)
RXDi
i = 0, 2
Figure 5.14
Table 5.30
Serial Interface Timing Diagram when VCC = 2.2 V
External Interrupt INTi (i = 0, 1, 3) Input, Key Input Interrupt KIi (i = 0 to 3)
Symbol
tW(INH)
tW(INL)
Standard
Parameter
INTi input “H” width, KIi input “H” width
Max.
1000 (1)
–
ns
(2)
–
ns
1000
INTi input “L” width, KIi input “L” width
Unit
Min.
Notes:
1. When selecting the digital filter by the INTi input filter select bit, use an INTi input HIGH width of either (1/digital filter clock
frequency × 3) or the minimum value of standard, whichever is greater.
2. When selecting the digital filter by the INTi input filter select bit, use an INTi input LOW width of either (1/digital filter clock
frequency × 3) or the minimum value of standard, whichever is greater.
VCC = 2.2 V
INTi input
(i = 0, 1, 3)
tW(INL)
KIi input
(i = 0 to 3)
Figure 5.15
tW(INH)
Input Timing for External Interrupt INTi and Key Input Interrupt KIi when VCC = 2.2 V
REJ03B0287-0100 Rev.1.00
Mar 31, 2010
Page 41 of 42
R8C/33D Group
Package Dimensions
Package Dimensions
Diagrams showing the latest package dimensions and mounting information are available in the “Packages” section of
the Renesas Electronics website.
JEITA Package Code
P-LQFP32-7x7-0.80
RENESAS Code
PLQP0032GB-A
Previous Code
32P6U-A
MASS[Typ.]
0.2g
HD
*1
D
24
17
NOTE)
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
16
25
bp
c
c1
HE
*2
E
b1
Reference
Symbol
32
9
1
ZE
Terminal cross section
8
ZD
c
A
A1
F
A2
Index mark
L
D
E
A2
HD
HE
A
A1
bp
b1
c
c1
L1
y
e
REJ03B0287-0100 Rev.1.00
Mar 31, 2010
*3
Detail F
bp
x
e
x
y
ZD
ZE
L
L1
Dimension in Millimeters
Min Nom Max
6.9 7.0 7.1
6.9 7.0 7.1
1.4
8.8 9.0 9.2
8.8 9.0 9.2
1.7
0.1 0.2
0
0.32 0.37 0.42
0.35
0.09 0.145 0.20
0.125
0°
8°
0.8
0.20
0.10
0.7
0.7
0.3 0.5 0.7
1.0
Page 42 of 42
REVISION HISTORY
Rev.
Date
0.01
1.00
Sep 10, 2009
Mar 31, 2010
R8C/33D Group Datasheet
Description
Summary
Page
—
All pages
4
22 to 41
First Edition issued
“Preliminary”, “Under development” deleted
Table 1.3 revised
“5. Electrical Characteristics” added
All trademarks and registered trademarks are the property of their respective owners.
C-1
General Precautions in the Handling of MPU/MCU Products
The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes
on the products covered by this manual, refer to the relevant sections of the manual. If the descriptions under
General Precautions in the Handling of MPU/MCU Products and in the body of the manual differ from each
other, the description in the body of the manual takes precedence.
1. Handling of Unused Pins
Handle unused pins in accord with the directions given under Handling of Unused Pins in the
manual.
 The input pins of CMOS products are generally in the high-impedance state. In operation
with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the
vicinity of LSI, an associated shoot-through current flows internally, and malfunctions occur
due to the false recognition of the pin state as an input signal become possible. Unused
pins should be handled as described under Handling of Unused Pins in the manual.
2. Processing at Power-on
The state of the product is undefined at the moment when power is supplied.
 The states of internal circuits in the LSI are indeterminate and the states of register
settings and pins are undefined at the moment when power is supplied.
In a finished product where the reset signal is applied to the external reset pin, the states
of pins are not guaranteed from the moment when power is supplied until the reset
process is completed.
In a similar way, the states of pins in a product that is reset by an on-chip power-on reset
function are not guaranteed from the moment when power is supplied until the power
reaches the level at which resetting has been specified.
3. Prohibition of Access to Reserved Addresses
Access to reserved addresses is prohibited.
 The reserved addresses are provided for the possible future expansion of functions. Do
not access these addresses; the correct operation of LSI is not guaranteed if they are
accessed.
4. Clock Signals
After applying a reset, only release the reset line after the operating clock signal has become
stable. When switching the clock signal during program execution, wait until the target clock
signal has stabilized.
 When the clock signal is generated with an external resonator (or from an external
oscillator) during a reset, ensure that the reset line is only released after full stabilization of
the clock signal. Moreover, when switching to a clock signal produced with an external
resonator (or by an external oscillator) while program execution is in progress, wait until
the target clock signal is stable.
5. Differences between Products
Before changing from one product to another, i.e. to one with a different part number, confirm
that the change will not lead to problems.
 The characteristics of MPU/MCU in the same group but having different part numbers may
differ because of the differences in internal memory capacity and layout pattern. When
changing to products of different part numbers, implement a system-evaluation test for
each of the products.
Notice
1.
All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas
Electronics products listed herein, please confirm the latest product information with a Renesas Electronics sales office. Also, please pay regular and careful attention to additional and different information to
be disclosed by Renesas Electronics such as that disclosed through our website.
2.
Renesas Electronics does not assume any liability for infringement of patents, copyrights, or other intellectual property rights of third parties by or arising from the use of Renesas Electronics products or
technical information described in this document. No license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property rights of Renesas Electronics or
others.
3.
You should not alter, modify, copy, or otherwise misappropriate any Renesas Electronics product, whether in whole or in part.
4.
Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples. You are fully responsible for
the incorporation of these circuits, software, and information in the design of your equipment. Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from the
use of these circuits, software, or information.
5.
When exporting the products or technology described in this document, you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and
regulations. You should not use Renesas Electronics products or the technology described in this document for any purpose relating to military applications or use by the military, including but not limited to
the development of weapons of mass destruction. Renesas Electronics products and technology may not be used for or incorporated into any products or systems whose manufacture, use, or sale is
prohibited under any applicable domestic or foreign laws or regulations.
6.
Renesas Electronics has used reasonable care in preparing the information included in this document, but Renesas Electronics does not warrant that such information is error free. Renesas Electronics
7.
Renesas Electronics products are classified according to the following three quality grades: "Standard", "High Quality", and "Specific". The recommended applications for each Renesas Electronics product
assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information included herein.
depends on the product's quality grade, as indicated below. You must check the quality grade of each Renesas Electronics product before using it in a particular application. You may not use any Renesas
Electronics product for any application categorized as "Specific" without the prior written consent of Renesas Electronics. Further, you may not use any Renesas Electronics product for any application for
which it is not intended without the prior written consent of Renesas Electronics. Renesas Electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the
use of any Renesas Electronics product for an application categorized as "Specific" or for which the product is not intended where you have failed to obtain the prior written consent of Renesas Electronics.
The quality grade of each Renesas Electronics product is "Standard" unless otherwise expressly specified in a Renesas Electronics data sheets or data books, etc.
"Standard":
Computers; office equipment; communications equipment; test and measurement equipment; audio and visual equipment; home electronic appliances; machine tools;
personal electronic equipment; and industrial robots.
"High Quality": Transportation equipment (automobiles, trains, ships, etc.); traffic control systems; anti-disaster systems; anti-crime systems; safety equipment; and medical equipment not specifically
designed for life support.
"Specific":
Aircraft; aerospace equipment; submersible repeaters; nuclear reactor control systems; medical equipment or systems for life support (e.g. artificial life support devices or systems), surgical
implantations, or healthcare intervention (e.g. excision, etc.), and any other applications or purposes that pose a direct threat to human life.
8.
You should use the Renesas Electronics products described in this document within the range specified by Renesas Electronics, especially with respect to the maximum rating, operating supply voltage
range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas Electronics shall have no liability for malfunctions or damages arising out of the
use of Renesas Electronics products beyond such specified ranges.
9.
Although Renesas Electronics endeavors to improve the quality and reliability of its products, semiconductor products have specific characteristics such as the occurrence of failure at a certain rate and
malfunctions under certain use conditions. Further, Renesas Electronics products are not subject to radiation resistance design. Please be sure to implement safety measures to guard them against the
possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas Electronics product, such as safety design for hardware and software including but not limited to
redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures. Because the evaluation of microcomputer software alone is very difficult,
please evaluate the safety of the final products or system manufactured by you.
10. Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility of each Renesas Electronics product. Please use Renesas Electronics
products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances, including without limitation, the EU RoHS Directive. Renesas Electronics assumes
no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations.
11. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written consent of Renesas Electronics.
12. Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electronics products, or if you have any other inquiries.
(Note 1)
"Renesas Electronics" as used in this document means Renesas Electronics Corporation and also includes its majority-owned subsidiaries.
(Note 2)
"Renesas Electronics product(s)" means any product developed or manufactured by or for Renesas Electronics.
http://www.renesas.com
SALES OFFICES
Refer to "http://www.renesas.com/" for the latest and detailed information.
Renesas Electronics America Inc.
2880 Scott Boulevard Santa Clara, CA 95050-2554, U.S.A.
Tel: +1-408-588-6000, Fax: +1-408-588-6130
Renesas Electronics Canada Limited
1101 Nicholson Road, Newmarket, Ontario L3Y 9C3, Canada
Tel: +1-905-898-5441, Fax: +1-905-898-3220
Renesas Electronics Europe Limited
Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K
Tel: +44-1628-585-100, Fax: +44-1628-585-900
Renesas Electronics Europe GmbH
Arcadiastrasse 10, 40472 Düsseldorf, Germany
Tel: +49-211-65030, Fax: +49-211-6503-1327
Renesas Electronics (China) Co., Ltd.
7th Floor, Quantum Plaza, No.27 ZhiChunLu Haidian District, Beijing 100083, P.R.China
Tel: +86-10-8235-1155, Fax: +86-10-8235-7679
Renesas Electronics (Shanghai) Co., Ltd.
Unit 204, 205, AZIA Center, No.1233 Lujiazui Ring Rd., Pudong District, Shanghai 200120, China
Tel: +86-21-5877-1818, Fax: +86-21-6887-7858 / -7898
Renesas Electronics Hong Kong Limited
Unit 1601-1613, 16/F., Tower 2, Grand Century Place, 193 Prince Edward Road West, Mongkok, Kowloon, Hong Kong
Tel: +852-2886-9318, Fax: +852 2886-9022/9044
Renesas Electronics Taiwan Co., Ltd.
7F, No. 363 Fu Shing North Road Taipei, Taiwan
Tel: +886-2-8175-9600, Fax: +886 2-8175-9670
Renesas Electronics Singapore Pte. Ltd.
1 harbourFront Avenue, #06-10, keppel Bay Tower, Singapore 098632
Tel: +65-6213-0200, Fax: +65-6278-8001
Renesas Electronics Malaysia Sdn.Bhd.
Unit 906, Block B, Menara Amcorp, Amcorp Trade Centre, No. 18, Jln Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, Malaysia
Tel: +60-3-7955-9390, Fax: +60-3-7955-9510
Renesas Electronics Korea Co., Ltd.
11F., Samik Lavied' or Bldg., 720-2 Yeoksam-Dong, Kangnam-Ku, Seoul 135-080, Korea
Tel: +82-2-558-3737, Fax: +82-2-558-5141
© 2010 Renesas Electronics Corporation. All rights reserved.
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