EM78568 8-Bit Microcontroller for FRS Product Specification DOC. VERSION 3.6 ELAN MICROELECTRONICS CORP. February 2005 Trademark Acknowledgments: IBM is a registered trademark and PS/2 is a trademark of IBM. Windows is a trademark of Microsoft Corporation. ELAN and ELAN logo are trademarks of ELAN Microelectronics Corporation. Copyright © 2005 by ELAN Microelectronics Corporation All Rights Reserved Printed in Taiwan The contents of this specification are subject to change without further notice. ELAN Microelectronics assumes no responsibility concerning the accuracy, adequacy, or completeness of this specification. ELAN Microelectronics makes no commitment to update, or to keep current the information and material contained in this specification. Such information and material may change to conform to each confirmed order. In no event shall ELAN Microelectronics be made responsible to any claims attributed to errors, omissions, or other inaccuracies in the information or material contained in this specification. ELAN Microelectronics shall not be liable for direct, indirect, special incidental, or consequential damages arising from the use of such information or material. The software (if any) described in this specification is furnished under a license or nondisclosure agreement, and may be used or copied only in accordance with the terms of such agreement. ELAN Microelectronics products are not intended for use in life support appliances, devices, or systems. Use of ELAN Microelectronics product in such applications is not supported and is prohibited. NO PART OF THIS SPECIFICATION MAY BE REPRODUCED OR TRANSMITTED IN ANY FORM OR BY ANY MEANS WITHOUT THE EXPRESS WRITTEN PERMISSION OF ELAN MICROELECTRONICS. ELAN MICROELECTRONICS CORPORATION Headquarters: Hong Kong: USA: No. 12, Innovation Road 1 Hsichu Science Park Hsinchu, Taiwan, 308 Tel: +886 3 563-9977 Fax: +886 3 563-9966 http://www.emc.com.tw Elan (HK) Microelectronics Corporation, Ltd. Elan Information Technology Group Rm. 1005B, 10/F Empire Centre 68 Mody Road, Tsimshatsui Kowloon , HONG KONG Tel: +852 2723-3376 Fax: +852 2723-7780 [email protected] 1821 Saratoga Ave., Suite 250 Saratoga, CA 95070 USA Tel: +1 408 366-8223 Fax: +1 408 366-8220 Europe: Shenzhen: Shanghai: Elan Microelectronics Corp. (Europe) Elan Microelectronics Shenzhen, Ltd. Elan Microelectronics Shanghai Corporation, Ltd. Siewerdtstrasse 105 8050 Zurich, SWITZERLAND Tel:+41 43 299-4060 Fax: +41 43 299-4079 http://www.elan-europe.com SSMEC Bldg., 3F, Gaoxin S. Ave. Shenzhen Hi-Tech Industrial Park Shenzhen, Guandong, CHINA Tel: +86 755 2601-0565 Fax: +86 755 2601-0500 23/Bldg. #115 Lane 572, Bibo Road Zhangjiang Hi-Tech Park Shanghai, CHINA Tel: +86 021 5080-3866 Fax: +86 021 5080-4600 Contents Contents 1 2 3 4 5 6 7 General Description ...................................................................................... 1 Features ......................................................................................................... 1 2.1 CPU.................................................................................................................... 1 2.2 PROGRAMMING TONE GENERATORS .......................................................... 2 2.3 COMPARATOR.................................................................................................. 2 2.4 DAC.................................................................................................................... 2 2.5 CTCSS Block .................................................................................................... 2 2.6 POVD ................................................................................................................. 3 2.7 LCD .................................................................................................................... 3 2.8 PACKAGE.......................................................................................................... 3 Application ..................................................................................................... 3 Pin Configuration .......................................................................................... 4 Functional Block Diagram ............................................................................ 5 Pin Description .............................................................................................. 6 Functional Description.................................................................................. 8 7.1 Operational Registers ...................................................................................... 8 7.2 Operational Register Detail Description......................................................... 9 7.2.1 7.2.2 7.2.3 7.2.4 7.2.5 7.2.6 R0 (Indirect Addressing Register) .......................................................................9 R1 (TCC) .............................................................................................................9 R2 (Program Counter).........................................................................................9 R3 (Status, Page Selection) ..............................................................................10 R4 (RAM Selection for Common Registers R20 ~ R3F)) .................................11 R5 (PORT5 I/O Data, Program Page Selection, LCD Address) .......................11 7.2.6.1 PAGE0 (PORT5 I/O Data Register, Program Page Register)............11 7.2.6.2 PAGE1 (LCD Address) .......................................................................12 7.2.7 R6 (PORT6 I/O Data, LCD Data) ......................................................................13 7.2.7.1 PAGE0 (PORT6 I/O Data Register) ...................................................13 7.2.7.2 PAGE1 (LCD Data) ............................................................................13 7.2.8 R7 (PORT7 I/O Data, Data RAM Bank) ............................................................13 7.2.8.1 PAGE0 (PORT7 I/O Data Register) ...................................................13 7.2.8.2 PAGE1 (VOX Detection Output, Ctcss Detection Output, Data RAM Bank Selection Bit)............................................................................................14 7.2.9 R8 (PORT8 I/O Data, Data RAM Address) .......................................................14 7.2.9.1 PAGE0 (PORT8 I/O Data Register) ...................................................14 7.2.9.2 PAGE1 (Data RAM Address Register) ...............................................14 7.2.10 R9 (PORT9 I/O Data, Data RAM Data Buffer) ..................................................15 7.2.10.1 PAGE0 (PORT9 I/O Data Register) ...................................................15 7.2.10.2 PAGE1 (Data RAM Data Register).....................................................16 Product Specification (V3.6) 02.02.2005 • iii Contents 7.2.11 RA (PLL, Main Clock Selection, Comparator Flag, Watchdog Timer, DAC Input Data Buffer)......................................................................................16 7.2.11.1 PAGE0 (PLL Enable Bit, Main Clock Selection Bits, Comparator Control Bits, Watchdog Timer Enable Bit) .....................................................................16 7.2.11.2 PAGE1 (DAC Input Data Register) ....................................................18 7.2.12 RC (PORTC0 I/O Data, Counter1 Data) ...........................................................18 7.2.12.1 PAGE0 (PORT9 I/O Data Register) ...................................................18 7.2.12.2 PAGE1 (Counter1 Data Register) ......................................................19 7.2.13 RD (LCD control, Counter2 Data) .....................................................................19 7.2.13.1 PAGE0 (LCD Driver Control Bits).......................................................19 7.2.13.2 PAGE1 (Counter2 Data Register) ......................................................20 7.2.14 RE (Wake-up control, DAC Tone Output Frequency Selection) .......................20 7.2.14.1 PAGE0 (Interrupt Flag, Wake-up Control Bits)...................................20 7.2.14.2 PAGE1 (Programmable D/A Tone Selection Register).......................21 7.2.15 RF (Interrupt Status)..........................................................................................23 7.3 Special Purpose Registers ............................................................................ 24 7.3.1 7.3.2 7.3.3 A (Accumulator).................................................................................................24 CONT (Control Register)...................................................................................24 IOC5 (PORT5 I/O Control, LCD Bias Control, Comparator Control) ................26 7.3.3.1 PAGE0 (LCD Bias Control Bits) .........................................................26 7.3.3.2 PAGE1 (Comparator Control Register) ..............................................29 7.3.4 IOC6 (PORT6 I/O control, P6* Pins Switch Control).........................................32 7.3.4.1 PAGE0 (PORT6 I/O Control Register) ...............................................32 7.3.4.2 PAGE1 (P6* Pins Switch Control Register)........................................32 7.3.5 IOC7 (PORT7 I/O Control, PORT7 Pull-high Control) ......................................33 7.3.5.1 PAGE0 (PORT7 I/O Control Register) ...............................................33 7.3.5.2 PAGE1 (PORT7 Pull-high Control Register) ......................................33 7.3.6 IOC8 (PORT8 I/O control, PORT8 Pull-high Control) .......................................34 7.3.6.1 PAGE0 (PORT8 I/O Control Register) ...............................................34 7.3.6.2 PAGE1 (PORT8 Pull High Control Register)......................................34 7.3.7 IOC9 (PORT9 I/O control, PORT9 Switches) ...................................................34 7.3.7.1 PAGE0 (PORT9 I/O Control Register) ...............................................34 7.3.7.2 PAGE1 (PORT9 Switches).................................................................34 7.3.8 IOCA (TONE2 Control, Control Bits for DAC, DAC Tone, Reference, VOX and P67 Switch)........................................................................................35 7.3.8.1 PAGE0 (TONE2 Control Register) .....................................................35 7.3.8.2 PAGE1 (Control Bits for DAC, DAC Tone, Reference, VOX and P67 Switch) .................................................................................36 7.3.9 IOCC (PORTC I/O Control, PORT Switch) .......................................................38 7.3.9.1 PAGE0 (PORTC I/O Control Register)...............................................38 7.3.9.2 PAGE1 (PORT Switch).......................................................................38 7.3.10 IOCD (TONE1 Control, Clock Source, Prescaler of CN1 and CN2) .................39 7.3.10.1 PAGE0 (TONE1 Control)....................................................................39 7.3.10.2 PAGE1 (Clock Source and Prescaler for COUNTER1 and COUNTER2) ......................................................................................39 iv • Product Specification (V3.6) 02.02.2005 Contents 7.3.11 IOCE (TONE1 Extra Control Bits, CTCSS Control Switches)...........................40 7.3.11.1 PAGE0 (Interrupt Mask, TONE1 Extra Three Control Bits)................40 7.3.11.2 PAGE1 (CTCSS Control Switches)....................................................40 7.3.12 IOCF (Interrupt Mask) .......................................................................................42 7.4 I/O Port ............................................................................................................ 43 7.5 RESET ............................................................................................................. 44 7.6 Wake-up........................................................................................................... 45 7.6.1 7.6.2 7.6.3 SLEEP Mode, RA(7) = 0 + "SLEP" Instruction..................................................45 IDLE mode, RA(7) = 1 + "SLEP" Instruction. ....................................................45 /RESET Pull Low...............................................................................................46 7.7 Interrupt........................................................................................................... 46 7.8 Instruction Set ................................................................................................ 46 7.9 CODE Option Register ................................................................................... 48 7.10 Signal and Control Paths for DAC, DAC Tone Gen., CTCSS and Comparator.............................................................................................. 50 7.10.1 7.10.2 7.10.3 7.10.4 7.10.5 7.10.6 DAC Program Mode ..........................................................................................51 DAC Output Paths.............................................................................................51 Using 2.5V Ref and DAC ..................................................................................51 Select DAO/P67 Pin as Normal I/O P67 ...........................................................52 Using DAC General Mode.................................................................................52 Using DAC Tone Generator Mode ....................................................................52 7.11 CTCSS Block .................................................................................................. 53 7.11.1 Block Control and Signal Flow Description ......................................................53 7.11.2 Special Application on Audio/CTCSS Tone Mixing Output................................56 7.12 8-bit R-2R DAC................................................................................................ 58 7.13 4-bit Comparator............................................................................................. 59 7.14 Programming Tone Generators..................................................................... 60 8 9 10 11 12 Absolute Operation Maximum Ratings...................................................... 61 DC Electrical Characteristic........................................................................ 61 AC Electrical Characteristic........................................................................ 63 Timing Diagrams ......................................................................................... 65 Application circuit ....................................................................................... 67 APPENDIX A User Application Note ................................................................................. 68 EM78568 Product Specification v Contents Specification Revision History Version Revision Description Date 1.0 Initial version 2002/01/04 1.1 Updated the description of errors 2002/01/07 1.2 Updated the description 2002/01/10 1.3 Revised the operating voltage for DAC and CTCSS 2002/01/11 1.4 Changed the package and pin configuration 2002/04/09 1.5 1. Removed the CTCSS VOX function 2002/04/12 2. Added the Microphone Amp mute function 3. Changed the RE PAGE1 default value from 0x00 to 0xFF 4. Changed the CTCSS tone generation channel 19 setting 1.6 1. Updated the description of the “program ROM” form 32kx13 Î 16kx13 2002/04/15 2. Updated the ”register configuration” table 1.7 1. Added LCD waveform option bit in the code option. The new two option : select LCD waveform as Type0 or Type1. 2002/06/10 1.8 1. Changed P73 interrupt setting from INT2 to INT3 2002/09/23 2. Updated the pin configuration and pin description 3. Updated the relative RF, IOCF register bit description 4. Changed the feature description for the interrupt numbers 2.0 1. Added item 1 and 2 in the user application note (see user application note) 2002/10/04 2. Clarified the “undefined bits” descriptions. Not allowed to use undefined bits. 3. Added LCD Type0 and Type1 waveforms 2.1 1. Reduced the data RAM from 1k to 0.5k. Removed R7 PAGE1 bit1. 2002/10/29 2. Relayout the chip to fit 100-pin compatible with EM78P568 3. Combined A/B version distinction 2.2 1. Fixed the bug in the application note 2002/10/31 2. Added extra notice in the application 2.3 Revised the current consumption of the DC electrical characteristic 2002/11/06 2.4 Revised the test condition of electrical characteristic 2002/11/07 2.5 1. Updated the operating voltage of the Comparator, DAC and CTCSS block in the feature description 2002/11/22 2. Added DC voltage characteristic for 2.5VREF 3. Revised the sleep current max value from 8µA to 5µA 4. Added description in the user application note 2.6 1. Added DC characteristic under VDD=3V for 2.5VREF 2002/11/26 2. Updated the description in the user application note 2.7 1. Updated the DC characteristic 2002/11/29 2. Fixed the code option 3. Removed /POVD function 4. Updated the user application note 2.8 vi • Revised the waveform of the LCD 1/4 duty for Type 1 2003/01/15 Product Specification (V3.6) 02.02.2005 Contents 2.9 1. Removed the waveform of the LCD for Type0 2003/02/26 2. Updated the DC characteristic for driver/sink current 3.0 1. Revised the description in the operating current for analog circuit 2003/10/24 2. Revised the dB to dBm on level for CTCSS tone to MTX 3.5 Revised the current consumption of DC electrical characteristic 2004/07/28 3.6 Revised the test condition of the electrical characteristic 2005/02/02 EM78568 Product Specification vii Contents viii • Product Specification (V3.6) 02.02.2005 EM78568 8-Bit Microcontroller for FRS 1 General Description The EM78568 is an 8-bit RISC type microprocessor with low power, high speed CMOS technology. This integrated single chip has an on-chip watchdog timer (WDT), program ROM, data RAM, LCD driver, programmable real time clock/counter, internal interrupt, power down mode, built-in 8-bit D/A converter, 5-bit Comparator, DAC tone generator, CTCSS analog circuit, programming dual tone generator and tri-state I/O. 2 Feature 2.1 CPU Operating voltage : 2.2V～5.5V 16k x 13 program ROM 0.5k x 8 on chip data RAM Up to 36 bi-directional tri-state I/O ports 16 level stack for subroutine nesting 8-bit real time clock/counter (TCC) two 8-bit counters : COUNTER1 and COUNTER2 On-chip watchdog timer (WDT) 99.9％ single instruction cycle commands Four modes (Main clock can be programmed from 447.829k to 17.913MHz generated by internal PLL) Mode CPU Status Main clock 32.768kHz Clock Status Sleep mode Turn off Turn off Turn off Idle mode Turn off Turn off Turn on Green mode Turn on Turn off Turn on Normal mode Turn on Turn on Turn on Input port interrupt function 8 interrupt source, 4 external , 4 internal Dual clock operation (Internal PLL main clock , External 32.768kHz) Product Specification (V3.6) 02.02.2005 (This specification is subject to change without further notice) •1 EM78568 8-Bit Microcontroller for FRS 2.2 PROGRAMMING TONE GENERATORS Operating voltage: 2.2V～5.5V Programming Tone1 and Tone2 dual tone generators 11-bit Programming Tone1 generators 8-bit Programming Tone2 generator 2.3 COMPARATOR Operating voltage: 2.7V ~ 5.5V 3-channel input 5-bit comparison reference level setting Internal (2.5V or VDD) or external reference level 2.4 DAC Operating: 2.7V～5.5V 8-bit R-2R D/A converter 8-bit programmable tone output Easy to direct access as programmable CTCSS tone output by DAC tone generator Internal (2.5V or VDD) or external reference level 2.5 CTCSS block 2• Operating voltage : 2.7V～5.5V Microphone amplifier (can be used as general OP Amp) Microphone mute function RX input OP Audio BPF (300Hz ~ 3400Hz) Sub-audio LPF (60Hz ~ 253Hz) for CTCSS tone detection Zero-crossing for detected CTCSS tone frequency output CTCSS Tx modulation summing Amp Product Specification (V3.6) 02.02.2005 (This specification is subject to change without further notice) EM78568 8-Bit Microcontroller for FRS 2.6 POVD Power-on voltage detector reset Without external reset circuit while enabling 2.7 LCD Common driver pins: 4 Segment driver pins: 20 1/3 bias 1/4 duty, 1/2 duty 16 Level LCD contrast control by software 2.8 PACKAGE 3 100-pin QFP (EM78568Q) 63-pin die (EM78568H) Application FRS (Family Radio Systems) and other wireless portable products Product Specification (V3.6) 02.02.2005 (This specification is subject to change without further notice) •3 EM78568 8-Bit Microcontroller for FRS SEG12/P57 SEG13/P97 SEG14/P96 SEG15/P95 SEG16/P94 SEG17/P93 SEG18/P92 SEG19/P91 P90 88 87 86 85 84 83 82 81 SEG8 93 SEG11/P56 SEG7 94 89 SEG6 95 90 SEG5 96 SEG9 SEG4 97 SEG10/P55 SEG3 98 91 SEG2 99 92 SEG1 100 Pin Configuration NC 1 80 NC NC 2 79 NC NC 3 78 NC NC 4 77 NC NC 5 76 NC NC 6 75 NC NC 7 74 NC NC 8 73 NC NC 9 72 NC SEG0 10 71 NC COM 3 11 70 NC COM 2 12 69 NC COM 1 13 68 NC COM 0 14 67 NC NC 15 66 NC NC 16 65 NC NC 17 64 NC NC 18 63 NC NC 19 62 NC NC AVDD 20 61 NC 21 60 PC0 RXO 22 59 INT0/P70 RXI 23 58 INT1/P71 NC 24 57 INT2/P72 NC 25 56 INT3/P73 49 50 P80 /RESET 46 P83 48 45 P84 P81 44 VSS 47 43 XOUT P82 42 41 P85 XIN 40 P86 CM P2/P63 AURX/P65 39 VDD P87 51 38 30 P60 P77 AVSS 37 P76 52 P61 53 29 36 28 PLLC CM P1/P62 TONE 34 35 P75 CM P3/P64 P74 54 32 33 55 27 31 26 DAO/P67 M ICI MICO M TX/P66 4 100-pin QFP or 63-pin die Fig.1b Pin Assignment 4• Product Specification (V3.6) 02.02.2005 (This specification is subject to change without further notice) EM78568 8-Bit Microcontroller for FRS 5 Functional Block Diagram DATA RAM CONTROL REGISTER CPU LCD DRIVER TIMING CONTROL TIM ER TCC COUNTER1 COUNTER2 WDT LCD I/O I/O PORT 8-bIT D/A PROGRAM MING TONE GEN. CTCSS block 5-bit COM PARATOR ROM Fig.2a Block diagram XIN XOUT PLLC WDT Timer R2 ROM Oscillator Timing Control Interrupt Control R1(TCC) DATA RAM STACK Prescaler Instruction Register ALU General RAM Control Sleep and Wake up on I/O port R3 R5 ACC Instruction Decoder R4 DATA & Control Bus LCD RAM LCD driver 8-bit D/A Prog. Tone Gen. CTCSS block Comparator IOC5 IOC6 IOC7 IOC8 R5 R6 R7 R8 R9 RC PORT5 PORT6 PORT7 PORT8 PORT9 PORTC P55~P57 P60~P67 P70~P77 P80~P87 P90~P97 PC0 IOC9 IOCC COM0~COM3 SEG0~SEG19 Fig.2b Block diagram Product Specification (V3.6) 02.02.2005 (This specification is subject to change without further notice) •5 EM78568 8-Bit Microcontroller for FRS 6 Pin Descriptions PIN I/O DESCRIPTION POWER VDD POWER AVDD VSS Digital power Analog power POWER AVSS Digital ground Analog ground CLOCK XIN I Input pin for 32.768 kHz oscillator XOUT O Output pin for 32.768 kHz oscillator PLLC I Phase loop lock capacitor, connect a capacitor 0.01µ to 0.047µ to the ground. O Common driver pins of LCD drivers LCD COM0 ~ COM3 SEG0 ~ SEG9 O SEG10 ~ SEG12 O (I/O : PORT5) SEG13 ~ SEG19 O (I/O : PORT9) Segment driver pins of LCD drivers SEG10 to SEG19 are shared with IO PORT. Programming tone generators TONE O Programming single tone or dual tone output Comparator CMP1 I (P62) CMP2 I (P63) CMP3 I (P64) Comparator input pins, shared with PORT62, PORT63 and PORT64. 8-bit D/A DAO O (P67) D/A converter output pin Shared with PORT67 CTCSS MICO O Microphone amplifier output. Put a feedback resistor to adjust the gain MICI I Microphone amplifier input RXO O Receiver amplifier output. Put a feedback resistor to adjust the gain RXI I Receiver amplifier input AURX O (P65) Receiving audio output Share with PORT65 MTX O (P66) Modulation transmission output for CTCSS tone Shared with PORT66 IO P55~P57 I/O Each bit on PORT5 can be INPUT or OUTPUT port PORT5 (7:5) are shared with LCD Segment signal P60 ~P67 6• I/O Each bit on PORT6 can be INPUT or OUTPUT Product Specification (V3.6) 02.02.2005 (This specification is subject to change without further notice) EM78568 8-Bit Microcontroller for FRS PIN I/O P70 ~ P77 I/O DESCRIPTION Each bit on PORT7 can be INPUT or OUTPUT Internal Pull high function PORT7 (0~3) has interrupt function P80 ~ P87 I/O Each bit on PORT8 can be INPUT or OUTPUT Internal pull high PORT8 (0~3) have wake-up functions (set by RE PAGE0) P90 ~ P97 I/O Each bit on PORT9 can be INPUT or OUTPUT port PORT9 (1~7) are shared with LCD Segment signal PC0 I/O Each bit on PORTC can be INPUT or OUTPUT port INT0 (PORT70) Interrupt sources. Once PORT70 has a falling edge or rising edge signal (controlled by CONT register), it will generate an interrupt. INT1 (PORT71) Interrupt sources which have the same interrupt flag. Any pin from PORT71 has a falling edge signal, which will generate an interrupt. INT2 (PORT72) Interrupt sources which have the same interrupt flag. Any pin from PORT72 has a falling edge signal, which will generate an interrupt. INT3 (PORT73) Interrupt sources which have the same interrupt flag. Any pin from PORT73 has a falling edge signal, which will generate an interrupt. /RESET I Product Specification (V3.6) 02.02.2005 (This specification is subject to change without further notice) Low reset •7 EM78568 8-Bit Microcontroller for FRS 7 Functional Descriptions 7.1 Operational Registers Register Configuration R PAGE Registers Addr R PAGE0 00 Indirect addressing 01 TCC 02 PC 03 Page, Status 04 RAM bank, RSR 05 06 07 Port 5 I/O data, Program ROM page IOC PAGE Registers R PAGE1 IOC PAGE0 LCD RAM address Port 5 I/O control, LCD bias control IOC PAGE1 Comparator control Port 6 I/O data LCD RAM data buffer Port 6 I/O control Port 6 switches Port 7 I/O data CTCSS detection output, Port 7 I/O control Port 7 pull high Data RAM bank 08 Port 8 I/O data Data RAM address Port 8 I/O control Port 8 pull high 09 Port 9 I/O data Data RAM data buffer Port 9 I/O control Port 9 switches DAC input data buffer TONE 2 control PLL, Main clock, 0A Comparator flag, WDTE DAC control, 2.5V ref control 0B 0C Port C I/O data Counter1 data PortC I/O control Port 5 switch 0D LCD control Counter2 data TONE1 control Clock source (CN1, CN2) Prescaler (CN1, CN2) 0E Wake-up control, 0F Interrupt flag 10 16 bytes : Common Registers DAC tone selection TONE1 extra control, CTCSS control switches Interrupt mask 1F 8• 20 Bank 0~Bank 3 : Common Registers 3F (32x8 for each bank) Product Specification (V3.6) 02.02.2005 (This specification is subject to change without further notice) EM78568 8-Bit Microcontroller for FRS 7.2 Operational Register Detail Description 7.2.1 R0 (Indirect Addressing Register) R0 is not a physically implemented register. It is used as indirect addressing pointer. Any instruction using R0 as register actually accesses data pointed by the RAM Select Register (R4). Example: MovA, @0x20; store an address at R4 for indirect addressing Mov0x04, A MovA, @0xAA ; write data 0xAA to R20 at bank0 through R0 Mov0x00, A 7.2.2 R1 (TCC) TCC data buffer; Increased by 16.384kHz or by the instruction cycle clock (controlled by CONT register). Written and read by the program as any other register. 7.2.3 R2 (Program Counter) The structure is depicted in Fig. 5. Generates 16k × 13 on-chip PROGRAM ROM addresses to the relative programming instruction codes. "JMP" instruction allows the direct loading of the low 10 program counter bits. "CALL" instruction loads the low 10 bits of the PC, PC+1, and then push into the stack. "RET'' ("RETL k", "RETI") instruction loads the program counter with the contents at the top of stack. "MOV R2,A" allows the loading of an address from the A register to the PC, and the ninth and tenth bits are cleared to "0''. "ADD R2,A" allows a relative address be added to the current PC, and contents of the ninth and tenth bits are cleared to "0''. "TBL" allows a relative address added to the current PC, and contents of the ninth and tenth bits don't change. The most significant bit (A10~A13) will be loaded with the contents of bit PS0~PS3 in the status register (R5 PAGE0) upon the execution of a "JMP'', "CALL'', "ADD R2, A'', or "MOV R2, A'' instruction. Product Specification (V3.6) 02.02.2005 (This specification is subject to change without further notice) •9 EM78568 8-Bit Microcontroller for FRS If an interrupt is triggered, PROGRAM ROM will jump to address 0x08 at page0. The CPU will store ACC, R3 status and R5 PAGE automatically, and they will be restored after instruction RETI. R5(PAGE) PC CALL and INTERRUPT A13 A12 A11 A10 A9 A8 STACK1 STACK2 STACK3 STACK4 STACK5 STACK6 STACK7 STACK8 STACK9 STACK10 STACK11 STACK12 STACK13 STACK14 STACK15 STACK16 A7~A0 0000 PAGE0 0000~03FF 0001 PAGE1 0400~07FF 0010 PAGE2 0800~0BFF 1110 PAGE14 3800~3BFF 1111 PAGE15 3C00~3FFF RET RETL RETI store ACC,R3,R5(PAGE) restore Fig.3 Program Counter Organization 7.2.4 R3 (Status, Page selection) PAGE0 (Status flag, Page selection bits) 7 6 5 4 3 2 1 0 RPAGE2 RPAGE IOCPAGE T P Z DC C R/W-0 R/W-0 R/W-0 R R R/W R/W R/W Bit 0(C) : Carry flag Bit 1(DC) : Auxiliary carry flag Bit 2(Z) : Zero flag Bit 3(P) : Power down bit Set to 1 during power on or by a "WDTC" command and reset to 0 by a "SLEP" command. Bit 4(T) : Time-out bit Set to 1 by the "SLEP" and "WDTC" command, or during power up and reset to 0 by WDT timeout. 10 • .EVENT T P WDT wake up from sleep mode 0 0 WDT time out (not sleep mode) 0 1 REMARK Product Specification (V3.6) 02.02.2005 (This specification is subject to change without further notice) EM78568 8-Bit Microcontroller for FRS /RESET wake up from sleep 1 0 Power up 1 1 Low pulse on /RESET x x x : don't care Bit 5(IOCPAGE) : change IOC5 ~ IOCE to another page Please refer to Fig.4 control register configuration for details. 0/1 Î page0 / page1 Bit 6(RPAGE) : change R5 ~ RE to another page Refer to Fig.4 control register configuration for details. 0/1 Î page0 / page1 Bit 7(RPAGE2) : change R5 ~ RE to R page2 (keep this bit unchanged at “0”) 0 Î The page for R5 ~ RE depends on Bit 6 (RPAGE) 1 Î change R5 ~ RE to page2 7.2.5 R4 (RAM selection for common registers R20 ~ R3F)) (RAM Selection Register) 7 6 5 4 3 2 1 0 RB1 RB0 RSR5 RSR4 RSR3 RSR2 RSR1 RSR0 R/W-0 R/W-0 R/W R/W R/W R/W R/W R/W Bit 0 ~ Bit 5 (RSR0 ~ RSR5) : Indirect addressing for common registers R20 ~ R3F RSR bits are used to select up to 32 registers (R20 to R3F) in the indirect addressing mode. Bit 6 ~ Bit 7 (RB0 ~ RB1) : Bank selection bits for common registers R20 ~ R3F These selection bits are used to determine which bank is activated among the 4 banks of the 32 registers (R20 to R3F). Refer to VII.1 Operational Registers for details. 7.2.6 R5 (PORT5 I/O data, Program page selection, LCD address) 7.2.6.1 PAGE0 (PORT5 I/O data register, Program page register) 7 6 5 4 3 2 1 0 P57 P56 P55 - PS3 PS2 PS1 PS0 R/W R/W R/W R/W-0 R/W-0 R/W-0 R/W-0 Bit 0 ~ Bit 3 (PS0 ~ PS3) : Program page selection bits PS3 PS2 PS1 PS0 Program memory page (Address) 0 0 0 0 Page 0 Product Specification (V3.6) 02.02.2005 (This specification is subject to change without further notice) • 11 EM78568 8-Bit Microcontroller for FRS 0 0 0 1 Page 1 0 0 1 0 Page 2 0 0 1 1 Page 3 : : : : : 1 1 1 0 Page 14 1 1 1 1 Page 15 You can use PAGE instruction to change page to maintain program page by user. Otherwise, you can use far jump (FJMP) or far call (FCALL) instructions to program your code. And the program page is maintained by EMC's complier. It will change your program by inserting instructions within the program. Bit 4 : (undefined) not allowed for use Bit 5 ~ Bit 7 (P55 ~ P57) : 8-bit PORT5 (5~7) I/O data register You can use the IOC register to define each bit as input or output. 7.2.6.2 PAGE1 (LCD address) 7 6 5 4 3 2 1 0 - - - - LCDA3 LCDA2 LCDA1 LCDA0 R/W-0 R/W-0 R/W-0 R/W-0 Bit 0 ~ Bit 3 (LCDA0 ~ LCDA3) : LCD address for LCD RAM read or write The address of the LCD RAM corresponds to the COMMON and SEGMENT signals as shown in the table. COM3 ~ COM0 LCD Address (LCDA3 ~ LCDA0) SEG1, SEG0 00H SEG3, SEG2 01H SEG5, SEG4 02H SEG7, SEG6 03H SEG9, SEG8 04H SEG11, SEG10 05H SEG13, SEG12 06H SEG15, SEG14 07H SEG17, SEG16 08H SEG19, SEG18 09H Bit 4 ~ Bit 7 : (undefined) not allowed for use 12 • Product Specification (V3.6) 02.02.2005 (This specification is subject to change without further notice) EM78568 8-Bit Microcontroller for FRS 7.2.7 R6 (PORT6 I/O data, LCD data) 7.2.7.1 PAGE0 (PORT6 I/O data register) 7 6 5 4 3 2 1 0 P67 P66 P65 P64 P63 P62 P61 P60 R/W R/W R/W R/W R/W R/W R/W R/W Bit 0 ~ Bit 8 (P60 ~ P67) : 8-bit PORT6(0~7) I/O data register You can use the IOC register to define each bit as input or output. 7.2.7.2 PAGE1 (LCD data) 7 6 5 4 3 2 1 0 LCDD7 LCDD6 LCDD5 LCDD4 LCDD3 LCDD2 LCDD1 LCDD0 R/W R/W R/W R/W R/W R/W R/W R/W Bit 0 ~ Bit 7 (LCDD0 ~ LCDD7 ) : LCD data buffer for LCD RAM read or write LCD Data vs. COM-SEG LCD Address LCDD7 ~ LCDD4 LCDD3 ~ LCDD0 (LCDA3 ~ LCDA0) COM3 ~ COM0 COM3 ~ COM0 SEG1 SEG0 00H SEG3 SEG2 01H SEG5 SEG4 02H SEG7 SEG6 03H SEG9 SEG8 04H SEG11 SEG10 05H SEG13 SEG12 06H SEG15 SEG14 07H SEG17 SEG16 08H SEG19 SEG18 09H 7.2.8 R7 (PORT7 I/O data, Data RAM bank) 7.2.8.1 PAGE0 (PORT7 I/O data register) 7 6 5 4 3 2 1 0 P77 P76 P75 P74 P73 P72 P71 P70 R/W R/W R/W R/W R/W R/W R/W R/W Bit 0 ~ Bit 7 (P70 ~ P77) : 8-bit PORT7 (0~7) I/O data register You can use the IOC register to define each bit as input or output. Product Specification (V3.6) 02.02.2005 (This specification is subject to change without further notice) • 13 EM78568 8-Bit Microcontroller for FRS 7.2.8.2 PAGE1 (VOX detection output, CTCSS detection output, Data RAM bank selection bit) 7 6 5 4 3 2 1 0 - DETO - - - - - RAM_B0 R R/W-0 Bit 0 (RAM_B0) : Data RAM bank selection bit Each bank has address 0 ~ address 255 which is total 256 (0.25k) bytes RAM size. Data RAM bank selection : (Total RAM = 1.0K) RAM_B1 RAM_B0 RAM bank 0 0 Bank0 0 1 Bank1 1 0 Bank2 1 1 Bank3 Bit 1 ~ Bit 5 : (undefined) not allowed to use Bit 6(DETO) : CTCSS tone detection The signal passing CTCSS sub audio LPF will be extracted CTCSS tone. Then this tone will go into the ZC(Zero-crossing detector) and output to DETO bit. This bit reflects the CTCSS tone frequency pulse waveform. The user can count the timing to get the CTCSS frequency. Also see IOCE PAGE1 for CTCSS block and switch control. Bit 7 : (undefined) not allowed to use 7.2.9 R8 (PORT8 I/O data, Data RAM address) 7.2.9.1 PAGE0 (PORT8 I/O data register) 7 6 5 4 3 2 1 0 P87 P86 P85 P84 P83 P82 P81 P80 R/W R/W R/W R/W R/W R/W R/W R/W Bit 0 ~ Bit 7 (P80 ~ P87) : 8-bit PORT8(0~7) I/O data register User can use IOC register to define input or output each bit. 7.2.9.2 PAGE1 (Data RAM address register) 7 6 RAM_A7 RAM_A6 R/W-0 R/W-0 5 4 3 2 1 0 RAM_A5 RAM_A4 RAM_A3 RAM_A2 RAM_A1 RAM_A0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 Bit 0 ~ Bit 7 (RAM_A0 ~ RAM_A7) : data RAM address The data RAM bank’s selection is from R7 PAGE1 bit0 ~ bit 1 (RAM_B0 ~ RAM_B1). 14 • Product Specification (V3.6) 02.02.2005 (This specification is subject to change without further notice) EM78568 8-Bit Microcontroller for FRS 7.2.10 R9 (PORT9 I/O data, Data RAM data buffer) 7.2.10.1PAGE0 (PORT9 I/O data register) 7 6 5 4 3 2 1 0 P97 P96 P95 P94 P93 P92 P91 P90 R/W R/W R/W R/W R/W R/W R/W R/W Bit 0 ~ Bit 7 (P90 ~ P97) : 8-bit PORT9(0~7) I/O data register User can use IOC register to define input or output each bit. Product Specification (V3.6) 02.02.2005 (This specification is subject to change without further notice) • 15 EM78568 8-Bit Microcontroller for FRS 7.2.10.2PAGE1 (Data RAM data register) 7 6 RAM_D7 RAM_D6 R/W R/W 5 4 3 2 1 0 RAM_D5 RAM_D4 RAM_D3 RAM_D2 RAM_D1 RAM_D0 R/W R/W R/W R/W R/W R/W Bit 0 ~ Bit 7 (RAM_D0 ~ RAM_D7) : Data RAM’s data The address for data RAM is accessed from R8 PAGE1. The data RAM bank is selected by R7 PAGE1 Bit 0 ~ Bit 1 (RAM_B0 ~ RAM_B1). 7.2.11 RA (PLL, Main clock selection, Comparator flag, Watchdog timer, DAC input data buffer) 7.2.11.1 PAGE0 (PLL enable bit, Main clock selection bits, Comparator control bits, Watchdog timer enable bit) 7 6 5 4 3 2 1 0 IDLE PLLEN CLK2 CLK1 CLK0 CMPFLAG CMPREF WDTEN R/W-0 R/W-0 R/W-0 R/W-1 R/W-1 R R/W-0 R/W-0 Bit 0(WDTEN) : Watch dog control bit User can use WDTC instruction to clear watch dog counter. The counter 's clock source is 32768/2 Hz. If the prescaler assigns to TCC. Watch dog will time out by (1/32768 )*2 * 256 = 15.616mS. If the prescaler assigns to WDT, the time of time out will be more times depending on the ratio of prescaler. 0/1 Î disable/enable Bit 1(CMPREF) : Comparator’s reference voltage source selection bit 0 Î Comparator’s reference voltage is driven from internal bias resistor string. This reference voltage level can be set by RD PAGE0 bit 0 ~ bit 5 (CMP_B0 ~ CMP_B5). 1 Î Comparator’s reference voltage is driven from external bias. This reference voltage input is CMP3/P65 pin. Also IOC6 PAGE1 bit 2(CMP63/P63) should be set to “1”. Bit 2(CMPFLAG) : Output of the comparator 0 Î Input voltage < reference voltage 1 Î input voltage > reference voltage Bit 3 ~ Bit 5 (CLK0 ~ CLK2) : MAIN clock selection bits User can choose different frequency of main clock by CLK1 and CLK2. All the clock selection is list below. 16 • Product Specification (V3.6) 02.02.2005 (This specification is subject to change without further notice) EM78568 8-Bit Microcontroller for FRS PLLEN CLK2 CLK1 CLK0 Sub clock MAIN clock CPU clock 1 0 0 0 32.768kHz 447.829kHz 447.829kHz (Normal mode) 1 0 0 1 32.768kHz 895.658kHz 895.658kHz (Normal mode) 1 0 1 0 32.768kHz 1.791MHz 1.791MHz (Normal mode) 1 0 1 1 32.768kHz 3.582MHz 3.582MHz (Normal mode) 1 1 0 0 32.768kHz 7.165MHz 7.165MHz (Normal mode) 1 1 0 1 32.768kHz 10.747MHz 10.747MHz (Normal mode) 1 1 1 0 32.768kHz 14.331MHz 14.331MHz (Normal mode) 1 1 1 1 32.768kHz 17.913MHz 17.913MHz (Normal mode) 0 don’t care don’t care 32.768kHz don’t care 32.768kHz (Green mode) Bit 6(PLLEN) : PLL's power control bit which is CPU mode control register 0/1 Î disable PLL/enable PLL If enable PLL, CPU will operate at normal mode (high frequency). Otherwise, it will run at green mode (low frequency, 32768 Hz). 447.8293kHz ~17.9132MHz CLK2 ~ CLK0 PLL circuit 1 switch ENPLL System clock 0 Sub-clock 32.768kHz Fig.4 The relation between 32.768kHz and PLL Bit 7(IDLE) : Sleep mode or IDLE mode control after using "SLEP" instruction. 0/1 Î SLEEP mode/IDLE mode. This bit will decide SLEP instruction which mode to go. The status after wake-up and the wake-up sources list as the table below. Product Specification (V3.6) 02.02.2005 (This specification is subject to change without further notice) • 17 EM78568 8-Bit Microcontroller for FRS Wakeup signal TCC time out SLEEP mode IDLE mode RA(7,6)=(0,0) RA(7,6)=(1,0) + SLEP + SLEP No function (1) Wake-up IOCF bit0=1 (2) Jump to SLEP next instruction COUNTER1 time out No function (1) Wake-up IOCF bit1=1 (2) Jump to SLEP next instruction COUNTER2 time out No function (1) Wake-up IOCF bit2=2 (2) Jump to SLEP next instruction WDT time out Reset and jump to address 0 Reset and Jump to address 0 RE PAGE0 bit3 or bit4 or bit5 or bit6 = 1 (1) Wake-up (2) Next instruction (1) Wake-up PORT8(0~3) PORT7(0~3) IOCF bit3 or bit4 or bit5 or bit7=1 Reset and Jump to address 0 (2) Jump to SLEP next instruction (1) Wake-up (2) Jump to SLEP next instruction Note PORT70 's wakeup function is controlled by IOCF bit 3. It's falling edge or rising edge trigger (controlled by CONT register bit7). PORT7(1~3) 's wakeup functions are controlled by IOCF bit (4,5,7). They are falling edge trigger. PORT80~PORT83’s wakeup function are controlled by RE PAGE0 bit 0 ~ bit 3. They are falling edge trigger. 7.2.11.2PAGE1 (DAC input data register) 7 6 5 4 3 2 1 0 DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 Bit 0 ~ Bit 7 (DA0 to DA7) : DA converter data buffer 7.2.12 RC (PORTC0 I/O data, Counter1 data) 7.2.12.1PAGE0 (PORT9 I/O data register) 7 6 5 4 3 2 1 0 - - - - - - - PC0 R/W Bit 0 (PC0) : PORTC0 I/O data register 18 • Product Specification (V3.6) 02.02.2005 (This specification is subject to change without further notice) EM78568 8-Bit Microcontroller for FRS User can use IOC register to define input or output this bit. Bit 1 ~ Bit 7 : (undefined) not allowed to use 7.2.12.2PAGE1 (Counter1 data register) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 CN17 CN16 CN15 CN14 CN13 CN12 CN11 CN10 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 Bit 0 ~ Bit 7 (CN10 ~ CN17) : Counter1's buffer that user can read and write. Counter1 is a 8-bit up-counter with 8-bit prescaler that user can use RC PAGE1 to preset and read the counter.(write Î preset) After a interruption , it will reload the preset value. Example for writing : MOV 0x0C, A ; write the data at accumulator to counter1 (preset) Example for reading : MOV A, 0x0C ; read the data at counter1 to accumulator 7.2.13 RD (LCD control, Counter2 data) 7.2.13.1PAGE0 (LCD driver control bits) 7 6 5 4 3 2 1 0 DETOED - - - - LCD_C1 LCD_C0 LCD_M R/W-0 R/W-0 R/W-0 R/W-0 Bit 0 (LCD_M) : LCD operation method including duty and frame frequency Bit 1 ~ Bit 2 (LCD_C0 ~ LCD_C1) : LCD display control LCD_C1 LCD_C0 LCD_M LCD Display Control Duty Bias 0 0 0 change duty 1/4 1/3 1 Disable(turn off LCD) 1/2 1/3 0 1 : Blanking : : 1 1 : LCD display enable : : Ps. To change the display duty must set the "LCD_C1 ,LCD_C0" to "00". The controller can drive LCD directly. The LCD block is made up of common driver, segment driver, display LCD RAM, common output pins, segment output pins and LCD operating power supply. The basic structure contains a timing control. This timing control uses the basic frequency 32.768KHz to generate the proper timing for different duty and display access. Product Specification (V3.6) 02.02.2005 (This specification is subject to change without further notice) • 19 EM78568 8-Bit Microcontroller for FRS RD PAGE0 Bit 0 ~ Bit 2 are LCD control bits for LCD driver. These LCD control bits determine the duty, the number of common and the frame frequency. The LCD display (disable, enable, blanking) is controlled by Bit 1 and Bit 2. The driving duty is decided by Bit 0. The display data is stored in LCD RAM which address and data access controlled by registers R5 PAGE1 and R6 PAGE1. You can regulate the contrast of the LCD display by IOC5 PAGE0 Bit 0 ~ Bit 3 (BIAS0 ~ BIAS3). Up to 16 levels contrast is convenient for better display. Bit 3 ~ Bit 6 : (undefined) not allowed for use. Bit 7 (DETOED) : the interrupt triggering edge control for CTCSS tone detection output 0/1 Î falling edge/falling and rising 7.2.13.2 PAGE1 (Counter2 data register) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 CN27 CN26 CN25 CN24 CN23 CN22 CN21 CN20 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 Bit 0 ~ Bit 7 (CN20 ~ CN27) : Counter2's buffer that you can read and write. Counter2 is an 8-bit up-counter with 8-bit prescaler that you can use with RD PAGE1 to preset and read the counter.(write Î preset) After an interrupt, it will reload the preset value. Example for writing: MOV 0x0D, A ; write the data at accumulator to counter2 (preset) Example for reading: MOV A, 0x0D ; read the data at counter2 to accumulator 7.2.14 RE (Wake-up control, DAC tone output frequency selection) 7.2.14.1PAGE0 (Interrupt flag, Wake-up control bits) 7 6 5 4 3 2 1 0 - - - - /WUP83 /WUP82 /WUP81 /WUP80 R/W-0 R/W-0 R/W-0 R/W-0 Bit 0 (/WUP80) : PORT80 wake-up control, 0/1 Î disable/enable P80 pin wake-up function Bit 1 (/WUP81) : PORT81 wake-up control, 0/1 Î disable/enable P81 pin wake-up function Bit 2 (/WUP82) : PORT82 wake-up control, 0/1 Î disable/enable P82 pin wake-up function 20 • Product Specification (V3.6) 02.02.2005 (This specification is subject to change without further notice) EM78568 8-Bit Microcontroller for FRS Bit 3 (/WUP83) : PORT83 wake-up control, 0/1 Î disable/enable P83 pin wake-up function Bit 4 ~ Bit 7 : (undefined) not allowed for use 7.2.14.2PAGE1 (Programmable D/A tone selection register) 7 6 5 4 3 2 1 0 DAT7 DAT6 DAT5 DAT4 DAT3 DAT2 DAT1 DAT0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 Bit 0 ~ Bit 7 (DAT0 ~ DAT7) : D/A tone output frequency selection The programmable D/A tone output frequency = 447829Hz / Mi / 32, where Mi = DAT7 ~ DAT0 = 1 ~ 255 When Mi = DAT7 ~ DAT0 = 0 or DAT/DAD (IOCA PAGE1 Bit 7) = 0, the D/A tone output generator circuit will be disabled. It is specially used for CTCSS tone generation. Also refer to DAC for details DAC Tone Gen. fm = 447.829kHz to DAC input MUX DA7~DA0 DAT7~DAT0 DAT/DAD Fig.5 Programmable DAC tone generation Example : CTCSS tone generation : Channel DAT7~DAT0 D/A tone generation CTCSS tone Mi Act. Freq. - 00000000 Disable - - - 1 11010001 Enable 67.0 209 66.960 2 11001010 69.3 202 69.280 3 11000011 71.9 195 71.767 4 10111100 74.4 188 74.440 5 10110110 77.0 182 76.894 6 10110000 79.7 176 79.515 7 10101010 82.5 170 82.322 8 10100100 85.4 164 85.333 9 10011110 88.5 158 88.574 10 10011001 91.5 153 91.468 11 10010100 94.8 148 94.558 12 10010000 97.4 144 97.185 13 10001100 100.0 140 99.962 Product Specification (V3.6) 02.02.2005 (This specification is subject to change without further notice) • 21 EM78568 8-Bit Microcontroller for FRS 22 • 14 10000111 103.5 135 103.664 15 10000011 107.2 131 106.829 Channel DAT7~DAT0 CTCSS tone Mi Act. Freq. 16 01111110 110.9 126 111.069 17 01111010 114.8 122 114.710 18 01110110 118.8 118 118.599 19 01110010 123.0 114 122.760 20 01101110 127.3 110 127.224 21 01101010 131.8 106 132.025 22 01100111 136.5 103 135.870 23 01100011 141.3 99 141.360 24 01100000 146.2 96 145.778 25 01011100 151.4 92 152.116 26 01011001 156.7 89 157.243 27 01011000 159.8 88 159.030 28 01010110 162.2 86 162.729 29 01010011 167.9 83 168.610 30 01010001 173.8 81 172.773 31 01001110 179.9 78 179.419 32 01001100 183.5 76 184.140 33 01001011 186.2 75 186.595 34 01001010 189.9 74 189.117 35 01001001 192.8 73 191.708 36 01000111 196.6 71 197.108 37 01000110 199.5 70 199.924 38 01000101 203.5 69 202.821 39 01000100 206.5 68 205.804 40 01000010 210.7 66 212.040 41 01000000 218.1 64 218.667 42 00111110 225.7 62 225.720 43 00111101 229.1 61 229.421 44 00111100 233.6 60 233.244 45 00111010 241.8 58 241.287 46 00111000 250.3 56 249.905 47 00110111 254.1 55 254.448 D/A tone generation Product Specification (V3.6) 02.02.2005 (This specification is subject to change without further notice) EM78568 8-Bit Microcontroller for FRS 7.2.15 RF (Interrupt status) (Interrupt status register) 7 6 5 4 3 2 1 0 INT3 DETO INT2 INT1 INT0 CNT2 CNT1 TCIF R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 "1" means interrupt request, "0" means non-interrupt Bit 0(TCIF) : TCC timer overflow interrupt flag Set when the TCC timer overflows. Bit 1(CNT1) : counter 1 timer overflow interrupt flag Set when counter1 timer overflows. Bit 2(CNT2) : Counter 2 timer overflow interrupt flag Set when counter2 timer overflows. Bit 3(INT0) : External INT0 pin interrupt flag If PORT70 has a falling edge/rising edge (controlled by the CONT register) trigger signal, CPU will set this bit. Bit 4(INT1) : External INT1 pin interrupt flag If PORT71 has a falling edge trigger signal, CPU will set this bit. Bit 5(INT2) : External INT2 pin interrupt flag If PORT72 has a falling edge trigger signal, CPU will set this bit. Bit 6(DETO) : CTCSS tone detection interrupt flag If CTCSS detection output signal (R7 PAGE1 bit 6) has an edge signal (falling edge, falling and rising edge), CPU will set this bit. Bit 7(INT3) : external INT3 pin interrupt flag If PORT73 has a falling edge trigger signal, CPU will set this bit. Note IOCF is the interrupt mask register. User can read and clear. Product Specification (V3.6) 02.02.2005 (This specification is subject to change without further notice) • 23 EM78568 8-Bit Microcontroller for FRS Trigger edge as shown in the table Signal Trigger TCC Time out COUNTER1 Time out COUNTER2 Time out Falling INT0 Rising edge INT1 Falling edge INT2 Falling edge Falling edge DETO Falling and rising edge R10~R3F (General Purpose Register) R10~R3F (Banks 0 ~ 3) : all are general purpose registers. 7.3 Special Purpose Registers 7.3.1 A (Accumulator) Internal data transfer, or instruction operand holding It is not an addressable register. 7.3.2 CONT (Control Register) 7 6 5 4 3 2 1 0 P70EG INT TS RETBK PAB PSR2 PSR1 PSR0 Bit 0 ~ Bit 2 (PSR0 ~ PSR2) : TCC/WDT prescaler bits 24 • PSR2 PSR1 PSR0 TCC Rate WDT Rate 0 0 0 1:2 1:1 0 0 1 1:4 1:2 0 1 0 1:8 1:4 0 1 1 1:16 1:8 1 0 0 1:32 1:16 1 0 1 1:64 1:32 1 1 0 1:128 1:64 1 1 1 1:256 1:128 Product Specification (V3.6) 02.02.2005 (This specification is subject to change without further notice) EM78568 8-Bit Microcontroller for FRS Bit 3(PAB) : Prescaler assignment bit 0/1 Î TCC/WDT Bit 4(RETBK) : Return backup control value for the interrupt routine 0 Î disable/enable When this bit is set to 1, the CPU will automatically store the ACC, R3 status and R5 PAGE after an interrupt is triggered. And it will be restored after instruction RETI. When this bit is set to 0, you need to store ACC, R3 and R5 PAGE in your program. Bit 5(TS) : TCC signal source 0 Î internal instruction clock cycle 1 Î 16.384kHz Bit 6 (INT) : INT enable flag 0 Î interrupt masked by DISI or hardware interrupt 1 Î interrupt enabled by ENI/RETI instructions Bit 7(P70EG) : interrupt edge type of P70 0 Î P70 's interruption source is a rising edge signal. 1 Î P70 's interruption source is a falling edge signal. CONT register is readable (CONTR) and writable (CONTW). TCC and WDT : There is an 8-bit counter available as prescaler for the TCC or WDT. The prescaler is available for TCC only or WDT only at the same time. An 8 bit counter is available for TCC or WDT as determined by the status of the bit 3 (PAB) of the CONT register. See the prescaler ratio in CONT register. Fig.17 depicts the circuit diagram of TCC/WDT. Both TCC and prescaler will be cleared by instructions which write to TCC each time. The prescaler will be cleared by the WDTC and SLEP instructions, when assigned to WDT mode. The prescaler will not be cleared by SLEP instructions, when assigned to TCC mode. Product Specification (V3.6) 02.02.2005 (This specification is subject to change without further notice) • 25 EM78568 8-Bit Microcontroller for FRS 16.38KHz Fig.6 Block Diagram of TCC and WDT 7.3.3 IOC5 (PORT5 I/O control, LCD bias control, Comparator control) 7.3.3.1 PAGE0 (LCD bias control bits) 7 6 5 4 3 2 1 0 IOC57 IOC56 IOC55 - BIAS3 BIAS2 BIAS1 BIAS0 R/W-1 R/W-1 R/W-1 R/W-0 R/W-0 R/W-0 R/W-0 Bit 0 ~ Bit 3 (BIAS0 ~ BIAS3) : LCD operation voltage selection. Vop = VDD * (1 - n/60), where n = 0 ~ 15 BIAS3 BIAS2 BIAS1 BIAS0 Vop (=VDD-VLCD) Example (VDD = 3V) 0 0 0 0 VDD * (1-0/60) 3V 0 0 0 1 VDD * (1-1/60) 2.95V 0 0 1 0 VDD * (1-2/60) 2.90V 0 0 1 1 VDD * (1-3/60) 2.85V 0 1 0 0 VDD * (1-4/60) 2.80V : : : : : : 1 1 0 1 VDD * (1-13/60) 2.35V 1 1 1 0 VDD * (1-14/60) 2.30V 1 1 1 1 VDD * (1-15/60) 2.25V Bit 4 : (undefined) not allowed for use 26 • Product Specification (V3.6) 02.02.2005 (This specification is subject to change without further notice) EM78568 8-Bit Microcontroller for FRS Bit 5 ~ Bit 7 (IOC55 ~ IOC57) : PORT5 (5~7) I/O direction control register 0 Î put the relative I/O pin as output 1 Î put the relative I/O pin into high impedance VDD Driver Resistor and Switch V1 V2 VLCD 4 BIAS3 to BIAS0 Bias Resistor and Switch Fig.7 LCD Driver Bias Circuit Product Specification (V3.6) 02.02.2005 (This specification is subject to change without further notice) • 27 EM78568 8-Bit Microcontroller for FRS Frame VDD V1 COM 0 V2 VLCD VDD V1 COM 1 V2 VLCD VDD V1 COM 2 V2 VLCD VDD V1 COM 3 V2 VLCD VDD V1 SEG V2 VLCD dark VDD V1 SEG V2 VLCD light Fig.8 Type1’s LCD Waveform for 1/3 bias, 1/4 duty (Type 0 is no longer available in this mask version) 28 • Product Specification (V3.6) 02.02.2005 (This specification is subject to change without further notice) EM78568 8-Bit Microcontroller for FRS Frame VDD V1 COM 0 V2 VLCD VDD V1 COM 1 V2 VLCD VDD V1 SEG V2 VLCD dark VDD V1 SEG V2 VLCD light Fig.9 Type1’s LCD Waveform for 1/3 bias, 1/2 duty (Type0 is no longer available in this mask version) 7.3.3.2 PAGE1 (Comparator Control Register) 7 6 5 4 3 2 1 0 CMPEN CMPS1 CMPS0 CMP_B4 CMP_B3 CMP_B2 CMP_B1 CMP_B0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 If you define CMP1/P63 pin, CMP2/P64 pin or CMP3/P65 pin (by CMPIN1, CMPIN2, CMPIN3 at IOCE page1) as CMP1, CMP2 pin or CMP3 pin (comparator’s input pins), you can use this register to control the comparator's function. Bit 0 ~ Bit 4 (CMP_B0 ~ CMP_B4) : Reference voltage selection of internal bias resistor string Voltage = VR x ( n + 0.5 )/ 32 , n=0 to 31. Set RB bit 6 (VREF) to select VR = VREG or 2.0V Product Specification (V3.6) 02.02.2005 (This specification is subject to change without further notice) • 29 EM78568 8-Bit Microcontroller for FRS Bit 5 ~ Bit 6 (CMPS0 ~ CMPS1) : Comparator’s channel selection bits from CMP1 to CMP3 Bit 7(CMPEN) : Enable bit of the comparator circuit 0/1 Î disable/enable the comparator circuit CMPS1 CMPS0 Input 0 0 CMP1 0 1 CMP2 1 0 CMP3 1 1 Reserved The relation between these registers is shown in Fig.10. Ps. VRSEL bit is in IOCA PAGE1 bit 4. 30 • Product Specification (V3.6) 02.02.2005 (This specification is subject to change without further notice) EM78568 8-Bit Microcontroller for FRS Nam P62 e P63 S 64 S P S CMP1/P62 Register bit location IOC6 PAGE1 bit IOC6 PAGE1 bit 2 IOC6 PAGE1 bit 3 4 CMP1 MUX PORT62 P62S CMP2/P63 CMP2 MUX + MUX CMPFLAG PORT63 2 P63S CMP3/P64 CMPS1 CMPS0 CMP3 MUX PORT64 1 0 P64S MUX VDD 2.5V ref REFEN 2.5V MUX VR CMPREF CMPEN VRSEL 1/2R 11111 R 11110 (This ckt is form DAC) R MUX 00000 1/2R 5 CMP_B4 to CMP_B0 Nam e CMPE NCMPS1 ~ CMP_B4 CMPS0 ~ CMP_B0 VRSEL Register bit location IOC5 PAGE1 bit IOC5 PAGE1 bit 6 ~ 7 IOC5 PAGE1 5 bit 4 ~ 0 IOCA PAGE1 bit 4 Name CMPREF CMPFLAG Register bit location RA PAGE0 bit 1 RA PAGE0 bit 2 Fig.10 The Comparator Circuit Product Specification (V3.6) 02.02.2005 (This specification is subject to change without further notice) • 31 EM78568 8-Bit Microcontroller for FRS CMPEN CMP1 to CMP3 reference voltage Setup time 10us CPU clock CMPFLAG Compare start Fig.11 The Comparator Timing Compare end 7.3.4 IOC6 (PORT6 I/O control, P6* pins switch control) 7.3.4.1 PAGE0 (PORT6 I/O control register) 7 6 5 4 3 2 1 0 IOC67 IOC66 IOC65 IOC64 IOC63 IOC62 IOC61 IOC60 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 Bit 0 ~ Bit 7 (IOC60 ~ IOC67) : PORT6(0~7) I/O direction control register 0 Î put the relative I/O pin as output 1 Î put the relative I/O pin into high impedance 7.3.4.2 PAGE1 (P6* pins switch control register) 7 6 5 4 3 2 1 0 AMUTE P66S P65S P64S P63S P62S - - R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 Bit 0 ~ Bit 1 : (undefined) not allowed F use Bit 2(P62S) : Select channel 1 input pin of comparator or I/O PORT62 pin 0 Î P62 (I/O PORT62) pin is selected 1 Î CMP1 (Channel 1 input of comparator) pin is selected Bit 3(P63S) : Select channel 2 input pin of comparator or I/O PORT63 pin 0 Î P63 (I/O PORT63) pin is selected 32 • Product Specification (V3.6) 02.02.2005 (This specification is subject to change without further notice) EM78568 8-Bit Microcontroller for FRS 1 Î CMP2 (Channel 2 input of comparator) pin is selected Bit 4(P64S) : Select channel 3 input pin of comparator or I/O PORT64 pin 0 Î P64 (I/O PORT64) pin is selected 1 Î CMP3 (Channel 3 input of comparator) pin is selected Bit 5(P65S) : Select receiving audio output pin of CTCSS or I/O PORT65 pin 0 Î P65 (I/O PORT65) pin is selected 1 Î AURX (Receiving audio output pin of CTCSS) pin is selected Bit 6(P66S) : Select modulation transmitting output pin of CTCSS or I/O PORT66 pin 0 Î P66 (I/O PORT66) pin is selected 1 Î MTX (Modulation transmitting output of CTCSS) pin is selected Bit 7(AMUTE) : Audio mute for MIC AMP of CTCSS block 0 Î Voice transmitting path from MIC AMP output 1 Î Audio mute from MIC AMP output Refer to Fig.14 CTCSS block for details. 7.3.5 IOC7 (PORT7 I/O control, PORT7 pull high control) 7.3.5.1 PAGE0 (PORT7 I/O control register) 7 6 5 4 3 2 1 0 IOC77 IOC76 IOC75 IOC74 IOC73 IOC72 IOC71 IOC70 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 Bit 0 ~ Bit 7 (IOC70 ~ IOC77) : PORT7(0~7) I/O direction control register 0 Î put the relative I/O pin as output 1 Î put the relative I/O pin into high impedance 7.3.5.2 PAGE1 (PORT7 pull high control register) 7 6 5 4 3 2 1 0 PH77 PH76 PH75 PH74 PH73 PH72 PH71 PH70 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 Bit 0 ~ Bit 7 (PH70 ~ PH77) : PORT7 bit0~bit7 pull high control register 0 Î disable pull high function 1 Î enable pull high function Product Specification (V3.6) 02.02.2005 (This specification is subject to change without further notice) • 33 EM78568 8-Bit Microcontroller for FRS 7.3.6 IOC8 (PORT8 I/O control, PORT8 pull high control) 7.3.6.1 PAGE0 (PORT8 I/O control register) 7 6 5 4 3 2 1 0 IOC87 IOC86 IOC85 IOC84 IOC83 IOC82 IOC81 IOC80 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 Bit 0 ~ Bit 7 (IOC80 ~ IOC87) : PORT8(0~7) I/O direction control register 0 Î put the relative I/O pin as output 1 Î put the relative I/O pin into high impedance 7.3.6.2 PAGE1 (PORT8 pull high control register) 7 6 5 4 3 2 1 0 PH87 PH86 PH85 PH84 PH83 PH82 PH81 PH80 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 Bit 0 ~ Bit 7 (PH80 ~ PH87) : PORT8 bit0~bit7 pull high control register 0 Î disable pull high function 1 Î enable pull high function 7.3.7 IOC9 (PORT9 I/O control, PORT9 switches) 7.3.7.1 PAGE0 (PORT9 I/O control register) 7 6 5 4 3 2 1 0 IOC97 IOC96 IOC95 IOC94 IOC93 IOC92 IOC91 IOC90 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 Bit 0 ~ Bit 7 (IOC90 ~ IOC97) : PORT9(0~7) I/O direction control register 0 Î put the relative I/O pin as output 1 Î put the relative I/O pin into high impedance 7.3.7.2 PAGE1 (PORT9 switches) P97S P96S P95S P94S P93S P92S P91S R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 - Bit 0 : (undefined) not allowed for use Bit 1(P91S) : Switch I/O PORT91 or LCD segment signal 34 • Product Specification (V3.6) 02.02.2005 (This specification is subject to change without further notice) EM78568 8-Bit Microcontroller for FRS 0 Î (P91 pin is selected) : normal PORT91 1 Î (SEG19 pin) : SEGMENT output Bit 2(P92S) : Switch I/O PORT92 or LCD segment signal 0 Î (P92 pin is selected) : normal PORT92 1 Î (SEG18 pin) : SEGMENT output Bit 3(P93S) : Switch I/O PORT93 or LCD segment signal 0 Î (P93 pin is selected) : normal PORT93 1 Î (SEG17 pin) : SEGMENT output Bit 4(P94S) : Switch I/O PORT94 or LCD segment signal 0 Î (P94 pin is selected) : normal PORT94 1 Î (SEG16 pin) : SEGMENT output Bit 5(P95S) : Switch I/O PORT95 or LCD segment signal 0 Î (P95 pin is selected) : normal PORT95 1 Î (SEG15 pin) : SEGMENT output Bit 6(P96S) : Switch I/O PORT96 or LCD segment signal 0 Î (P96 pin is selected) : normal PORT96 1 Î (SEG14 pin) : SEGMENT output Bit 7(P97S) : Switch I/O PORT97 or LCD segment signal 0 Î (P97 pin is selected) : normal PORT97 1 Î (SEG13 pin) : SEGMENT output 7.3.8 IOCA (TONE2 control, Control bits for DAC, DAC tone, Reference, VOX and P67 switch) 7.3.8.1 PAGE0 (TONE2 control register) T27 T26 T25 T24 T23 T22 T21 T20 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 Bit 0 ~ Bit 7(T20 ~ T27) : Tone generator 2 ‘s frequency divider and power control Run in Normal mode. Clock source = 111957Hz T27~T20 = ‘11111111’ => Tone generator2 has 438Hz SIN wave output. Product Specification (V3.6) 02.02.2005 (This specification is subject to change without further notice) • 35 EM78568 8-Bit Microcontroller for FRS T27~T20 = ‘00000010’ => Tone generator2 has 55921Hz SIN wave output. T27~T20 = ‘00000001’ => DC bias voltage output T27~T20 = ‘00000000’ => Power off Built-in tone generators can generate dialing tone signals for telephone of dialing tone type or just a single tone. In DTMF application, there are two kinds of tones. One is the group with row frequency (TONE1), the other is the group with column frequency (TONE2), each group has 4 kinds of frequency, you can get a total of 16 kinds of DTMF frequency. The tone generator contains a row frequency sine wave generator for generating the DTMF signal which is selected by IOCD PAGE0, IOCE PAGE0 and a column frequency sine wave generator for generating the DTMF signal which is selected by IOCA PAGE0. This block can generate single tone by filling one of these two registers. If all the values are low, the power of the tone generators will be turned off . TONE1(IOCD, 699.7Hz (0x0A0) 1 2 3 A IOCE PAGE0) 772.1Hz (0x091) 4 5 6 B Low group freq. 854.6Hz (0x083) 7 8 9 C 940.8Hz (0x077) * 0 # D 7.3.8.2 PAGE1 (Control bits for DAC, DAC tone, Reference, VOX and P67 switch) DAT/DAD VREF DATEN VRSEL DAST/P67 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 - - - Bit 0 ~ Bit 2 : (undefined) not allowed for use Bit 3(DAST/P67) : DAC enable control or P67 switch 0 Î switch DAO/P67 pin as normal I/O P67 1 Î enable DAC, enable DAC output buffer B1 and DAC output to DAO/P67 pin When this bit is set by software, the DA converter will start converting and output to DAO/P67 pin. If you clean this bit, the DA converter will stop and the DAO/P67 pin will be become a normal I/O P67. Refer also to bit 5 (DATEN) for DAC power control. Bit 4(VRSEL) : Reference voltage selection bit for Comparator circuit 0/1 Î VDD/2.5V from DAC See also Fig.13 in the next page. 36 • Product Specification (V3.6) 02.02.2005 (This specification is subject to change without further notice) EM78568 8-Bit Microcontroller for FRS Bit 5(DATEN) : DAC enable control 0/1 Î disable/enable DAC and its tone output buffer B2 When this bit is set by software, the DA converter will start converting and output to internal CTCSS VTX3 end. If you clean this bit, the DA converter will stop and the DAO tone output buffer B2 is disabled. Refer also to bit 3 (DAST/P67) for DAC power control. Bit 6(VREF) : Reference voltage selection bit for the DA converter circuit DAC reference setting is shown as follows. Also see Fig.12 and Fig.13 in the next page. ASW3 VREF DATEN DAST/P67 Function 1 x 1 x Select 2.5V ref, enable 2.5V ref, enable DAC, 0 1 1 x Enable buffer B2, buffer B2 output to CTCSS LPF 0 0 1 x Select VDD, disable 2.5V, enable DAC, enable buffer B2 x 1 0 1 Select 2.5V ref, enable 2.5V ref, enable DAC, enable buffer B1, buffer B1 output to DAO/P67 pin x 0 0 1 Select VDD, disable 2.5V, enable DAC, enable buffer B1, buffer B1 output to DAO/P67 pin Ps. IOCE PAGE1 bit 2 (ASW3), IOCA PAGE1 bit 6 (VREF), IOCA PAGE1 bit 5 (DATEN), IOCA PAGE1 bit 3 (DAST/P67) VDD MUX CMPEN 2.5V ref MUX VRSEL To ladder resistors (This circuit is from theComparator) REFSEL REFEN VRX3 2R DAC input 8-bit DAC input data buffer B2 R DATEN VTX3 MUX To Sub-Audio LPF ASW3 (This circuit is from CTCSS) 2R R DAO/P67 B1 2R 2R DAST/P67 Product Specification (V3.6) 02.02.2005 (This specification is subject to change without further notice) PORT67 • 37 EM78568 8-Bit Microcontroller for FRS Fig.12 D/A converter (DAC) ASW3 REFSEL VREF REFEN DATEN DAST/P67 CMPEN VRSEL Fig.13 DAC reference voltage control logic Bit 7(DAT/DAD) : Programmable D/A tone generation or D/A input data enable control 0 Î Enable D/A input data and disable D/A tone generation (also stop to D/A tone generation) 1 Î Enable Programmable D/A tone generation and disable D/A input data 7.3.9 IOCC (PORTC I/O control, PORT switch) 7.3.9.1 PAGE0 (PORTC I/O control register) 7 6 5 4 3 2 1 0 - - - - - - - IOCC0 R/W-1 Bit 0 (IOCC0) : PORTC0 I/O direction control register Bit 1 ~ Bit 7 : (undefined) not allowed to use 7.3.9.2 PAGE1 (PORT switch) 7 6 5 4 3 2 1 0 - - - - - P5SH - - R/W-0 Bit 0 ~ Bit 1 : (undefined) not allowed to use Bit 2(P5SH) : Switch I/O PORT5 high nibble(5~7) or LCD segment signal 0 Î (P55 ~ P57 pins are selected) : normal PORT5 high nibble(5~7) 1 Î (SEG10 ~ SEG12 pins are selected) : SEGMENT output Bit 3 ~ Bit 7 : (undefined) not allowed to use 38 • Product Specification (V3.6) 02.02.2005 (This specification is subject to change without further notice) EM78568 8-Bit Microcontroller for FRS 7.3.10 IOCD (TONE1 control, Clock source, Prescaler of CN1 and CN2) 7.3.10.1PAGE0 (TONE1 control) 7 6 5 4 3 2 1 0 T17 T16 T15 T14 T13 T12 T11 T10 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 Bit 0 ~ Bit 7 (T10 ~ T17) : Tone generator 1‘s frequency divider and power control Please Run in Normal mode. Clock source = 111957Hz and Freq. = 111957Hz / N, where N is divider value for T1A ~ T10 (T1A ~ T18 are in the IOCE PAGE0 Bit 2 ~ Bit 0. If T20 ~ T18 are all “0”, then T17 ~ T10 = ‘11111111’ => Tone generator1 will has 439Hz SIN wave output. : T17~T10 = ‘00000010’ => Tone generator1 will has 55978Hz SIN wave output. T17~T10 = ‘00000001’ => DC bias voltage output T17~T10 = ‘00000000’ => Power off 7.3.10.2PAGE1 (Clock source and prescaler for COUNTER1 and COUNTER2) 7 6 CNT2S C2_PSC2 R/W-0 R/W-0 5 4 C2_PSC1 C2_PSC0 R/W-0 R/W-0 3 2 CNT1S C1_PSC2 R/W-0 R/W-0 1 0 C1_PSC1 C1_PSC0 R/W-0 R/W-0 Bit 0 ~ Bit 2 (C1_PSC0 ~ C1_PSC2) : COUNTER1 prescaler ratio C1_PSC2 C1_PSC1 C1_PSC0 COUNTER1 0 0 0 1:2 0 0 1 1:4 0 1 0 1:8 0 1 1 1:16 1 0 0 1:32 1 0 1 1:64 1 1 0 1:128 1 1 1 1:256 Bit 3(CNT1S) : COUNTER1 clock source 0/1 Î 16.384kHz/system clock Product Specification (V3.6) 02.02.2005 (This specification is subject to change without further notice) • 39 EM78568 8-Bit Microcontroller for FRS Bit 4 ~ Bit 6 (C2_PSC0 ~ C2_PSC2) : COUNTER2 prescaler ratio C2_PSC2 C2_PSC1 C2_PSC0 COUNTER2 0 0 0 1:2 0 0 1 1:4 0 1 0 1:8 0 1 1 1:16 1 0 0 1:32 1 0 1 1:64 1 1 0 1:128 1 1 1 1:256 Bit 7(CNT2S) : COUNTER2 clock source 0/1 Î 16.384kHz/system clock 7.3.11 IOCE (TONE1 extra control bits, CTCSS control switches) 7.3.11.1PAGE0 (Interrupt mask, TONE1 extra three control bits) 7 6 5 4 3 2 1 0 - - - - - T1A T19 T18 R/W-0 R/W-0 R/W-0 Bit 0 ~ Bit 2 (T18 ~ T1A) : Most significant 3 bits of Tone generator 1‘s frequency divider and power control These 3 bits and other 8 bits (IOCA PAGE0 bit 7 ~ bit0) are assembled as 11-bit frequency divider for Tone generator 1 Bit 3 ~ Bit 7 = 0 : (undefined) not allowed to use 7.3.11.2PAGE1 (CTCSS control switches) 7 6 5 4 3 2 1 0 TXPWR RXPWR BPFPWR LPFPWR ASW4 ASW3 ASW2 ASW1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 Bit 0(ASW1) : Analog switch-1 control for multi-plexer in the CTCSS block 0 Î Select VRX1 input 1 Î Select VTX1 input Bit 1(ASW2) : Analog switch-2 control for multi-plexer in the CTCSS block 0 Î Select VRX2 output 40 • Product Specification (V3.6) 02.02.2005 (This specification is subject to change without further notice) EM78568 8-Bit Microcontroller for FRS 1 Î Select VTX2 output Bit 2(ASW3) : Analog switch-3 control for multi-plexer in the CTCSS block 0 Î Select VRX3 input 1 Î Select VTX3 input Bit 3(ASW4) : Analog switch-4 control for multi-plexer in the CTCSS block 0 Î Select VRX4 input 1 Î Select VTX4 input Bit 4(LPFPWR) : Power control for sub-audio LPF in the CTCSS block. 0/1 Î disable/enable Bit 5(BPFPWR) : Power control for audio BPF in the CTCSS block. 0/1 Î disable/enable Bit 6(RXPWR) : RX power control for the CTCSS block 0/1 Î disable/enable Bit 7(TXPWR) : TX power control for the CTCSS block 0/1 Î disable/enable Product Specification (V3.6) 02.02.2005 (This specification is subject to change without further notice) • 41 EM78568 8-Bit Microcontroller for FRS Name P65S P66S AMUTE DETO Register bit location IOC6 PAGE1 bit 5 IOC6 PAGE1 bit 6 IOC6 PAGE1 bit 7 R7 PAGE1 bit 6 RXO RXPWR RXPWR RXI Rx AMP ZC VRF DETO BPFPWR MICO Audio BPF MUX MUX PORT65 AURX/P65 MUX VTX2 MICO MIC AMP AURX VRX2 VRX1 MICI MUX VTX1 ASW2 ASW1 P65S VRF TXPWR AMUTE VRX3 CTCSS tone input VTX3 0dB VRX4 Sub-Audio LPF MUX MUX (from DAC output buffer B2) ASW3 ASW4 LPFPWR Summing AMP -10dB VTX4 VRF TXPWR Name ASW1 ASW2 ASW3 ASW4 LPFPWR BPFPWR RXPWR TXPWR MTX PORT66 MTX/P66 MUX P66S Register bit location IOCE PAGE1 bit 0 IOCE PAGE1 bit 1 IOCE PAGE1 bit 2 IOCE PAGE1 bit 3 IOCE PAGE1 bit 4 IOCE PAGE1 bit 5 IOCE PAGE1 bit 6 IOCE PAGE1 bit 7 Fig.14 CTCSS block 7.3.12 IOCF (Interrupt mask) (Interrupt mask register) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 INT3 DETO INT2 INT1 INT0 CNT2 CNT1 TCIF R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 Bit 0 ~ 7 : interrupt enable bit 0 Î disable interrupt 1 Î enable interrupt 42 • Product Specification (V3.6) 02.02.2005 (This specification is subject to change without further notice) EM78568 8-Bit Microcontroller for FRS The status after interrupt and the interrupt sources list as the table below. Interrupt signal IDLE mode GREEN mode NORMAL mode RA(7,6)=(1,0) RA(7,6)=(x,0) RA(7,6)=(x,1) + SLEP no SLEP no SLEP TCC time out (1) Wake-up Interrupt Interrupt IOCF bit0=1 (2) Interrupt (jump to address 8 at page0) (jump to address 8 at page0) (jump to address 8 at page0) (1) Wake-up Interrupt Interrupt (2)Interrupt (jump to address 8 at page0) (jump to address 8 at page0) (jump to address 8 at page0) And "ENI" (3) after RETI instruction, jump to SLEP Next instruction COUNTER1 time out IOCF bit1=1 And "ENI" (3) after RETI instruction, jump to SLEP Next instruction COUNTER2 time out (1) Wake-up Interrupt Interrupt (2) Interrupt (jump to address 8 at page0) (jump to address 8 at page0) (jump to address 8 at page0) IOCF bit2=2 And "ENI" (3) after RETI instruction, jump to SLEP Next instruction PORT7(0~3) (1) Wake-up Interrupt Interrupt IOCF bit3 or bit4 or bit5 or bit7=1 (2) Interrupt (jump to address 8 at page0) (jump to address 8 at page0) (jump to address 8 at page0) And "ENI" (3) after RETI instruction, jump to SLEP Next instruction DETO No function No function Interrupt IOCF bit6 = 1 (jump to address 8 at page0) And “ENI” Note PORT70 's interrupt function is controlled by IOCF bit 3. It's falling edge or rising edge trigger (controlled by CONT register bit7). PORT7(1~3) 's wakeup functions are controlled by IOCF bit (4,5,7). They are falling edge trigger. DETO’s interrupt function is controlled by IOCF bit 6. It’s falling edge trigger, falling and rising edge trigger (set by RD PAGE0 bit 7). 7.4 I/O Port The I/O registers are bi-directional tri-state I/O ports. The I/O ports can be defined as "input" or "output" pins by the I/O control registers under program control. The I/O data Product Specification (V3.6) 02.02.2005 (This specification is subject to change without further notice) • 43 EM78568 8-Bit Microcontroller for FRS registers and I/O control registers are both readable and writable. The I/O interface circuit is shown in Fig.17. PCRD PORT Q P R Q C L Q P R Q C L D CLK PCWR D CLK IOD PDWR PDRD 0 1 M U X Fig.15 The circuit of I/O port and I/O control register 7.5 RESET The RESET can be caused by (1) Power on voltage detector reset (/POVD) and power on reset (2) WDT timeout. (if enabled and in GREEN or NORMAL mode) (3) /RESET pin pull low Note At case (1), /POVD is controlled by CODE OPTION. If you enable /POVD, CPU will reset at under 1.8V and CPU will consume more current about 5uA. It is used for low voltage reset/ And the power-on reset is a circuit which is always enabled and only works on initially power-on reset. It will reset CPU at about 1.4V and consume about 0.5uA. Once a RESET occurs, the following functions are performed. 44 • The oscillator is running, or will be started. The Program Counter (R2) is set to all "0". Product Specification (V3.6) 02.02.2005 (This specification is subject to change without further notice) EM78568 8-Bit Microcontroller for FRS When power is on, the upper 3 bits of R3 and the upper 2 bits of R4 are cleared. The Watchdog timer and prescaler counter are cleared. The Watchdog timer is disabled. The CONT register is set to all "1" The other register (bit 7 ~ bit 0) default values are as follows. Operation registers : Address R register R register IOC register IOC register PAGE0 PAGE1 PAGE0 PAGE1 0x4 00xxxxxx 0x5 xx0x0000 xxxx0000 111x0000 00000000 0x6 xxxxxxxx xxxxxxxx 11111111 000000xx 0x7 xxxxxxxx xxxxxx00 11111111 00000000 0x8 xxxxxxxx 00000000 11111111 00000000 0x9 xxxxxxxx xxxxxxxx 11111111 0000000x 0xA 00011x00 11111111 00000000 00000xxx 0xC xxxxxxxx 00000000 xxxxxxxx xxxxx0xx 0xD 0xxxx000 00000000 00000000 00000000 0xE xxxx0000 11111111 xxxxx000 00000000 0xF 00000000 0xB 00000000 7.6 Wake-up The controller has two types of sleep mode for power saving: 7.6.1 SLEEP mode, RA(7) = 0 + "SLEP" instruction The controller will turn off all the CPU and crystal. Other circuit with power control like key tone control or PLL control (which has an enable register), you have to turn it off by software. 7.6.2 IDLE mode, RA(7) = 1 + "SLEP" instruction. The controller will turn the CPU off, but not the crystal. Wake-up from SLEEP mode WDT time out External interrupt Product Specification (V3.6) 02.02.2005 (This specification is subject to change without further notice) • 45 EM78568 8-Bit Microcontroller for FRS 7.6.3 /RESET pull low All these cases will reset the controller, and run the program at address zero. The status is just like the power on reset. Be sure to enable the circuit in case (1) or (2). Wake-up from IDLE mode (1) WDT time out (2) External interrupt (3) Internal interrupt like counters For all these cases, you have to enable the circuit before entering IDLE mode. After wake-up, all the registers will keep the values just like with "SLEP" instruction before. In case (2) or (3), the controller will wake up and jump to address 0x08 for interrupt sub-routine. After finishing a sub-routine ("RETI" instruction), the program will jump to the next instruction from "SLEP" instruction. 7.7 Interrupt RF is an interrupt status register which records the interrupt request in flag bit. IOCF is an interrupt mask register. Global interrupt is enabled by ENI instruction and is disabled by DISI instruction. When one of the interrupts (when enabled) is generated, it will allow the next instruction to be fetched from address 008H. Once in the interrupt service routine, the source of the interrupt can be determined by polling the flag bits in the RF register. The interrupt flag bit must be cleared by software before leaving the interrupt service routine and enabling interrupts to avoid recursive interrupts. 7.8 Instruction Set Instruction set has the following features: (1) Every bit of any register can be set, cleared, or tested directly. (2) The I/O register can be regarded as a general register. That is, the same instruction can operate on the I/O register. The symbol "R" represents a register designator which specifies which one of the 64 registers (including operational registers and general purpose registers) is to be utilized by the instruction. Bits 6 and 7 in R4 determine the selected register bank. "b'' represents a bit field designator which selects the number of the bit, located in the register "R'', affected by the operation. "k'' represents an 8 or 10-bit constant or literal value. 46 • Product Specification (V3.6) 02.02.2005 (This specification is subject to change without further notice) EM78568 8-Bit Microcontroller for FRS INSTRUCTION BINARY HEX MNEMONIC OPERATION 0 0000 0000 0000 0000 NOP No Operation None 1 0 0000 0000 0001 0001 DAA Decimal Adjust A C 1 0 0000 0000 0010 0002 CONTW A → CONT None 1 0 0000 0000 0011 0003 SLEP 0 → WDT, Stop oscillator T,P 1 0 0000 0000 0100 0004 WDTC 0 → WDT T,P 1 0 0000 0000 rrrr 000r IOW R A → IOCR None 1 0 0000 0001 0000 0010 ENI Enable Interrupt None 1 0 0000 0001 0001 0011 DISI Disable Interrupt None 1 0 0000 0001 0010 0012 RET [Top of Stack] → PC None 2 0 0000 0001 0011 0013 RETI [Top of Stack] → PC Enable Interrupt None 2 0 0000 0001 0100 0014 CONTR CONT → A None 1 0 0000 0001 rrrr 001r IOR R IOCR → A None 1 0 0000 0010 0000 0020 TBL R2+A → R2 bits 9,10 do not clear Z,C,DC 2 0 0000 01rr rrrr 00rr MOV R,A A→R None 1 0 0000 1000 0000 0080 CLRA 0→A Z 1 0 0000 11rr rrrr 00rr CLR R 0→R Z 1 0 0001 00rr rrrr 01rr SUB A,R R-A → A Z,C,DC 1 0 0001 01rr rrrr 01rr SUB R,A R-A → R Z,C,DC 1 0 0001 10rr rrrr 01rr DECA R R-1 → A Z 1 0 0001 11rr rrrr 01rr DEC R R-1 → R Z 1 0 0010 00rr rrrr 02rr OR A,R A ∨ VR → A Z 1 0 0010 01rr rrrr 02rr OR R,A A ∨ VR → R Z 1 0 0010 10rr rrrr 02rr AND A,R A&R→A Z 1 0 0010 11rr rrrr 02rr AND R,A A&R→R Z 1 0 0011 00rr rrrr 03rr XOR A,R A⊕R→A Z 1 0 0011 01rr rrrr 03rr XOR R,A A⊕R→R Z 1 0 0011 10rr rrrr 03rr ADD A,R A+R→A Z,C,DC 1 0 0011 11rr rrrr 03rr ADD R,A A+R→R Z,C,DC 1 0 0100 00rr rrrr 04rr MOV A,R R→A Z 1 0 0100 01rr rrrr 04rr MOV R,R R→R Z 1 0 0100 10rr rrrr 04rr COMA R /R → A Z 1 0 0100 11rr rrrr 04rr COM R /R → R Z 1 0 0101 00rr rrrr 05rr INCA R R+1 → A Z 1 0 0101 01rr rrrr 05rr INC R R+1 → R Z 1 0 0101 10rr rrrr 05rr DJZA R R-1 → A, skip if zero None 2 if skip Product Specification (V3.6) 02.02.2005 (This specification is subject to change without further notice) STATUS Instruction AFFECTED Cycle • 47 EM78568 8-Bit Microcontroller for FRS INSTRUCTION BINARY HEX MNEMONIC OPERATION STATUS Instruction AFFECTED Cycle 0 0101 11rr rrrr 05rr DJZ R R-1 → R, skip if zero None 2 if skip 0 0110 00rr rrrr 06rr RRCA R R(n) → A(n-1) R(0) → C, C → A(7) C 1 0 0110 01rr rrrr 06rr RRC R R(n) → R(n-1) R(0) → C, C → R(7) C 1 0 0110 10rr rrrr 06rr RLCA R R(n) → A(n+1) R(7) → C, C → A(0) C 1 0 0110 11rr rrrr 06rr RLC R R(n) → R(n+1) R(7) → C, C → R(0) C 1 0 0111 00rr rrrr 07rr SWAPA R R(0-3) → A(4-7) R(4-7) → A(0-3) None 1 0 0111 01rr rrrr 07rr SWAP R R(0-3) ↔ R(4-7) None 1 0 0111 10rr rrrr 07rr JZA R R+1 → A, skip if zero None 2 if skip 0 0111 11rr rrrr 07rr JZ R R+1 → R, skip if zero None 2 if skip 0 100b bbrr rrrr 0xxx BC R,b 0 → R(b) None 1 0 101b bbrr rrrr 0xxx BS R,b 1 → R(b) None 1 0 110b bbrr rrrr 0xxx JBC R,b if R(b)=0, skip None 2 if skip 0 111b bbrr rrrr 0xxx JBS R,b if R(b)=1, skip None 2 if skip 1 00kk kkkk kkkk 1kkk CALL k PC+1 → [SP] (Page, k) → PC None 2 1 01kk kkkk kkkk 1kkk JMP k (Page, k) → PC None 2 1 1000 kkkk kkkk 18kk MOV A,k k→A None 1 1 1001 kkkk kkkk 19kk OR A,k A∨k→A Z 1 1 1010 kkkk kkkk 1Akk AND A,k A&k→A Z 1 1 1011 kkkk kkkk 1Bkk XOR A,k A⊕k→A Z 1 1 1100 kkkk kkkk 1Ckk RETL k k → A, [Top of Stack] → PC None 2 1 1101 kkkk kkkk 1Dkk SUB A,k k-A → A Z,C,DC 1 1 1110 0000 0001 1E01 INT PC+1 → [SP] 001H → PC None 1 1 1110 1000 kkkk 1E8k PAGE k K->R5(3:0) None 1 1 1111 kkkk kkkk 1Fkk ADD A,k k+A → A Z,C,DC 1 7.9 CODE Option Register The controller has one 13-bit CODE option register which is not part of the normal program memory. The option bits cannot be accessed during normal program execution. 48 • Product Specification (V3.6) 02.02.2005 (This specification is subject to change without further notice) EM78568 8-Bit Microcontroller for FRS Bit12 Bit11 Bit10 Bit9 - - - - Bit8 Bit7 Bit6 Bit5 Bit4 Bit3 - - - - - - Bit2 Bit1 Bit0 LCDOPT ROMSEL /POVD Bit 0(/POVD) : Power on voltage detector, 0/1 Î enable/disable This bit is fixed to 1 for disable. Bit 1(ROMSEL) : 16k ROM/8k ROM option, 0/1 Î 16k/8k ROM selection This bit is fixed to 0 for 16K ROM. Bit 2 (LCDOPT) : LCD output waveform option 0 Î default LCD waveform for Type0 LCD waveform 1 Î switch over LCD bias V1 and V2 of segment for Type1 LCD waveform This bit is fixed to 1 for Type1 LCD waveform Bit 3 ~ Bit 12 : unused Product Specification (V3.6) 02.02.2005 (This specification is subject to change without further notice) • 49 EM78568 8-Bit Microcontroller for FRS 7.10 Signal and control paths for DAC, DAC tone gen., CTCSS and Comparator Volgage reference control logic ASW3 REFSEL VREF DATEN DAST/P67 REFEN CMPEN VRSEL VDD VDD (part of Comparator) DAC MUX CMPEN To ladder resistors VRSEL MUX 2.5V ref (part of CTCSS) VRX3 REFSEL REFEN VTX3 B2 DATEN R-2R MUX To Sub-Audio LPF ASW3 DAO/P67 B1 DAST/P67 PORT67 DAC Tone Gen. fm = 447.829kHz DAC Tone Gen. MUX DA7~DA0 DAT7~DAT0 DAT/DAD Name DAST/P67 VRSEL DATEN VREF DAT/DAD CMPEN ASW3 Register bit location IOCA PAGE1 bit 3 IOCA PAGE1 bit 4 IOCA PAGE1 bit 5 IOCA PAGE1 bit 6 IOCA PAGE1 bit 7 IOC5 PAGE1 bit 7 IOCE PAGE1 bit 2 Name Register bit location DAT7 ~ DAT0 RE PAGE1 bit 7 ~ 0 DA7 ~ DA0 RA PAGE1 bit 7 ~ 0 Fig.16 Signal and control paths for analog circuit ps. REFEN, REFSEL are not register bits. 50 • Product Specification (V3.6) 02.02.2005 (This specification is subject to change without further notice) EM78568 8-Bit Microcontroller for FRS The Fig.16 above try to explain how to use built-in 8-bit R-2R DAC. This DAC can be used as general DAC; here is call “DAC general mode”. Also it can be used as FRS CTCSS tone generation; here is called DAC tone generator mode. When you use DAC general mode, you have to software program DAC input data DA7 ~ DA0 bits with different points of value for tone generation. When you use DAC tone generator mode, you just need to set DAT7 ~ DAT0 bits and then the hardware “DAC Tone Gen.” will auto-program DAC to generate corresponding frequency signal output. Using this feature, it is easy and software free to generate accurate CTCSS tone. 7.10.1 DAC program mode： The below item “1” is for DAC general mode. The below item “2,3” are for DAC tone generator mode. (1) DAT/DAD = 0 Î DAC general mode, software-program DAC from DA7 ~ DA0 register bits , disable DAC tone generator。 (2) DAT/DAD = 1 Î DAC tone generator mode, hardware-program DAC by setting DAT7 ~ DAT0 register bits, enable DAC tone generator。 (3) DAT7 ~ DAT0 = 0 Î Disable DAC tone generator。 7.10.2 DAC output paths： DAST/P67 is used to enable DAC output buffer B1. DATEN is used to enable DAC output buffer B2. (1) External：DAC output from its output buffer B1 to DAO/P67 pin。 DAST/P67 = 1 Î power on DAC, enable DAC output buffer B1, output sent to DAO/P67 pin。 (2) Internal：DAC output from its output buffer B2 to CTCSS Sub-audio LPF。 DATEN = 1 Î power on DAC, enable DAC output buffer B2, output sent to CTCSS VTX3。 7.10.3 Using 2.5V ref and DAC ASW3 REFSEL VREF DATEN REFEN DAST/P67 CMPEN VRSEL Product Specification (V3.6) 02.02.2005 (This specification is subject to change without further notice) • 51 EM78568 8-Bit Microcontroller for FRS Fig.17 Voltage reference control logic “2.5V ref.” is the reference voltage used in DAC, Comparator or CTCSS. The voltage reference control logic process these combination use. For this reference used in Comparator, you just only take care of CMPEN and VRSEL bits. For this reference used in others, you need to set ASW3, VREF, DATEN and DAST/P67. The following table shows the least two bits setting to logic “1” (CMPEN=VRSEL=1 or ASW3=DATEN=1 or VREF=DATEN=1 or VREF=DAST/P67=1) will “select 2.5V and enable 2.5V ref”. When REFSEL = 1, the 2.5V ref is select not VDD. (select 2.5V ref) When REFEN = 1, the 2.5V ref is power on. (2.5V ref enable) ASW3 VREF DATEN DAST/P67 CMPEN VRSEL Function x x x x 1 1 select 2.5V ref, enable 2.5V ref, enable Comparator 1 x 1 x x x select 2.5V ref, enable 2.5V ref, enable DAC, 0 1 1 x x x enable buffer B2, buffer B2 output to CTCSS LPF x 1 0 1 x x select 2.5V ref, enable 2.5V ref, enable DAC, enable buffer B1, buffer B1 output to DAO/P67 pin 7.10.4 Select DAO/P67 pin as normal I/O P67 Set DAST/P67 = 0 to select normal I/O P67. 7.10.5 Using DAC general mode DAT/DAD = 0 Î select DAC general mode。 Program DA7 ~ DA0。 Enable DAC, enable DAC output buffer, select DAC reference source。 7.10.6 Using DAC tone generator mode (1) DAT/DAD = 1 Î select DAC tone generator mode。 (2) Program DAT7 ~ DAT0 = 1 to 255. (If DAT7 ~ DAT0 = 0, DAC tone gen. is disabled.)。 (3) Enable DAC, enable DAC output buffer, select DAC reference source。 Ps. When DAC tone output is set to CTCSS Sub-audio LPF(ASW3=DATEN=1 or VREF=DATEN=1), it will be forced to select 2.5V ref by voltage reference control logic. 52 • Product Specification (V3.6) 02.02.2005 (This specification is subject to change without further notice) EM78568 8-Bit Microcontroller for FRS When its output is set to DAO/P67 pin, reference voltage can be selected as VDD or 2.5V. Ref to Page 18,19 for CTCSS tone generation table. 7.11 CTCSS block 7.11.1 Block control and signal flow description Name P65S P66S AMUTE DETO Register bit location IOC6 PAGE1 bit 5 IOC6 PAGE1 bit 6 IOC6 PAGE1 bit 7 R7 PAGE1 bit 6 RXO RXPWR RXPWR RXI Rx AMP ZC VRF DETO BPFPWR MICO MUX MIC AMP AURX VRX2 VRX1 MICI Audio BPF MUX PORT65 AURX/P65 MUX VTX2 MICO MUX VTX1 ASW2 ASW1 P65S VRF TXPWR AMUTE VRX3 CTCSS tone input VTX3 MUX Sub-Audio LPF 0dB VRX4 MUX (from DAC output buffer B2) ASW3 LPFPWR ASW4 Summing AMP -10dB VTX4 VRF TXPWR Name ASW1 ASW2 ASW3 ASW4 LPFPWR BPFPWR RXPWR TXPWR MTX PORT66 MTX/P66 MUX P66S Register bit location IOCE PAGE1 bit 0 IOCE PAGE1 bit 1 IOCE PAGE1 bit 2 IOCE PAGE1 bit 3 IOCE PAGE1 bit 4 IOCE PAGE1 bit 5 IOCE PAGE1 bit 6 IOCE PAGE1 bit 7 CTCSS block on page 36 Fig.14 is the key feature for FRS baseband signal processing. For receiving path, it receives the RF demodulator output signal and extract the audio output signal to AURX pin. Also it decodes CTCSS tone and its decoding data is shown in the DETO. For transmitting path, it combines audio signal from Mic Amp and CTCSS signal from DAC tone generator(as description in VII.9 section) thru MTX output to RF modulator input end. CTCSS block consists of amplifiers, analog switch, filters and zero-crossing detector which descriptions are shown below. RX AMP : (Receiving amplifier) It accepts RF demodulator output signals which combine demodulated audio and CTCSS tone. Its bias voltage is VDD/2. Product Specification (V3.6) 02.02.2005 (This specification is subject to change without further notice) • 53 EM78568 8-Bit Microcontroller for FRS MIC AMP : (Microphone amplifier) It is the audio input amplifier. Its bias voltage is VDD/s. MUX : (Analog multiplexer switch) It is used for analog signal path switching. Audio BPF : (Audio band pass filter) This audio BPF has pass band 300Hz ~ 3.4kHz. It is used to let audio signal pass through and filter out CTCSS tones. It plays an important role in extracting audio signal. Also it cut out unwanted signal while audio signal transmitting. Sub-Audio LPF : (Sub-audio low pass filter) This sub-audio LPF has pass band 253Hz. It is used to let CTCSS tone pass through and filters out audio signal. It plays an important in extracting CTCSS tone. Also it cut out unwanted signal while CTCSS tone transmitting. Summing AMP : (Summing amplifier) It is an analog signal mixer for audio signal and CTCSS tone transmitting. CTCSS tone will be attenuated about 10dB before signal mixing. ZC : (Zero-crossing detector) This detector transforms CTCSS tone signal from analog form to digital form. It will be the CTCSS tone detection. Description for register control bits ASW1 ~ ASW4 for analog input/output signal path switching RXPWR for power control of receiving RX AMP and ZC TXPWR for power control of transmitting MIC AMP and Summing AMP AMUTE for MIC AMP output signal muting P65S for receiving audio output pin AURX or port P65 pin switching P66S for transmitting output pin MTX or port P66 pin switching The following is the above CTCSS block signal flow and it is easy to use these figures to explain how CTCSS works. (‘blue’ highlight means signal flow and switch setting) (1) RX : receiving CTCSS tone 54 • Product Specification (V3.6) 02.02.2005 (This specification is subject to change without further notice) EM78568 8-Bit Microcontroller for FRS RXO RXPWR =1 RXPWR = 1 RXI Rx AMP ZC VRF DETO BPFPWR MICO MUX MIC AMP AURX VRX2 VRX1 MICI Audio BPF MUX PORT65 AURX/P65 MUX VTX2 MICO MUX VTX1 ASW2 ASW1 P65S VRF TXPWR AMUTE VRX3 CTCSS tone input VTX3 MUX (from DAC output buffer B2) Sub-Audio LPF ASW3 = 0 0dB VRX4 MUX LPFPWR = 1 ASW4 = 0 Summing AMP -10dB VTX4 VRF MTX PORT66 TXPWR MTX/P66 MUX P66S Fig.18 (2) RX : receiving audio RXO RXPWR =1 RXPWR RXI Rx AMP ZC VRF DETO BPFPWR = 1 MICO MUX MIC AMP AURX VRX2 VRX1 MICI Audio BPF MUX PORT65 AURX/P65 MUX VTX2 MICO MUX ASW2 = 0 VTX1 ASW1 = 0 P65S = 1 VRF TXPWR AMUTE VRX3 CTCSS tone input VTX3 MUX (from DAC output buffer B2) Sub-Audio LPF ASW3 LPFPWR 0dB VRX4 MUX ASW4 Summing AMP -10dB VTX4 VRF MTX PORT66 TXPWR MTX/P66 MUX P66S Fig.19 (3) TX : transmitting audio RXO RXPWR RXPWR RXI Rx AMP ZC VRF DETO BPFPWR = 1 MICO MUX MIC AMP AURX VRX2 VRX1 MICI Audio BPF MUX PORT65 AURX/P65 MUX VTX2 MICO MUX ASW2 = 1 VTX1 ASW1 = 1 P65S VRF TXPWR = 1 AMUTE = 0 VRX3 CTCSS tone input VTX3 MUX Sub-Audio LPF 0dB VRX4 MUX (from DAC output buffer B2) ASW3 LPFPWR ASW4 Summing AMP -10dB VTX4 VRF TXPWR = 1 MTX PORT66 MTX/P66 MUX P66S = 1 Fig.20 Product Specification (V3.6) 02.02.2005 (This specification is subject to change without further notice) • 55 EM78568 8-Bit Microcontroller for FRS (4) TX : transmitting CTCSS tone RXO RXPWR RXPWR RXI Rx AMP ZC VRF DETO BPFPWR MICO MUX MIC AMP AURX VRX2 VRX1 MICI Audio BPF MUX PORT65 AURX/P65 MUX VTX2 MICO MUX VTX1 ASW2 ASW1 P65S VRF TXPWR AMUTE VRX3 CTCSS tone input VTX3 MUX 0dB VRX4 Sub-Audio LPF MUX (from DAC output buffer B2) ASW3 = 1 Summing AMP -10dB VTX4 VRF MTX PORT66 MTX/P66 MUX ASW4 = 1 LPFPWR = 1 TXPWR = 1 P66S = 1 Fig.21 7.11.2 Special application on Audio/CTCSS tone mixing output Generally speaking, users can use a built-in DAC tone generator (described in VII.9) to generate CTCSS tone accompanied with audio on MTX/P66 pin output without any problem. For some customers, due to modulation index criteria of their FM modulator cannot accept built-in CTCSS tone because this level is too large for them to use. In this case, there are two ways to solve this problem : (1) One way is not to use built-in DAC tone generator but need to program the built-in DAC to generate CTCSS tone by user software algorithm. User software algorithm can normalize the final CTCSS tone level to their requirement without adding any external elements. (2) The other way is still to use a built-in DAC tone generator but needs some external components to attenuate the CTCSS tone on the DAO/P67 pin. Program some control bits to output CTCSS tone on the DAO/P67 pin, refer to VII.9 (3) description. Since DAO/P67 output is a stair-case waveform, we need to put simple RC LPF circuit to smooth the output waveform before going to the CTCSS attenuation circuit. RC LPF also has some attenuation effect. It depends on its cut-off frequency of LPF. You can design it on your own. There are two circuits suggested for your reference. 56 • Product Specification (V3.6) 02.02.2005 (This specification is subject to change without further notice) EM78568 8-Bit Microcontroller for FRS VCC MTX/P66 32 FM modulator DAO/P67 31 (option) (LPF for DA sample clk) (I/O port) MTX/P66 32 FM modulator DAO/P67 31 (bias) (LPF for DA sample clk) (I/O port) Product Specification (V3.6) 02.02.2005 (This specification is subject to change without further notice) • 57 EM78568 8-Bit Microcontroller for FRS 7.12 8-bit R-2R DAC VDD MUX CMPEN 2.5V ref MUX VRSEL To ladder resistors (This circuit is from the Comparator) REFSEL REFEN VRX3 2R (part of DAC Tone Gen.) DAC tone gen DAC input MUX DA7~DA0 8-bit DAC Input Data Buffer B2 R DATEN VTX3 MUX To Sub-Audio LPF ASW3 (This circuit is from CTCSS) 2R DAO/P67 B1 R 2R DAT/DAD 2R DAST/P67 Name DA7 ~ DA0 DAT/DAD Register bit location RA PAGE1 bit 7 ~ 0 IOCA PAGE1 bit 7 Name DAST/P67 DATEN PORT67 Register bit location IOCA PAGE1 bit 3 IOCA PAGE1 bit 5 Fig.22 DAC block Refer to “Voltage reference control logic” to set the DAC reference. In DAC tone generator mode, you can retrieve the CTCSS tone output. In other case, DAC is useful in general tone generation such as key tone, alert tone, music and so on. In DAC general mode, only VREF and DAST/P67 bits are relative to DAC reference voltage. DAC reference voltage comes from VDD or 2.5V ref. Setting VREF bit (IOCE PAGE1 bit 6) = 0/1 to select VDD/2.5V as reference. Set the DAST/P67 bit=1 to power on the DAC and also enable the output buffer B1. After that, the DAC output signal will be sent to DAO/P67 pin. 58 • Product Specification (V3.6) 02.02.2005 (This specification is subject to change without further notice) EM78568 8-Bit Microcontroller for FRS 7.13 4-bit Comparator Name P62S P63S P64S CMP1/P62 Register bit location IOC6 PAGE1 bit 2 IOC6 PAGE1 bit 3 IOC6 PAGE1 bit 4 CMP1 MUX PORT62 P62S CMP2/P63 CMP2 MUX + MUX CMPFLAG PORT63 2 P63S CMP3/P64 CMPS1 CMPS0 CMP3 MUX PORT64 1 0 P64S MUX VDD 2.5V ref REFEN 2.5V MUX VR CMPREF CMPEN VRSEL (This ckt is form DAC) 1/2R 11111 R 11110 R MUX 00000 1/2R 5 CMP_B4 to CMP_B0 Name CMPEN CMPS1 ~ CMPS0 CMP_B4 ~ CMP_B0 VRSEL Register bit location IOC5 PAGE1 bit 7 IOC5 PAGE1 bit 6 ~ 5 IOC5 PAGE1 bit 4 ~ 0 IOCA PAGE1 bit 4 Name CMPREF CMPFLAG Register bit location RA PAGE0 bit 1 RA PAGE0 bit 2 This comparator is not only a single comparator. It consists of 16-R resistor string, 3-channel input and optional external comparison reference source input. The 16-R resistor string acts as a 16-level voltage divider of which top voltage reference can be selected from VDD or 2.5V ref. Use the above register bits to set the whole job. This comparator is used in some applications such as voltage detection, RSSI level, sensor output level and other slow signal level transition detection and so on. This comparator can be called a simple 4-bit low speed ADC but the sampling time is determine by Product Specification (V3.6) 02.02.2005 (This specification is subject to change without further notice) • 59 EM78568 8-Bit Microcontroller for FRS software. For AC frequency detection, it is limited by its output comparator structure. AC frequency below 1kHz is recommended. 7.14 Programming Tone Generators Vref1 N-R Resistor String Tone 1 Analog Multiplexer Buffer Vref2 VT Vref1 Reference Voltage Vref2 Tone 2 Analog Multiplexer Vref2 Buffer TON E Mixer (output inverse) Vref2 fs2 fi T2Mux Control T1Mux Control fs1 Tone 2 N2 Programmable counter T27 ~ T20 Nam T1A ~ e T17 T18~ T27 T10~ T20 Tone 1 N1 Programmable counter fs1 = fi / N1, fs2 = fi / N2 fT1 = fi / N1 / N, tone1 output frequency fT2 = fi / N2 / N, tone2 output frequency T1A ~ T10 Register bit location IOCE PAGE0 bit 2 ~ IOCD PAGE0 0 bit 7 ~ IOCA PAGE0 0 bit 7 ~ 0 Fig.23 Programming Tone Generator Programming tone generators are universal dual tone generators. It includes Tone 1 and Tone 2 generators which can be combined as dual tone output or either one tone output. The clock source fi comes from PLL and is divided to the required ratio. Tone 1 and Tone 2 are sinewave output. The programming tone generators consist of Tone 1/2 programmable counters, analog multiplexer, N-R resistor string, output buffers, mixer amplifier and reference voltage. N-R resistor is a voltage divider which has different output levels. By programmable counters and analog multiplexer, the hardware will automatically generate individual divider output with circular order back and forth. The output frequency is 119957/N1 for Tone 1 and 11.957/N2 for Tone 2, where N1 is 11-bit T1A ~ T10 and N2 is 8-bit T17 ~ T10. 60 • Product Specification (V3.6) 02.02.2005 (This specification is subject to change without further notice) EM78568 8-Bit Microcontroller for FRS 8 Absolute Maximum Ratings RATING SYMBOL VALUE UNIT VDD -0.3 To 6 V Input Voltage VIN -0.5 to VDD +0.5 V Operating Temperature Range Ta -30 to 70 ℃ DC Supply Voltage 9 DC Electrical Characteristic (Ta = 0°C ~ 70°C, AVDD=VDD=5V±5%, VSS=0V) Parameter Symbol Condition Min Typ Max Unit Input leakage current for input pins IIL1 VIN = VDD, VSS ±1 µA Input leakage current for bi-directional pins IIL2 VIN = VDD, VSS ±1 µA Input high voltage VIH Input low voltage VIL 2.5 V 0.8 Input high threshold voltage VIHT /RESET, TCC Input low threshold voltage VILT /RESET, TCC Clock input high voltage VIHX OSCI Clock input low voltage VILX OSCI VOH1 IOH = -5mA 2.4 V VOH2 IOH = -8 mA 2.4 V VOL1 IOH = 5mA 0.4 V VOL2 IOH = 8 mA 0.4 V VLCD VDD=5V, Contrast adjust Output high voltage for PORT 5, 6, 7, 8 Output high voltage for PORT 9, C Output low voltage for PORT 5, 6, 7,8 Output low voltage for PORT 9, C LCD drive reference voltage 2.0 V V 0.8 3.5 V V 1.5 4~5 V V Pull-high current IPH Pull-high active input pin at VSS -10 -15 µA Power down current (SLEEP mode) ISB1 All input and I/O pin at VDD, Output pin floating, WDT disabled 1 5 µA ISB2 CLK=32.768kHz, All analog circuits disabled, All input and I/O pin at VDD, output 35 50 µA ISB3 CLK=32.768kHz, All analog circuits disabled, All input and I/O pin at VDD, output 30 45 µA Low clock current (GREEN mode) Low clock current (IDLE mode) Product Specification (V3.6) 02.02.2005 (This specification is subject to change without further notice) • 61 EM78568 8-Bit Microcontroller for FRS ICC1 /RESET=High, CLK=3.582MHz, All analog circuits disabled, Output pin floating Tone generator reference voltage Vref2 VREG is regulator output 0.5 Tone1 signal strength V1rms Root mean square voltage 130 Tone2 signal strength V2rms Root mean square voltage Operating supply current (Normal mode) 1 155 2 mA 0.7 VREG 180 mV 1.259V1rms mV 2.5Vref for Comparator or DAC Parameter Symbol Condition Min Typ Max Unit Internal 2.5V ref. voltage. 2.5VREF VDD=5V, 25 deg 2.32 2.46 2.58 V VDD=3V, 25 deg 2.22 2.36 2.48 V 5 8 % 8 15 % Reference voltage linearity △2.5VREF/△VDD VDD=5.5V ~ 3.0V, 5 deg VDD=3.0V ~ 2.7V, 25 deg Effective VDD reference for Comparator or DAC Parameter Symbol VDD ref. voltage VDDref Condition VDD=5V ~ 2.7V, - 20 ~ +50 deg Min Typ Max Unit VDD-0.05 VDD-0.02 VDD V (Operating current consumption for analog circuit) (Ta = 0°C ~ 70°C, AVDD=VDD=5V±5%, VSS=0V) Parameter Symbol Condition Min Typ Max Unit 0.35 0.6 mA I_DA 0.65 0.9 mA I_CMP 70 120 µA 0.7 1.0 mA 0.12 0.2 mA 0.3 0.5 mA 0.3 0.5 mA Programming Tone Generators Operating current for Programming Tone Generators I_TONE TONE1 is power on TONE2 is power on Digital to Analog Converter Operating current for DAC Comparator Operating current for Comparator CTCSS Operating current for RX power on I_RX Operating current for TX power on I_TX Operating current for LPF power on I_LPF Operating current for BPF power on I_BPF 62 • RXPWR=1, TXPWR=0 LPFPWR=0, BPFPWR=0 RXPWR=0, TXPWR=1 LPFPWR=0, BPFPWR=0 RXPWR=0, TXPWR=0 LPFPWR=1, BPFPWR=0 RXPWR=0, TXPWR=0 LPFPWR=0, BPFPWR=1 Product Specification (V3.6) 02.02.2005 (This specification is subject to change without further notice) EM78568 8-Bit Microcontroller for FRS * The spec for the above table does not include the MCU current consumption 10 AC Electrical Characteristic CPU instruction timing (Ta = -30°C ~ 70°C, AVDD=VDD=5V, VSS=0V) Parameter Symbol Condition Input CLK duty cycle Dclk Instruction cycle time Tins Device delay hold time Tdrh TCC input period Ttcc Note 1 Watchdog timer period Twdt Ta = 25°C Min Typ Max Unit 45 50 55 % 32.768kHz 60 µs 3.582MHz 550 ns 16 ms (Tins+20)/N ns 16 ms Note 1 N= selected prescaler ratio. OSC and reset timing characteristics (see Fig.25 in page 50 for details) Description Symbol Min Toscs 400 Typ Max Unit 1500 ms 10 us Oscillator timing characteristic OSC start up 32.768kHz 3.579MHz PLL 5 Reset timing characteristic The minimum width of reset low pulse Trst The delay between reset and program start Tdrs 3 uS 18 mS TONE generators for AC Characteristic (AVDD=VDD=5V,Ta=+25°C) CHARACTERISTIC Min Typ Max Unit 130 155 180 mV Tone1/Tone2 signal strength (root mean square voltage) Tone1 signal strength V1rms (ps1) ~= -14dBm (600Ω) Tone2 signal strength V2rms (ps1) ~ = -12dBm (600Ω) 1.259V1rms mV -2 dB Tone twist (Tone1 – Tone2) twist (ps1) : V1rms and V2rms has 2 dB difference. It means 20log (V2rms/V1rms) = 20log1.259 = 2 (dB) Product Specification (V3.6) 02.02.2005 (This specification is subject to change without further notice) • 63 EM78568 8-Bit Microcontroller for FRS CTCSS block (AVDD=VDD=5V, Ta=+25°C) Parameter Min. Typ. Max. Unit RX mode Zero crossing threshold (mVrms) 20 Data Duty Ratio 30 50 mV 70 % TX mode CTCSS tone (form Tone 2) to VTX3, for 600Ω -12 dBm CTCSS tone to MTX, for 600Ω -22 dBm Filter BPF for Audio Pass-Band Frequency 300 3400 Hz 1.0 dB 253 Hz 1.0 dB Driving capacity for AURX pin 30 µA Driving capacity for MTX pin 30 µA Pass-Band Ripple LPF for Sub-Audio Pass-Band Frequency 60 Pass-Band Ripple Output Output loading impedance for AURX pin 42 kΩ 42 kΩ (Ref. Voltage = 2.5V) Output loading impedance for MTX pin (Ref. Voltage = 2.5V) Note: Test under Fig.26 application circuit. Zero crossing threshold means ZC’s transition level in Fig.14 CTCSS block. This level is close but not equal to CTCSS receiving sensitivity. The CTCSS receiving sensitivity partially depends on your software judgment. Also CTCSS receiving sensitivity can be adjusted by changing the external resistors of RX AMP in Fig.26 application circuit. 64 • Product Specification (V3.6) 02.02.2005 (This specification is subject to change without further notice) EM78568 8-Bit Microcontroller for FRS 11 Timing Diagrams ins Fig.24 AC Timing Product Specification (V3.6) 02.02.2005 (This specification is subject to change without further notice) • 65 EM78568 8-Bit Microcontroller for FRS VDD OSC Power on reset Toscs Trst /RESET Tdrs Tdrs Program Active Fig.25 OSC and Reset Timing 66 • Product Specification (V3.6) 02.02.2005 (This specification is subject to change without further notice) EM78568 8-Bit Microcontroller for FRS 12 Application Circuit LCD display VC C FM demodulator 100 k 0.1u 100 k 22 RXO 51 VDD 23 RXI 100 k 100 k 14..1 1 COM(0..3 ) SEG(0..19 ) 10,100..8 2 AURX/P65 33 26 MICI 0.1u from Mic 21 AVD D MTX/P66 32 27 MICO TON E EM78568 28 DAO/P67 31 RSSI low battery detect (other detect) to speaker AMP FM modulator 36 CMP1/P62 (I/O port) 35 CMP2/P63 34 CMP3/P64 AVSS 30 RF module VSS 44 EM78568 Fig.26 Application Circuit Product Specification (V3.6) 02.02.2005 (This specification is subject to change without further notice) • 67 EM78568 8-Bit Microcontroller for FRS APPENDIX A User Application Note (Before using this chip, take a look at the following description note, it includes important messages.) 1. There are some undefined bits in the registers. The values in these bits are unpredictable. These bits are not allowed for use. We use the symbol “-” in the spec to recognize them. 2. You will see some names for the register bits definitions. Some name will appear very frequently in the whole spec. The following describes the meaning for the register’s definitions such as bit type, bit name, bit number and so on. RA PAGE0 7 RAB7 R/W-0 Bit type 6 RAB6 R/W-0 5 BAB5 R-1 read/write (default value=0) 4 RAB4 R/W-1 3 - read/write (default value=1) 2 RAB2 R 1 RAB1 0 RAB0 R/W R-0 read/write (w/o default value) read only (w/o default value) Bit name Bit number Register name and its page (undefined) not allowed to use read only (default value=1) read only (default value=0) 3. While in the ICE programming, the you need to follow the rules : Let “IOCE PAGE0 Bit 4 ~ Bit 7” retain these values to “0”otherwise it will generate unpredictable interrupts. Let “IOCC PAGE1 Bit 0” keep its value unchanged at “0”, otherwise the Comparator and CTCSS function will fail. 4. The function differs between EM78568 and EM78P568. Function 68 • Item EM78568 EM78P568 Data RAM 0.5K x 8 1K x 8 I/O PC0 LCD driver SEG0 ~ SEG19 SEG0 ~ SEG31 Package 100-pin QFP,63-pin die 100-Pin QPF, 78-pin die PC0 ~ PC7 PB0 ~ PB7 Product Specification (V3.6) 02.02.2005 (This specification is subject to change without further notice) EM78568 8-Bit Microcontroller for FRS DC Characteristics Parameter Symbol Internal 2.5V ref.. 2.5VREF Voltage Condition Min Typ Max Unit VDD=5V, 25 deg for EM78568 2.32 2.46 2.58 V VDD=5V, 25 deg for EM78P568 2.14 2.26 2.38 V VDD=3V, 25 deg for EM78568 2.22 2.36 2.48 V VDD=3V, 25 deg for EM78P568 2.04 2.18 2.3 V 5. In the features description, the CPU operating voltage is 2.2 ~ 5.5V, the minimum operating voltage 2.2V is under maximum main clock = 3.5826MHz. Product Specification (V3.6) 02.02.2005 (This specification is subject to change without further notice) • 69