EMC PH86P558

PH86P558
8-Bit Microprocessor
with OTP ROM
Product
Specification
DRAFT DOC.
VERSION 0.98
ELAN MICROELECTRONICS CORP.
Mar.2006
Trademark Acknowledgments:
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ELAN and ELAN logo
are trademarks of ELAN Microelectronics Corporation.
Copyright © 2005 by ELAN Microelectronics Corporation
All Rights Reserved
Printed in Taiwan
The contents of this specification are subject to change without further notice. ELAN Microelectronics assumes
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this specification. Such information and material may change to conform to each confirmed order.
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ELAN MICROELECTRONICS CORPORATION
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Elan (HK) Microelectronics
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Elan Information
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Elan Microelectronics
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Elan Microelectronics
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Contents
Contents
Contents
iii
1
General Description .................................................................................................................5
2
Features ....................................................................................................................................5
3
Pin ASSIGNMENTS ..................................................................................................................7
4
Functional Block Diagram.......................................................................................................8
5.
PH86P558 Pin Description.......................................................................................................9
6.1 Operational Registers............................................................................................................11
6.2
Special Purpose Registers .............................................................................. 33
6.3
TCC/WDT and Prescaler................................................................................. 37
6.4
I/O Ports .......................................................................................................... 39
6.5 SERIAL PERIPHERAL INTERFACE MODE ....................................................... 42
6.6 Timer 4 ................................................................................................................ 55
6.7 RESET and Wake-up .......................................................................................... 56
6.8 Interrupt............................................................................................................... 69
6.9 Analog-To-Digital Converter (ADC) ..................................................................... 70
6.10 Dual Sets of PWM (Pulse Width Modulation).................................................... 77
6.11 Timer.................................................................................................................. 79
6.12 Comparator ....................................................................................................... 81
6.13 Oscillator ........................................................................................................... 83
6.14 Power-on Considerations.................................................................................. 87
6.15 LVD (Low Voltage Detector) .............................................................................. 88
6.16 Code Option ...................................................................................................... 90
Instruction Set ........................................................................................................... 92
7
Absolute Maximum Ratings..................................................................................................95
8
DC Electrical Characteristics................................................................................................96
8.1
AD Converter Characteristic............................................................................. 97
8.2
Comparator (OP) Characteristic ....................................................................... 98
8.3
Device Characteristics...................................................................................... 99
9
AC Electrical Characteristic................................................................................................100
10
Timing Diagrams ..................................................................................................................101
A
Package Types .....................................................................................................................102
B
Quality Assurance and Reliability ......................................................................................102
Product Specification (V0.98) 04.03.2006
• iii
Contents
B.1 Address Trap Detect....................................................................................... 102
Specification Revision History
Doc. Version
0.98
iv •
Revision Description
First product version
Date
2006/04/03
Product Specification (V0.98) 04.03.2006
Contents
1
General Description
PH86P558 is 8-bit microprocessors designed and developed with low-power and
high-speed CMOS technology. It is equipped with an 8K*13-bit Electrical One Time
Programmable Read Only Memory (OTP-ROM). With its OTP-ROM feature, it is able to
offer a convenient way of developing and verifying your programs. Moreover, it provides a
protect bit to guard against code intrusion, as well as 3 Code Option words to accommodate
your requirements. Furthermore you can take advantage of ELAN Writer to easily write your
development code into the PH86P558.
2
Features
Operating voltage range:
0°C ~ 70°C (commercial)
–40°C ~ 85°C (industrial)
OTP
2.1~5.5V
2.3~5.5V
MASK
1.8~5.5V
1.8~5.5V
Operating frequency range (base on 2 clocks):
Main clock
• Crystal mode: DC ~ 20MHz/2clks, 5V; DC ~ 8MHz/2clks, 3V
• RC mode: DC ~ 4MHz/2clks, 5V; DC ~ 4MHz/2clks, 3V
Sub clock
Crystal: 32.768KHz
Low power consumption:
• Less than 2.2 mA at 5V/4MHz
• Typically 15 μA, at 3V/32KHz
• Typically 1 μA, during sleep mode
8K × 13 bits on chip ROM
144 × 8 bits on chip registers (SRAM)
4 programmable Level Voltage Detector (LVD)
Vdd power monitor and support low voltage detector interrupt flag
4 programmable Level Voltage Reset (LVR)
Serial peripheral interface (SPI) available
4 bi-directional I/O ports
8 level stacks for subroutine nesting
8-bit real time clock/counter (TCC) with selective signal sources, trigger edges, and
overflow interrupt
8-bit multi-channel Analog-to-Digital Converter with 12-bit resolution
Product Specification (Draft 0.98) 04.03.2006
(This specification is subject to change without further notice)
•5
Contents
Three Pulse Width Modulation (PWM ) with 10-bit resolution
One pair of comparators (can be set to act as an OP)
Power-down (SLEEP) mode
Seven available interruptions:
•
•
•
•
•
•
•
TCC overflow interrupt
Input-port status changed interrupt (wake-up from sleep mode)
Two External interrupt
ADC completion interrupt
PWM time period match completion interrupt
Comparator high/low interrupt
Serial I/O interrupt
Programmable free running watchdog timer
8 Programmable pull-down I/O pins
16 programmable pull-high I/O pins
Two clocks per instruction cycle
Package types:
• 28 pin DIP/SOP
• 32 pin LQFP/Skinny DIP
Power on voltage detector provided (1.8V± 0.1V)
6•
Product Specification (V0.98) 04.03.2006
Contents
3
Pin ASSIGNMENTS
(1) 28 Pin DIP/SOP
P7 3 /X IN
P7 4 /X O U T
P7 5 //SS
P7 6 /CN TR1
P8 0 /SCK
P8 1 /So u t
P8 2 /Sin
RESET
P8 3 /BO
P5 0 /O SCO
P5 1 /O SCI
V SS
VDD
P8 4 /V re f
1
P7 3
P7 1
28
2
P7 4
P7 0
27
3
P7 5
P5 7
26
4
P7 6
P5 6
25
5
P8 0
P5 5
24
6
P8 1
P5 4
23
7
P8 2
P6 5
22
8
Re s e t
P6 4
21
9
P8 3
P6 3
20
10
P5 0
P6 2
19
11
P5 1
P6 1
18
12
V SS
P6 0
17
13
VDD
P5 3
16
14
P8 4
P5 2
15
PWM2 /P7 1
PWM1 /P7 0
TCC/P5 7
Co /P5 6
Cin -/P5 5
Cin +/P5 4
A in 5 /P6 5
A in 4 /P6 4
A in 3 /P6 3
A in 2 /P6 2
A in 1 /P6 1
A in 0 /P6 0
IN T1 /P5 3
IN T0 /P5 2
Fig. 3-1 28 Pin DIP/SOP
(2) 32 Pin QFP
6
n
i
A
/
6
6
P
5
n
i
A
/
5
6
P
4
n
i
A
/
4
6
P
3
n
i
A
/
3
6
P
2
n
i
A
/
2
6
P
1
n
i
A
/
1
6
P
0
n
i
A
/
0
6
P
1
T
N
I
/
3
5
P
7
1
8
1
9
1
0
2
1
2
2
2
3
2
4
2
0
T
N
I
/
2
5
P
7
n
i
A
/
7
6
P
26
15
27
14
28
13
29
12
30
11
31
10
32
9
F
E
R
V
/
4
8
P
16
+
n
i
C
/
4
5
P
25
D
D
V
n
i
C
/
5
5
P
S
S
V
o
C
/
6
5
P
I
C
S
O
/
1
5
P
C
C
T
/
7
5
P
O
C
S
O
/
0
5
P
1
M
W
P
/
0
7
P
O
B
/
3
8
P
2
M
W
P
/
1
7
P
T
E
S
E
R
/
3
M
W
P
/
2
7
P
t
u
o
S
/
1
8
P
8
k
c
S
/
0
8
P
7
2
R
T
N
C
/
7
7
P
6
1
R
T
N
C
/
6
7
P
5
S
S
/
5
7
P
4
3
T
U
O
X
/
4
7
P
2
1
N
I
X
/
3
7
P
n
i
S
/
2
8
P
Fig. 3-2 32 Pin QFP
Product Specification (Draft 0.98) 04.03.2006
(This specification is subject to change without further notice)
•7
Contents
4
Functional Block Diagram
WDT
Time-Out
Prescaler
STACK 0
WDT Timer
ROM
Oscillator
Timer
Control
STACK 1
PC
STACK 2
STACK 3
Prescaler
TCC
/INT
Instruction
Register
STACK 4
STACK 5
STACK 6
Interrupt
Control
Sleep
&
Wake Up
Control
STACK 7
R1(TCC)
Instruction
Decoder
RAM
ALU
R4
R3
ACC
Data & Control Bus
22INTs
PWMs
Comparators
12 ADC
SPI
IOC5
IOC6
IOC7
IOC8
R5
R6
R7
R8
P P P P P P P P
5 5 5 5 5 5 5 5
0 1 2 3 4 5 6 7
P P P P P P P P
6 6 6 6 6 6 6 6
0 1 2 3 4 5 6 7
P P P P P P P P
7 7 7 7 7 7 7 7
0 1 2 3 4 5 6 7
P P P P P
8 8 8 8 8
0 1 2 3 4
Fig. 4-1 PH86P558 Functional Block Diagram
8•
Product Specification (V0.98) 04.03.2006
Contents
5. PH86P558 Pin Description
Symbol
Pin No.
Type
VDD
14
–
OSCI
12
I
Function
Power supply
XTAL type Crystal input terminal or external clock input pin
RC type:
RC oscillator input pin
XTAL type: Output terminal for crystal oscillator or external clock
input pin
OSCO
11
O
RC type: Clock output with a duration of one instruction cycle time.
The prescaler is determined by the CONT register.
External clock signal input
XIN
1
I
Low crystal 32.768KHz input
XOUT
2
O
Low crystal 32.768KHz output
11~12,
P50 ~ P57
16~17,
I/O
26~29
P60 ~ P67
P70 ~ P77
18~25
30~32,
1~5
I/O
I/O
P80 ~ P84
6~8,10,15
I/O
INT0, INT1
16, 17
I
Ain0~Ain7
18 ~ 25
I
PWM1,
PWM2
30,
PWM3
32
BO
10
O
VREF
15
I
CIN-,
I
CIN+,
27,
26,
CO
28
O
31,
O
I
General-purpose I/O pin
Default value at power-on reset
General-purpose I/O pin
Default value at power-on reset
General-purpose I/O pin
Default value at power-on reset
General-purpose I/O pin
Default value at power-on reset
External interrupt pin triggered by falling edge
Analog to Digital Converter
Defined by AISR (Bank2 R8)<0:7>
Pulse width modulation outputs
Defined by PWMCON (Bank1 R5)<5:7>
Buzzer output driver
External reference voltage for ADC
Defined by ADCON (Bank2 R9)<7>
“–“ –> the input pin of Vin– of the comparator
“+” –> the input pin of Vin+ of the comparator
Pin CO is the output of the comparator
Defined by CMPCON (IOC9) <0:1>
General-purpose Input only
/RESET
9
I
If it remains at logic low, the device will be reset
Wake-up from sleep mode when pin status changes
Voltage on /RESET must not exceed Vdd during normal mode
TCC
29
I
Real time clock/counter with Schmitt trigger input pin. It must be tied
to VDD or VSS if not in use.
Sin
8
I
Sin pin is used to input serial datasignals by software.
Product Specification (Draft 0.98) 04.03.2006
(This specification is subject to change without further notice)
•9
Contents
Sin pin is also used as port P80.
Sout
7
O
Sck
6
I/O
Sout pin is used to input serial datasignals by software.
Sout pin is also used as port P81.
Sck pin is used to input and output synchronous clock signals for
serial data transfer by software.
Sck pin is also used as port P83.
10 •
VSS
13
–
CNTR1/CNT
R2
4,5
I
Ground.
Counter1/counter2 with Schmitt trigger input pin.
Product Specification (V0.98) 04.03.2006
Contents
6.1 Operational Registers
6.1.1 R0 (Indirect Address Register)
R0 is not a physically implemented register. Its major function is to perform as an indirect
address pointer. Any instruction using R0 as a pointer, actually accesses the data pointed
by the RAM Select Register (R4).
6.1.2 R1 (Time Clock /Counter)
Increased by an external signal edge through the TCC pin, or by the instruction cycle
clock.
External signal of TCC trigger pulse width must be greater than one instruction.
The signals to increase the counter are determined by Bit 4 and Bit 5 of the CONT
register.
Writable and readable as any other registers.
6.1.3 R2 (Program Counter) and Stack
Reset Vector
Interrupt Vector
PC (A12 ~ A0)
000H
008H
User Memory
Space
On-chip Program
Memory
Stack Level 1
Stack Level 2
Stack Level 3
Stack Level 8
1FFFH
Fig. 6-1 Program Counter Organization
R2 and hardware stacks are 12-bit wide. The structure is depicted in the table under
Section 6.1.3.1 Data Memory Configuration (next section).
Generates 8K×13 bits on-chip ROM addresses to the relative programming instruction
codes. One program page is 1024 words long.
The contents of R2 are all set to "0"s when a RESET condition occurs.
Product Specification (Draft 0.98) 04.03.2006
(This specification is subject to change without further notice)
• 11
Contents
"JMP" instruction allows direct loading of the lower 10 program counter bits. Thus,
"JMP" allows PC to jump to any location within a page.
"CALL" instruction loads the lower 10 bits of the PC, and then PC+1 is pushed into the
stack. Thus, the subroutine entry address can be located anywhere within a page.
"RET" ("RETL k", "RETI") instruction loads the program counter with the contents of the
top of stack.
"ADD R2, A" allows a relative address to be added to the current PC, and the ninth and
above bits of the PC will increase progressively.
"MOV R2, A" allows loading of an address from the "A" register to the lower 8 bits of the
PC, and the ninth and tenth bits (A8 ~ A9) of the PC will remain unchanged.
Any instruction (except “ADD R2,A”) that is written to R2 (e.g., "MOV R2, A", "BC R2,
6",⋅⋅⋅⋅⋅) will cause the ninth bit and the tenth bit (A8 ~ A9) of the PC to remain unchanged.
In the case of PH86P558, the most three significant bits (A12,A11 and A10) will be
loaded with the content of PS2,PS1 and PS0 in the status register (R3) upon execution
of a "JMP", "CALL", or any other instructions set which write to R2.
All instructions are single instruction cycle (fclk/2 or fclk/4) except for the instructions
that are written to R2. Note that these instructions need one or two instructions cycle as
determined by Code Option Register CYES bit.
12 •
Product Specification (V0.98) 04.03.2006
Contents
6.1.3.1 Data Memory Configuration
REGISTER
BANK0
REGISTER
BANK1
REGISTER
BANK2
REGISTER
BANK3
Control
REGISTER
R5(PullLowControl1)
IOC5(Port5I/Ocontrol)
Address
01
R1(TCCBuffer)
02
R2(PC)
03
R3(STATUS)
04
R4(RSR,bank select)
05
R5(Port5 IO data)
R5(PWMcontrol register
#1)
06
R6(Port6 IO data)
R6(PWMcontrolregister
#2)
R6(Buzzeroutput
ControlRegister)
R6(PullLowControl2)
IOC6(Port6I/Ocontrol)
07
R7(Port7 IO data)
R7(PWMtimer/counter
controlregister)
R7(Systemcontrol
Register)
R7(PullLowControl3)
IOC7(Port7I/Ocontrol)
08
R8(Port8 IO data)
R8(PRD1H:PWM1
period)
R8(TADCinput select
register)
R8(PullLowControl4)
IOC8(Port8I/Ocontrol)
R9(ADC control register)
R9(PullHighControl1)
IOC9(Timer4control
register)
R4(7,6)
(0,1)
(1,0)
09
R9(Timer4control
register)
R9(PRD2H:PWM2
period)
0A
RA (SPI read buffer)
RA(PRD3H:PWM3
period)
RA(ADC offset calibration
RA(Pull HighControl 2)
register)
0B
RB(SPI writebuffer)
RB(PRDL:Periodcycle
ofPWM)
RB(ADDATA ADCdata
bit11~bit4)
RB(PullHigh Control3)
0C
RC(SPI status buffer)
RC(DT1L:Dutycycleof
PWM1)
RC(ADDATA1H ADC
databit11~bit8)
RC(PullHigh Control4)
0D
RD(SPI control buffer )
RD(DT2L:Dutycycleof
PWM2)
RD(ADATA1L ADC
databit7~bit0)
RD(TIMER1H:PWM1
timer)
0E
RE(Wake-upcontrol
register)
RE(DT3L:Dutycycleof
PWM3)
RE(LVDC:LVDControl)
RE(TIMER2H:PWM2
timer)
0F
RF(Interrupt flag)
RF(DTH:Dutycycleof
PWM)
RF(TIMER3H:PWM3
timer)
RF(TMRL:PWMtimer)
10
:
1F
20
:
3F
IOCA(Comparator Control
Register )
IOCE(WDT control
register)
IOCF(Interrupt mask1)
16ByteCommomregister
Bank0
32x8
Bank1
32x8
Bank2
32x8
Bank3
32x8
Commomregister
Product Specification (Draft 0.98) 04.03.2006
(This specification is subject to change without further notice)
• 13
Contents
6.1.4 R3 (Status Register)
7
6
5
4
3
2
1
0
PS2
PS1
PS0
T
P
Z
DC
C
• Bits 7 (PS2) ~ 5 (PS0) Page select bits. PS2~PS0 are used to pre-select a program
memory page. When executing a "JMP", "CALL", or other instructions which causes the
program counter to change (e.g. MOV R2, A), PS2~PS0 are loaded into the 11th,12th and
13th bits of the program counter and select one of the available program memory pages.
Note that RET (RETL, RETI) instruction does not change the PS2~PS0 bits. That is, the
return will always be to the page from where the subroutine was called, regardless of the
PS2~PS0 bits current setting.
PS2
0
0
0
0
1
1
1
1
PS1
0
0
1
1
0
0
1
1
PS0
0
1
0
1
0
1
0
1
Program memory page [Address]
Page 0 [0000-03FF]
Page 1 [0400-07FF]
Page 2 [0800-0BFF]
Page 3 [0C00-0FFF]
Page 4 [1000-13FF]
Page 5 [1400-17FF]
Page 6 [1800-1BFF]
Page 7 [1C00-1FFF]
Bit 4 (T):
Time-out bit. Set to 1 by the "SLEP" and "WDTC" commands or during power
on and reset to 0 by WDT time-out.
Bit 3 (P):
Power-down bit. Set to 1 during power-on or by a "WDTC" command and
reset to 0 by a "SLEP" command.
NOTE
Bit 4 & Bit 3 (T & P) are read only.
Bit 2 (Z):
Zero flag. Set to "1" if the result of an arithmetic or logic operation is zero.
Bit 1 (DC):
Auxiliary carry flag
Bit 0 (C):
Carry flag
6.1.5 R4 (RAM Select Register)
Bit 7 & Bit 6: are used to select Banks 0 ~ 3.
Bit 5 ~ Bit 0: are used to select registers (address: 00 ~ 3F) in the indirect address mode.
See the table under Section 6.1.3.1 Data Memory Configuration for the configuration of the
data memory.
14 •
Product Specification (V0.98) 04.03.2006
Contents
6.1.6 R5 ~ R8 (Port 5 ~ Port 8)
R5 & R6 & R7 are I/O registers.
R8
is I/O registers. The upper 3 bits of R8 are fixed to 0.
6.1.7 R9 (TMR4: Timer4 register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
TMR47
TMR46
TMR45
TMR44
TMR43
TMR42
Bit 1
Bit 0
TMR41 TMR40
• TMR47~TMR40 is bit set of timer4 register and it increases until the value matches PWP
and then, it resets to 0.
6.1.8 RA (SPIRB: SPI Read Buffer)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SRB7
SRB6
SRB5
SRB4
SRB3
SRB2
SRB1
SRB0
SRB7~SRB0 are the 8-bit data when transmission is completed by SPI.
6.1.9 RB (SPIWB: SPI Write Buffer)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SWB7
SWB6
SWB5
SWB4
SWB3
SWB2
SWB1
SWB0
SWB7~SWB0 are the 8-bit data that are waiting for transmission by SPI.
6.1.10 RC (SPIS: SPI Status Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
DORD
TD1
TD0
T4ROS
OD3
OD4
-
RBF
Bit 7 (DORD): Data transmission order.
0:Shift left (MSB first)
1:Shift right (LSB first)
Bit6~Bit5 : Sout Status output Delay times Options
TD1
TD0
Delay Time
0
0
1
1
0
1
0
1
8 CLK
16 CLK
24 CLK
32 CLK
Bit4 (T4ROS): Timer4 Read Out Buffer Select Bit
1: Read Value from Timer4 Counter Register.
0: Read Value from Timer4 Preset Register.
Bit 3 (OD3):Open-Drain Control bit
1 = Open-drain enable for Sout,
0 = Open-drain disable for Sout.
Bit 2 (OD4):Open-Drain Control bit
Product Specification (Draft 0.98) 04.03.2006
(This specification is subject to change without further notice)
• 15
Contents
1 = Open-drain enable for SCK,
0 = Open-drain disable for SCK.
Bit 1 are not used and read as “0”.
Bit 0 (RBF):Read Buffer Full flag
1 = Receiving completed; SPIRB is fully exchanged.
0 = Receiving not completed, and SPIRB has not fully exchanged.
6.1.11 RD (SPIC: SPI Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CES
SPIE
SRO
SSE
SDOC
SBRS2
SBRS1
SBRS0
Bit 7 (CES): Clock Edge Select bit
0 = Data shifts out on rising edge, and shifts in on falling edge. Data is on hold
during low-level.
1 = Data shifts out on falling edge, and shifts in on rising edge. Data is on hold
during high-level.
Bit 6 (SPIE): SPI Enable bit
0= Disable SPI mode
1= Enable SPI mode
Bit 5 (SRO): SPI Read Overflow bit
0 = No overflow
1 = A new data is received while the previous data is still being held in the SPIB
register. In this situation, the data in SPIS register will be destroyed. To
avoid setting this bit, users are required to read the SPIRB register
although only the transmission is implemented.
NOTE
This can only occur in slave mode.
Bit 4 (SSE): SPI Shift Enable bit
0 = Reset as soon as the shifting is complete, and the next byte is ready to shift.
1 = Start to shift, and keep on “1” while the current byte is still being transmitted.
NOTE
This bit will reset to 0 at every one-byte transmission by the hardware
Bit 3 (SDOC): Sout output status control bit:
1: After the Serial data output, the Sout remains low.
0: After the Serial data output, the Sout remains high.
Bit 2~Bit 0 (SBRS): SPI Baud Rate Select bits
16 •
Product Specification (V0.98) 04.03.2006
Contents
Refer to the SPI baud rate table illustration under the section “SPI” on the
subsequent pages.
RE (WUCR: Wake-Up Control Register)
6.1.12
7
6
5
4
3
2
1
0
PH86P558
“0”
“0”
“0”
LVDIF
ADWE
CMPWE
ICWE
PWMWE
ICE558
Simulator
C3
C2
C1
C0
ADWE
CMPWE
ICWE
PWMWE
Bit 7 ~ Bit 4:
Unimplemented, read as ‘0’.
[With PH86P558]:
Bit 4(LVDIF)(only for PH86P558) : Low voltage Detector interrupt flag.
When LVD1, LVD0 = “1,1”, Vdd
LVDIF reset to “0” by software.
When LVD1, LVD0 = “1,0”, Vdd
LVDIF reset to “0” by software.
When LVD1, LVD0 = “0,1”, Vdd
LVDIF reset to “0” by software.
When LVD1, LVD0 = “0,0”, Vdd
LVDIF reset to “0” by software.
> 2.3V, LVDIF is “0”, Vdd<= 2.3V, set LVDIF to “1”.
> 3.3V, LVDIF is “0”, Vdd<= 3.3V, set LVDIF to “1”.
> 4.0V, LVDIF is “0”, Vdd<= 4.0V, set LVDIF to “1”.
> 4.5V, LVDIF is “0”, Vdd<= 4.5V, set LVDIF to “1”.
[With Simulator (C3~C0)]: are IRC calibration bits in IRC oscillator mode. Under IRC
oscillator mode of ICE558 simulator, these are the IRC calibration
bits of IRC oscillator mode.
C3
C2
C1
C0
Frequency (MHz)
0
0
0
0
0
0
0
1
(1-31.5%) x F
0
0
1
0
(1-27%) x F
(1-36%) x F
0
0
1
1
(1-22.5%) x F
0
0
1
1
0
0
0
1
(1-18%) x F
(1-13.5%) x F
0
1
1
0
(1-9%) x F
0
1
1
1
(1-4.5%) x F
1
1
1
1
F (default)
1
1
1
0
(1+4.5%) x F
1
1
1
1
0
0
1
0
(1+9%) x F
(1+135%) x F
1
0
1
1
(1+18%) x F
1
0
1
0
(1+22.5%) x F
1
0
0
1
(1+27%) x F
1
0
0
0
(1+31.5%) x F
1. Frequency values shown are theoretical and taken from an instance of a high
frequency mode. Hence are shown for reference only. Definite values will
depend on the actual process.
2. Similar way of calculation is also applicable to low frequency mode.
Bit 3 (ADWE):
ADC wake-up enable bit
0 = Disable ADC wake-up
1 = Enable ADC wake-up
Product Specification (Draft 0.98) 04.03.2006
(This specification is subject to change without further notice)
• 17
Contents
When the ADC Complete is used to enter interrupt vector or to wake-up
PH86P558 from sleep with AD conversion running, the ADWE bit must be
set to “Enable“.
Bit 2 (CMPWE): Comparator wake-up enable bit
0 = Disable Comparator wake-up
1 = Enable Comparator wake-up
When the Comparator output status change is used to enter interrupt
vector or to wake-up PH86P558 from sleep, the CMPWE bit must be set to
“Enable“.
Bit 1 (ICWE):
Port 6 input change to wake-up status enable bit
0 = Disable Port 6 input change to wake-up status
1 = Enable Port 6 input change wake-up status
When the Port 6 Input Status Change is used to enter interrupt vector or to
wake-up PH86P558 from sleep, the ICWE bit must be set to “Enable“.
Bit 0 (PWMWE): PWM/Timer wake-up enable bit.
0 = Disable PWM/Timer wake up.
1 = Enable PWM/Timer wake up.
When the PWM/Timer output status change is used to enter interrupt
vector or to wake-up PH86P558 from sleep, the PWMWE must be set to
“Enable”, reset by software.
6.1.13
RF (Interrupt Status Register)
7
6
5
4
3
2
1
0
PWM3IF
PWM2IF
PWM1IF
ADIF
EXIF1
EXIF0
ICIF
TCIF
NOTE
■ “1” means interrupt request; “0” means no interrupt occurs.
■ RF can be cleared by instruction but cannot be set.
■ IOCF is the interrupt mask register.
■ Reading RF will result to "logic AND" of RF and IOCF.
Bit 7 (PWM3IF): PWM3 (Pulse Width Modulation) interrupt flag. Set when a selected
duration is reached. Reset by software.
Bit 6 (PWM2IF): PWM2 (Pulse Width Modulation) interrupt flag. Set when a selected
duration is reached. Reset by software.
Bit 5 (PWM1IF): PWM1 (Pulse Width Modulation) interrupt flag. Set when a selected
duration is reached. Reset by software.
18 •
Bit 4 (ADIF):
Interrupt flag for analog to digital conversion. Set when AD conversion is
completed. Reset by software.
Bit 3 (EXIF1):
External interrupt flag. Set by falling edge on /INT1 pin. Reset by
software.
Bit 2 (EXIF0):
External interrupt flag. Set by falling edge on /INT0 pin. Reset by
software.
Product Specification (V0.98) 04.03.2006
Contents
Bit 1 (ICIF):
Port 6 input status change interrupt flag. Set when Port 6 input changes.
Reset by software.
Bit 0 (TCIF):
TCC overflow interrupt flag. Set when TCC overflows. Reset by
software.
6.1.14 R10 ~ R3F
All of these are 8-bit general-purpose registers.
6.1.15
Bank1 R5 ( PWM control register #1)
7
6
5
4
3
2
1
0
PWM3E
PWM2E
PWM1E
“0”
T1EN
T1P2
T1P1
T1P0
Bit 7 (PWM3E): PWM3 enable bit
0 = PWM3 is off (default value), and its related pin carries out the P72
function.
1 = PWM3 is on, and its related pin is automatically set to output.
Bit 6 (PWM2E): PWM2 enable bit
0 = PWM2 is off (default value), and its related pin carries out the P71
function.
1 = PWM2 is on, and its related pin is automatically set to output.
Bit 5 (PWM1E): PWM1 enable bit
0 = PWM1 is off (default value), and its related pin carries out the P70
function;
1 = PWM1 is on, and its related pin is automatically set to output.
Bit 4:
Unimplemented, read as ‘0’
Bit 3 (T1EN):
TMR1 enable bit
0 = TMR1 is off (default value)
1 = TMR1 is on
Bit 2 ~ Bit 0 (T1P2 ~ T1P0): TMR1 clock prescale option bits
6.1.16
7
T1P2
T1P1
T1P0
Prescale
0
0
0
1:2 (default)
0
0
1
1:4
0
0
1
1
0
1
1:8
1:16
1
0
0
1:32
1
0
1
1:64
1
1
0
1:128
1
1
1
1:256
Bank1 R6 ( PWM control register #2)
6
5
Product Specification (Draft 0.98) 04.03.2006
(This specification is subject to change without further notice)
4
3
2
1
0
• 19
Contents
T2EN
T2P2
Bit 7 (T2EN):
T2P1
T2P0
T3EN
T3P2
T3P1
T3P0
TMR2 enable bit
0 = TMR2 is off (default value)
1 = TMR2 is on
Bit 6 ~ Bit 4 (T2P2 ~ T2P0): TMR2 clock prescale option bits
Bit 3 (T3EN):
T2P2
T2P1
T2P0
Prescale
0
0
0
1:2 (default)
0
0
1
1:4
0
0
1
1
0
1
1:8
1:16
1
0
0
1:32
1
0
1
1:64
1
1
0
1:128
1
1
1
1:256
TMR3 enable bit
0 = TMR3 is off (default value)
1 = TMR3 is on
Bit 2 ~ Bit 0 (T3P2 ~ T3P0): TMR3 clock prescale option bits
T3P2
6.1.17
T3P1
T3P0
Prescale
0
0
0
1:2 (default)
0
0
1
1:4
0
1
0
1:8
0
1
1
0
1
0
1:16
1:32
1
0
1
1:64
1
1
0
1:128
1
1
1
1:256
Bank1 R7 ( PWM timer/counter control register)
7
6
5
4
3
2
1
0
“0”
“0”
“0”
“0”
T2TS
T2TE
T1TS
T1TE
Bit 7~4:
Unimplemented, read as ‘0’
Bit 3 (T2TS): Timer2/Counter2 signal source
0 = internal instruction cycle clock. If P77 is used as I/O pin, T2TS must be
0.
1 = transition on the CNTR2 pin
Bit 2 (T2TE): Timer2/Counter2 signal edge
0 = increment if the transition from low to high takes place on the CNTR2
pin
1 = increment if the transition from high to low takes place on the CNTR2
pin.
Bit 1 (T1TS): Timer1/Counter1 signal source
20 •
Product Specification (V0.98) 04.03.2006
Contents
0 = internal instruction cycle clock. If P76 is used as I/O pin, T1TS must be
0.
1 = transition on the CNTR1 pin
Bit 0 (T1TE): Timer1/Counter1 signal edge
0 = increment if the transition from low to high takes place on the CNTR1
pin
1 = increment if the transition from high to low takes place on the CNTR1
pin.
6.1.18 Bank1 R8 (PRD1H: the Most Significant Byte (Bit 9 ~ Bit 2) of
PWM1 Time Period)
The content of bank1 R8 is the time period (time base) of PWM1. The frequency of PWM1 is
the reverse of the period.
6.1.19 Bank1 R9 (PRD2H: the Most Significant Byte (Bit 9 ~ Bit 2) of
PWM2 Time Period)
The content of bank1 R9 is the time period (time base) of PWM2. The frequency of PWM2 is
the reverse of the period.
6.1.20 Bank1 RA (PRD3H: the Most Significant Byte (Bit 9 ~ Bit 2) of
PWM3 Time Period)
The content of bank1 RA is the time period (time base) of PWM3. The frequency of PWM3
is the reverse of the period.
6.1.21 Bank1 RB (PRDL: the Least Significant Bits of PWM Period
Cycle)
7
6
5
4
3
2
1
0
“0”
“0”
PRD3[1]
PRD3[0]
PRD2[1]
PRD2[0]
PRD1[1]
PRD1[0]
Bit 7 & Bit 6:
Unimplemented, read as ‘0’.
Bit 5 & Bit 4 (PRD3[1], PRD3[0]): The Least Significant Bits of PWM3 Period Cycle.
Bit 3 & Bit 2 (PRD2[1], PRD2[0]): The Least Significant Bits of PWM2 Period Cycle.
Bit 1 & Bit 0 (PRD1[1], PRD1[0]):
The Least Significant Bits of PWM1 Period Cycle.
6.1.22 Bank1 RC (DT1H: the Most Significant Byte (Bit 9 ~ Bit 2) of
PWM1 Duty Cycle)
A specified value keeps the output of PWM1 to stay high until the value matches with TMR1.
6.1.23 Bank1 RD (DT2H: the Most Significant Byte (Bit 9 ~ Bit 2) of
PWM2 Duty Cycle)
A specified value keeps the output of PWM2 to stay high until the value matches with TMR2.
Product Specification (Draft 0.98) 04.03.2006
(This specification is subject to change without further notice)
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Contents
6.1.24 Bank1 RE (DT3H: the Most Significant Byte (Bit 9 ~ Bit 2) of
PWM3 Duty Cycle)
A specified value keeps the output of PWM3 to stay high until the value matches with TMR3.
6.1.25 Bank1 RF (DTL: the Least Significant Bits of PWM Duty Cycle)
7
6
5
4
3
2
1
0
“0”
“0”
PWM3[1]
PWM3[0]
PWM2[1]
PWM2[0]
PWM1[1]
PWM1[0]
Unimplemented, read as ‘0’.
Bit 7 & Bit 6:
Bit 5 & Bit 4 (PWM3[1], PWM3[0]): The Least Significant Bits of PWM3 Duty Cycle.
Bit 3 & Bit 2 (PWM2[1], PWM2[0]): The Least Significant Bits of PWM2 Duty Cycle.
Bit 1 & Bit 0 (PWM1[1], PWM1[0]): The Least Significant Bits of PWM1 Duty Cycle.
6.1.26 Bank2 R6 (BOCON: Buzzer output Control Register)
7
6
TEN
TCK1
5
4
TCK0
FSCS
3
2
1
0
“0”
“0”
“0”
“0”
•Bit 4 (FSCS): High or low frequency select in Function operating
0: High
1: Low
•Bit 5~Bit 6 (TCK0~TCK1): Key tone output clock source select.
TCK1
TCK0
Clock source
Normal1/2,Idle1/2
0
0
1
1
0
1
0
1
Key_tone output frequency
FSCS=0
FSCS=1
Slow,
Sleep
Fc/2^13
Fc/2^12
Fc/2^11
Fc/2^10
Fs/2^5
Fs/2^4
Fs/2^3
Fs/2^2
Fs/2^5
Fs/2^4
Fs/2^3
Fs/2^2
•Bit 7 (TEN): Key_tone enable control.
0: Disable
1: Enable
output latch
data output
13
fc/2 ,
fc/212,
11
fc/2 ,
fc/210 ,
D
fs/2 5
fs/2 4
3
fs/2
2
fs/2
Fc=8M
Fs=32.768K
0.976KHz
1.953KHz
3.906KHz
7.812KHz
1.024KHz
2.048KHz
4.096KHz
8.192KHz
output enable
Q
/BO pin
MUX
TCK
2
TEN
TBKTC
Figure36. Buzzer output pin configuration
Key tone output can generate 50% duty pulse for driving piezo-electric buzzer. The P83 must
22 •
Product Specification (V0.98) 04.03.2006
Contents
set to “1” before key tone enable and it can be halted by setting P83 to “0”.
P83
TEN
BO pin
Figure37. TONE output pin Timing chart
Unimplemented, read as ‘0’.
Bit 3 ~ Bit 0:
6.1.27 Bank2 R7 (System Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
T1S
T2S
T3S
“0”
“0”
“0”
IDLE
CPUS
Bit 7: Timer1 Clock source
0 = Timer1 source is used Main Clock.
1 = Timer1 source is used Sub clock.
Bit 6: Timer 2 Clock Source
0 = Timer2 source is used Main Clock.
1 = Timer2 source is used Sub clock.
Bit 5: Timer 3 Clock Source
0 = Timer3 source is used Main Clock.
1 = Timer3 source is used Sub clock.
Bit 4 ~ Bit2: Unimplemented, read as ‘0’
Bit 1: idle mode enable bit. This bit will decide the intended mode of the Sleep instruction.
IDLE = “0” + SLEP Instruction => Sleep mode.
IDLE = “1” + SLEP Instruction => Idle mode.
NOP Instruction must be added after Sleep instruction.
Example: IDLE mode: IDLE bit = “1” + SLEP instruction + NOP instruction
SLEEP mode : IDLE bit = ”0” + SLEP instruction + NOP instruction.
Bit0 (CPUS): CPU oscillator source select, When CPUS =0, the CPU oscillator
select
sub-oscillator and the main oscillator is stopped.
CPUS = “0”: sub-oscillator (Fs), Fs = 32.768K Hz (idle mode). In idle mode,
there is only sub-oscillator act as timer1, 2, 3 sources, and CPU is halted.
CPUS = “1”: main-oscillator (Fm) (Normal mode). In this mode Fm and Fs is
work simultaneously.
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(This specification is subject to change without further notice)
• 23
Contents
Only the normal can entering sleep mode, idle mode can’t entering the sleep mode.
Normal mode
Wake-up
Pin change or
Timer interrupt
Wake-up
Idle mode
IDLE = “1”
IDLE = “0”
+Slep
+Slep
Timer must
select low
crystal source to
work normal
Sleep mode
Fig CPU Operation Mode
In Sleep mode, the internal oscillator is turned off and all system operation is halted. Sleep
mode is released by /Sleep pin (level sensitive or edge sensitive). After warm-up period, the
next instruction will be executed which is after the Sleep mode start instruction. Sleep mode
can also be released by setting the /Reset pin to low and executing a reset operation.
In Idle mode, only the low crystal source existence, the others crystal source were off. Only
the Timer(TCC,Timer1,Timer2,Timer3,PWM1,PWM2,PWM3) can work normally when its
clock source select low crystal(if clock source select High crystal, timer will not work). If timer
set the PWMWE as “1”, when the timer or PWM occurs interrupt will wake up the CPU and
entering normal mode. The TCC overflow will not wake up CPU.
6.1.18
Bank1 R8 (PRD1: PWM1 Time Period)
The content of bank1 R8 is the time period (time base) of PWM1. The frequency of PWM1 is
the reverse of the period.
6.1.19
Bank1 R9 (PRD2: PWM2 Time Period)
The content of bank1 R9 is the time period (time base) of PWM2. The frequency of PWM2 is
the reverse of the period.
6.1.20 Bank1 RA (PRD3: PWM3 Time Period)
The content of bank1 RA is the time period (time base) of PWM3. The frequency of PWM3 is
the reverse of the period.
6.1.21 Bank1 RB (PRD: the Most Significant Bits of PWM Period
Cycle)
7
6
5
4
3
2
1
0
“0”
“0”
PRD3[9]
PRD3[8]
PRD2[9]
PRD2[8]
PRD1[9]
PRD1[8]
Bit 7 & Bit 6:
Unimplemented, read as ‘0’.
Bit 5 & Bit 4 (PRD3[9], PRD3[8]): The Most Significant Bits of PWM3 Period Cycle.
Bit 3 & Bit 2 (PRD2[9], PRD2[8]): The Most Significant Bits of PWM2 Period Cycle.
Bit 1 & Bit 0 (PRD1[9], PRD1[8]): The Most Significant Bits of PWM1 Period Cycle.
24 •
Product Specification (V0.98) 04.03.2006
Contents
6.1.22 Bank1 RC (DT1L: the Least Significant Byte (Bit 7 ~ Bit 0) of
PWM1 Duty Cycle)
A specified value keeps the output of PWM1 to stay high until the value matches with TMR1.
6.1.23 Bank1 RD (DT2L: the Least Significant Byte (Bit 7 ~ Bit 0) of
PWM2 Duty Cycle)
A specified value keeps the output of PWM2 to stay high until the value matches with TMR2.
6.1.24 Bank1 RE (DT3L: the Least Significant Byte (Bit 7 ~ Bit 0) of
PWM3 Duty Cycle)
A specified value keeps the output of PWM3 to stay high until the value matches with TMR3.
6.1.25 Bank1 RF (DTH: the Most Significant Bits of PWM Duty Cycle)
7
6
5
4
3
2
1
0
“0”
“0”
PWM3[9]
PWM3[8]
PWM2[9]
PWM2[8]
PWM1[9]
PWM1[8]
Unimplemented, read as ‘0’.
Bit 7 & Bit 6:
Bit 5 & Bit 4 (PWM3[9], PWM3[8]): The Most Significant Bits of PWM3 Duty Cycle.
Bit 3 & Bit 2 (PWM2[9], PWM2[8]): The Most Significant Bits of PWM2 Duty Cycle.
Bit 1 & Bit 0 (PWM1[9], PWM1[8]): The Most Significant Bits of PWM1 Duty Cycle.
6.1.28 Bank2 R8 (AISR: ADC Input Select Register)
The AISR register defines the pins of Port 6 as analog inputs or as digital I/O, individually.
7
6
5
4
3
2
1
0
ADE7
ADE6
ADE5
ADE4
ADE3
ADE2
ADE1
ADE0
Bit 7 (ADE7 ): AD converter enable bit of P67 pin
0 = Disable AIN7, P67 acts as I/O pin
1 = Enable AIN7, acts as analog input pin
Bit 6 (ADE6 ): AD converter enable bit of P66 pin
0 = Disable AIN6, P66 acts as I/O pin
1 = Enable AIN6, acts as analog input pin
Bit 5 (ADE5 ): AD converter enable bit of P65 pin
0 = Disable AIN5, P65 acts as I/O pin
1 = Enable AIN5, acts as analog input pin
Bit 4 (ADE4 ): AD converter enable bit of P64 pin
0 = Disable AIN4, P64 acts as I/O pin
1 = Enable AIN4 acts as analog input pin
Bit 3 (ADE3 ): AD converter enable bit of P63 pin
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(This specification is subject to change without further notice)
• 25
Contents
0 = Disable AIN3, P63 acts as I/O pin
1 = Enable AIN3, acts as analog input pin
Bit 2 (ADE2 ): AD converter enable bit of P62 pin
0 = Disable AIN2, P62 acts as I/O pin
1 = Enable AIN2, acts as analog input pin
Bit 1 (ADE1 ): AD converter enable bit of P61 pin
0 = Disable AIN1, P61 acts as I/O pin
1 = Enable AIN1, acts as analog input pin
Bit 0 (ADE0 ): AD converter enable bit of P60 pin.
0 = Disable AIN0, P60 acts as I/O pin
1 = Enable AIN0, acts as analog input pin
NOTE
Note the pin priority of the COS1 and COS0 bits of IOCA0 Control register when P60/ADE0
acts as analog input or as digital I/O. The Comparator/OP select bits are as shown in a table
under Section 6.2.6, IOCA0 (CMPCON: Comparator Control Register).
The P60/ADE0 pin priority is as follows:
P60/ADE0 PRIORITY
High
Low
ADE0
P60
6.1.29 Bank2 R9 (ADCON: ADC Control Register)
7
6
5
4
3
2
1
0
VREFS
CKR1
CKR0
ADRUN
ADPD
ADIS2
ADIS1
ADIS0
Bit 7 (VREFS): The input source of the Vref of the ADC
0 = The Vref of the ADC is connected to Vdd (default value), and the
P84/VREF pin carries out the function of P84
1 = The Vref of the ADC is connected to P84/VREF
NOTE
The P84/VREF pin priority is as follows:
P84/ VREF PIN PRIORITY
High
Low
VREF
P84
Bit 6 & Bit 5 (CKR1 & CKR0): The prescaler of oscillator clock rate of ADC
00 = 1: 16 (default value)
01 = 1: 4
10 = 1: 64
26 •
Product Specification (V0.98) 04.03.2006
Contents
11 = 1: WDT ring oscillator frequency
CKR1:CKR0
Operation Mode
Max. Operation Frequency
00
Fosc/16
4 MHz
01
Fosc/4
1 MHz
10
Fosc/64
16MHz
11
Internal RC
-
Bit 4 (ADRUN): ADC starts to RUN.
0 = Reset upon completion of the conversion. This bit cannot be
reset through software
1 = an AD conversion is started. This bit can be set by software
Bit 3 (ADPD):
ADC Power-down mode
0 = Switch off the resistor reference to save power even while the CPU is
operating
1 = ADC is operating
Bit 2 ~ Bit 0 (ADIS2 ~ADIS0): Analog Input Select
000 = AIN0/P60
001 = AIN1/P61
010 = AIN2/P62
011 = AIN3/P63
100 = AIN4/P64
101 = AIN5/P65
110 = AIN6/P66
111 = AIN7/P67
These bits can only be changed when the ADIF bit (see Section 6.1.14)
and the ADRUN bit are both LOW.
6.1.30 Bank2 RA (ADOC: ADC Offset Calibration Register)
7
6
5
4
3
2
1
0
CALI
SIGN
VOF[2]
VOF[1]
VOF[0]
“0”
“0”
“0”
Bit 7 (CALI):
Calibration enable bit for ADC offset
0 = Calibration disable
1 = Calibration enable
Bit 6 (SIGN):
Polarity bit of offset voltage
0 = Negative voltage
1 = Positive voltage
Bit 5 ~ Bit 3 (VOF [2] ~ VOF [0]): Offset voltage bits
VOF[2]
VOF[1]
VOF[0]
PH86P558
0
0
0
0LSB
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Contents
0
0
1
2LSB
0
0
1
1
0
1
4LSB
6LSB
1
0
0
8LSB
1
0
1
10LSB
1
1
0
12LSB
1
1
1
14LSB
Unimplemented, read as ‘0’
Bit 2 ~ Bit 0:
6.1.31 Bank2 RB (ADDATA: Converted Value of ADC)
7
6
5
4
3
2
1
0
AD11
AD10
AD9
AD8
AD7
AD6
AD5
AD4
When the AD conversion is completed, the result is loaded into the ADDATA. The ADRUN
bit is cleared, and the ADIF (see Section 6.1.14) is set.
RB is read only.
6.1.31 Bank2 RC (ADDATA1H: Converted Value of ADC )
7
6
5
4
3
2
1
0
“0”
“0”
“0”
“0”
AD11
AD10
AD9
AD8
When the AD conversion is completed, the result is loaded into the ADDATA1H. The
ADRUN bit is cleared, and the ADIF (see Section 6.1.14) is set.
RC is read only.
6.1.32 Bank2 RD (ADDATA1L: Converted Value of ADC )
7
6
5
4
3
2
1
0
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
When the AD conversion is completed, the result is loaded into the ADDATA1L. The
ADRUN bit is cleared, and the ADIF (see Section 6.1.14) is set.
RD is read only
6.1.33 Bank2 RE (LVDC: LVD Control Register )
7
6
5
4
3
2
1
0
“0”
“0”
“0”
“0”
LVDEN
/LVD
LVD1
LVD0
Bit 7 ~ 4: Not used, set “0” at all time.
Bit 3 (LVDEN): Low Voltage Detect Register:
0 : LVD disable
1: LVD enable
Bit 2 (/LVD): Low Voltage Detector. This is a read only bit. When the Vdd pin voltage is lower
than LVD voltage interrupt level(selected by LVD1 and LVD0), this bit will be cleared.
28 •
Product Specification (V0.98) 04.03.2006
Contents
0: the low voltage is detected.
1: the low voltage is not detected or LVD function is disabled.
Bit 1 ~ 0 (LVD1 ~ LVD0) : Low Voltage Detect level select bits
LVD1
LVD0
LVD voltage interrupt level
1
1
2.3
1
0
3.3
0
1
4.0
0
0
4.5
When LVD1, LVD0 = “1,1”, Vdd
LVDIF reset to “0” by software.
When LVD1, LVD0 = “1,0”, Vdd
LVDIF reset to “0” by software.
When LVD1, LVD0 = “0,1”, Vdd
LVDIF reset to “0” by software.
When LVD1, LVD0 = “0,0”, Vdd
LVDIF reset to “0” by software.
> 2.3V, LVDIF is “0”, Vdd<= 2.3V, set LVDIF to “1”.
> 3.3V, LVDIF is “0”, Vdd<= 3.3V, set LVDIF to “1”.
> 4.0V, LVDIF is “0”, Vdd<= 4.0V, set LVDIF to “1”.
> 4.5V, LVDIF is “0”, Vdd<= 4.5V, set LVDIF to “1”.
6.1.34 Bank2 RF (TMR3H: The Most Significant Bits (Bit9 ~ Bit2) of
PWM3 Timer)
The content of RF is read-only.
6.1.35 Bank3 R5 (Pull-Low Control Register#1)

7
6
5
4
3
2
1
0
/PL57
/PL56
/PL55
/PL54
/PL53
/PL52
/PL51
/PL50
Bank3 R5 register is both readable and writable.
Bit 7 (/PL57): Control bit is used to enable the pull-high of the P57 pin.
0 = Enable pull-low output
1 = Disable pull-low output
Bit 6 (/PL56): Control bit is used to enable the pull-low of the P56 pin.
Bit 5 (/PL55): Control bit is used to enable the pull-low of the P55 pin.
Bit 4 (/PL54): Control bit is used to enable the pull-low of the P54 pin.
Bit 3 (/PL53): Control bit is used to enable the pull-low of the P53 pin.
Bit 2 (/PL52): Control bit is used to enable the pull-low of the P52 pin.
Bit 1 (/PL51): Control bit is used to enable the pull-low of the P51 pin.
Bit 0 (/PL50): Control bit is used to enable the pull-low of the P50 pin.
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Contents
6.1.36 Bank3 R6 (Pull-Low Control Register#2)
7
6
5
4
3
2
1
0
/PL67
/PL66
/PL65
/PL64
/PL63
/PL62
/PL61
/PL60
Bank3 R6 register is both readable and writable.
Bit 7 (/PL67): Control bit is used to enable the pull-high of the P67 pin.
0 = Enable pull-low output
1 = Disable pull-low output
Bit 6 (/PL66): Control bit is used to enable the pull-low of the P66 pin.
Bit 5 (/PL65): Control bit is used to enable the pull-low of the P65 pin.
Bit 4 (/PL64): Control bit is used to enable the pull-low of the P64 pin.
Bit 3 (/PL63): Control bit is used to enable the pull-low of the P63 pin.
Bit 2 (/PL62): Control bit is used to enable the pull-low of the P62 pin.
Bit 1 (/PL61): Control bit is used to enable the pull-low of the P61 pin.
Bit 0 (/PL60): Control bit is used to enable the pull-low of the P60 pin.

6.1.37 Bank3 R7 (Pull-Low Control Register#3)
7
6
5
4
3
2
1
0
/PL77
/PL76
/PL75
/PL74
/PL73
/PL72
/PL71
/PL70
Bank3 R7 register is both readable and writable.
Bit 7 (/PL77): Control bit is used to enable the pull-high of the P77 pin.
0 = Enable pull-low output
1 = Disable pull-low output
Bit 6 (/PL76): Control bit is used to enable the pull-low of the P76 pin.
Bit 5 (/PL75): Control bit is used to enable the pull-low of the P75 pin.
Bit 4 (/PL74): Control bit is used to enable the pull-low of the P74 pin.
Bit 3 (/PL73): Control bit is used to enable the pull-low of the P73 pin.
Bit 2 (/PL72): Control bit is used to enable the pull-low of the P72 pin.
Bit 1 (/PL71): Control bit is used to enable the pull-low of the P71 pin.
Bit 0 (/PL70): Control bit is used to enable the pull-low of the P70 pin.
6.1.38 Bank3 R8 (Pull-low Control Register#4)
7
6
5
4
3
2
1
0
“0”
“0”
“0”
/PL84
/PL83
/PL82
/PL81
/PL80
Bank3 R8 register is both readable and writable.
Bit 7 ~ 5: Not used, set “0” at all time.
30 •
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Bit 4 (/PL84): Control bit is used to enable the pull-high of the P84 pin.
0 = Enable pull-low output
1 = Disable pull-low output
Bit 3 (/PL83): Control bit is used to enable the pull-low of the P83 pin.
Bit 2 (/PL82): Control bit is used to enable the pull-low of the P82 pin.
Bit 1 (/PL81): Control bit is used to enable the pull-low of the P81 pin.
Bit 0 (/PL80): Control bit is used to enable the pull-low of the P80 pin.
6.1.39 Bank3 R9 (Pull-High Control Register#1)

7
6
5
4
3
2
1
0
/PH57
/PH56
/PH55
/PH54
/PH53
/PH52
/PH51
/PH50
Bank3 R9 register is both readable and writable.
Bit 7 (/PH57): Control bit is used to enable the pull-high of the P57 pin.
0 = Enable pull-high output
1 = Disable pull-high output
Bit 6 (/PH56): Control bit is used to enable the pull-high of the P56 pin.
Bit 5 (/PH55): Control bit is used to enable the pull-high of the P55 pin.
Bit 4 (/PH54): Control bit is used to enable the pull-high of the P54 pin.
Bit 3 (/PH53): Control bit is used to enable the pull-high of the P53 pin.
Bit 2 (/PH52): Control bit is used to enable the pull-high of the P52 pin.
Bit 1 (/PH51): Control bit is used to enable the pull-high of the P51 pin.
Bit 0 (/PH50): Control bit is used to enable the pull-high of the P50 pin.
6.1.40 Bank3 RA (Pull-High Control Register#2)
7
6
5
4
3
2
1
0
/PH67
/PH66
/PH65
/PH64
/PH63
/PH62
/PH61
/PH60
Bank3 RA register is both readable and writable.
Bit 7 (/PH67): Control bit is used to enable the pull-high of the P67 pin.
0 = Enable pull-high output
1 = Disable pull-high output
Bit 6 (/PH66): Control bit is used to enable the pull-high of the P66 pin.
Bit 5 (/PH65): Control bit is used to enable the pull-high of the P65 pin.
Bit 4 (/PH64): Control bit is used to enable the pull-high of the P64 pin.
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Bit 3 (/PH63): Control bit is used to enable the pull-high of the P63 pin.
Bit 2 (/PH62): Control bit is used to enable the pull-high of the P62 pin.
Bit 1 (/PH61): Control bit is used to enable the pull-high of the P61 pin.
Bit 0 (/PH60): Control bit is used to enable the pull-high of the P60 pin.

6.1.41 Bank3 RB (Pull-High Control Register#3)
7
6
5
4
3
2
1
0
/PH77
/PH76
/PH75
/PH74
/PH73
/PH72
/PH71
/PH70
Bank3 RB register is both readable and writable.
Bit 7 (/PH77): Control bit is used to enable the pull-high of the P77 pin.
0 = Enable pull-high output
1 = Disable pull-high output
Bit 6 (/PH76): Control bit is used to enable the pull-high of the P76 pin.
Bit 5 (/PH75): Control bit is used to enable the pull-high of the P75 pin.
Bit 4 (/PH74): Control bit is used to enable the pull-high of the P74 pin.
Bit 3 (/PH73): Control bit is used to enable the pull-high of the P73 pin.
Bit 2 (/PH72): Control bit is used to enable the pull-high of the P72 pin.
Bit 1 (/PH71): Control bit is used to enable the pull-high of the P71 pin.
Bit 0 (/PH70): Control bit is used to enable the pull-high of the P70 pin.
6.1.42 Bank3 RC (Pull-High Control Register#4)
7
6
5
4
3
2
1
0
“0”
“0”
“0”
/PH84
/PH83
/PH82
/PH81
/PH80
Bank3 RC register is both readable and writable.
Bit 7 ~ 5: Not used, set “0” at all time.
Bit 4 (/PH84): Control bit is used to enable the pull-high of the P84 pin.
0 = Enable pull-low output
1 = Disable pull-low output
Bit 3 (/PH83): Control bit is used to enable the pull-high of the P83 pin.
Bit 2 (/PH82): Control bit is used to enable the pull-low of the P82 pin.
Bit 1 (/PH81): Control bit is used to enable the pull-low of the P81 pin.
Bit 0 (/PH80): Control bit is used to enable the pull-low of the P80 pin.
32 •
Product Specification (V0.98) 04.03.2006
Contents
6.1.43 Bank3 RD (TMR1H: The Most Significant Bits (Bit9 ~ Bit2) of
PWM1 Timer)
The content of RD is read-only.
6.1.44 Bank3 RE (TMR2H: The Most Significant Bits (Bit9 ~ Bit2) of
PWM2 Timer)
The content of RE is read-only.
6.1.45 Bank3 RF (TMRL: The Least Significant Bits of PWM Timer)
7
6
5
4
3
2
1
0
“0”
“0’
TMR3[1]
TMR3[0]
TMR2[1]
TMR2[0]
TMR1[1]
TMR1[0]
The content of RF is read only,
Bit7 ~ Bit6: Unimplemented, read as “0”.
Bit5 ~ Bit4: (TMR3 [1], TMR3 [0]): The Most Significant Bits of PWM3 Timer.
Bit3 ~ Bit2: (TMR2 [1], TMR2 [0]): The Most Significant Bits of PWM2 Timer.
Bit1 ~ Bit0: (TMR1 [1], TMR1 [0]): The Most Significant Bits of PWM1 Timer.
6.2
Special Purpose Registers
6.2.1 A (Accumulator)
Internal data transfer, or instruction operand holding. It cannot be addressed.
6.2.2 CONT (Control Register)
7
6
5
4
3
2
1
0
INTE
INT
TS
TE
PSTE
PST2
PST1
PST0
Bit 7 (INTE): INT signal edge
0 = interrupt occurs at the rising edge on the INT pin
1 = interrupt occurs at the falling edge on the INT pin
Bit 6 (INT):
Interrupt enables flag
0 = masked by DISI or hardware interrupt
1 = enabled by the ENI/RETI instructions
This bit is readable only.
Bit 5 (TS):
TCC signal source
0 = internal instruction cycle clock. If P56 is used as I/O pin, TS must be
0.
1 = transition on the TCC pin
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TCC signal edge
Bit 4 (TE):
0 = increment if the transition from low to high takes place on the TCC
pin
1 = increment if the transition from high to low takes place on the TCC
pin.
Bit 3 (PSTE): Prescaler enable bit for TCC
0 = prescaler disable bit. TCC rate is 1:1.
1 = prescaler enable bit. TCC rate is set as Bit 2 ~ Bit 0.
Bit 2 ~ Bit 0 (PST2 ~ PST0): TCC prescaler bits
PST2
PST1
PST0
TCC Rate
0
0
0
1:2
0
0
1
1:4
0
0
1
1
0
1
1:8
1:16
1
0
0
1:32
1
0
1
1:64
1
1
0
1:128
1
1
1
1:256
NOTE
Tcc timeout period [1/Fosc x prescaler x 256 (Tcc cnt) x 1 (CLK=2)]
Tcc timeout period [1/Fosc x prescaler x 256 (Tcc cnt) x 2 (CLK=4)]
6.2.3 IOC5 ~ IOC8 (I/O Port Control Register)
"1" puts the relative I/O pin into high impedance, while "0" defines the relative I/O pin as
output.
IOC5, IOC6, IOC7, and IOC8 registers are all readable and writable.
6.2.6 IOC9 (T4CON: Timer4 control register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SPIE
SPIF
TM4IE
TM4IF
“0”
TM4E
TM4P1
TM4P0
Bit 7(SPIIE):
SPI Interrupt enable bit
0: Disable SPI interrupt
1: Enable SPI interrupt
Bit 6 (SPIIF):SPI interrupt flag. Set by data transmission complete, flag cleared by
software.
Bit 5 (TM4IE) TM4IE interrupt enable bit.
0: disable TM4IE interrupt
1: enable TM4IE interrupt
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Bit 3 (TM4IF) Timer4 interrupt flag. Set by the comparator at Timer4 application, flag cleared
by software.
Bit3:Unimplemented, read as ‘0’
Bit2 (TM4E): Timer4 Function Enable bit
0 = Disable timer4 function as default.
1 = Enable timer4 function.
Bit1~Bit0 (TM4P): Timer4 Prescaler bit
TM4P1
TM4P0
Prescaler Rate
0
0
1:1
0
1
1:4
1
0
1:8
1
1
1:16
6.2.6 IOCA (TCMPCON:Comparator Control Register)
7
6
5
4
3
2
1
0
“0”
“0”
“0”
CMPIF
CMPIE
CPOUT
COS1
COS0
Unimplemented, read as ‘0’
Bit 7~ 5:
Bit 4 (CMPIF): Comparator interrupt flag. Set when a change occurs in the output of
Comparator. Reset by software.
Bit 3 (CMPIE):
CMPIF interrupt enable bit
0 = Disable CMPIF interrupt
1 = Enable CMPIF interrupt
When the Comparator output status change is used to enter interrupt
vector or to enter next instruction, the CMPIE bit must be set to “Enable. “
Bit 2 (CPOUT): the result of the comparator output
Bit 1 ~ Bit 0 (COS1 ~ COS0): Comparator/OP Select bits
6.2.7
COS1
COS0
Function Description
0
0
Comparator and OP not used. P56 acts as normal I/O pin
0
1
1
0
1
1
Acts as Comparator and P56 acts as normal I/O pin
Acts as Comparator and P56 acts as Comparator output
pin (CO)
Acts as OP and P56 acts as OP output pin (CO)
IOCE (WDT Control Register)
7
6
5
4
3
2
1
0
WDTE
EIS0
EIS1
PSWE
PSW2
PSW1
PSW0
LVDIE
Bit 7 (WDTE): Control bit is used to enable Watchdog Timer
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0 = Disable WDT
1 = Enable WDT
WDTE is both readable and writable
Bit 6 (EIS0):
Control bit is used to define the function of the P52 (/INT0) pin
0 = P52, normal I/O pin
1 = /INT0, external interrupt pin. In this case, the I/O control bit of P52
(Bit 2 of IOC50) must be set to "1", and tie to a pull-high register (around
75k ohm)
NOTE
■ When EIS0 is "0," the path of /INT0 is masked. When EIS0 is "1," the status of /INT0 pin
can also be read by way of reading Port 5 (R5). Refer to Fig. 6-4 (I/O Port and I/O Control
Register Circuit for P52(/INT0)) under Section 6.4 (I/O Ports).
■ EIS0 is both readable and writable.
Bit 5 (EIS1):
Control bit is used to define the function of the P53 (/INT1) pin
0 = P53, normal I/O pin
1 = /INT1, external interrupt pin. In this case, the I/O control bit of P53 (Bit 3
of IOC50) must be set to "1", and tie to a pull-high register (around 75k ohm)
NOTE
■ When EIS1 is "0," the path of /INT1 is masked. When EIS1 is "1," the status of /INT1 pin
can also be read by way of reading Port 5 (R5). Refer to Fig. 6-4 (I/O Port and I/O Control
Register Circuit for P53(/INT1)) under Section 6.4 (I/O Ports).
■ EIS1 is both readable and writable.
Bit 4 (PSWE): Prescaler enable bit for WDT
0 = prescaler disable bit. WDT rate is 1:1
1 = prescaler enable bit. WDT rate is set as Bit4~Bit2
Bit 3 ~ Bit 1 (PSW2 ~ PSW0): WDT prescaler bits.
PSW2
PSW1
PSW0
WDT Rate
0
0
0
1:2
0
0
1
1:4
0
1
0
1:8
0
1
1
1:16
1
0
0
1:32
1
0
1
1:64
1
1
0
1:128
1
1
1
1:256
Bit 0 (LVDIE) LVDIF interrupt enable bit.
0: disable LVDIF interrupt
1: enable LVDIF interrupt
36 •
Product Specification (V0.98) 04.03.2006
Contents
6.2.8
IOCF (Interrupt Mask Register)
7
6
5
4
3
2
1
0
PWM3IE
PWM2IE
PWM1IE
ADIE
EXIE0
EXIE1
ICIE
TCIE
NOTE
■ IOCF register is both readable and writable
■ Individual interrupt is enabled by setting its associated control bit in the IOCF to "1."
■ Global interrupt is enabled by the ENI instruction and is disabled by the DISI instruction.
Refer to Fig. 6-8 (Interrupt Input Circuit) under Section 6.6 (Interrupt).
Bit 7 (PWM3IE): PWM3IF interrupt enable bit
0 = Disable PWM3 interrupt
1 = Enable PWM3 interrupt
Bit 6 (PWM2IE): PWM2IF interrupt enable bit
0 = Disable PWM2 interrupt
1 = Enable PWM2 interrupt
Bit 5 (PWM1IE): PWM1IF interrupt enable bit
0 = Disable PWM1 interrupt
1 = Enable PWM1 interrupt
Bit 4 (ADIE):
ADIF interrupt enable bit
0 = Disable ADIF interrupt
1 = Enable ADIF interrupt
When the ADC Complete is used to enter interrupt vector or to enter next
instruction, the ADIE bit must be set to “Enable.“
Bit 3 (EXIE0):
EXIF external 0 interrupt enable bit
0 = Disable EXIF interrupt
1 = Enable EXIF interrupt
Bit 2 (EXIE1):
EXIF external 1 interrupt enable bit
0 = Disable EXIF interrupt
1 = Enable EXIF interrupt
Bit 1 (ICIE):
ICIF interrupt enable bit
0 = Disable ICIF interrupt
1 = Enable ICIF interrupt
Bit 0 (TCIE):
If Port6 Input Status Change Interrupt is used to enter interrupt vector or
to enter next instruction, the ICIE bit must be set to “Enable.“
TCIF interrupt enable bit.
0 = Disable TCIF interrupt
1 = Enable TCIF interrupt
6.3
TCC/WDT and Prescaler
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There are two 8-bit counters available as prescalers for the TCC and WDT respectively. The
PST0 ~ PST2 bits of the CONT register are used to determine the ratio of the TCC prescaler,
and the PWR0 ~ PWR2 bits of the IOCE0 register are used to determine the prescaler of
WDT. The prescaler counter is cleared by the instructions each time such instructions are
written into TCC. The WDT and prescaler will be cleared by the “WDTC” and “SLEP”
instructions. Fig. 6-2 (next page) depicts the block diagram of TCC/WDT.
TCC (R1) is an 8-bit timer/counter. The TCC clock source can be internal clock or external
signal input (edge selectable from the TCC pin). If TCC signal source is from internal clock,
TCC will increase by 1 at every instruction cycle (without prescaler). Referring to Fig. 6-2,
CLK=Fosc/2 or CLK=Fosc/4 is dependent to the CODE Option bit <CLKS>. CLK=Fosc/2 if
the CLKS bit is "0," and CLK=Fosc/4 if the CLKS bit is "1." If TCC signal source is from
external clock input, TCC will increase by 1 at every falling edge or rising edge of the TCC
pin. TCC pin input time length (kept in High or Low level) must be greater than 1CLK.
NOTE
The internal TCC will stop running when sleep mode occurs. However, during AD
conversion, when TCC is set to “SLEP” instruction, if the ADWE bit of RE register is enabled,
the TCC will keep on running
The watchdog timer is a free running on-chip RC oscillator. The WDT will keep on running
even when the oscillator driver has been turned off (i.e., in sleep mode). During normal
operation or sleep mode, a WDT time-out (if enabled) will cause the device to reset. The
WDT can be enabled or disabled at any time during normal mode through software
programming. Refer to WDTE bit of IOCE0 register (Section 6.2.10IOCE0 (WDT Control
Register). With no prescaler, the WDT time-out duration is approximately 18ms. 1
CLK (Fosc/2 or Fosc/4)
Data Bus
0
TCC Pin
1
8-Bit Counter (IOCC1)
MUX
8 to 1 MUX
TE (CONT)
Prescaler
TS (CONT)
WDT
8-Bit counter
WDTE
(IOCE0)
8 to 1 MUX
WDT Time out
SYNC
2 cycles
TCC (R1)
TCC overflow
interrupt
PSR2~0
(CONT)
Prescaler
PSW2~0
(IOCE0)
Fig. 6-2 TCC and WDT Block Diagram
1
VDD=5V, Setup time period = 16.5ms ± 30%.
VDD=3V, Setup time period = 18ms ± 30%.
38 •
Product Specification (V0.98) 04.03.2006
Contents
6.4
I/O Ports
The I/O registers (Port 5, Port 6, Port7 and Port8) are bi-directional tri-state I/O ports. The
Pull-high and Pull-down functions can be set internally by IOCB0, IOCC0, and IOCD0
respectively. Port 6 features an input status change interrupt (or wake-up) function. Each
I/O pin can be defined as "input" or "output" pin by the I/O control registers (IOC50 ~ IOC80).
The I/O registers and I/O control registers are both readable and writable. The I/O interface
circuits for Port 5, Port 6, and Port7 are illustrated in Figures 6-3, 6-4, & 6-5 respectively (see
next page). Port 6 with Input Change Interrupt/Wake-up is shown in Fig. 6-6.
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PCRD
Q
PORT
P
R
D
_
CLK
Q
C
L
Q
P
R
_
Q
PCWR
IOD
D
CLK
PDWR
C
L
PDRD
M
U
X
0
1
NOTE: Pull-high and Open-drain are not shown in the figure.
Fig. 6-3 I/O Port and I/O Control Register Circuit for Port 5 and Port7
PCRD
Q
P
R
D
_
CLK
Q
C
L
PCWR
P52, /INT0
P53,/INT1
Q
PORT
P
R
D
_
CLK
Q
C
L
PDWR
IO
D
Bit 6 of IOCE0
D
P
R
CLK
C
L
0
Q
1
_
Q
M
U
X
PDRD
TI 0
INT
NOTE: Pull-high and Open-drain are not shown in the figure.
Fig. 6-4 I/O Port and I/O Control Register Circuit for P52(/INT0) and P53(/INT1)
40 •
Product Specification (V0.98) 04.03.2006
Contents
PCRD
Q
P
R
D
_
CLK
Q
C
L
PCWR
P60 ~ P67
Q
PORT
0
P
R
IOD
D
_
CLK
Q
C
L
PDWR
M
U
X
1
PDRD
TI n
D
P
R
Q
CLK
_
C
L
Q
NOTE: Pull-high (down) and Open-drain are not shown in the figure.
Fig. 6-5 I/O Port and I/O Control Register Circuit for Port 6
IOCE.1
D
P
R
Q
CLK
C
L
Interrupt
_
Q
RE.1
ENI Instruction
T10
T11
D
P
R
Q
CLK
_
C Q
L
Q
P
R
D
CLK
_
Q
C
L
T17
DISI Instruction
Interrupt
(W ake-up from SLEEP)
/SLEP
Next Instruction
(W ake-up from SLEEP)
Fig. 6-6 Port 6 Block Diagram with Input Change Interrupt/Wake-up
Product Specification (Draft 0.98) 04.03.2006
(This specification is subject to change without further notice)
• 41
Contents
6.4.1 Usage of Port 6 Input Change Wake-up/Interrupt Function
(1) Wake-up
(a) Before SLEEP
1. Disable WDT
2. Read I/O Port 6 (MOV R6,R6)
3. Execute "ENI" or "DISI"
4. Enable wake-up bit (Set RE ICWE =1)
5. Execute "SLEP" instruction
(b) After wake-up
→ Next instruction
(2) Wake-up and Interrupt
(a) Before SLEEP
1. Disable WDT
2. Read I/O Port 6 (MOV R6,R6)
3. Execute "ENI" or "DISI"
4. Enable wake-up bit (Set RE ICWE =1)
5. Enable interrupt (Set IOCF ICIE =1)
6. Execute "SLEP" instruction
(b) After wake-up
1. IF "ENI" → Interrupt vector (008H)
2. IF "DISI" → Next instruction
(3) Interrupt
(a) Before Port 6 pin change
1. Read I/O Port 6 (MOV R6,R6)
2. Execute "ENI" or "DISI"
3. Enable interrupt (Set IOCF ICIE =1)
(b) After Port 6 pin changed (interrupt)
1. IF "ENI" → Interrupt vector (008H)
2. IF "DISI" → Next instruction
6.5 SERIAL PERIPHERAL INTERFACE MODE
6.5.1 Overview & Features
Overview:
Figures 6-7, 6-8, and 6-9 shows how the PH86P558 communicates with other devices
through SPI module. If PH86P558 is a master controller, it sends clock through the SCK pin.
A couple of 8-bit data are transmitted and received at the same time. However, if PH86P558
is defined as a slave, its SCK pin could be programmed as an input pin. Data will continue to
be shifted based on both the clock rate and the selected edge. You can also set SPIS bit
7(DORD) to decide the SPI transmission order, SPIC bit3 (SDOC) to control SDO pin after
serial data output status and SPIS bit 6 (TD1), bit 5 (TD0) decides the SDO status output
delay times.
Features:
Operation in either Master mode or Slave mode,
Three-wire or four-wire synchronous communication; that is, full duplex
Programmable baud rates of communication,
Programming clock polarity, (RD bit7)
Interrupt flag available for the read buffer full,
SPI transmission order
After serial data output SDO status select,
SDO status output delay times,
SPI handshake pin,
Up to 8 MHz (maximum) bit frequency,
42 •
Product Specification (V0.98) 04.03.2006
Contents
SDO
SPIW
SPIW Reg
Reg
SPIR Reg
SPIR Reg
SPIW
SPIW Reg
Reg
/SS
SDI
SPIS Reg
SPI Module
Bit 7
SCK
Master Device
Slave Device
Fig. 6-7 SPI Master/Slave Communication
SDI
SDO
SCK
/SS
Vdd
Master
P50
P51
P52
P53
SDO
SDI
SCK
/SS
SDO
SDI
SCK
/SS
SDO
SDI
SCK
/SS
SDO
SDI
SCK
/SS
Slave Device 1
Slave Device 2
Slave Device 3
Slave Device 4
Fig. 6-8 The SPI Configuration of Single-Master and Multi-Slave
Product Specification (Draft 0.98) 04.03.2006
(This specification is subject to change without further notice)
• 43
Contents
SDI
SDO
SCK
/SS
SDI
SDO
SCK
/SS
Master1
or
P50
Slave1 P51
Master2
or
P50
Slave6
P51
P52
P53
Slave 4 for Master1/2
SDO
SDI
SCK
/SS
Slave 3 for Master 1/2
SDO
SDI
SCK
/SS
SDO
SDI
SCK
/SS
SDO
SDI
SCK
/SS
Slave 2 for master 1
P52
P53
Slave 5 for Master 2
Fig. 6-9 The SPI Configuration of Single-Master and Multi-Slave
6.5.2 SPI Function Description
R ead
RBF
R BFI
W rite
S P IR
SE
re g
S P IW
re g
S e t to 1
B u ffe r F u ll D e te c to r
S P IS
P 8 2 /S in
s h ift
rig h t
re g
b it 0
b it 7
S P IC re g
P 8 1 /S o u t
Edge
S e le c t
SBR0 ~SBR2
P 7 5 / /S S
SB R 2~SB R 0
8
SS
Tsco
N o is e
F ilte r
C lo c k S e le c t
2
P re s c a le
4 , 8 , 1r6 , 3 2 , 6 4
Edge
S e le c t
T M R 1 /2
S P IC
b it6
P 8 0 /S C K
Fig. 6-10 SPI Block Diagram
44 •
Product Specification (V0.98) 04.03.2006
Contents
SPI
SPI Read Register
(0X0A)
7~0
SPIWB
/SS
SPI Write Register
(0X0B)
8-1 MUX
SPI Mode Select
Register
2 1 0
SPIC
SDO
SDI
Shift Clock
SPI Shift Buffer
FOSC
1 0
7 6 4 1 0
T1CON
SPIC
SPIS
2
4
INTC
SPIC
7~0
SPIRB
DATA BUS
Fig. 6-11 The Function Block Diagram of SPI Transmission
Below are the functions of each block and explanations on how to carry out the SPI
communication with the signals depicted in Fig.11 and Fig.12:
P82/Sin:Serial Data In.
P81/Sout: Serial Data Out.
P80/SCK: Serial Clock.
P75//SS:/Slave Select (Option). This pin (/SS) may be required during a slave mode.
RBF:Set by Buffer Full Detector, and reset in software.
Buffer Full Detector: Sets to 1 when an 8-bit shifting is completed.
SSE:Loads the data in SPIS register, and begin to shift
SPIS reg.:Shifting byte in and out. The MSB is shifted first. Both the SPIS and the
SPIW registers are loaded at the same time. Once data are written, SPIS starts
transmission / reception. The data received will be moved to the SPIR register as the
shifting of the 8-bit data is completed. The RBF (Read Buffer Full) flag and the
RBFI(Read Buffer Full Interrupt) flag are then set.
SPIR reg.: Read buffer. The buffer will be updated as the 8-bit shifting is completed. The
data must be read before the next reception is completed. The RBF flag is cleared as
the SPIR register reads.
SPIW reg.:Write buffer. The buffer will deny any attempts to write until the 8-bit shifting
is completed.
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(This specification is subject to change without further notice)
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Contents
The SSE bit will be kept in “1“if the communication is still undergoing. This flag must be
cleared as the shifting is completed. Users can determine if the next write attempt is
available.
SBRS2~SBRS0:Programming the clock frequency/rates and sources.
Clock Select:Selecting either the internal or the external clock as the shifting clock.
Edge Select:Selecting the appropriate clock edges by programming the CES bit
6.5.3
SPI Signal & Pin Description
The detailed functions of the four pins, SDI, SDO, SCK, and /SS, which are shown in Fig.
6-9, are as follows:
Sin/P82 (Pin 8):
Serial Data In,
Receive sequentially, the Most Significant Bit (MSB) first, Least Significant Bit (LSB)
last,
Defined as high-impedance, if not selected,
Program the same clock rate and clock edge to latch on both the master and slave
devices,
The byte received will update the transmitted byte,
Both the RBF and RBFIF bits (located in Register 0x0C) will be set as the SPI operation
is completed.
Timing is shown in Fig.6-12 and 6-13.
Sout/P81 (Pin 7):
Serial Data Out,
Transmit sequentially; the Most Significant Bit (MSB) first, Least Significant Bit (LSB)
last,
Program the same clock rate and clock edge to latch on both the master and slave
devices,
The received byte will update the transmitted byte,
The CES (located in Register 0x0D) bit will be reset, as the SPI operation is completed.
Timing is shown in Fig.6-12 and 6-13.
SCK/P80 (Pin 6):
Serial Clock
Generated by a master device
Synchronize the data communication on both the SDI and SDO pins
The CES (located in Register 0x0D) is used to select the edge to communicate.
The SBR0~SBR2 (located in Register 0x0D) is used to determine the baud rate of
communication
46 •
Product Specification (V0.98) 04.03.2006
Contents
The CES, SBR0, SBR1, and SBR2 bits have no effect in the slave mode
Timing is show in Fig.6-12 and 6-13.
/SS/P75 (Pin 4):
Slave Select; negative logic,
Generated by a master device to signify the slave(s) to receive data,
Goes low before the first cycle of SCK appears, and remains low until the last (eighth)
cycle is completed,
Ignores the data on the SDI and SDO pins while /SS is high, because the SDO is no
longer driven.
Timing is shown in Fig.6-12 and 6-13.
6.5.4 Programmed the related registers
As the SPI mode is defined, the related registers of this operation are shown in Table 2 and
Table 3.
Table 1 Related Control Registers of the SPI Mode
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
0x0D
*SPIC/RD
CES
SPIE
SRO
SSE
SOUTC
SBR2
0x0F
T4CR/IOC9
SPIE
SPIF
TM4IE
TM4IF
“0”
TM4E
Bit 1
Bit 0
SBR1
SBR0
TM4P1 TM4P0
SPIC: SPI Control Register.
Bit 7 (CES): Clock Edge Select bit
0 = Data shifts out on rising edge, and shifts in on falling edge. Data is on hold
during the low level.
1 = Data shifts out on falling edge, and shifts in on rising edge. Data is on hold
during the high level.
Bit 6 (SPIE): SPI Enable bit
0 = Disable SPI mode
1 = Enable SPI mode
Bit 5 (SRO): SPI Read Overflow bit
0 = No overflow.
1 = A new data is received while the previous data is still being on hold in the
SPIRB register. Under this condition, the data in SPIS register will be
destroyed. To avoid setting this bit, users should read the SPIRB register even
if the transmission is implemented only.
NOTE
This can only occur under slave mode.
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Contents
Bit 4 (SSE): SPI Shift Enable bit
0 = Reset as soon as the shifting is completed and the next byte is ready to
shift.
1 = Start to shift, and stays on 1 while the current byte continues to transmit.
NOTE
This bit can be reset by hardware only.
Bit3 (SOUTC): Sout output status control bit:
1: After Serial data output Sout keep low.
0: After Serial data output Sout keep High
Bit 2~0 (S BRS): SPI Baud Rate Select Bits
SBRS2 (Bit 2)
SBRS1 (Bit 1)
SBRS0 (Bit 0)
Mode
Baud Rate
0
0
0
Master
Fsco/2
0
0
1
Master
Fsco/4
0
1
0
Master
Fsco/8
0
1
1
Master
Fsco/16
1
0
0
Master
Fsco/32
1
0
1
Slave
/SS enable
1
1
0
Slave
/SS disable
1
1
1
Master
TMR4/2
NOTE
In master mode, /SS is disable.
T4CR: Timer4 control register
Bit 7(SPIIE):
SPI Interrupt enable bit
0: Disable SPI interrupt
1: Enable SPI interrupt
Bit 6 (SPIIF):SPI interrupt flag. Set by data transmission complete, flag cleared by
software.
Bit 5 (TM4IE) TM4IE interrupt enable bit.
0: disable TM4IE interrupt
1: enable TM4IE interrupt
Bit 3 (TM4IF) Timer4 interrupt flag. Set by the comparator at Timer4 application, flag cleared
by software.
Bit3:Unimplemented, read as ‘0’
Bit2 (TM4E): Timer4 Function Enable bit
0 = Disable timer4 function as default.
48 •
Product Specification (V0.98) 04.03.2006
Contents
1 = Enable timer4 function.
Bit1~Bit0 (TM4P): Timer4 Prescaler bit
TM4P1
TM4P0
Prescaler Rate
0
0
1:1
0
1
1:4
1
0
1:8
1
1
1:16
Table 2 Related Status/Data Registers of the SPI Mode
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0X0A
SPIRB/RA
SRB7
SRB6
SRB5
SRB4
SRB3
SRB2
SRB1
SRB0
0x0B
0x0C
SPIWB/RB SWB7
SPIS/RC DORD
SWB6
TD1
SWB5
TD0
SWB4
T4ROS
SWB3
OD3
SWB2
OD4
SWB1
-
SWB0
RBF
SPIRB: SPI Read Buffer. Once the serial data is received completely, it will load to SPIRB
from SPISR. The RBF bit and the RBFIF bit in the SPIS register will be set also.
SPIWB: SPI Write Buffer. As a transmitted data is loaded, the SPIS register stands by and
start to shift the data when sensing SCK edge with SSE set to “1”.
SPIS: SPI Status register
Bit 7 (DORD): Data transmission order
0: Shift left (MSB first)
1: Shift right (LSB first)
Bit6~Bit5: SDO Status Output Delay Times Options
TD1
TD0
Delay Time
0
0
1
1
0
1
0
1
8 CLK
16 CLK
24 CLK
32 CLK
Bit4 (T4ROS): Timer4 Read Out Buffer Select Bit
1: Read Value from Timer4 Counter Register.
0: Read Value from Timer4 Preset Register.
Bit 3 (OD3) Open-Drain Control bit (P81)
0 = Open-drain disable for Sout.
1 = Open-drain enable for Sout,
Bit 2 (OD4): Open Drain-Control bit (P80)
0 = Open-drain disable for SCK.
1 = Open-drain enable for SCK
Bit 0 (RBF): Read Buffer Full flag
Product Specification (Draft 0.98) 04.03.2006
(This specification is subject to change without further notice)
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Contents
0 = Receive is ongoing, SPIB is empty.
1 = Receive is completed, SPIB is full.
6.5.5 SPI Mode Timing
The edge of SCK is selected by programming bit CES. The waveform shown in Fig.13 is
applicable regardless of whether the PH86P558 is under master or slave mode with /SS
disabled. However, The waveform in Fig. 14 can only be implemented in slave mode with
/SS enabled.
Fig. 4 SPI Mode with /SS Disable
Fig. 5 SPI Mode with /SS Enable
6.5.6 Software Application of SPI
Example for SPI:
For Master
ORG 0X0
50 •
Product Specification (V0.98) 04.03.2006
Contents
SETTING:
CLRA
IOW 0X05
;Set Port5 output
IOW 0X06
;Set Port6 output
MOV 0X05,A
MOV A,@0B11001111
;Set prescaler for WDT
CONTW
MOV A,@0B00010001
;Disable wakeup function
IOW 0X0E
MOV A,@0B00000000
;Disable interrupt
IOW 0X0F
MOV A,@0x04
;SDI input and SDO, SCK output
IOW 0x08
MOV A,@0B10000000
;Clear RBF and RBFIF flag
MOV 0x0C,A
MOV A,@0B11100000
;Select clock edge and enable SPI
MOV 0X0D,A
START:
WDTC
BC 0X0C,1
;Clear RBFIF flag
MOV A,@0XFF
MOV 0X05,A
;Show a signal at Port5
MOV 0X0A,A
;Move FF at read buffer
MOV A,@0XAA
;Move AA at write buffer
MOV 0X0B,A
BS 0X0D,4
;Start to shift SPI data
NOP
JBC 0X0D,4
;Polling loop for checking SPI transmission completed
JMP $-2
BC 0X03,2
CALL DELAY
;To catch the data from slaver
MOV A,0X0A
XOR A,@0X5A
;Compare the data from slaver
JBS 0X03,2
JMP START
FLAG:
MOV A,@0X55
;Show the signal when receiving correct data from slaver
MOV 0X05,A
Product Specification (Draft 0.98) 04.03.2006
(This specification is subject to change without further notice)
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Contents
CALL DELAY
JMP START
DELAY:
; (user’s program)
EOP
ORG 0XFFF
JMP SETTING
52 •
Product Specification (V0.98) 04.03.2006
Contents
For Slaver
ORG 0X0
INITI:
JMP INIT
ORG 0X2
INTERRUPT:
;Interrupt address
MOV A,@0X55
MOV 0X06,A
;Show a signal at Port 6 when entering interrupt
MOV A,@0B11100110;Enable SPI, /SS disabled
MOV 0X0D,A
BS 0X0D,4
;Keep SSE at 1 to wait for SCK signal in order to shift data
MOV A,@0X00
;Move 00 to write buffer in order to keep master’s read buffer as 00
MOV 0X0B,A
BS 0X0D,4
;Keep SSE at 1 to wait for SCK signal in order to shift data
NOP
JBC 0X0D,4
;Polling loop for checking SPI transmission completed
JMP $-2
BS 0X0D,4
;Keep SSE at 1 to wait for SCK signal in order to shift data
BC 0X03,2
MOV A,0X0A
MOV 0X06,A
XOR A,@0XAA
;Read master’s data from read buffer
;Check pass signal from read buffer
JBS 0X03,2
JMP $-6
JMP SPI
ORG 0X30
INIT:
CLRA
IOW 0X05
IOW 0X06
MOV 0x05,A
MOV 0X06,A
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Contents
MOV A,@0XFF
IOW 0X08
MOV A,@0B11001111
;Set prescaler for WDT
CONTW
MOV A,@0B00010001
;Disable wakeup function
IOW 0X0E
MOV A,@0B00000010
;Enable external interrupt
IOW 0XF
ENI
MOV A,@0B00110111
IOW 0x09
BC 0X3F,1
;Clear RBFIF flag
NOP
JBS 0X3F,1
;Polling loop for checking interrupt occurrences
JMP $-2
JMP INTERRUPT
SPI:
BS 0X0D,4
;Keep SSE enabled as long as possible
WDTC
MOV A,@0X0F
;Show a signal when entering SPI loop
MOV 0X06,A
JBC 0X08,1
;Choose P81 as a signal button
JMP SPI
MOV A,@0X5A
;Move 5A into write buffer when P81 button is pushed
MOV 0X0B,A
NOP
JBC 0X0D,4
;Polling loop for checking SPI transmission completed
JMP $-2
BS 0XD,4
NOP
NOP
MOV A,@0XF0
;Display at Port6 when P81 button is pushed
MOV 0X06,A
MOV A,@0X00
54 •
;Send a signal to master to prevent infinite loop
Product Specification (V0.98) 04.03.2006
Contents
MOV 0X0B,A
NOP
JBC 0X0D,4
JMP $-2
BS 0X0D,4
BS 0x0C,7
BC 0x0C,1
NOP
JMP SPI
DELAY:
; (user’s program)
EOP
ORG 0XFFF
JMP INITI
6.6 Timer 4
1. Overview
Timer4(TMR4) is an eight-bit clock counter with a programmable prescaler. When TMR4 in
SPI baud rate clock generator mode (SBRS0, SBRS1and SBRS2 a1l set to 1) and then SPI
control register bit4 (SSE) set to 1. Timer4 will enable automatic without set TM4E. TMR4
can be read and written and cleared on any reset conditions.
2. Function description
Fig. 3 shows TIMER4 block diagram. Each signal and block is described as follows:
Set predict value
TM4E
0
TMR4 value
1
Set TM4IF
TMR4
up Counter
In SPI baud
generator mode ?
Yes
Interrupt
and
SPI clock output
Overflow
T4ROS
Prescaler
1:1~1:16
No
Interrupt
OSC / 4
Fig. 6 TIMER4 Block Diagram
Product Specification (Draft 0.98) 04.03.2006
(This specification is subject to change without further notice)
• 55
Contents
• OSC/4:Input clock.
• Prescaler: Option of 1:1, 1:4, 1:8, and 1:16 defined by TM4P1 and TM4P2 (T4CON<1, 0>).
It is cleared when a value is written to TMR4 or T4CON, and during any kind of reset as well.
•TMR4: Timer 4 register. TMR4 increases until it overflowed, and then resets to 0. If it is in
the SPI baud rate generator mode, its output is fed as a shifting clock. TMR4 register;
increases until it overflowed, and then reload the predict value. If write value to Timer4, the
predict value and TMR4 value will be the set the value. However, If TRIOS set to 1 and read
value from TMR4, the value will be TMR4 direct value else TRIOS set to 0 and read value
from TMR4, the value will be TMR4 predict value.
3. Programmed the related registers
The related registers of the defining TMR4 operation are shown in Table 4 and Table 5
Table 3 Related Control Registers of the TMR4
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0x0C
SPIS/RC(bank0)
DORD
TD1
TD0
T4ROS
OD3
OD4
-
RBF
0x0F
T4CR/IOC9
SPIE
SPIF
TM4IE
TM4IF
“0”
TM4E
TM4P1
TM4P0
Table 4 Related Status/Data Registers ofTMR4
Address Name
Bit 7
0X09
TMR4/R9(bank0) TMR47
0x0C
T4CR/IOC9
SPIE
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TMR46
TMR45
TMR44
TMR43
TMR42
TMR41
TMR40
SPIF
TM4IE
TM4IF
“0”
TM4E
TM4P1
TM4P0
• TMR4: Timer4 Register
TMR47~TMR40 is bit set of Timer4 register and it increases until the value matches PWP
and then it reset to 0.
•T4ROS (bit3): Timer4 Read Buffer Select Bit
0: Read Value from Timer4 Preset Register
1: Read Value from Timer4 Counter Register.
• T4CR: Timer4 Control Register
Bit 2 (TM4E): Timer4 enable bit
Bit 1 (TM4P1) and Bit 0 (TM4P): Timer4 prescaler for FSCO
TM4P1
TM4P0
Prescaler Rate
0
0
1:1
0
1
1:4
1
0
1:8
1
1
1:16
6.7 RESET and Wake-up
6.7.1 RESET and Wake-up Operation
A RESET is initiated by one of the following events:
1. Power-on reset
56 •
Product Specification (V0.98) 04.03.2006
Contents
2. /RESET pin input "low"
3. WDT time-out (if enabled).
The device is kept in a RESET condition for a period of approximately 18ms (one oscillator
start-up timer period) after the Power-on reset is detected. And if the /Reset pin goes “low” or
WDT time-out is active, a reset is generated, the reset time is 150μs and 8clocks in high
XTAL mode. In RC mode (IEC or ERC), the reset time is 10μs. In low XTAL mode, the reset
time is 500ms.Once the RESET occurs, the following functions are performed. (The initial
address is 000h)
The oscillator continues running, or will be started (if under sleep mode)
The Program Counter (R2) is set to all "0"
All I/O port pins are configured as input mode (high-impedance state)
The Watchdog Timer and prescaler are cleared
When power is switched on, the upper 3 bits of R3 and upper 2 bits of R4 are cleared
The CONT register bits are set to all "1" except for the Bit 6 (INT flag)
The IOCB0 register bits are set to all "1"
The IOCC0 register bits are set to all "1"
The IOCD0 register bits are set to all "1"
Bit 7 of the IOCE0 register is set to "1", and Bit 6~0 are cleared
Bits 0~6 of RF register and bits 0~6 of IOCF register are cleared
Executing the “SLEP” instruction will assert the sleep (power down) mode. While entering
sleep mode, the Oscillator, TCC, TIMER1, TIMER2, and TIMER3 are stopped. The WDT (if
enabled) is cleared but keeps on running.
The controller can be awakened byCase 1 External reset input on /RESET pin
Case 2 WDT time-out (if enabled)
Case 3 Port 6 input status changes (if ICWE is enabled)
Case 4 Comparator output status changes (if CMPWE is enabled)
Case 5 AD conversion completed (if ADWE enable).
Case 6 PWM/Timer is overflow (if PWMWE enable).
The first two cases (1 & 2) will cause the PH86P558 to reset. The T and P flags of R3 can be
used to determine the source of the reset (wake-up). Cases 3, 4, & 5 are considered the
continuation of program execution and the global interrupt ("ENI" or "DISI" being executed)
decides whether or not the controller branches to the interrupt vector following wake-up. If
ENI is executed before SLEP, the instruction will begin to execute from address 0x8 after
wake-up. If DISI is executed before SLEP, the execution will restart from the instruction next
to SLEP after wake-up. All sleep mode wake up time is 2ms in high XTAL mode. In RC mode
(IRC or ERC), wake up time is 10μs. Under low XTAL mode, wake up time is 500ms.
Only one of the Cases 1 to 5 can be enabled before entering into sleep mode. That is:
Product Specification (Draft 0.98) 04.03.2006
(This specification is subject to change without further notice)
• 57
Contents
Case [a] If WDT is enabled before SLEP, all of the RE bit is disabled. Hence, the
PH86P558 can be awaken only with Case 1 or Case 2. Refer to the section on
Interrupt (Section 6.7) for further details.
Case [b] If Port 6 Input Status Change is used to wake -up PH86P558 and ICWE bit of RE
register is enabled before SLEP, WDT must be disabled. Hence, the PH86P558
can be awaken only with Case 3. Wake-up time is dependent on oscillator mode.
Under RC mode the reset time is 32 clocks (for oscillator stables).
In High XTAL mode, reset time is 2ms and 32clocks(for oscillator stables); and in
low XTAL mode, the reset time is 500ms.
Case [c] If Comparator output status change is used to wake-up PH86P558 and CMPWE
bit of RE register is enabled before SLEP, WDT must be disabled by software.
Hence, the PH86P558 can be awaken only with Case 4.
Wake-up time is dependent on oscillator mode. Under RC mode the reset time is
32 clocks (for oscillator stables). In High XTAL mode, reset time is 2ms and 32
clocks (for oscillator stables); and in low XTAL mode, the reset time is 500ms.
Case [d] If AD conversion completed is used to wake-up PH86P558 and ADWE bit of RE
register is enabled before SLEP, WDT must be disabled by software. Hence, the
PH86P558 can be awaken only with Case 5. The wake-up time is 15 TAD (ADC
clock period).
Wake-up time is dependent on oscillator mode. Under RC mode the reset time is
32 clocks (for oscillator stables). In High XTAL mode, reset time is 2ms and 32
clocks (for oscillator stables); and in low XTAL mode, the reset time is 500ms.
Case [e] If PWM/Timer output status change is used to wake-up PH86P558 and PWMWE
bit of RE register is enabled before Idle mode(except sleep mode),
WDT must be disabled by software. Hence, the PH86P558 can be awakening
only with Case 6.
Wake-up time is dependent on oscillator mode. Under RC mode the reset time is
32 clocks (for oscillator stables). In High XTAL mode, reset time is 2ms and 32
clocks (for oscillator stables); and in low XTAL mode, the reset time is 500ms.
If Port 6 Input Status Change Interrupt is used to wake up the PH86P558 (as in Case b
above), the following instructions must be executed before SLEP:
BC
R3, 7
MOV
A, @001110xxb
IOW
IOCE0
WDTC
MOV
R6, R6
ENI (or DISI)
MOV
A, @00000x1xb
MOV
RE
MOV
A, @00000x1xb
IOW
IOCF
SLEP
; Select Segment 0
; Select WDT prescaler and Disable WDT
;
;
;
;
Clear WDT and prescaler
Read Port 6
Enable (or disable) global interrupt
Enable Port 6 input change wake-up bit
; Enable Port 6 input change interrupt
; Sleep
Similarly, if the Comparator Interrupt is used to wake up the PH86P558 (as in Case [c]
above), the following instructions must be executed before SLEP:
58 •
BC
MOV
R3, 7
A, @xxxxxx10b
IOW
IOCA0
; Select Segment 0
; Select an comparator and P60 act as CO
pin
Product Specification (V0.98) 04.03.2006
Contents
MOV
A, @001110xxb
IOW
IOCE0
WDTC
ENI (or DISI)
MOV
A, @000001xxb
MOV
MOV
RE
A, @000001xxb
IOW
SLEP
IOCF
; Select WDT prescaler and Disable WDT
; Clear WDT and prescaler
; Enable (or disable) global interrupt
; Enable comparator output status change
wake-up bit
; Enable comparator output status change
interrupt
; Sleep
6.7.1.1 Wake-Up and Interrupt Modes Operation Summary
All categories under Wake-up and Interrupt modes are summarized below.
Signal
Sleep Mode
TCC Over Flow
N/A
Normal Mode
DISI + IOCF (TCIE) bit0=1
Next Instruction+ Set RF (TCIF)=1
ENI + IOCF (TCIE) bit0=1
Interrupt Vector (0x08)+ Set RF (TCIF)=1
IOCF (ICIE) bit1=0
RE (ICWE) bit1=0, IOCF (ICIE) bit1=0
Oscillator, TCC and TIMERX are stopped.
Port6 input status change interrupted is invalid
Port6 input status changed wake-up is invalid.
RE (ICWE) bit1=0, IOCF (ICIE) bit1=1
Set RF (ICIF)=1,
Oscillator, TCC and TIMERX are stopped.
Port6 input status changed wake-up is invalid.
RE (ICWE) bit1=1, IOCF (ICIE) bit1=0
Port 6 Input Status Change
Wake-up+ Next Instruction
Oscillator, TCC and TIMERX are stopped.
RE (ICWE) bit1=1, DISI + IOCF (ICIE) bit1=1
DISI + IOCF (ICIE) bit1=1
Wake-up+ Next Instruction+ Set RF (ICIF)=1
Next Instruction+ Set RF (ICIF)=1
Oscillator, TCC and TIMERX are stopped.
RE (ICWE) bit1=1, ENI + IOCF (ICIE) bit1=1
ENI + IOCF (ICIE) bit1=1
Wake-up+ Interrupt Vector (0x08)+ Set RF (ICIF)=1
Interrupt Vector (0x08)+ Set RF (ICIF)=1
Oscillator, TCC and TIMERX are stopped.
DISI + IOCF (EXIE1,0) bit2,3=1
Next Instruction+ Set RF (EXIF)=1
INT Pin
N/A
ENI + IOCF (EXIE1,0) bit2,3=1
Interrupt Vector (0x08)+ Set RF (EXIF)=1
RE (ADWE) bit3=0, IOCF (ADIE) bit4=0
IOCF (ADIE) bit1=0
Clear R9 (ADRUN)=0, ADC is stopped,
AD conversion interrupted is invalid
AD conversion wake-up is invalid.
Oscillator, TCC and TIMERX are stopped.
RE (ADWE) bit3=0, IOCF (ADIE) bit4=1
Set RF (ADIF)=1, R9 (ADRUN)=0,
ADC is stopped,
AD conversion wake-up is invalid.
Oscillator, TCC and TIMERX are stopped.
RE (ADWE) bit3=1, IOCF (ADIE) bit4=0
AD Conversion
Wake-up+ Next Instruction,
Oscillator, TCC and TIMERX keep on running.
Wake-up when ADC completed.
RE (ADWE) bit3=1, DISI + IOCF (ADIE) bit4=1
DISI + IOCF (ADIE) bit4=1
Wake-up+ Next Instruction+ RF (ADIF)=1,
Next Instruction+ RF (ADIF)=1
Oscillator, TCC and TIMERX keep on running.
Wake-up when ADC completed.
RE (ADWE) bit3=1, ENI + IOCF (ADIE) bit4=1
ENI + IOCF (ADIE) bit4=1
Wake-up+ Interrupt Vector (0x08)+ RF (ADIF)=1,
Interrupt Vector (0x08)+ Set RF (ADIF)=1
Oscillator, TCC and TIMERX keep on running.
Wake-up when ADC completed.
DISI + IOCF (PWMXIE)=1
PWMX (PWM1,PWM2)
Next Instruction+ Set RF (PWMXIF)=1
N/A
(When TimerX matches PRDX)
ENI + IOCF (PWMXIE)=1
Interrupt Vector (0x08)+ Set RF (PWMXIF)=1
Product Specification (Draft 0.98) 04.03.2006
(This specification is subject to change without further notice)
• 59
Contents
Signal
Sleep Mode
Comparator
(Comparator Output Status
Change)
Normal Mode
RE (CMPWE) bit2=0, IOCE (CMPIE) bit0=0
Comparator output status changed wake-up is
invalid.
Oscillator, TCC and TIMERX are stopped.
RE (CMPWE) bit2=0, IOCE (CMPIE) bit0=1
Set RF (CMPIF)=1,
Comparator output status changed wake-up is
invalid.
Oscillator, TCC and TIMERX are stopped.
RE (CMPWE) bit2=1, IOCE (CMPIE) bit0=0
Wake-up+ Next Instruction,
Oscillator, TCC and TIMERX are stopped.
RE (CMPWE) bit2=1, DISI + IOCE (CMPIE) bit0=1
Wake-up+ Next Instruction+ Set RF (CMPIF)=1,
Oscillator, TCC and TIMERX are stopped.
IOCF (CMPIE) bit7=0
Comparator output status change interrupted
is invalid.
DISI + IOCE (CMPIE) bit0=1
Next Instruction+ Set RF (CMPIF)=1
RE (CMPWE) bit2=1, ENI + IOCE (CMPIE) bit0=1 ENI + IOCE (CMPIE) bit0=1
Wake-up+ Interrupt Vector (0x08)+ Set RF
Interrupt Vector (0x08)+ Set RF (CMPIF)=1
(CMPIF)=1,
Oscillator, TCC and TIMERX are stopped.
WDT Time Out
IOCE (WDTE) Bit7=1
Wake-up+ Reset (address 0x00)
Reset (address 0x00)
6.7.1.2 Register Initial Values after Reset
The following summarizes the initialized values for registers.
Address
N/A
N/A
N/A
N/A
60 •
Name
IOC5
IOC6
IOC7
Reset Type
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit Name
C57
C56
C55
C54
C53
C52
C51
C50
Power-on
1
1
1
1
1
1
1
1
/RESET & WDT
1
1
1
1
1
1
1
1
Wake-up from
Pin change
P
P
P
P
P
P
P
P
Bit Name
C67
C66
C65
C64
C63
C62
C61
C60
Power-on
1
1
1
1
1
1
1
1
/RESET & WDT
1
1
1
1
1
1
1
1
Wake-up from
Pin change
P
P
P
P
P
P
P
P
Bit Name
C77
C76
C75
C74
C73
C72
C71
C70
Power-on
1
1
1
1
1
1
1
1
/RESET & WDT
1
1
1
1
1
1
1
1
Wake-up from
Pin change
P
P
P
P
P
P
P
P
Bit Name
-
-
-
C84
C83
C82
C81
C80
0
0
0
1
1
1
1
1
0
0
0
1
1
1
1
1
P
P
P
P
P
P
P
P
Power-on
IOC8
(PWMCON) /RESET &WDT
Wake-up from
Pin change
Product Specification (V0.98) 04.03.2006
Contents
Address
N/A
N/A
N/A
N/A
N/A
N/A
Name
IOC9
(T4CR)
Reset Type
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit Name
SPIE
SPIF
TM4IF
TM4IE
-
TM4E
TM4P1
TM4P0
Power-on
0
0
0
0
0
0
0
0
/RESET & WDT
0
0
0
0
0
0
0
0
Wake-up from Pin
change
P
P
P
P
P
P
P
P
Bit Name
-
-
-
CMPIF
CMPIE
CPOUT
COS1
COS0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
P
P
P
P
P
P
P
P
Bit Name
/PWP7
/PWP6
/PWP5
/PWP4
/PWP3
/PWP2
/PWP1
/PWP0
Power-on
1
1
1
1
1
1
1
1
/RESET & WDT
1
1
1
1
1
1
1
1
Wake-up from Pin
change
P
P
P
P
P
P
P
P
Bit Name
-
-
-
-
-
-
-
-
Power-on
1
1
1
1
1
1
1
1
/RESET & WDT
1
1
1
1
1
1
1
1
Wake-up from Pin
change
P
P
P
P
P
P
P
P
Bit Name
-
-
-
-
-
-
-
-
Power-on
1
1
1
1
1
1
1
1
/RESET & WDT
1
1
1
1
1
1
1
1
Wake-up from Pin
change
P
P
P
P
P
P
P
P
Bit Name
WDTE
EIS0
EIS1
PSWE
PSW2
PSW1
PSW0
LVDIE
Power-on
0
0
0
0
0
0
0
0
/RESET & WDT
0
0
0
0
0
0
0
0
Wake-up from Pin
change
P
P
P
P
P
P
P
P
ADIE
EXIE0
EXIE1
ICIE
TCIE
Power-on
IOCA
(CMPCON) /RESET & WDT
Wake-up from Pin
change
IOCB
(PWP)
IOCC
IOCD
IOCE
Bit Name
N/A
N/A
IOCF
CONT
PMW3IE PMW2IE PWM1IE
Power-on
0
0
0
0
0
0
0
0
/RESET & WDT
0
0
0
0
0
0
0
0
Wake-up from Pin
change
P
P
P
P
P
P
P
P
Bit Name
INTE
INT
TS
TE
PSTE
PST2
PST1
PST0
Power-on
0
0
0
0
0
0
0
0
/RESET & WDT
0
0
0
0
0
0
0
0
Wake-up from Pin
change
P
P
P
P
P
P
P
P
Product Specification (Draft 0.98) 04.03.2006
(This specification is subject to change without further notice)
• 61
Contents
Address
0x00
0x01
0x02
Name
R0(IAR)
R1(TCC)
R2(PC)
Reset Type
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit Name
-
-
-
-
-
-
-
-
Power-on
U
U
U
U
U
U
U
U
/RESET & WDT
P
P
P
P
P
P
P
P
Wake-up from Pin
change
P
P
P
P
P
P
P
P
Bit Name
-
-
-
-
-
-
-
-
Power-on
0
0
0
0
0
0
0
0
/RESET & WDT
0
0
0
0
0
0
0
0
Wake-up from Pin
change
P
P
P
P
P
P
P
P
Bit Name
-
-
-
-
-
-
-
-
Power-on
0
0
0
0
0
0
0
0
/RESET & WDT
0
0
0
0
0
0
0
0
Wake-up from
Pin Change
0x03
0x04
0x05
0x06
0x7
R3(SR)
R4(RSR)
R5
P6
P7
Address
Name
0x8
P8
62 •
Jump to address 0x08 or continue to execute next instruction
Bit Name
PS2
PS1
PS0
T
P
Z
DC
C
Power-on
0
0
0
1
1
U
U
U
/RESET & WDT
0
0
0
t
t
P
P
P
Wake-up from Pin
change
P
P
P
t
t
P
P
P
Bit Name
BS7
BS6
-
-
-
-
-
-
Power-on
0
0
U
U
U
U
U
U
/RESET & WDT
0
0
P
P
P
P
P
P
Wake-up from Pin
change
P
P
P
P
P
P
P
P
Bit Name
P57
P56
P55
P54
P53
P52
P51
P50
Power-on
1
1
1
1
1
1
1
1
/RESET & WDT
1
1
1
1
1
1
1
1
Wake-up from Pin
change
P
P
P
P
P
P
P
P
Bit Name
P67
P66
P65
P64
P63
P62
P61
P60
Power-on
1
1
1
1
1
1
1
1
/RESET & WDT
1
1
1
1
1
1
1
1
Wake-up from Pin
change
P
P
P
P
P
P
P
P
Bit Name
P74
P73
P72
P74
P73
P72
P71
P70
Power-on
1
1
1
1
1
1
1
1
/RESET & WDT
1
1
1
1
1
1
1
1
Wake-up from Pin
change
P
P
P
P
P
P
P
P
Reset Type
Bit Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
“0”
“0”
“0”
P84
P83
P82
P81
P80
Product Specification (V0.98) 04.03.2006
Contents
Address
0x9
0xA
0xB
0xB
0xD
0xE
Name
R9
(T4R)
RA
(SPIR)
RB
(SPIW)
RC
(SPISB)
RD
(SPICB)
RE
(WUCR)
Reset Type
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Power-on
0
0
0
1
1
1
1
1
/RESET & WDT
0
0
0
1
1
1
1
1
Wake-up from Pin
change
P
P
P
P
P
P
P
P
Bit Name
TMR47
TMR46
TMR45
TMR44
TMR43
TMR42
Power-on
0
0
0
0
0
0
0
0
/RESET and WDT
0
0
0
0
0
0
0
0
Wake-up from Pin
change
P
P
P
P
P
P
P
P
Bit Name
SRB7
SRB6
SRB5
SRB4
SRB3
SRB2
SRB1
SRB0
Power-on
0
0
0
0
0
0
0
0
/RESET and WDT
0
0
0
0
0
0
0
0
Wake-up from Pin
change
P
P
P
P
P
P
P
P
Bit Name
SWB7
SWB6
SWB5
SWB4
SWB3
SWB2
SWB1
SWB0
Power-on
0
0
0
0
0
0
0
0
/RESET and WDT
0
0
0
0
0
0
0
0
Wake-up from Pin
change
P
P
P
P
P
P
P
P
Bit Name
DORD
TD1
TD0
T4ROS
OD3
OD4
“0”
RBF
Power-on
0
0
0
0
0
0
0
0
/RESET and WDT
0
0
0
0
0
0
0
0
Wake-up from Pin
change
P
P
P
P
P
P
P
P
Bit Name
CES
SPIE
SDO
SSE
SDOC
SBRS2
SBRS1
SBRS0
Power-on
0
0
0
0
0
0
0
0
/RESET and WDT
0
0
0
0
0
0
0
0
Wake-up from Pin
change
P
P
P
P
P
P
P
P
Bit Name
-
-
-
LVDIF
ADWE
CMPWE
ICWE
CMPIF
Power-on
0
0
0
0
0
0
0
0
/RESET and WDT
0
0
0
0
0
0
0
0
Wake-up from Pin
change
P
P
P
P
P
P
P
P
ADIF
EXIF0
EXIF1
ICIF
TCIF
Bit Name
0xF
RF
(ISR)
Power-on
0
0
0
0
0
0
0
0
/RESET and WDT
0
0
0
0
0
0
0
0
Wake-up from Pin
change
P
P
P
P
P
P
P
P
“0”
T1EN
T1P2
T1P1
T1P0
Bit Name
0X5
R5(Bank1)
PWM3IF PWM2IF PWM1IF
TMR41 TMR40
PWM3E PWM2E PWM1E
Power-on
0
0
0
0
0
0
0
0
/RESET & WDT
0
0
0
0
0
0
0
0
Wake-up from Pin
change
P
P
P
P
P
P
P
P
Product Specification (Draft 0.98) 04.03.2006
(This specification is subject to change without further notice)
• 63
Contents
Address
0X6
0X7
Name
R6(Bank1)
R7(Bank1)
Reset Type
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit Name
T2EN
T2P2
T2P1
T2P0
T3EN
T3P2
T3P1
T3P0
Power-on
0
0
0
0
0
0
0
0
/RESET & WDT
0
0
0
0
0
0
0
0
Wake-up from Pin
change
P
P
P
P
P
P
P
P
Bit Name
“0”
“0”
“0”
“0”
T2TS
T2TE
T1TS
T1TE
Power-on
0
0
0
0
0
0
0
0
/RESET & WDT
0
0
0
0
0
0
0
0
Wake-up from Pin
change
P
P
P
P
P
P
P
P
Bit Name
0X8
R8(Bank1)
Power-on
0
0
0
0
0
0
0
0
/RESET & WDT
0
0
0
0
0
0
0
0
Wake-up from Pin
change
P
P
P
P
P
P
P
P
Bit Name
0X9
R9(Bank1)
0XB
RA(Bank1)
RB(Bank1)
Power-on
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Wake-up from Pin
change
P
P
P
P
P
P
P
P
0
0
0
0
0
0
0
0
/RESET & WDT
0
0
0
0
0
0
0
0
Wake-up from Pin
change
P
P
P
P
P
P
P
P
Bit Name
“0”
“0”
Power-on
0
0
0
0
0
0
0
0
/RESET & WDT
0
0
0
0
0
0
0
0
Wake-up from Pin
change
P
P
P
P
P
P
P
P
DT1[9]
DT1[8]
DT1[7]
DT1[6]
DT1[5]
DT1[4]
DT1[3]
DT1[2]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
P
P
P
P
P
P
P
P
DT2[9]
DT2[8]
DT2[7]
DT2[6]
DT2[5]
DT2[4]
DT2[3]
DT2[2]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
P
P
P
P
P
0
P
P
Power-on
RC(Bank1) /RESET & WDT
Wake-up from Pin
change
Bit Name
0XD
Power-on
RD(Bank1) /RESET & WDT
Wake-up from Pin
change
64 •
PRD3[9] PRD3[8] PRD3[7] PRD3[6] PRD3[5] PRD3[4] PRD3[3] PRD3[2]
Power-on
Bit Name
0XC
PRD2[9] PRD2[8] PRD2[7] PRD2[6] PRD2[5] PRD2[4] PRD2[3] PRD2[2]
/RESET & WDT
Bit Name
0XA
PRD1[9] PRD1[8] PRD1[7] PRD1[6] PRD1[5] PRD1[4] PRD1[3] PRD1[2]
PRD3[1] PRD3[0] PRD2[1] PRD2[0] PRD1[1] PRD1[0]
Product Specification (V0.98) 04.03.2006
Contents
Address
Name
Reset Type
Bit Name
0xE
0xF
Bit 0
DT3[9]
DT3[8]
DT3[7]
DT3[6]
DT3[5]
DT3[4]
DT3[3]
DT3[2]
0
0
0
0
0
0
0
0
0
0
0
0
P
P
P
P
P
0
P
P
Bit Name
-
-
DT3[9]
DT3[8]
DT2[9]
DT2[8]
DT1[9]
DT1[8]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
P
P
P
P
P
P
P
P
TEN
TCK1
TCK0
FSCS
“0”
“0”
“0”
“0”
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
P
P
P
P
P
P
P
P
T1S
T2S
T3S
“0”
“0”
“0”
“0”
CPUS
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
P
P
P
P
P
P
P
P
ADE7
ADE6
ADE5
ADE4
ADE3
ADE2
ADE1
ADE0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
P
P
P
P
P
P
P
P
VREFS
CKR1
CKR0
ADIS2
ADIS1
ADIS0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
P
P
P
P
P
P
P
P
CALI
SIGN
-
-
-
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
P
P
P
P
P
P
P
P
AD11
AD10
AD9
AD8
AD7
AD6
AD5
AD4
RB
Power-on
(ADDDATA, /RESET and WDT
Bank2)
Wake-up from
Pin change
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
P
P
P
P
P
P
P
P
Bit Name
RC
(ADDATA1H Power-on
Bank2)
/RESET and WDT
-
-
-
-
AD11
AD10
AD9
AD8
0
0
0
0
U
U
U
U
0
0
0
0
U
U
U
U
Power-on
RF(Bank1) /RESET & WDT
Power-on
R6(BOCR,
/RESET & WDT
Bank2)
Power-on
R7(SCR,Ba
/RESET & WDT
nk2)
R8
Power-on
(AISR,Bank /RESET & WDT
2)
Wake-up from
Pin change
Bit Name
R9
Power-on
(ADCON,B /RESET and WDT
ank2)
Wake-up from
Pin change
Bit Name
RA
Power-on
(ADOC,Ban /RESET and WDT
k2)
Wake-up from
Pin change
Bit Name
0xC
Bit 1
0
Bit Name
0xB
Bit 2
0
Wake-up from Pin
change
0xA
Bit 3
0
Bit Name
0x9
Bit 4
0
Wake-up from Pin
change
0x8
Bit 5
Wake-up from Pin
change
Bit Name
0X7
Bit 6
Power-on
RE(Bank1) /RESET & WDT
Wake-up from Pin
change
0X6
Bit 7
Product Specification (Draft 0.98) 04.03.2006
(This specification is subject to change without further notice)
ADRUN ADPD
VOF[2] VOF[1] VOF[0]
• 65
Contents
Address
Name
Reset Type
Wake-up from
Pin change
Bit Name
0XD
RD
Power-on
(ADDATA1L, /RESET and WDT
Bank2)
Wake-up from
Pin change
Bit Name
0XE
RE
Power-on
(LVDC,Ban /RESET and WDT
k2)
Wake-up from
Pin change
Bit Name
0XF
RF
(TIMER3H,
Bank2)
Bit 0
P
P
P
P
P
P
P
P
AD7
AD7
AD5
AD4
AD3
AD2
AD1
AD0
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
P
P
P
P
P
P
P
P
“0”
“0”
“0”
“0”
LVDEN
/LVD
LVD1
LVD0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
P
P
P
P
P
P
P
P
TMR3H[9] TMR3H[8] TMR3H[7] TMR3H[6] TMR3H[5] TMR3H[4] TMR3H[1] TMR3H[0]
0
0
0
/RESET & WDT
0
0
0
0
0
0
0
0
Wake-up from Pin
change
P
P
P
P
P
P
P
P
/PL57
/PL56
/PL55
/PL54
/PL53
/PL52
/PL51
/PL50
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
P
P
P
P
P
P
P
P
/PL67
/PL66
/PL65
/PL64
/PL63
/PL62
/PL61
/PL60
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
P
P
P
P
P
P
P
P
/PL77
/PL76
/PL75
/PL74
/PL73
/PL72
/PL71
/PL70
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Wake-up from Pin
change
P
P
P
P
P
P
P
P
Bit Name
“0”
“0”
“0”
/PL84
/PL83
/PL82
/PL81
/PL80
Power-on
0
0
0
1
1
1
1
1
0
0
0
1
1
1
1
1
P
P
P
P
P
P
P
P
/PH57
/PH56
/PH55
/PH54
/PH53
/PH52
/PH51
/PH50
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
P
P
P
P
P
P
P
P
/PH67
/PH66
/PH65
/PH64
/PH63
/PH62
/PH61
/PH60
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
P
P
P
P
P
P
P
P
/PH77
/PH76
/PH75
/PH74
/PH73
/PH72
/PH71
/PH70
Power-on
R5(Bank3) /RESET & WDT
Power-on
R6(Bank3) /RESET & WDT
Power-on
R7(Bank1) /RESET & WDT
R8(Bank3) /RESET & WDT
Bit Name
Power-on
R9(Bank3) /RESET & WDT
Wake-up from Pin
change
Bit Name
Power-on
RA(Bank3) /RESET & WDT
Wake-up from Pin
change
Bit Name
66 •
Bit 1
0
Wake-up from Pin
change
0XA
Bit 2
0
Bit Name
0X9
Bit 3
0
Wake-up from Pin
change
0X8
Bit 4
0
Bit Name
0X7
Bit 5
0
Wake-up from Pin
change
0X6
Bit 6
Power-on
Bit Name
0X5
Bit 7
Product Specification (V0.98) 04.03.2006
Contents
Address
Name
Reset Type
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
/PH77
/PH76
/PH75
/PH74
/PH73
/PH72
/PH71
/PH70
1
1
1
1
1
1
1
1
Wake-up from Pin
change
P
P
P
P
P
P
P
P
Bit Name
“0”
“0”
“0”
/PH84
/PH83
/PH82
/PH81
/PH80
0
0
0
1
1
1
1
1
0
0
0
1
1
1
1
1
P
P
P
P
P
P
P
P
Bit Name
0XB
0XC
RB(Bank3) /RESET
Power-on
& WDT
Power-on
RC(Bank3) /RESET & WDT
Wake-up from Pin
change
Bit Name
0XD
Power-on
RD(TMR1H
/RESET & WDT
Bank3)
Wake-up from Pin
change
Bit Name
0xE
Power-on
RE(TMR2H
/RESET & WDT
,Bank3)
Wake-up from Pin
change
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
P
P
P
P
P
P
P
P
TMR2H[9] TMR2H[8] TMR2H[7] TMR2H[6] TMR2H[5] TMR2H[4] TMR2H[1] TMR2H[0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
P
P
P
P
P
P
P
P
“0”
“0’
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
P
P
P
P
P
P
P
P
Bit Name
-
-
-
-
-
-
-
-
Power-on
U
U
U
U
U
U
U
U
/RESET and WDT
P
P
P
P
P
P
P
P
Wake-up from
Pin change
P
P
P
P
P
P
P
P
Bit Name
0xF
TMR1H[9] TMR1H[8] TMR1H[7] TMR1H[6] TMR1H[5] TMR1H[4] TMR1H[1] TMR1H[0]
Power-on
RF(TMRL,B
/RESET & WDT
ank3)
Wake-up from Pin
change
TMR3[1] TMR3[0] TMR2[1] TMR2[0] TMR1[1] TMR1[0]
LEGEND:
Product Specification (Draft 0.98) 04.03.2006
(This specification is subject to change without further notice)
– : not used.
U: unknown or don’t care
t: check “Reset Type” table in Section 6.5.2
P: previous value before reset
• 67
Contents
6.7.1.3 Controller Reset Block Diagram
VDD
D
Oscillator
Q
CLK
CLK
CLR
Power-On Reset
Voltage Detector
W TE
W DT Timeout
W DT
Reset
Setup time
/RESET
Fig. 6-7 Controller Reset Block Diagram
6.7.2 The T and P Status under STATUS Register
A RESET condition is initiated by one of the following events:
1. Power-on reset
2. /RESET pin input "low"
3. WDT time-out (if enabled).
The values of T and P as listed in the table below, are used to check how the processor
wakes up.
Reset Type
Power-on
/RESET during Operating mode
T
P
1
*P
1
*P
/RESET wake-up during SLEEP mode
1
0
WDT during Operating mode
0
*P
WDT wake-up during SLEEP mode
0
0
Wake-up on pin change during SLEEP mode
1
0
*P: Previous status before reset
The following shows the events that may affect the status of T and P.
T
P
Power-on
Event
1
1
WDTC instruction
1
1
WDT time-out
SLEP instruction
0
1
*P
0
Wake-up on pin changed during SLEEP mode
1
0
*P: Previous value before reset
68 •
Product Specification (V0.98) 04.03.2006
Contents
6.8 Interrupt
The PH86P558 has seven interrupts as listed below:
1. TCC overflow interrupt
2. Port 6 Input Status Change Interrupt
3. External interrupt [(P52, /INT0), (P53,/INT1) pin]
4. Analog to Digital conversion completed
5. When TMR1/TMR2 matches with PRD1/PRD2/PRD3 respectively in PWM
6. When the comparators output changes
7.Completion of Serial interface transmit/ receive
Before the Port 6 Input Status Change Interrupt is enabled, reading Port 6 (e.g., "MOV R6,
R6") is necessary. Each Port 6 pin will have this feature if its status changes. Any pin
configured as output, including the P52 (/INT0), and P53 (/INT1), is excluded from this
function. Port 6 Input Status Change Interrupt will wake up the PH86P558 from sleep mode
if it is enabled prior to going into the sleep mode by executing SLEP. When wake-up occurs,
the controller will continue to execute the succeeding program if the global interrupt is
disabled. If enabled, it will branch out to the interrupt vector 008H.
External interrupt equipped with digital noise rejection circuit (input pulse less than 8 system
clocks time) is eliminated as noise. Edge selection is possible with /INT. Refer to the Word
1 Bits 8~7 (Section 6.14.2, Code Option Register (Word 1)) for digital noise rejection
definition.
RF is the interrupt status register that records the interrupt requests in the relative flags/bits.
IOCF is an interrupt mask register. The global interrupt is enabled by the ENI instruction and
is disabled by the DISI instruction. When one of the interrupts (when enabled) occurs, the
next instruction will be fetched from address 008H. Once in the interrupt service routine, the
source of an interrupt can be determined by polling the flag bits in RF. The interrupt flag bit
must be cleared by instructions before leaving the interrupt service routine to avoid recursive
interrupts.
The flag (except ICIF bit) in the Interrupt Status Register (RF) is set regardless of the status
of its mask bit or of the ENI execution. Note that the result of RF will be the logic AND of RF
and IOCF (refer to figure below). The RETI instruction ends the interrupt routine and
enables the global interrupt (the ENI execution).
Product Specification (Draft 0.98) 04.03.2006
(This specification is subject to change without further notice)
• 69
Contents
Fig. 6-8 Interrupt Input Circuit
6.9 Analog-To-Digital Converter (ADC)
The analog-to-digital circuitry consists of an 8-bit analog multiplexer; three control registers
(AISR/R8, ADCON/R9, & ADOC/RA), three data registers (ADDATA1/RB, ADDATA1H/RC,
& ADDATA1L/RD) and an ADC with 12-bit resolution as shown in the functional block
diagram below. The analog reference voltage (Vref) and the analog ground are connected
via separate input pins.
The ADC module utilizes successive approximation to convert the unknown analog signal
into a digital value. The result is fed to the ADDATA, ADDATA1H and ADDATA1L. Input
channels are selected by the analog input multiplexer via the ADCON register Bits.
ADC7
Vref
ADC6
h
c
t
i
w
S
g
o
l
a
n
A
1
8
ADC5
ADC4
ADC3
ADC2
ADC1
ADC0
Power-Down
ADC
( successive approximation )
Start to Convert
Fsco
4-1
MUX
Internal RC
7 ~ 0
AISR
2
ADCON
1
0
6
3
5
ADCON
RF
11 10
9
8
ADDATA1H
7
6
5
4
3
2
1
0
ADDATA1L
4
3
ADCON
DATA BUS
Fig. 6-9 Analog-to-Digital Conversion Functional Block Diagram
70 •
Product Specification (V0.98) 04.03.2006
Contents
6.9.1 ADC Control Register (AISR/Bank 2 R8, ADCON/ Bank 2 R9,
ADOC/ Bank2 RA)
6.9.1.1 Bank2 R8 (AISR: ADC Input Select Register)
7
6
5
4
3
2
1
0
SYMBOL
ADE7
ADE6
ADE5
ADE4
ADE3
ADE2
ADE1
*Init_Value
0
0
0
0
0
0
0
AISR register defines the Port 6 pins as analog inputs or as digital I/O, individually.
Bit 7 (ADE7 ): AD converter enable bit of P67 pin
0 = Disable AIN7, P67 acts as I/O pin
1 = Enable AIN7 acts as analog input pin
Bit 6 (ADE6 ): AD converter enable bit of P66 pin
0 = Disable AIN6, P66 acts as I/O pin
1 = Enable AIN6 acts as analog input pin
Bit 5 (ADE5 ): AD converter enable bit of P65 pin
0 = Disable AIN5, P65 acts as I/O pin
1 = Enable AIN5 acts as analog input pin
Bit 4 (ADE4 ): AD converter enable bit of P64 pin
0 = Disable AIN4, P64 acts as I/O pin
1 = Enable AIN4 acts as analog input pin
Bit 3 (ADE3 ): AD converter enable bit of P63 pin
0 = Disable AIN3, P63 acts as I/O pin
1 = Enable AIN3 acts as analog input pin
Bit 2 (ADE2 ): AD converter enable bit of P62 pin
0 = Disable AIN2, P63 acts as I/O pin
1 = Enable AIN2 acts as analog input pin
Bit 1 (ADE1 ): AD converter enable bit of P61 pin
0 = Disable AIN1, P61 acts as I/O pin
1 = Enable AIN1 acts as analog input pin
Product Specification (Draft 0.98) 04.03.2006
(This specification is subject to change without further notice)
• 71
Contents
Bit 0 (ADE0 ): AD converter enable bit of P60 pin
0 = Disable AIN0, P60 acts as I/O pin
1 = Enable AIN0 acts as analog input pin
NOTE
Note the pin priority of the COS1 and COS0 bits of IOCA0 Control register when P60/ADE0
acts as analog input or as digital I/O. The Comparator/OP select bits are as shown in a table
under Section 6.2.6.
The P60/ADE0 pin priority is as follows:
P60/ADE0 PRIORITY
High
Low
ADE0
P60
6.9.1.2 Bank2 R9 (ADCON: ADC Control Register)
Bit
7
6
5
4
3
2
1
0
SYMBOL
VREFS
CKR1
CKR0
ADRUN
ADPD
ADIS2
ADIS1
ADIS0
*Init_Value
0
0
0
0
0
0
0
0
*Init_Value: Initial value at power on reset
ADCON register controls the operation of the AD conversion and decides which pin should
be currently active.
Bit 7(VREFS): The input source of the Vref of the ADC
0 = The Vref of the ADC is connected to Vdd (default value), and the
P84/VREF pin carries out the function of P84
1 = The Vref of the ADC is connected to P84/VREF
Bit 6 ~ Bit 5 (CKR1 ~ CKR0): The prescaler oscillator clock rate of ADC
00 = 1:16 (default value)
01 = 1: 4
10 = 1: 64
11 = 1: WDT ring oscillator frequency
CKR1:CKR0 Operation Mode Max. Operation Frequency
Bit 4 (ADRUN):
00
Fosc/16
4MHz
01
Fosc/4
1 MHz
10
Fosc/64
16MHz
11
Internal RC
-
ADC starts to RUN.
0 = reset on completion of the conversion. This bit
cannot be reset though software.
1 = an AD conversion is started. This bit can be set by
software.
Bit 3 (ADPD):
72 •
ADC Power-down mode.
Product Specification (V0.98) 04.03.2006
Contents
0 = switch off the resistor reference to save power even
while the CPU is operating.
1 = ADC is operating
Bit 2 ~ Bit 0 (ADIS2 ~ ADIS0): Analog Input Select.
000 = AN0/P60
001 = AN1/P61
010 = AN2/P62
011 = AN3/P63
100 = AN4/P64
101 = AN5/P65
110 = AN6/P66
111 = AN7/P67
These bits can only be changed when the ADIF bit and the
ADRUN bit are both LOW.
6.9.1.3
Bank2 RA (ADOC: ADC Offset Calibration Register)
7
6
5
4
3
2
1
0
CALI
SIGN
VOF[2]
VOF[1]
VOF[0]
“0”
“0”
“0”
Bit 7 (CALI): Calibration enable bit for ADC offset
0 = Calibration disable;
1 = Calibration enable.
Bit 6 (SIGN): Polarity bit of offset voltage
0 = Negative voltage;
1 = Positive voltage.
Bit 5 ~ Bit 3 (VOF[2] ~ VOF[0]): Offset voltage bits.
VOF[2]
VOF[1]
VOF[0]
PH86P558
0
0
0
0LSB
0
0
1
2LSB
0
1
0
4LSB
0
1
1
0
1
0
6LSB
8LSB
1
0
1
10LSB
1
1
0
12LSB
1
1
1
14LSB
Bit 2 ~ Bit 0: Unimplemented, read as ‘0’.
6.9.2 ADC Data Register (ADDATA/Bank2 RB, ADDATA1H//Bank2 RC,
ADDATA1L//Bank2 RD)
When the AD conversion is completed, the result is loaded to the ADDATA, ADDATA1H and
ADDATA1L registers. The ADRUN bit is cleared, and the ADIF is set.
Product Specification (Draft 0.98) 04.03.2006
(This specification is subject to change without further notice)
• 73
Contents
6.9.3 ADC Sampling Time
The accuracy, linearity, and speed of the successive approximation of AD converter are
dependent on the properties of the ADC and the comparator. The source impedance and
the internal sampling impedance directly affect the time required to charge the sample
holding capacitor. The application program controls the length of the sample time to meet
the specified accuracy. Generally speaking, the program should wait for 2μs for each KΩ of
the analog source impedance and at least 2μs for the low-impedance source. The
maximum recommended impedance for analog source is 10KΩ at Vdd=5V. After the analog
input channel is selected, this acquisition time must be done before the conversion is
started.
6.9.4 AD Conversion Time
CKR1 and CKR0 select the conversion time (Tct), in terms of instruction cycles. This allows
the MCU to run at the maximum frequency without sacrificing the AD conversion accuracy.
For the PH86P558, the conversion time per bit is about 4μs. The table below shows the
relationship between Tct and the maximum operating frequencies.
CKR1:CKR0
Operation
Mode
Max. Operation Max. Conversion
Frequency
Rate/Bit
Max. Conversion Rate
00
Fosc/16
4MHz
250KHz (4us)
15*4us=60us(16.7KHz)
01
Fosc/4
1MHz
250KHz (4us)
15*4us=60us(16.7KHz)
10
Fosc/64
16MHz
250KHz( 4us)
15*4us=60us(16.7KHz)
11
Internal RC
-
14KHz (71us)
15*71us=1065us(0.938KHz)
NOTE
■ Pin not used as an analog input pin can be used as regular input or output pin.
■ During conversion, do not perform output instruction to maintain precision for all of the
pins.
6.9.5 ADC Operation during Sleep Mode
In order to obtain a more accurate ADC value and reduce power consumption, the AD
conversion remains operational during sleep mode. As the SLEP instruction is executed, all
the MCU operations will stop except for the Oscillator, TCC, TIMER1, TIMER2, TIMER3,
Timer4 and AD conversion.
The AD Conversion is considered completed as determined by:
1. ADRUN bit of R9 register is cleared (“0” value)
2. Wake-up from AD conversion (where it remains in operation during sleep mode)
The results are fed into the ADDATA, ADDATA1H, and ADDATA1L registers when the
conversion is completed. If the ADWE is enabled, the device will wake up. Otherwise, the
AD conversion will be shut off, no matter what the status of ADPD bit is.
6.9.6 Programming Process/Considerations
6.9.6.1 Programming Process
Follow these steps to obtain data from the ADC:
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Product Specification (V0.98) 04.03.2006
Contents
1. Write to the eight bits (ADE7:ADE0) on the Bank2 R8 (AISR) register to define the
characteristics of R6 (digital I/O, analog channels, or voltage reference pin)
2. Write to the Bank2 R9/ADCON register to configure AD module:
a) Select ADC input channel ( ADIS2:ADIS0 )
b) Define AD conversion clock rate ( CKR1:CKR0 )
c) Select the VREFS input source of the ADC
d) Set the ADPD bit to 1 to begin sampling
3. Set the ADWE bit, if the wake-up function is employed
4. Set the ADIE bit, if the interrupt function is employed
5. Write “ENI” instruction, if the interrupt function is employed
6. Set the ADRUN bit to 1
7. Write “SLEP” instruction or Polling.
8. Wait for wake-up or for ADRUN bit to be cleared (“0” value)
9. Read the ADDATA or ADDATA1H and ADDATA1L conversion data registers. If ADC
input channel changes at this time, the ADDATA, ADDATA1H, and ADDATA1L values
can be cleared to ‘0’.
10. Clear the interrupt flag bit (ADIF).
11. For next conversion, go to Step 1 or Step 2 as required. At least 2 Tct is required before
the next acquisition starts.
NOTE
In order to obtain accurate values, it is necessary to avoid any data transition on I/O pins
during AD conversion
6.9.6.2 Sample Demo Programs
A. Define a General Registers
R_0 == 0
PSW == 3
PORT5 == 5
PORT6 == 6
RE== 0XE
RF== 0XF
; Indirect addressing register
; Status register
; Wake-up control resister
; Interrupt status register
B. Define a Control Register
IOC50 == 0X5
IOC60 == 0X6
C_INT== 0XF
; Control Register of Port 5
; Control Register of Port 6
; Interrupt Control Register
C. ADC Control Register
ADDATA == 0xB
AISR == 0x08
ADCON == 0x9
; The contents are
; ADC Input select
; 7
6
5
; VREFS CKR1 CKR0
Product Specification (Draft 0.98) 04.03.2006
(This specification is subject to change without further notice)
the results of ADC
register
4
3
2
1
0
ADRUN ADPD ADIS2 ADIS1 ADIS0
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Contents
D. Define Bits in ADCON
ADRUN == 0x4
ADPD == 0x3
; ADC is executed as the bit is set
; Power Mode of ADC
E. Program Starts
ORG 0
JMP INITIAL
; Initial address
;
ORG 0x08
; Interrupt vector
;
;
;(User program section)
;
;
CLR RF
; To clear the ADIF bit
BS ADCON, ADRUN
; To start to execute the next AD conversion
if necessary
RETI
INITIAL:
MOV A,@0B00000001 ; To define P60 as an analog input
MOV AISR,A
MOV A,@0B00001000 ; To select P60 as an analog input channel, and AD
power on
MOV ADCON,A
; To define P60 as an input pin and set clock
rate at fosc/16
En_ADC:
MOV A, @0BXXXXXXX1 ; To define P50 as an input pin, and the others
IOW PORT6
; are dependent on applications
MOV A, @0BXXXX1XXX ; Enable the ADWE wake-up function of ADC, “X”
by application
MOV RE,A
MOV A, @0BXXXX1XXX ; Enable the ADIE interrupt function of ADC,
“X” by application
IOW C_INT
ENI
; Enable the interrupt function
BS ADCON, ADRUN
; Start to run the ADC
; If the interrupt function is employed, the following three lines may
be ignored
POLLING:
JBC ADCON, ADRUN
JMP POLLING
; To check the ADRUN bit continuously;
; ADRUN bit will be reset as the AD conversion
is completed
;
;
;(User program section)
;
;
76 •
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Contents
6.10 Dual Sets of PWM (Pulse Width Modulation)
6.10.1 Overview
In PWM mode, PWM1, PWM2, and PWM3 pins produce up to a 10-bit resolution PWM
output (see. the functional block diagram below). A PWM output consisted of a time period
and a duty cycle, and it keeps the output high. The baud rate of the PWM is the inverse of
the time period. Fig. 6 -11 (PWM Output Timing) depicts the relationships between a time
period and a duty cycle.
DL2H + DL2L
Fosc
latch
To PWM1IF
DT2H
+
DT2L
1:2
1:4
1:8
1:16
1:32
1:64
1:128
1:256
Duty Cycle
Match
Comparator
MUX
PWM1
R
Q
TMR1H + TMR1L
reset
S
IOC80, 5
Comparator
T1P2 T1P1 T1P0 T1EN
Period
Match
PRD1
Data Bus
Data Bus
DL2H + DL2L
DT2H
+
DT2L
T2P2 T2P1 T2P0 T2EN
Comparator
latch
To PWM2IF
Duty Cycle
Match
PWM2
Fosc
R
TMR2H + TMR2L
reset
1:2
1:4
1:8
1:16
1:32
1:64
1:128
1:256
Q
S
MUX
IOC80, 6
Comparator
Period
Match
PRD2
DL3H + DL3L
Fosc
latch
DT3H
+
DT3L
1:2
1:4
1:8
1:16
1:32
1:64
1:128
1:256
Comparator
MUX
To PWM3IF
Duty Cycle
Match
PWM3
R
Q
TMR3H + TMR3L
reset
S
IOC80, 7
Comparator
T3P2 T3P1 T3P0 T3EN
Period
Match
PRD3
Data Bus
Data Bus
Fig. 6-10 The Three PWMs Functional Block Diagram
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(This specification is subject to change without further notice)
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Period
Duty Cycle
PRD1 = TMR1
DT1 = TMR1
Fig. 6-11 PWM Output Timing
6.10.2 Increment Timer Counter (TMRX: TMR1H/TWR1L, TMR2H
/TWR2L, or TMR3H/TWR3L)
TMRX are ten-bit clock counters with programmable prescalers. They are designed for the
PWM module as baud rate clock generators. TMRX can be read only. If employed, they can
be turned off for power saving by setting the T1EN bit [Bank1 R5<3>], T2EN bit [Bank1
R6<7>]. or T3EN bit [Bank1 R6<3>] to 0.
6.10.3 PWM Time Period (PRDX : PRD1 or PRD2)
The PWM time period is defined by writing to the PRDX register. When TMRX is equal to
PRDX, the following events occur on the next increment cycle:
TMRX is cleared
The PWMX pin is set to 1
The PWM duty cycle is latched from DT1/DT2/DT3 to DL1/DL2/DL3
NOTE
The PWM output will not be set, if the duty cycle is 0
The PWMXIF pin is set to 1
The following formula describes how to calculate the PWM time period:
PERIOD = (PRDX + 1) * (1/Fosc) * CLKS/2 * (TMRX prescale value )
Example:
PRDX=49; Fosc=4MHz; CLKS bit of Code Option Register =0 (2 oscillator
periods); TMRX(0,0,0)=1:2, then PERIOD=(49 + 1) * (1/4M) * 2/2 * 2 =25us
78 •
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Contents
6.10.4 PWM Duty Cycle (DTX: DT1H/ DT1L, DT2H/ DT2L and
DT3H/DT3L; DLX: DL1H/DL1L, DL2H/DL2L
and DL3H/DL3L )
The PWM duty cycle is defined by writing to the DTX register, and is latched from DTX to
DLX while TMRX is cleared. When DLX is equal to TMRX, the PWMX pin is cleared. DTX
can be loaded anytime. However, it cannot be latched into DLX until the current value of
DLX is equal to TMRX.
The following formula describes how to calculate the PWM duty cycle:
Duty Cycle = (DTX) * (1/Fosc) * CLKS/2 * (TMRX prescale value )
Example:
DTX=10; Fosc=4MHz; CLKS bit of Code Option Register =0 (2 oscillator
periods); TMRX(0,0,0)=1:2, then Duty Cycle=10 * (1/4M) * 2/2 * 2 =5us
6.10.5 Comparator X
Changing the output status while a match occurs, will set the TMRXIF flag at the same time.
6.10.6 PWM Programming Process/Steps
1. Load PRDX with the PWM time period.
2. Load DTX with the PWM Duty Cycle.
3. Enable interrupt function by writing IOCF, if required.
4. Set PWMX pin to be output by writing a desired value to Bank1 R5 or R6.
5. Load a desired value to Bank1 R5 or R6 with TMRX prescaler value and enable both
PWMX and TMRX.
6.11 Timer
6.11.1 Overview
Timer1 (TMR1), Timer2 (TMR2),and Timer3 (TMR3) (TMRX) are 10-bit clock counters with
programmable prescalers. They are designed for the PWM module as baud rate clock
generators. TMRX can be read only. The TIMER1, TIMER2, and TIMER3 will stop running
when sleep mode occurs with AD conversion not running. However, if AD conversion is
running when sleep mode occurs, the TIMER1, TIMER2 and TIMER3, will keep on running.
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(This specification is subject to change without further notice)
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6.11.2 Function Description
The following figure shows the TMRX block diagram followed by descriptions of its signals
and blocks:
Fosc
1:2
1:4
1:8
1:16
1:32
1:64
1:128
1:256
To PWM1IF
MUX
TMR1X
reset
Period
Match
Comparator
T1P2 T1P1 T1P0 T1EN
PRD1
Data Bus
Data Bus
PRD2
T2P2 T2P1 T2P0 T2EN
Comparator
TMR2X
1:2
1:4
1:8
1:16
1:32
1:64
1:128
1:256
Fosc
reset
Period
Match
MUX
To PWM2IF
*TMR1X = TMR1H + TMR1L;
*TMR2X = TMR2H + TMR2L;
*TMR3X = TMR3H + TMR3L
Fosc
1:2
1:4
1:8
1:16
1:32
1:64
1:128
1:256
To PWM13F
MUX
TMR3X
reset
Period
Match
Comparator
T3P2 T3P1 T3P0 T3EN
PRD3
Data Bus
Data Bus
Fig. 6-12 TMRX Block Diagram
Fosc: Input clock.
Prescaler (T1P2, T1P1 and T1P0 / T2P2, T2P1 and T2P0 / T3P2, T3P1 and T3P0): The
options 1:2, 1:4, 1:8, 1:16, 1:32, 1:64, 1:128, and 1:256 are defined by TMRX. It is
cleared when any type of reset occurs.
TMR1X, TMR2X and TMR3X (TMR1H/TWR1L, TMR2H/TMR2L, & TMR3H/TMR3L):
Timer X register; TMRX is increased until it matches with PRDX, and then is reset to
1 (default valve).
80 •
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Contents
PRDX (PRD1/PRD1H, PRD2/PRD2H and PRD3/PRD3H):
PWM time period register.
ComparatorX (Comparator 1 and Comparator 2):
Reset TMRX while a match occurs. The TMRXIF flag is set at the same time.
6.11.3 Programming the Related Registers
When defining TMRX, refer to the related registers of its operation as shown in the table
below. It must be noted that the PWMX bits must be disabled if their related TMRXs are
employed. That is, Bit 7 ~ Bit 5 of the PWMCON register must be set to ‘0’.
6.11.3.1Related Control Registers of TMR1, TMR2, and TMR3
Address
Name
Bit 7
Bit 6
Bit 5
IOC80
PWMCON#1/Bank1 R5 PWM3E PWM2E PWM1E
IOC90
PWMCON#2/Bank1 R6
T2EN
T2P2
T2P1
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
“0”
T1EN
T1P2
T1P1
T1P0
T2P0
T3EN
T3P2
T3P1
T3P0
6.11.4 Timer Programming Process/Steps
1. Load PRDX with the TIMER duration
2. Enable interrupt function by writing IOCF, if required
3. Load a desired a TMRX prescaler value to PWMCON and TMRCON and enable TMRX
and disable PWMX
6.12 Comparator
PH86P558 has one comparator comprising of two analog inputs and one output. The
comparator can be utilized to wake up PH86P558 from sleep mode. The comparator circuit
diagram is depicted in the figure below.
Cin CMP
+
Cin+
CO
CinCin+
Output
10mV
Fig. 6-13 Comparator Circuit Diagram & Operating Mode
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(This specification is subject to change without further notice)
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6.12.1 External Reference Signal
The analog signal that is presented at Cin– compares to the signal at Cin+, and the digital
output (CO) of the comparator is adjusted accordingly by taking the following notes into
considerations:
NOTE
■ The reference signal must be between Vss and Vdd.
■ The reference voltage can be applied to either pin of comparator.
■ Threshold detector applications may be of the same reference.
■ The comparator can operate from the same or different reference sources.
6.12.2 Comparator Outputs
The compared result is stored in the CMPOUT of IOCA0.
The comparator outputs are sent to CO (P56) through programming Bit 1,
Bit 0<COS1, COS0> of the IOCA0 register to <1,0>. See Section 6.2.6, IOCA0
(CMPCON: Comparator Control Register) for Comparator/OP select bits function
description.
NOTE
■ The P56/CO pin priority is as follows:
P60/ADE0/CO PRIORITY
High
Low
CO
P56
The following figure shows the Comparator Output block diagram.
To C0
From OP I/O
CMRD
EN
Q
EN
D
Q
D
To CMPOUT
RESET
To CPIF
CMRD
From other
comparator
Fig. 6-14 Comparator Output Configuration
82 •
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6.12.3 Using Comparator as an Operation Amplifier
The comparator can be used as an operation amplifier if a feedback resistor is connected
from the input to the output externally. In this case, the Schmitt trigger can be disabled for
power saving by setting Bit 1, Bit 0<COS1, COS0> of the IOCA0 register to <1,1>. See
Section 6.2.6, IOCA0 (CMPCON: Comparator Control Register) for Comparator/OP select
bits function description.
6.12.4 Comparator Interrupt
CMPIE (IOCE.0) must be enabled for the “ENI” instruction to take effect
Interrupt is triggered whenever a change occurs on the comparator output pin
The actual change on the pin can be determined by reading the Bit CMPOUT, IOCA0<2>
CMPIF (RE.0), the comparator interrupt flag, can only be cleared by software
6.12.5 Wake-up from SLEEP Mode
If enabled, the comparator remains active and the interrupt remains functional, even
under SLEEP mode.
If a mismatch occurs, the interrupt will wake up the device from SLEEP mode.
The power consumption should be taken into consideration for the benefit of energy
conservation.
If the function is unemployed during SLEEP mode, turn off comparator before entering
into sleep mode.
6.13 Oscillator
6.13.1 Oscillator Modes
The PH86P558 can be operated in four different oscillator modes, such as High XTAL
oscillator mode (HXT), Low XTAL oscillator mode (LXT), External RC oscillator mode (ERC),
and RC oscillator mode with Internal RC oscillator mode (IRC). You can select one of them
by programming the OSC2, OCS1, and OSC0 in the CODE Option register.
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The Oscillator modes defined by OSC2, OCS1, and OSC0 are described below.
Oscillator Modes
OSC2
OSC1
OSC0
1
0
0
0
1
0
0
1
0
1
0
ERC (External RC oscillator mode); P50/OSCO acts as P50
ERC (External RC oscillator mode); P50/OSCO acts as OSCO
2
IRC (Internal RC oscillator mode); P50/OSCO acts as P50
2
0
1
1
3
1
1
0
1
1
1
IRC (Internal RC oscillator mode); P50/OSCO acts as OSCO
LXT (Low XTAL oscillator mode)
3
HXT High XTAL oscillator mode) (default)
1
Under ERC mode, OSCI is used as oscillator pin. OSCO/P50 is defined by code
option WORD0 Bit6 ~ Bit4.
2
Under IRC mode, P55 is normal I/O pin. OSCO/P50 is defined by code
option WORD0 Bit6 ~ Bit4.
3
Under LXT and HXT modes; OSCI and OSCO are used as oscillator pins. These
pins cannot and should not be defined as normal I/O pins.
NOTE
The transient point of the system frequency between HXT and LXY is around 400kHz.
The maximum operating frequency limit of crystal/resonator at different VDDs, are as
follows:
Conditions
Two clocks
VDD
Max. Freq. (MHz)
2.3
4
3.0
8
5.0
20
6.13.2 Crystal Oscillator/Ceramic Resonators (XTAL)
PH86P558 can be driven by an external clock signal through the OSCI pin as illustrated
below.
Fig. 6.15 External Clock Input Circuit
84 •
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Contents
In the most applications, Pin OSCI and Pin OSCO can be connected with a crystal or
ceramic resonator to generate oscillation. Fig. 6-16 below depicts such circuit. The same
applies to the HXT mode and the LXT mode.
Fig. 6-16 Crystal/Resonator Circuit
The following table provides the recommended values for C1 and C2. Since each resonator
has its own attribute, you should refer to the resonator specifications for appropriate values
of C1 and C2. RS, a serial resistor, may be required for AT strip cut crystal or low frequency
mode.
Capacitor selection guide for crystal oscillator or ceramic resonators:
Oscillator Type
Frequency Mode
Ceramic Resonators
HXT
LXT
Crystal Oscillator
HXT
Frequency
C1(pF)
C2(pF)
455 kHz
100~150
100~150
2.0 MHz
20~40
20~40
4.0 MHz
10~30
10~30
32.768kHz
25
15
100KHz
25
25
200KHz
25
25
455KHz
20~40
20~150
1.0MHz
15~30
15~30
2.0MHz
15
15
4.0MHz
15
15
6.13.3 External RC Oscillator Mode
For some applications that do not require
precise timing calculation, the RC
oscillator (Fig. 6-17 right) could offer you
with effective cost savings. Nevertheless,
it should be noted that the frequency of
the RC oscillator is influenced by the
supply voltage, the values of the resistor
(Rext), the capacitor (Cext), and even by
the operation temperature. Moreover, the
frequency also changes slightly from one
chip to another due to the manufacturing
process variation.
Product Specification (Draft 0.98) 04.03.2006
(This specification is subject to change without further notice)
Fig. 6-17 External RC Oscillator Mode Circuit
• 85
Contents
In order to maintain a stable system frequency, the values of the Cext should be no less than
20pF, and that the value of Rext should be no greater than 1MΩ. If the frequency cannot be
kept within this range, the frequency can be affected easily by noise, humidity, and leakage.
The smaller the Rext in the RC oscillator is, the faster its frequency will be. On the contrary,
for very low Rext values, for instance, 1 KΩ, the oscillator will become unstable because the
NMOS cannot discharge the capacitance current correctly.
Based on the above reasons, it must be kept in mind that all supply voltage, the operation
temperature, the components of the RC oscillator, the package types, and the way the PCB
is layout, have certain effect on the system frequency.
The RC Oscillator frequencies:
Cext
20 pF
100 pF
300 pF
Rext
Average Fosc 5V,25°C
Average Fosc 3V,25°C
3.3k
3.5 MHz
3.2 MHz
5.1k
2.5 MHz
2.3 MHz
10k
1.30 MHz
1.25 MHz
100k
140 KHz
140 KHz
3.3k
1.27 MHz
1.21 MHz
5.1k
850 KHz
820 KHz
10k
450 KHz
450 KHz
100k
48 KHz
50 KHz
3.3k
560 KHz
540 KHz
5.1k
370 KHz
360 KHz
10k
196 KHz
192 KHz
100k
20 KHz
20 KHz
NOTE: 1. Measured on DIP packages.
2. Design reference only
3. The frequency drift is about ±30%
6.13.4 Internal RC Oscillator Mode
PH86P558 offers a versatile internal RC mode with default frequency value of 4MHz.
Internal RC oscillator mode has other frequencies (1MHz, 8MHz, and 455KHz) that can be
set by CODE OPTION (WORD1), RCM1, and RCM0. Table below describes the PH86P558
internal RC drift with the variation of voltage, temperature, and process.
86 •
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Contents
Internal RC Drift Rate (Ta=25℃, VDD=5V±5%, VSS=0V)
Drift Rate
Internal
RC Frequency
Temperature
(-40℃~+85℃)
Voltage
(2.3V~5.5V)
Process
Total
4MHz
±10%
±5%
±4%
±19%
8MHz
±10%
±6%
±4%
±20%
1MHz
±10%
±5%
±4%
±19%
455MHz
±10%
±5%
±4%
±19%
Theoretical values are for reference only. Actual values may vary depending on actual process.
6.14 Power-on Considerations
Any microcontroller is not warranted to start operating properly before the power supply
stabilizes in steady state. PH86P558 is equipped with Power On Voltage Detector (POVD)
with detection level range of 1.9V to 2.1V. The circuitry eliminates the extra external reset
circuit. It will work well if Vdd rises quickly enough (50 ms or less). However, under critical
applications, extra devices are still required to assist in solving power-on problems.
6.14.1 External Power-on Reset Circuit
The circuit shown in the
following figure implements
an external RC to produce a
reset pulse. The pulse
width (time constant) should
be kept long enough to
allow Vdd to reach the
minimum operating voltage.
This circuit is used when the
power supply has a slow
Fig. 6-18 External Power on Reset Circuit
power rise time. Because
the current leakage from the /RESET pin is about ±5μA, it is recommended that R should not
be great than 40 K. This way, the voltage at Pin /RESET is held below 0.2V. The diode (D)
acts as a short circuit at power-down. The “C” capacitor is discharged rapidly and fully. Rin,
the current-limited resistor, prevents high current discharge or ESD (electrostatic discharge)
from flowing into Pin /RESET.
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6.14.2 Residual Voltage Protection
When the battery is replaced, device power (Vdd) is removed but residual voltage remains.
The residual voltage may trips below Vdd minimum, but not to zero. This condition may
cause a poor power on reset. Fig. 6-16 and Fig. 6-20 show how to create a protection circuit
against residual voltage.
Fig. 6-19 Residual Voltage Protection Circuit 1
Fig. 6-20 Residual Voltage Protection Circuit 2
6.15 LVD (Low Voltage Detector)
During the power source unstable situation, such like external power noise interference of
EMS test condition, it will cause the power vibrate fierce. At the time the Vdd is unsettled, it
maybe below working voltage. When system supplies voltage, Vdd, below the working
voltage, the IC kernel must keep all register status automatically. LVD property is setting at
Register RE, Bit 1,0 detail operation mode as following:
•
88 •
7
6
5
4
3
2
1
0
“0”
“0”
“0”
“0”
LVDEN
/LVD
LVD1
LVD0
Bit 1 ~ 0 (LVD1 ~ LVD0) : Low Voltage Detect level control Bits.
Product Specification (V0.98) 04.03.2006
Contents
LVD1
LVD0
LVD voltage interrupt level
1
1
2.3
1
0
3.3
0
1
4.0
0
0
4.5
The LVD status and interrupt flag is refer to RF
Register
7
6
5
4
RF
“0”
“0”
“0”
LVDIF
3
2
ADWE CMPWE
1
0
ICWE
PWMWE
“1” means interrupt request, and “0” means no interrupt occurs.
Bit 4 (LVDIF): Low voltage Detector interrupt Register
When LVD1, LVD0 = “1,1”, Vdd >2.3V, LVDF is “0”, Vdd<= 2.3V, set LVIF to “1”. LVDIF reset
to “0” by software.
When LVD1, LVD0 = “1,0”, Vdd >3.3V, LVDF is “0”, Vdd<= 3.3V, set LVIF to “1”. LVDIF reset
to “0” by software.
When LVD1, LVD0 = “0,1”, Vdd >4.0V, LVDF is “0”, Vdd<= 4.0V, set LVIF to “1”. LVDIF reset
to “0” by software.
When LVD1, LVD0 = “0,0”, Vdd >4.5V, LVDF is “0”, Vdd<= 4.5V, set LVIF to “1”. LVDIF reset
to “0” by software.
The following steps are needed to setup the LVD function:
Set the LVDEN of Register RE of bank2 to”1”, then use bit 1,0(LVD1,LVD0) of Register RE of
bank2 to set LVD interrupt level Waiting for occur interrupt.
The internal LVD module is using internal circuit to fit. When you set the LVDEN enable the
LVD module. The current consumption will increase about 10uA. During the sleep mode, the
LVD module continues to operate. If the device voltage drop slowly and crosses the detect
point. The LVDIF bit will be set and device won’t wake up from sleep time. Until the others
wake-up source of PH86P558, the LVD interrupt flag still set as the prior status.
When system reset, the LVD flag will be clear.
When Vdd drop not below VLVD, LVDIF keep at “0”.
When Vdd drop below VLVD, LVDIF set to “1”. If global ENI enable, LVDIF will be set to “1”, the next
instruction will branched to interrupt vector. The LVD interrupt flag clear to “0” by software.
When Vdd drop below VRESET and less than 80us, system will keep all the register status
and system halt but oscillation active. When Vdd drop below VRESET and more than 80us,
system will occur RESET, and the following actions refer the section 6.5.1 RESET
description.
Product Specification (Draft 0.98) 04.03.2006
(This specification is subject to change without further notice)
• 89
Contents
6.16 Code Option
PH86P558 has two CODE option words and one Customer ID word that are not a part of the
normal program memory.
Word 0
Word1
Word 2
Bit12 ~ Bit0
Bit12 ~ Bit0
Bit12 ~ Bit0
6.16.1 Code Option Register (Word 0)
WORD 0
Bit 12 Bit 11 Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
MCEN
LCE
CLKS
ENWDTB
OSC2
OSC1
OSC0
HLP
PR2
PR1
PR0
LVR1
LVR0
Bit 12:
Low voltage reset enable bits.
Bit 11 ~ 10:
LVR1, LVR0
Reset Level
Release Level
00
01
10
11
4.0V
3.5V
2.7V
NA
4.2V
3.7V
2.9V
NA
If VDD < 1.8V, IC will be reset.
If VDD < 2.7V, IC will be reset
If VDD < 3.5V, IC will be reset.
If VDD < 4.0V, IC will be reset.
Bit 9 (LCE) :
Low crystal output enable
0 : Select General-purpose I/O (P74)
1 : Low crystal 32.768K Hz output
Bit 8 (CLKS):
Instruction time period option bit
0 = two oscillator time periods
1 = four oscillator time periods (default)
Refer to the Section 6.15 for Instruction Set
Bit 7 (ENWDTB):
Watchdog timer enable bit
0 = Enable
1 = Disable (default)
Bit 6, 5 & 4 (OSC2, OSC1 & OSC0): Oscillator Modes Selection bits
Oscillator Modes
1
ERC (External RC oscillator mode); P50/OSCO acts as P50
1
ERC (External RC oscillator mode); P50/OSCO acts as OSCO
2
IRC (Internal RC oscillator mode); P50/OSCO acts as P50
90 •
OSC2
OSC1
OSC0
0
0
0
0
0
1
0
1
0
Product Specification (V0.98) 04.03.2006
Contents
2
0
1
1
3
1
1
0
1
1
1
IRC (Internal RC oscillator mode); P50/OSCO acts as OSCO
LXT (Low XTAL oscillator mode)
3
HXT High XTAL oscillator mode) (default)
1
Under ERC mode, OSCI is used as oscillator pin. OSCO/P50 is defined by code
option WORD0 Bit6 ~ Bit4.
2
Under IRC mode, P51 is normal I/O pin. OSCO/P50 is defined by code
option WORD0 Bit6 ~ Bit4.
3
Under LXT and HXT modes; OSCI and OSCO are used as oscillator pins. These
pins cannot and should not be defined as normal I/O pins.
NOTE
The transient point of the system frequency between HXT and LXY is around 400kHz.
Power consumption selection
Bit 3 (HLP):
0 = Low power consumption, applies to working frequency
at 4MHz or below 4MHz
1 = High power consumption, applies to working frequency
above 4MHz
Bit 2 ~ 0 (PR2 ~ PR0):
Protect Bit
PR2 ~ PR0 are protect bits. Each protect status is as follows:
PR2
PR1
PR0
Protect
0
0
0
Enable
0
0
1
Enable
0
1
0
Enable
0
1
1
Enable
1
0
0
Enable
1
0
1
Enable
1
1
0
Enable
1
1
1
Disable
6.16.2 Code Option Register (Word 1)
Bit 12 Bit 11
–
–
Bit 10
Bit 9
Bit 8
WORD 1
Bit 7 Bit 6 Bit 5
–
-
NRHL
NRE
CYES
C3
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
C2
C1
C0
RCM1
RCM0
Bits 12 ~ 9:
Not used (reserved). These bits are set to “1” all the time
Bit 8 (NRHL):
Noise rejection high/low pulses define bit. INT pin is falling edge trigger
0 = Pulses equal to 8/fc [s] is regarded as signal.
1 = Pulses equal to 32/fc [s] is regarded as signal.
(default)
NOTE
The noise rejection function is turned off under the LXT and sleep mode.
Bit 7 (NRE):
Noise rejection enable
0 = disable noise rejection
Product Specification (Draft 0.98) 04.03.2006
(This specification is subject to change without further notice)
• 91
Contents
1 = enable noise rejection (default). However under Low XTAL
oscillator (LXT) mode, the noise rejection circuit always
disabled.
Bit 6 (CYES):
Instruction cycle selection bit
0 = one instruction cycle
1 = two instruction cycles (default)
Bits 5, 4, 3 & Bit2 ( C3, C2, C1, & C0 ): Calibrator of internal RC mode. These bits
must always be set to “1” only (auto calibration)
Bit 1 & Bit 0 (RCM1 & RCM0): RC mode selection bits
RCM 1
RCM 0
Frequency(MHz)
1
1
4
1
0
8
0
1
1
0
0
455kHz
6.16.3 Customer ID Register (Word 2)
WORD 2
Bit 12 Bit 11 Bit 10
X
X
X
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
X
X
X
X
X
X
X
X
X
X
Bit 12 ~ 0 : Customer’s ID code
Instruction Set
Each instruction in the instruction set is a 13-bit word divided into an OP code and one or
more operands. Normally, all instructions are executed within one single instruction cycle
(one instruction consists of 2 oscillator time periods), unless the program counter is changed
by instructions "MOV R2,A," "ADD R2,A," or by instructions of arithmetic or logic operation
on R2 (e.g., "SUB R2,A," "BS(C) R2,6," "CLR R2," etc.). In this case, these instructions
need one or two instruction cycles as determined by Code Option Register CYES bit.
In addition, the instruction set has the following features:
1. Every bit of any register can be set, cleared, or tested directly.
2. The I/O registers can be regarded as general registers. That is, the same instruction can
operate on I/O registers.
The symbol "R" represents a register designator that specifies which one of the registers
(including operational registers and general-purpose registers) is to be utilized by the
instruction. The symbol "b" represents a bit field designator that selects the value for the bit
located in the register "R" that is affected by the operation. The symbol "k" represents an 8
or 10-bit constant or literal value.
92 •
Product Specification (V0.98) 04.03.2006
Contents
The following are the list of the PH86P558 instruction set
Instruction Binary
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0001
0001
0001
0001
0010
0010
0010
0010
0011
0011
0011
0011
0100
0100
0100
0100
0101
0101
0101
0101
0110
0110
0110
0110
0111
0111
0111
0111
100b
101b
110b
111b
00kk
01kk
1000
1001
0000 0000
0000 0001
0000 0010
0000 0011
0000 0100
0000 rrrr
0001 0000
0001 0001
0001 0010
0001 0011
0001 0100
0001 rrrr
01rr rrrr
1000 0000
11rr rrrr
00rr rrrr
01rr rrrr
10rr rrrr
11rr rrrr
00rr rrrr
01rr rrrr
10rr rrrr
11rr rrrr
00rr rrrr
01rr rrrr
10rr rrrr
11rr rrrr
00rr rrrr
01rr rrrr
10rr rrrr
11rr rrrr
00rr rrrr
01rr rrrr
10rr rrrr
11rr rrrr
00rr rrrr
01rr rrrr
10rr rrrr
11rr rrrr
00rr rrrr
01rr rrrr
10rr rrrr
11rr rrrr
bbrr rrrr
bbrr rrrr
bbrr rrrr
bbrr rrrr
kkkk kkkk
kkkk kkkk
kkkk kkkk
kkkk kkkk
HEX
Mnemonic
0000
0001
0002
0003
0004
000r
0010
0011
0012
0013
0014
001r
00rr
0080
00rr
01rr
01rr
01rr
01rr
02rr
02rr
02rr
02rr
03rr
03rr
03rr
03rr
04rr
04rr
04rr
04rr
05rr
05rr
05rr
05rr
06rr
06rr
06rr
06rr
07rr
07rr
07rr
07rr
0xxx
0xxx
0xxx
0xxx
1kkk
1kkk
18kk
19kk
NOP
DAA
CONTW
SLEP
WDTC
IOW R
ENI
DISI
RET
RETI
CONTR
IOR R
MOV R,A
CLRA
CLR R
SUB A,R
SUB R,A
DECA R
DEC R
OR A,R
OR R,A
AND A,R
AND R,A
XOR A,R
XOR R,A
ADD A,R
ADD R,A
MOV A,R
MOV R,R
COMA R
COM R
INCA R
INC R
DJZA R
DJZ R
RRCA R
RRC R
RLCA R
RLC R
SWAPA R
SWAP R
JZA R
JZ R
BC R,b
BS R,b
JBC R,b
JBS R,b
CALL k
JMP k
MOV A,k
OR A,k
Operation
No Operation
Decimal Adjust A
A → CONT
0 → WDT, Stop oscillator
0 → WDT
A → IOCR
Enable Interrupt
Disable Interrupt
[Top of Stack] → PC
[Top of Stack] → PC, Enable Interrupt
CONT → A
IOCR → A
A→R
0→A
0→R
R-A → A
R-A → R
R-1 → A
R-1 → R
A ∨ VR → A
A ∨ VR → R
A&R→A
A&R→R
A⊕R→A
A⊕R→R
A+R→A
A+R→R
R→A
R→R
/R → A
/R → R
R+1 → A
R+1 → R
R-1 → A, skip if zero
R-1 → R, skip if zero
R(n) → A(n-1),R(0) → C, C → A(7)
R(n) → R(n-1),R(0) → C, C → R(7)
R(n) → A(n+1),R(7) → C, C → A(0)
R(n) → R(n+1),R(7) → C, C → R(0)
R(0-3) → A(4-7),R(4-7) → A(0-3)
R(0-3) ↔ R(4-7)
R+1 → A, skip if zero
R+1 → R, skip if zero
0 → R(b)
1 → R(b)
if R(b)=0, skip
if R(b)=1, skip
PC+1 → [SP],(Page, k) → PC
(Page, k) → PC
k→A
A∨k→A
Product Specification (Draft 0.98) 04.03.2006
(This specification is subject to change without further notice)
Status Affected
None
C
None
T,P
T,P
1
None
None
None
None
None
None
1
None
None
Z
Z
Z,C,DC
Z,C,DC
Z
Z
Z
Z
Z
Z
Z
Z
Z,C,DC
Z,C,DC
Z
Z
Z
Z
Z
Z
None
None
C
C
C
C
None
None
None
None
2
None
3
None
None
None
None
None
None
Z
• 93
Contents
Instruction Binary
1
1
1
1
1
1
1
94 •
1010
1011
1100
1101
1110
1110
1111
kkkk
kkkk
kkkk
kkkk
1000
1001
kkkk
kkkk
kkkk
kkkk
kkkk
00kk
00kk
kkkk
HEX
1Akk
1Bkk
1Ckk
1Dkk
1E8K
1E9K
1Fkk
Mnemonic
Operation
Status Affected
AND A,k
A&k→A
Z
XOR A,k
A⊕k→A
Z
RETL k
k → A,[Top of Stack] → PC
None
SUB A,k
k-A → A
Z,C,DC
PAGE k
k->R3(7:5)
None
BANK k
k->R4(7:6)
None
ADD A,k
k+A → A
Z,C,DC
1
This instruction is applicable to IOC50 ~ IOCF, IOC51 ~ IOCF1 only.
2
This instruction is not recommended for RF operation.
3
This instruction cannot operate under RF.
Product Specification (V0.98) 04.03.2006
Contents
7
Absolute Maximum Ratings
Items
Rating
Temperature under bias
-40°C
to
85°C
Storage temperature
-65°C
to
150°C
Input voltage
Vss-0.3V
to
Vdd+0.5V
Output voltage
Vss-0.3V
to
Vdd+0.5V
Working Voltage(industrial
grade)
2.3V
to
5.5V
Working Frequency
DC
to
20MHz
Product Specification (Draft 0.98) 04.03.2006
(This specification is subject to change without further notice)
• 95
Contents
8
DC Electrical Characteristics
(Ta= 25 °C, VDD= 5.0V, VSS= 0V )
Symbol
FXT
IRC1
IRC2
IRC3
IRC4
VIHRC
VILRC
IIL
VIH1
VIL1
VIHT1
VILT1
VIHT2
VILT2
VIHX1
Parameter
XTAL: VDD to 5V
XTAL: VDD to 3V
ERC: VDD to 5V
IRC:VDD to 5V
IRC:VDD to 5V
IRC:VDD to 5V
IRC:VDD to 5V
Input High Threshold
Voltage (Schmitt trigger )
Input Low Threshold Voltage
(Schmitt trigger )
Input Leakage Current for
input pins
Input High Voltage (Schmitt
trigger )
Input Low Voltage (Schmitt
trigger )
Input High Threshold
Voltage (Schmitt trigger )
Input Low Threshold Voltage
(Schmitt trigger )
Input High Threshold
Voltage (Schmitt trigger )
Input Low Threshold Voltage
(Schmitt trigger )
Clock Input High Voltage
VILX1 Clock Input Low Voltage
Output High Voltage
IOH1 (Ports 50~53, Ports 60~63)
(Ports 70~77, Ports 80~84)
Output High Voltage
IOH2 (Ports P54~P57,
Ports 64~67)
Output Low Voltage
IOL1 (Ports 50~53, Ports 60~63)
(Ports 70~77, Ports 80~84)
Output Low Voltage
IOL2 (Ports P54~P57,
Ports 64~67)
IBOL Output Sink Current
IBOH Output Drive Current
IPH Pull-high current
IPL Pull-low current
ISB1
Power down current
ISB2
Power down current
ICC1
Operating supply current
at two clocks
ICC2
Operating supply current
at two clocks
96 •
Condition
Min.
DC
DC
F±30%
3.84
7.68
0.96
436.8
Two cycle with two clocks
R: 5.1KΩ, C: 100 pF
RCM0:RCM1=1:1
RCM0:RCM1=1:0
RCM0:RCM1=0:1
RCM0:RCM1=0:0
Typ.
850
4.0
8.0
1.0
455
Max.
Unit
20
8
F±30%
4.16
8.32
1.06
473.2
MHz
MHz
KHz
MHz
MHz
MHz
KHz
OSCI in RC mode
3.5
V
OSCI in RC mode
1.5
V
VIN = VDD, VSS
–1.0
0
1.0
μA
Ports 5, 6, 7,8
3.75
V
Ports 5, 6, 7,8
1.25
V
/RESET
2.0
V
/RESET
1.0
V
TCC,INT
3.75
V
TCC,INT
1.25
V
OSCI in crystal mode
3.5
V
OSCI in crystal mode
1.5
V
VOH = VDD-0.5V (IOH =-6mA)
-9.0
mA
VOH = VDD-0.5V (IOH =-9mA)
-12.0
mA
VOL = GND+0.5V (IOL =12mA)
18.0
mA
VOL = GND+0.5V (IOL =24mA)
24.0
mA
Buzzer output sink current
Buzzer output drive current
Pull-high active, input pin at VSS –50
Pull-low active, input pin at Vdd 25
All input and I/O pins at VDD,
output pin floating, WDT disabled
All input and I/O pins at VDD,
output pin floating, WDT enabled
/RESET= 'High', Fosc=32KHz
(Crystal type,CLKS="0"), output 15
pin floating, WDT disabled
/RESET= 'High', Fosc=32KHz
(Crystal type,CLKS="0"), output
pin floating, WDT enabled
24
24
–75
40
–240
120
mA
mA
μA
μA
1.0
2.0
μA
15
μA
20
35
μA
25
35
μA
Product Specification (V0.98) 04.03.2006
Contents
ICC3
Operating supply current
at two clocks
ICC4
Operating supply current
at two clocks
8.1
/RESET= 'High', Fosc=4MHz
(Crystal type, CLKS="0"), output
pin floating, WDT enabled
/RESET= 'High', Fosc=10MHz
(Crystal type, CLKS="0"), output
pin floating, WDT enabled
1.7
2.2
mA
3.0
3.5
mA
AD Converter Characteristic
(Vdd=2.5V to 5.5V,Vss=0V,Ta=25℃)
Symbol
VAREF
VASS
VAI
Analog reference voltage
Condition
VAREF - VASS≧2.3V
Analog input voltage
Min.
Typ.
Max.
Unit
2.3
Vdd
V
Vss
Vss
V
VASS
VAREF
V
Analog supply current
Vdd=VAREF=5.0V, VASS
=0.0V(V reference from Vdd)
750
850
1000
uA
-10
0
+10
uA
Vdd=VAREF=5.0V, VASS
=0.0V(V reference from
VREF)
500
600
820
uA
Analog supply current
200
250
300
uA
IOP
OP current
Vdd=5.0V, OP used
Output voltage swing 0.15V to
4.85V
450
550
650
uA
RN
Resolution
Vdd=VAREF=5.0V, VASS =0.0V
10
11
LN
Linearity error
Vdd = 2.3 to 5.5V Ta=25℃
0
±4
±8
LSB
DNL
Differential nonlinear error
Vdd = 2.3 to 5.5V Ta=25℃
0
±0.5
±0.9
LSB
FSE
Full scale error
Vdd=VAREF=5.0V, VASS =0.0V
±0
±4
±8
LSB
OE
Offset error
Vdd=VAREF=5.0V, VASS =0.0V
±0
±2
±4
LSB
ZAI
Recommended impedance of
analog voltage source
0
8
10
KΩ
TAD
ADC clock duration
Vdd=VAREF=5.0V, VASS =0.0V
4
TCN
AD conversion time
Vdd=VAREF=5.0V, VASS =0.0V
15
15
TAD
ADIV
ADC OP input voltage range
Vdd=VAREF=5.0V, VASS =0.0V
0
VAREF
V
ADOV
ADC OP output voltage swing
Vdd=VAREF=5.0V, VASS
=0.0V,RL=10KΩ
0
0.2
0.3
4.7
4.8
5
ADSR
ADC OP slew rate
Vdd=VAREF=5.0V, VASS =0.0V
0.1
0.3
Power Supply Rejection
Vdd=5.0V±0.5V
±0
IAI1
Ivdd
Parameter
Ivref
Ivdd
IAI2
IVref
PSR
NOTE:
Bits
us
V
V/us
±2
LSB
1. These parameters are hypothetical (not tested) and are provided for design reference only.
2. There is no current consumption when ADC is off other than minor leakage current.
3. AD conversion result will not decrease when the input voltage is increased, and no missing code
will result.
4. These parameters are subject to change without further notice.
Product Specification (Draft 0.98) 04.03.2006
(This specification is subject to change without further notice)
• 97
Contents
8.2
Comparator (OP) Characteristic
(Vdd = 5.0V,Vss=0V,Ta=25℃)
Symbol
Parameter
Condition
SR
Slew rate
IVR
Input voltage range
Vdd =5.0V, VSS =0.0V
OVS
Output voltage swing
Vd =5.0V, VSS =0.0V,RL=10KΩ
Iop
Supply current of OP
Ico
Supply current of Comparator
PSRR
Power-supply Rejection Ration
for OP
Vs
Operating range
NOTE:
98 •
Min.
Typ.
0.1
0.2
0
Max.
Unit
V/us
5
0
0.2
0.3
4.7
4.8
5
250
350
500
300
Vdd= 5.0V, VSS =0.0V
50
2.5
60
V
V
uA
uA
70
dB
5.5
V
1. These parameters are hypothetical (not tested) and are provided for design reference only.
2. These parameters are subject to change without further notice.
Product Specification (V0.98) 04.03.2006
Contents
8.3
Device Characteristics
The graphs below were derived based on a limited number of samples and they are
provided for reference only. Hence, the device characteristic shown herein cannot be
guaranteed as fully accurate. In these graphs, the data maybe out of the specified operating
warranted range.
IRC OSC Frequency (VDD=3V)
9
Frequency (M Hz) .
8
7
6
5
4
3
2
1
0
-40
-20
0
25
70
50
85
Temperature (℃)
Fig. 8-1 Internal RC OSC Frequency vs. Temperature, VDD=3V
Product Specification (Draft 0.98) 04.03.2006
(This specification is subject to change without further notice)
• 99
Contents
IRC OSC Frequency (VDD=5V)
10
Frequency (M Hz) .
9
8
7
6
5
4
3
2
1
0
-40
-20
0
25
50
70
85
Temperature (℃)
Fig. 8-2 Internal RC OSC Frequency vs. Temperature, VDD=5V
9
AC Electrical Characteristic
(Ta=25 °C, VDD=5V±5%, VSS=0V)
Symbol
Parameter
Conditions
Min
Dclk
Input CLK duty cycle
Tins
Instruction cycle time
(CLKS="0")
Ttcc
TCC input time period
Tdrh
Device reset hold time
Ta = 25°C
11.3
Trst
/RESET pulse width
Ta = 25°C
2000
Twdt
Watchdog timer duration
Ta = 25°C
11.3
Tset
Input pin setup time
Thold
Input pin hold time
Tdelay
Output pin delay time
ERC delay time
Tdrc
45
Type
Max
Unit
50
55
%
Crystal type
100
DC
ns
RC type
500
DC
ns
(Tins+20)/N*
ns
16.2
21.6
ms
ns
16.2
21.6
0
ms
ns
15
20
25
ns
Cload=20pF
45
50
55
ns
Ta = 25°C
1
3
5
ns
* N = selected prescaler ratio
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Product Specification (V0.98) 04.03.2006
Contents
10 Timing Diagrams
AC Test Input/Output Waveform
VDD-0.5V
0.75VDD
0.75VDD
0.25VDD
0.25VDD
TEST POINTS
GND+0.5V
AC Testing : Input is driven at VDD-0.5V for logic "1",and GND+0.5V for logic "0".Timing
measurements are made at 0.75VDD for logic "1",and 0.25VDD for logic "0".
RESET Timing (CLK="0")
NOP
Instruction 1
Executed
CLK
/RESET
Tdrh
TCC Input Timing (CLKS="0")
Tins
CLK
TCC
Ttcc
Product Specification (Draft 0.98) 04.03.2006
(This specification is subject to change without further notice)
• 101
Contents
APPENDIX
A Package Types
OTP MCU
Package Type
Pin Count
PH86P558P
DIP
28 pins
PH86P558M
SOP
28 pins
PH86P558K
Skinny DIP
32 pins
PH86P558Q
QFP
32 pins
B Quality Assurance and Reliability
Test Category
Test Conditions
Remarks
Solder temperature=255±5℃, for 5 seconds up to the
stopper using a rosin-type flux
Solderability
Step 1: TCT, 65℃ (15mins)~150℃ (15mins), 10 cycles
Step 2: Bake at 125℃, TD (endurance)=24 hrs
Step 3: Soak at 30°C/60%，TD (endurance)=192 hrs
Pre-condition
Step 4: IR flow 3 cycles
(Pkg thickness≧2.5mm or
Pkg volume≧350mm3 ----235±5℃)
For SMD IC (such as
SOP, QFP, SOJ, etc)
(Pkg thickness≦2.5mm or
Pkg volume≦350mm3 ----250±5℃ )
Temperature cycle test
-65℃ (15mins)~150℃ (15mins), 200 cycles
Pressure cooker test
TA =121℃, RH=100%, pressure=2 atm,
TD (endurance)= 96 hrs
High temperature /
High humidity test
TA=85℃ , RH=85%，TD (endurance)=168 , 500 hrs
High-temperature
storage life
TA=150℃, TD (endurance)=500, 1000 hrs
High-temperature
operating life
TA=125℃, VCC=Max. operating voltage,
TD (endurance) =168, 500, 1000 hrs
Latch-up
TA=25℃, VCC=Max. operating voltage, 600mA/40V
ESD (HBM)
TA=25℃, ≧∣± 4KV∣
IP_ND,OP_ND,IO_ND
IP_NS,OP_NS,IO_NS
IP_PD,OP_PD,IO_PD,
IP_PS,OP_PS,IO_PS,
ESD (MM)
TA=25℃, ≧∣± 400V∣
VDD-VSS(+),VDD_VSS
(-)mode
B.1 Address Trap Detect
An address trap detect is one of the MCU embedded fail-safe functions that detects MCU
malfunction caused by noise or the like. Whenever the MCU attempts to fetch an instruction
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Product Specification (V0.98) 04.03.2006
Contents
from a certain section of ROM, an internal recovery circuit is auto started. If a noise caused
address error is detected, the MCU will repeat execution of the program until the noise is
eliminated. The MCU will then continue to execute the next program.
Product Specification (Draft 0.98) 04.03.2006
(This specification is subject to change without further notice)
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