HD74LS75 Quadruple Bistable Latches REJ03D0416-0300 Rev.3.00 May 10, 2006 The HD74LS75 is ideally suited for use as temporary storage for binary information between processing units and input / output or indicator units. Information present at a data (D) input is transferred to the Q output when the enable (G) is high and the Q output will follow the data input as long as the enable remains high. When the enable goes low, the information (that was present at the data input at the time the transition occurred) is retained at the Q output until the enable is permitted to go high. This device features complementary Q and Q outputs from a 4-bit latch. Features • Ordering Information Part Name Package Type Package Code (Previous Code) Package Abbreviation Taping Abbreviation (Quantity) HD74LS75P DILP-16 pin PRDP0016AE-B (DP-16FV) P — HD74LS75FPEL SOP-16 pin (JEITA) PRSP0016DH-B (FP-16DAV) FP EL (2,000 pcs/reel) Note: Please consult the sales office for the above package availability. Pin Arrangement 1Q 1 Q 16 1Q 15 2Q 14 2Q 13 Enable 1-2 12 GND Q 1D 2 2D 3 Enable 3-4 4 Q Q VCC 5 Q Q 3D 6 G D 11 3Q 4D 7 G D 10 3Q 4Q 8 9 4Q Q G D G D Q (Top view) Rev.3.00, May 10, 2006, page 1 of 5 HD74LS75 Function Table Inputs Outputs D L H X G H H L Q H L Q0 Q L H Q0 H; high level, L; low level, X; irrelevant Q0; level of Q before the indicated steady-state input conditions were established. Q0; complement of Q0 or level of Q0 before the indicated steady-state input conditions were established. Circuit Schematic (1/4) Q Data Q To Other Latch Enable Absolute Maximum Ratings Item Symbol Ratings Supply voltage VCC 7 Input voltage VIN 7 Power dissipation PT 400 Storage temperature Tstg –65 to +150 Note: Voltage value, unless otherwise noted, are with respect to network ground terminal. Unit V V mW °C Recommended Operating Conditions Item Supply voltage Output current Operating temperature Pulse width Setup time Hold time Rev.3.00, May 10, 2006, page 2 of 5 Symbol VCC IOH IOL Topr tw tsu th Min 4.75 — — –20 20 15 5 Typ 5.00 — — 25 — — — Max 5.25 –400 8 75 — — — Unit V µA mA °C ns ns ns HD74LS75 Electrical Characteristics (Ta = –20 to +75 °C) Item Input voltage Symbol VIH VIL min. 2.0 — typ.* — — max. — 0.8 Unit V V VOH 2.7 — — V — — — — — — — — — — — — — — — — 0.4 0.5 20 80 –0.4 –1.6 0.1 0.4 Output voltage VOL Input current D input G input D input G input D input G input IIH IIL II V Condition VCC = 4.75 V, VIH = 2 V, VIL = 0.8 V, IOH = –400 µA IOL = 4 mA VCC = 4.75 V, VIH = 2 V, VIL = 0.8 V IOL = 8 mA µA VCC = 5.25 V, VI = 2.7 V mA VCC = 5.25 V, VI = 0.4 V mA VCC = 5.25 V, VI = 7 V Short-circuit output –20 — –100 mA IOS current Supply current** ICC — 6.3 12 mA Input clamp voltage VIK — — –1.5 V Notes: * VCC = 5 V, Ta = 25°C ** ICC is measured with all outputs open and all inputs grounded. VCC = 5.25 V VCC = 5.25 V VCC = 4.75 V, IIN = –18 mA Switching Characteristics (VCC = 5 V, Ta = 25°C) Item Propagation delay time Symbol tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL Rev.3.00, May 10, 2006, page 3 of 5 Inputs Outputs D Q D Q G Q G Q min. — — — — — — — — typ. 15 9 12 7 15 14 16 7 max. 27 17 20 15 27 25 30 15 Unit Condition ns ns ns ns CL = 15 pF, RL = 2 kΩ HD74LS75 Testing Method Test Circuit Q Q VCC D G RL P.G. Zout = 50Ω D G Q Q P.G. Zout = 50Ω Notes: RL CL CL 1. Test is put into the each flip-flop. 2. CL includes probe and jig capacitance. 3. All diodes are 1S2074(H). Waveform 1µs tTLH D 90% 1.3 V 1µs tTHL 3V 90% 1.3 V 10% 1.3 V 10% tsu th tTLH tTHL tsu 500ns tPLH tPLH th 3V 90% 90% 1.3 V 1.3 V 10% 10% G 0V 1.3 V 1.3 V 0V 500ns tPHL tPHL VOH Q 1.3 V 1.3 V VOL tPLH VOH tPLH Q 1.3 V tPHL 1.3 V VOL tPHL Notes: 1. Input pulse; D input: PRR = 500 kHz, G input; PRR = 1 MHz, tTHL ≤ 10 ns,tTLH ≤ 10 ns. 2. When measuring propugation delay times from the D input, the corresponding G input must be held high. Rev.3.00, May 10, 2006, page 4 of 5 HD74LS75 Package Dimensions JEITA Package Code P-DIP16-6.3x19.2-2.54 RENESAS Code PRDP0016AE-B Previous Code DP-16FV MASS[Typ.] 1.05g D 9 E 16 1 8 b3 0.89 A1 A Z L Reference Symbol θ bp e e1 D E A A1 bp b3 c θ e Z L c e1 ( Ni/Pd/Au plating ) JEITA Package Code P-SOP16-5.5x10.06-1.27 RENESAS Code PRSP0016DH-B *1 Previous Code FP-16DAV Dimension in Millimeters Min Nom Max 7.62 19.2 20.32 6.3 7.4 5.06 0.51 0.40 0.48 0.56 1.30 0.19 0.25 0.31 0° 15° 2.29 2.54 2.79 1.12 2.54 MASS[Typ.] 0.24g D F 16 NOTE) 1. DIMENSIONS"*1 (Nom)"AND"*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET. 9 c HE *2 E bp Index mark Terminal cross section ( Ni/Pd/Au plating ) 1 Z 8 e *3 bp x Reference Dimension in Millimeters Symbol M A L1 A1 θ y L Detail F Rev.3.00, May 10, 2006, page 5 of 5 D E A2 A1 A bp b1 c c1 θ HE e x y Z L L1 Min Nom Max 10.06 10.5 5.50 0.00 0.10 0.20 2.20 0.34 0.40 0.46 0.15 0.20 0.25 0° 8° 7.50 7.80 8.00 1.27 0.12 0.15 0.80 0.50 0.70 0.90 1.15 Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. 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