To all our customers Regarding the change of names mentioned in the document, such as Mitsubishi Electric and Mitsubishi XX, to Renesas Technology Corp. The semiconductor operations of Hitachi and Mitsubishi Electric were transferred to Renesas Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.) Accordingly, although Mitsubishi Electric, Mitsubishi Electric Corporation, Mitsubishi Semiconductors, and other Mitsubishi brand names are mentioned in the document, these names have in fact all been changed to Renesas Technology Corp. Thank you for your understanding. Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been made to the contents of the document, and these changes do not constitute any alteration to the contents of the document itself. Note : Mitsubishi Electric will continue the business operations of high frequency & optical devices and power devices. Renesas Technology Corp. Customer Support Dept. April 1, 2003 MITSUBISHI MICROCOMPUTERS 7477/7478 GROUP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER DESCRIPTION The 7477/7478 group is the single-chip microcomputer designed with CMOS silicon gate technology. The single-chip microcomputer is useful for business equipment and other consumer applications. In addition to its simple instruction set, the ROM, RAM, and I/O addresses are placed on the same memory map to enable easy programming. In addition, built-in PROM type microcomputers with built-in electrically writable PROM, and additional functions equivalent to the mask ROM version are also available. 7477/7478 group products are shown noted below. The 7477 and the 7478 differ in the number of I/O por ts, package outline, and clock generating circuit only. Product M37477M4-XXXSP/FP M37477M8-XXXSP/FP M37477E8SP/FP M37477E8-XXXSP/FP M37478M4-XXXSP/FP M37478M8-XXXSP/FP M37478E8SP/FP M37478E8-XXXSP/FP M37478E8SS Version Mask ROM version One Time PROM version (Built-in PROM type microcomputers) Mask ROM version One Time PROM version (Built-in PROM type microcomputers) PROM version (Built-in PROM type microcomputer) M37477M2TXXXSP/FP* M37477M4TXXXSP/FP* Mask ROM version M37477M8TXXXSP/FP* One Time PROM version M37477E8TXXXSP/FP* (Built-in PROM type microcomputers) M37478M2TXXXSP/FP* M37478M4TXXXSP/FP* Mask ROM version M37478M8TXXXSP/FP* One Time PROM version M37478E8TXXXSP/FP* (Built-in PROM type microcomputers) * : Extended operating temperature version FEATURES ●Basic machine-language instructions ...................................... 71 ●Memory size ROM ................. 16384 bytes (M37477M8/E8, M37478M8/E8) RAM ..................... 384 bytes (M37477M8/E8, M37478M8/E8) ●The minimum instruction execution time ...................................... 0.5µs (at 8MHz oscillation frequency) ●Power source voltage .......... 2.7 to 4.5V (at 2.2VCC – 2.0MHz oscillation frequency) ............................. 4.5 to 5.5V (at 8MHz oscillation frequency) ●Power dissipation in normal mode .................................... 35mW (at 8MHz oscillation frequency) ●Subroutine nesting ................... 192 levels max. (M37477M8/E8, M37478M8/E8) ●Interrupt .................................................... 13 sources, 11 vectors ●8-bit timers ................................................................................. 4 ●Programmable I/O ports (Ports P0, P1, P4) .......................................... 18 (7477 group) 20 (7478 group) ●Input ports (Ports P2, P3) .................................... 8 (7477 group) (Ports P2, P3, P5) ............................16 (7478 group) ●8-bit serial I/O ........................... 1 (UART or clock-synchronized) ●8-bit A-D converter ................................ 4 channels (7477 group) 8 channels (7478 group) APPLICATIONS Audio-visual equipment, VCR, Tuner, Office automation equipment Extended operating temperature range version ……………………………………………… Automotive controls MITSUBISHI MICROCOMPUTERS 7477/7478 GROUP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER PIN CONFIGURATION (TOP VIEW) 1 32 2 31 3 30 4 29 5 28 7 8 9 10 11 12 27 26 25 24 23 22 21 13 20 14 19 15 18 16 17 Outline 32P4B (Note 1) P07 P06 P05 P04 P03 P02 P01 P00 P41 P40 P33/CNTR 1 P32/CNTR 0 P31/INT1 P30/INT0 RESET VCC P17/SRDY P16/SCLK P15/TXD P14/RXD P13/T1 P12/T0 P11 P10 P23/IN3 P22/IN2 P21/IN1 P20/IN0 VREF XIN XOUT VSS 1 32 2 31 3 30 4 29 5 28 6 7 8 9 10 11 12 M37477M4-XXXFP M37477M8-XXXFP M37477E8-XXXFP 6 M37477M4-XXXSP M37477M8-XXXSP M37477E8-XXXSP P17/SRDY P16/SCLK P15/TXD P14/RXD P13/T1 P12/T0 P11 P10 P23/IN3 P22/IN2 P21/IN1 P20/IN0 VREF XIN XOUT VSS 27 26 25 24 23 22 21 13 20 14 19 15 18 16 17 P07 P06 P05 P04 P03 P02 P01 P00 P41 P40 P33/CNTR 1 P32/CNTR 0 P31/INT1 P30/INT0 RESET VCC Outline 32P2W-A (Note 2) Notes 1 : The M37477M2TXXXSP, M37477M4TXXXSP, M37477M8TXXXSP and M37477E8TXXXSP are included in the 32P4B package. These products are pin- compatible. 2 : The M37477M2TXXXFP, M37477M4TXXXFP, M37477M8TXXXFP and M37477E8TXXXFP are included in the 32P2W-A package. These products are pin-compatible. 3 : The only differences between the 32P4B package product and the 32P2W-A package product are package shape and absolute maximum ratings. 2 MITSUBISHI MICROCOMPUTERS 7477/7478 GROUP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER 17 26 18 25 RESET 19 24 20 23 21 22 P51/XCOUT P50/XCIN VCC Outline 42P4B (Note 1) 42S1B-A (Window) 29 31 30 33 32 35 34 37 36 39 38 41 40 19 55 18 56 17 23 22 16 27 20 54 51 24 14 28 16 53 50 15 15 21 P17/SRDY P16/SCLK P15/TXD NC 25 M37478M4-XXXFP M37478M8-XXXFP M37478E8-XXXFP 49 12 29 52 48 13 30 NC P51/XCOUT P50/XCIN NC VCC VSS AVSS NC XOUT XIN NC 10 14 31 26 11 13 32 47 9 12 33 RESET 27 8 11 34 28 46 7 9 10 35 45 6 8 NC P05 P06 P07 P52 NC VSS P53 5 36 42 37 7 4 38 6 3 39 5 43 40 4 44 3 P52 P07 P06 P05 P04 P03 P02 P01 P00 P43 P42 P41 P40 P33/CNTR 1 P32/CNTR 0 P31/INT 1 P30/INT 0 1 41 2 42 2 NC P14/RXD P13/T1 P12/T0 P11 P10 P27/IN7 P26/IN6 P25/IN5 P24/IN4 P23/IN3 P22/IN2 P21/IN1 P20/IN0 VREF NC 1 M37478M4-XXXSP M37478M8-XXXSP M37478E8-XXXSP M37478E8SS P53 P17/SRDY P16/SCLK P15/TXD P14/RXD P13/T1 P12/T0 P11 P10 P27/IN7 P26/IN6 P25/IN5 P24/IN4 P23/IN3 P22/IN2 P21/IN1 P20/IN0 VREF XIN XOUT VSS NC P04 P03 P02 P01 P00 P43 P42 P41 P40 NC P33/CNTR1 P32/CNTR 0 P31/INT1 P30/INT0 NC PIN CONFIGURATION (TOP VIEW) Outline 56P6N-A (Note 2) NC: No connection Notes 1 : The M37478M2TXXXSP, M37478M4TXXXSP, M37478M8TXXXSP and M37478E8TXXXSP are included in the 42P4B package. These products are pin- compatible. 2 : The M37478M2TXXXFP, M37478M4TXXXFP, M37478M8TXXXFP and M37478E8TXXXFP are included in the 56P6N-A package. These products are pin-compatible. 3 : The only differences between the 42P4B package product and the 56P6N-A package product are package shape, absolute maximum ratings and the fact that the 56P6N-A package product has an AV SS pin. 3 4 I/O port P4 13 VREF 4 (Note 1) 9 10 11 12 P2(4) Stack pointer S(8) 16384 bytes (P)ROM Input port P3 Reference voltage input Input port P2 22 21 20 19 24 23 Index register Y(8) Program counter PCL (8) A-D converter INT0 INT1 P3(4) CNTR0 Index register X(8) P4(2) CNTR1 Processor status register PS(8) 384 bytes RAM Program counter PCH(8) 16 17 (Note 2) VSS VCC S I/O(8) Data bus Notes 1 : 8192 bytes for M37477M4-XXXSP/FP and M37477M4TXXXSP/FP, 4096 bytes for M37477M2TXXXSP/FP 2 : 192 bytes for M37477M4-XXXSP/FP and M37477M4TXXXSP/FP, 128 bytes for M37477M2TXXXSP/FP 8-bit Arithmetic and logical unit Accumulator A(8) 18 Clock generating circuit RESET 15 14 Reset input Clock output X OUT Clock input XIN M37477M8/E8-XXXSP/FP, M37477M8/E8TXXXSP/FP BLOCK DIAGRAM 1 2 4 5 6 I/O port P1 3 P1(8) Timer 4(8) Timer 3(8) Timer 2(8) Timer 1(8) 7 8 PWM control I/O port P0 32 31 30 29 28 27 26 25 P0(8) Control signal Instruction decoder Instruction register(8) MITSUBISHI MICROCOMPUTERS 7477/7478 GROUP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER 20 33 32 31 30 I/O port P4 1 42 24 23 Input port P5 384 bytes RAM Input port P3 Reference voltage input Input port P2 10 11 12 13 14 15 16 17 18 VREF 29 28 27 26 8 Stack pointer S(8) 16384 bytes (P)ROM P2(8) INT0 A-D converter Index register Y(8) Program counter PCL(8) (Note 1) S I/O(8) Data bus P3(4) CNTR0 INT1 Index register X(8) Program counter PCH(8) 21 VSS Notes 1 : 8192 bytes for M37478M4-XXXSP, M37478M4TXXXSP and 4096 bytes for M37478M2TXXXSP 2 : 192 bytes for M37478M4-XXXSP, M37478M4TXXXSP and 128 bytes for M37478M2TXXXSP P4(4) 22 VCC (Note 2) Processor status register PS(8) CNTR1 25 RESET Reset input P5(4) XCIN XCOUT Accumulator A(8) XCOUT Sub-clock output 8-bit Arithmetic and logical unit XCIN Sub-clock input Clock generating circuit 19 Main clock Main clock output input XOUT XIN 2 3 5 6 7 I/O port P1 4 P1(8) Timer 4(8) Timer 3(8) Timer 2(8) Timer 1(8) M37478M8/E8-XXXSP, M37478M8/E8TXXXSP, M37478E8SS BLOCK DIAGRAM 8 9 PWM control I/O port P0 41 40 39 38 37 36 35 34 P0(8) Control signal Instruction decoder Instruction register(8) MITSUBISHI MICROCOMPUTERS 7477/7478 GROUP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER 5 6 19 I/O port P4 Input port P5 384 bytes P3(4) Index register Y(8) 15 7 8 (Note 1) S I/O(8) Data bus 9 10 11 12 13 14 P2(8) Stack pointer S(8) 16384 bytes (P)ROM Input port P3 Reference voltage input Input port P2 VREF 8 A-D converter INT0 INT1 33 32 31 30 CNTR0 Index register X(8) Program counter PCL(8) 21 Program counter PCH(8) AVSS VSS 22 51 Notes 1 : 8192 bytes for M37478M4-XXXFP, M37478M4TXXXFP and 4096 bytes for M37478M2TXXXFP 2 : 192 bytes for M37478M4-XXXFP, M37478M4TXXXFP and 128 bytes for M37478M2TXXXFP 38 37 36 35 52 49 26 25 23 VCC (Note 2) RAM Processor status register PS(8) CNTR1 P4(4) Accumulator A(8) 28 RESET Reset input P5(4) XCIN XCOUT 8-bit Arithmetic and logical unit XCIN Sub-clock input XCOUT Sub-clock output Clock generating circuit 18 Main clock Main clock output input XOUT XIN M37478M8/E8-XXXFP, M37478M8/E8TXXXFP BLOCK DIAGRAM 3 4 I/O port P1 53 54 55 2 P1(8) Timer 4(8) Timer 3(8) Timer 2(8) Timer 1(8) 5 6 PWM control I/O port P0 48 47 46 43 42 41 40 39 P0(8) Control signal Instruction decoder Instruction register(8) MITSUBISHI MICROCOMPUTERS 7477/7478 GROUP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS 7477/7478 GROUP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER FUNCTIONS OF 7477/7478 GROUP Parameter Functions Basic machine-language instructions 71 Instruction execution time 0.5µs (The minimum instructions, at 8 MHz oscillation frequency) Clock input oscillation frequency Memory size Input/Output port 8 MHz (max.) M37477M2T ROM 4096 bytes M37478M2T RAM 128 bytes M37477M4 ROM 8192 bytes M37478M4 RAM 192 bytes M37477M8/E8 (P)ROM 16384 bytes M37478M8/E8 RAM 384 bytes P0, P1 I/O 8-bit ✕ 2 P2 Input 8-bit ✕ 1 (4-bit ✕ 1 for the 7477 group) P3, P5 Input 4-bit ✕ 2 (Port P5 is not included in the 7477 group) P4 I/O 4-bit ✕ 1 (2-bit ✕ 1 for the 7477 group) Serial I/O 8-bit ✕ 1 Timers 8-bit timer ✕ 4 A-D converter 8-bit ✕ 1 (8 channels) (8-bit ✕ 1 (4 channels) for the 7477 group) Subroutine nesting M37477M2T, M37478M2T 64 (max.) M37477M4, M37478M4 96 (max.) M37477M8/E8, M37478M8/E8 192 (max.) Interrupt 5 external interrupts, 7 internal interrupts, 1 software interrupt Clock generating circuit Built-in circuit with internal feedback resistor (a ceramic or a quartzcrystal oscillator) Power source voltage 2.7 to 4.5V (at 2.2VCC–2.0MHz oscillation frequency), 4.5 to 5.5V (at 8MHz oscillation frequency) Power dissipation 35mW (at 8MHz oscillation frequency) Input/Output characters Input/Output voltage 5V Output current –5 to 10mA (P0, P1, P4 : CMOS tri-states) Operating temperature range –20 to 85°C (–40 to 85°C for extended operating temperature version) Device structure CMOS silicon gate M37477M4/M8/E8-XXXSP, M37477M2/M4/M8/E8TXXXSP M37477M4/M8/E8-XXXFP, M37477M2/M4/M8/E8TXXXFP Package M37478M4/M8/E8-XXXSP, M37478M2/M4/M8/E8TXXXSP M37478M4/M8/E8-XXXFP, M37478M2/M4/M8/E8TXXXFP M37478E8SS 32-pin shrink plastic molded DIP 32-pin plastic molded SOP 42-pin shrink plastic molded DIP 56-pin plastic molded QFP 42-pin ceramic DIP 7 MITSUBISHI MICROCOMPUTERS 7477/7478 GROUP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER PIN DESCRIPTION Input/ Output Pin Name Functions VCC, VSS Power source Apply voltage of 2.7 to 5.5V to VCC, and 0V to V SS. AVSS (Note 1) Analog power source Ground level input pin for A-D converter. Same voltage as VSS is applied. RESET Reset input Input To enter the reset state, the reset input pin must be kept at “L” for 2µs or more (under normal VCC conditions). XIN Clock input Input XOUT Clock output Output These are I/O pins of internal clock generating circuit for main clock. To control generating frequency, an external ceramic or a quartz crystal oscillator is connected between the XIN and X OUT pins. If an external clock is used, the clock source should be connected the XIN pin and the XOUT pin should be left open. Feedback resistor is connected between XIN and XOUT . VREF Reference voltage input Input Reference voltage input pin for A-D converter. P00 – P07 I/O port P0 I/O Port P0 is an 8-bit I/O port. The output structure is CMOS output. When this port is selected for input, pull-up transistor can be connected in units of 1-bit and a key on wake up function is provided. P10 – P17 I/O port P1 I/O Port P1 is an 8-bit I/O port. The output structure is CMOS output. When this port is selected for input, pull-up transistor can be connected in units of 4-bit. P1 2 and P13 are in common with timer output pins T0 and T1 . P14, ____ P15, P1 6 and P1 7 are in common with serial I/O pins R XD, TXD, SCLK and SRDY, respectively. P20 – P27 (Note 2) Input port P2 Input Port P2 is an 8-bit input port. This port is in common with analog input pins IN 0 to IN7 . P30 – P33 Input port P3 Input Port P3 is a 4-bit input port. P30, P31 are in common with external interrupt input pins INT0, INT1 , and P32, P33 are in common with timer input pins CNTR0, CNTR1 . P40 – P43 (Note 3) I/O port P4 I/O Port P4 is a 4-bit I/O port. The output structure is CMOS output, When this port is selected for input, pull-up transistor can be connected in units of 4-bit. P50 – P53 (Note 4) Input port P5 Input Port P5 is a 4-bit input port and pull-up transistor can be connected in units of 4-bit. P50, P51 are in common with input/output pins of clock for clock function XCIN , XCOUT. When P50, P51 are used as XCIN , XCOUT, connect a ceramic or a quartz crystal oscillator between XCIN and XCOUT. If an external clock input is used, connect the clock input to the XCIN pin and open the XCOUT pin. Feedback resistor is connected between XCIN and XCOUT pins. Notes 1 : AVSS for M37478M4/M8/E8-XXXFP and M37478M2/M4/M8/E8TXXXFP. 2 : Only P2 0–P23 (IN 0–IN3 ) 4-bit for the 7477 group. 3 : Only P4 0 and P41 2-bit for the 7477 group. 4 : This port is not included in the 7477 group. 8 MITSUBISHI MICROCOMPUTERS 7477/7478 GROUP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER FUNCTIONAL DESCRIPTION Central Processing Unit (CPU) CPU Mode Register The 7477/7478 group uses the standard 740 family instruction set. Refer to the table of 740 family addressing modes and machine instructions or the SERIES 740 <Software> User’s Manual for details on the instruction set. Machine-resident 740 family instructions are as follows: The FST and SLW instruction cannot be used. The MUL, DIV, WIT, and STP instruction can be used. b7 The CPU mode register is allocated at address 00FB16 . This register contains the stack page selection bit. b0 CPU mode register (Address 00FB 16) These bits must always be set to “0”. Stack page selection bit (Note 1) 0 : In page 0 area 1 : In page 1 area P50, P51/X CIN, XCOUT selection bit (Note 2) 0 : P5 0, P51 1 : X CIN, XCOUT XCOUT drive capacity selection bit (Note 2) 0 : Low 1 : High Clock (X IN-XOUT) stop bit (Note 2) 0 : Oscillates 1 : Stops Internal system clock selection bit (Note 2) 0 : X IN-XOUT selected (normal mode) 1 : X CIN-XCOUT selected (low-speed mode) Notes 1 : In the M37477M4-XXXSP/FP, M37477M2/M4TXXXSP/FP, set this bit to “0”. In the M37478M4-XXXSP/FP, M37478M2/M4TXXXSP/FP, set this bit to “0”. 2 : In the 7477 group, set this bit to “0”. Fig. 1 Structure of CPU mode register 9 MITSUBISHI MICROCOMPUTERS 7477/7478 GROUP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MEMORY • Special Function Register (SFR) Area The special function register (SFR) area contains the registers relating to functions such as I/O ports and timers. • RAM RAM is used for data storage as well as a stack area. • ROM ROM is used for storing user programs as well as the interrupt vector area. • Interrupt Vector Area The interrupt vector area is for storing jump destination addresses used at reset or when an interrupt is generated. • Zero Page Zero page addressing mode is useful because it enables access to this area with fewer instruction cycles. • Special Page Special page addressing mode is useful because it enables access to this area with fewer instruction cycles. 000016 RAM (192 bytes) for M37477M4 M37477M8/E8 M37478M4 M37478M8/E8 RAM (128 bytes) for M37477M2T M37478M2T 007F16 Zero page 00BF 16 RAM (192 bytes) for M37477M8/E8 M37478M8/E8 00FF16 010016 SFR area 01BF 16 Not used C000 16 E00016 ROM (16384 bytes) for M37477M8/E8 M37478M8/E8 ROM (8192 bytes) for M37477M4 M37478M4 F00016 ROM (4096 bytes) for M37477M2T M37478M2T FF0016 Special page FFE8 16 Interrupt vector area FFFF 16 Fig. 2 Memory map 10 MITSUBISHI MICROCOMPUTERS 7477/7478 GROUP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER 00C016 Port P0 00E016 Transmit/receive buffer register 00C116 Port P0 direction register 00E116 Serial I/O status register 00C216 Port P1 00E216 Serial I/O control register 00C316 Port P1 direction register 00E316 UART control register 00C416 Port P2 00E416 Baud rate generator 00E516 00C516 00C616 Port P3 00E616 00E716 00C716 00C816 Port P4 00E816 00C916 Port P4 direction register 00E916 00CA16 Port P5 (Note 1) 00EA16 00CB16 00EB16 00CC16 00EC16 00CD16 00ED16 00CE16 00EE16 00EF16 00CF16 00D016 P0 pull-up control register 00F016 Timer 1 00D116 P1–P5 pull-up control register (Note 2) 00F116 Timer 2 00D216 00F216 Timer 3 00D316 00F316 Timer 4 00D416 Edge polarity selection register 00D516 00D616 00F416 00F516 Input latch register 00F616 00D716 00F716 Timer FF register 00D816 00F816 Timer 12 mode register 00D916 A-D control register 00F916 Timer 34 mode register 00DA16 A-D conversion register 00FA16 Timer mode register 2 00DB16 00FB16 CPU mode register 00DC16 00FC16 Interrupt request register 1 00DD16 00FD16 Interrupt request register 2 00DE16 00FE16 Interrupt control register 1 00DF16 00FF16 Interrupt control register 2 Notes 1 : This address is not used in the 7477 group. 2 : This address is allocated P1–P4 pull-up control register for the 7477 group. Fig. 3 SFR (Special Function Register) memory map 11 MITSUBISHI MICROCOMPUTERS 7477/7478 GROUP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER INTERRUPTS Interrupts can be caused by 13 different sources consisting of five external, seven internal, and one software sources. Interrupts are vectored interrupts with priorities shown in Table 1. Reset is also included in the table because its operation is similar to an interrupt. When an interrupt is accepted, the registers are pushed, interrupt disable flag I is set, and the program jumps to the address specified in the vector table. The interrupt request bit is cleared automatically. The reset and BRK instruction interrupt can never be disabled. Other interrupts are disabled when the interrupt disable flag is set. All interrupts except the BRK instruction interrupt have an interrupt request bit and an interrupt enable bit. The interrupt request bits are in interrupt request registers 1 and 2 and the interrupt enable bits are in interrupt control registers 1 and 2. External interrupts INT0 and INT1 can be asserted on either the falling or rising edge as set in the edge polarity selection register. When “0” is set to this register, the interrupt is activated on the falling edge; when “1” is set to the register, the interrupt is activated on the rising edge. When the device is put into power-down state by the STP instruction or the WIT instruction, if bit 5 in the edge polarity selection register is “1”, the INT1 interrupt becomes a key on wake up interrupt. When a key on wake up interrupt is valid, an interrupt request is generated by applying the “L” level to any pin in port P0. In this case , the port used for interrupt must have been set for the input mode. If bit 5 in the edge polarity selection register is “0” when the device is in power-down state, the INT 1 interrupt is selected. Also, if bit 5 in the edge polarity selection register is set to “1” when the device is not in a power-down state, neither key on wake up interrupt request nor INT1 interrupt request is generated. The CNTR0/CNTR 1 interrupts function in the same as INT 0 and INT1 . The interrupt input pin can be specified for either CNTR0 or CNTR1 pin by setting bit 4 in the edge polarity selection register. Figure 4 shows the structure of the edge polarity selection register, interrupt request registers 1 and 2, and interrupt control registers 1 and 2. Interrupts other than the BRK instruction interrupt and reset are accepted when the interrupt enable bit is “1”, interrupt request bit is “1”, and the interrupt disable flag is “0”. The interrupt request bit can be reset with a program, but not set. The interrupt enable bit can be set and reset with a program. Reset is treated as a non-maskable interrupt with the highest priority. Figure 5 shows interrupts control. Table 1. Interrupt vector address and priority. Priority Vector addresses RESET Interrupt source 1 FFFF16 , FFFE 16 Non-maskable Remarks INT 0 interrupt 2 FFFD16 , FFFC 16 External interrupt (polarity programmable) INT 1 interrupt or key on wake up interrupt 3 FFFB16 , FFFA16 External interrupt (INT1 is polarity programmable) CNTR 0 interrupt or CNTR1 interrupt 4 FFF916, FFF816 External interrupt (polarity programmable) Timer 1 interrupt 5 FFF716, FFF616 Timer 2 interrupt 6 FFF516, FFF416 Timer 3 interrupt 7 FFF316, FFF216 Timer 4 interrupt 8 FFF116, FFF016 Serial I/O receive interrupt 9 FFEF16 , FFEE 16 Serial I/O transmit interrupt 10 FFED16 , FFEC16 A-D conversion completion interrupt 11 FFEB16 , FFEA 16 BRK instruction interrupt 12 FFE916 , FFE816 ______ 12 Non-maskable software interrupt MITSUBISHI MICROCOMPUTERS 7477/7478 GROUP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER b7 b0 Edge polarity selection register (EG) (Address 00D4 16) INT0 edge selection bit INT1 edge selection bit CNTR0 edge selection bit CNTR1 edge selection bit 0 : Falling edge 1 : Rising edge CNTR0/CNTR1 interrupt selection bit 0 : CNTR0 1 : CNTR1 INT1 source selection bit (at power-down state) 0 : P31/INT1 1 : P00 – P07 “L” level (for key-on wake-up) Nothing is allocated (The value is undefined at reading) b7 b0 b7 b0 Interrupt request register 1 (Address 00FC 16) Interrupt request register 2 (Address 00FD 16) Timer 1 interrupt request bit Timer 2 interrupt request bit Timer 3 interrupt request bit Timer 4 interrupt request bit Nothing is allocated (The value is undefined at reading) INT0 interrupt request bit INT1 interrupt request bit CNTR0 or CNTR1 interrupt request bit 0 : No interrupt request 1 : Interrupt requested Nothing is allocated (The value is undefined at reading) Serial I/O receive interrupt request bit Serial I/O transmit interrupt request bit A-D conversion completion interrupt request bit b7 b0 b7 Interrupt control register 1 (Address 00FE 16) Timer 1 interrupt enable bit Timer 2 interrupt enable bit Timer 3 interrupt enable bit Timer 4 interrupt enable bit Nothing is allocated (The value is undefined at reading) Serial I/O receive interrupt enable bit Serial I/O transmit interrupt enable bit A-D conversion completion interrupt enable bit b0 Interrupt control register 2 (Address 00FF 16) INT0 interrupt enable bit INT1 interrupt enable bit CNTR0 or CNTR1 interrupt enable bit 0 : Interrupt disable 1 : Interrupt enabled Nothing is allocated (The value is undefined at reading) Fig. 4 Structure of registers related to interrupt Interrupt request bit Interrupt enable bit Interrupt request Interrupt disable flag I BRK instruction Reset Fig. 5 Interrupt control 13 MITSUBISHI MICROCOMPUTERS 7477/7478 GROUP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER TIMER The 7477/7478 group has four timers; timer 1, timer 2, timer 3, and timer 4. A block diagram of timer 1 through 4 is shown in Figure 6. Timer 1 can be operated in the timer mode, event count mode, or pulse output mode. Timer 1 starts counting when bit 0 in the timer 12 mode register (address 00F816 ) is set to “0”. The count source can be selected from the f(X IN) divided by 16, f(XCIN ) divided by 16, f(XCIN ), or event input from P32/CNTR0 pin. Do not select f(XCIN ) as the count source in the 7477 group. When bit 1 and bit 2 in the timer 12 mode register are “0”, f(X IN) divided by 16 or f(X CIN) divided by 16 is selected. Selection between f(XIN ) and f(XCIN) is done by bit 7 in the CPU mode register (address 00FB16 ). When bit 1 in the timer 12 mode register is “0” and bit 2 is “1”, f(XCIN ) is selected. And, when bit 1 in the timer 12 mode register is “1”, an event input from the CNTR 0 pin is selected. Event inputs are selected depending on bit 2 in the edge polarity selection register (address 00D416 ). When this bit is “0”, the inverted value of CNTR 0 input is selected; when the bit is “1”, CNTR0 input is selected. When bit 3 in the timer 12 mode register is set to “1”, the P12 pin becomes timer output T0. When the direction register of P12 is set for the output mode at this time, the timer 1 overflow divided by 2 is output from T0 . Please set the initial output value in the following procedure. ➀ Set “1” to bit 0 of the timer 12 mode register. (Timer 1 count stop.) ➁ Set “1” to bit 0 of the timer mode register 2. ➂ Set the output value to bit 0 of the timer FF register. ➃ Set the count value to the timer 1. ➄ Set “0” to bit 0 of the timer 12 mode register. (Timer 1 count start.) Timer 2 can only be operated in the timer mode. Timer 2 starts counting when bit 4 in the timer 12 mode register is set to “0”. The count source can be selected from the divide by 16, divide by 64, divide by 128, or divide by 256 frequency of f(XIN ) or f(XCIN ), and timer 1 overflow. Do not select f(XCIN ) as the count source in the 7477 group. When bit 5 in the timer 12 mode register is “0”, any of the divide by 16, divide by 64, divide by 128, or divide by 256 frequency of f(XIN ) or f(XCIN) is selected. The divide ratio is selected according to bit 6 and bit 7 in the timer 12 mode register, and selection between f(XIN) and f(XCIN) is made according to bit 7 in the CPU mode register. When bit 5 in the timer 12 mode register is “1”, timer 1 overflow is selected as the count source. Timer 3 can be operated in the timer mode, event count mode, or PWM mode. Timer 3 starts counting when bit 0 in the timer 34 mode register (address 00F916) is set to “0”. The count source can be selected from the f(X IN) divided by 16, f(X CIN) divided by 16, f(XCIN), timer 1 or timer 2 overflow, or an event input from P3 3/CNTR1 pins according to the statuses of bit 1 and bit 2 in the timer 34 mode register, bit 6 in the timer mode register 2 (address 00FA16) and bit 7 in the CPU mode register. Do not select f(XCIN) as the count source in the 7477 group. Note, however, that if timer 1 overflow or timer 2 overflow is selected for the count source of timer 3 when timer 1 overflow is selected for the count source of timer 2, timer 1 overflow is always selected regardless of the status of bit 6 in the timer mode register 2. Event inputs are selected depending on bit 3 in the edge polarity selection register. When this bit is “0”, the inverted value of CNTR1 input 14 is selected; when the bit is “1”, CNTR1 input is selected. Timer 4 can be operated in the timer mode, event count mode, pulse output mode, pulse width measuring mode, or PWM mode. Timer 4 starts counting when bit 3 in the timer 34 mode register is set to “0” when bit 6 in this register is “0”. When bit 6 is “1”, the pulse width measuring mode is selected. The count source can be selected from timer 3 overflow, f(XIN) divided by 16, f(XCIN ) divided by 16, f(XCIN), timer 1 or timer 2 overflow, or an event input from P33/CNTR 1 pin according to the statuses of bit 4 and bit 5 in the timer 34 mode register, bit 6 in the timer mode register 2, and bit 7 in the CPU mode register. Do not select f(X CIN ) as the count source in the 7477 group. Note, however, that if timer 1 overflow or timer 2 overflow is selected for the count source of timer 4 when timer 1 overflow is selected for the count source of timer 2, timer 1 overflow is always selected regardless of the status of bit 6 in the timer mode register 2. Event inputs are selected depending on bit 3 in the edge polarity selection register. When this bit is “0”, the inverted value of CNTR1 input is selected; when the bit is “1”, CNTR1 input is selected. When bit 7 in the timer 34 mode register is set to “1”, the P13 pin becomes timer output T1 . When the direction register of P1 3 is set for the output mode at this time, the timer 4 overflow divided by 2 is output from T1 when bit 7 in the timer mode register 2 is “0”. Please set the initial output value in the following procedure. ➀ Set “1” to bit 3 of the timer 34 mode register. (Timer 4 count stop.) ➁ Set “1” to bit 1 of the timer mode register 2. ➂ Set the output value to bit 1 of the timer FF register. ➃ Set the count value to the timer 4. ➄ Set “0” to bit 3 of the timer 34 mode register. (Timer 4 count start.) (1) Timer mode Timer performs down count operations with the dividing ratio being 1/(n+1). Writing a value to the timer latch sets a value to the timer. When the value to be set to the timer latch is nn16 , the value to be set to a timer is nn16, which is down counted at the falling edge of the count source from nn16 to (nn16-1) to (nn16-2) to ...0116 to 00 16 to FF16 . At the falling edge of the count source immediately after timer value has reached FF 16, value (nn16 -1) obtained by subtracting one from the timer latch value is set (reloaded) to the timer to continue counting. At the rising edge of the count source immediately after the timer value has reached FF16 , an overflow occurs and an interrupt request is generated. (2) Event count mode Timer operates in the same way as in the timer mode except that it counts input from the CNTR0 or CNTR1 pin. (3) Pulse output mode In this mode, duty 50% pulses are output from the T0 or T1 pin. When the timer overflows, the polarity of the T0 or T1 pin output level is inverted. (4) Pulse width measuring mode The 7477/7478 group can measure the “H” or “L” width of the CNTR0 or CNTR1 input waveform by using the pulse width measuring mode of timer 4. The pulse width measuring mode is selected by writing “1” to bit 6 in the timer 34 mode register. In the pulse width measuring mode, the timer counts the count source while the CNTR0 or CNTR 1 input is “H” or “L”. Whether the CNTR0 input or CNTR1 input to be measured can be specified by the status of bit 4 in the edge polarity selection register; whether the “H” MITSUBISHI MICROCOMPUTERS 7477/7478 GROUP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER width or “L” width to be measured can be specified by the status of bit 2 (CNTR 0) and bit 3 (CNTR1) in the edge polarity selection register. (5) PWM mode The PWM mode can be entered for timer 3 and timer 4 by setting bit 7 in the timer mode register 2 to “1”. In the PWM mode, the P13 pin is set for timer output T1 to output PWM waveforms by setting bit 7 in the timer 34 mode register to “1”. The direction register of P13 must be set for the output mode before this can be done. In the PWM mode, timer 3 is counting and timer 4 is idle while the PWM waveform is “L”. When timer 3 overflows, the PWM waveform goes “H”. At this time, timer 3 stops counting simultaneously and timer 4 starts counting. When timer 4 overflows, the PWM waveform goes “L”, and timer 4 stops and timer 3 starts counting again. Consequently, the “L” duration of the PWM waveform is determined by the value of timer 3; the “H” duration of the PWM waveform is determined by the value of timer 4. When a value is written to the timer in operation during the PWM mode, the value is only written to the timer latch, and not written to the timer. In this case, if the timer overflows, a value one less the value in the timer latch is written to the timer. When any value is written to an idle timer, the value is written to both the timer latch and the timer. In this mode, do not select timer 3 overflow as the count source for timer 4. INPUT LATCH FUNCTION The 7477/7478 group can latch the P30 /INT0 , P31 /INT 1 , P32 / CNTR0, and P3 3/CNTR1 pin level into the input latch register (address 00D616) when timer 4 overflows. The polarity of each pin latched to the input latch register can be selected by using the edge polarity selection register. When bit 0 in the edge polarity selection register is “0”, the inverted value of the P30 /INT 0 pin level is latched; when the bit is “1”, the P30/INT0 pin level is latched as it is. When bit 1 in the edge polarity selection register is “0”, the inverted value of the P31 /INT 1 pin level is latched; when the bit is “1”, the P31 /INT1 pin level is latched as it is. When bit 2 in the edge polarity selection register is “0”, the inverted value of the P32/CNTR0 pin level is latched; when the bit is “1“, the P32/CNTR 0 pin level is latched as it is. When bit 3 in the edge polarity selection register is “0”, the inverted value of the P33/CNTR 1 pin level is latched; when the bit is “1”, the P33/CNTR1 pin level is latched as it is. 15 MITSUBISHI MICROCOMPUTERS 7477/7478 GROUP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER XCIN (Note) Data bus 1/2 1/2 XIN 1/8 CM7 Timer 1 latch (8) T12M 2 T12M 0 P32/CNTR0 Timer 1 (8) EG 2 Port latch T12M 1 Timer 1 interrupt request TM20 1/2 P12/T0 T12M3 Timer 2 latch (8) T12M6 T12M7 T12M4 Timer 2 (8) T12M 5 1/4 Timer 2 interrupt request TM2 6 T34M 1 T34M 2 1/8 1/16 Timer 3 latch (8) T34M 0 P32/CNTR1 Timer 3 (8) EG3 Timer 3 interrupt request T34M 4 T34M 5 Timer 4 latch (8) Timer 4 (8) Port latch T34M 6 EG 4 T34M3 F/F P13 /T1 1/2 T34M7 P33 /CNTR1 P32 /CNTR0 P31 /INT1 P30 /INT0 ( EG3 TM27 EG2 EG1 EG0 Select gate : At reset, shaded side is connected.) Note : The 7477 group does not have X CIN input. Fig. 6 Block diagram of timer 1 through 4 16 TM2 1 C D3 Q3 D2 Q2 D1 Q1 D0 Q0 Timer 4 interrupt request MITSUBISHI MICROCOMPUTERS 7477/7478 GROUP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER b7 b7 b0 b7 b0 Timer mode register 2 (TM2) (Address 00FA 16) Timer 34 mode register (T34M) (Address 00F9 16) Timer 1 overflow FF set enable bit 0 : Set disable 1 : Set enable Timer 4 overflow FF set enable bit 0 : Set disable 1 : Set enable Nothing is allocated (The value is undefined at reading) Timer 3, timer 4 count overflow signal selection bit 0 : Timer 1 overflow 1 : Timer 2 overflow Timer 3, timer 4 function selection bit 0 : Normal mode 1 : PWM mode Timer 3 count stop bit 0 : Count start 1 : Count stop Timer 3 count source selection bits (Note 3) 00 : f(XIN ) divided by 16 or f(X CIN ) divided by 16 01 : f(XCIN ) 10 : Timer 1 overflow or timer 2 overflow 11 : P33 /CNTR1 external clock Timer 4 count stop bit 0 : Count start 1 : Count stop Timer 4 count source selection bits (Note 3) 00 : Timer 3 overflow 01 : f(XIN ) divided by 16 or f(X CIN ) divided by 16 10 : Timer 1 overflow or timer 2 overflow 11 : P33 /CNTR1 external clock Timer 4 pulse width measuring mode selection bit 0 : Timer mode 1 : Pulse width measuring mode P13/T1 port output selection bit 0 : P13 port output 1 : Timer 4 overflow divided by 2 or PWM output b0 Timer 12 mode register (T12M) (Address 00F8 16) Timer 1 count stop bit 0 : Count start 1 : Count stop Timer 1 count source selection bit 0 : Internal clock (Note 1) 1 : P32/CNTR0 external clock Timer 1 internal clock source selection bit (Note 2) 0 : f(XIN) divided by 16 or f(XCIN ) divided by 16 1 : f(XCIN ) P12 /T0 port output selection bit 0 : P12 port output 1 : Timer 1 overflow divided by 2 Timer 2 count stop bit 0 : Count start 1 : Count stop Timer 2 count source selection bit 0 : Internal clock 1 : Timer 1 overflow Timer 2 internal clock source selection bits (Note 3) 00 : f(XIN) divided by 16 or f(XCIN ) divided by 16 01 : f(XIN) divided by 64 or f(XCIN ) divided by 64 10 : f(XIN) divided by 128 or f(XCIN ) divided by 128 11 : f(XIN) divided by 256 or f(XCIN ) divided by 256 Notes 1 : f(XIN ) divided by 16 in the 7477 group. 2 : The 7477 group does not use this bit (bit 2). Set this bit to “0”. 3 : Do not select f(X CIN ) as the count source in the 7477 group. Fig. 7 Structure of timer mode registers 17 MITSUBISHI MICROCOMPUTERS 7477/7478 GROUP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER SERIAL I/O Clock Synchronous Serial I/O Mode Serial I/O can be used as either clock synchronous or asynchronous (UART) serial I/O. A dedicated timer (baud rate generator) is also provided for baud rate generation. Clock synchronous serial I/O mode can be selected by setting the mode selection bit of the serial I/O control register to “1”. For clock synchronous serial I/O, the transmitter and the receiver must use the same clock. If an internal clock is used, transfer is started by a write signal to the transmit or receive buffer. Data bus P14 P16 RXD Address 00E0 16 Receive buffer register Serial I/O control register Address 00E2 16 Receive buffer full flag (RBF) Receive interrupt request (RI) Receive shift register RE Shift clock Clock control circuit SCLK SIOE Frequency dividing ratio 1/(n+1) Baud rate generator CSS f(XIN) 1/4 1/4 Serial I/O synchronous clock selection bit (SCS) 1/4 Address 00E4 16 SRDY SRDY F/F Clock control circuit Fall detect Shift clock TE Transmit shift completion flag (TSC) Transmit shift register TXD TIC P17 P15 Transmit interrupt request (TI) Transmit buffer register Transmit buffer empty flag (TBE) Address 00E0 16 Serial I/O status register Address 00E1 16 Data bus Fig. 8 Clock synchronous serial I/O block diagram Transfer shift clock (1/8 to 1/8192 of the internal clock, or an external clock) Serial output TxD D0 D1 D2 D3 D4 D5 D6 D7 Serial input RxD D0 D1 D2 D3 D4 D5 D6 D7 Receive enable signal S RDY Write signal to receive/transmit buffer TBE = 0 TBE = 1 TSC = 0 RBF = 1 TSC = 1 Overrun error (OE) detection Notes 1 : The transmit interrupt request (TI) can be selected to occur either when the transmit buffer has emptied (TBE = 1) or after the transmit shift operation has ended (TSC = 1), by setting the transmit interrupt source selection bit (TIC) of the serial I/O control register. 2 : If data is written to the transmit buffer when TSC = 0, the transmit clock is generated continuously and serial data is output continuously from the TxD pin. 3 : The receive interrupt request (RI) is set when the receive buffer full flag (RBF) becomes “1”. Fig. 9 Operation of clock synchronous serial I/O function 18 MITSUBISHI MICROCOMPUTERS 7477/7478 GROUP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Asynchronous Serial I/O (UART) Mode buffers have the same address in memory. Since the shift register cannot be written to or read from directly, transmit data is written to the transmit buffer, and receive data is read from the receive buffer. The transmit buffer can also hold the next data to be transmitted, and the receive buffer can hold a character while the next character is being received. Clock asynchronous serial I/O mode (UART) can be selected by clearing the serial I/O mode selection bit of the serial I/O control register to “0”. Eight serial data transfer formats can be selected, and the transfer formats used by a transmitter and receiver must be identical. The transmit and receive shift registers each have a buffer, but the two Data bus P14 RXD Address 00E2 16 RE Address 00E0 16 OE ST detection 7-bit Serial I/O control register Receive buffer register Receive buffer full flag (RBF) Receive interrupt request (RI) Receive shift register 8-bit PE FE SP detection UART control register 1/16 Address 00E3 16 Clock control circuit Serial I/O synchronous clock selection bit SCLK Frequency dividing ratio 1/(n+1) f(XIN) 1/4 Baud rate generator 1/4 ST/SP/PA generation TE 1/16 TIC Transmit shift register TXD P16 P15 Character length selection bit Transmit shift completion flag (TSC) Transmit interrupt request (TI) Transmit buffer register Transmit buffer empty flag (TBE) Address 00E1 16 Serial I/O status register Address 00E0 16 Data bus Fig. 10 UART serial I/O block diagram Transmit or receive clock Transmit buffer write signal TBE=0 TSC=0 TBE=1 Serial output TxD ST TBE=0 TSC=1✽ TBE=1 D0 D1 SP ST D0 1 start bit 7 or 8 data bits 1 or 0 parity bit 1 or 2 stop bit(s) Receive buffer read signal D1 SP ✽Generated at 2nd bit in 2-stop-bit mode RBF=0 RBF=1 RBF=1 Serial input RxD ST D0 D1 SP ST D0 D1 SP Notes 1 : Error flag detection occurs at the same time that the RBF flag becomes “1” (at 1st stop bit during reception). 2 : The transmit interrupt (TI) can be selected to occur when either the TBE or TSC flag becomes “1,” depending on the setting of the transmit interrupt source selection bit (TIC) of the serial I/O control register. 3 : The receive interrupt (RI) is set when the RBF flag becomes “1”. Fig. 11 Operation of UART serial I/O function 19 MITSUBISHI MICROCOMPUTERS 7477/7478 GROUP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Serial I/O Control Register SIOCON The serial I/O control register consists of eight control bits for the serial I/O function. UART Control Register UARTCON The UART control register consists of four control bits (bits 0 to 3) which are valid when asynchronous serial I/O is selected and set the data format of a data transfer. Serial I/O Status Register SIOSTS The read-only serial I/O status register consists of seven flags (bits 0 to 6) which indicate the operating status of the serial I/O function and various errors. Three of the flags (bits 4 to 6) are valid only in selected UART. The receive buffer full flag (bit 1) is cleared to “0” when the receive buffer is read. If there is an error, it is detected at the same time that data is transferred from the receive shift register to the receive buffer, and the receive buffer full flag is set. Writing to the serial I/O status register clears all the error flags OE, PE, FE, and SE(bit 3 to bit 6, respectively). Writing “0” to the serial I/O enable bit SIOE (bit 7 of the serial I/O control register) also clears all the status flags, including the error flags. All bits of the serial I/O status register are initialized to “0” at reset, but if the transmit enable bit (bit 4) of the serial I/O control register has been set to “1”, the transmit shift completion flag (bit 2) and the transmit buffer empty flag (bit 0) become “1”. Transmit Buffer/Receive Buffer TB/RB The transmit buffer and the receive buffer are located at the same address. The transmit buffer is write-only and the receive buffer is read-only. If a character bit length is 7 bits, the MSB of data stored in the receive buffer is “0”. Baud Rate Generator BRG The baud rate generator determines the baud rate for serial transfer. The baud rate generator divides the frequency of the count source by 1/(n+1), where n is the value written to the baud rate generator. 20 MITSUBISHI MICROCOMPUTERS 7477/7478 GROUP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER b7 b0 Serial I/O status register (SIOSTS: address 00E116) Transmit buffer empty flag (TBE) 0 : Buffer full 1 : Buffer empty Receive buffer full flag (RBF) 0 : Buffer empty 1 : Buffer full Transmit shift completion flag (TSC) 0 : Transmit shift in progress 1 : Transmit shift completed Overrun error flag (OE) 0 : No error 1 : Overrun error Parity error flag (PE) 0 : No error 1 : Parity error Framing error flag (FE) 0 : No error 1 : Framing error Summing error flag (SE) 0 : (OE)U(PE)U(FE)=0 1 : (OE)U(PE)U(FE)=1 Not used (returns “1” when read) b7 b0 UART control register (UARTCON: address 00E316) Character length selection bit (CHAS) 0 : 8 bits 1 : 7 bits Parity enable bit (PARE) 0 : Parity checking disabled 1 : Parity checking enabled Parity selection bit (PARS) 0 : Even parity 1 : Odd parity Stop bit length selection bit (STPS) 0 : 1 stop bit 1 : 2 stop bits Not used (returns “1” when read) b7 b0 Serial I/O control register (SIOCON: address 00E216) BRG count source selection bit (CSS) 0 : f(X IN )divided by 4 1 : f(X IN )divided by16 Serial I/O synchronous clock selection bit (SCS) 0 : BRG output divided by 4 (when clock synchronous serial I/O is selected) BRG output divided by 16 (when UART is selected) 1 : External clock input (when clock synchronous serial I/O is selected ) External clock input divided by16 (when UART is selected) SRDY output enable bit (SRDY) 0 : P17 pin operates as ordinary I/O pin 1 : P17 pin operates as SRDY output pin Transmit interrupt source selection bit (TIC) 0 : Interrupt when transmit buffer has emptied. 1 : Interrupt when transmit shift operation is completed. Transmit enable bit (TE) 0 : Transmit disabled 1 : Transmit enabled Receive enable bit (RE) 0 : Receive disabled 1 : Receive enabled Serial I/O mode selection bit (SIOM) 0 : Asynchronous serial I/O (UART) 1 : Clock synchronous serial I/O Serial I/O enable bit (SIOE) 0 : Serial I/O disabled (pins P1 4 to P17 operate as ordinary I/O pins) 1 : Serial I/O enabled (pins P14 to P17 operate as serial I/O pins) Fig. 12 Structure of serial I/O control registers 21 MITSUBISHI MICROCOMPUTERS 7477/7478 GROUP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER A-D CONVERTER The A-D conversion register (address 00DA 16) contains information on the results of conversion, so that it is possible to know the results of conversion by reading the contents of this register. The following explains the procedure to execute A-D conversion. First, set values to bit 2 to bit 0 in the A-D control register to select the pins that you want to execute A-D conversion. Next, clear the A-D conversion end bit to “0”. When the above is done, A-D conversion is initiated. The A-D conversion is completed after an elapse of 50 machine cycles (12.5µs when f(XIN) = 8MHz), the AD conversion end bit is set to “1”, and the interrupt request bit is set to “1”. The results of conversion are contained in the A-D conversion register. The A-D conversion uses an 8-bit successive comparison method. Figure 13 shows a block diagram of the A-D conversion circuit. Conversion is automatically carried out once started by the program. There are eight analog input pins which are shared with P20 to P27 of port P2 (Only P20 to P23 4-bit for 7477 group). Which analog inputs are to be A-D converted is specified by using bit 2 to bit 0 in the A-D control register (address 00D916 ). Pins for inputs to be A-D converted must be set for input by setting the direction register bit to “0”. Bit 3 in the A-D control register is an A-D conversion end bit. This is “0” during A-D conversion; it is set to “1“ when the conversion is terminated. Therefore, it is possible to know whether A-D conversion is terminated by checking this bit. Figure 14 shows the relationship between the contents of A-D control register and the selected input pins. Data bus bit 3 bit 0 A-D control register (address 00D9 16) P20/IN0 A-D control circuit P21/IN1 Channel selector P22/IN2 P23/IN3 P24/IN4 P25/IN5 Comparator A-D conversion register (address 00DA 16) Switch tree Ladder resistor P26/IN6 P27/IN7 VSS (Note 1) VREF Notes 1 : AV SS for M37478M4/M8/E8-XXXFP and M37478M2/M4/M8/E8TXXXFP. 2 : The 7477 group does not have P2 4/IN4 to P2 7/IN7 pins. Fig. 13 A-D converter circuit 22 A-D conversion completion interrupt request MITSUBISHI MICROCOMPUTERS 7477/7478 GROUP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER b7 b0 A-D control register (Address 00D9 16) Analog input selection bits 000 : IN0 001 : IN1 010 : IN2 011 : IN3 100 : IN4 101 : IN5 (Note) 110 : IN6 111 : IN7 A-D conversion end bit 0 : Under conversion 1 : End conversion Nothing is allocated (The value is undefined at reading) This bit must be set to “0”. Note : Do not select IN 4 to IN7 in the 7477 group. Fig. 14 Structure of A-D control register 23 MITSUBISHI MICROCOMPUTERS 7477/7478 GROUP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER KEY ON WAKE UP “Key on wake up” is one way of returning from a power down state caused by the STP or WIT instruction. If any terminal of port P0 has “L” level applied, after bit 5 of the edge polarity selection register (EG 5) is set to “1”, an interrupt is generated and the microcomputer is returned to the normal operating state. A key matrix can be connected to port P0 and the microcomputer can be returned to a normal state by pushing any key. The key on wake up interrupt is common with the INT1 interrupt. When EG5 is set to “1”, the key on wake up function is selected. However, key on wake up cannot be used in the normal operating state. When the microcomputer is in the normal operating state, both key on wake up and INT1 are invalid. P33/CNTR 1 Port P33 data read circuit EG3 CNTR interrupt request signal EG2 P32/CNTR 0 EG4 Port P32 data read circuit XCIN (P50) 1/2 XIN 1/2 P30/INT0 CM7 Port P30 data read circuit P31/INT1 EG0 Noise eliminating circuit INT0 interrupt request signal Port P31 data read circuit EG1 Noise eliminating circuit EG5 INT1 interrupt request signal CPU halt state signal Pull-up control register P07 Direction register Pull-up control register P01 Direction register Port P0 data read circuit Pull-up control register P00 ( Direction register Select gate: At reset, shaded side is connected.). Note: The 7477 group does not have X CIN input. Fig. 15 Block diagram of interrupt input and key on wake up circuit 24 MITSUBISHI MICROCOMPUTERS 7477/7478 GROUP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER RESET CIRCUIT Address The 7477/7478 group is reset according to the sequence shown in Figure 18. It starts the program from the address formed by using the content of address FFFF16 as the high order address and the content of the address FFFE16 as the low order address, when the RESET pin is held at “L” level for no less than 2µs while the power voltage is in the recommended operating condition and then returned to “H” level. The internal initializations following reset are shown in Figure 17. Example of reset circuit is Figure 16. Immediately after reset, timer 3 and timer 4 are connected, and counts the f(XIN) divided by 16. At this time, FF16 is set to timer 3, and 07 16 is set to timer 4. The reset is cleared when timer 4 overflows. 7477/7478 group RESET VCC (1) Port P0 direction register (C116) … 0016 (2) Port P1 direction register (C316) … 0016 (3) Port P4 direction register (C916) … (4) P0 pull-up control register (D016) … (5) P1–P5 pull-up control register (Note 1) (D116) … (6) Edge selection register (EG) (D416) … (7) A-D control register (D916) … 0 (8) Serial I/O status register (E116) … (9) Serial I/O control register (E216) … (10) UART control register (E316) … 0 0 0 0 0016 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0016 0 0 0 0 (11) Timer 12 mode register (T12M) (F8 16) … 0016 (12) Timer 34 mode register (T34M) (F9 16) … 0016 (13) Timer mode register 2 (TM2) (FA16) … 0 0 (14) CPU mode register (CM) (FB16) … 0 0 0 0 (15) Interrupt request register 1 (FC16) … 0 0 (16) Interrupt request register 2 (FD16) … (17) Interrupt control register 1 (FE16) … 0 0 (18) Interrupt control register 2 (FF16) … (19) Program counter (PCH) … Contents of address FFFF 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (PC L) … Contents of address FFFE 16 (20) Processor status register (PS) … 1 Notes 1 : This address is allocated P1–P4 pull-up control register for the 7477 group. Bit 6 is not used. 2 : Since the contents of both registers other than those listed above (including timers and the transmit/receive buffer register) are undefined at reset, it is necessary to set initial values. Fig. 16 Example of reset circuit Fig. 17 Internal state of microcomputer at reset XIN φ RESET Internal RESET SYNC Address ? Data ? ? 32768 counts of f(X IN) 00, S ? 00, S-1 00, S-2 FFFE16 FFFF16 PC H PCL PS AD L ADH,L ADH Reset address from the vector table Notes 1 : Frequency relation of X IN and φ is f(XIN)=2·φ. 2 : The mark “?” means that the address is changeable depending upon the previous state. Fig. 18 Timing diagram at reset 25 MITSUBISHI MICROCOMPUTERS 7477/7478 GROUP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER I/O PORTS (1) Port P0 Port P0 is an 8-bit I/O port with CMOS outputs. As shown in Figure 2, P0 can be accessed as memory through zero page address 00C016. Port P0’s direction register allows each bit to be programmed individually as input or output. The direction register (zero page address 00C116 ) can be programmed as input with “0”, or as output with “1”. When in the output mode, the data to be output is latched to the port latch and output. When data is read from the output port, the output pin level is not read, only the latched data of the port latch is read. Therefore, a previously output value can be read correctly even though the output voltage level has been shifted up or down. Port pins set as input are in the high impedance state so the signal level can be read. When data is written into the input port, the data is latched only to the output latch and the pin still remains in the high impedance state. Following the execution of STP or WIT instruction, key matrix with port P0 can be used to generate the interrupt to bring the microcomputer back in its normal state. When this port is selected for input, pull-up transistor can be connected in units of 1-bit. (2) Port P1 Port P1 has the same function as port P0. P12 – P17 serve dual functions, and the desired function can be selected by the program. When this port is selected for input, pull-up transistor can be connected in units of 4-bit. (3) Port P2 Port P2 is an 8-bit input port. In the 7477 group, this port is P20 – P23 , a 4-bit input port. This port can also be used as the analog voltage input pins. (4) Port P3 Port P3 is a 4-bit input port. 26 (5) Port P4 Port P4 is a 4-bit I/O port and has basically the same functions as port P0. In the 7477 group, this port is P40 and P41 , a 2-bit I/O port. When this port is selected for input, pull-up transistor can be connected in units of 4-bit . (6) Port P5 Port P5 is a 4-bit input port and pull-up transistor can be connected in units of 4-bit. P50 and P5 1 are shared with clock generating circuit input/output pins. The 7477 group does not have this port. (7) INT0 pin (P3 0/INT0 pin) This is an interrupt input pin, and is shared with port P30 . When “H” to “L” or “L” to “H” transition input is applied to this pin, the INT0 interrupt request bit (bit 0 of address 00FD 16) is set to “1”. (8) INT1 pin (P3 1/INT1 pin) This is an interrupt input pin, and is shared with port P31 . When “H” to “L” or “L” to “H” transition input is applied to this pin, the INT1 interrupt request bit (bit 1 of address 00FD 16) is set to “1”. (9) Counter input CNTR0 pin (P32/CNTR 0 pin) This is a timer input pin, and is shared with port P32. When this pin is selected to CNTR0 or CNTR 1 interrupt input pin and “H” to “L” or “L” to “H” transition input is applied to this pin, the CNTR0 or CNTR 1 interrupt request bit (bit 2 of address 00FD16 ) is set to “1”. (10) Counter input CNTR1 pin (P33/CNTR 1 pin) This is a timer input pin, and is shared with port P33. When this pin is selected to CNTR0 or CNTR 1 interrupt input pin and “H” to “L” or “L” to “H” transition input is applied to this pin, the CNTR0 or CNTR 1 interrupt request bit (bit 2 of address 00FD16 ) is set to “1”. MITSUBISHI MICROCOMPUTERS 7477/7478 GROUP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Port P0 Pull-up control register Tr1 Direction register Port latch Data bus Port P0 Interrupt control circuit Ports P1 0 – P13 Pull-up control register Data bus Tr2 T34M7 Direction register Data bus Port latch Port P13 T1 Tr3 T12M3 Direction register Data bus Port latch Port P12 T0 Tr4 Direction register Data bus Port latch Port P11 Tr5 Direction register Data bus Port latch Port P10 Tr1 to Tr5 are pull-up transistors. Fig. 19 Block diagram of ports P0, P1 0–P13 27 MITSUBISHI MICROCOMPUTERS 7477/7478 GROUP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Ports P14 – P17 SIOE SIOM SRDY Tr6 Direction register Data bus Port latch Port P17 SRDY SCS SIOE SIOM SIOE Tr7 Direction register Data bus Port latch Port P16 CLK output CLK input SIOE TE Tr8 Direction register Data bus Port latch Port P15 T XD SIOE RE Tr9 Direction register Data bus Port latch Port P14 RX D Data bus Pull-up control register Tr6 to Tr9 are pull-up transistors. Fig. 20 Block diagram of ports P14 – P17 28 MITSUBISHI MICROCOMPUTERS 7477/7478 GROUP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Port P2 Data bus Port P2 A-D conversion circuit Multiplexer Port P3 Data bus Port P3 INT0, INT1 CNTR0, CNTR 1 Port P4 Data bus * : Control in units of 4-bit (Control in units of 2-bit for the 7477 group) Pull-up control register* Tr10 Direction register Data bus Port latch Port P4 Tr10 is pull-up transistor Fig. 21 Block diagram of ports P2 – P4 29 MITSUBISHI MICROCOMPUTERS 7477/7478 GROUP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Port P5 Data bus Pull-up control register Tr11 Data bus Port P53 Tr12 Data bus Port P52 CM4 Tr13 Data bus Port P51 CM4 CM4 XCIN CM4 Tr14 Data bus Port P50 Tr11 to Tr14 are pull-up transistors Note : The 7477 group does not have this port. Fig. 22 Block diagram of port P5 30 MITSUBISHI MICROCOMPUTERS 7477/7478 GROUP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER CLOCK GENERATING CIRCUIT The 7477 group has one internal clock generating circuit and 7478 group has two internal clock generating circuits. Figure 27 shows a block diagram of the clock generating circuit. Normally, the frequency applied to the clock input pin XIN divided by two is used as the internal clock φ. Bit 7 of CPU mode register can be used to switch the internal clock φ to 1/2 the frequency applied to the clock input pin XCIN in the 7478 group. Figure 23, 24 show a circuit example using a ceramic resonator (or quartz cr ystal oscillator). Use the manufacturer’s recommended values for constants such as capacitance which will differ depending on each oscillator. When using an external clock signal, input from the XIN (XCIN) pin and leave the XOUT(X COUT) pin open. A circuit example is shown in Figure 25, 26. The 7477/7478 group has two low power dissipation modes; stop and wait. The microcomputer enters a stop mode when the STP instruction is executed. The oscillator (both XIN clock and XCIN clock) stops with the internal clock φ held at “H” level. In this case timer 3 and timer 4 are forcibly connected and FF 16 is automatically set in timer 3 and 0716 in timer 4. Although oscillation is restarted when an external interrupt is accepted, the internal clock φ remains in the “H” state until timer 4 overflows. In other words, the internal clock φ is not supplied until timer 4 overflows. This is because when a ceramic or similar other oscillator is used, a finite time is required until stable oscillation is obtained after restart. The microcomputer enters an wait mode when the WIT instruction is executed. The internal clock φ stops at “H” level, but the oscillator does not stop. φ is re-supplied (wait mode release) when the microcomputer receives an interrupt. Instructions can be executed immediately because the oscillator is not stopped. The interrupt enable bit of the interrupt used to reset the wait mode or the stop mode must be set to “1” before executing the WIT or the STP instruction. Low power dissipation operation is also achieved when the XIN clock is stopped and the internal clock φ is generated from the XCIN clock (30µA typ. at f(XCIN) = 32kHz). This operation is only 7478 group. X IN clock oscillation is stopped when the bit 6 of CPU mode register is set and restarted when it is cleared. However, the wait time until the oscillation stabilizes must be generated with a program when restarting. Figure 29 shows the transition of states for the system clock. M37477M4-XXXSP/FP XIN XOUT Rd CIN COUT Fig. 23 Example of ceramic resonator circuit (7477 group) M37478M4-XXXSP/FP XOUT XIN XCIN XCOUT Rd Rd COUT CIN CCIN CCOUT Fig. 24 Example of ceramic resonator circuit (7478 group) M37477M4-XXXSP/FP XIN XOUT Open External oscillation circuit VCC VSS Fig. 25 External clock input circuit (7477 group) M37478M4-XXXSP/FP XIN XOUT XCIN XCOUT Open Open External oscillation External oscillation circuit circuit or external pulse VCC VSS VCC VSS Fig. 26 External clock input circuit (7478 group) 31 MITSUBISHI MICROCOMPUTERS 7477/7478 GROUP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER XCIN XCOUT XIN XOUT 1/2 T34M0 1/8 1/2 CM7 Timer 3 Timer 4 T34M1 T34M2 CM6 CM7 Internal clock φ Q S R S Q STP instruction WIT instruction Q Q S R R Reset STP instruction Reset Interrupt disable flag I Interrupt request Select gate : At reset, shaded side is connected. Note : The 7477 group does not have X CIN input and XCOUT output. Fig. 27 Block diagram of clock generating circuit b7 b0 CPU mode register (Address 00FB 16) These bits must always be set to “0”. Stack page selection bit (Note 1) 0 : In page 0 area 1 : In page 1 area P50, P51/XCIN, XCOUT selection bit (Note 2) 0 : P50, P51 1 : X CIN, XCOUT XCOUT drive capacity selection bit (Note 2) 0 : Low 1 : High Clock (XIN-X OUT) stop bit (Note 2) 0 : Oscillates 1 : Stops Internal system clock selection bit (Note 2) 0 : X IN-X OUT selected (normal mode) 1 : X CIN-XCOUT selected (low-speed mode) Notes 1 : In the M37477M4-XXXSP/FP, M37477M2/M4TXXXSP/FP, set this bit to “0”. In the M37478M4-XXXSP/FP, M37478M2/M4TXXXSP/FP, set this bit to “0”. 2 : In the 7477 group, set this bit to “0”. Fig. 28 Structure of CPU mode register 32 MITSUBISHI MICROCOMPUTERS 7477/7478 GROUP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Reset CM4 = 0 CM5 = 0 CM6 = 0 CM7 = 0 f(XIN) oscillation f(XIN) oscillation WIT instruction f(XCIN) stop φ stop Timer operation STP instruction f(XCIN) stop P50, P51 input φ stop φ = f(X IN)/2 Interrupt f(XIN) stop f(XCIN) stop Interrupt (Note 1) CM5 = 1 CM4 = 1 CM4 = 0 (Note 2) f(XIN) oscillation WIT instruction f(XIN) oscillation f(XCIN) oscillation φ = f(XIN)/2 Interrupt f(XIN) stop f(XCIN) stop f(XCIN) oscillation φ stop Timer operation STP instruction φ stop Interrupt (Note 1) (CM5 = 0) CM7 = 0 CM7 = 1 f(XIN) oscillation WIT instruction f(XIN) oscillation f(XCIN) oscillation φ = f(XCIN)/2 Interrupt f(XIN) stop f(XCIN) stop f(XCIN) oscillation φ stop Timer operation CM5 = 1 STP instruction φ stop Interrupt (Note 1) CM6 = 0 CM6 = 1 (Note 2) f(XIN) stop WIT instruction f(XCIN) oscillation Interrupt φ = f(XCIN)/2 f(XIN) stop f(XCIN) stop f(XCIN) oscillation φ stop Timer operation f(XIN) stop CM5 = 1 STP instruction φ stop Interrupt (Note 1) Notes 1 : Latency time is automatically generated upon release from the STP instruction due to the connections of timer 3 and 4. 2 : When the system clock is switched over by restarting clock oscillation, a certain wait time required for oscillation to stabilize must be inserted by the program. Fig. 29 Transition of states for the system clock. 33 MITSUBISHI MICROCOMPUTERS 7477/7478 GROUP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER … Power on reset ↓ Clock X oscillation ↓ Internal system clock start (X→1/2→ φ) ↓ Program star t from RESET vector Operating at f(XIN) … Normal program … Clock for clock function XC oscillation start (CM4 = 1, CM5 = 1) ↓ Latency time for oscillation to stabilize (by program) ← Operating at f(XIN) ↓ XC clock power down (CM5 : 1→0) ↓ Internal clock φ source switching X→XC (CM7 : 0→1) ↓ Clock X halt (X C in operation) (CM6 = 1) ↓ Internal clock halt (WIT instruction) ↓ Timer 4 (clock count) overflow ↓ Internal clock operation star t (WIT instruction released) Clock processing routine ← Operating at f(XCIN ) … Operation on the clock function only Normal operation <An example of flow for system> 34 Interrupts from INT0 , INT1, CNTR 0/CNTR1 , timer 1, timer 2, timer 3, timer 4, serial I/O, key on wake up ↓ Internal clock operation star t (WIT instruction released) ↓ Program star t from interrupt vector ↓ Clock X oscillation start (CM6 = 0) ↓ ← Operating at f(X CIN) Latency time for oscillation to stabilize (by program) ↓ Internal clock φ source switching (XC→X) (CM7 : 1→0) … Return from clock function Internal clock halt (WIT instruction) Normal program → Operating at f(X IN) MITSUBISHI MICROCOMPUTERS 7477/7478 GROUP STP instruction preparation (pushing registers) … ↓ Timer 3, timer 4 interrupt disable ↓ X/16 or X C/16 selected for timer 3 count source; timer 3 overflow selected for timer 4 count source ↓ Timer 3, timer 4 start counting ↓ Values set to timer 3, timer 4 that do not cause timer 4 to overflow until STP instruction is executed ↓ Interrupt for return from STP enabled ↓ Timer 4 interrupt request bit cleared ↓ Clock X and clock for clock function X C halt (STP instruction) RAM backup status … Interrupts from INT0, INT 1, CNTR0/CNTR 1, timer 1, timer 2, serial I/O, key on wake up ↓ Clock X and clock for clock function X C oscillation start ↓ Timer 4 overflow (X/16 or XC /16→timer 3→timer 4) ↓ Internal system clock start ↓ Program start from interrupt vector Normal program … Return from RAM backup function RAM backup function SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER 35 MITSUBISHI MICROCOMPUTERS 7477/7478 GROUP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER BUILT-IN PROM TYPE MICROCOMPUTERS PIN DESCRIPTION Pin Mode Name Input/ output Functions VCC,V SS Single-chip /EPROM Power source Apply voltage of 2.7 to 5.5 V to V CC and 0 V to VSS . AVSS (Note 1) Single-chip /EPROM Analog power source Ground level input pin for A-D converter. Same voltage as VSS is applied. RESET Single-chip Reset input Input To enter the reset state, the reset input pin must be kept at a “L” for 2µs or more (under normal V CC conditions). EPROM Reset input Input Connect to V SS. XIN Single-chip /EPROM Clock input Input XOUT Single-chip /EPROM Clock output Output These are I/O pins of internal clock generating circuit for main clock. To control generating frequency, an external ceramic or a quartz crystal oscillator is connected between the XIN and XOUT pins. If an external clock is used, the clock source should be connected the X IN pin and the X OUT pin should be left open. Feedback resistor is connected between X IN and XOUT. VREF Single-chip Reference voltage input Input Reference voltage input pin for the A-D converter. EPROM Select mode Input VREF works as CE input. P00 – P0 7 Single-chip EPROM P10 – P1 7 P20 – P2 7 (Note 2) P30 – P3 3 Single-chip P50 – P5 3 (Note 4) I/O Port P0 is an 8-bit I/O port. The output structure is CMOS output. When this port is selected for input, pull-up transistor can be connected in units of 1-bit and a key on wake up function is provided. Data I/O D0–D7 I/O Por t P0 works as an 8-bit data bus (D0 to D 7). I/O port P1 I/O Port P1 is an 8-bit I/O port. The output structure is CMOS output. When this port is selected for input, pull-up transistor can be connected in units of 4-bit. P1 2 and P1 3 are in common with timer output pins T0, T 1. P14 , P15, P1 6 and P1 7 are in common with serial I/O pins RxD, TxD, SCLK , SRDY, respectively. EPROM Address input A4–A10 Input P11 to P17 works as the 7-bit address input (A 4 to A 10). P1 0 must be opened. Single-chip Input port P2 Input Port P2 is an 8-bit input port. This port is in common with analog input pins IN0 to IN7. EPROM Address input A0–A3 Input P20 to P23 works as the lower 4-bit address input (A0 to A3 ). P24 to P27 must be opened. Single-chip Input port P3 Input Port P3 is a 4-bit input port. P30 and P31 are in common with external interrupt input pins INT0, INT1 and P32, P33 are in common with timer input pins CNTR0, CNTR1. Address input A11, A12 Select mode VPP input Input P30 , P31 works as the 2-bit address input (A11, A12 ). P32 works as OE input. Connect to P33 to VPP when programming or verifying. EPROM P40 – P4 3 (Note 3) I/O port P0 Single-chip I/O port P4 I/O Por t P4 is a 4-bit I/O port. The output structure is CMOS output. When this port is selected for input, pull-up transistor can be connected in units of 4-bit. EPROM Address input A13, A14 Input P40 and P41 works as the higher 2-bit address input (A13, A14 ). P42 and P43 must be opened. Single-chip Input port P5 Input Port P5 is a 4-bit input port and pull-up transistor can be connected in units of 4bit. P50 , P51 are in common with input/output pins of clock for clock function XCIN, XCOUT. When P5 0, P5 1 are used as X CIN, X COUT, connect a ceramic or a quartz crystal oscillator between XCIN and XCOUT. If an external clock input is used, connect the clock input to the X CIN pin and open the XCOUT pin. Feedback resistor is connected between XCIN and XCOUT pins. EPROM Open. Notes 1 : AVSS for M37478M4/M8/E8-XXXFP and M37478M2/M4/E8TXXXFP. 2 : Only P20–P23 (IN 0–IN3 ) 4-bit for the 7477 group. 3 : Only P40 and P41 2-bit for the 7477group. 4 : This port is not included in the 7477 group. 36 MITSUBISHI MICROCOMPUTERS 7477/7478 GROUP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER EPROM MODE Table 2. Pin function in EPROM mode The M37477E8, M37478E8 feature an EPROM mode in addition to its normal modes. When the RESET signal level is low (“L”), the chip automatically enters the EPROM mode. Table 2 lists the correspondence between pins and Figure 30 to 32 give the pin connection in the EPROM mode. When in the EPROM mode, ports P0, P1 1 to P17, P20 to P23, P3, P40 , P41 and VREF are used for the PROM (equivalent to the M5L27C256K). When in this mode, the built-in PROM can be written to or read from using these pins in the same way as with the M5L27C256K. The oscillator should be connected to the X IN and XOUT pins, or external clock should be connected to the XIN pin. A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 CE Oscillation circuit VSS M5L27C256K VCC VCC VCC VPP P33 VPP VSS VSS VSS Ports Address input CE VREF CE OE P32 OE 42 41 3 40 4 39 5 38 6 37 7 36 9 10 11 12 13 14 A0 – A14 Port P0 2 8 P11 – P1 7, P20 – P23, P30, P31 , P40, P41 Data I/O 1 M37478E8SS M37478E8TXXXSP M37478E8-XXXSP P53 P17/SRDY P16/SCLK P15/TXD P14/RXD P13/T1 P12/T0 P11 P10 P27/IN7 P26/IN6 P25/IN5 P24/IN4 P23/IN3 P22/IN2 P21/IN1 P20/IN0 VREF XIN XOUT VSS A10 M37477E8, M37478E8 35 34 33 32 31 30 29 15 28 16 27 17 26 18 25 19 24 20 23 21 22 P52 P07 P06 P05 P04 P03 P02 P01 P00 P43 P42 P41 P40 P33/CNTR 1 P32/CNTR 0 P31/INT1 P30/INT0 RESET P51/XCOUT P50/XCIN VCC D0 – D7 D7 D6 D5 D4 D3 D2 D1 D0 A14 A13 VPP OE A12 A11 VSS VCC : Same functions as M5L27C256K Fig. 30 Pin connection in EPROM mode 37 MITSUBISHI MICROCOMPUTERS 7477/7478 GROUP A11 A12 OE VPP A13 A14 D0 D1 D2 29 30 31 33 32 34 35 37 36 38 39 41 40 42 48 25 NC P51/XCOUT P50/XCIN NC VCC VSS AVSS NC XOUT XIN NC 49 24 M37478E8-XXXFP M37478E8TXXXFP 50 51 23 22 VCC VSS Oscillation circuit CE A0 A1 A3 A2 A5 A4 A6 A7 NC P14/RXD/A7 P13/T1/A6 P12/T0/A5 P11/A4 P10 P27/IN7 P26/IN6 P25/IN5 P24/IN4 P23/IN3/A3 P22/IN2/A2 P21/IN1/A1 P20/IN0/A0 VREF/CE NC 13 VSS 16 17 15 56 14 18 12 19 55 11 20 54 10 53 9 21 8 52 1 A8 26 7 A9 47 6 A10 RESET 27 5 VSS 28 46 4 D7 45 3 D6 NC P05/D5 P06/D6 P07/D7 P52 NC VSS P53 P17/SRDY/A10 P16/SCLK/A9 P15/TXD/A8 NC 2 D5 43 44 NC P04/D4 P03/D3 P02/D2 P01/D1 P00/D0 P43 P42 P41/A14 P40/A13 NC P33/CNTR1/VPP P32/CNTR 0/OE P31/INT 1/A12 P30/INT0/A11 NC D3 D4 SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER : Same functions as M5L27C256K Fig. 31 Pin connection in EPROM mode A10 A9 A8 A7 A5 A4 A3 A2 A1 A0 CE Oscillation circuit VSS 1 32 2 31 3 30 4 29 5 6 7 8 9 10 11 12 M37477E8-XXXSP/FP M37477E8TXXXSP/FP A6 P17/SRDY P16/SCLK P15/TXD P14/RXD P13/T1 P12/T0 P11 P10 P23/IN3 P22/IN2 P21/IN1 P20/IN0 VREF XIN XOUT VSS 38 27 26 25 24 23 22 21 13 20 14 19 15 18 16 17 : Same functions as M5L27C256K Fig. 32 Pin connection in EPROM mode (7477 Group ) 28 P07 P06 P05 P04 P03 P02 P01 P00 P41 P40 P33/CNTR 1 P32/CNTR 0 P31/INT1 P30/INT0 RESET VCC D7 D6 D5 D4 D3 D2 D1 D0 A14 A13 VPP OE A12 A11 VCC VSS MITSUBISHI MICROCOMPUTERS 7477/7478 GROUP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER PROM READING AND WRITING Reading NOTES ON HANDLING To read the PROM, set the CE and OE pins to “L” level. Input the address of the data (A0 to A14) to be read and the data will be output to the I/O pins (D0 to D7). The data I/O pins will be floating when either the CE or OE pin is in the “H” state. Writing To write to the PROM, set the OE pin to “H” level. The CPU will enter the program mode when VPP is applied to the VPP pin. The address to be written to is selected with pins A0 to A 14 , and the data to be written is input to pins D0 to D 7. Set the CE pin to “L” level to begin writing. Note on Writing When using a PROM programmer, the address range should be between 4000 16 and 7FFF16. When data is written between addresses 0000 16 and 7FFF16 , fill addresses 000016 to 3FFF 16 with FF16. (1) Sunlight and fluorescent light contain wave lengths capable of erasing data. For ceramic package types, cover the transparent window with a seal (provided) when this chip is in use. However, this seal must not contact the lead pins. (2) Before erasing, the glass should be cleaned and stains such as finger prints should be removed thoroughly. If these stains are not removed, complete erasure of the data could be prevented. (3) Since a high voltage (12.5V) is used to write data, care should be taken when turning on the PROM programmer’s power. (4) For the programmable microcomputer (shipped in One Time PROM version), Mitsubishi does not perform PROM write test and screening in the assembly process and following processes. To improve reliability after write, performing write and test according to the flow below before use is recommended. Writing with PROM programmer Erasing Data can only erased on the M37478E8SS ceramic package, which includes a window. To erase data on this chip, use an ultraviolet light source with a 2537 Angstrom wave length. The minimum radiation power necessary for erasing is 15W · s/cm2. Screening (Caution) (Leave at 150°C for 40 hours.) Verify test with PROM programmer Function check in target device Caution : Since the screening temperature is higher than storage temperature, never expose to 150°C exceeding 100 hours. Table 3. I/O signal in each mode Pin __ __ CE OE VPP VCC Data I/O Read-out VIL VIL VCC VCC Output Output disable VIL VIH VCC VCC Floating Programming VIL VIH VPP VCC Input Programming verify VIH VIL VPP VCC Output Program disable VIH VIH VPP VCC Floating Mode Note : VIL and VIH indicate an “L” and an “H” input voltage, respectively. 39 MITSUBISHI MICROCOMPUTERS 7477/7478 GROUP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER PROGRAMMING NOTES (1) The frequency ratio of the timer is 1/(n+1). (2) The contents of the interrupt request bits are not modified immediately after they have been written. After writing to an interrupt request register, execute at least one instruction before executing a BBC or BBS instruction. (3) To calculate in decimal notation, set the decimal mode flag (D) to “1”, then execute an ADC or SBC instruction. Only the ADC and SBC instruction yield proper decimal results. After executing an ADC or SBC instruction, execute at least one instruction before executing a SEC, CLC, or CLD instruction. (4) An NOP instruction must be used after the execution of a PLP instruction. (5) Do not execute the STP instruction during A-D conversion. (6) In the 7477 group, set bit 0, bit 1, and bit 3 – bit 7 to “0” of the CPU mode register. (7) Multiply/Divide instructions The index X mode (T) and the decimal mode (D) flag do not affect the MUL and DIV instruction. The execution of these instructions does not modify the contents of the processor status register. DATA REQUIRED FOR MASK ORDERING Please send the following data for mask orders. (1) mask ROM confirmation form (2) mark specification form (3) ROM data ......................................................... EPROM 3 sets 40 MITSUBISHI MICROCOMPUTERS 7477/7478 GROUP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER M37477M4/M8/E8-XXXSP/FP, M37477M2T/M4T/M8T/E8TXXXSP/FP ABSOLUTE MAXIMUM RATINGS Symbol Parameter Conditions VCC Power source voltage VI Input voltage XIN VI Input voltage P00 – P07, P1 0 – P1 7, P20 – P23, P30 – P3 3, P40, P41, VREF, RESET VO Output voltage P00 – P0 7, P1 0 – P17, P40, P41, X OUT Pd Power dissipation Topr Operating temperature Tstg Storage temperature All voltages are based on V SS. Output transistors are cut off Ratings Unit –0.3 to 7 V –0.3 to VCC +0.3 V –0.3 to VCC +0.3 V –0.3 to VCC +0.3 V 1000 (Note 1) mW –20 to 85 (Note 2) °C –40 to 150 (Note 3) °C Ta = 25°C Notes 1 : 500mW for 32P2W-A package. 2 : –40°C to 85°C for extended operating temperature version. 3 : –65°C to 150°C for extended operating temperature version. RECOMMENDED OPERATING CONDITIONS (VCC = 2.7 to 5.5 V, VSS = 0 V, Ta = –20 to 85°C unless otherwise noted (Note 1)) Symbol Limits Parameter VCC Power source voltage VSS Power source voltage Min. f(XIN) = 2.2VCC – 2.0 MHz 2.7 f(XIN) = 8 MHz 4.5 Typ. Max. 4.5 5 5.5 Unit V V 0 VIH “H” input voltage P0 0 – P07, P10 – P17, P30 – P33, RESET, XIN 0.8 VCC VCC V VIH “H” input voltage P20 – P23 , P40, P41 0.7 VCC VCC V VIL “L” input voltage P00 – P07 , P10 – P17, P3 0 – P33 0 0.2 VCC V VIL “L” input voltage P20 – P23 , P40, P41 0 0.25 VCC V VIL “L” input voltage RESET 0 0.12 VCC V VIL “L” input voltage XIN 0 0.16 VCC V I OH(sum) “H” sum output current P00 – P07 , P40, P41 –30 mA I OH(sum) “H” sum output current P10 – P17 –30 mA I OL(sum) “L” sum output current P00 – P07 , P40, P41 60 mA I OL(sum) “L” sum output current P10 – P17 60 mA I OH(peak) “H” peak output current P00 – P07, P10 – P17, P40, P4 1 –10 mA I OL(peak) “L” peak output current P00 – P07, P10 – P17, P40, P4 1 20 mA I OH(avg) “H” average output current P0 0 – P07 , P10 – P17 , P40, P41 (Note 2) –5 mA I OL(avg) “L” average output current P00 – P07 , P10 – P17 , P40, P41 (Note 2) 10 mA f( CNTR) Timer input frequency CNTR0 (P3 2), CNTR1 (P3 3) (Note 3) f(SCLK ) f(XIN ) Serial I/O clock input frequency SCLK (P16 ) (Note 3) Use as clock synchronous serial I/O mode Use as UART mode Clock input oscillation frequency (Note 3) f(XIN) = 4 MHz 1 f(XIN) = 8 MHz 2 f(XIN) = 4 MHz 250 f(XIN) = 8 MHz 500 f(XIN) = 4 MHz 1 f(XIN) = 8 MHz 2 VCC = 2.7 to 4.5 V VCC = 4.5 to 5.5 V 2.2VCC – 2 MHz kHz MHz MHz 8 Notes 1 : –40°C to 85°C for extended operating temperature version. 2 : The average output current IOH (avg) and IOL (avg) are the average value during a 100ms. 3 : Oscillation frequency is at 50% duty cycle. 41 MITSUBISHI MICROCOMPUTERS 7477/7478 GROUP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER M37477M4/M8/E8-XXXSP/FP, M37477M2T/M4T/M8T/E8TXXXSP/FP ELECTRICAL CHARACTERISTICS (VCC = 2.7 to 5.5 V, VSS = 0 V, Ta = –20 to 85°C, unless otherwise noted (Note)) Symbol VOH VOL VT + – VT– VT + – VT– VT + – VT– Parameter Min. Typ. Max. “H” output voltage VCC = 5 V, IOH = –5 mA 3 P00 – P0 7, P10 – P17 , P40, P41 VCC = 3 V, IOH = –1.5 mA 2 “L” output voltage VCC = 5 V, IOL = 10 mA 2 P00 – P0 7, P10 – P17 , P40, P41 VCC = 3 V, IOL = 3 mA 1 Hysteresis P00 – P07 , VCC = 5 V 0.5 P30 – P3 3 VCC = 3 V 0.3 VCC = 5 V 0.5 VCC = 3 V 0.3 Hysteresis RESET Hysteresis P16/S CLK ”H“ input current I IL Limits Test Conditions P00-P07 , P10-P17 P30-P32 , P40-P41 use as S CLK input V VCC = 5 V 0.5 VCC = 3 V 0.3 V V VI = 0 V, VCC = 5 V –5 not use pull-up transistor VCC = 3 V –3 VI = 0 V, VCC = 5 V –0.25 –0.5 –1.0 use pull-up transistor VCC = 3 V –0.08 –0.18 –0.35 –5 VCC = 3 V –3 VI = 0 V, VCC = 5 V –5 not use as analog input VCC = 3 V –3 VI = 0 V VCC = 5 V –5 (X IN is at stop mode) VCC = 3 V –3 “H” input current P0 0 – P07 , VI = VCC, VCC = 5 V 5 P10 – P17, P30 – P3 2, P40, P41 not use pull-up transistor VCC = 3 V 3 “H” input current, P33 VCC = 5 V I IH VI = VCC 5 VCC = 3 V 3 I IH “H” input current P20 – P23 I IH “H” input current RESET X IN, “L” input current P3 3 I IL “L” input current P2 0 – P23 I IL “L” input current RESET, X IN I IH I CC Power source current VI = 0 V VI = VCC, VCC = 5 V 5 not use as analog input VCC = 3 V 3 VI = VCC, VCC = 5 V 5 (X IN is at stop mode) VCC = 3 V 3 At normal mode, A-D conversion is not executed. f(XIN)=8MHz At normal mode, A-D conversion is executed. f(XIN)=8MHz f(XIN)=4MHz f(XIN)=4MHz f(XIN)=8MHz At wait mode. f(XIN)=4MHz At stop mode, f(XIN)=0, V CC=5V VRAM RAM retention voltage Stop all oscillation Note : –40°C to 85°C for extended operating temperature version. 42 7 14 3.5 7 1.8 3.6 7.5 15 4 8 2 4 2 4 1 2 VCC = 3 V 0.5 1 Ta = 25°C 0.1 1 Ta = 85°C 1 10 VCC = 5 V VCC = 3 V VCC = 5 V VCC = 3 V VCC = 5 V 2 V V VCC = 5 V I IL Unit 5.5 µA mA µA µA µA µA µA µA µA mA mA mA µA V MITSUBISHI MICROCOMPUTERS 7477/7478 GROUP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER M37477M4/M8/E8-XXXSP/FP, M37477M2T/M4T/M8T/E8TXXXSP/FP A-D CONVERSION CHARACTERISTICS (VCC = 2.7 to 5.5 V, VSS = 0 V, Ta = –20 to 85°C, unless otherwise noted (Note 1)) Symbol Parameter —— Resolution —— Absolute accuracy TCONV Conversion time Test Conditions Limits Min. Typ. Max. 8 bits ±3 LSB VCC = 2.7 to 5.5 V, f(XIN ) = 4 MHz 25 VCC = 4.5 to 5.5 V, f(XIN ) = 8 MHz 12.5 VREF Reference input voltage 0.5 VCC (Note 2) RLADDER Ladder resistance value 2 VIA Analog input voltage 0 5 Unit µs VCC V 10 kΩ VREF V Notes 1 : –40°C to 85°C for extended operating temperature version. 2 : Set the VREF voltage to 0.5VCC or more and 2V or more. When using no A-D converter, connect it to V CC. 43 MITSUBISHI MICROCOMPUTERS 7477/7478 GROUP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER M37478M4/M8/E8-XXXSP/FP, M37478M2T/M4T/M8T/E8TXXXSP/FP, M37478E8SS ABSOLUTE MAXIMUM RATINGS Symbol Parameter Conditions VCC Power source voltage VI Input voltage XIN VI Input voltage P00 – P07, P1 0 – P17, P2 0 _____ – P27 , P30 – P33, P4 0 – P4 3, P50 – P53 , VREF, RESET VO Output voltage P00 – P07, P10 – P17, P4 0 – P43, XOUT Pd Power dissipation Topr Operating temperature Tstg Storage temperature All voltages are based on V SS. Output transistors are cut off Ratings Unit –0.3 to 7 V –0.3 to VCC +0.3 V –0.3 to VCC +0.3 V –0.3 to VCC +0.3 V 1000 (Note 1) mW –20 to 85 (Note 2) °C –40 to 150 (Note 3) °C Ta = 25°C Notes 1 : 500mW for 56P6N-A package. 2 : –40°C to 85°C for extended operating temperature version. 3 : –65°C to 150°C for extended operating temperature version. RECOMMENDED OPERATING CONDITIONS (VCC = 2.7 to 5.5 V, VSS = AVSS = 0 V, Ta = –20 to 85°C unless otherwise noted (Note 1)) Symbol Limits Parameter Min. f(XIN) = 2.2VCC – 2.0 MHz 2.7 f(XIN) = 8 MHz 4.5 Typ. Max. 4.5 Unit VCC Power source voltage VSS Power source voltage 0 V AVSS Analog power source voltage 0 V VIH “H” input voltage P00 – P07, P10 – P17 , P30 – P33 , RESET, XIN 0.8 VCC VCC V VIH “H” input voltage P20 – P27, P40 – P43, P50 – P5 3 (Note 2) 0.7 VCC VCC V 5 5.5 V VIL “L” input voltage P0 0 – P07, P10 – P17, P30 – P33 0 0.2 VCC V VIL “L” input voltage P2 0 – P27, P40 – P43, P50 –P53 (Note 2) 0 0.25 VCC V VIL “L” input voltage RESET 0 0.12 VCC V VIL “L” input voltage XIN 0 0.16 VCC V I OH(sum) “H” sum output current P00 – P07, P4 0 – P43 – 30 mA I OH(sum) “H” sum output current P10 – P17 – 30 mA I OL(sum) “L” sum output current P00 – P07, P4 0 – P43 60 mA I OL(sum) “L” sum output current P10 – P17 60 mA I OH(peak) “H” peak output current P00 – P07, P10 – P1 7, P40 – P43 – 10 mA I OL(peak) “L” peak output current P00 – P0 7, P10 – P1 7, P40 – P4 3 20 mA I OH(avg) “H” average output current P0 0 – P07, P1 0 – P17, P4 0 – P43 (Note 3) –5 mA I OL(avg) “L” average output current P0 0 – P07 , P10 – P17, P4 0 – P43 (Note 3) 10 mA f( CNTR) Timer input frequency CNTR0 (P3 2), CNTR1 (P3 3) (Note 4) f(SCLK ) f(XIN ) f(XCIN ) Serial I/O clock input frequency SCLK (P16 ) (Note 3) Use as clock synchronous serial I/O mode Use as UART mode Main clock input oscillation frequency (Note 4) f(XIN) = 4 MHz 1 f(XIN) = 8 MHz 2 f(XIN) = 4 MHz 250 f(XIN) = 8 MHz 500 f(XIN) = 4 MHz 1 f(XIN) = 8 MHz 2 VCC = 2.7 to 4.5 V Sub-clock input oscillation frequency for clock function (Note 4,5) Notes 1 : –40°C to 85°C for extended operating temperature version. 2 : It is except to use P50 as XCIN . 3 : The average output current IOH (avg) and IOL (avg) are the average value during a 100ms. 4 : Oscillation frequency is at 50% duty cycle. 5 : Set f(XCIN) < f(XIN) / 3 when the sub-clock is used. 44 2.2VCC – 2 VCC = 4.5 to 5.5 V MHz kHz MHz MHz 8 32 50 kHz MITSUBISHI MICROCOMPUTERS 7477/7478 GROUP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER M37478M4/M8/E8-XXXSP/FP, M37478M2T/M4T/M8T/E8TXXXSP/FP, M37478E8SS ELECTRICAL CHARACTERISTICS (V CC = 2.7 to 5.5 V, VSS = AVSS = 0 V, Ta = –20 to 85°C, unless otherwise noted (Note)) Symbol VOH VOL VT + – VT– Parameter VCC = 5 V, IOH = –5 mA 3 2 “L” output voltage VCC = 5 V, IOL = 10 mA 2 P00 – P0 7, P10 – P17 , P40 – P43 VCC = 3 V, IOL = 3 mA 1 Hysteresis P00 – P0 7, VCC = 5 V 0.5 P30 – P3 3 VCC = 3 V 0.3 VCC = 5 V 0.5 VCC = 3 V 0.3 Hysteresis P16/SCLK “L” input current P00 – P07 , P10 – P17, P3 0 – P32, P40 – P43 , P50 – P53 I IL “L” input current P3 3 I IL “L” input current P2 0 – P27 I IL “L” input current RESET, XIN used as S CLK input 0.3 V not use pull-up transistor VCC = 3 V –3 VI = 0 V, VCC = 5 V –0.25 –0.5 –1.0 use pull-up transistor VCC = 3 V –0.08 –0.18 –0.35 VCC = 5 V –5 VCC = 3 V –3 VI = 0 V, VCC = 5 V –5 not use as analog input VCC = 3 V –3 VI = 0 V VCC = 5 V –5 (XIN is at stop mode) VCC = 3 V –3 VCC = 5 V 5 VCC = 3 V 3 VCC = 5 V 5 VCC = 3 V 3 not use pull-up transistor I IH “H” input current P33 VI = V CC I IH “H” input current P20 – P27 I IH “H” input current RESET, XIN VI = V CC, VCC = 5 V 5 not use as analog input VCC = 3 V 3 VI = V CC, VCC = 5 V 5 (XIN is at stop mode) VCC = 3 V 3 At normal mode, A-D conversion is not executed. f(XIN)=8MHz At normal mode, A-D conversion is executed. f(XIN)=8MHz 7 VCC = 5 V 7 1.8 3.6 7.5 15 4 8 VCC = 3 V 2 4 VCC = 5 V 30 80 VCC = 3 V 15 40 2 4 1 2 VCC = 3 V 0.5 1 At wait mode, Ta =25°C, f(X IN)=0, f(XCIN )=32kHz, lowpower mode VCC = 5 V 3 12 VCC = 3 V 2 8 At stop mode, f(XIN)=0, f(X CIN)=0, VCC=5V Ta = 25°C 0.1 1 Ta = 85°C 1 10 f(XIN)=4MHz f(XIN)=4MHz At low-speed mode, T a=25°C, f(X IN)=0, f(XCIN)=32kHz, low-power mode, A-D conversion is not executed. f(XIN)=8MHz f(XIN)=4MHz Stop all oscillation VCC = 3 V VCC = 5 V VCC = 5 V 2 µA mA µA µA µA µA µA µA µA 14 3.5 At wait mode. RAM retention voltage 0.5 VCC = 3 V V –5 “H” input current P00 – P07, P10 – P17, VI = V CC, Power source current VCC = 5 V V V VCC = 5 V VI = 0 V Unit V VI = 0 V, P30 – P3 2, P40 – P4 3, P50 – P5 3 VRAM Max. VCC = 3 V, I OH = –1.5 mA VT + – VT– I CC Typ. P00 – P0 7, P10 – P17 , P40 – P43 Hysteresis RESET I IH Min. “H” output voltage VT + – VT– I IL Limits Test Conditions 5.5 mA mA µA mA µA µA V Note : –40°C to 85°C for extended operating temperature version. 45 MITSUBISHI MICROCOMPUTERS 7477/7478 GROUP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER M37478M4/M8/E8-XXXSP/FP, M37478M2T/M4T/M8T/E8TXXXSP/FP, M37478E8SS A-D CONVERSION CHARACTERISTICS (VCC = 2.7 to 5.5 V, VSS = AVSS = 0 V, Ta = –20 to 85°C, unless otherwise noted (Note 1)) Symbol Parameter —— Resolution —— Absolute accuracy TCONV Conversion time Test Conditions Limits Min. Typ. 8 bits LSB VCC = 2.7 to 5.5 V, f(XIN ) = 4 MHz 25 12.5 Reference input voltage 0.5 VCC (Note 2) RLADDER Ladder resistance value 2 VIA Analog input voltage 0 5 Notes 1 : –40°C to 85°C for extended operating temperature version. 2 : Set the VREF voltage to 0.5VCC or more and 2V or more. When using no A-D converter, connect it to V CC. Unit ±3 VCC = 4.5 to 5.5 V, f(XIN ) = 8 MHz VREF 46 Max. µs VCC V 10 kΩ VREF V Keep safety first in your circuit designs! • Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap. • These materials are intended as a reference to assist our customers in the selection of the Mitsubishi semiconductor product best suited to the customer’s application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Mitsubishi Electric Corporation or a third party. Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement of any third-party’s rights, originating in the use of any product data, diagrams, charts or circuit application examples contained in these materials. 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Notes regarding these materials • • • • • • © 1997 MITSUBISHI ELECTRIC CORP. 9706 Printed in Japan (ROD) II New publication, effective June. 1997. Specifications subject to change without notice.