To all our customers Regarding the change of names mentioned in the document, such as Mitsubishi Electric and Mitsubishi XX, to Renesas Technology Corp. The semiconductor operations of Hitachi and Mitsubishi Electric were transferred to Renesas Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.) Accordingly, although Mitsubishi Electric, Mitsubishi Electric Corporation, Mitsubishi Semiconductors, and other Mitsubishi brand names are mentioned in the document, these names have in fact all been changed to Renesas Technology Corp. Thank you for your understanding. Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been made to the contents of the document, and these changes do not constitute any alteration to the contents of the document itself. Note : Mitsubishi Electric will continue the business operations of high frequency & optical devices and power devices. Renesas Technology Corp. Customer Support Dept. April 1, 2003 Rev.1.0 Mitsubishi microcomputers M16C / 30L Group Description SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Description The M16C/30L group of single-chip microcomputers are built using the high-performance silicon gate CMOS process using a M16C/60 Series CPU core and are packaged in a 100-pin plastic molded QFP. These single-chip microcomputers operate using sophisticated instructions featuring a high level of instruction efficiency. With 1M bytes of address space, low voltage (2.2V to 3.6V), they are capable of executing instructions at high speed. They also feature a built-in multiplier and DMAC, making them ideal for controlling office, communications, industrial equipment, and other high-speed processing applications. The M16C/30L group includes a wide range of products with different internal memory sizes and various package types. Features • Memory capacity .................................. ROM (See Figure 1.1.4. ROM Expansion) RAM 2K to 3K bytes • Shortest instruction execution time ...... 62.5ns (f(XIN)=16MHZ, VCC=3.0V to 3.6V) 142.9ns (f(XIN)=7MHZ, VCC=2.4V to 3.6V without software wait) • Supply voltage ..................................... 3.0V to 3.6V (f(XIN)=16MHZ, without software wait) 2.4V to 3.6V (f(XIN)=7MHZ, without software wait) 2.2V to 3.6V (f(XIN)=7MHZ, with software one-wait) • Low power consumption ...................... 34.0mW (VCC = 3V, f(XIN)=10MHZ, without software wait) 66.0mW (VCC = 3.3V, f(XIN)=16MHZ, without software wait) • Interrupts .............................................. 16 internal and 5 external interrupt sources, 4 software interrupt sources; 7 levels (including key input interrupt) • Multifunction 16-bit timer ...................... 3 output timers + 2 input timers • Serial I/O .............................................. 3 channels (3 for UART or clock synchronous) • DMAC .................................................. 1 channels (trigger: 14 sources) • A-D converter ....................................... 10 bits X 8 channels (Expandable up to 10 channels) • Watchdog timer .................................... 1 line • Programmable I/O port ........................ 87 lines _______ • Input port .............................................. 1 line (P85 shared with NMI pin) • Memory expansion .............................. Available (to a maximum of 1M bytes) • Chip select output ................................ 4 lines • Clock generating circuit ....................... 2 built-in clock generation circuits (built-in feedback resistor, and external ceramic or quartz oscillator) Applications Audio, cameras, office equipment, communications equipment, portable equipment ------Table of Contents-----Central Processing Unit (CPU) ..................... 11 Reset ............................................................. 14 Processor Mode ............................................ 21 Clock Generating Circuit ............................... 34 Protection ...................................................... 43 Interrupt ......................................................... 44 Watchdog Timer ............................................ 64 DMAC ........................................................... 66 Timer ............................................................. 75 Serial I/O ....................................................... 93 A-D Converter ............................................. 130 Programmable I/O Ports ............................. 136 Electrical characteristics ............................. 146 1 Mitsubishi microcomputers M16C / 30L Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Description Pin Configuration Figures 1.1.1 and 1.1.2 show the pin configurations (top view). P10/D8 P11/D9 P12/D10 P13/D11 P14/D12 P15/D13 P16/D14 P17/D15 P20/A0(/D0/-) P21/A1(/D1/D0) P22/A2(/D2/D1) P23/A3(/D3/D2) P24/A4(/D4/D3) P25/A5(/D5/D4) P26/A6(/D6/D5) P27/A7(/D7/D6) Vss P30/A8(/-/D7) Vcc P31/A9 P32/A10 P33/A11 P34/A12 P35/A13 P36/A14 P37/A15 P40/A16 P41/A17 P42/A18 P43/A19 PIN CONFIGURATION (top view) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 P07/D7 P06/D6 P05/D5 P04/D4 P03/D3 P02/D2 P01/D1 P00/D0 P107/AN7/KI3 P106/AN6/KI2 P105/AN5/KI1 P104/AN4/KI0 P103/AN3 P102/AN2 P101/AN1 AVSS P100/AN0 VREF AVcc P97/ADTRG 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 M16C/30L Group 97 98 99 100 2 3 4 5 P44/CS0 P45/CS1 P46/CS2 P47/CS3 P50/WRL/WR P51/WRH/BHE P52/RD P53/BCLK P54/HLDA P55/HOLD P56/ALE P57/RDY/CLKOUT P60/CTS0/RTS0 P61/CLK0 P62/RxD0 P63/TXD0 P64/CTS1/RTS1/CLKS1 P65/CLK1 P66/RxD1 P67/TXD1 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 P96/ANEX1 P95/ANEX0 P94 P93 P92/TB2IN P91/TB1IN P90 BYTE CNVss P87/XCIN P86/XCOUT RESET XOUT VSS XIN VCC P85/NMI P84/INT2 P83/INT1 P82/INT0 P81 P80 P77 P76 P75/TA2IN P74/TA2OUT P73/CTS2/RTS2/TA1IN P72/CLK2/TA1OUT P71/RxD2/SCL/TA0IN (Note) P70/TXD2/SDA/TA0OUT (Note) 1 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 Note: P70 and P71 are N channel open-drain output pin. Package: 100P6S-A Figure 1.1.1. Pin configuration (top view) 2 Mitsubishi microcomputers M16C / 30L Group Description SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER P13/D11 P14/D12 P15/D13 P16/D14 P17/D15 P20/A0(/D0/-) P21/A1(/D1/D0) P22/A2(/D2/D1) P23/A3(/D3/D2) P24/A4(/D4/D3) P25/A5(/D5/D4) P26/A6(/D6/D5) P27/A7(/D7/D6) Vss P30/A8(/-/D7) Vcc P31/A9 P32/A10 P33/A11 P34/A12 P35/A13 P36/A14 P37/A15 P40/A16 P41/A17 PIN CONFIGURATION (top view) 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 P12/D10 P11/D9 P10/D8 P07/D7 P06/D6 P05/D5 P04/D4 P03/D3 P02/D2 P01/D1 P00/D0 P107/AN7/KI3 P106/AN6/KI2 P105/AN5/KI1 P104/AN4/KI0 P103/AN3 P102/AN2 P101/AN1 AVSS P100/AN0 VREF AVcc P97/ADTRG P96/ANEX1 P95/ANEX0 76 77 78 79 80 50 49 48 47 46 45 44 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 M16C/30L Group 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 97 98 99 100 28 27 26 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 P94 P93 P92/TB2IN P91/TB1IN P90 BYTE CNVss P87/XCIN P86/XCOUT RESET XOUT VSS XIN VCC P85/NMI P84/INT2 P83/INT1 P82/INT0 P81 P80 P77 P76 P75/TA2IN P74/TA2OUT P73/CTS2/RTS2/TA1IN 1 2 P42/A18 P43/A19 P44/CS0 P45/CS1 P46/CS2 P47/CS3 P50/WRL/WR P51/WRH/BHE P52/RD P53/BCLK P54/HLDA P55/HOLD P56/ALE P57/RDY/CLKOUT P60/CTS0/RTS0 P61/CLK0 P62/RxD0 P63/TXD0 P64/CTS1/RTS1/CLKS1 P65/CLK1 P66/RxD1 P67/TXD1 P70/TXD2/SDA/TA0OUT (Note) P71/RxD2/SCL/TA0IN (Note) P72/CLK2/TA1OUT Note: P70 and P71 are N channel open-drain output pin. Package: 100P6Q-A Figure 1.1.2. Pin configuration (top view) 3 Mitsubishi microcomputers M16C / 30L Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Description Block Diagram Figure 1.1.3 is a block diagram of the M16C/30L group. 8 I/O ports Port P0 8 8 Port P1 Port P2 8 Port P3 Port P4 Port P5 Expandable up to 10 channels) XIN-XOUT XCIN-XCOUT UART/clock synchronous SI/O (8 bits X 3 channels) (15 bits) (1 channel) Figure 1.1.3. Block diagram of M16C/30L group ISP USP Vector table INTB Flag register FLG RAM (Note 2) Multiplier 8 Note 1: ROM size depends on MCU type. Note 2: RAM size depends on MCU type. Stack pointer ROM (Note 1) Port P10 SB PC 8 DMAC Program counter Port P9 Watchdog timer R0H R0L R0H R0L R1H R1L R1H R1L R2 R2 R3 R3 A0 A0 A1 A1 FB FB Memory Port P85 Registers AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAA AAAA 7 (10 bits X 8 channels Timer TA0 (16 bits) Timer TA1 (16 bits) Timer TA2 (16 bits) Timer TB1 (16 bits) Timer TB2 (16 bits) 8 System clock generator Port P6 Port P8 A-D converter Timer M16C/60 series16-bit CPU core 4 8 8 Port P7 Internal peripheral functions 8 Mitsubishi microcomputers M16C / 30L Group Description SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Performance Outline Table 1.1.1 is a performance outline of M16C/30L group. Table 1.1.1. Performance outline of M16C/30L group Item Number of basic instructions Shortest instruction execution time Memory capacity I/O port Input port Multifunction timer Serial I/O A-D converter ROM RAM P0 to P10 (except P85) P85 TA0, TA1, TA2 TB1, TB2 UART0, UART1, UART2 DMAC Watchdog timer Interrupt Clock generating circuit Supply voltage Power consumption I/O I/O withstand voltage characteristics Output current Memory expansion Device configuration Package Performance 91 instructions 62.5ns(f(XIN)=16MHZ, VCC=3.0V to 3.6V) 142.9ns(f(XIN)=7MHZ, VCC=2.4V to 3.6V, without software wait) (See the figure 1.1.4. ROM Expansion) 2K to 3K bytes 8 bits x 10, 7 bits x 1 1 bit x 1 16 bits x 3 16 bits x 2 (UART or clock synchronous) x 3 10 bits x (8+2) channels 1 channels (trigger: 14 sources) 15 bits x 1 (with prescaler) 16 internal and 5 external sources, 4 software sources, 7 levels 2 built-in clock generation circuits (built-in feedback resistor, and external ceramic or quartz oscillator) 3.0V to 3.6V (f(XIN)=16MHZ, without software wait) 2.4V to 3.6V (f(XIN)=7MHZ, without software wait) 2.2V to 3.6V (f(XIN)=7MHZ, with software one-wait) 34.0mW (VCC=3V, f(XIN)=10MHZ, without software wait) 66.0mW (VCC=3.3V, f(XIN)=16MHZ, without software wait) 3.3V 1mA Available (to a maximum of 1M bytes) CMOS high performance silicon gate 100-pin plastic mold QFP 5 Mitsubishi microcomputers M16C / 30L Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Description Mitsubishi plans to release the following products in the M16C/30L group: (1) Support for mask ROM version (2) ROM capacity (3) Package 100P6S-A : Plastic molded QFP 100P6Q-A : Plastic molded QFP ROM Size (Byte) 128K M30302MCL-XXXFP/GP 96K M30302MAL-XXXFP/GP 64K M30302M8L-XXXFP/GP Mask ROM version Figure 1.1.4. ROM expansion The M16C/30L group products currently supported are listed in Table 1.1.2. Table 1.1.2. M16C/30L group Type No. ROM capacity RAM capacity M30302M8L-XXXFP ** M30302M8L-XXXGP ** 64K byte M30302MAL-XXXFP ** M30302MAL-XXXGP ** 96K byte M30302MCL-XXXFP * M30302MCL-XXXGP * 128K byte **: Under development * : New product 6 June, 2002 2K byte Package type Remarks 100P6S-A 100P6Q-A 100P6S-A 100P6Q-A 3K byte 100P6S-A 100P6Q-A Mask ROM version Mitsubishi microcomputers M16C / 30L Group Description Type No. SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER M30302 M 8 L– XXX GP Package type: FP : Package GP : 100P6S-A 100P6Q-A ROM No. ROM capacity: 8 : 64K bytes A : 96K bytes C : 128K bytes Memory type: M : Mask ROM version Shows RAM capacity, pin count, etc (The value itself has no specific meaning) M16C/30 Group M16C Family Figure 1.1.5. Type No., memory size, and package 7 Mitsubishi microcomputers M16C / 30L Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Pin Description Pin Description Pin name Signal name Function VCC, VSS Power supply input CNVSS CNVSS Input This pin switches between processor modes. Connect this pin to the VSS pin when after a reset you want to start operation in single-chip mode (memory expansion mode) or the VCC pin when starting operation in microprocessor mode. RESET Reset input Input A “L” on this input resets the microcomputer. XIN Clock input Input XOUT Clock output Output These pins are provided for the main clock generating circuit.Connect a ceramic resonator or crystal between the XIN and the XOUT pins. To use an externally derived clock, input it to the XIN pin and leave the XOUT pin open. BYTE External data bus width select input Input AVCC Analog power supply input This pin is a power supply input for the A-D converter. Connect this pin to VCC. AVSS Analog power supply input This pin is a power supply input for the A-D converter. Connect this pin to VSS. VREF Reference voltage input Input This pin is a reference voltage input for the A-D converter. P00 to P07 I/O port P0 Input/output This is an 8-bit CMOS I/O port. It has an input/output port direction register that allows the user to set each pin for input or output individually. When used for input in single-chip mode, the port can be set to have or not have a pull-up resistor in units of four bits by software. In memory expansion and microprocessor modes, selection of the internal pull-resistor is not available. Input/output When set as a separate bus, these pins input and output data (D0–D7). Input/output This is an 8-bit I/O port equivalent to P0. Input/output When set as a separate bus, these pins input and output data (D8–D15). Input/output This is an 8-bit I/O port equivalent to P0. A0 to A7 Output These pins output 8 low-order address bits (A0–A7). A0/D0 to A7/D7 Input/output If the external bus is set as an 8-bit wide multiplexed bus, these pins input and output data (D0–D7) and output 8 low-order address bits (A0–A7) separated in time by multiplexing. A0 A1/D0 to A7/D6 Output Input/output If the external bus is set as a 16-bit wide multiplexed bus, these pins input and output data (D0–D6) and output address (A1–A7) separated in time by multiplexing. They also output address (A0). Input/output This is an 8-bit I/O port equivalent to P0. A8 to A15 Output These pins output 8 middle-order address bits (A8–A15). A8/D7, A9 to A15 Input/output Output If the external bus is set as a 16-bit wide multiplexed bus, these pins input and output data (D7) and output address (A8) separated in time by multiplexing. They also output address (A9–A15). Input/output This is an 8-bit I/O port equivalent to P0. Output Output These pins output A16–A19 and CS0–CS3 signals. A16–A19 are 4 highorder address bits. CS0–CS3 are chip select signals used to specify an access space. D0 to D7 P10 to P17 I/O port P1 D8 to D15 P20 to P27 P30 to P37 P40 to P47 A16 to A19, CS0 to CS3 8 I/O type I/O port P2 I/O port P3 I/O port P4 Supply 2.2V to 3.6 V to the VCC pin. Supply 0 V to the VSS pin. This pin selects the width of an external data bus. A 16-bit width is selected when this input is “L”; an 8-bit width is selected when this input is “H”. This input must be fixed to either “H” or “L”. Connect this pin to the VSS pin when not using external data bus. Mitsubishi microcomputers M16C / 30L Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Pin Description Pin Description Pin name Signal name I/O type Function Input/output This is an 8-bit I/O port equivalent to P0. In single-chip mode, P57 in this port outputs a divide-by-8 or divide-by-32 clock of XIN or a clock of the same frequency as XCIN as selected by software. WRL / WR, WRH / BHE, RD, BCLK, HLDA, HOLD, Output Output Output Output Output Input ALE, RDY Output Input Output WRL, WRH (WR and BHE), RD, BCLK, HLDA, and ALE signals. WRL and WRH, and BHE and WR can be switched using software control. WRL, WRH, and RD selected With a 16-bit external data bus, data is written to even addresses when the WRL signal is “L” and to the odd addresses when the WRH signal is “L”. Data is read when RD is “L”. WR, BHE, and RD selected Data is written when WR is “L”. Data is read when RD is “L”. Odd addresses are accessed when BHE is “L”. Use this mode when using an 8-bit external data bus. While the input level at the HOLD pin is “L”, the microcomputer is placed in the hold state. While in the hold state, HLDA outputs a “L” level. ALE is used to latch the address. While the input level of the RDY pin is “L”, the microcomputer is in the ready state. P50 to P57 I/O port P5 P60 to P67 I/O port P6 Input/output This is an 8-bit I/O port equivalent to P0. When used for input in singlechip, memory expansion, and microprocessor modes, the port can be set to have or not have a pull-up resistor in units of four bits by software. Pins in this port also function as UART0 and UART1 I/O pins as selected by software. P70 to P77 I/O port P7 Input/output This is an 8-bit I/O port equivalent to P6 (P70 and P71 are N channel open-drain output). Pins in this port also function as timer A0–A2, or UART2 I/O pins as selected by software. P80 to P84, P86, I/O port P8 Input/output Input/output P80 to P84, P86, and P87 are I/O ports with the same functions as P6. Using software, they can be made to function as the I/O pins for the input pins for external interrupts. P86 and P87 can be set using software to function as the I/O pins for a sub clock generation circuit. In this case, connect a quartz oscillator between P86 (XCOUT pin) and P87 (XCIN pin). P85 is an input-only port that also functions for NMI. The NMI interrupt is generated when the input at this pin changes from “H” to “L”. The NMI function cannot be cancelled using software. The pull-up cannot be set for this pin. Input/output P87, P85 I/O port P85 Input P90 to P97 I/O port P9 Input/output This is an 8-bit I/O port equivalent to P6. Pins in this port also function as, timer B1, B2 input pins, A-D converter extended input pins, or A-D trigger input pins as selected by software. P100 to P107 I/O port P10 Input/output This is an 8-bit I/O port equivalent to P6. Pins in this port also function as A-D converter input pins as selected by software. Furthermore, P104 –P107 also function as input pins for the key input interrupt function. 9 Mitsubishi microcomputers M16C / 30L Group Memory SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Operation of Functional Blocks The M16C/30L group accommodates certain units in a single chip. These units include ROM and RAM to store instructions and data and the central processing unit (CPU) to execute arithmetic/logic operations. Also included are peripheral units such as timers, serial I/O, DMAC, A-D converter, and I/O ports. The following explains each unit. Memory Figure 1.3.1 is a memory map of the M16C/30L group. The address space extends the 1M bytes from address 0000016 to FFFFF16. From FFFFF16 down is ROM. For example, in the M30302MCL-XXXGP, there is 128K bytes of internal ROM from E000016 to FFFFF16. The vector table for fixed interrupts such as _______ the reset and NMI are mapped to FFFDC16 to FFFFF16. The starting address of the interrupt routine is stored here. The address of the vector table for timer interrupts, etc., can be set as desired using the internal register (INTB). See the section on interrupts for details. From 0040016 up is RAM. For example, in the M30302MCL-XXXGP, 3K bytes of internal RAM is mapped to the space from 0040016 to 00FFF16. In addition to storing data, the RAM also stores the stack used when calling subroutines and when interrupts are generated. The SFR area is mapped to 0000016 to 003FF16. This area accommodates the control registers for peripheral devices such as I/O ports, A-D converter, serial I/O, and timers, etc. Figures 1.6.1 to 1.6.3 are location of peripheral unit control registers. Any part of the SFR area that is not occupied is reserved and cannot be used for other purposes. The special page vector table is mapped to FFE0016 to FFFDB16. If the starting addresses of subroutines or the destination addresses of jumps are stored here, subroutine call instructions and jump instructions can be used as 2-byte instructions, reducing the number of program steps. In memory expansion mode and microprocessor mode, a part of the spaces are reserved and cannot be used. For example, in the M30302MCL-XXXGP, the following spaces cannot be used. • The space between 0180016 and 03FFF16 (Memory expansion and microprocessor modes) • The space between D000016 and DFFFF16 (Memory expansion mode) 0000016 SFR area For details, see Figures 1.6.1 to 1.6.3 FFE0016 0040016 Internal RAM area Special page vector table XXXXX16 AAAAAA AAAAAA AAAAAA AAAAAA Internal reserved area (Note 1) 0400016 RAM size Address XXXXX16 2K bytes 00BFF16 3K bytes 00FFF16 ROM size Address YYYYY16 64K bytes F000016 96K bytes E800016 128K bytes E000016 External area D000016 FFFDC16 Undefined instruction FFFFF16 BRK instruction Address match Single step Watchdog timer DBC NMI Reset Overflow Internal reserved area (Note 2) YYYYY16 Internal ROM area FFFFF16 Note 1: During memory expansion and microprocessor modes, can not be used. Note 2: In memory expansion mode, can not be used. Figure 1.3.1. Memory map 10 Mitsubishi microcomputers M16C / 30L Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER CPU Central Processing Unit (CPU) The CPU has a total of 13 registers shown in Figure 1.4.1. Seven of these registers (R0, R1, R2, R3, A0, A1, and FB) come in two sets; therefore, these have two register banks. AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA b15 R0(Note) b8 b7 b15 R1(Note) b15 R3(Note) b15 A0(Note) b15 FB(Note) b19 b0 L Program counter Data registers b19 INTB b0 Interrupt table register L H b15 b0 b0 User stack pointer USP b15 b0 b0 b0 PC b0 AAAAAAA AAAAAAA AAAAAAA b15 A1(Note) b8 b7 H b15 R2(Note) b0 L H b0 Interrupt stack pointer ISP Address registers b15 b0 Static base register SB b15 b0 Frame base registers b0 FLG Flag register A AAAAAAA AA A AA A AA AA AA A AAAAAAAAAAAAAA A AAAAAA IPL U I O B S Z D C Note: These registers consist of two register banks. Figure 1.4.1. Central processing unit register (1) Data registers (R0, R1, R1H, R2, and R3) Data registers (R0, R1, R2, and R3) are configured with 16 bits, and are used primarily for transfer and arithmetic/logic operations. Register R0 can be used as separate 8-bit data registers, R0H and R0L. Register R1 can be used as separate 8-bit data registers, R1H and R1L. In some instructions, registers R2 and R0, as well as R3 and R1 can use as 32-bit data registers (R2R0 or R3R1). (2) Address registers (A0 and A1) Address registers (A0 and A1) are configured with 16 bits, and have functions equivalent to those of data registers. These registers can also be used for address register indirect addressing and address register relative addressing. In some instructions, registers A1 and A0 can be combined for use as a 32-bit address register (A1A0). 11 Mitsubishi microcomputers M16C / 30L Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER CPU (3) Frame base register (FB) Frame base register (FB) is configured with 16 bits, and is used for FB relative addressing. (4) Program counter (PC) Program counter (PC) is configured with 20 bits, indicating the address of an instruction to be executed. (5) Interrupt table register (INTB) Interrupt table register (INTB) is configured with 20 bits, indicating the start address of an interrupt vector table. (6) Stack pointer (USP or ISP) Stack pointer comes in two types: user stack pointer (USP) and interrupt stack pointer (ISP), each configured with 16 bits. Your desired type of stack pointer (USP or ISP) can be selected by a stack pointer select flag (U flag). This flag is located at the position of bit 7 in the flag register (FLG). (7) Static base register (SB) Static base register (SB) is configured with 16 bits, and is used for SB relative addressing. (8) Flag register (FLG) Flag register (FLG) is configured with 11 bits, each bit is used as a flag. Figure 1.4.2 shows the flag register (FLG). The following explains the function of each flag: • Bit 0: Carry flag (C flag) This flag retains a carry, borrow, or shift-out bit that has occurred in the arithmetic/logic unit. • Bit 1: Debug flag (D flag) This flag enables a single-step interrupt. When this flag is “1”, a single-step interrupt is generated after instruction execution. This flag is cleared to “0” when the interrupt is acknowledged. • Bit 2: Zero flag (Z flag) This flag is set to “1” when an arithmetic operation resulted in 0; otherwise, cleared to “0”. • Bit 3: Sign flag (S flag) This flag is set to “1” when an arithmetic operation resulted in a negative value; otherwise, cleared to “0”. • Bit 4: Register bank select flag (B flag) This flag chooses a register bank. Register bank 0 is selected when this flag is “0” ; register bank 1 is selected when this flag is “1”. • Bit 5: Overflow flag (O flag) This flag is set to “1” when an arithmetic operation resulted in overflow; otherwise, cleared to “0”. • Bit 6: Interrupt enable flag (I flag) This flag enables a maskable interrupt. An interrupt is disabled when this flag is “0”, and is enabled when this flag is “1”. This flag is cleared to “0” when the interrupt is acknowledged. 12 Mitsubishi microcomputers M16C / 30L Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER CPU • Bit 7: Stack pointer select flag (U flag) Interrupt stack pointer (ISP) is selected when this flag is “0” ; user stack pointer (USP) is selected when this flag is “1”. This flag is cleared to “0” when a hardware interrupt is acknowledged or an INT instruction of software interrupt Nos. 0 to 31 is executed. • Bits 8 to 11: Reserved area • Bits 12 to 14: Processor interrupt priority level (IPL) Processor interrupt priority level (IPL) is configured with three bits, for specification of up to eight processor interrupt priority levels from level 0 to level 7. If a requested interrupt has priority greater than the processor interrupt priority level (IPL), the interrupt is enabled. • Bit 15: Reserved area The C, Z, S, and O flags are changed when instructions are executed. See the software manual for details. AA AAAAAAA AA AA A AA AA AA A AA AAAAAAAAAAAAAA AA AA AA A AA b15 b0 IPL U I O B S Z D C Flag register (FLG) Carry flag Debug flag Zero flag Sign flag Register bank select flag Overflow flag Interrupt enable flag Stack pointer select flag Reserved area Processor interrupt priority level Reserved area Figure 1.4.2. Flag register (FLG) 13 Mitsubishi microcomputers M16C / 30L Group Reset SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Reset There are two kinds of resets; hardware and software. In both cases, operation is the same after the reset. (See “Software Reset” for details of software resets.) This section explains on hardware resets. When the supply voltage is in the range where operation is guaranteed, a reset is effected by holding the reset pin level “L” (0.2VCC max.) for at least 20 cycles. When the reset pin level is then returned to the “H” level while main clock is stable, the reset status is cancelled and program execution resumes from the address in the reset vector table. The RAM is undefined at power on. The initial value must therefore be set. When a reset signal is applied while the CPU is writing a value to the RAM, the value may be set as unknown due to the termination of the CPU access. Figure 1.5.1 shows the example reset circuit. Figure 1.5.2 shows the reset sequence. 3V 2.4V VCC 0V 3V VCC RESET RESET 0.48V 0V More than 20 cycles of XIN are needed. Example when VCC = 3V. Figure 1.5.1. Example reset circuit XIN More than 20 cycles are needed Microprocessor mode BYTE = “H” RESET BCLK 28cycles BCLK Content of reset vector Address FFFFC16 FFFFD16 FFFFE16 RD WR CS0 Microprocessor mode BYTE = “L” Address Content of reset vector FFFFC16 FFFFE16 RD WR CS0 Single chip mode Address Figure 1.5.2. Reset sequence 14 FFFFC16 Content of reset vector FFFFE16 Mitsubishi microcomputers M16C / 30L Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Reset ____________ Table 1.5.1 shows the statuses of the other pins while the RESET pin level is “L”. Figures 1.5.3 and 1.5.4 show the internal status of the microcomputer immediately after the reset is cancelled. ____________ Table 1.5.1. Pin status when RESET pin level is “L” Status Pin name CNVSS = VCC CNVSS = VSS BYTE = VSS BYTE = VCC P0 Input port (floating) Data input (floating) Data input (floating) P1 Input port (floating) Data input (floating) Input port (floating) P2, P3, P40 to P43 Input port (floating) Address output (undefined) Address output (undefined) P44 Input port (floating) CS0 output (“H” level is output) CS0 output (“H” level is output) P45 to P47 Input port (floating) Input port (floating) (pull-up resistor is on) Input port (floating) (pull-up resistor is on) P50 Input port (floating) WR output (“H” level is output) WR output (“H” level is output) P51 Input port (floating) BHE output (undefined) BHE output (undefined) P52 Input port (floating) RD output (“H” level is output) RD output (“H” level is output) P53 Input port (floating) BCLK output BCLK output P54 Input port (floating) HLDA output (The output value HLDA output (The output value depends on the input to the depends on the input to the HOLD pin) HOLD pin) P55 Input port (floating) HOLD input (floating) HOLD input (floating) P56 Input port (floating) ALE output (“L” level is output) ALE output (“L” level is output) P57 Input port (floating) RDY input (floating) RDY input (floating) Input port (floating) Input port (floating) P6, P7, P80 to P84, P86, P87, P9, P10 Input port (floating) 15 Mitsubishi microcomputers M16C / 30L Group Reset SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER (1) Processor mode register 0 (Note) (000416)··· 0016 (005316)··· ? 0 0 0 (2) Processor mode register 1 (000516)··· 0 0 0 0 0 0 (21) UART1 receive interrupt control register (005416)··· ? 0 0 0 (3) System clock control register 0 (000616)··· 0 1 0 0 1 0 0 0 (22) Timer A0 interrupt control register (005516)··· ? 0 0 0 (4) System clock control register 1 (000716)··· 0 0 1 0 0 0 0 0 (23) Timer A1 interrupt control register (005616)··· ? 0 0 0 (5) Chip select control register (000816)··· 0 0 0 0 0 0 0 1 (24) Timer A2 interrupt control register (005716)··· ? 0 0 0 (6) Address match interrupt enable register (000916)··· 0 0 (25) Timer B1 interrupt control register (005B16)··· ? 0 0 0 (7) Protect register (000A16)··· 0 0 0 (26) Timer B2 interrupt control register (005C16)··· ? 0 0 0 (8) Watchdog timer control register (000F16)··· 0 0 0 ? ? ? ? ? (27) INT0 interrupt control register (005D16)··· 0 0 ? 0 0 0 (9) Address match interrupt register 0 (001016)··· 0016 (28) INT1 interrupt control register (005E16)··· 0 0 ? 0 0 0 (001116)··· 0016 (29) INT2 interrupt control register (005F16)··· 0 0 ? 0 0 0 (30) Interrupt cause select register (035F16)··· 0016 (001216)··· (10) Address match interrupt register 1 0 0 0 0 (001416)··· 0016 (31) UART2 special mode register 3 (037516)··· 0016 (001516)··· 0016 (32) UART2 special mode register 2 (037616)··· 0016 (33) UART2 special mode register (037716)··· 8016 (34) UART2 transmit/receive mode register (037816)··· 0016 (001616)··· (11) DMA0 control register 0 (20) UART1 transmit interrupt control register 0 0 0 0 (002C16)··· 0 0 0 0 0 ? 0 0 (12) Bus collision detection interrupt control register (13) DMA0 interrupt control register (004A16)··· ? 0 0 0 (35) UART2 transmit/receive control register 0 (037C16)··· 0 0 0 0 1 0 0 0 (004B16)··· ? 0 0 0 (36) UART2 transmit/receive control register 1 (037D16)··· 0 0 0 0 0 0 1 0 (14) Key input interrupt control register (004D16)··· ? 0 0 0 (37) Count start flag (038016)··· (15) A-D conversion interrupt control register (004E16)··· ? 0 0 0 (38) Clock prescaler reset flag (038116)··· 0 (16) UART2 transmit interrupt control register (004F16)··· ? 0 0 0 (39) One-shot start flag (038216)··· 0 0 0 0 0 0 0 (17) UART2 receive interrupt control register (005016)··· ? 0 0 0 (40) Trigger select flag (038316)··· 0016 (18) UART0 transmit interrupt control register (005116)··· ? 0 0 0 (41) Up-down flag (038416)··· 0016 (19) UART0 receive interrupt control register (005216)··· ? 0 0 0 x : Nothing is mapped to this bit ? : Undefined The content of other registers are undefined when the microcomputer is reset. The initial values must therefore be set. The RAM is undefined at power on. The initial values must therefore be set. When a reset signal is applied while the CPU is writing a value to the RAM, the value may be set as unknown due to the termination of the CPU access. Note: When the VCC level is applied to the CNVSS pin, it is 0316 at a reset. Figure 1.5.3. Device's internal status after a reset is cleared 16 0016 Mitsubishi microcomputers M16C / 30L Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Reset (42) Timer A0 mode register (039616)··· 0016 (62) Port P4 direction register (03EA16)··· 0016 (43) Timer A1 mode register (039716)··· 0016 (63) Port P5 direction register (03EB16)··· 0016 (44) Timer A2 mode register (039816)··· 0016 (64) Port P6 direction register (03EE16)··· 0016 (45) Timer B1 mode register (039C16)··· 0 0 ? 0 0 0 0 (65) Port P7 direction register (03EF16)··· 0016 (46) Timer B2 mode register (039D16)··· 0 0 ? 0 0 0 0 (66) Port P8 direction register (03F216)··· 0 0 0 0 0 0 0 (47) UART0 transmit/receive mode register (03A016)··· (67) Port P9 direction register (03F316)··· 0016 (48) UART0 transmit/receive control register 0 (03A416)··· 0 0 0 0 1 0 0 0 (68) Port P10 direction register (03F616)··· 0016 (49) UART0 transmit/receive control register 1 (03A516)··· 0 0 0 0 0 0 1 0 (69) Pull-up control register 0 (03FC16)··· 0016 (70) Pull-up control register 1(Note) (03FD16)··· 0016 (51) UART1 transmit/receive control register 0 (03AC16)··· 0 0 0 0 1 0 0 0 (71) Pull-up control register 2 (03FE16)··· 0016 (52) UART1 transmit/receive control register 1 (03AD16)··· 0 0 0 0 0 0 1 0 (72) Port control register (03FF16)··· 0016 (50) UART1 transmit/receive mode register (03A816)··· (53) UART transmit/receive control register 2 (03B016)··· (54) DMA0 cause select register (03B816)··· 0016 0016 0 0 0 0 0 0 0 0016 (73) Data registers (R0/R1/R2/R3) 000016 (74) Address registers (A0/A1) 000016 (55) A-D control register 2 (03D416)··· 0 0 0 0 ? ? ? 0 (75) Frame base register (FB) (56) A-D control register 0 (03D616)··· 0 0 0 0 0 ? ? ? (76) Interrupt table register (INTB) 0000016 (57) A-D control register 1 (03D716)··· 0016 (77) User stack pointer (USP) 000016 (58) Port P0 direction register (03E216)··· 0016 (78) Interrupt stack pointer (ISP) 000016 000016 000016 (59) Port P1 direction register (03E316)··· 0016 (79) Static base register (SB) (60) Port P2 direction register (03E616)··· 0016 (80) Flag register (FLG) (61) Port P3 direction register (03E716)··· 0016 000016 x : Nothing is mapped to this bit ? : Undefined The content of other registers are undefined when the microcomputer is reset. The initial values must therefore be set. The RAM is undefined at power on. The initial values must therefore be set. When a reset signal is applied while the CPU is writing a value to the RAM, the value may be set as unknown due to the termination of the CPU access. Note: When the VCC level is applied to the CNVSS pin, it is 0216 at a reset. Figure 1.5.4. Device's internal status after a reset is cleared 17 Mitsubishi microcomputers M16C / 30L Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER SFR 000016 004016 000116 004116 000216 004216 000316 000416 000516 000616 000716 000816 000916 000A16 004316 Processor mode register 0 (PM0) Processor mode register 1(PM1) System clock control register 0 (CM0) System clock control register 1 (CM1) Chip select control register (CSR) Address match interrupt enable register (AIER) Protect register (PRCR) 004416 004516 004616 004716 004816 004916 000B16 000C16 004A16 Bus collision detection interrupt control register (BCNIC) 000D16 004B16 DMA0 interrupt control register (DM0IC) 000E16 000F16 Watchdog timer start register (WDTS) Watchdog timer control register (WDC) 001016 001116 004C16 004D16 004E16 Address match interrupt register 0 (RMAD0) 004F16 001216 005016 001316 005116 001416 001516 005216 Address match interrupt register 1 (RMAD1) 005316 001616 005416 001716 005516 001816 005616 001916 005716 001A16 005816 001B16 005916 001C16 005A16 001D16 005B16 001E16 005C16 001F16 005D16 005E16 002016 002116 DMA0 source pointer (SAR0) 005F16 002216 006016 002316 006116 DMA0 destination pointer (DAR0) Timer B1 interrupt control register (TB1IC) Timer B2 interrupt control register (TB2IC) INT0 interrupt control register (INT0IC) INT1 interrupt control register (INT1IC) INT2 interrupt control register (INT2IC) 006316 006516 002716 002916 Timer A0 interrupt control register (TA0IC) Timer A1 interrupt control register (TA1IC) Timer A2 interrupt control register (TA2IC) 006416 002616 002816 UART2 transmit interrupt control register (S2TIC) UART2 receive interrupt control register (S2RIC) UART0 transmit interrupt control register (S0TIC) UART0 receive interrupt control register (S0RIC) UART1 transmit interrupt control register (S1TIC) UART1 receive interrupt control register (S1RIC) 006216 002416 002516 Key input interrupt control register (KUPIC) A-D conversion interrupt control register (ADIC) DMA0 transfer counter (TCR0) 002A16 002B16 002C16 DMA0 control register (DM0CON) 032A16 002D16 032B16 002E16 032C16 002F16 032D16 003016 032E16 003116 032F16 003216 033016 003316 033116 003416 033216 003516 033316 003616 033416 003716 033516 003816 033616 003916 033716 003A16 033816 003B16 033916 003C16 033A16 003D16 033B16 003E16 033C16 003F16 033D16 033E16 033F16 Note : Locations in the SFR area where nothing is allocated are reserved areas. Do not access these areas for read or write. Figure 1.6.1. Location of peripheral unit control registers (1) 18 Mitsubishi microcomputers M16C / 30L Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER SFR 034016 038016 034116 038116 034216 038216 034316 038316 034416 038416 034516 038516 034616 038616 034716 038716 034816 038816 034916 038916 034A16 038A16 034B16 038B16 034C16 038C16 034D16 038D16 034E16 038E16 034F16 038F16 035016 039016 035116 039116 035216 039216 035316 039316 035416 039416 035516 039516 035616 039616 035716 039716 035816 039816 035916 039916 035A16 039A16 035B16 039B16 035C16 039C16 035D16 039D16 Timer A0 register (TA0) Timer A1 register (TA1) Timer A2 register (TA2) Timer B1 register (TB1) Timer B2 register (TB2) Timer A0 mode register (TA0MR) Timer A1 mode register (TA1MR) Timer A2 mode register (TA2MR) Timer B1 mode register (TB1MR) Timer B2 mode register (TB2MR) 039E16 035E16 035F16 Count start flag (TABSR) Clock prescaler reset flag (CPSRF) One-shot start flag (ONSF) Trigger select register (TRGSR) Up-down flag (UDF) Interrupt cause select register (IFSR) 039F16 036016 03A016 UART0 transmit/receive mode register (U0MR) 036116 03A116 UART0 bit rate generator (U0BRG) 036216 03A216 036316 03A316 036416 03A416 036516 03A516 036616 03A616 036716 03A716 036816 03A816 UART1 transmit/receive mode register (U1MR) 036916 03A916 UART1 bit rate generator (U1BRG) 036A16 03AA16 036B16 03AB16 036C16 03AC16 036D16 03AD16 036E16 03AE16 036F16 03AF16 037016 03B016 037116 03B116 037216 03B216 037316 03B316 037616 037716 037816 037916 037A16 037B16 037C16 037D16 037E16 037F16 UART0 transmit/receive control register 0 (U0C0) UART0 transmit/receive control register 1 (U0C1) UART0 receive buffer register (U0RB) UART1 transmit buffer register (U1TB) UART1 transmit/receive control register 0 (U1C0) UART1 transmit/receive control register 1 (U1C1) UART1 receive buffer register (U1RB) UART transmit/receive control register 2 (UCON) 03B416 037416 037516 UART0 transmit buffer register (U0TB) UART2 special mode register 3(U2SMR3) UART2 special mode register 2(U2SMR2) UART2 special mode register (U2SMR) 03B516 UART2 transmit/receive mode register (U2MR) UART2 bit rate generator (U2BRG) 03B816 UART2 transmit buffer register (U2TB) UART2 transmit/receive control register 0 (U2C0) UART2 transmit/receive control register 1 (U2C1) UART2 receive buffer register (U2RB) 03B616 03B716 DMA0 request cause select register (DM0SL) 03B916 03BA16 03BB16 03BC16 03BD16 03BE16 03BF16 Note : Locations in the SFR area where nothing is allocated are reserved areas. Do not access these areas for read or write. Figure 1.6.2. Location of peripheral unit control registers (2) 19 Mitsubishi microcomputers M16C / 30L Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER SFR 03C016 03C116 03C216 03C316 03C416 03C516 03C616 03C716 03C816 03C916 03CA16 03CB16 03CC16 03CD16 03CE16 03CF16 A-D register 0 (AD0) A-D register 1 (AD1) A-D register 2 (AD2) A-D register 3 (AD3) A-D register 4 (AD4) A-D register 5 (AD5) A-D register 6 (AD6) A-D register 7 (AD7) 03D016 03D116 03D216 03D316 03D416 A-D control register 2 (ADCON2) 03D516 03D616 03D716 A-D control register 0 (ADCON0) A-D control register 1 (ADCON1) 03D816 03D916 03DA16 03DB16 03DC16 03DD16 03DE16 03DF16 03E016 03E116 03E216 03E316 03E416 03E516 03E616 03E716 03E816 03E916 03EA16 03EB16 03EC16 03ED16 03EE16 03EF16 03F016 03F116 03F216 03F316 03F416 Port P0 register (P0) Port P1 register (P1) Port P0 direction register (PD0) Port P1 direction register (PD1) Port P2 register (P2) Port P3 register (P3) Port P2 direction register (PD2) Port P3 direction register (PD3) Port P4 register (P4) Port P5 register (P5) Port P4 direction register (PD4) Port P5 direction register (PD5) Port P6 register (P6) Port P7 register (P7) Port P6 direction register (PD6) Port P7 direction register (PD7) Port P8 register (P8) Port P9 register (P9) Port P8 direction register (PD8) Port P9 direction register (PD9) Port P10 register (P10) 03F516 03F616 Port P10 direction register (PD10) 03F716 03F816 03F916 03FA16 03FB16 03FC16 03FD16 03FE16 03FF16 Pull-up control register 0 (PUR0) Pull-up control register 1 (PUR1) Pull-up control register 2 (PUR2) Port control register (PCR) Note : Locations in the SFR area where nothing is allocated are reserved areas. Do not access these areas for read or write. Figure 1.6.3. Location of peripheral unit control registers (3) 20 Mitsubishi microcomputers M16C / 30L Group Software Reset SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Software Reset Writing “1” to bit 3 of the processor mode register 0 (address 000416) applies a (software) reset to the microcomputer. A software reset has the same effect as a hardware reset. The contents of internal RAM are preserved. Processor Mode (1) Types of Processor Mode One of three processor modes can be selected: single-chip mode, memory expansion mode, and microprocessor mode. The functions of some pins, the memory map, and the access space differ according to the selected processor mode. • Single-chip mode In single-chip mode, only internal memory space (SFR, internal RAM, and internal ROM) can be accessed. However, after the reset has been released and the operation of shifting from the microprocessor mode has started (“H” applied to the CNVSS pin), the internal ROM area cannot be accessed even if the CPU shifts to the single-chip mode. Ports P0 to P10 can be used as programmable I/O ports or as I/O ports for the internal peripheral functions. • Memory expansion mode In memory expansion mode, external memory can be accessed in addition to the internal memory space (SFR, internal RAM, and internal ROM). However, after the reset has been released and the operation of shifting from the microprocessor mode has started (“H” applied to the CNVSS pin), the internal ROM area cannot be accessed even if the CPU shifts to the memory expansion mode. In this mode, some of the pins function as the address bus, the data bus, and as control signals. The number of pins assigned to these functions depends on the bus and register settings. (See “Bus Settings” for details.) • Microprocessor mode In microprocessor mode, the SFR, internal RAM, and external memory space can be accessed. The internal ROM area cannot be accessed. In this mode, some of the pins function as the address bus, the data bus, and as control signals. The number of pins assigned to these functions depends on the bus width and register settings. (See “Bus Settings” for details.) (2) Setting Processor Modes The processor mode is set using the CNVSS pin and the processor mode bits (bits 1 and 0 at address 000416). Do not set the processor mode bits to “102”. Regardless of the level of the CNVSS pin, changing the processor mode bits selects the mode. Therefore, never change the processor mode bits when changing the contents of other bits. Do not change the processor mode bits simultaneously with other bits when changing the processor mode bits “012” or “112”. Change the processor mode bits after changing the other bits. Also do not attempt to shift to or from the microprocessor mode within the program stored in the internal ROM area. • Applying VSS to CNVSS pin The microcomputer begins operation in single-chip mode after being reset. Memory expansion mode is selected by writing “012” to the processor mode bits. • Applying VCC to CNVSS pin The microcomputer starts to operate in microprocessor mode after being reset. 21 Mitsubishi microcomputers M16C / 30L Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Processor Mode Figure 1.7.1 shows the processor mode register 0 and 1. Figure 1.7.2 shows the memory maps in each processor modes. Processor mode register 0 (Note 1) b7 b6 b5 b4 b3 b2 b1 b0 Symbol PM0 Address 000416 Bit symbol PM00 When reset 0016 (Note 2) Bit name Processor mode bit PM01 Function b1 b0 0 0: Single-chip mode 0 1: Memory expansion mode 1 0: Must not be set 1 1: Microprocessor mode A AA A AA A AA AA AA AA AA AA AA AA AA AA R W PM02 R/W mode select bit PM03 Software reset bit The device is reset when this bit is set to “1”. The value of this bit is “0” when read. PM04 Multiplexed bus space select bit b5 b4 PM06 Port P40 to P43 function select bit (Note 3) 0 : Address output 1 : Port function (Address is not output) PM07 BCLK output disable bit 0 : BCLK is output 1 : BCLK is not output (Pin is left floating) PM05 0 : RD,BHE,WR 1 : RD,WRH,WRL 0 0 : Multiplexed bus is not used 0 1 : Allocated to CS2 space 1 0 : Allocated to CS1 space 1 1 : Allocated to entire space (Note4) Note 1: Set bit 1 of the protect register (address 000A16) to “1” when writing new values to this register. Note 2: If the VCC voltage is applied to the CNVSS, the value of this register when reset is 0316. (PM00 and PM01 both are set to “1”.) Note 3: Valid in microprocessor and memory expansion modes. Note 4: If the entire space is of multiplexed bus in memory expansion mode, choose an 8bit width.The processor operates using the separate bus after reset is revoked, so the entire space multiplexed bus cannot be chosen in microprocessor mode. P31 to P37 become a port if the entire space multiplexed bus is chosen, so only 256 bytes can be used in each chip select. Processor mode register 1 (Note 1) b7 b6 b5 b4 b3 0 0 0 0 b2 b1 b0 0 Symbol PM1 Address 000516 Bit symbol Bit name When reset 000000X02 Function Must always be set to “0” Reserved bit Nothing is assigned. In an attempt to write to this bit, write “0”. The value, if read, turns out to be indeterminate. PM12 Watchdog timer function select bit 0 : Interrupt 1 : Reset (Note 2) Reserved bit Must always be set to “0” Reserved bit Must always be set to “0” Reserved bit Must always be set to “0” Must always be set to “0” Reserved bit PM17 Wait bit 0 : No wait state 1 : Wait state inserted AA R W AAA AAA AAA AAAA (Note 2) Note 1: Set bit 1 of the protect register (address 000A16) to “1” when writing new values to this register. Note 2: This bit can only be set to “1”. Figure 1.7.1. Processor mode register 0 and 1 22 Mitsubishi microcomputers M16C / 30L Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Processor Mode Single-chip mode Memory expansion mode Microprocessor mode 0000016 SFR area SFR area SFR area Internal RAM area Internal RAM area Internal RAM area Internally reserved area Internally reserved area External area External area 0040016 XXXXX16 0400016 Inhibited D000016 Internally reserved area YYYYY16 Internal ROM area Internal ROM area FFFFF16 RAM size Address XXXXX16 ROM size Address YYYYY16 2K bytes 00BFF16 64K bytes F000016 3K bytes 00FFF16 96K bytes E800016 128K bytes E000016 External area : Accessing this area allows the user to access a device connected externally to the microcomputer. Figure 1.7.2. Memory maps in each processor modes 23 Mitsubishi microcomputers M16C / 30L Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Bus Settings Bus Settings The BYTE pin and bits 4 to 6 of the processor mode register 0 (address 000416) are used to change the bus settings. Table 1.8.1 shows the factors used to change the bus settings. Table 1.8.1. Factors for switching bus settings Bus setting Switching external address bus width Switching external data bus width Switching between separate and multiplex bus Switching factor Bit 6 of processor mode register 0 BYTE pin Bits 4 and 5 of processor mode register 0 (1) Selecting external address bus width The address bus width for external output in the 1M bytes of address space can be set to 16 bits (64K bytes address space) or 20 bits (1M bytes address space). When bit 6 of the processor mode register 0 is set to “1”, the external address bus width is set to 16 bits, and P2 and P3 become part of the address bus. P40 to P43 can be used as programmable I/O ports. When bit 6 of processor mode register 0 is set to “0”, the external address bus width is set to 20 bits, and P2, P3, and P40 to P43 become part of the address bus. (2) Selecting external data bus width The external data bus width can be set to 8 or 16 bits. (Note, however, that only the separate bus can be set.) When the BYTE pin is “L”, the bus width is set to 16 bits; when “H”, it is set to 8 bits. (The internal bus width is permanently set to 16 bits.) While operating, fix the BYTE pin either to “H” or to “L”. (3) Selecting separate/multiplex bus The bus format can be set to multiplex or separate bus using bits 4 and 5 of the processor mode register 0. • Separate bus In this mode, the data and address are input and output separately. The data bus can be set using the BYTE pin to be 8 or 16 bits. When the BYTE pin is “H”, the data bus is set to 8 bits and P0 functions as the data bus and P1 as a programmable I/O port. When the BYTE pin is “L”, the data bus is set to 16 bits and P0 and P1 are both used for the data bus. When the separate bus is used for access, a software wait can be selected. • Multiplex bus In this mode, data and address I/O are time multiplexed. With the BYTE pin = “H”, the 8 bits from D0 to D7 are multiplexed with A0 to A7. With the BYTE pin = “L”, the 8 bits from D0 to D7 are multiplexed with A1 to A8. D8 to D15 are not multiplexed. In this case, the external devices connected to the multiplexed bus are mapped to the microcomputer’s even addresses (every 2nd address). To access these external devices, access the even addresses as bytes. The ALE signal latches the address. It is output from P56. Before using the multiplex bus for access, be sure to insert a software wait. If the entire space is of multiplexed bus in memory expansion mode, choose an 8-bit width. The processor operates using the separate bus after reset is revoked, so the entire space multiplexed bus cannot be chosen in microprocessor mode. P31 to P37 become a port if the entire space multiplexed bus is chosen, so only 256 bytes can be used in each chip select. 24 Mitsubishi microcomputers M16C / 30L Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Bus Settings Table 1.8.2. Pin functions for each processor mode Processor mode Single-chip mode Memory expansion mode/microprocessor modes “01”, “10” Multiplexed bus space select bit “00” Either CS1 or CS2 is for multiplexed bus and others are for separate bus Data bus width BYTE pin level 8 bits “H” 16 bits “L” (separate bus) 8 bits “H” Memory expansion mode “11” (Note 1) multiplexed bus for the entire space 16 bits “L” 8 bit “H” P00 to P07 I/O port Data bus Data bus Data bus Data bus I/O port P10 to P17 I/O port I/O port Data bus I/O port Data bus I/O port P20 I/O port Address bus Address bus /data bus(Note 2) Address bus Address bus Address bus /data bus P21 to P27 I/O port Address bus /data bus(Note 2) Address bus /data bus(Note 2) Address bus Address bus Address bus /data bus P30 I/O port Address bus Address bus Address bus Address bus A8/D7 /data bus(Note 2) P31 to P37 I/O port Address bus Address bus Address bus Address bus I/O port P40 to P43 Port P40 to P43 function select bit = 1 I/O port I/O port I/O port I/O port I/O port I/O port P40 to P43 Port P40 to P43 function select bit = 0 I/O port Address bus Address bus Address bus Address bus I/O port P44 to P47 I/O port CS (chip select) or programmable I/O port (For details, refer to “Bus control”) P50 to P53 I/O port Outputs RD, WRL, WRH, and BCLK or RD, BHE, WR, and BCLK (For details, refer to “Bus control”) P54 I/O port HLDA HLDA HLDA HLDA HLDA P55 I/O port HOLD HOLD HOLD HOLD HOLD P56 I/O port ALE ALE ALE ALE ALE P57 I/O port RDY RDY RDY RDY RDY Note 1: If the entire space is of multiplexed bus in memory expansion mode, choose an 8-bit width. The processor operates using the separate bus after reset is revoked, so the entire space multiplexed bus cannot be chosen in microprocessor mode. P31 to P37 become a port if the entire space multiplexed bus is chosen, so only 256 bytes can be used in each chip select. Note 2: Address bus when in separate bus mode. 25 Mitsubishi microcomputers M16C / 30L Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Bus Control Bus Control The following explains the signals required for accessing external devices and software waits. The signals required for accessing the external devices are valid when the processor mode is set to memory expansion mode and microprocessor mode. The software waits are valid in all processor modes. (1) Address bus/data bus The address bus consists of the 20 pins A0 to A19 for accessing the 1M bytes of address space. The data bus consists of the pins for data I/O. When the BYTE pin is “H”, the 8 ports D0 to D7 function as the data bus. When BYTE is “L”, the 16 ports D0 to D15 function as the data bus. When a change is made from single-chip mode to memory expansion mode, the value of the address bus is undefined until external memory is accessed. (2) Chip select signal The chip select signal is output using the same pins as P44 to P47. Bits 0 to 3 of the chip select control register (address 000816) set each pin to function as a port or to output the chip select signal. The chip select control register is valid in memory expansion mode and microprocessor mode. In single-chip mode, P44 to P47 function as programmable I/O ports regardless of the value in the chip select control register. _______ In microprocessor mode, only CS0 outputs the chip select signal after the reset state has been can_______ _______ celled. CS1 to CS3 function as input ports. Figure 1.9.1 shows the chip select control register. The chip select signal can be used to split the external area into as many as four blocks. Tables 1.9.1 shows the external memory areas specified using the chip select signal. Table 1.9.1. External areas specified by the chip select signals Chip select signal Processor mode CS0 Memory expansion mode Microprocessor mode 26 3000016 to CFFFF16 (640K bytes) 3000016 to FFFFF16 (832K bytes) CS1 CS2 CS3 2800016 to 2FFFF16 (32K bytes) 0800016 to 27FFF16 (128K bytes) 0400016 to 07FFF16 (16K bytes) Mitsubishi microcomputers M16C / 30L Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Bus Control Chip select control register b7 b6 b5 b4 b3 b2 b1 b0 Symbol CSR Address 000816 Bit name Bit symbol CS0 CS1 CS0 output enable bit CS1 output enable bit CS2 CS2 output enable bit CS3 CS3 output enable bit CS0W CS0 wait bit CS1W CS1 wait bit CS2W CS2 wait bit CS3W CS3 wait bit When reset 0116 Function 0 : Chip select output disabled (Normal port pin) 1 : Chip select output enabled 0 : Wait state inserted 1 : No wait state AA A AA A A A A AA AA A A AA A A AA RW Figure 1.9.1. Chip select control register The timing of the chip select signal changing to “L”(active) is synchronized with the address bus. But the timing of the chip select signal changing to “H” depends on the area which will be accessed in the next cycle. Figure 1.9.2 shows the output example of the address bus and chip select signal. 27 Mitsubishi microcomputers M16C / 30L Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Bus Control Example 1) After access the external area, both the address signal and the chip select signal change concurrently in the next cycle. Example 2) After access the external area, only the chip select signal changes in the next cycle (the address bus does not change). In this example, after access to the external area(i), an access to the area indicated by the other chip select signal(j) will occur in the next cycle. In this case, both the address bus and the chip select signal change between the two cycles. In this example, an access to the internal ROM or the internal RAM in the next cycle will occur, after access to the external area. In this case, the chip select signal changes between the two cycles, but the address does not change. Access to the Access to the Other External Area( i ) External Area( j ) BCLK Address bus Internal ROM/RAM Access BCLK Read/Write signal Data bus Access to the External Area Read/Write signal Data Data bus Address bus Address Chip select (CS i) Data Address Chip select Chip select (CS j) Example 3) After access the external area, only the address bus changes in the next cycle (the chip select signal does not change). Example 4) After access the external area, either the address signal and the chip select signal do not change in the next cycle. In this example, after access to the external area(i), an access to the area indicated by the same chip select signal(i) will occur in the next cycle. In this case, the address bus changes between the two cycles, but the chip select signal does not change. In this example, any access to any area does not occur in the next cycle (either instruction prefetch does not occur). In this case,either the address bus and chip select signal do not change between the two cycles. Access to the External Area( i ) BCLK Address bus Chip select (CS i) Access to the External Area No Access BCLK Read/Write signal Read/Write signal Data bus Access to the Same External Area( i ) Data Address Data bus Address bus Data Address Chip select Note : These examples show the address bus and chip select signal within the successive two cycles. According to the combination of these examples, the chip select can be elongated to over 2cycles. Figure 1.9.2. Output Examples about Address Bus and Chip Select Signal (Separated Bus without Wait) 28 Mitsubishi microcomputers M16C / 30L Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Bus Control (3) Read/write signals With a 16-bit data bus (BYTE pin =“L”), bit 2 of the processor mode register 0 (address 000416) select the _____ ________ ______ _____ ________ _________ combinations of RD, BHE, and WR signals or RD, WRL, and WRH signals. With an 8-bit data bus (BYTE _____ ______ _______ pin = “H”), use the combination of RD, WR, and BHE signals. (Set bit 2 of the processor mode register 0 (address 000416) to “0”.) Tables 1.9.3 and 1.9.4 show the operation of these signals. _____ ______ ________ After a reset has been cancelled, the combination of RD, WR, and BHE signals is automatically selected. _____ _________ _________ When switching to the RD, WRL, and WRH combination, do not write to external memory until bit 2 of the processor mode register 0 (address 000416) has been set (Note). Note: Before attempting to change the contents of the processor mode register 0, set bit 1 of the protect register (address 000A16) to “1”. _____ ________ _________ Table 1.9.3. Operation of RD, WRL, and WRH signals Data bus width 16-bit (BYTE = “L”) RD L H H H WRL H L H L _____ ______ Status of external data bus WRH H H L L Read data Write 1 byte of data to even address Write 1 byte of data to odd address Write data to both even and odd addresses ________ Table 1.9.4. Operation of RD, WR, and BHE signals Data bus width 16-bit (BYTE = “L”) 8-bit (BYTE = “H”) RD H L H L H L H L WR L H L H L H L H BHE L L H H L L Not used Not used A0 H H L L L L H/L H/L Status of external data bus Write 1 byte of data to odd address Read 1 byte of data from odd address Write 1 byte of data to even address Read 1 byte of data from even address Write data to both even and odd addresses Read data from both even and odd addresses Write 1 byte of data Read 1 byte of data (4) ALE signal The ALE signal latches the address when accessing the multiplex bus space. Latch the address when the ALE signal falls. When BYTE pin = “L” When BYTE pin = “H” ALE ALE D0/A0 to D7/A7 A8 to A19 Address Data (Note 1) A0 D0/A1 to D7/A8 Address Address Data (Note 1) Address (Note 2) A9 to A19 Address Note 1: Floating when reading. Note 2: When multiplexed bus for the entire space is selected, these are I/O ports. Figure 1.9.3. ALE signal and address/data bus 29 Mitsubishi microcomputers M16C / 30L Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Bus Control ________ (5) The RDY signal ________ RDY is a signal that facilitates access to an external device that requires long access time. As shown in ________ Figure 1.9.4, if an “L” is being input to the RDY at the BCLK falling edge, the bus turns to the wait state. If ________ an “H” is being input to the RDY pin at the BCLK falling edge, the bus cancels the wait state. Table 1.9.5 shows the state of the microcomputer with the bus in the wait state, and Figure 1.9.4 shows an example ____ ________ in which the RD signal is prolonged by the RDY signal. ________ The RDY signal is valid when accessing the external area during the bus cycle in which bits 4 to 7 of the ________ chip select control register (address 000816) are set to “0”. The RDY signal is invalid when setting “1” to ________ all bits 4 to 7 of the chip select control register (address 000816), but the RDY pin should be treated as properly as in non-using. Table 1.9.5. Microcomputer status in wait state (Note) Item Status Oscillation On ___ _____ ________ R/W signal, address bus, data bus, CS __________ ALE signal, HLDA, programmable I/O ports Internal peripheral circuits Maintain status when RDY signal received On ________ Note: The RDY signal cannot be received immediately prior to a software wait. In an instance of separate bus BCLK AAAA RD CSi (i=0 to 3) RDY tsu(RDY - BCLK) Accept timing of RDY signal In an instance of multiplexed bus BCLK AAAAAA AAAAAA RD CSi (i=0 to 3) RDY tsu(RDY - BCLK) AA AA : Wait using RDY signal Accept timing of RDY signal : Wait using software _____ ________ Figure 1.9.4. Example of RD signal extended by RDY signal 30 Mitsubishi microcomputers M16C / 30L Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Bus Control (6) Hold signal The hold signal is used to transfer the bus privileges from the CPU to the external circuits. Inputting “L” to __________ the HOLD pin places the microcomputer in the hold state at the end of the current bus access. This status __________ __________ is maintained and “L” is output from the HLDA pin as long as “L” is input to the HOLD pin. Table 1.9.6 shows the microcomputer status in the hold state. __________ Bus-using priorities are given to HOLD, DMAC, and CPU in order of decreasing precedence. __________ HOLD > DMAC > CPU Figure 1.9.5. Bus-using priorities Table 1.9.6. Microcomputer status in hold state Item Status Oscillation ON ___ _____ _______ R/W signal, address bus, data bus, CS, BHE Programmable I/O ports P0, P1, P2, P3, P4, P5 P6, P7, P8, P9, P10 Floating Floating Maintains status when hold signal is received __________ HLDA Internal peripheral circuits ALE signal Output “L” ON (but watchdog timer stops) Undefined (7) External bus status when the internal area is accessed Table 1.9.7 shows the external bus status when the internal area is accessed. Table 1.9.7. External bus status when the internal area is accessed Item SFR accessed Internal ROM/RAM accessed Address bus Address output Maintain status before accessed address of external area Data bus When read Floating Floating When write Output data Undefined RD, WR, WRL, WRH RD, WR, WRL, WRH output Output “H” BHE BHE output Maintain status before accessed status of external area CS Output “H” Output “H” ALE Output “L” Output “L” 31 Mitsubishi microcomputers M16C / 30L Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Bus Control (8) BCLK output The user can choose the BCLK output by use of bit 7 of processor mode register 0 (000416) (Note). When set to “1”, the output floating. Note: Before attempting to change the contents of the processor mode register 0, set bit 1 of the protect register (address 000A16) to “1”. (9) Software wait A software wait can be inserted by setting the wait bit (bit 7) of the processor mode register 1 (address 000516) (Note) and bits 4 to 7 of the chip select control register (address 000816). A software wait is inserted in the internal ROM/RAM area and in the external memory area by setting the wait bit of the processor mode register 1. When set to “0”, each bus cycle is executed in one BCLK cycle. When set to “1”, each bus cycle is executed in two or three BCLK cycles. After the microcomputer has been reset, this bit defaults to “0”. When set to “1”, a wait is applied to all memory areas (two or three BCLK cycles), regardless of the contents of bits 4 to 7 of the chip select control register. Set this bit after referring to the recommended operating conditions (main clock input oscillation frequency) of the electric character________ istics. However, when the user is using the RDY signal, the relevant bit in the chip select control register’s bits 4 to 7 must be set to “0”. When the wait bit of the processor mode register 1 is “0”, software waits can be set independently for each of the 4 areas selected using the chip select signal. Bits 4 to 7 of the chip select control register _______ _______ correspond to chip selects CS0 to CS3. When one of these bits is set to “1”, the bus cycle is executed in one BCLK cycle. When set to “0”, the bus cycle is executed in two or three BCLK cycles. These bits default to “0” after the microcomputer has been reset. The SFR area is always accessed in two BCLK cycles regardless of the setting of these control bits. Also, insert a software wait if using the multiplex bus to access the external memory area. Table 1.9.8 shows the software wait and bus cycles. Figure 1.9.6 shows example of bus timing when using software waits. Note: Before attempting to change the contents of the processor mode register 1, set bit 1 of the protect register (address 000A16) to “1”. Table 1.9.8. Software waits and bus cycles Area Wait bit Bits 4 to 7 of chip select control register Invalid Invalid 2 BCLK cycles 0 Invalid 1 BCLK cycle 1 Invalid 2 BCLK cycles Separate bus 0 1 1 BCLK cycle Separate bus 0 0 2 BCLK cycles Separate bus 1 0 (Note) 2 BCLK cycles Multiplex bus 0 0 3 BCLK cycles Multiplex bus 1 0 (Note) 3 BCLK cycles Bus status SFR Internal ROM/RAM External memory area Note: When using the RDY signal, always set to “0”. 32 Bus cycle Mitsubishi microcomputers M16C / 30L Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Bus Control < Separate bus (no wait) > Bus cycle (Note 1) Bus cycle (Note 1) BCLK Write signal Read signal Output Data bus Address bus (Note 2) Address Input Address Chip select (Note 2) < Separate bus (with wait) > Bus cycle (Note 1) Bus cycle (Note 1) BCLK Write signal Read signal Input Output Data bus Address Address Bus cycle (Note 1) Bus cycle (Note 1) Address Address Address bus (Note 2) Chip select (Note 2) < Multiplexed bus > BCLK Write signal Read signal ALE Address bus (Note 2) Address bus/ Data bus Address Data output Address Input Chip select (Note 2) Note 1: These example timing charts indicate bus cycle length. After this bus cycle sometimes come read and write cycles in succession. Note 2: The address bus and chip select may be extended depending on the CPU status such as that of the instruction queue buffer. Figure 1.9.6. Typical bus timings using software wait 33 Mitsubishi microcomputers M16C / 30L Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Clock Generating Circuit Clock Generating Circuit The clock generating circuit contains two oscillator circuits that supply the operating clock sources to the CPU and internal peripheral units. Table 1.10.1. Main clock and sub-clock generating circuits Use of clock Usable oscillator Pins to connect oscillator Oscillation stop/restart function Oscillator status immediately after reset Other Main clock generating circuit Sub-clock generating circuit • CPU’s operating clock source • CPU’s operating clock source • Internal peripheral units’ • Timer A/B’s count clock operating clock source source Ceramic or crystal oscillator Crystal oscillator XIN, XOUT XCIN, XCOUT Available Available Oscillating Stopped Externally derived clock can be input Example of oscillator circuit Figure 1.10.1 shows some examples of the main clock circuit, one using an oscillator connected to the circuit, and the other one using an externally derived clock for input. Figure 1.10.2 shows some examples of sub-clock circuits, one using an oscillator connected to the circuit, and the other one using an externally derived clock for input. Circuit constants in Figures 1.10.1 and 1.10.2 vary with each oscillator used. Use the values recommended by the manufacturer of your oscillator. Microcomputer Microcomputer (Built-in feedback resistor) (Built-in feedback resistor) XIN XIN XOUT XOUT Open (Note) Rd Externally derived clock CIN COUT Vcc Vss Note: Insert a damping resistor if required. The resistance will vary depending on the oscillator and the oscillation drive capacity setting. Use the value recommended by the maker of the oscillator. When the oscillation drive capacity is set to low, check that oscillation is stable. Also, if the oscillator manufacturer's data sheet specifies that a feedback resistor be added external to the chip, insert a feedback resistor between XIN and XOUT following the instruction. Figure 1.10.1. Examples of main clock Microcomputer Microcomputer (Built-in feedback resistor) (Built-in feedback resistor) XCIN XCOUT XCIN XCOUT Open (Note) RCd Externally derived clock CCIN CCOUT Vcc Vss Note: Insert a damping resistor if required. The resistance will vary depending on the oscillator and the oscillation drive capacity setting. Use the value recommended by the maker of the oscillator. When the oscillation drive capacity is set to low, check that oscillation is stable. Also, if the oscillator manufacturer's data sheet specifies that a feedback resistor be added external to the chip, insert a feedback resistor between XCIN and XCOUT following the instruction. Figure 1.10.2. Examples of sub-clock 34 Mitsubishi microcomputers M16C / 30L Group Clock Generating Circuit SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Clock Control Figure 1.10.3 shows the block diagram of the clock generating circuit. XCIN XCOUT fC32 1/32 f1 CM04 f1SIO2 fAD fC f8SIO2 f8 Sub clock f32SIO2 CM10 “1” Write signal f32 S Q XIN XOUT a RESET Software reset Main clock CM02 CM05 NMI Interrupt request level judgment output AAA AAA b R c Divider d CM07=0 BCLK fC CM07=1 S Q WAIT instruction R c b a 1/2 1/2 1/2 1/2 1/2 CM06=0 CM17,CM16=11 CM06=1 CM06=0 CM17,CM16=10 d CM06=0 CM17,CM16=01 CM06=0 CM17,CM16=00 CM0i : Bit i at address 000616 CM1i : Bit i at address 000716 WDCi : Bit i at address 000F16 Details of divider Figure 1.10.3. Clock generating circuit 35 Mitsubishi microcomputers M16C / 30L Group Clock Generating Circuit SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER The following paragraphs describes the clocks generated by the clock generating circuit. (1) Main clock The main clock is generated by the main clock oscillation circuit. After a reset, the clock is divided by 8 to the BCLK. The clock can be stopped using the main clock stop bit (bit 5 at address 000616). Stopping the clock, after switching the operating clock source of CPU to the sub-clock, reduces the power dissipation. After the oscillation of the main clock oscillation circuit has stabilized, the drive capacity of the main clock oscillation circuit can be reduced using the XIN-XOUT drive capacity select bit (bit 5 at address 000716). Reducing the drive capacity of the main clock oscillation circuit reduces the power dissipation. This bit changes to “1” when shifting from high-speed/medium-speed mode to stop mode, shifting to low power dissipation mode and at a reset. When shifting from high-speed/medium-speed mode to low-speed mode, the value before high-speed/medium-speed mode is retained. (2) Sub-clock The sub-clock is generated by the sub-clock oscillation circuit. No sub-clock is generated after a reset. After oscillation is started using the port XC select bit (bit 4 at address 000616), the sub-clock can be selected as the BCLK by using the system clock select bit (bit 7 at address 000616). However, be sure that the sub-clock oscillation has fully stabilized before switching. After the oscillation of the sub-clock oscillation circuit has stabilized, the drive capacity of the sub-clock oscillation circuit can be reduced using the XCIN-XCOUT drive capacity select bit (bit 3 at address 000616). Reducing the drive capacity of the sub-clock oscillation circuit reduces the power dissipation. This bit changes to “1” when the port XC select bit (bit 4 at address 000616) is set to “0” , shifting to stop mode and at a reset. When the XCIN/XCOUT is used, set ports P86 and P87 as the input ports without pull-up. (3) BCLK The BCLK is the clock that drives the CPU, and is fC or the clock is derived by dividing the main clock by 1, 2, 4, 8, or 16. The BCLK is derived by dividing the main clock by 8 after a reset. The BCLK signal can be output from BCLK pin by the BCLK output disable bit (bit 7 at address 000416) in the memory expansion and the microprocessor modes. The main clock division select bit 0 (bit 6 at address 000616) changes to “1” when shifting from highspeed/medium-speed to stop mode, shifting to low power dissipation mode and at reset. When shifting from high-speed/medium-speed mode to low-speed mode, the value before high-speed/medium-speed mode is retained. (4) Peripheral function clock(f1, f8, f32, f1SIO2, f8SIO2,f32SIO2,fAD) The clock for the peripheral devices is derived from the main clock or by dividing it by 1, 8, or 32. The peripheral function clock is stopped by stopping the main clock or by setting the WAIT peripheral function clock stop bit (bit 2 at 000616) to “1” and then executing a WAIT instruction. (5) fC32 This clock is derived by dividing the sub-clock by 32. It is used for the timer A and timer B counts. (6) fC This clock has the same frequency as the sub-clock. It is used for the BCLK and for the watchdog timer. 36 Mitsubishi microcomputers M16C / 30L Group Clock Generating Circuit SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Figure 1.10.4 shows the system clock control registers 0 and 1. System clock control register 0 (Note 1) b7 b6 b5 b4 b3 b2 b1 b0 Symbol CM0 Address 000616 Bit symbol When reset 4816 Bit name Function b1 b0 AA A AA A AAA AAA AA A AA A AA A AAA AAA RW Clock output function select bit (Valid only in single-chip mode) 0 0 : I/O port P57 0 1 : fC output 1 0 : f8 output 1 1 : f32 output CM02 WAIT peripheral function clock stop bit 0 : Do not stop peripheral function clock in wait mode 1 : Stop peripheral function clock in wait mode (Note 8) CM03 XCIN-XCOUT drive capacity 0 : LOW select bit (Note 2) 1 : HIGH CM04 Port XC select bit (Note 10) 0 : I/O port 1 : XCIN-XCOUT generation (Note 9) CM05 Main clock (XIN-XOUT) stop bit (Note 3, 4, 5) 0 : On 1 : Off CM06 Main clock division select bit 0 (Note 7) 0 : CM16 and CM17 valid 1 : Division by 8 mode CM07 System clock select bit (Note 6) 0 : XIN, XOUT 1 : XCIN, XCOUT CM00 CM01 Note 1: Set bit 0 of the protect register (address 000A16) to “1” before writing to this register. Note 2: Changes to “1” when the port XC select bit (CM04) is set to “0”, shiffing to stop mode and at a reset. Note 3: When entering low power dissipation mode, main clock stops by using this bit. To stop the main clock, when the sub clock oscillation is stable, set system clock select bit (CM07) to “1” before setting this bit to “1”. The main clock division select bit 0 (CM06) and the XIN-XOUT drive capacity select bit (CM15) change to “1” when this bit is set to “1”. Note 4: When inputting external clock, only clock oscillation buffer is stopped and clock input is acceptable. Note 5: If this bit is set to “1”, XOUT turns “H”. The built-in feedback resistor remains being connected, so XIN turns pulled up to XOUT (“H”) via the feedback resistor. Note 6: Set port XC select bit (CM04) to “1” and stabilize the sub-clock oscillating before setting this bit from “0” to “1”. Do not write to both bits at the same time. And also, set the main clock stop bit (CM05) to “0” and stabilize the main clock oscillating before setting this bit from “1” to “0”. Note 7: This bit changes to “1” when shifting from high-speed/medium-speed mode to stop mode, shifting to low power dissipation mode and at a reset. When shifting from high-speed/medium-speed mode to low-speed mode, the value before high-speed/ medium-speed mode is retained. Note 8: fC32 is not included. Do not set to “1” when using low-speed or low power dissipation mode. Note 9: When the XCIN/XCOUT is used, set ports P86 and P87 as the input ports without pull-up. Note10: The XCIN-XCOUT drive capacity select bit changes to “1” when this bit is set to “0”. System clock control register 1 (Note 1) b7 b6 b5 b4 b3 b2 b1 0 0 0 0 b0 Symbol CM1 Address 000716 Bit symbol CM10 When reset 2016 Bit name All clock stop control bit (Note4) Function 0 : Clock on 1 : All clocks off (stop mode) Reserved bit Must always be set to “0” Reserved bit Must always be set to “0” Reserved bit Must always be set to “0” Reserved bit Must always be set to “0” CM15 XIN-XOUT drive capacity select bit (Note 2) CM16 Main clock division select bit 1 (Note 3) 0 : LOW 1 : HIGH b7 b6 CM17 0 0 : No division mode 0 1 : Division by 2 mode 1 0 : Division by 4 mode 1 1 : Division by 16 mode AA A AAA AA A AA A AA A AAA AAA AAA RW Note 1: Set bit 0 of the protect register (address 000A16) to “1” before writing to this register. Note 2: This bit changes to “1” when shifting from high-speed/medium-speed mode to stop mode, shifting to low power dissipation mode and at a reset. When shifting from high-speed/medium-speed mode to low-speed mode, the value before high-speed/ medium-speed mode is retained. Note 3: Can be selected when bit 6 of the system clock control register 0 (address 000616) is “0”. If “1”, division mode is fixed at 8. Note 4: If this bit is set to “1”, XOUT turns “H”, and the built-in feedback resistor is cut off. XCIN and XCOUT turn high-impedance state. Figure 1.10.4. Clock control registers 0 and 1 37 Mitsubishi microcomputers M16C / 30L Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Clock Generating Circuit Clock Output In single-chip mode, the clock output function select bits (bits 0 and 1 at address 000616) enable f8, f32, or fc to be output from the P57/CLKOUT pin. When the WAIT peripheral function clock stop bit (bit 2 at address 000616) is set to “1”, the output of f8 and f32 stops when a WAIT instruction is executed. Stop Mode Writing “1” to the all-clock stop control bit (bit 0 at address 000716) stops all oscillation and the microcomputer enters stop mode. In stop mode, the content of the internal RAM is retained provided that VCC remains above 2V. Because the oscillation , BCLK, f1 to f32, f1SIO2 to f32SIO2, fC, fC32, and fAD stops in stop mode, peripheral functions such as the A-D converter and watchdog timer do not function. However, timer A and timer B operate provided that the event counter mode is set to an external pulse, and UARTi(i = 0 to 2) functions provided an external clock is selected. Table 1.10.2 shows the status of the ports in stop mode. Stop mode is cancelled by a hardware reset or an interrupt. If an interrupt is to be used to cancel stop mode, that interrupt must first have been enabled, and the priority level of the interrupt which is not used to cancel must have been changed to 0. If returning by an interrupt, that interrupt routine is executed. If only a _______ hardware reset or an NMI interrupt is used to cancel stop mode, change the priority level of all interrupt to 0, then shift to stop mode. The main clock division select bit 0 (bit 6 at address 000616) changes to “1” when shifting from high-speed/ medium-speed mode to stop mode, shifting to low power dissipation mode and at reset. When shifting from high-speed/medium-speed mode to low-speed mode, the value before high-speed/medium-speed mode is retained. Table 1.10.2. Port status during stop mode Pin Memory expansion mode Microprocessor mode _______ Single-chip mode _______ Address bus, data bus, CS0 to CS3, Retains status before stop mode ________ BHE _____ ______ ________ _________ RD, WR, WRL, WRH “H” __________ HLDA, BCLK ALE Port CLKOUT When fc selected When f8, f32 selected 38 “H” “H” Retains status before stop mode Retains status before stop mode Valid only in single-chip mode “H” Valid only in single-chip mode Retains status before stop mode Mitsubishi microcomputers M16C / 30L Group Wait Mode SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Wait Mode When a WAIT instruction is executed, the BCLK stops and the microcomputer enters the wait mode. In this mode, oscillation continues but the BCLK and watchdog timer stop. Writing “1” to the WAIT peripheral function clock stop bit and executing a WAIT instruction stops the clock being supplied to the internal peripheral functions, allowing power dissipation to be reduced. However, peripheral function clock fC32 does not stop so that the peripherals using fC32 do not contribute to the power saving. When the MCU running in low-speed or low power dissipation mode, do not enter WAIT mode with this bit set to “1”. Table 1.10.3 shows the status of the ports in wait mode. Wait mode is cancelled by a hardware reset or an interrupt. If an interrupt is used to cancel wait mode, that interrupt must first have been enabled, and the priority level of the interrupt which is not used to cancel must have been changed to 0. If returning by an interrupt, the clock in which the WAIT instruction executed is set to BCLK by the microcomputer, and the action is resumed from the interrupt routine. If only a hardware _______ reset or an NMI interrupt is used to cancel wait mode, change the priority level of all interrupt to 0,then shift to wait mode. Table 1.10.3. Port status during wait mode Pin Memory expansion mode Microprocessor mode _______ Single-chip mode _______ Address bus, data bus, CS0 to CS3, Retains status before wait mode ________ BHE _____ ______ ________ _________ RD, WR, WRL, WRH “H” __________ HLDA,BCLK ALE Port CLKOUT “H” “H” Retains status before wait mode When fC selected Valid only in single-chip mode When f8, f32 selected Valid only in single-chip mode Retains status before wait mode Does not stop Does not stop when the WAIT peripheral function clock stop bit is “0”. When the WAIT peripheral function clock stop bit is “1”, the status immediately prior to entering wait mode is maintained. 39 Mitsubishi microcomputers M16C / 30L Group Status Transition of BCLK SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Status Transition of BCLK Power dissipation can be reduced and low-voltage operation achieved by changing the count source for BCLK. Table 1.10.4 shows the operating modes corresponding to the settings of system clock control registers 0 and 1. When reset, the device starts in division by 8 mode. The main clock division select bit 0 (bit 6 at address 000616) and the XIN-XOUT drive capacity select bit (bit 5 at address 000716) change to “1” when shifting from high-speed/medium-speed mode to stop mode, shifting to low power dissipation mode and at a reset. When shifting from high-speed/medium-speed mode to low-speed mode, the value before high-speed/ medium-speed mode is retained. The following shows the operational modes of BCLK. (1) Division by 2 mode The main clock is divided by 2 to obtain the BCLK. (2) Division by 4 mode The main clock is divided by 4 to obtain the BCLK. (3) Division by 8 mode The main clock is divided by 8 to obtain the BCLK. When reset, the device starts operating from this mode. Before the user can go from this mode to no division mode, division by 2 mode, or division by 4 mode, the main clock must be oscillating stably. When going to low-speed or lower power consumption mode, make sure the sub-clock is oscillating stably. (4) Division by 16 mode The main clock is divided by 16 to obtain the BCLK. (5) No-division mode The main clock is divided by 1 to obtain the BCLK. (6) Low-speed mode fC is used as the BCLK. Note that oscillation of both the main and sub-clocks must have stabilized before transferring from this mode to another or vice versa. At least 2 to 3 seconds are required after the subclock starts. Therefore, the program must be written to wait until this clock has stabilized immediately after powering up and after stop mode is cancelled. (7) Low power dissipation mode fC is the BCLK and the main clock is stopped. Note : Before the count source for BCLK can be changed from XIN to XCIN or vice versa, the clock to which the count source is going to be switched must be oscillating stably. Allow a wait time in software for the oscillation to stabilize before switching over the clock. Table 1.10.4. Operating modes dictated by settings of system clock control registers 0 and 1 CM17 CM16 CM07 CM06 CM05 CM04 Operating mode of BCLK 0 1 Invalid 1 0 Invalid Invalid 1 0 Invalid 1 0 Invalid Invalid 0 0 0 0 0 1 1 CM1i : Bit i of the address 000716 CM0i : Bit i of the address 000616 40 0 0 1 0 0 Invalid Invalid 0 0 0 0 0 0 1 Invalid Invalid Invalid Invalid Invalid 1 1 Division by 2 mode Division by 4 mode Division by 8 mode Division by 16 mode No-division mode Low-speed mode Low power dissipation mode Mitsubishi microcomputers M16C / 30L Group Power control SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Power control The following is a description of the three available power control modes: Modes Power control is available in three modes. (a) Normal operation mode • High-speed mode Divide-by-1 frequency of the main clock becomes the BCLK. The CPU operates with the BCLK. Each peripheral function operates according to its assigned clock. • Medium-speed mode Divide-by-2, divide-by-4, divide-by-8, or divide-by-16 frequency of the main clock becomes the BCLK. The CPU operates with the BCLK. Each peripheral function operates according to its assigned clock. • Low-speed mode fC becomes the BCLK. The CPU operates according to the fC clock. The fC clock is supplied by the subclock. Each peripheral function operates according to its assigned clock. • Low power dissipation mode The main clock operating in low-speed mode is stopped. The CPU operates according to the fC clock. The fC clock is supplied by the subclock. The only peripheral functions that operate are those with the subclock selected as the count source. (b) Wait mode The CPU operation is stopped. The oscillators do not stop. (c) Stop mode All oscillators stop. The CPU and all built-in peripheral functions stop. This mode, among the three modes listed here, is the most effective in decreasing power consumption. Figure 1.10.5 is the state transition diagram of the above modes. 41 Mitsubishi microcomputers M16C / 30L Group Power control SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Transition of stop mode, wait mode Reset All oscillators stopped CM10 = “1” Stop mode WAIT instruction Medium-speed mode (divided-by-8 mode) Interrupt CPU operation stopped Wait mode Interrupt Interrupt All oscillators stopped Stop mode WAIT instruction High-speed/mediumspeed mode CM10 = “1” Low power dissipation mode CM10 = “1” Low-speed mode WAIT instruction Low-speed/low power dissipation mode Interrupt Wait mode Interrupt All oscillators stopped Stop mode CPU operation stopped CPU operation stopped Wait mode Interrupt Normal mode (Refer to the following for the transition of normal mode.) Transition of normal mode Main clock is oscillating Sub clock is stopped Medium-speed mode (divided-by-8 mode) CM06 = “1” BCLK : f(XIN)/8 CM07 = “0” CM06 = “1” Main clock is oscillating CM04 = “0” Sub clock is oscillating CM07 = “0” (Note 1) CM06 = “1” CM04 = “0” CM04 = “1” (Notes 1, 3) High-speed mode Medium-speed mode (divided-by-2 mode) BCLK : f(XIN) CM07 = “0” CM06 = “0” CM17 = “0” CM16 = “0” BCLK : f(XIN)/2 CM07 = “0” CM06 = “0” CM17 = “0” CM16 = “1” Medium-speed mode (divided-by-8 mode) Medium-speed mode (divided-by-4 mode) Medium-speed mode (divided-by-16 mode) BCLK : f(XIN)/8 CM07 = “0” CM06 = “1” BCLK : f(XIN)/4 CM07 = “0” CM06 = “0” CM17 = “1” CM16 = “0” BCLK : f(XIN)/16 CM07 = “0” CM06 = “0” CM17 = “1” CM16 = “1” Main clock is oscillating Sub clock is oscillating Low-speed mode CM07 = “0” (Note 1, 3) BCLK : f(XCIN) CM07 = “1” CM07 = “1” (Note 2) CM05 = “0” CM04 = “0” CM06 = “0” (Notes 1,3) Main clock is oscillating Sub clock is stopped CM04 = “1” High-speed mode Medium-speed mode (divided-by-2 mode) BCLK : f(XIN) CM07 = “0” CM06 = “0” CM17 = “0” CM16 = “0” BCLK : f(XIN)/2 CM07 = “0” CM06 = “0” CM17 = “0” CM16 = “1” Medium-speed mode (divided-by-4 mode) Medium-speed mode (divided-by-16 mode) BCLK : f(XIN)/4 CM07 = “0” CM06 = “0” CM17 = “1” CM16 = “0” BCLK : f(XIN)/16 CM07 = “0” CM06 = “0” CM17 = “1” CM16 = “1” Main clock is stopped Sub clock is oscillating Low power dissipation mode CM07 = “1” (Note 2) CM05 = “1” BCLK : f(XCIN) CM07 = “1” CM06 = “1” CM15 = “1” CM07 = “0” (Note 1) CM06 = “0” (Note 3) CM04 = “1” CM03 = “1” Note 1: Switch clock after oscillation of main clock is sufficiently stable. Note 2: Switch clock after oscillation of sub clock is sufficiently stable. Note 3: Change CM06 after changing CM17 and CM16. Note 4: Transit in accordance with arrow. Figure 1.10.5. State transition diagram of Power control mode 42 CM05 = “1” Mitsubishi microcomputers M16C / 30L Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Protection Protection The protection function is provided so that the values in important registers cannot be changed in the event that the program runs out of control. Figure 1.10.6 shows the protect register. The values in the processor mode register 0 (address 000416), processor mode register 1 (address 000516), system clock control register 0 (address 000616), system clock control register 1 (address 000716), port P9 direction register (address 03F316) can only be changed when the respective bit in the protect register is set to “1”. Therefore, important outputs can be allocated to port P9. If, after “1” (write-enabled) has been written to the port P9 direction register write-enable bit (bit 2 at address 000A16), a value is written to any address, the bit automatically reverts to “0” (write-inhibited). However, the system clock control registers 0 and 1 write-enable bit (bit 0 at 000A16) and processor mode register 0 and 1 write-enable bit (bit 1 at 000A16) do not automatically return to “0” after a value has been written to an address. The program must therefore be written to return these bits to “0”. Protect register b7 b6 b5 b4 b3 b2 b1 b0 Symbol PRCR Bit symbol Address 000A16 When reset XXXXX0002 Bit name Function PRC0 Enables writing to system clock control registers 0 and 1 (addresses 0 : Write-inhibited 1 : Write-enabled 000616 and 000716) PRC1 Enables writing to processor mode 0 : Write-inhibited registers 0 and 1 (addresses 000416 1 : Write-enabled and 000516) PRC2 Enables writing to port P9 direction register (address 03F316) (Note) 0 : Write-inhibited 1 : Write-enabled Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be indeterminate. A A A A R W Note: Writing a value to an address after “1” is written to this bit returns the bit to “0” . Other bits do not automatically return to “0” and they must therefore be reset by the program. Figure 1.10.6. Protect register 43 Mitsubishi microcomputers M16C / 30L Group Interrupt SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Overview of Interrupt Type of Interrupts Figure 1.11.1 lists the types of interrupts. Hardware Special Peripheral I/O (Note) Interrupt Software Undefined instruction (UND instruction) Overflow (INTO instruction) BRK instruction INT instruction Reset NMI ________ DBC Watchdog timer Single step Address matched _______ Note: Peripheral I/O interrupts are generated by the peripheral functions built into the microcomputer system. Figure 1.11.1. Classification of interrupts • Maskable interrupt : An interrupt which can be enabled (disabled) by the interrupt enable flag (I flag) or whose interrupt priority can be changed by priority level. • Non-maskable interrupt : An interrupt which cannot be enabled (disabled) by the interrupt enable flag (I flag) or whose interrupt priority cannot be changed by priority level. 44 Mitsubishi microcomputers M16C / 30L Group Interrupt SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Software Interrupts A software interrupt occurs when executing certain instructions. Software interrupts are non-maskable interrupts. • Undefined instruction interrupt An undefined instruction interrupt occurs when executing the UND instruction. • Overflow interrupt An overflow interrupt occurs when executing the INTO instruction with the overflow flag (O flag) set to “1”. The following are instructions whose O flag changes by arithmetic: ABS, ADC, ADCF, ADD, CMP, DIV, DIVU, DIVX, NEG, RMPA, SBB, SHA, SUB • BRK interrupt A BRK interrupt occurs when executing the BRK instruction. • INT interrupt An INT interrupt occurs when specifying one of software interrupt numbers 0 through 63 and executing the INT instruction. Software interrupt numbers 0 through 31 are assigned to peripheral I/O interrupts, so executing the INT instruction allows executing the same interrupt routine that a peripheral I/ O interrupt does. The stack pointer (SP) used for the INT interrupt is dependent on which software interrupt number is involved. So far as software interrupt numbers 0 through 31 are concerned, the microcomputer saves the stack pointer assignment flag (U flag) when it accepts an interrupt request. If change the U flag to “0” and select the interrupt stack pointer (ISP), and then execute an interrupt sequence. When returning from the interrupt routine, the U flag is returned to the state it was before the acceptance of interrupt request. So far as software numbers 32 through 63 are concerned, the stack pointer does not make a shift. 45 Mitsubishi microcomputers M16C / 30L Group Interrupt SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Hardware Interrupts Hardware interrupts are classified into two types — special interrupts and peripheral I/O interrupts. (1) Special interrupts Special interrupts are non-maskable interrupts. • Reset ____________ Reset occurs if an “L” is input to the RESET pin. _______ • NMI interrupt _______ _______ An NMI interrupt occurs if an “L” is input to the NMI pin. ________ • DBC interrupt This interrupt is exclusively for the debugger, do not use it in other circumstances. • Watchdog timer interrupt Generated by the watchdog timer. Write to the watchdog timer start register after the watchdog timer interrupt occurs (initialize watchdog timer). • Single-step interrupt This interrupt is exclusively for the debugger, do not use it in other circumstances. With the debug flag (D flag) set to “1”, a single-step interrupt occurs after one instruction is executed. • Address match interrupt An address match interrupt occurs immediately before the instruction held in the address indicated by the address match interrupt register is executed with the address match interrupt enable bit set to “1”. If an address other than the first address of the instruction in the address match interrupt register is set, no address match interrupt occurs. (2) Peripheral I/O interrupts A peripheral I/O interrupt is generated by one of built-in peripheral functions. Built-in peripheral functions are dependent on classes of products, so the interrupt factors too are dependent on classes of products. The interrupt vector table is the same as the one for software interrupt numbers 0 through 31 the INT instruction uses. Peripheral I/O interrupts are maskable interrupts. • Bus collision detection interrupt This is an interrupt that the serial I/O bus collision detection generates. • DMA0 interrupt This is an interrupts that DMA generates. • Key-input interrupt ___ A key-input interrupt occurs if an “L” is input to the KI pin. • A-D conversion interrupt This is an interrupt that the A-D converter generates. • UART0, UART1, UART2/NACK transmission interrupt These are interrupts that the serial I/O transmission generates. • UART0, UART1, UART2/ACK reception interrupt These are interrupts that the serial I/O reception generates. • Timer A0 interrupt through timer A2 interrupt These are interrupts that timer A generates • Timer B1, timer B2 interrupt These are interrupts that timer B generates. ________ ________ • INT0 interrupt through INT2 interrupt ______ ______ An INT interrupt occurs if either a rising edge or a falling edge or a both edge is input to the INT pin. 46 Mitsubishi microcomputers M16C / 30L Group Interrupt SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Interrupts and Interrupt Vector Tables If an interrupt request is accepted, a program branches to the interrupt routine set in the interrupt vector table. Set the first address of the interrupt routine in each vector table. Figure 1.11.2 shows the format for specifying the address. Two types of interrupt vector tables are available — fixed vector table in which addresses are fixed and variable vector table in which addresses can be varied by the setting. AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA MSB LSB Vector address + 0 Low address Vector address + 1 Mid address Vector address + 2 0000 High address Vector address + 3 0000 0000 Figure 1.11.2. Format for specifying interrupt vector addresses • Fixed vector tables The fixed vector table is a table in which addresses are fixed. The vector tables are located in an area extending from FFFDC16 to FFFFF16. One vector table comprises four bytes. Set the first address of interrupt routine in each vector table. Table 1.11.1 shows the interrupts assigned to the fixed vector tables and addresses of vector tables. Table 1.11.1. Interrupts assigned to the fixed vector tables and addresses of vector tables Interrupt source Undefined instruction Overflow BRK instruction Vector table addresses Address (L) to address (H) FFFDC16 to FFFDF16 FFFE016 to FFFE316 FFFE416 to FFFE716 Remarks Interrupt on UND instruction Interrupt on INTO instruction If the vector contains FF16, program execution starts from the address shown by the vector in the variable vector table There is an address-matching interrupt enable bit Do not use Address match FFFE816 to FFFEB16 Single step (Note) FFFEC16 to FFFEF16 Watchdog timer FFFF016 to FFFF316 ________ DBC (Note) FFFF416 to FFFF716 Do not use _______ _______ NMI FFFF816 to FFFFB16 External interrupt by input to NMI pin Reset FFFFC16 to FFFFF16 Note: Interrupts used for debugging purposes only. 47 Mitsubishi microcomputers M16C / 30L Group Interrupt SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER • Variable vector tables The addresses in the variable vector table can be modified, according to the user’s settings. Indicate the first address using the interrupt table register (INTB). The 256-byte area subsequent to the address the INTB indicates becomes the area for the variable vector tables. One vector table comprises four bytes. Set the first address of the interrupt routine in each vector table. Table 1.11.2 shows the interrupts assigned to the variable vector tables and addresses of vector tables. Table 1.11.2. Interrupts assigned to the variable vector tables and addresses of vector tables Software interrupt number Vector table address Interrupt source Address (L) to address (H) Software interrupt number 0 +0 to +3 (Note 1) BRK instruction Software interrupt number 10 +40 to +43 (Note 1) Bus collision detection Software interrupt number 11 +44 to +47 (Note 1) DMA0 Software interrupt number 13 +52 to +55 (Note 1) Key input interrupt Software interrupt number 14 +56 to +59 (Note 1) A-D Software interrupt number 15 +60 to +63 (Note 1) UART2 transmit/NACK (Note 2) Software interrupt number 16 +64 to +67 (Note 1) UART2 receive/ACK (Note 2) Software interrupt number 17 +68 to +71 (Note 1) UART0 transmit Software interrupt number 18 +72 to +75 (Note 1) UART0 receive Software interrupt number 19 +76 to +79 (Note 1) UART1 transmit Software interrupt number 20 +80 to +83 (Note 1) UART1 receive Software interrupt number 21 +84 to +87 (Note 1) Timer A0 Software interrupt number 22 +88 to +91 (Note 1) Timer A1 Software interrupt number 23 +92 to +95 (Note 1) Timer A2 Software interrupt number 27 +108 to +111 (Note 1) Timer B1 Software interrupt number 28 +112 to +115 (Note 1) Timer B2 Software interrupt number 29 +116 to +119 (Note 1) INT0 Software interrupt number 30 +120 to +123 (Note 1) INT1 Software interrupt number 31 +124 to +127 (Note 1) INT2 Software interrupt number 32 +128 to +131 (Note 1) to Software interrupt number 63 to +252 to +255 (Note 1) Software interrupt Note 1: Address relative to address in interrupt table register (INTB). Note 2: When IIC mode is selected, NACK and ACK interrupts are selected. 48 Remarks Cannot be masked I flag Cannot be masked I flag Mitsubishi microcomputers M16C / 30L Group Interrupt SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Interrupt Control Descriptions are given here regarding how to enable or disable maskable interrupts and how to set the priority to be accepted. What is described here does not apply to non-maskable interrupts. Enable or disable a maskable interrupt using the interrupt enable flag (I flag), interrupt priority level selection bit, or processor interrupt priority level (IPL). Whether an interrupt request is present or absent is indicated by the interrupt request bit. The interrupt request bit and the interrupt priority level selection bit are located in the interrupt control register of each interrupt. Also, the interrupt enable flag (I flag) and the IPL are located in the flag register (FLG). Figure 1.11.3 shows the memory map of the interrupt control registers. 49 Mitsubishi microcomputers M16C / 30L Group Interrupt SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Interrupt control register (Note 2) AAA b7 b6 b5 b4 b3 b2 b1 b0 Symbol BCNIC DM0IC KUPIC ADIC SiTIC(i=0 to 2) SiRIC(i=0 to 2) TAiIC(i=0 to 2) TBiIC(i=1, 2) Bit symbol ILVL0 Address 004A16 004B16 004D16 004E16 005116, 005316, 004F16 005216, 005416, 005016 005516 to 005716 005B16, 005C16 Bit name Interrupt priority level select bit ILVL2 IR Function b2 b1 b0 000: 001: 010: 011: 100: 101: 110: 111: ILVL1 Interrupt request bit When reset XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 AAAA AA A A AA AA AA AA AAAA R W Level 0 (interrupt disabled) Level 1 Level 2 Level 3 Level 4 Level 5 Level 6 Level 7 0 : Interrupt not requested 1 : Interrupt requested Nothing is assigned. (Note 1) In an attempt to write to these bits, write “0”. The value, if read, turns out to be indeterminate. Note 1: This bit can only be accessed for reset (= 0), but cannot be accessed for set (= 1). Note 2: To rewrite the interrupt control register, do so at a point that does not generate the interrupt request for that register. For details, see the precautions for interrupts. AAA A AA b7 b6 b5 0 b4 b3 b2 b1 b0 Symbol INTiIC(i=0 to 2) Bit symbol ILVL0 Address 005D16 to 005F16 Bit name Interrupt priority level select bit ILVL1 ILVL2 IR POL When reset XX00X0002 Interrupt request bit Polarity select bit Reserved bit Nothing is assigned. Function b2 b1 b0 AA A A AA AA AAAA AA A A AA AA AAAA AA A A AAAA R W 0 0 0 : Level 0 (interrupt disabled) 0 0 1 : Level 1 0 1 0 : Level 2 0 1 1 : Level 3 1 0 0 : Level 4 1 0 1 : Level 5 1 1 0 : Level 6 1 1 1 : Level 7 0: Interrupt not requested 1: Interrupt requested 0 : Selects falling edge 1 : Selects rising edge Must always be set to “0” (Note 1) In an attempt to write to these bits, write “0”. The value, if read, turns out to be indeterminate. Note 1: This bit can only be accessed for reset (= 0), but cannot be accessed for set (= 1). Note 2: To rewrite the interrupt control register, do so at a point that does not generate the interrupt request for that register. For details, see the precautions for interrupts. Figure 1.11.3. Interrupt control registers 50 Mitsubishi microcomputers M16C / 30L Group Interrupt SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Interrupt Enable Flag (I flag) The interrupt enable flag (I flag) controls the enabling and disabling of maskable interrupts. Setting this flag to “1” enables all maskable interrupts; setting it to “0” disables all maskable interrupts. This flag is set to “0” after reset. Interrupt Request Bit The interrupt request bit is set to “1” by hardware when an interrupt is requested. After the interrupt is accepted and jumps to the corresponding interrupt vector, the request bit is set to “0” by hardware. The interrupt request bit can also be set to “0” by software. (Do not set this bit to “1”). Interrupt Priority Level Select Bit and Processor Interrupt Priority Level (IPL) Set the interrupt priority level using the interrupt priority level select bit, which is one of the component bits of the interrupt control register. When an interrupt request occurs, the interrupt priority level is compared with the IPL. The interrupt is enabled only when the priority level of the interrupt is higher than the IPL. Therefore, setting the interrupt priority level to “0” disables the interrupt. Table 1.11.3 shows the settings of interrupt priority levels and Table 1.11.4 shows the interrupt levels enabled, according to the contents of the IPL. The following are conditions under which an interrupt is accepted: · interrupt enable flag (I flag) = “1” · interrupt request bit = “1” · interrupt priority level > IPL The interrupt enable flag (I flag), the interrupt request bit, the interrupt priority select bit, and the IPL are independent, and they are not affected by one another. Table 1.11.3. Settings of interrupt priority levels Interrupt priority level select bit Interrupt priority level Table 1.11.4. Interrupt levels enabled according to the contents of the IPL Priority order b2 b1 b0 IPL Enabled interrupt priority levels IPL2 IPL1 IPL0 0 0 0 Level 0 (interrupt disabled) 0 0 1 Level 1 0 1 0 0 1 1 0 0 0 Interrupt levels 1 and above are enabled 0 0 1 Interrupt levels 2 and above are enabled Level 2 0 1 0 Interrupt levels 3 and above are enabled 1 Level 3 0 1 1 Interrupt levels 4 and above are enabled 0 0 Level 4 1 0 0 Interrupt levels 5 and above are enabled 1 0 1 Level 5 1 0 1 Interrupt levels 6 and above are enabled 1 1 0 Level 6 1 1 0 Interrupt levels 7 and above are enabled 1 1 1 Level 7 1 1 1 All maskable interrupts are disabled Low High 51 Mitsubishi microcomputers M16C / 30L Group Interrupt SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Rewrite the interrupt control register To rewrite the interrupt control register, do so at a point that does not generate the interrupt request for that register. If there is possibility of the interrupt request occur, rewrite the interrupt control register after the interrupt is disabled. The program examples are described as follow: Example 1: INT_SWITCH1: FCLR I AND.B #00h, 0055h NOP NOP FSET I ; Disable interrupts. ; Clear TA0IC int. priority level and int. request bit. ; Four NOP instructions are required when using HOLD function. ; Enable interrupts. Example 2: INT_SWITCH2: FCLR I AND.B #00h, 0055h MOV.W MEM, R0 FSET I ; Disable interrupts. ; Clear TA0IC int. priority level and int. request bit. ; Dummy read. ; Enable interrupts. Example 3: INT_SWITCH3: PUSHC FLG FCLR I AND.B #00h, 0055h POPC FLG ; Push Flag register onto stack ; Disable interrupts. ; Clear TA0IC int. priority level and int. request bit. ; Enable interrupts. The reason why two NOP instructions (four when using the HOLD function) or dummy read are inserted before FSET I in Examples 1 and 2 is to prevent the interrupt enable flag I from being set before the interrupt control register is rewritten due to effects of the instruction queue. When changing an interrupt control register in a sate of interrupts being disabled, please read the following precautions on instructions used before changing the register. Changing a non-interrupt request bit If an interrupt request for an interrupt control register is generated during an instruction to rewrite the register is being executed, there is a case that the interrupt request bit is not set and consequently the interrupt is ignored. This will depend on the instruction. If this creates problems, use the below instructions to change the register. Instructions : AND, OR, BCLR, BSET Changing the interrupt request bit When attempting to clear the interrupt request bit of an interrupt control register, the interrupt request bit is not cleared sometimes. This will depend on the instruction. If this creates problems, use the below instructions to change the register. Instructions : MOV 52 Mitsubishi microcomputers M16C / 30L Group Interrupt SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Interrupt Sequence An interrupt sequence — what are performed over a period from the instant an interrupt is accepted to the instant the interrupt routine is executed — is described here. If an interrupt occurs during execution of an instruction, the processor determines its priority when the execution of the instruction is completed, and transfers control to the interrupt sequence from the next cycle. If an interrupt occurs during execution of either the SMOVB, SMOVF, SSTR or RMPA instruction, the processor temporarily suspends the instruction being executed, and transfers control to the interrupt sequence. In the interrupt sequence, the processor carries out the following in sequence given: (1) CPU gets the interrupt information (the interrupt number and interrupt request level) by reading address 0000016. After this, the corresponding interrupt request bit becomes “0”. (2) Saves the content of the flag register (FLG) as it was immediately before the start of interrupt sequence in the temporary register (Note) within the CPU. (3) Sets the interrupt enable flag (I flag), the debug flag (D flag), and the stack pointer select flag (U flag) to “0” (the U flag, however does not change if the INT instruction, in software interrupt numbers 32 through 63, is executed) (4) Saves the content of the temporary register (Note) within the CPU in the stack area. (5) Saves the content of the program counter (PC) in the stack area. (6) Sets the interrupt priority level of the accepted instruction in the IPL. After the interrupt sequence is completed, the processor resumes executing instructions from the first address of the interrupt routine. Note: This register cannot be utilized by the user. Interrupt Response Time 'Interrupt response time' is the period between the instant an interrupt occurs and the instant the first instruction within the interrupt routine has been executed. This time comprises the period from the occurrence of an interrupt to the completion of the instruction under execution at that moment (a) and the time required for executing the interrupt sequence (b). Figure 1.11.4 shows the interrupt response time. Interrupt request generated Interrupt request acknowledged Time Instruction Interrupt sequence (a) Instruction in interrupt routine (b) Interrupt response time (a) Time from interrupt request is generated to when the instruction then under execution is completed. (b) Time in which the instruction sequence is executed. Figure 1.11.4. Interrupt response time 53 Mitsubishi microcomputers M16C / 30L Group Interrupt SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Time (a) is dependent on the instruction under execution. Thirty cycles is the maximum required for the DIVX instruction (without wait). Time (b) is as shown in Table 1.11.5. Table 1.11.5. Time required for executing the interrupt sequence Interrupt vector address Stack pointer (SP) value 16-Bit bus, without wait 8-Bit bus, without wait Even Even 18 cycles (Note 1) 20 cycles (Note 1) Even Odd 19 cycles (Note 1) 20 cycles (Note 1) Odd (Note 2) Even 19 cycles (Note 1) 20 cycles (Note 1) Odd (Note 2) Odd 20 cycles (Note 1) 20 cycles (Note 1) ________ Note 1: Add 2 cycles in the case of a DBC interrupt; add 1 cycle in the case either of an address match interrupt or of a single-step interrupt. Note 2: Locate an interrupt vector address in an even address, if possible. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 BCLK Address bus Address 0000 Interrupt information Data bus R Indeterminate Indeterminate SP-2 SP-4 SP-2 contents SP-4 contents vec vec+2 vec contents PC vec+2 contents Indeterminate W The indeterminate segment is dependent on the queue buffer. If the queue buffer is ready to take an instruction, a read cycle occurs. Figure 1.11.5. Time required for executing the interrupt sequence Variation of IPL when Interrupt Request is Accepted If an interrupt request is accepted, the interrupt priority level of the accepted interrupt is set in the IPL. If an interrupt request, that does not have an interrupt priority level, is accepted, one of the values shown in Table 1.11.6 is set in the IPL. Table 1.11.6. Relationship between interrupts without interrupt priority levels and IPL Interrupt sources without priority levels Value set in the IPL _______ Watchdog timer, NMI 7 Reset 0 Other 54 Not changed Mitsubishi microcomputers M16C / 30L Group Interrupt SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Saving Registers In the interrupt sequence, only the contents of the flag register (FLG) and that of the program counter (PC) are saved in the stack area. First, the processor saves the four higher-order bits of the program counter, and 4 upper-order bits and 8 lower-order bits of the FLG register, 16 bits in total, in the stack area, then saves 16 lower-order bits of the program counter. Figure 1.11.6 shows the state of the stack as it was before the acceptance of the interrupt request, and the state the stack after the acceptance of the interrupt request. Save other necessary registers at the beginning of the interrupt routine using software. Using the PUSHM instruction alone can save all the registers except the stack pointer (SP). Address MSB Stack area Address MSB LSB Stack area LSB m–4 m–4 Program counter (PCL) m–3 m–3 Program counter (PCM) m–2 m–2 Flag register (FLGL) m–1 m–1 m Content of previous stack m+1 Content of previous stack Stack status before interrupt request is acknowledged [SP] Stack pointer value before interrupt occurs Flag register (FLGH) [SP] New stack pointer value Program counter (PCH) m Content of previous stack m+1 Content of previous stack Stack status after interrupt request is acknowledged Figure 1.11.6. State of stack before and after acceptance of interrupt request 55 Mitsubishi microcomputers M16C / 30L Group Interrupt SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER The operation of saving registers carried out in the interrupt sequence is dependent on whether the content of the stack pointer (Note) , at the time of acceptance of an interrupt request, is even or odd. If the content of the stack pointer (Note) is even, the content of the flag register (FLG) and the content of the program counter (PC) are saved, 16 bits at a time. If odd, their contents are saved in two steps, 8 bits at a time. Figure 1.11.7 shows the operation of the saving registers. Note: When any INT instruction in software numbers 32 to 63 has been executed, this is the stack pointer indicated by the U flag. Otherwise, it is the interrupt stack pointer (ISP). (1) Stack pointer (SP) contains even number Address Stack area Sequence in which order registers are saved [SP] – 5 (Odd) [SP] – 4 (Even) Program counter (PCL) [SP] – 3(Odd) Program counter (PCM) [SP] – 2 (Even) Flag register (FLGL) [SP] – 1(Odd) [SP] Flag register (FLGH) Program counter (PCH) (2) Saved simultaneously, all 16 bits (1) Saved simultaneously, all 16 bits (Even) Finished saving registers in two operations. (2) Stack pointer (SP) contains odd number Address Stack area Sequence in which order registers are saved [SP] – 5 (Even) [SP] – 4(Odd) Program counter (PCL) (3) [SP] – 3 (Even) Program counter (PCM) (4) [SP] – 2(Odd) Flag register (FLGL) [SP] – 1 (Even) [SP] Flag register (FLGH) Program counter (PCH) Saved simultaneously, all 8 bits (1) (2) (Odd) Finished saving registers in four operations. Note: [SP] denotes the initial value of the stack pointer (SP) when interrupt request is acknowledged. After registers are saved, the SP content is [SP] minus 4. Figure 1.11.7. Operation of saving registers 56 Mitsubishi microcomputers M16C / 30L Group Interrupt SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Returning from an Interrupt Routine Executing the REIT instruction at the end of an interrupt routine returns the contents of the flag register (FLG) as it was immediately before the start of interrupt sequence and the contents of the program counter (PC), both of which have been saved in the stack area. Then control returns to the program that was being executed before the acceptance of the interrupt request, so that the suspended process resumes. Return the other registers saved by software within the interrupt routine using the POPM or similar instruction before executing the REIT instruction. Interrupt Priority If there are two or more interrupt requests occurring at a point in time within a single sampling (checking whether interrupt requests are made), the interrupt assigned a higher priority is accepted. Assign an arbitrary priority to maskable interrupts (peripheral I/O interrupts) using the interrupt priority level select bit. If the same interrupt priority level is assigned, however, the interrupt assigned a higher hardware priority is accepted. Priorities of the special interrupts, such as Reset (dealt with as an interrupt assigned the highest priority), watchdog timer interrupt, etc. are regulated by hardware. Figure 1.11.8 shows the priorities of hardware interrupts. Software interrupts are not affected by the interrupt priority. If an instruction is executed, control branches invariably to the interrupt routine. _______ ________ Reset > NMI > DBC > Watchdog timer > Peripheral I/O > Single step > Address match Figure 1.11.8. Hardware interrupts priorities Interrupt resolution circuit When two or more interrupts are generated simultaneously, this circuit selects the interrupt with the highest priority level. Figure 1.11.9 shows the circuit that judges the interrupt priority level. 57 Mitsubishi microcomputers M16C / 30L Group Interrupt SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Priority level of each interrupt Level 0 (initial value) INT1 High Timer B2 Timer A1 INT2 INT0 Timer B1 Timer A2 UART1 reception UART0 reception UART2 reception/ACK Priority of peripheral I/O interrupts (if priority levels are same) A-D conversion Bus collision detection Timer A0 UART1 transmission UART0 transmission UART2 transmission/NACK Key input interrupt DMA0 Low Processor interrupt priority level (IPL) Interrupt request level judgment output to clock generating circuit (Fig.1.10.3) Interrupt enable flag (I flag) Address match Watchdog timer DBC NMI Reset Figure 1.11.9. Maskable interrupts priorities (peripheral I/O interrupts) 58 Interrupt request accepted Mitsubishi microcomputers M16C / 30L Group ______ INT Interrupt SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER ______ INT Interrupt ________ ________ INT0 to INT2 are triggered by the edges of external inputs. The edge polarity is selected using the polarity select bit. As for external interrupt input, an interrupt can be generated both at the rising edge and at the falling edge by setting “1” in the INTi interrupt polarity switching bit of the interrupt request cause select register (035F16). To select both edges, set the polarity switching bit of the corresponding interrupt control register to ‘falling edge’ (“0”). Figure 1.11.10 shows the Interrupt request cause select register. AA A AA A AAAA AA Interrupt request cause select register b7 b6 b5 b4 b3 0 0 0 0 0 b2 b1 b0 Symbol IFSR Address 035F16 Bit name Bit symbol When reset 0016 Function IFSR0 INT0 interrupt polarity switching bit 0 : One edge 1 : Two edges IFSR1 INT1 interrupt polarity switching bit 0 : One edge 1 : Two edges IFSR2 INT2 interrupt polarity switching bit 0 : One edge 1 : Two edges Reserved bit Must always be set to “0” Reserved bit Must always be set to “0” Reserved bit Must always be set to “0” Reserved bit Must always be set to “0” Reserved bit Must always be set to “0” AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A R W Figure 1.11.10. Interrupt request cause select register 59 Mitsubishi microcomputers M16C / 30L Group ________ NMI Interrupt SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER ______ NMI Interrupt ______ ______ ______ An NMI interrupt is generated when the input to the P85/NMI pin changes from “H” to “L”. The NMI interrupt is a non-maskable external interrupt. The pin level can be checked in the port P85 register (bit 5 at address 03F016). This pin cannot be used as a normal port input. Key Input Interrupt If the direction register of any of P104 to P107 is set for input and a falling edge is input to that port, a key input interrupt is generated. A key input interrupt can also be used as a key-on wakeup function for cancelling the wait mode or stop mode. However, if you intend to use the key input interrupt, do not use P104 to P107 as A-D input ports. Figure 1.11.11 shows the block diagram of the key input interrupt. Note that if an “L” level is input to any pin that has not been disabled for input, inputs to the other pins are not detected as an interrupt. Port P104-P107 pull-up select bit Pull-up transistor Key input interrupt control register Port P107 direction register (address 004D16) Port P107 direction register P107/KI3 Pull-up transistor Port P106 direction register Interrupt control circuit P106/KI2 Pull-up transistor Port P105 direction register P105/KI1 Pull-up transistor Port P104 direction register P104/KI0 Figure 1.11.11. Block diagram of key input interrupt 60 Key input interrupt request Mitsubishi microcomputers M16C / 30L Group Address Match Interrupt SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Address Match Interrupt An address match interrupt is generated when the address match interrupt address register contents match the program counter value. Two address match interrupts can be set, each of which can be enabled and disabled by an address match interrupt enable bit. Address match interrupts are not affected by the interrupt enable flag (I flag) and processor interrupt priority level (IPL). For an address match interrupt, the value of the program counter (PC) that is saved to the stack area varies depending on the instruction being executed. Note that when using the external data bus in width of 8 bits, the address match interrupt cannot be used for external area. Figure 1.11.12 shows the address match interrupt-related registers. Address match interrupt enable register b7 b6 b5 b4 b3 b2 b1 b0 Symbol AIER Address 000916 When reset XXXXXX002 AAAAAAAAAAAAAA AAAAAAAAAAAAAA AA A AAAAAAAAAAAAAA AA A AAAAAAAAAAAAAA AAAAAAAAAAAAAA Bit symbol Bit name Function AIER0 Address match interrupt 0 enable bit 0 : Interrupt disabled 1 : Interrupt enabled AIER1 Address match interrupt 1 enable bit 0 : Interrupt disabled 1 : Interrupt enabled RW Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be indeterminated. Address match interrupt register i (i = 0, 1) (b23) b7 (b19) b3 (b16)(b15) b0 b7 (b8) b0 b7 b0 Symbol RMAD0 RMAD1 Address 001216 to 001016 001616 to 001416 Function Address setting register for address match interrupt When reset X0000016 X0000016 AA A AAA Values that can be set R W 0000016 to FFFFF16 Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be indeterminated. Figure 1.11.12. Address match interrupt-related registers 61 Mitsubishi microcomputers M16C / 30L Group Precautions for Interrupts SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Precautions for Interrupts (1) Reading address 0000016 • When maskable interrupt is occurred, CPU reads the interrupt information (the interrupt number and interrupt request level) in the interrupt sequence. The interrupt request bit of the certain interrupt written in address 0000016 will then be set to “0”. Even if the address 0000016 is read out by software, “0” is set to the enabled highest priority interrupt source request bit. Therefore interrupt can be canceled and unexpected interrupt can occur. Do not read address 0000016 by software. (2) Setting the stack pointer • The value of the stack pointer immediately after reset is initialized to 000016. Accepting an interrupt before setting a value in the stack pointer may become a factor of runaway. Be sure to set a value in _______ the stack pointer before accepting an interrupt. When using the NMI interrupt, initialize the stack pointer at the beginning of a program. Concerning the first instruction immediately after reset, generat_______ ing any interrupts including the NMI interrupt is prohibited. _______ (3) The NMI interrupt _______ _______ •The NMI interrupt can not be disabled. Be sure to connect NMI pin to Vcc via a pull-up resistor if unused. Be sure to work on it. _______ • The NMI pin also serves as P85, which is exclusively input. Reading the contents of the P8 register allows reading the pin value. Use the reading of this pin only for establishing the pin level at the time _______ when the NMI interrupt is input. _______ • Do not attempt to go into stop mode with the input to the NMI pin being in the “L” state. With the input to _______ the NMI being in the “L” state, the CM10 is fixed to “0”, so attempting to go into stop mode is turned down. _______ • Do not attempt to go into wait mode with the input to the NMI pin being in the “L” state. With the input to _______ the NMI pin being in the “L” state, the CPU stops but the oscillation does not stop, so no power is saved. In this instance, the CPU is returned to the normal state by a later interrupt. _______ • Signals input to the NMI pin require “L” level and “H” level of 2 clock +300ns or more, from the operation clock of the CPU. (4) External interrupt ________ • Either an________ “L” level or an “H” level of at least 250 ns width is necessary for the signal input to pins INT0 through INT2 regardless of the CPU operation clock. ________ ________ • When the polarity of the INT0 to INT2 pins is changed, the interrupt request bit is sometimes set to “1”. After changing the polarity, set the interrupt request bit to “0”. Figure 1.11.13 shows the procedure for ______ changing the INT interrupt generate factor. Clear the interrupt enable flag to “0” (Disable interrupt) Set the interrupt priority level to level 0 (Disable INTi interrupt) Set the polarity select bit NOP X 2 Clear the interrupt request bit to “0” Set the interrupt priority level to level 1 to 7 (Enable the accepting of INTi interrupt request) Set the interrupt enable flag to “1” (Enable interrupt) Note: Execute the setting above individually. Don't execute two or more settings at once(by one instruction). ______ Figure 1.11.13. Switching condition of INT interrupt request 62 Mitsubishi microcomputers M16C / 30L Group Precautions for Interrupts SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER (5) Watchdog timer interrupt • Write to the watchdog timer start register after the watchdog timer interrupt occurs (initialize watchdog timer). (6) Rewrite the interrupt control register • To rewrite the interrupt control register, do so at a point that does not generate the interrupt request for that register. If there is possibility of the interrupt request occur, rewrite the interrupt control register after the interrupt is disabled. The program examples are described as follow: Example 1: INT_SWITCH1: FCLR I AND.B #00h, 0055h NOP NOP FSET I ; Disable interrupts. ; Clear TA0IC int. priority level and int. request bit. ; Four NOP instructions are required when using HOLD function. ; Enable interrupts. Example 2: INT_SWITCH2: FCLR I AND.B #00h, 0055h MOV.W MEM, R0 FSET I ; Disable interrupts. ; Clear TA0IC int. priority level and int. request bit. ; Dummy read. ; Enable interrupts. Example 3: INT_SWITCH3: PUSHC FLG FCLR I AND.B #00h, 0055h POPC FLG ; Push Flag register onto stack ; Disable interrupts. ; Clear TA0IC int. priority level and int. request bit. ; Enable interrupts. The reason why two NOP instructions (four when using the HOLD function) or dummy read are inserted before FSET I in Examples 1 and 2 is to prevent the interrupt enable flag I from being set before the interrupt control register is rewritten due to effects of the instruction queue. When changing an interrupt control register in a sate of interrupts being disabled, please read the following precautions on instructions used before changing the register. Changing a non-interrupt request bit If an interrupt request for an interrupt control register is generated during an instruction to rewrite the register is being executed, there is a case that the interrupt request bit is not set and consequently the interrupt is ignored. This will depend on the instruction. If this creates problems, use the below instructions to change the register. Instructions : AND, OR, BCLR, BSET Changing the interrupt request bit When attempting to clear the interrupt request bit of an interrupt control register, the interrupt request bit is not cleared sometimes. This will depend on the instruction. If this creates problems, use the below instructions to change the register. Instructions : MOV 63 Mitsubishi microcomputers M16C / 30L Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Watchdog Timer Watchdog Timer The watchdog timer has the function of detecting when the program is out of control. Therefore, we recommend using the watchdog timer to improve reliability of a system. The watchdog timer is a 15-bit counter which down-counts the clock derived by dividing the BCLK using the prescaler. Whether a watchdog timer interrupt is generated or reset is selected when an underflow occurs in the watchdog timer. When the watchdog timer interrupt is selected, write to the watchdog timer start register after the watchdog timer interrupt occurs (initialize watchdog timer). Watchdog timer interrupt is selected when bit 2 (PM12) of the processor mode register 1 (address 000516) is "0" and reset is selected when PM12 is "1". No value other than "1" can be written in PM12. Once when reset is selected (PM12="1"), watchdog timer interrupt cannot be selected by software. When XIN is selected for the BCLK, bit 7 of the watchdog timer control register (address 000F16) selects the prescaler division ratio (by 16 or by 128). When XCIN is selected as the BCLK, the prescaler is set for division by 2 regardless of bit 7 of the watchdog timer control register (address 000F16). Thus the watchdog timer's period can be calculated as given below. The watchdog timer's period is, however, subject to an error due to the prescaler. With XIN chosen for BCLK prescaler dividing ratio (16 or 128) X watchdog timer count (32768) Watchdog timer period = BCLK With XCIN chosen for BCLK Watchdog timer period = prescaler dividing ratio (2) X watchdog timer count (32768) BCLK For example, suppose that BCLK runs at 16 MHz and that 16 has been chosen for the dividing ratio of the prescaler, then the watchdog timer's period becomes approximately 32.8 ms. The watchdog timer is initialized by writing to the watchdog timer start register (address 000E16) and when a watchdog timer interrupt request is generated. The prescaler is initialized only when the microcomputer is reset. After a reset is cancelled, the watchdog timer and prescaler are both stopped. The count is started by writing to the watchdog timer start register (address 000E16). In stop mode, wait mode and hold state, the watchdog timer and prescaler are stopped. Counting is resumed from the held value when the modes or state are released. Also PM12 is initialized only when reset. The watchdog timer interrupt is selected after reset is cancelled. Figure 1.12.1 shows the block diagram of the watchdog timer. Figure 1.12.2 shows the watchdog timerrelated registers. 64 Mitsubishi microcomputers M16C / 30L Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Watchdog Timer Prescaler “CM07 = 0” “WDC7 = 0” 1/16 BCLK “PM12 = 0” Watchdog timer interrupt request “CM07 = 0” “WDC7 = 1” 1/128 Watchdog timer HOLD Reset “PM12 = 1” “CM07 = 1” 1/2 Write to the watchdog timer start register (address 000E16) Set to “7FFF16” RESET Figure 1.12.1. Block diagram of watchdog timer Watchdog timer control register b7 b6 b5 b4 b3 b2 b1 b0 0 0 Symbol WDC Bit symbol Address 000F16 When reset 000XXXXX2 Function Bit name High-order bit of watchdog timer Reserved bit Must always be set to “0” Reserved bit Must always be set to “0” WDC7 Prescaler select bit 0 : Divided by 16 1 : Divided by 128 AA AA A AA A AA A R W Watchdog timer start register b7 b0 Symbol WDTS Address 000E16 When reset Indeterminate Function The watchdog timer is initialized and starts counting after a write instruction to this register. The watchdog timer value is always initialized to “7FFF16” regardless of whatever value is written. A R W Figure 1.12.2. Watchdog timer control and start registers 65 Mitsubishi microcomputers M16C / 30L Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER DMAC DMAC This microcomputer has one DMAC (direct memory access controller) channel that allow data to be sent to memory without using the CPU. DMAC shares the same data bus with the CPU. The DMAC is given a higher right of using the bus than the CPU, which leads to working the cycle stealing method. On this account, the operation from the occurrence of DMA transfer request signal to the completion of 1-word (16bit) or 1-byte (8-bit) data transfer can be performed at high speed. Figure 1.13.1 shows the block diagram of the DMAC. Table 1.13.1 shows the DMAC specifications. Figures 1.13.2 to 1.13.4 show the registers used by the DMAC. AA AAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAA AA A AA AAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAA AA A AA AA AAA A AA AAA AA AA AA AA A AA AA AA A A AA AA A AA AA AA Address bus DMA0 source pointer SAR0(20) (addresses 002216 to 002016) DMA0 destination pointer DAR0 (20) (addresses 002616 to 002416) DMA0 transfer counter reload register TCR0 (16) (addresses 002916, 002816) DMA0 transfer counter TCR0 (16) Data bus low-order bits Data bus high-order bits DMA0 forward address pointer (20) (Note) DMA latch high-order bits DMA latch low-order bits AA Note: Pointer is incremented by a DMA request. Figure 1.13.1. Block diagram of DMAC Either a write signal to the software DMA request bit or an interrupt request signal is used as a DMA transfer request signal. But the DMA transfer is affected neither by the interrupt enable flag (I flag) nor by the interrupt priority level. The DMA transfer doesn't affect any interrupts either. If the DMAC is active (the DMA enable bit is set to 1), data transfer starts every time a DMA transfer request signal occurs. If the cycle of the occurrences of DMA transfer request signals is higher than the DMA transfer cycle, there can be instances in which the number of transfer requests doesn't agree with the number of transfers. For details, see the description of the DMA request bit. 66 Mitsubishi microcomputers M16C / 30L Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER DMAC Table 1.13.1. DMAC specifications Item No. of channels Transfer memory space Maximum No. of bytes transferred Specification 2 (cycle steal method) • From any address in the 1M bytes space to a fixed address • From a fixed address to any address in the 1M bytes space • From a fixed address to a fixed address (Note that DMA-related registers [002016 to 003F16] cannot be accessed) 128K bytes (with 16-bit transfers) or 64K bytes (with 8-bit transfers) ________ DMA request factors (Note) Falling edge of INT0 or both edge Timer A0 to timer A2 interrupt requests Timer B1 and timer B2 interrupt requests UART0 transfer and reception interrupt requests UART1 transfer and reception interrupt requests UART2 transfer and reception interrupt requests A-D conversion interrupt requests Software triggers Transfer unit 8 bits or 16 bits Transfer address direction forward/fixed (forward direction cannot be specified for both source and destination simultaneously) Transfer mode • Single transfer mode After the transfer counter underflows, the DMA enable bit turns to “0”, and the DMAC turns inactive • Repeat transfer mode After the transfer counter underflows, the value of the transfer counter reload register is reloaded to the transfer counter. The DMAC remains active unless a “0” is written to the DMA enable bit. DMA interrupt request generation timing When an underflow occurs in the transfer counter Active When the DMA enable bit is set to “1”. When the DMAC is active, data transfer starts every time a DMA transfer request signal occurs. Inactive • When the DMA enable bit is set to “0”. At the time of starting data transfer immediately after turning the DMAC active, the Reload timing for forward value of one of source pointer and destination pointer - the one specified for the address pointer and transfer forward direction - is reloaded to the forward direction address pointer, and the value counter of the transfer counter reload register is reloaded to the transfer counter. Writing to register Registers specified for forward direction transfer are always write enabled. Registers specified for fixed address transfer are write-enabled when the DMA enable bit is “0”. Reading the register Can be read at any time. However, when the DMA enable bit is “1”, reading the register set up as the forward register is the same as reading the value of the forward address pointer. Note: DMA transfer is not effective to any interrupt. DMA transfer is affected neither by the interrupt enable flag (I flag) nor by the interrupt priority level. 67 Mitsubishi microcomputers M16C / 30L Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER DMAC DMA0 request cause select register b7 b6 b5 b4 b3 b2 b1 b0 Symbol DM0SL Bit symbol DSEL0 Address 03B816 DMA request cause select bit DSEL2 DSEL3 DSEL4 DSEL5 DMS Figure 1.13.2. DMAC register (1) 68 Function Bit name DSEL1 DSR When reset 0016 Software DMA request bit b6 b5 b4 b3 b2 b1 b0 (DMS) 0 0 0 0 0 0 0 : Falling edge of INT0 pin 0 0 0 0 0 0 1 : Software trigger 0 0 0 0 0 1 0 : Timer A0 0 0 0 0 0 1 1 : Timer A1 0 0 0 0 1 0 0 : Timer A2 0 0 0 0 1 0 1 : Must not be set 0 0 0 0 1 1 0 : Must not be set 0 0 0 0 1 1 1 : Must not be set 0 0 0 1 0 0 0 : Timer B1 0 0 0 1 0 0 1 : Timer B2 0 0 0 1 0 1 0 : UART0 transmit 0 0 0 1 0 1 1 : UART0 receive 0 0 0 1 1 0 0 : UART2 transmit 0 0 0 1 1 0 1 : UART2 receive 0 0 0 1 1 1 0 : A-D conversion 0 0 0 1 1 1 1 : UART1 transmit 1 0 0 0 1 1 0 : Two edges of INT0 pin Must not be set except the above. If software trigger is selected, a DMA request is generated by setting this bit to “1” (When read, the value of this bit is always “0”) AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A R W Mitsubishi microcomputers M16C / 30L Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER DMAC DMA0 control register b7 b6 b5 b4 b3 b2 b1 b0 Symbol DM0CON Bit symbol Address 002C16 When reset 00000X002 Bit name Function DMBIT Transfer unit bit select bit 0 : 16 bits 1 : 8 bits DMASL Repeat transfer mode select bit 0 : Single transfer 1 : Repeat transfer DMAS DMA request bit (Note 1) 0 : DMA not requested 1 : DMA requested DMAE DMA enable bit 0 : Disabled 1 : Enabled DSD Source address direction select bit (Note 3) 0 : Fixed 1 : Forward DAD Destination address 0 : Fixed direction select bit (Note 3) 1 : Forward Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be “0”. AA AA AA A A A A AA AA R W (Note 2) Note 1: DMA request can be cleared by resetting the bit. Note 2: This bit can only be set to “0”. Note 3: Source address direction select bit and destination address direction select bit cannot be set to “1” simultaneously. Figure 1.13.3. DMAC register (2) 69 Mitsubishi microcomputers M16C / 30L Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER DMAC DMA0 source pointer (b23) b7 (b19) b3 (b16)(b15) b0 b7 (b8) b0 b7 b0 Symbol SAR0 Address 002216 to 002016 When reset Indeterminate Transfer address specification Function • Source pointer Stores the source address 0000016 to FFFFF16 Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be “0”. R W A DMA0 destination pointer (b23) b7 (b19) b3 (b16)(b15) b0 b7 (b8) b0 b7 b0 Symbol DAR0 Address 002616 to 002416 When reset Indeterminate Transfer address specification Function • Destination pointer Stores the destination address 0000016 to FFFFF16 Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be “0”. AA R W DMA0 transfer counter (b15) b7 (b8) b0 b7 b0 Symbol TCR0 Address 002916, 002816 Function • Transfer counter Set a value one less than the transfer count Figure 1.13.4. DMAC register (3) 70 When reset Indeterminate Transfer count specification 000016 to FFFF16 A R W Mitsubishi microcomputers M16C / 30L Group DMAC SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER (1) Transfer cycle The transfer cycle consists of the bus cycle in which data is read from memory or from the SFR area (source read) and the bus cycle in which the data is written to memory or to the SFR area (destination write). The number of read and write bus cycles depends on the source and destination addresses. In memory expansion mode and microprocessor mode, the number of read and write bus cycles also depends on the level of the BYTE pin. Also, the bus cycle itself is longer when software waits are inserted. (a) Effect of source and destination addresses When 16-bit data is transferred on a 16-bit data bus, and the source and destination both start at odd addresses, there are one more source read cycle and destination write cycle than when the source and destination both start at even addresses. (b) Effect of BYTE pin level When transferring 16-bit data over an 8-bit data bus (BYTE pin = “H”) in memory expansion mode and microprocessor mode, the 16 bits of data are sent in two 8-bit blocks. Therefore, two bus cycles are required for reading the data and two are required for writing the data. Also, in contrast to when the CPU accesses internal memory, when the DMAC accesses internal memory (internal ROM, internal RAM, and SFR), these areas are accessed using the data size selected by the BYTE pin. (c) Effect of software wait When the SFR area or a memory area with a software wait is accessed, the number of cycles is increased for the wait by 1 bus cycle. The length of the cycle is determined by BCLK. Figure 1.13.5 shows the example of the transfer cycles for a source read. For convenience, the destination write cycle is shown as one cycle and the source read cycles for the different conditions are shown. In reality, the destination write cycle is subject to the same conditions as the source read cycle, with the transfer cycle changing accordingly. When calculating the transfer cycle, remember to apply the respective conditions to both the destination write cycle and the source read cycle. For example (2) in Figure 1.13.5, if data is being transferred in 16-bit units on an 8-bit bus, two bus cycles are required for both the source read cycle and the destination write cycle. 71 Mitsubishi microcomputers M16C / 30L Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER DMAC (1) 8-bit transfers 16-bit transfers and the source address is even. BCLK Address bus CPU use Source Destination Dummy cycle CPU use RD signal WR signal Data bus CPU use Source Destination Dummy cycle CPU use (2) 16-bit transfers and the source address is odd Transferring 16-bit data on an 8-bit data bus (In this case, there are also two destination cycles). BCLK Address bus CPU use Source Source + 1 Destination Dummy cycle CPU use RD signal WR signal Data bus CPU use Source + 1 Destination Source Dummy cycle CPU use (3) One wait is inserted into the source read under the conditions in (1) BCLK Address bus CPU use Source Destination Dummy cycle CPU use RD signal WR signal Data bus CPU use Source Destination Dummy cycle CPU use (4) One wait is inserted into the source read under the conditions in (2) (When 16-bit data is transferred on an 8-bit data bus, there are two destination cycles). BCLK Address bus CPU use Source Source + 1 Destination Dummy cycle CPU use RD signal WR signal Data bus CPU use Source Source + 1 Destination Dummy cycle CPU use Note: The same timing changes occur with the respective conditions at the destination as at the source. Figure 1.13.5. Example of the transfer cycles for a source read 72 Mitsubishi microcomputers M16C / 30L Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER DMAC (2) DMAC transfer cycles Any combination of even or odd transfer read and write addresses is possible. Table 1.13.2 shows the number of DMAC transfer cycles. The number of DMAC transfer cycles can be calculated as follows: No. of transfer cycles per transfer unit = No. of read cycles x j + No. of write cycles x k Table 1.13.2. No. of DMAC transfer cycles Single-chip mode Transfer unit 8-bit transfers (DMBIT= “1”) 16-bit transfers (DMBIT= “0”) Memory expansion mode Bus width Access address Microprocessor mode No. of read No. of write No. of read No. of write cycles cycles cycles cycles 16-bit Even 1 1 1 1 (BYTE= “L”) Odd 1 1 1 1 8-bit Even — — 1 1 (BYTE = “H”) Odd — — 1 1 16-bit Even 1 1 1 1 (BYTE = “L”) Odd 2 2 2 2 8-bit Even — — 2 2 (BYTE = “H”) Odd — — 2 2 Coefficient j, k Internal memory Internal ROM/RAM Internal ROM/RAM No wait With wait 1 2 SFR area 2 External memory Separate bus Separate bus No wait With wait 1 2 Multiplex bus 3 73 Mitsubishi microcomputers M16C / 30L Group DMAC SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER DMA enable bit Setting the DMA enable bit to “1” makes the DMAC active. The DMAC carries out the following operations at the time data transfer starts immediately after DMAC is turned active. (1) Reloads the value of one of the source pointer and the destination pointer - the one specified for the forward direction - to the forward direction address pointer. (2) Reloads the value of the transfer counter reload register to the transfer counter. Thus overwriting “1” to the DMA enable bit with the DMAC being active carries out the operations given above, so the DMAC operates again from the initial state at the instant “1” is overwritten to the DMA enable bit. DMA request bit The DMAC can generate a DMA transfer request signal triggered by a factor chosen in advance out of DMA request factors. DMA request factors include the following. * Factors effected by using the interrupt request signals from the built-in peripheral functions and software DMA factors (internal factors) effected by a program. * External factors effected by utilizing the input from external interrupt signals. For the selection of DMA request factors, see the descriptions of the DMA0 factor selection register. The DMA request bit turns to “1” if the DMA transfer request signal occurs regardless of the DMAC's state (regardless of whether the DMA enable bit is set to “1” or “0”). It turns to “0” immediately before data transfer starts. In addition, it can be set to “0” by use of a program, but cannot be set to “1”. There can be instances in which a change in DMA request factor selection bit causes the DMA request bit to turn to “1”. So be sure to set the DMA request bit to “0” after the DMA request factor selection bit is changed. The DMA request bit turns to “1” if a DMA transfer request signal occurs, and turns to “0” immediately before data transfer starts. If the DMAC is active, data transfer starts immediately, so the value of the DMA request bit, if read by use of a program, turns out to be “0” in most cases. To examine whether the DMAC is active, read the DMA enable bit. Here follows the timing of changes in the DMA request bit. (1) Internal factors Except the DMA request factors triggered by software, the timing for the DMA request bit to turn to “1” due to an internal factor is the same as the timing for the interrupt request bit of the interrupt control register to turn to “1” due to several factors. Turning the DMA request bit to “0” due to an internal factor is timed to be effected immediately before the transfer starts. (2) External factors ________ An external factor is a factor caused to occur by the leading edge of input from the INT0 pin. ________ Selecting the INT0 pins as external factors using the DMA request factor selection bit causes input from these pins to become the DMA transfer request signals. The timing for the DMA request bit to turn to “1” when an external factor is selected synchronizes with the signal's edge applicable to the function specified by the DMA request factor selection bit (synchronizes ________ with the trailing edge of the input signal to INT0 pin, for example). With an external factor selected, the DMA request bit is timed to turn to “0” immediately before data transfer starts similarly to the state in which an internal factor is selected. 74 Mitsubishi microcomputers M16C / 30L Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Timer Timer There are five 16-bit timers. These timers can be classified by function into timers A (three) and timers B (two). All these timers function independently. Figures 1.14.1 and 1.14.2 show the block diagram of timers. Clock prescaler f1 XIN f8 1/8 1/4 f32 1/32 XCIN Clock prescaler reset flag (bit 7 at address 038116) set to “1” fC32 Reset f1 f8 f32 fC32 • Timer mode • One-shot timer mode • PWM mode Timer A0 interrupt TA0IN Noise filter Timer A0 • Event counter mode • Timer mode • One-shot timer mode • PWM mode TA1IN Noise filter Timer A1 interrupt Timer A1 • Event counter mode • Timer mode • One-shot timer mode • PWM mode Timer A2 interrupt TA2IN Noise filter Timer A2 • Event counter mode Timer B2 overflow Note : The TA0IN pin (P71) is shared with RxD2, so be careful. Figure 1.14.1. Timer A block diagram 75 Mitsubishi microcomputers M16C / 30L Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Timer Clock prescaler f1 XIN f8 1/8 1/4 f32 fC32 1/32 XCIN Clock prescaler reset flag (bit 7 at address 038116) set to “1” Reset f1 f8 f32 fC32 • Timer mode • Pulse width measuring mode TB1IN Noise filter Timer B1 interrupt Timer B1 • Event counter mode • Timer mode • Pulse width measuring mode TB2IN Noise filter Timer B2 interrupt Timer B2 • Event counter mode Timer A Figure 1.14.2. Timer B block diagram 76 Mitsubishi microcomputers M16C / 30L Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Timer A Timer A Figure 1.14.3 shows the block diagram of timer A. Figures 1.14.4 to 1.14.6 show the timer A-related registers. Except in event counter mode, timers A0 through A2 all have the same function. Use the timer Ai mode register (i = 0 to 2) bits 0 and 1 to choose the desired mode. Timer A has the four operation modes listed as follows: • Timer mode: The timer counts an internal count source. • Event counter mode: The timer counts pulses from an external source or a timer overflow. • One-shot timer mode: The timer stops counting when the count reaches “000016”. • Pulse width modulation (PWM) mode: The timer outputs pulses of a given width. Data bus high-order bits Clock source selection f1 f8 f32 High-order 8 bits Low-order 8 bits Clock selection • Timer (gate function) fC32 AAA AAA AA AA AA Data bus low-order bits • Timer • One shot • PWM Reload register (16) • Event counter Counter (16) Polarity selection Up count/down count Clock selection TAiIN (i = 0 to 2) Always down count except in event counter mode Count start flag (Address 038016) TB2 overflow To external trigger circuit TAj overflow Down count TAi Addresses TAj TAk Timer A1 Timer A0 038716 038616 Must not be set Timer A0 Timer A2 Timer A1 038916 038816 Timer A1 Must not be set Timer A2 038B16 038A16 (j = i – 1. Note, however, must not be set when i = 0) Up/down flag TAk overflow (k = i + 1. Note, however, must not be set when i = 2) (Address 038416) Pulse output TAiOUT (i = 0 to 2) Toggle flip-flop Figure 1.14.3. Block diagram of timer A Timer Ai mode register b7 b6 b5 b4 b3 b2 b1 b0 Symbol TAiMR(i=0 to 2) Bit symbol TMOD0 Bit name Operation mode select bit TMOD1 MR0 MR1 Address When reset 039616 to 039816 0016 Function b1 b0 0 0 : Timer mode 0 1 : Event counter mode 1 0 : One-shot timer mode 1 1 : Pulse width modulation (PWM) mode Function varies with each operation mode MR2 MR3 TCK0 TCK1 Count source select bit (Function varies with each operation mode) A A A A AA A AA A A AA A AA AA RW Figure 1.14.4. Timer A-related registers (1) 77 Mitsubishi microcomputers M16C / 30L Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Timer A Timer Ai register (Note 1) (b15) b7 (b8) b0 b7 Symbol TA0 TA1 TA2 b0 Address 038716,038616 038916,038816 038B16,038A16 When reset Indeterminate Indeterminate Indeterminate Function Values that can be set • Timer mode Counts an internal count source 000016 to FFFF16 RW AA AAA AA A • Event counter mode 000016 to FFFF16 Counts pulses from an external source or timer overflow • One-shot timer mode Counts a one shot width 000016 to FFFF16 (Note 2,4) • Pulse width modulation mode (16-bit PWM) Functions as a 16-bit pulse width modulator 000016 to FFFE16 (Note 3,4) • Pulse width modulation mode (8-bit PWM) Timer low-order address functions as an 8-bit prescaler and high-order address functions as an 8-bit pulse width modulator 0016 to FE16 (High-order address) 0016 to FF16 (Low-order address) (Note 3,4) Note 1: Read and write data in 16-bit units. Note 2: When the timer Ai register is set to “000016”, the counter does not operate and the timer Ai interrupt request is not generated. When the pulse is set to output, the pulse does not output from the TAiOUT pin. Note 3: When the timer Ai register is set to “000016”, the pulse width modulator does not operate and the output level of the TAiOUT pin remains “L” level, therefore the timer Ai interrupt request is not generated. This also occurs in the 8-bit pulse width modulator mode when the significant 8 high-order bits in the timer Ai register are set to “0016”. Note 4: Use MOV instruction to write to this register. Count start flag b7 b6 b5 b4 0 0 0 b3 b2 b1 b0 Symbol TABSR Address 038016 When reset 0016 AA AA AA AA AAAAAAAAAAAAAAAA AA A A AAAAAAAAAAAAAAAA AA Bit symbol Bit name TA0S Timer A0 count start flag TA1S Timer A1 count start flag TA2S Timer A2 count start flag Reserved bit R W Function 0 : Stops counting 1 : Starts counting Must always be set to “0” TB1S Timer B1 count start flag TB2S Timer B2 count start flag 0 : Stops counting 1 : Starts counting Up/down flag (Note 1) b7 b6 0 0 b5 b4 b3 0 0 b2 b1 b0 Symbol UDF Address 038416 Bit symbol Bit name TA0UD Timer A0 up/down flag TA1UD Timer A1 up/down flag TA2UD Timer A2 up/down flag Reserved bit TA2P When reset 0016 Function AA AA AA AA A A RW 0 : Down count 1 : Up count This specification becomes valid when the up/down flag content is selected for up/down switching cause Must always be set to “0” 0 : two-phase pulse signal processing disabled Timer A2 two-phase pulse signal processing select bit 1 : two-phase pulse signal processing enabled (Note 2) When not using the two-phase pulse signal processing function, set the select bit to “0” Reserved bit Must always be set to “0” Note 1: Use MOV instruction to write to this register. Note 2: Set the TAiIN and TAiOUT pins correspondent port direction registers to “0”. Figure 1.14.5. Timer A-related registers (2) 78 Mitsubishi microcomputers M16C / 30L Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Timer A One-shot start flag b7 b6 b5 b4 b3 0 0 b2 b1 Symbol ONSF b0 Address 038216 When reset 00X000002 Bit symbol Bit name TA0OS Timer A0 one-shot start flag TA1OS Timer A1 one-shot start flag TA2OS Timer A2 one-shot start flag Reserved bit Function 1 : Timer start When read, the value is “0” Must always be set to “0” AA AA AA AA AA AA RW Nothing is assigned. In an attempt to write to this bit, write “0”. The value, if read, turns out to be indeterminate. TA0TGL Timer A0 event/trigger select bit TA0TGH b7 b6 0 0 : Input on TA0IN is selected (Note) 0 1 : TB2 overflow is selected 1 0 : Must not be set 1 1 : TA1 overflow is selected Note: Set the corresponding port direction register to “0”. Trigger select register b7 b5 b4 0 0 0 b6 0 b3 b2 b1 b0 Symbol TRGSR Address 038316 Bit symbol Bit name Timer A1 event/trigger select bit TA1TGL TA1TGH Timer A2 event/trigger select bit TA2TGL TA2TGH Reserved bit When reset 0016 Function b1 b0 0 0 : Input on TA1IN is selected (Note) 0 1 : TB2 overflow is selected 1 0 : TA0 overflow is selected 1 1 : TA2 overflow is selected b3 b2 0 0 : Input on TA2IN is selected (Note) 0 1 : TB2 overflow is selected 1 0 : TA1 overflow is selected 1 1 : Must not be set Must always be set to “0” Note: Set the corresponding port direction register to “0”. AA AA AA A AA A AA A AA R W Clock prescaler reset flag b7 b6 b5 b4 b3 b2 b1 b0 Symbol CPSRF Bit symbol Address 038116 Bit name When reset 0XXXXXXX2 Function RW Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be indeterminate. AAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAA CPSR Clock prescaler reset flag 0 : No effect 1 : Prescaler is reset (When read, the value is “0”) Figure 1.14.6. Timer A-related registers (3) 79 Mitsubishi microcomputers M16C / 30L Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Timer A (1) Timer mode In this mode, the timer counts an internally generated count source. (See Table 1.14.1.) Figure 1.14.7 shows the timer Ai mode register in timer mode. Table 1.14.1. Specifications of timer mode Item Count source Count operation Specification f1, f8, f32, fC32 • Down count • When the timer underflows, it reloads the reload register contents before continuing counting 1/(n+1) n : Set value Count start flag is set (= 1) Count start flag is reset (= 0) When the timer underflows Programmable I/O port or gate input Programmable I/O port or pulse output Count value can be read out by reading timer Ai register • When counting stopped When a value is written to timer Ai register, it is written to both reload register and counter • When counting in progress When a value is written to timer Ai register, it is written to only reload register (Transferred to counter at next reload time) • Gate function Counting can be started and stopped by the TAiIN pin’s input signal • Pulse output function Each time the timer underflows, the TAiOUT pin’s polarity is reversed Divide ratio Count start condition Count stop condition Interrupt request generation timing TAiIN pin function TAiOUT pin function Read from timer Write to timer Select function Timer Ai mode register b7 b6 b5 0 b4 b3 b2 b1 b0 0 0 Symbol TAiMR(i=0 to 2) Bit symbol TMOD0 TMOD1 Address When reset 039616 to 039816 0016 Bit name Operation mode select bit Function b1 b0 0 0 : Timer mode MR0 Pulse output function select bit 0 : Pulse is not output (TAiOUT pin is a normal port pin) 1 : Pulse is output (Note 1) (TAiOUT pin is a pulse output pin) MR1 Gate function select bit b4 b3 AA AA AA AAA A AA AA AA AA RW 0 X (Note 2): Gate function not available (TAiIN pin is a normal port pin) 1 0 : Timer counts only when TAiIN pin is held “L” (Note 3) 1 1 : Timer counts only when TAiIN pin is held “H” (Note 3) MR2 MR3 0 (Must always be “0” in timer mode) TCK0 Count source select bit TCK1 b7 b6 0 0 : f1 0 1 : f8 1 0 : f32 1 1 : fC32 Note 1: The settings of the corresponding port register and port direction register are invalid. Note 2: The bit can be “0” or “1”. Note 3: Set the corresponding port direction register to “0”. Figure 1.14.7. Timer Ai mode register in timer mode 80 Mitsubishi microcomputers M16C / 30L Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Timer A (2) Event counter mode In this mode, the timer counts an external signal or an internal timer’s overflow. Timers A0 and A1 can count a single-phase external signal. Timer A2 can count a single-phase and a two-phase external signal. Table 1.14.2 lists timer specifications when counting a single-phase external signal. Figure 1.14.8 shows the timer Ai mode register in event counter mode. Table 1.14.3 lists timer specifications when counting a two-phase external signal. Figure 1.14.9 shows the timer Ai mode register in event counter mode. Table 1.14.2. Timer specifications in event counter mode (when not processing two-phase pulse signal) Item Specification Count source • External signals input to TAiIN pin (effective edge can be selected by software) • TB2 overflow, TAj overflow Count operation • Up count or down count can be selected by external signal or software • When the timer overflows or underflows, it reloads the reload register con tents before continuing counting (Note) Divide ratio 1/ (FFFF16 - n + 1) for up count 1/ (n + 1) for down count n : Set value Count start condition Count start flag is set (= 1) Count stop condition Count start flag is reset (= 0) Interrupt request generation timing The timer overflows or underflows TAiIN pin function Programmable I/O port or count source input TAiOUT pin function Programmable I/O port, pulse output, or up/down count select input Read from timer Count value can be read out by reading timer Ai register Write to timer • When counting stopped When a value is written to timer Ai register, it is written to both reload register and counter • When counting in progress When a value is written to timer Ai register, it is written to only reload register (Transferred to counter at next reload time) Select function • Free-run count function Even when the timer overflows or underflows, the reload register content is not reloaded to it • Pulse output function Each time the timer overflows or underflows, the TAiOUT pin’s polarity is reversed Note: This does not apply when the free-run function is selected. Timer Ai mode register (When not using two-phase pulse signal processing) b7 b6 b5 0 b4 b3 b2 b1 b0 Symbol Address TAiMR(i = 0 to 2) 039616 to 039816 0 1 When reset 0016 Function AA AAAA AA AA AA AA AA Bit symbol Bit name TMOD0 Operation mode select bit b1 b0 MR0 Pulse output function select bit 0 : Pulse is not output (TAiOUT pin is a normal port pin) 1 : Pulse is output (Note 2) (TAiOUT pin is a pulse output pin) MR1 Count polarity select bit (Note 3) 0 : Counts external signal's falling edge 1 : Counts external signal's rising edge MR2 Up/down switching cause select bit 0 : Up/down flag's content 1 : TAiOUT pin's input signal (Note 4) 0 1 : Event counter mode (Note 1) TMOD1 MR3 0 (Must always be “0” in event counter mode) TCK0 Count operation type select bit TCK1 Invalid when not using two-phase pulse signal processing Can be “0” or “1” 0 : Reload type 1 : Free-run type RW Note 1: In event counter mode, the count source is selected by the event / trigger select bit (addresses 038216 and 038316). Note 2: The settings of the corresponding port register and port direction register are invalid. Note 3: Valid only when counting an external signal. Note 4: When an “L” signal is input to the TAiOUT pin, the downcount is activated. When “H”, the upcount is activated. Set the corresponding port direction register to “0”. Figure 1.14.8. Timer Ai mode register in event counter mode 81 Mitsubishi microcomputers M16C / 30L Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Timer A Table 1.14.3. Timer specifications in event counter mode (when processing two-phase pulse signal with timer A2) Item Count source Count operation Divide ratio Count start condition Count stop condition Interrupt request generation timing TA2IN pin function TA2OUT pin function Read from timer Write to timer Select function Specification • Two-phase pulse signals input to TA2IN or TA2OUT pin • Up count or down count can be selected by two-phase pulse signal • When the timer overflows or underflows, the reload register content is reloaded and the timer starts over again (Note) 1/ (FFFF16 - n + 1) for up count 1/ (n + 1) for down count n : Set value Count start flag is set (= 1) Count start flag is reset (= 0) Timer overflows or underflows Two-phase pulse input (Set the TA2IN pin correspondent port direction register to “0”.) Two-phase pulse input (Set the TA2OUT pin correspondent port direction register to “0”.) Count value can be read out by reading timer A2 register • When counting stopped When a value is written to timer A2 register, it is written to both reload register and counter • When counting in progress When a value is written to timer A2 register, it is written to only reload register. (Transferred to counter at next reload time.) • Normal processing operation The timer counts up rising edges or counts down falling edges on the TA2IN pin when input signal on the TA2OUT pin is “H”. TA2OUT TA2IN Up count Up count Up count Note: This does not apply when the free-run function is selected. 82 Down count Down count Down count Mitsubishi microcomputers M16C / 30L Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Timer A Timer Ai mode register (When using two-phase pulse signal processing) (Note) b6 0 b5 b4 b3 b2 b1 b0 0 1 0 0 0 1 Symbol TA2MR Address 039816 When reset 0016 Bit name TMOD0 Operation mode select bit TMOD1 Function b1 b0 0 1 : Event counter mode MR0 0 (Must always be “0” when using two-phase pulse signal processing) MR1 0 (Must always be “0” when using two-phase pulse signal processing) MR2 1 (Must always be “1” when using two-phase pulse signal processing) MR3 0 (Must always be “0” when using two-phase pulse signal processing) TCK0 Count operation type select bit TCK1 0 (Must always be “0” when using two-phase pulse signal processing) 0 : Reload type 1 : Free-run type AA A AA A AA A AA A AA A AA A AA A AA A AA A RW Note : When performing two-phase pulse signal processing, make sure the two-phase pulse signal processing operation select bit (address 038416) is set to “1”. Also, always be sure to set the event/trigger select bit (address 038316) to “00”. Figure 1.14.9. Timer Ai mode register in event counter mode 83 Mitsubishi microcomputers M16C / 30L Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Timer A (3) One-shot timer mode In this mode, the timer operates only once. (See Table 1.14.4.) When a trigger occurs, the timer starts up and continues operating for a given period. Figure 1.14.10 shows the timer Ai mode register in one-shot timer mode. Table 1.14.4. Timer specifications in one-shot timer mode Item Count source Count operation Specification f1, f8, f32, fC32 • The timer counts down • When the count reaches 000016, the timer stops counting after reloading a new count • If a trigger occurs when counting, the timer reloads a new count and restarts counting 1/n n : Set value • An external trigger is input • The timer overflows • The one-shot start flag is set (= 1) • A new count is reloaded after the count has reached 000016 • The count start flag is reset (= 0) The count reaches 000016 Programmable I/O port or trigger input Programmable I/O port or pulse output When timer Ai register is read, it indicates an indeterminate value • When counting stopped When a value is written to timer Ai register, it is written to both reload register and counter • When counting in progress When a value is written to timer Ai register, it is written to only reload register (Transferred to counter at next reload time) Divide ratio Count start condition Count stop condition Interrupt request generation timing TAiIN pin function TAiOUT pin function Read from timer Write to timer Timer Ai mode register b7 b6 b5 0 b4 b3 b2 b1 b0 1 0 Symbol Address When reset TAiMR(i = 0 to 2) 039616 to 039816 0016 AA A AAA AAA AA A AA A AA A AAA AA A AAA Bit symbol Bit name TMOD0 Operation mode select bit b1 b0 MR0 Pulse output function select bit 0 : Pulse is not output (TAiOUT pin is a normal port pin) 1 : Pulse is output (Note 1) (TAiOUT pin is a pulse output pin) MR1 External trigger select bit (Note 2) 0 : Falling edge of TAiIN pin's input signal (Note 3) 1 : Rising edge of TAiIN pin's input signal (Note 3) MR2 Trigger select bit 0 : One-shot start flag is valid 1 : Selected by event/trigger select bits MR3 0 (Must always be “0” in one-shot timer mode) TCK0 Count source select bit TMOD1 TCK1 Function 1 0 : One-shot timer mode b7 b6 0 0 : f1 0 1 : f8 1 0 : f32 1 1 : fC32 RW Note 1: The settings of the corresponding port register and port direction register are invalid. Note 2: Valid only when the TAiIN pin is selected by the event/trigger select bit (addresses 038216 and 038316). If timer overflow is selected, this bit can be “1” or “0”. Note 3: Set the corresponding port direction register to “0”. Figure 1.14.10. Timer Ai mode register in one-shot timer mode 84 Mitsubishi microcomputers M16C / 30L Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Timer A (4) Pulse width modulation (PWM) mode In this mode, the timer outputs pulses of a given width in succession. (See Table 1.14.5.) In this mode, the counter functions as either a 16-bit pulse width modulator or an 8-bit pulse width modulator. Figure 1.14.11 shows the timer Ai mode register in pulse width modulation mode. Figure 1.14.12 shows the example of how a 16-bit pulse width modulator operates. Figure 1.14.13 shows the example of how an 8bit pulse width modulator operates. Table 1.14.5. Timer specifications in pulse width modulation mode Item Specification Count source Count operation 16-bit PWM 8-bit PWM Count start condition Count stop condition Interrupt request generation timing TAiIN pin function TAiOUT pin function Read from timer Write to timer f1, f8, f32, fC32 • The timer counts down (operating as an 8-bit or a 16-bit pulse width modulator) • The timer reloads a new count at a rising edge of PWM pulse and continues counting • The timer is not affected by a trigger that occurs when counting • High level width n / fi n : Set value • Cycle time (216-1) / fi fixed • High level width n (m+1) / fi n : values set to timer Ai register’s high-order address • Cycle time (28-1) (m+1) / fi m : values set to timer Ai register’s low-order address • External trigger is input • The timer overflows • The count start flag is set (= 1) • The count start flag is reset (= 0) PWM pulse goes “L” Programmable I/O port or trigger input Pulse output When timer Ai register is read, it indicates an indeterminate value • When counting stopped When a value is written to timer Ai register, it is written to both reload register and counter • When counting in progress When a value is written to timer Ai register, it is written to only reload register (Transferred to counter at next reload time) Timer Ai mode register b7 b6 b5 b4 b3 b2 b1 b0 1 1 1 Symbol TAiMR(i=0 to 2) Bit symbol TMOD0 TMOD1 Address When reset 039616 to 039816 0016 Bit name Operation mode select bit Function b1 b0 1 1 : PWM mode A AA AAA A AA AA AA A AA A AA AA AA MR0 1 (Must always be “1” in PWM mode) MR1 External trigger select bit (Note 1) 0: Falling edge of TAiIN pin's input signal (Note 2) 1: Rising edge of TAiIN pin's input signal (Note 2) MR2 Trigger select bit 0: Count start flag is valid 1: Selected by event/trigger select bits MR3 16/8-bit PWM mode select bit 0: Functions as a 16-bit pulse width modulator 1: Functions as an 8-bit pulse width modulator TCK0 Count source select bit 0 0 : f1 0 1 : f8 1 0 : f32 1 1 : fC32 b7 b6 TCK1 R W Note 1: Valid only when the TAiIN pin is selected by the event/trigger select bit (addresses 038216 and 038316). If timer overflow is selected, this bit can be “1” or “0”. Note 2: Set the corresponding port direction register to “0”. Figure 1.14.11. Timer Ai mode register in pulse width modulation mode 85 Mitsubishi microcomputers M16C / 30L Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Timer A Condition : Reload register = 000316, when external trigger (rising edge of TAiIN pin input signal) is selected 1 / fi X (2 16 – 1) Count source “H” TAiIN pin input signal “L” Trigger is not generated by this signal 1 / fi X n PWM pulse output from TAiOUT pin “H” Timer Ai interrupt request bit “1” “L” “0” fi : Frequency of count source (f1, f8, f32, fC32) Cleared to “0” when interrupt request is accepted, or cleared by software Note: n = 000016 to FFFE16. Figure 1.14.12. Example of how a 16-bit pulse width modulator operates Condition : Reload register high-order 8 bits = 0216 Reload register low-order 8 bits = 0216 External trigger (falling edge of TAiIN pin input signal) is selected 1 / fi X (m + 1) X (2 8 – 1) Count source (Note1) TAiIN pin input signal “H” “L” AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA 1 / fi X (m + 1) “H” Underflow signal of 8-bit prescaler (Note2) “L” 1 / fi X (m + 1) X n PWM pulse output from TAiOUT pin “H” Timer Ai interrupt request bit “1” “L” “0” fi : Frequency of count source (f1, f8, f32, fC32) Cleared to “0” when interrupt request is accepted, or cleaerd by software Note 1: The 8-bit prescaler counts the count source. Note 2: The 8-bit pulse width modulator counts the 8-bit prescaler's underflow signal. Note 3: m = 0016 to FF16; n = 0016 to FE16. Figure 1.14.13. Example of how an 8-bit pulse width modulator operates 86 Mitsubishi microcomputers M16C / 30L Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Timer B Timer B Figure 1.14.14 shows the block diagram of timer B. Figures 1.14.15 and 1.14.16 show the timer B-related registers. Use the timer Bi mode register (i = 1, 2) bits 0 and 1 to choose the desired mode. Timer B has three operation modes listed as follows: • Timer mode: The timer counts an internal count source. • Event counter mode: The timer counts pulses from an external source or a timer overflow. • Pulse period/pulse width measuring mode: The timer measures an external signal's pulse period or pulse width. Data bus high-order bits Data bus low-order bits Clock source selection High-order 8 bits Low-order 8 bits f1 • Timer • Pulse period/pulse width measurement f8 f32 fC32 Reload register (16) Clock selection Counter (16) • Event counter Count start flag Polarity switching and edge pulse TBiIN (i = 1, 2) (address 038016) Counter reset circuit Can be selected in only event counter mode TBi Timer B1 Timer B2 TBj overflow (j = i – 1. Note, however, must not be set when i = 1) Address 039316 039216 039516 039416 TBj Must not be set Timer B1 Figure 1.14.14. Block diagram of timer B Timer Bi mode register b7 b6 b5 b4 b3 b2 b1 b0 Symbol TBiMR(i = 1, 2) Bit symbol TMOD0 Address 039C16, 039D16 Function Bit name Operation mode select bit TMOD1 MR0 When reset 00XX00002 b1 b0 0 0 : Timer mode 0 1 : Event counter mode 1 0 : Pulse period/pulse width measurement mode 1 1 : Must not be set. Function varies with each operation mode MR1 Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be indeterminate. MR3 TCK0 TCK1 Function varies with each operation mode Count source select bit (Function varies with each operation mode) AAA A AA A A AA AA AA R W Figure 1.14.15. Timer B-related registers (1) 87 Mitsubishi microcomputers M16C / 30L Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Timer B Timer Bi register (Note) (b15) b7 (b8) b0 b7 Symbol TB1 TB2 b0 Address 039316, 039216 039516, 039416 Function When reset Indeterminate Indeterminate Values that can be set • Timer mode Counts the timer's period 000016 to FFFF16 • Event counter mode Counts external pulses input or a timer overflow 000016 to FFFF16 • Pulse period / pulse width measurement mode Measures a pulse period or width Note: Read and write data in 16-bit units. A A A RW Count start flag b7 b6 b5 b4 0 0 0 b3 b2 b1 b0 Symbol TABSR Address 038016 When reset 0016 AAAAAAAAAAAAAAA A AAAAAAAAAAAAAAA A AAAAAAAAAAAAAAA A AAAAAAAAAAAAAAA A AAAAAAAAAAAAAAA A Bit symbol Bit name TA0S Timer A0 count start flag TA1S Timer A1 count start flag TA2S Timer A2 count start flag Reverved bit Function RW 0 : Stops counting 1 : Starts counting Must always be set to “0” TB1S Timer B1 count start flag TB2S Timer B2 count start flag 0 : Stops counting 1 : Starts counting Clock prescaler reset flag b7 b6 b5 b4 b3 b2 b1 b0 Symbol CPSRF Address 038116 Bit symbol Bit name When reset 0XXXXXXX2 Function R W AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA A AAAAAAAAAAAAAAA Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be indeterminate. CPSR Clock prescaler reset flag Figure 1.14.16. Timer B-related registers (2) 88 0 : No effect 1 : Prescaler is reset (When read, the value is “0”) Mitsubishi microcomputers M16C / 30L Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Timer B (1) Timer mode In this mode, the timer counts an internally generated count source. (See Table 1.14.6.) Figure 1.14.17 shows the timer Bi mode register in timer mode. Table 1.14.6. Timer specifications in timer mode Item Count source Count operation Specification Divide ratio Count start condition Count stop condition Interrupt request generation timing TBiIN pin function Read from timer Write to timer AA A AA A f1, f8, f32, fC32 • Counts down • When the timer underflows, it reloads the reload register contents before continuing counting 1/(n+1) n : Set value Count start flag is set (= 1) Count start flag is reset (= 0) The timer underflows Programmable I/O port Count value is read out by reading timer Bi register • When counting stopped When a value is written to timer Bi register, it is written to both reload register and counter • When counting in progress When a value is written to timer Bi register, it is written to only reload register (Transferred to counter at next reload time) Timer Bi mode register b7 b6 b5 b4 b3 b2 b1 b0 0 0 Symbol TBiMR(i=1, 2) Address 039C16, 039D16 Bit symbol Bit name TMOD0 Operation mode select bit When reset 00XX00002 Function b1 b0 0 0 : Timer mode TMOD1 MR0 MR1 Invalid in timer mode Can be “0” or “1” Nothing is assiigned. In an attempt to write to this bit, write “0”. The value, if read, turns out to be indeterminate. MR3 Invalid in timer mode. In an attempt to write to this bit, write “0”. The value, if read in timer mode, turns out to be indeterminate. TCK0 Count source select bit TCK1 b7 b6 0 0 : f1 0 1 : f8 1 0 : f32 1 1 : fC32 AA AA AA AAA A AA A AA A AA AA AA AA AA AA AA AA AA R W Figure 1.14.17. Timer Bi mode register in timer mode 89 Mitsubishi microcomputers M16C / 30L Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Timer B (2) Event counter mode In this mode, the timer counts an external signal or an internal timer's overflow. (See Table 1.14.7.) Figure 1.14.18 shows the timer Bi mode register in event counter mode. Table 1.14.7. Timer specifications in event counter mode Item Count source Specification • External signals input to TBiIN pin • Effective edge of count source can be a rising edge, a falling edge, or falling and rising edges as selected by software Count operation • Counts down • When the timer underflows, it reloads the reload register contents before continuing counting Divide ratio 1/(n+1) n : Set value Count start condition Count start flag is set (= 1) Count stop condition Count start flag is reset (= 0) Interrupt request generation timing The timer underflows TBiIN pin function Read from timer Write to timer AA AA Count source input Count value can be read out by reading timer Bi register • When counting stopped When a value is written to timer Bi register, it is written to both reload register and counter • When counting in progress When a value is written to timer Bi register, it is written to only reload register (Transferred to counter at next reload time) Timer Bi mode register b7 b6 b5 b4 b3 b2 b1 b0 0 1 Symbol TBiMR(i=1, 2) Address 039C16, 039D16 Bit symbol Bit name TMOD0 Operation mode select bit TMOD1 MR0 Count polarity select bit (Note 1) MR1 When reset 00XX00002 Function b1 b0 0 1 : Event counter mode b3 b2 0 0 : Counts external signal's falling edges 0 1 : Counts external signal's rising edges 1 0 : Counts external signal's falling and rising edges 1 1 : Must not be set. Nothing is assigned. In an attempt to write to this bit, write “0”. The value, if read, turns out to be indeterminate. MR3 Invalid in event counter mode. In an attempt to write to this bit, write “0”. The value, if read in event counter mode, turns out to be indeterminate. TCK0 Invalid in event counter mode. Can be “0” or “1”. TCK1 Event clock select 0 : Input from TBiIN pin (Note 2) 1 : TBj overflow (j = i – 1; however, must not be set, when i = 1) Note 1: Valid only when input from the TBiIN pin is selected as the event clock. If timer's overflow is selected, this bit can be “0” or “1”. Note 2: Set the corresponding port direction register to “0”. Figure 1.14.18. Timer Bi mode register in event counter mode 90 AA AA AA AA R W AAA AA Mitsubishi microcomputers M16C / 30L Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Timer B (3) Pulse period/pulse width measurement mode In this mode, the timer measures the pulse period or pulse width of an external signal. (See Table 1.14.8.) Figure 1.14.19 shows the timer Bi mode register in pulse period/pulse width measurement mode. Figure 1.14.20 shows the operation timing when measuring a pulse period. Figure 1.14.21 shows the operation timing when measuring a pulse width. Table 1.14.8. Timer specifications in pulse period/pulse width measurement mode Item Count source Count operation Specification f1, f8, f32, fC32 • Up count • Counter value “000016” is transferred to reload register at measurement pulse's effective edge and the timer continues counting Count start condition Count start flag is set (= 1) Count stop condition Count start flag is reset (= 0) Interrupt request generation timing • When measurement pulse's effective edge is input (Note 1) • When an overflow occurs. (Simultaneously, the timer Bi overflow flag changes to “1”. Assume that the count start flag condition is “1” and then the timer Bi overflow flag becomes “1”. If the timer Bi mode register has a writeaccess after next count cycle of the timer from the above condition, the timer Bi overflow flag becomes “0”.) TBiIN pin function Measurement pulse input Read from timer When timer Bi register is read, it indicates the reload register’s content (measurement result) (Note 2) Write to timer Cannot be written to Note 1: An interrupt request is not generated when the first effective edge is input after the timer has started counting. Note 2: The value read out from the timer Bi register is indeterminate until the second effective edge is input after the timer has started counting. Timer Bi mode register b7 b6 b5 b4 b3 b2 b1 b0 1 0 Symbol TBiMR(i=1, 2) Bit symbol TMOD0 TMOD1 MR0 Address 039C16, 039D16 When reset 00XX00002 Bit name Operation mode select bit Measurement mode select bit MR1 Function b1 b0 1 0 : Pulse period / pulse width measurement mode b3 b2 0 0 : Pulse period measurement (Interval between measurement pulse's falling edge to falling edge) 0 1 : Pulse period measurement (Interval between measurement pulse's rising edge to rising edge) 1 0 : Pulse width measurement (Interval between measurement pulse's falling edge to rising edge, and between rising edge to falling edge) 1 1 : Must not be set. Nothing is assigned. In an attempt to write to this bit, write “0”. The value, if read, turns out to be indeterminate. MR3 Timer Bi overflow flag (Note) TCK0 Count source select bit TCK1 0 : Timer did not overflow 1 : Timer has overflowed b7 b6 0 0 : f1 0 1 : f8 1 0 : f32 1 1 : fC32 AAAA AAA AA AAA A A AA A AAA A AAA A R W Note: It is indeterminate when reset. Assume that the count start flag condition is “1” and then the timer Bi overflow flag becomes “1”. If the timer Bi mode register has a write access after next count cycle of the timer from the above condition, the timer Bi overflow flag becomes “0”. This flag cannot be set to “1” by software. Figure 1.14.19. Timer Bi mode register in pulse period/pulse width measurement mode 91 Mitsubishi microcomputers M16C / 30L Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Timer B When measuring measurement pulse time interval from falling edge to falling edge Count source Measurement pulse Reload register transfer timing “H” “L” Transfer (indeterminate value) Transfer (measured value) counter (Note 1) (Note 1) (Note 2) Timing at which counter reaches “000016” “1” Count start flag “0” Timer Bi interrupt request bit “1” Timer Bi overflow flag “1” “0” Cleared to “0” when interrupt request is accepted, or cleared by software. “0” Note 1: Counter is initialized at completion of measurement. Note 2: Timer has overflowed. Figure 1.14.20. Operation timing when measuring a pulse period Count source Measurement pulse Reload register transfer timing “H” “L” counter Transfer (indeterminate value) (Note 1) Transfer (measured value) Transfer (measured value) (Note 1) (Note 1) Transfer (measured value) (Note 1) (Note 2) Timing at which counter reaches “000016” Count start flag “1” “0” Timer Bi interrupt request bit “1” “0” Cleared to “0” when interrupt request is accepted, or cleared by software. Timer Bi overflow flag “1” “0” Note 1: Counter is initialized at completion of measurement. Note 2: Timer has overflowed. Figure 1.14.21. Operation timing when measuring a pulse width 92 Mitsubishi microcomputers M16C / 30L Group Serial I/O SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Serial I/O Serial I/O is configured as three channels: UART0, UART1, UART2. UART0, UART1 and UART2 each have an exclusive timer to generate a transfer clock, so they operate independently of each other. Figure 1.16.1 shows the block diagram of UART0, UART1 and UART2. Figures 1.16.2 and 1.16.3 show the block diagram of the transmit/receive unit. UARTi (i = 0 to 2) has two operation modes: a clock synchronous serial I/O mode and a clock asynchronous serial I/O mode (UART mode). The contents of the serial I/O mode select bits (bits 0 to 2 at addresses 03A016, 03A816 and 037816) determine whether UARTi is used as a clock synchronous serial I/O or as a UART. Although a few functions are different, UART0, UART1 and UART2 have almost the same functions. UART2, in particular, is used for the SIM interface with some extra settings added in clock-asynchronous serial I/O mode (Note). It also has the bus collision detection function that generates an interrupt request if the TxD pin and the RxD pin are different in level. Table 1.16.1 shows the comparison of functions of UART0 through UART2, and Figures 1.16.4 to 1.16.9 show the registers related to UARTi. Note: SIM : Subscriber Identity Module Table 1.16.1. Comparison of functions of UART0 through UART2 Function UART0 UART1 UART2 CLK polarity selection Possible (Note 1) Possible (Note 1) Possible (Note 1) LSB first / MSB first selection Possible (Note 1) Possible (Note 1) Possible (Note 2) Continuous receive mode selection Possible (Note 1) Possible (Note 1) Possible (Note 1) Transfer clock output from multiple pins selection Impossible Possible (Note 1) Impossible Serial data logic switch Impossible Impossible Sleep mode selection Possible TxD, RxD I/O polarity switch Impossible Impossible Possible TxD, RxD port output format CMOS output CMOS output N-channel open-drain output Parity error signal output Impossible Impossible Possible Bus collision detection Impossible Impossible Possible (Note 3) Possible Possible (Note 3) (Note 4) Impossible (Note 4) Note 1: Only when clock synchronous serial I/O mode. Note 2: Only when clock synchronous serial I/O mode and 8-bit UART mode. Note 3: Only when UART mode. Note 4: Using for SIM interface. 93 Mitsubishi microcomputers M16C / 30L Group Serial I/O SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER (UART0) RxD0 TxD0 UART reception 1/16 Clock source selection Bit rate generator Internal (address 03A116) f1 f8 f32 1 / (n0+1) Reception control circuit Clock synchronous type UART transmission 1/16 Transmission control circuit Clock synchronous type External Receive clock Transmit/ receive unit Transmit clock Clock synchronous type (when internal clock is selected) 1/2 Clock synchronous type (when internal clock is selected) Clock synchronous type (when external clock is selected) CLK polarity reversing circuit CLK0 CTS/RTS disabled CTS/RTS selected RTS0 CTS0 / RTS0 Vcc CTS/RTS disabled CTS0 (UART1) RxD1 TxD1 1/16 Clock source selection Bit rate generator Internal (address 03A916) f1 f8 f32 UART reception 1 / (n1+1) UART transmission 1/16 CTS1 / RTS1/ CLKS1 Clock synchronous type (when internal clock is selected) Transmit clock Clock synchronous type (when external clock is selected) CTS/RTS disabled CTS/RTS selected Clock output pin select switch Transmit/ receive unit (when internal clock is selected) 1/2 CLK1 Transmission control circuit Clock synchronous type Clock synchronous type External CLK polarity reversing circuit Reception control circuit Clock synchronous type Receive clock RTS1 VCC CTS/RTS disabled CTS1 (UART2) RxD2 TxD polarity reversing circuit RxD polarity reversing circuit UART reception Clock source selection Bit rate generator f1 Internal (address 037916) f8 f32 1 / (n2+1) 1/16 Clock synchronous type UART transmission 1/16 Clock synchronous type External Reception control circuit Transmission control circuit Receive clock Transmit/ receive unit Transmit clock Clock synchronous type 1/2 CLK2 CLK polarity reversing circuit (when internal clock is selected) Clock synchronous type (when internal clock is selected) CTS/RTS selected Clock synchronous type (when external clock is selected) CTS/RTS disabled RTS2 CTS2 / RTS2 Vcc CTS/RTS disabled CTS2 n0 : Values set to UART0 bit rate generator (U0BRG) n1 : Values set to UART1 bit rate generator (U1BRG) n2 : Values set to UART2 bit rate generator (U2BRG) Figure 1.16.1. Block diagram of UARTi (i = 0 to 2) 94 TxD2 Mitsubishi microcomputers M16C / 30L Group Serial I/O SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Clock synchronous type PAR disabled 1SP RxDi SP SP UART (7 bits) UART (8 bits) Clock synchronous type UARTi receive register UART (7 bits) PAR 2SP PAR enabled UART UART (9 bits) Clock synchronous type UART (8 bits) UART (9 bits) 0 0 0 0 0 0 0 D8 D7 D6 D5 D4 D3 D2 D1 D0 UARTi receive buffer register Address 03A616 Address 03A716 Address 03AE16 Address 03AF16 MSB/LSB conversion circuit Data bus high-order bits Data bus low-order bits MSB/LSB conversion circuit D7 D8 D6 D5 D4 D3 D2 D1 UART (9 bits) 2SP SP SP Clock synchronous type UART TxDi PAR 1SP UARTi transmit buffer register Address 03A216 Address 03A316 Address 03AA16 Address 03AB16 UART (8 bits) UART (9 bits) PAR enabled D0 PAR disabled “0” Clock synchronous type UART (7 bits) UARTi transmit register UART (7 bits) UART (8 bits) Clock synchronous type SP: Stop bit PAR: Parity bit Figure 1.16.2. Block diagram of UARTi (i = 0, 1) transmit/receive unit 95 Mitsubishi microcomputers M16C / 30L Group Serial I/O SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER No reverse RxD data reverse circuit RxD2 Reverse Clock synchronous type PAR disabled 1SP SP SP UART2 receive register UART(7 bits) PAR 2SP PAR enabled 0 UART (7 bits) UART (8 bits) Clock synchronous type 0 0 0 UART 0 Clock synchronous type UART (9 bits) 0 0 UART (8 bits) UART (9 bits) D8 D0 UART2 receive buffer register Logic reverse circuit + MSB/LSB conversion circuit Address 037E16 Address 037F16 D7 D6 D5 D4 D3 D2 D1 Data bus high-order bits Data bus low-order bits Logic reverse circuit + MSB/LSB conversion circuit D7 D8 D6 D5 D4 D3 D2 D1 D0 UART2 transmit buffer register Address 037A16 Address 037B16 UART (8 bits) UART (9 bits) PAR enabled 2SP SP SP UART (9 bits) Clock synchronous type UART PAR 1SP PAR disabled “0” Clock synchronous type UART (7 bits) UART (8 bits) UART2 transmit register UART(7 bits) Clock synchronous type Error signal output disable No reverse TxD data reverse circuit Error signal output circuit Error signal output enable Reverse SP: Stop bit PAR: Parity bit Figure 1.16.3. Block diagram of UART2 transmit/receive unit 96 TxD2 Mitsubishi microcomputers M16C / 30L Group Serial I/O SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER UARTi transmit buffer register (Note) (b15) b7 (b8) b0 b7 b0 Symbol U0TB U1TB U2TB Address 03A316, 03A216 03AB16, 03AA16 037B16, 037A16 When reset Indeterminate Indeterminate Indeterminate Function AA R W Transmit data Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be indeterminate. Note: Use MOV instruction to write to this register. UARTi receive buffer register (b15) b7 (b8) b0 b7 b0 Bit symbol Symbol U0RB U1RB U2RB Address 03A716, 03A616 03AF16, 03AE16 037F16, 037E16 When reset Indeterminate Indeterminate Indeterminate Function (During clock synchronous serial I/O mode) Bit name Receive data Function (During UART mode) Receive data Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be “0”. ABT Arbitration lost detecting flag (Note 2) OER Overrun error flag (Note 1) 0 : No overrun error 1 : Overrun error found 0 : No overrun error 1 : Overrun error found FER Framing error flag (Note 1) Invalid 0 : No framing error 1 : Framing error found PER Parity error flag (Note 1) Invalid 0 : No parity error 1 : Parity error found SUM Error sum flag (Note 1) Invalid 0 : No error 1 : Error found 0 : Not detected 1 : Detected Invalid A AA AA AA A R W Note 1: Bits 15 through 12 are set to “0” when the serial I/O mode select bit (bits 2 to 0 at addresses 03A016, 03A816 and 037816) are set to “0002” or the receive enable bit is set to “0”. (Bit 15 is set to “0” when bits 14 to 12 all are set to “0”.) Bits 14 and 13 are also set to “0” when the lower byte of the UARTi receive buffer register (addresses 03A616, 03AE16 and 037E16) is read out. Note 2: Arbitration lost detecting flag is allocated to U2RB and noting but “0” may be written. Nothing is assigned in bit 11 of U0RB and U1RB. When write, set “0”. The value, if read, turns out to be “0”. UARTi bit rate generator (Note 1, 2) b7 b0 Symbol U0BRG U1BRG U2BRG Address 03A116 03A916 037916 When reset Indeterminate Indeterminate Indeterminate Function Assuming that set value = n, BRGi divides the count source by n+1 Note 1: Write a value to this register while transmit/receive halts. Note 2: Use MOV instruction to write to this register. Values that can be set 0016 to FF16 AA RW Figure 1.16.4. Serial I/O-related registers (1) 97 Mitsubishi microcomputers M16C / 30L Group Serial I/O SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER UARTi transmit/receive mode register b7 b6 b5 b4 b3 b2 b1 b0 Symbol UiMR(i=0,1) Address 03A016, 03A816 When reset 0016 Function (During clock synchronous serial I/O mode) Bit symbol Bit name SMD0 Serial I/O mode select bit Must always be “001” b2 b1 b0 0 0 0 : Serial I/O invalid 0 1 0 : Must not be set. 0 1 1 : Must not be set. 1 1 1 : Must not be set. SMD1 SMD2 Function (During UART mode) b2 b1 b0 R W A A AA A A AA A A A AA A AA A A AA 1 0 0 : Transfer data 7 bits long 1 0 1 : Transfer data 8 bits long 1 1 0 : Transfer data 9 bits long 0 0 0 : Serial I/O invalid 0 1 0 : Must not be set. 0 1 1 : Must not be set. 1 1 1 : Must not be set. CKDIR Internal/external clock select bit 0 : Internal clock 1 : External clock (Note) 0 : Internal clock 1 : External clock (Note) STPS Stop bit length select bit Invalid 0 : One stop bit 1 : Two stop bits PRY Odd/even parity select bit Invalid PRYE Parity enable bit Invalid 0 : Parity disabled 1 : Parity enabled SLEP Sleep select bit Must always be “0” 0 : Sleep mode deselected 1 : Sleep mode selected Valid when bit 6 = “1” 0 : Odd parity 1 : Even parity Note : Set the corresponding port direction register to “0”. UART2 transmit/receive mode register b7 b6 b5 b4 b3 b2 b1 Symbol U2MR b0 Address 037816 Bit symbol Bit name SMD0 Serial I/O mode select bit When reset 0016 Function (During clock synchronous serial I/O mode) Must always be “001” b2 b1 b0 0 0 0 : Serial I/O invalid 0 1 0 : (Note 1) 0 1 1 : Must not be set. 1 1 1 : Must not be set. SMD1 SMD2 b2 b1 b0 0 : Internal clock 1 : External clock (Note 2) Must always be “0” STPS Stop bit length select bit Invalid 0 : One stop bit 1 : Two stop bits PRY Odd/even parity select bit Invalid PRYE Parity enable bit Invalid 0 : Parity disabled 1 : Parity enabled IOPOL TxD, RxD I/O polarity reverse bit 0 : No reverse 1 : Reverse Usually set to “0” 0 : No reverse 1 : Reverse Usually set to “0” Figure 1.16.5. Serial I/O-related registers (2) R W A A A A A A A A AA A A A AA A AA AA 1 0 0 : Transfer data 7 bits long 1 0 1 : Transfer data 8 bits long 1 1 0 : Transfer data 9 bits long 0 0 0 : Serial I/O invalid 0 1 0 : Must not be set. 0 1 1 : Must not be set. 1 1 1 : Must not be set. CKDIR Internal/external clock select bit Note 1: Bit 2 to bit 0 are set to “0102” when I2C mode is used. Note 2: Set the corresponding port direction register to “0”. 98 Function (During UART mode) Valid when bit 6 = “1” 0 : Odd parity 1 : Even parity Mitsubishi microcomputers M16C / 30L Group Serial I/O SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER UARTi transmit/receive control register 0 b7 b6 b5 b4 b3 b2 b1 b0 Symbol UiC0(i=0,1) Bit symbol CLK0 Address When reset 03A416, 03AC16 0816 Function (During clock synchronous serial I/O mode) Bit name b1 b0 BRG count source select bit CLK1 CRS TXEPT CTS/RTS function select bit Function (During UART mode) b1 b0 R W AA AA AA A AA AAAA AA AA 0 0 : f1 is selected 0 1 : f8 is selected 1 0 : f32 is selected 1 1 : Must not be set. 0 0 : f1 is selected 0 1 : f8 is selected 1 0 : f32 is selected 1 1 : Must not be set. Valid when bit 4 = “0” Valid when bit 4 = “0” 0 : CTS function is selected (Note 1) 1 : RTS function is selected (Note 2) 0 : CTS function is selected (Note 1) 1 : RTS function is selected (Note 2) 0 : Data present in transmit 0 : Data present in transmit register Transmit register empty register (during transmission) (during transmission) flag 1 : No data present in transmit 1 : No data present in transmit register (transmission completed) register (transmission completed) CRD CTS/RTS disable bit 0 : CTS/RTS function enabled 1 : CTS/RTS function disabled (P60 and P64 function as programmable I/O port) 0 : CTS/RTS function enabled 1 : CTS/RTS function disabled (P60 and P64 function as programmable I/O port) NCH Data output select bit 0 : TXDi pin is CMOS output 1 : TXDi pin is N-channel open-drain output 0: TXDi pin is CMOS output 1: TXDi pin is N-channel open-drain output CKPOL CLK polarity select bit 0 : Transmit data is output at falling edge of transfer clock and receive data is input at rising edge 1 : Transmit data is output at rising edge of transfer clock and receive data is input at falling edge Must always be “0” UFORM Transfer format select bit 0 : LSB first 1 : MSB first Must always be “0” Note 1: Set the corresponding port direction register to “0”. Note 2: The settings of the corresponding port register and port direction register are invalid. UART2 transmit/receive control register 0 b7 b6 b5 b4 b3 b2 b1 b0 Symbol U2C0 Bit symbol CLK0 Address 037C16 Bit name BRG count source select bit CLK1 CRS TXEPT CTS/RTS function select bit When reset 0816 Function (During clock synchronous serial I/O mode) b1 b0 0 0 : f1 is selected 0 1 : f8 is selected 1 0 : f32 is selected 1 1 : Must not be set. Valid when bit 4 = “0” Valid when bit 4 = “0” 0 : CTS function is selected (Note 1) 1 : RTS function is selected (Note 2) 0 : CTS function is selected (Note 1) 1 : RTS function is selected (Note 2) R W 0 : Data present in transmit 0 : Data present in transmit register Transmit register empty register (during transmission) (during transmission) flag 1 : No data present in transmit 1 : No data present in transmit CTS/RTS disable bit Nothing is assigned. register (transmission completed) 0 : CTS/RTS function enabled 1 : CTS/RTS function disabled (P73 functions programmable I/O port) 0 : CTS/RTS function enabled 1 : CTS/RTS function disabled (P73 functions programmable I/O port) 0 : TXDi pin is CMOS output 0: TXDi pin is CMOS output : TXDi pinvalue, is N-channel 1: TXDi is N-channel In an attempt to write to this bit, write1“0”. The if read, turns out to bepin“0”. CKPOL AA AAAA AA AA AAAA AAAA AAAA b1 b0 0 0 : f1 is selected 0 1 : f8 is selected 1 0 : f32 is selected 1 1 : Must not be set. register (transmission completed) CRD Function (During UART mode) CLK polarity select bit open-drain output 0 : Transmit data is output at falling edge of transfer clock and receive data is input at rising edge 1 : Transmit data is output at rising edge of transfer clock and receive data is input at falling edge UFORM Transfer format select bit 0 : LSB first 1 : MSB first (Note 3) open-drain output Must always be “0” 0 : LSB first 1 : MSB first Note 1: Set the corresponding port direction register to “0”. Note 2: The settings of the corresponding port register and port direction register are invalid. Note 3: Only clock synchronous serial I/O mode and 8-bit UART mode are valid. Figure 1.16.6. Serial I/O-related registers (3) 99 Mitsubishi microcomputers M16C / 30L Group Serial I/O SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER UARTi transmit/receive control register 1 b7 b6 b5 b4 b3 b2 b1 Symbol UiC1(i=0,1) b0 Bit symbol Address 03A516,03AD16 When reset 0216 Function (During clock synchronous serial I/O mode) Bit name Function (During UART mode) TE Transmit enable bit 0 : Transmission disabled 1 : Transmission enabled 0 : Transmission disabled 1 : Transmission enabled TI Transmit buffer empty flag 0 : Data present in transmit buffer register 1 : No data present in transmit buffer register 0 : Data present in transmit buffer register 1 : No data present in transmit buffer register RE Receive enable bit 0 : Reception disabled 1 : Reception enabled 0 : Reception disabled 1 : Reception enabled RI Receive complete flag 0 : No data present in receive buffer register 1 : Data present in receive buffer register 0 : No data present in receive buffer register 1 : Data present in receive buffer register R W A A A A A Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be “0”. UART2 transmit/receive control register 1 b7 b6 b5 b4 b3 b2 b1 Symbol U2C1 b0 Bit symbol Address 037D16 Bit name Function (During clock synchronous serial I/O mode) Function (During UART mode) TE Transmit enable bit 0 : Transmission disabled 1 : Transmission enabled 0 : Transmission disabled 1 : Transmission enabled TI Transmit buffer empty flag 0 : Data present in transmit buffer register 1 : No data present in transmit buffer register 0 : Data present in transmit buffer register 1 : No data present in transmit buffer register RE Receive enable bit 0 : Reception disabled 1 : Reception enabled 0 : Reception disabled 1 : Reception enabled RI Receive complete flag 0 : No data present in receive buffer register 1 : Data present in receive buffer register 0 : No data present in receive buffer register 1 : Data present in receive buffer register 0 : Transmit buffer empty (TI = 1) 1 : Transmit is completed (TXEPT = 1) 0 : Transmit buffer empty (TI = 1) 1 : Transmit is completed (TXEPT = 1) U2RRM UART2 continuous receive mode enable bit 0 : Continuous receive mode disabled 1 : Continuous receive mode enabled Must always be "0" U2LCH Data logic select bit 0 : No reverse 1 : Reverse 0 : No reverse 1 : Reverse U2ERE Error signal output enable bit Must always be "0" 0 : Output disabled 1 : Output enabled U2IRS UART2 transmit interrupt cause select bit Figure 1.16.7. Serial I/O-related registers (4) 100 When reset 0216 A A A A A A A A A A A R W Mitsubishi microcomputers M16C / 30L Group Serial I/O SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER UART transmit/receive control register 2 b7 b6 b5 b4 b3 b2 b1 b0 Symbol UCON 0 Bit symbol Address 03B016 Function (During clock synchronous serial I/O mode) Bit name UART0 transmit interrupt cause select bit U0IRS When reset X00000002 0 : Transmit buffer empty (Tl = 1) 1 : Transmission completed (TXEPT = 1) U1IRS UART1 transmit interrupt cause select bit 0 : Transmit buffer empty (Tl = 1) 1 : Transmission completed (TXEPT = 1) Function (During UART mode) 0 : Transmit buffer empty (Tl = 1) 1 : Transmission completed (TXEPT = 1) 0 : Transmit buffer empty (Tl = 1) 1 : Transmission completed (TXEPT = 1) U0RRM UART0 continuous receive mode enable bit 0 : Continuous receive mode disabled 1 : Continuous receive mode enable Must always be “0” U1RRM UART1 continuous receive mode enable bit 0 : Continuous receive mode disabled 1 : Continuous receive mode enabled Valid when bit 5 = “1” 0 : Clock output to CLK1 1 : Clock output to CLKS1 Must always be “0” CLKMD0 CLK/CLKS select bit 0 0 : Normal mode CLKMD1 CLK/CLKS select bit 1 (Note) Invalid Must always be “0” (CLK output is CLK1 only) 1 : Transfer clock output from multiple pins function selected Reserved bit AAA A AA AA AAA A AAA AAA AAA AA AAA R W Must always be set to “0” Nothing is assigned. In an attempt to write to this bit, write “0”. The value, if read, turns out to be indeterminate. Note: When using multiple pins to output the transfer clock, the following requirements must be met: • UART1 internal/external clock select bit (bit 3 at address 03A816) = “0”. UART2 special mode register b7 b6 b5 b4 b3 b2 b1 b0 Symbol U2SMR Bit symbol Address 037716 When reset 8016 Function (During clock synchronous serial I/O mode) Bit name Function (During UART mode) AAAA AA AA AA AA AA AA AAAA IICM I2C mode select bit 0 : Normal mode 1 : I2C mode Must always be “0” ABC Arbitration lost detecting flag control bit 0 : Update per bit 1 : Update per byte Must always be “0” BBS Bus busy flag 0 : STOP condition detected 1 : START condition detected Must always be “0” SCLL sync output enable bit 0 : Disabled 1 : Enabled Must always be “0” ABSCS Bus collision detect sampling clock select bit Must always be “0” 0 : Rising edge of transfer clock 1 : Underflow signal of timer A0 ACSE Auto clear function select bit of transmit enable bit Must always be “0” 0 : No auto clear function 1 : Auto clear at occurrence of bus collision SSS Transmit start condition select bit Must always be “0” 0 : Ordinary 1 : Falling edge of RXD2 SDDS SDA digital delay select bit (Note 2) LSYN R W (Note1) 0 : Must always be “0” Must always be “0” when not using I2C mode 1 : Digital delay output is selected Note 1: Nothing but “0” may be written. Note 2: When not in I2C mode, do not set this bit by writing a “1”. During normal mode, fix it to “0”. When this bit = “0”, UART2 special mode register 3 (U2SMR3 at address 037516) bits 7 to 5 (DL2 to DL0 = SDA digital delay setup bits) are initialized to “000”. Also, when SDDS = “0”, the U2SMR3 register cannot be read or written to. Figure 1.16.8. Serial I/O-related registers (5) 101 Mitsubishi microcomputers M16C / 30L Group Serial I/O SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER UART2 special mode register 2 (I 2 C bus exclusive use register) b7 b6 b5 b4 b3 b2 b1 b0 Symbol U2SMR2 Bit symbol Address 037616 When reset 0016 Function (I2C bus exclusive use) Bit name IICM2 I 2C mode select bit 2 Refer to Table 1.16.11 CSC Clock-synchronous bit 0 : Disabled 1 : Enabled SWC SCL wait output bit 0 : Disabled 1 : Enabled ALS SDA output stop bit 0 : Disabled 1 : Enabled STAC UART2 initialization bit 0 : Disabled 1 : Enabled SWC2 SCL wait output bit 2 0: UART2 clock 1: 0 output SDHI SDA output disable bit 0: Enabled 1: Disabled (high impedance) SHTC Start/stop condition control bit 1: Set this bit to “1” in I2C mode (refer to Table 1.16.12) A A A AA A AA AA A A A A AA A A AA R W UART2 special mode register 3 (I 2 C bus exclusive use register) b7 b6 b5 b4 b3 b2 b1 b0 Symbol U2SMR3 Bit symbol Address 037516 When reset 0016 Function (I 2 C bus exclusive use register) Bit name Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be indeterminate. However, when SDDS = “1”, the value “0” is read out (Note 1) DL0 SDA digital delay setup bit (Note 1, Note 2, Note 3) DL1 DL2 b7 b6 b5 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 : Must not be set when using I2C mode 1 : 1 to 2 cycle(s) of 1/f(XIN) 0 : 2 to 3 cycles of 1/f(XIN) 1 : 3 to 4 cycles of 1/f(XIN) Digital delay 0 : 4 to 5 cycles of 1/f(XIN) is selected 1 : 5 to 6 cycles of 1/f(XIN) 0 : 6 to 7 cycles of 1/f(XIN) 1 : 7 to 8 cycles of 1/f(XIN) R W A A A AA A AA AA Note 1: This bit can be read or written to when UART2 special mode register (U2SMR at address 037716) bit 7 (SDDS: SDA digital delay select bit) = “1”. When the initial value of UART2 special mode register 3 (U2SMR3) is read after setting SDDS = “1”, the value is “0016”. When writing to UART2 special mode register 3 (U2SMR3) after setting SDDS = “1”, be sure to write 0's to bits 0–4. When SDDS = “0”, this register cannot be written to; when read, the value is indeterminate. Note 2: These bits are initialized to “000” when SDDS = “0”. After a reset, these bits are set to “000”. However, because these bits can be read only when SDDS = “1”, the value read from these bits when SDDS = “0” is indeterminate. Note 3: The amount of delay varies with the load on SCL and SDA pins. Also, when using an external clock, the amount of delay increases by about 200 ns, so be sure to take this into account when using the device. Figure 1.16.9. Serial I/O-related registers (6) 102 Mitsubishi microcomputers M16C / 30L Group Clock synchronous serial I/O mode SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER (1) Clock synchronous serial I/O mode The clock synchronous serial I/O mode uses a transfer clock to transmit and receive data. Tables 1.16.2 and 1.16.3 list the specifications of the clock synchronous serial I/O mode. Figure 1.16.10 shows the UARTi transmit/receive mode register. Table 1.16.2. Specifications of clock synchronous serial I/O mode (1) Item Transfer data format Transfer clock Specification • Transfer data length: 8 bits • When internal clock is selected (bit 3 at addresses 03A016, 03A816, 037816 = “0”) : fi/ 2(n+1) (Note 1) fi = f1, f8, f32 • When external clock is selected (bit 3 at addresses 03A016, 03A816, 037816 = “1”) : Input from CLKi pin _______ _______ _______ _______ Transmission/reception control • CTS function, RTS function, CTS and RTS function invalid: selectable Transmission start condition • To start transmission, the following requirements must be met: _ Transmit enable bit (bit 0 at addresses 03A516, 03AD16, 037D16) = “1” _ Transmit buffer empty flag (bit 1 at addresses 03A516, 03AD16, 037D16) = “0” _______ _______ _ When CTS function selected, CTS input level = “L” • Furthermore, if external clock is selected, the following requirements must also be met: _ CLKi polarity select bit (bit 6 at addresses 03A416, 03AC16, 037C16) = “0”: CLKi input level = “H” _ CLKi polarity select bit (bit 6 at addresses 03A416, 03AC16, 037C16) = “1”: CLKi input level = “L” Reception start condition • To start reception, the following requirements must be met: _ Receive enable bit (bit 2 at addresses 03A516, 03AD16, 037D16) = “1” _ Transmit enable bit (bit 0 at addresses 03A516, 03AD16, 037D16) = “1” _ Transmit buffer empty flag (bit 1 at addresses 03A516, 03AD16, 037D16) = “0” • Furthermore, if external clock is selected, the following requirements must also be met: _ CLKi polarity select bit (bit 6 at addresses 03A416, 03AC16, 037C16) = “0”: CLKi input level = “H” _ CLKi polarity select bit (bit 6 at addresses 03A416, 03AC16, 037C16) = “1”: CLKi input level = “L” • When transmitting Interrupt request _ Transmit interrupt cause select bit (bits 0, 1 at address 03B016, bit 4 at generation timing address 037D16) = “0”: Interrupts requested when data transfer from UARTi transfer buffer register to UARTi transmit register is completed _ Transmit interrupt cause select bit (bits 0, 1 at address 03B016, bit 4 at address 037D16) = “1”: Interrupts requested when data transmission from UARTi transfer register is completed • When receiving _ Interrupts requested when data transfer from UARTi receive register to UARTi receive buffer register is completed Error detection • Overrun error (Note 2) This error occurs when the next data is ready before contents of UARTi receive buffer register are read out Note 1: “n” denotes the value 0016 to FF16 that is set to the UART bit rate generator. Note 2: If an overrun error occurs, the UARTi receive buffer will have the next data written in. Note also that the UARTi receive interrupt request bit does not change. 103 Mitsubishi microcomputers M16C / 30L Group Clock synchronous serial I/O mode SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Table 1.16.3. Specifications of clock synchronous serial I/O mode (2) Item Select function Specification • CLK polarity selection Whether transmit data is output/input timing at the rising edge or falling edge of the transfer clock can be selected • LSB first/MSB first selection Whether transmission/reception begins with bit 0 or bit 7 can be selected • Continuous receive mode selection Reception is enabled simultaneously by a read from the receive buffer register • Transfer clock output from multiple pins selection (UART1) UART1 transfer clock can be chosen by software to be output from one of the two pins set • Switching serial data logic (UART2) Whether to reverse data in writing to the transmission buffer register or reading the reception buffer register can be selected. • TxD, RxD I/O polarity reverse (UART2) This function is reversing TxD port output and RxD port input. All I/O data level is reversed. 104 Mitsubishi microcomputers M16C / 30L Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Clock synchronous serial I/O mode UARTi transmit/receive mode registers b7 b6 b5 b4 b3 0 b2 b1 b0 0 0 1 Symbol UiMR(i=0,1) Bit symbol SMD0 Address 03A016, 03A816 When reset 0016 Bit name Serial I/O mode select bit SMD1 SMD2 CKDIR Internal/external clock select bit Function b2 b1 b0 0 0 1 : Clock synchronous serial I/O mode 0 : Internal clock 1 : External clock (Note) STPS PRY Invalid in clock synchronous serial I/O mode PRYE SLEP 0 (Must always be “0” in clock synchronous serial I/O mode) Note : Set the corresponding port direction register to “0”. A AA A AAA A A AA A A AA A AAA A RW UART2 transmit/receive mode register b7 0 b6 b5 b4 b3 b2 b1 b0 0 0 1 Symbol U2MR Bit symbol SMD0 Address 037816 Bit name Serial I/O mode select bit SMD1 SMD2 CKDIR When reset 0016 Internal/external clock select bit Function b2 b1 b0 0 0 1 : Clock synchronous serial I/O mode 0 : Internal clock 1 : External clock (Note 2) STPS PRY Invalid in clock synchronous serial I/O mode PRYE IOPOL TxD, RxD I/O polarity reverse bit (Note 1) 0 : No reverse 1 : Reverse Note 1: Usually set to “0”. Note 2: Set the corresponding port direction register to “0”. AA A A AA A A A A A A A AA A A AA RW Figure 1.16.10. UARTi transmit/receive mode register in clock synchronous serial I/O mode 105 Mitsubishi microcomputers M16C / 30L Group Clock synchronous serial I/O mode SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Table 1.16.4 lists the functions of the input/output pins during clock synchronous serial I/O mode. This table shows the pin functions when the transfer clock output from multiple pins function is not selected. Note that for a period from when the UARTi operation mode is selected to when transfer starts, the TxDi pin outputs an “H”. (If the N-channel open-drain is selected, this pin is in floating state.) Table 1.16.4. Input/output pin functions in clock synchronous serial I/O mode (when transfer clock output from multiple pins is not selected) Pin name Function Method of selection TxDi Serial data output (P63, P67, P70) (Outputs dummy data when performing reception only) Serial data input RxDi (P62, P66, P71) Port P62, P66 and P71 direction register (bits 2 and 6 at address 03EE16, bit 1 at address 03EF16)= “0” (Can be used as an input port when performing transmission only) CLKi Transfer clock output (P61, P65, P72) Transfer clock input Internal/external clock select bit (bit 3 at address 03A016, 03A816, 037816) = “0” CTSi/RTSi CTS input (P60, P64, P73) CTS/RTS disable bit (bit 4 at address 03A416, 03AC16, 037C16) =“0” CTS/RTS function select bit (bit 2 at address 03A416, 03AC16, 037C16) = “0” Port P60, P64 and P73 direction register (bits 0 and 4 at address 03EE16, bit 3 at address 03EF16) = “0” 106 Internal/external clock select bit (bit 3 at address 03A016, 03A816, 037816) = “1” Port P61, P65 and P72 direction register (bits 1 and 5 at address 03EE16, bit 2 at address 03EF16) = “0” RTS output CTS/RTS disable bit (bit 4 at address 03A416, 03AC16, 037C16) = “0” CTS/RTS function select bit (bit 2 at address 03A416, 03AC16, 037C16) = “1” Programmable I/O port CTS/RTS disable bit (bit 4 at address 03A416, 03AC16, 037C16) = “1” Mitsubishi microcomputers M16C / 30L Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Clock synchronous serial I/O mode • Example of transmit timing (when internal clock is selected) Tc Transfer clock Transmit enable bit (TE) Transmit buffer empty flag (Tl) “1” “0” Data is set in UARTi transmit buffer register “1” “0” Transferred from UARTi transmit buffer register to UARTi transmit register “H” CTSi TCLK “L” Stopped pulsing because CTS = “H” Stopped pulsing because transfer enable bit = “0” CLKi TxDi D0 D 1 D2 D3 D4 D5 D6 D7 Transmit register empty flag (TXEPT) D0 D 1 D2 D3 D4 D5 D 6 D7 D 0 D1 D2 D 3 D 4 D 5 D6 D7 “1” “0” Transmit interrupt “1” request bit (IR) “0” Cleared to “0” when interrupt request is accepted, or cleared by software Shown in ( ) are bit symbols. The above timing applies to the following settings: • Internal clock is selected. • CTS function is selected. • CLK polarity select bit = “0”. • Transmit interrupt cause select bit = “0”. Tc = TCLK = 2(n + 1) / fi fi: frequency of BRGi count source (f1, f8, f32) n: value set to BRGi • Example of receive timing (when external clock is selected) “1” Receive enable bit (RE) “0” Transmit enable bit (TE) “0” Transmit buffer empty flag (Tl) “1” “0” “H” RTSi Dummy data is set in UARTi transmit buffer register “1” Transferred from UARTi transmit buffer register to UARTi transmit register “L” 1 / fEXT CLKi Receive data is taken in D 0 D1 D 2 D3 D 4 D5 D6 D 7 RxDi Receive complete “1” flag (Rl) “0” Receive interrupt request bit (IR) Transferred from UARTi receive register to UARTi receive buffer register D0 D 1 D 2 D3 D4 D5 Read out from UARTi receive buffer register “1” “0” Cleared to “0” when interrupt request is accepted, or cleared by software Shown in ( ) are bit symbols. The above timing applies to the following settings: • External clock is selected. • RTS function is selected. • CLK polarity select bit = “0”. Meet the following conditions are met when the CLK input before data reception = “H” • Transmit enable bit “1” • Receive enable bit “1” • Dummy data write to UARTi transmit buffer register fEXT: frequency of external clock Figure 1.16.11. Typical transmit/receive timings in clock synchronous serial I/O mode 107 Mitsubishi microcomputers M16C / 30L Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Clock synchronous serial I/O mode (a) Polarity select function As shown in Figure 1.16.12, the CLK polarity select bit (bit 6 at addresses 03A416, 03AC16, 037C16) allows selection of the polarity of the transfer clock. • When CLK polarity select bit = “0” CLKi TXDi D0 D1 D2 D3 D4 D5 D6 D7 RXDi D0 D1 D2 D3 D4 D5 D6 D7 Note 1: The CLKi pin level when not transferring data is “H”. • When CLK polarity select bit = “1” CLKi TXDi D0 D1 D2 D3 D4 D5 D6 D7 RXDi D0 D1 D2 D3 D4 D5 D6 D7 Note 2: The CLKi pin level when not transferring data is “L”. Figure 1.16.12. Polarity of transfer clock (b) LSB first/MSB first select function As shown in Figure 1.16.13, when the transfer format select bit (bit 7 at addresses 03A416, 03AC16, 037C16) = “0”, the transfer format is “LSB first”; when the bit = “1”, the transfer format is “MSB first”. • When transfer format select bit = “0” CLKi TXDi D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 LSB first R XD i • When transfer format select bit = “1” CLKi TXDi D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 MSB first R XD i Note: This applies when the CLK polarity select bit = “0”. Figure 1.16.13. Transfer format 108 Mitsubishi microcomputers M16C / 30L Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Clock synchronous serial I/O mode (c) Transfer clock output from multiple pins function (UART1) This function allows the setting two transfer clock output pins and choosing one of the two to output a clock by using the CLK and CLKS select bit (bits 4 and 5 at address 03B016). (See Figure 1.16.14.) The multiple pins function is valid only when the internal clock is selected for UART1. Microcomputer TXD1 (P67) CLKS1 (P64) CLK1 (P65) IN IN CLK CLK Note: This applies when the internal clock is selected and transmission is performed only in clock synchronous serial I/O mode. Figure 1.16.14. The transfer clock output from the multiple pins function usage (d) Continuous receive mode If the continuous receive mode enable bit (bits 2 and 3 at address 03B016, bit 5 at address 037D16) is set to “1”, the unit is placed in continuous receive mode. In this mode, when the receive buffer register is read out, the unit simultaneously goes to a receive enable state without having to set dummy data to the transmit buffer register back again. (e) Serial data logic switch function (UART2) When the data logic select bit (bit6 at address 037D16) = “1”, and writing to transmit buffer register or reading from receive buffer register, data is reversed. Figure 1.16.15 shows the example of serial data logic switch timing. •When LSB first Transfer clock “H” “L” TxD2 “H” (no reverse) “L” TxD2 “H” (reverse) “L” D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 Figure 1.16.15. Serial data logic switch timing 109 Mitsubishi microcomputers M16C / 30L Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Clock asynchronous serial I/O (UART) mode (2) Clock asynchronous serial I/O (UART) mode The UART mode allows transmitting and receiving data after setting the desired transfer rate and transfer data format. Tables 1.16.5 and 1.16.6 list the specifications of the UART mode. Figure 1.16.16 shows the UARTi transmit/receive mode register. Table 1.16.5. Specifications of UART Mode (1) Item Transfer data format Transfer clock Specification • Character bit (transfer data): 7 bits, 8 bits, or 9 bits as selected • Start bit: 1 bit • Parity bit: Odd, even, or nothing as selected • Stop bit: 1 bit or 2 bits as selected • When internal clock is selected (bit 3 at addresses 03A016, 03A816, 037816 = “0”) : fi/16(n+1) (Note 1) fi = f1, f8, f32 • When external clock is selected (bit 3 at addresses 03A016, 03A816 =“1”) : fEXT/16(n+1) (Note 1) (Note 2) (Do not set external clock for UART2) _______ _______ _______ _______ Transmission/reception control • CTS function, RTS function, CTS and RTS function invalid: selectable Transmission start condition • To start transmission, the following requirements must be met: - Transmit enable bit (bit 0 at addresses 03A516, 03AD16, 037D16) = “1” - Transmit buffer empty flag (bit 1 at addresses 03A516, 03AD16, 037D16) = “0” _______ _______ - When CTS function selected, CTS input level = “L” Reception start condition • To start reception, the following requirements must be met: - Receive enable bit (bit 2 at addresses 03A516, 03AD16, 037D16) = “1” - Start bit detection Interrupt request • When transmitting generation timing - Transmit interrupt cause select bits (bits 0,1 at address 03B016, bit4 at address 037D16) = “0”: Interrupts requested when data transfer from UARTi transfer buffer register to UARTi transmit register is completed - Transmit interrupt cause select bits (bits 0, 1 at address 03B016, bit4 at address 037D16) = “1”: Interrupts requested when data transmission from UARTi transfer register is completed • When receiving - Interrupts requested when data transfer from UARTi receive register to UARTi receive buffer register is completed Error detection • Overrun error (Note 3) This error occurs when the next data is ready before contents of UARTi receive buffer register are read out • Framing error This error occurs when the number of stop bits set is not detected • Parity error This error occurs when if parity is enabled, the number of 1’s in parity and character bits does not match the number of 1’s set • Error sum flag This flag is set (= 1) when any of the overrun, framing, and parity errors is encountered Note 1: ‘n’ denotes the value 0016 to FF16 that is set to the UARTi bit rate generator. Note 2: fEXT is input from the CLKi pin. Note 3: If an overrun error occurs, the UARTi receive buffer will have the next data written in. Note also that the UARTi receive interrupt request bit does not change. 110 Mitsubishi microcomputers M16C / 30L Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Clock asynchronous serial I/O (UART) mode Table 1.16.6. Specifications of UART Mode (2) Item Select function Specification • Sleep mode selection (UART0, UART1) This mode is used to transfer data to and from one of multiple slave microcomputers • Serial data logic switch (UART2) This function is reversing logic value of transferring data. Start bit, parity bit and stop bit are not reversed. • TXD, RXD I/O polarity switch (UART2) This function is reversing TXD port output and RXD port input. All I/O data level is reversed. 111 Mitsubishi microcomputers M16C / 30L Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Clock asynchronous serial I/O (UART) mode UARTi transmit / receive mode registers b7 b6 b5 b4 b3 b2 b1 b0 Symbol UiMR(i=0,1) Bit symbol SMD0 Address 03A016, 03A816 Bit name Serial I/O mode select bit SMD1 SMD2 CKDIR When reset 0016 Function b2 b1 b0 1 0 0 : Transfer data 7 bits long 1 0 1 : Transfer data 8 bits long 1 1 0 : Transfer data 9 bits long Internal / external clock select bit Stop bit length select bit 0 : Internal clock 1 : External clock (Note) 0 : One stop bit 1 : Two stop bits PRY Odd / even parity select bit Valid when bit 6 = “1” 0 : Odd parity 1 : Even parity PRYE Parity enable bit 0 : Parity disabled 1 : Parity enabled SLEP Sleep select bit 0 : Sleep mode deselected 1 : Sleep mode selected STPS A A AA A A AA A A A A AA AA AA RW Note : Set the corresponding port direction register to “0”. UART2 transmit / receive mode register b7 b6 b5 b4 b3 b2 b1 b0 Symbol U2MR Address 037816 Bit symbol SMD0 Bit name Serial I/O mode select bit SMD1 SMD2 CKDIR STPS When reset 0016 Internal / external clock select bit Stop bit length select bit Function b2 b1 b0 Must always be “0” 0 : One stop bit 1 : Two stop bits PRY Odd / even parity select bit Valid when bit 6 = “1” 0 : Odd parity 1 : Even parity PRYE Parity enable bit 0 : Parity disabled 1 : Parity enabled IOPOL TxD, RxD I/O polarity reverse bit (Note) 0 : No reverse 1 : Reverse Note: Usually set to “0”. Figure 1.16.16. UARTi transmit/receive mode register in UART mode 112 A A AA A AA A AA AA AA AA AA 1 0 0 : Transfer data 7 bits long 1 0 1 : Transfer data 8 bits long 1 1 0 : Transfer data 9 bits long RW Mitsubishi microcomputers M16C / 30L Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Clock asynchronous serial I/O (UART) mode Table 1.16.7 lists the functions of the input/output pins during UART mode. Note that for a period from when the UARTi operation mode is selected to when transfer starts, the TxDi pin outputs an “H”. (If the Nchannel open-drain is selected, this pin is in floating state.) Table 1.16.7. Input/output pin functions in UART mode Pin name Function TxDi Serial data output (P63, P67, P70) Method of selection RxDi Serial data input (P62, P66, P71) Port P62, P66 and P71 direction register (bits 2 and 6 at address 03EE16, bit 1 at address 03EF16)= “0” (Can be used as an input port when performing transmission only) CLKi Programmable I/O port (P61, P65, P72) Transfer clock input Internal/external clock select bit (bit 3 at address 03A016, 03A816, 037816) = “0” CTSi/RTSi CTS input (P60, P64, P73) CTS/RTS disable bit (bit 4 at address 03A416, 03AC16, 037C16) =“0” CTS/RTS function select bit (bit 2 at address 03A416, 03AC16, 037C16) = “0” Port P60, P64 and P73 direction register (bits 0 and 4 at address 03EE16, bit 3 at address 03EF16) = “0” Internal/external clock select bit (bit 3 at address 03A016, 03A816) = “1” Port P61, P65 direction register (bits 1 and 5 at address 03EE16) = “0” (Do not set external clock for UART2) RTS output CTS/RTS disable bit (bit 4 at address 03A416, 03AC16, 037C16) = “0” CTS/RTS function select bit (bit 2 at address 03A416, 03AC16, 037C16) = “1” Programmable I/O port CTS/RTS disable bit (bit 4 at address 03A416, 03AC16, 037C16) = “1” 113 Mitsubishi microcomputers M16C / 30L Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Clock asynchronous serial I/O (UART) mode • Example of transmit timing when transfer data is 8 bits long (parity enabled, one stop bit) The transfer clock stops momentarily as CTS is “H” when the stop bit is checked. The transfer clock starts as the transfer starts immediately CTS changes to “L”. Tc Transfer clock Transmit enable bit(TE) “1” Transmit buffer empty flag(TI) “1” “0” Data is set in UARTi transmit buffer register. “0” Transferred from UARTi transmit buffer register to UARTi transmit register “H” CTSi “L” Start bit TxDi Parity bit ST D0 D1 D2 D3 D4 D5 D6 D7 P Stopped pulsing because transmit enable bit = “0” Stop bit SP ST D0 D1 D2 D3 D4 D5 D6 D7 P ST D0 D1 SP “1” Transmit register empty flag (TXEPT) “0” Transmit interrupt request bit (IR) “1” “0” Cleared to “0” when interrupt request is accepted, or cleared by software Shown in ( ) are bit symbols. The above timing applies to the following settings : • Parity is enabled. • One stop bit. • CTS function is selected. • Transmit interrupt cause select bit = “1”. Tc = 16 (n + 1) / fi or 16 (n + 1) / fEXT fi : frequency of BRGi count source (f1, f8, f32) fEXT : frequency of BRGi count source (external clock) n : value set to BRGi • Example of transmit timing when transfer data is 9 bits long (parity disabled, two stop bits) Tc Transfer clock Transmit enable bit(TE) “1” Transmit buffer empty flag(TI) “1” “0” Data is set in UARTi transmit buffer register “0” Transferred from UARTi transmit buffer register to UARTi transmit register Start bit TxDi Stop bit ST D0 D1 D2 D3 D4 D5 D6 D7 D8 SP SP Stop bit ST D0 D1 D2 D3 D4 D5 D6 D7 D8 SPSP ST D0 D1 “1” Transmit register empty flag (TXEPT) “0” Transmit interrupt request bit (IR) “1” “0” Cleared to “0” when interrupt request is accepted, or cleared by software Shown in ( ) are bit symbols. The above timing applies to the following settings : • Parity is disabled. • Two stop bits. • CTS function is disabled. • Transmit interrupt cause select bit = “0”. Tc = 16 (n + 1) / fi or 16 (n + 1) / fEXT fi : frequency of BRGi count source (f1, f8, f32) fEXT : frequency of BRGi count source (external clock) n : value set to BRGi Figure 1.16.17. Typical transmit timings in UART mode(UART0,UART1) 114 Mitsubishi microcomputers M16C / 30L Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Clock asynchronous serial I/O (UART) mode • Example of transmit timing when transfer data is 8 bits long (parity enabled, one stop bit) Tc Transfer clock Transmit enable bit(TE) “1” Transmit buffer empty flag(TI) “1” Data is set in UART2 transmit buffer register “0” Note “0” Transferred from UART2 transmit buffer register to UARTi transmit register Parity bit Start bit TxD2 ST D0 D1 D 2 D 3 D4 D 5 D 6 D 7 P Stop bit SP ST D0 D1 D2 D3 D4 D5 D6 D7 P SP “1” Transmit register empty flag (TXEPT) “0” Transmit interrupt request bit (IR) “1” “0” Cleared to “0” when interrupt request is accepted, or cleared by software Shown in ( ) are bit symbols. The above timing applies to the following settings : • Parity is enabled. • One stop bit. • Transmit interrupt cause select bit = “1”. Tc = 16 (n + 1) / fi fi : frequency of BRG2 count source (f1, f8, f32) n : value set to BRG2 Note: The transmit is started with overflow timing of BRG after having written in a value at the transmit buffer in the above timing. Figure 1.16.18. Typical transmit timings in UART mode(UART2) 115 Mitsubishi microcomputers M16C / 30L Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Clock asynchronous serial I/O (UART) mode • Example of receive timing when transfer data is 8 bits long (parity disabled, one stop bit) BRGi count source Receive enable bit “1” “0” Stop bit Start bit RxDi D1 D0 D7 Sampled “L” Receive data taken in Transfer clock Reception triggered when transfer clock “1” is generated by falling edge of start bit Receive complete flag Transferred from UARTi receive register to UARTi receive buffer register “0” “H” “L” RTSi Receive interrupt request bit “1” “0” Cleared to “0” when interrupt request is accepted, or cleared by software The above timing applies to the following settings : •Parity is disabled. •One stop bit. •RTS function is selected. Figure 1.16.19. Typical receive timing in UART mode (a) Sleep mode (UART0, UART1) This mode is used to transfer data between specific microcomputers among multiple microcomputers connected using UARTi. The sleep mode is selected when the sleep select bit (bit 7 at addresses 03A016, 03A816) is set to “1” during reception. In this mode, the unit performs receive operation when the MSB of the received data = “1” and does not perform receive operation when the MSB = “0”. (b) Function for switching serial data logic (UART2) When the data logic select bit (bit 6 of address 037D16) is assigned “1”, data is inverted in writing to the transmission buffer register or reading the reception buffer register. Figure 1.16.20 shows the example of timing for switching serial data logic. • When LSB first, parity enabled, one stop bit Transfer clock “H” “L” TxD2 “H” (no reverse) “L” TxD2 “H” (reverse) “L” ST D0 D1 D2 D3 D4 D5 D6 D7 P SP ST D0 D1 D2 D3 D4 D5 D6 D7 P SP ST : Start bit P : Even parity SP : Stop bit Figure 1.16.20. Timing for switching serial data logic 116 Mitsubishi microcomputers M16C / 30L Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Clock asynchronous serial I/O (UART) mode (c) TxD, RxD I/O polarity reverse function (UART2) This function is to reverse TXD pin output and RXD pin input. The level of any data to be input or output (including the start bit, stop bit(s), and parity bit) is reversed. Set this function to “0” (not to reverse) for usual use. (d) Bus collision detection function (UART2) This function is to sample the output level of the TXD pin and the input level of the RXD pin at the rising edge of the transfer clock; if their values are different, then an interrupt request occurs. Figure 1.16.21 shows the example of detection timing of a bus collision (in UART mode). Transfer clock “H” “L” TxD2 “H” ST SP ST SP “L” RxD2 “H” “L” Bus collision detection interrupt request signal “1” Bus collision detection interrupt request bit “1” “0” “0” ST : Start bit SP : Stop bit Figure 1.16.21. Detection timing of a bus collision (in UART mode) 117 Mitsubishi microcomputers M16C / 30L Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Clock asynchronous serial I/O (UART) mode (3) Clock-asynchronous serial I/O mode (used for the SIM interface) The SIM interface is used for connecting the microcomputer with a memory card or the like; adding some extra settings in UART2 clock-asynchronous serial I/O mode allows the user to effect this function. Table 1.16.8 shows the specifications of clock-asynchronous serial I/O mode (used for the SIM interface). Table 1.16.8. Specifications of clock-asynchronous serial I/O mode (used for the SIM interface) Item Transfer data format Transfer clock Specification • Transfer data 8-bit UART mode (bit 2 through bit 0 of address 037816 = “1012”) • One stop bit (bit 4 of address 037816 = “0”) • With the direct format chosen Set parity to “even” (bit 5 and bit 6 of address 037816 = “1” and “1” respectively) Set data logic to “direct” (bit 6 of address 037D16 = “0”). Set transfer format to LSB (bit 7 of address 037C16 = “0”). • With the inverse format chosen Set parity to “odd” (bit 5 and bit 6 of address 037816 = “0” and “1” respectively) Set data logic to “inverse” (bit 6 of address 037D16 = “1”) Set transfer format to MSB (bit 7 of address 037C16 = “1”) • With the internal clock chosen (bit 3 of address 037816 = “0”) : fi / 16 (n + 1) (Note 1) : fi=f1, f8, f32 (Do not set external clock) _______ _______ Transmission / reception control • Disable the CTS and RTS function (bit 4 of address 037C16 = “1”) Other settings • The sleep mode select function is not available for UART2 • Set transmission interrupt factor to “transmission completed” (bit 4 of address 037D16 = “1”) Transmission start condition • To start transmission, the following requirements must be met: - Transmit enable bit (bit 0 of address 037D16) = “1” - Transmit buffer empty flag (bit 1 of address 037D16) = “0” Reception start condition • To start reception, the following requirements must be met: - Reception enable bit (bit 2 of address 037D16) = “1” - Detection of a start bit Interrupt request • When transmitting generation timing When data transmission from the UART2 transmit register is completed (bit 4 of address 037D16 = “1”) • When receiving When data transfer from the UART2 receive register to the UART2 receive buffer register is completed Error detection • Overrun error (see the specifications of clock-asynchronous serial I/O) (Note 2) • Framing error (see the specifications of clock-asynchronous serial I/O) • Parity error (see the specifications of clock-asynchronous serial I/O) - On the reception side, an “L” level is output from the TXD2 pin by use of the parity error signal output function (bit 7 of address 037D16 = “1”) when a parity error is detected - On the transmission side, a parity error is detected by the level of input to the RXD2 pin when a transmission interrupt occurs • The error sum flag (see the specifications of clock-asynchronous serial I/O) Note 1: ‘n’ denotes the value 0016 to FF16 that is set to the UART2 bit rate generator. Note 2: If an overrun error occurs, the UART2 receive buffer will have the next data written in. Note also that the UART2 receive interrupt request bit does not change. 118 Mitsubishi microcomputers M16C / 30L Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Clock asynchronous serial I/O (UART) mode Tc Transfer clock Transmit enable bit(TE) “1” Transmit buffer empty flag(TI) “1” “0” Data is set in UART2 transmit buffer register Note 1 “0” Transferred from UART2 transmit buffer register to UART2 transmit register Start bit TxD2 ST D0 Parity bit D 1 D 2 D 3 D4 D 5 D 6 D 7 P Stop bit ST D0 D1 D2 D3 D4 D5 D6 D7 SP P SP P SP RxD2 An “L” level returns from TxD2 due to the occurrence of a parity error. Signal conductor level (Note 2) ST D0 D1 D2 D3 D4 D5 D6 D7 P SP ST D0 D1 D2 D3 D4 D5 D6 D7 The level is detected by the interrupt routine. The level is detected by the interrupt routine. “1” Transmit register empty flag (TXEPT) “0” Transmit interrupt request bit (IR) “1” “0” Cleared to “0” when interrupt request is accepted, or cleared by software Shown in ( ) are bit symbols. The above timing applies to the following settings : • Parity is enabled. • One stop bit. • Transmit interrupt cause select bit = “1”. Tc = 16 (n + 1) / fi fi : frequency of BRG2 count source (f1, f8, f32) n : value set to BRG2 Note 1: The transmit is started with overflow timing of BRG after having written in a value at the transmit buffer in the above timing. Tc Transfer clock Receive enable bit (RE) “1” “0” Start bit RxD2 Parity bit ST D0 D1 D2 D3 D4 D5 D6 D7 P Stop bit SP ST D0 D1 D2 D3 D4 D5 D6 D7 P SP TxD2 An “L” level returns from TxD2 due to the occurrence of a parity error. Signal conductor level (Note 2) Receive complete flag (RI) “1” Receive interrupt request bit (IR) “1” ST D0 D1 D2 D3 D4 D5 D6 D7 P SP ST D0 D1 D2 D3 D4 D5 D6 D7 P SP “0” Read to receive buffer Read to receive buffer “0” Cleared to “0” when interrupt request is accepted, or cleared by software Shown in ( ) are bit symbols. The above timing applies to the following settings : • Parity is enabled. • One stop bit. • Transmit interrupt cause select bit = “0”. Tc = 16 (n + 1) / fi fi : frequency of BRG2 count source (f1, f8, f32) n : value set to BRG2 Note 2: Equal in waveform because TxD2 and RxD2 are connected. Figure 1.16.22. Typical transmit/receive timing in UART mode (used for the SIM interface) 119 Mitsubishi microcomputers M16C / 30L Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Clock asynchronous serial I/O (UART) mode (a) Function for outputting a parity error signal During reception, with the error signal output enable bit (bit 7 of address 037D16) assigned “1”, you can output an “L” level from the TXD2 pin when a parity error is detected. And during transmission, comparing with the case in which the error signal output enable bit (bit 7 of address 037D16) is assigned “0”, the transmission completion interrupt occurs in the half cycle later of the transfer clock. Therefore parity error signals can be detected by a transmission completion interrupt program. Figure 1.16.23 shows the output timing of the parity error signal. • LSB first Transfer clock “H” RxD2 “H” TxD2 “H” Receive complete flag “L” ST D0 D1 D2 D3 D4 D5 D6 D7 P SP “L” Hi-Z “L” “1” “0” ST : Start bit P : Even Parity SP : Stop bit Figure 1.16.23. Output timing of the parity error signal (b) Direct format/inverse format Connecting the SIM card allows you to switch between direct format and inverse format. If you choose the direct format, D0 data is output from TxD2. If you choose the inverse format, D7 data is inverted and output from TxD2. Figure 1.16.24 shows the SIM interface format. Transfer clcck TxD2 (direct) D0 D1 D2 D3 D4 D5 D6 D7 P TxD2 (inverse) D7 D6 D5 D4 D3 D2 D1 D0 P P : Even parity Figure 1.16.24. SIM interface format 120 Mitsubishi microcomputers M16C / 30L Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Clock asynchronous serial I/O (UART) mode Figure 1.16.25 shows the example of connecting the SIM interface. Connect TXD2 and RXD2 and apply pull-up. Microcomputer SIM card TxD2 RxD2 Figure 1.16.25. Connecting the SIM interface 121 Mitsubishi microcomputers M16C / 30L Group UART2 Special Mode Register SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER UART2 Special Mode Register The UART2 special mode register (address 037716) is used to control UART2 in various ways. Figure 1.16.26 shows the UART2 special mode register. Bit 0 of the UART2 special mode register (037716) is used as the I2C mode select bit. Setting “1” in the I2C mode select bit (bit 0) goes the circuit to achieve the I2C bus (simplified I2C bus) interface effective. Table 1.16.9 shows the relation between the I2C mode select bit and respective control workings. Since this function uses clock-synchronous serial I/O mode, set this bit to “0” in UART mode. UART2 special mode register b7 b6 b5 b4 b3 b2 b1 b0 Symbol U2SMR Bit symbol Address 037716 When reset 8016 Function (During clock synchronous serial I/O mode) Bit name Function (During UART mode) AA A AA AAA AA AAA AAA AA A AA AAA AA AAA A R W IICM I2C mode select bit 0 : Normal mode 1 : I2C mode Must always be “0” ABC Arbitration lost detecting flag control bit 0 : Update per bit 1 : Update per byte Must always be “0” BBS Bus busy flag 0 : STOP condition detected 1 : START condition detected Must always be “0” LSYN SCL L sync output enable bit 0 : Disabled 1 : Enabled Must always be “0” ABSCS Bus collision detect sampling clock select bit Must always be “0” 0 : Rising edge of transfer clock 1 : Underflow signal of timer A0 ACSE Auto clear function select bit of transmit enable bit Must always be “0” 0 : No auto clear function 1 : Auto clear at occurrence of bus collision SSS Transmit start condition select bit Must always be “0” 0 : Ordinary 1 : Falling edge of RxD2 SDDS SDA digital delay select bit (Note 2) 0 : Must always be “0” Must always be “0” when not using I2C mode 1 : Digital delay output is selected (Note1) Note 1: Nothing but “0” may be written. Note 2: When not in I2C mode, do not set this bit by writing a “1”. During normal mode, fix it to “0”. When this bit = “0”, UART2 special mode register 3 (U2SMR3 at address 037516) bits 7 to 5 (DL2 to DL0 = SDA digital delay setup bits) are initialized to “000”. Also, when SDDS = “0”, the U2SMR3 register cannot be read or written to. UART2 special mode register 3 (I 2 C bus exclusive use register) b7 b6 b5 b4 b3 b2 b1 b0 Symbol U2SMR3 Bit symbol Address 037516 When reset 0016 Function (I 2 C bus exclusive use register) Bit name Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be indeterminate. However, when SDDS = “1”, the value “0” is read out (Note 1) DL0 SDA digital delay setup bit (Note 1, Note 2, Note 3) DL1 DL2 b7 b6 b5 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 : Must not be set when using I2C mode 1 : 1 to 2 cycle(s) of 1/f(XIN) 0 : 2 to 3 cycles of 1/f(XIN) 1 : 3 to 4 cycles of 1/f(XIN) Digital delay 0 : 4 to 5 cycles of 1/f(XIN) is selected 1 : 5 to 6 cycles of 1/f(XIN) 0 : 6 to 7 cycles of 1/f(XIN) 1 : 7 to 8 cycles of 1/f(XIN) R W AAAA AA Note 1: This bit can be read or written to when UART2 special mode register (U2SMR at address 037716) bit 7 (SDDS: SDA digital delay select bit) = “1”. When the initial value of UART2 special mode register 3 (U2SMR3) is read after setting SDDS = “1”, the value is “0016”. When writing to UART2 special mode register 3 (U2SMR3) after setting SDDS = “1”, be sure to write 0's to bits 0–4. When SDDS = “0”, this register cannot be written to; when read, the value is indeterminate. Note 2: These bits are initialized to “000” when SDDS = “0”. After a reset, these bits are set to “000”. However, because these bits can be read only when SDDS = “1”, the value read from these bits when SDDS = “0” is indeterminate. Note 3: The amount of delay varies with the load on SCL and SDA pins. Also, when using an external clock, the amount of delay increases by about 200 ns, so be sure to take this into account when using the device. Figure 1.16.26. UART2 special mode register 122 Mitsubishi microcomputers M16C / 30L Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER UART2 Special Mode Register P70 through P72 conforming to the simplified I 2C bus P70/TxD2/SDA Timer I/O Selector UART2 Digital delay (Divider) To DMA0 UART2 SDDS=0 or DL=000 Transmission register SDDS=1 and DL 000 D IICM=0 or IICM2=1 UART2 transmission/ NACK interrupt request IICM=1 and IICM2=0 SDHI ALS Q Arbitration T Noize Filter Timer To DMA0 IICM=1 IICM=0 or IICM2=1 Reception register IICM=0 UART2 reception/ACK interrupt request UART2 IICM=1 and IICM2=0 Start condition detection S Q R Stop condition detection Bus busy NACK D L-synchronous output enabling bit Falling edge detection Q T D P71/RxD2/SCL I/O R Q Bus collision/start, stop condition detection interrupt request SWC2 IICM=1 Noize Filter IICM=1 Bus collision CLK control detection UART2 External clock IICM=1 Noize Filter ACK 9th pulse (Port P71 output data latch) Internal clock UART2 Selector Q T Data bus IICM=0 Falling edge of 9 bit IICM=0 SWC Port reading UART2 * With IICM set to 1, the port terminal is to be readable IICM=0 P72/CLK2 Selector even if 1 is assigned to P71 of the direction register. I/O Timer Figure 1.16.27. Functional block diagram for I2C mode Table 1.16.9. Features in I2C mode Function Normal mode I2C mode (Note 1) Start condition detection or stop condition detection 1 Factor of interrupt number 10 (Note 2) Bus collision detection 2 Factor of interrupt number 15 (Note 2) UART2 transmission No acknowledgment detection (NACK) 3 Factor of interrupt number 16 (Note 2) UART2 reception Acknowledgment detection (ACK) 4 UART2 transmission output delay Not delayed Delayed (digital delay) 5 P70 at the time when UART2 is in use TxD2 (output) SDA (input/output) (Note 3) 6 P71 at the time when UART2 is in use RxD2 (input) SCL (input/output) 7 P72 at the time when UART2 is in use CLK2 P72 8 Noise filter width 15ns 200ns 9 Reading P71 Reading the terminal when 0 is assigned to the direction register Reading the terminal regardless of the value of the direction register H level (when 0 is assigned to the CLK polarity select bit) The value set in latch P70 when the port is selected 10 Initial value of UART2 output Note 1: Make the settings given below when I2C mode is in use. Set 0 1 0 in bits 2, 1, 0 of the UART2 transmission/reception mode register. Disable the RTS/CTS function. Choose the MSB First function. Note 2: Follow the steps given below to switch from a factor to another. 1. Disable the interrupt of the corresponding number. 2. Switch from a factor to another. 3. Reset the interrupt request flag of the corresponding number. 4. Set an interrupt level of the corresponding number. Note 3: Set an initial value of SDA transmission output when serial I/O is invalid. 123 Mitsubishi microcomputers M16C / 30L Group UART2 Special Mode Register SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Figure 1.16.27 shows the functional block diagram for I2C mode. Setting “1” in the I2C mode select bit (IICM) causes ports P70, P71, and P72 to work as data transmission-reception terminal SDA, clock inputoutput terminal SCL, and port P72 respectively. A delay circuit is added to the SDA transmission output, so the SDA output changes after SCL fully goes to “L”. The amount of delay can be selected in the range of 2 cycles to 8 cycles of f1 using UART2 special mode register 3 (at address 037516). Delay circuit select conditions are shown in Table 1.16.10. Table 1.16.10. Delay circuit select conditions Register value Contents Digital delay is selected No delay IICM SDDS 1 1 0 0 DL 001 to 111 (000) Digital delay is added When IICM = “0”, no delay circuit is selected. When IICM = “0”, however, always make sure SDDS = “0”. An attempt to read Port P71 (SCL) results in getting the terminal’s level regardless of the content of the port direction register. The initial value of SDA transmission output goes to the value set in port P70. The interrupt factors of the bus collision detection interrupt, UART2 transmission interrupt, and of UART2 reception interrupt turn to the start/stop condition detection interrupt, acknowledgment non-detection interrupt, and acknowledgment detection interrupt respectively. The start condition detection interrupt refers to the interrupt that occurs when the falling edge of the SDA terminal (P70) is detected with the SCL terminal (P71) staying “H”. The stop condition detection interrupt refers to the interrupt that occurs when the rising edge of the SDA terminal (P70) is detected with the SCL terminal (P71) staying “H”. The bus busy flag (bit 2 of the UART2 special mode register) is set to “1” by the start condition detection, and set to “0” by the stop condition detection. The acknowledgment non-detection interrupt refers to the interrupt that occurs when the SDA terminal level is detected still staying “H” at the rising edge of the 9th transmission clock. The acknowledgment detection interrupt refers to the interrupt that occurs when SDA terminal’s level is detected already went to “L” at the 9th transmission clock. Bit 1 of the UART2 special mode register (037716) is used as the arbitration lost detecting flag control bit. Arbitration means the act of detecting the nonconformity between transmission data and SDA terminal data at the timing of the SCL rising edge. This detecting flag is located at bit 11 of the UART2 reception buffer register (037F16, 037E16), and “1” is set in this flag when nonconformity is detected. Use the arbitration lost detecting flag control bit to choose which way to use to update the flag, bit by bit or byte by byte. When setting this bit to “1” and updated the flag byte by byte if nonconformity is detected, the arbitration lost detecting flag is set to “1” at the falling edge of the 9th transmission clock. If update the flag byte by byte, must judge and clear (“0”) the arbitration lost detecting flag after completing the first byte acknowledge detect and before starting the next one byte transmission. Bit 3 of the UART2 special mode register is used as SCL- and L-synchronous output enable bit. Setting this bit to “1” goes the P71 data register to “0” in synchronization with the SCL terminal level going to “L”. 124 Mitsubishi microcomputers M16C / 30L Group UART2 Special Mode Register SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Some other functions added are explained here. Figure 1.16.28 shows their workings. Bit 4 of the UART2 special mode register is used as the bus collision detect sampling clock select bit. The bus collision detect interrupt occurs when the RXD2 level and TXD2 level do not match, but the nonconformity is detected in synchronization with the rising edge of the transfer clock signal if the bit is set to “0”. If this bit is set to “1”, the nonconformity is detected at the timing of the overflow of timer A0 rather than at the rising edge of the transfer clock. Bit 5 of the UART2 special mode register is used as the auto clear function select bit of transmit enable bit. Setting this bit to “1” automatically resets the transmit enable bit to “0” when “1” is set in the bus collision detect interrupt request bit (nonconformity). Bit 6 of the UART2 special mode register is used as the transmit start condition select bit. Setting this bit to “1” starts the TxD transmission in synchronization with the falling edge of the RxD terminal. 1. Bus collision detect sampling clock select bit (Bit 4 of the UART2 special mode register) 0: Rising edges of the transfer clock CLK TxD/RxD 1: Timer A0 overflow Timer A0 2. Auto clear function select bit of transmt enable bit (Bit 5 of the UART2 special mode register) CLK TxD/RxD Bus collision detect interrupt request bit Transmit enable bit 3. Transmit start condition select bit (Bit 6 of the UART2 special mode register) 0: In normal state CLK TxD Enabling transmission With "1: falling edge of RxD2" selected CLK TxD RxD Figure 1.16.28. Some other functions added 125 Mitsubishi microcomputers M16C / 30L Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER UART2 Special Mode Register 2 UART2 Special Mode Register 2 UART2 special mode register 2 (address 037616) is used to further control UART2 in I2C mode. Figure 1.16.29 shows the UART2 special mode register 2. UART2 special mode register 2 (I 2 C bus exclusive use register) b7 b6 b5 b4 b3 b2 b1 b0 Symbol U2SMR2 Bit symbol Address 037616 Bit name Function IICM2 I 2C mode select bit 2 Refer to Table 1.16.11 CSC Clock-synchronous bit 0 : Disabled 1 : Enabled SWC SCL wait output bit 0 : Disabled 1 : Enabled ALS SDA output stop bit 0 : Disabled 1 : Enabled STAC UART2 initialization bit 0 : Disabled 1 : Enabled SWC2 SCL wait output bit 2 0: UART2 clock 1: 0 output SDHI SDA output disable bit 0: Enabled 1: Disabled (high impedance) SHTC Start/stop condition control bit 1: Set this bit to “1” in I2C mode (refer to Table 1.16.12) Figure 1.16.29. UART2 special mode register 2 126 When reset 0016 R W AA A A AA A A A A A A A AA A AA A AA Mitsubishi microcomputers M16C / 30L Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER UART2 Special Mode Register 2 Bit 0 of the UART2 special mode register 2 (address 037616) is used as the I2C mode select bit 2. Table 1.16.11 shows the types of control to be changed by I2C mode select bit 2 when the I2C mode select bit is set to “1”. Table 1.16.12 shows the timing characteristics of detecting the start condition and the stop condition. Set the start/stop condition control bit (bit 7 of UART2 special mode register 2) to “1” in I2C mode. Table 1.16.11. Functions changed by I2C mode select bit 2 Function IICM2 = 0 IICM2 = 1 1 Factor of interrupt number 15 No acknowledgment detection (NACK) UART2 transmission (the rising edge of the final bit of the clock) 2 Factor of interrupt number 16 Acknowledgment detection (ACK) UART2 reception (the falling edge of the final bit of the clock) 3 Timing for transferring data from the UART2 reception shift register to the reception buffer. The rising edge of the final bit of the reception clock The falling edge of the final bit of the reception clock 4 Timing for generating a UART2 reception/ACK interrupt request The rising edge of the final bit of the reception clock The falling edge of the final bit of the reception clock Table 1.16.12. Timing characteristics of detecting the start condition and the stop condition (Note 1) 3 to 6 cycles < duration for setting-up (Note 2) 3 to 6 cycles < duration for holding (Note 2) Note 1 : When the start/stop condition control bit SHTC is “1” . Note 2 : “Cycles” is in terms of the input oscillation frequency f(XIN) of the main clock. Duration for setting up Duration for holding SCL SDA (Start condition) SDA (Stop condition) 127 Mitsubishi microcomputers M16C / 30L Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER UART2 Special Mode Register 2 P70 through P72 conforming to the simplified I 2C bus P70/TxD2/SDA Timer I/O Selector UART2 Digital delay (Divider) To DMA0 UART2 SDDS=0 or DL=000 Transmission register SDDS=1 and DL 000 D IICM=0 or IICM2=1 UART2 transmission/ NACK interrupt request IICM=1 and IICM2=0 SDHI ALS Q Arbitration T Noize Filter Timer To DMA0 IICM=1 IICM=0 or IICM2=1 Reception register IICM=0 UART2 reception/ACK interrupt request UART2 IICM=1 and IICM2=0 Start condition detection S Q R Stop condition detection Bus busy NACK L-synchronous output enabling bit Falling edge detection D Q T D P71/RxD2/SCL I/O R Q Selector (Port P71 output data latch) Internal clock UART2 IICM=1 SWC2 IICM=1 Noize Filter External clock Noize Filter Q T ACK Data bus 9th pulse IICM=1 Bus collision CLK control detection Bus collision/start, stop condition detection interrupt request IICM=0 UART2 Falling edge of 9 bit IICM=0 SWC Port reading UART2 * With IICM set to 1, the port terminal is to be readable IICM=0 P72/CLK2 Selector even if 1 is assigned to P71 of the direction register. I/O Timer Figure 1.16.30. Functional block diagram for I2C mode Functions available in I2C mode are shown in Figure 1.16.30 — a functional block diagram. Bit 3 of the UART2 special mode register 2 (address 037616) is used as the SDA output stop bit. Setting this bit to “1” causes an arbitration loss to occur, and the SDA pin turns to high-impedance state at the instant when the arbitration lost detecting flag is set to “1”. Bit 1 of the UART2 special mode register 2 (address 037616) is used as the clock synchronization bit. With this bit set to “1” at the time when the internal SCL is set to “H”, the internal SCL turns to “L” if the falling edge is found in the SCL pin; and the baud rate generator reloads the set value, and start counting within the “L” interval. When the internal SCL changes from “L” to “H” with the SCL pin set to “L”, stops counting the baud rate generator, and starts counting it again when the SCL pin turns to “H”. Due to this function, the UART2 transmission-reception clock becomes the logical product of the signal flowing through the internal SCL and that flowing through the SCL pin. This function operates over the period from the moment earlier by a half cycle than falling edge of the UART2 first clock to the rising edge of the ninth bit. To use this function, choose the internal clock for the transfer clock. Bit 2 of the UART2 special mode register 2 (037616) is used as the SCL wait output bit. Setting this bit to “1” causes the SCL pin to be fixed to “L” at the falling edge of the ninth bit of the clock. Setting this bit to “0” frees the output fixed to “L”. 128 Mitsubishi microcomputers M16C / 30L Group UART2 Special Mode Register 2 SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Bit 4 of the UART2 special mode register 2 (address 037616) is used as the UART2 initialization bit. Setting this bit to “1”, and when the start condition is detected, the microcomputer operates as follows. (1) The transmission shift register is initialized, and the content of the transmission register is transferred to the transmission shift register. This starts transmission by dealing with the clock entered next as the first bit. The UART2 output value, however, doesn’t change until the first bit data is output after the entrance of the clock, and remains unchanged from the value at the moment when the microcomputer detected the start condition. (2) The reception shift register is initialized, and the microcomputer starts reception by dealing with the clock entered next as the first bit. (3) The SCL wait output bit turns to “1”. This turns the SCL pin to “L” at the falling edge of the ninth bit of the clock. Starting to transmit/receive signals to/from UART2 using this function doesn’t change the value of the transmission buffer empty flag. To use this function, choose the external clock for the transfer clock. Bit 5 of the UART2 special mode register 2 (037616) is used as the SCL wait output bit 2. Setting this bit to “1” with the serial I/O specified allows the user to forcibly output an “1” from the SCL pin even if UART2 is in operation. Setting this bit to “0” frees the “L” output from the SCL pin, and the UART2 clock is input/ output. Bit 6 of the UART2 special mode register 2 (037616) is used as the SDA output disable bit. Setting this bit to “1” forces the SDA pin to turn to the high-impedance state. Refrain from changing the value of this bit at the rising edge of the UART2 transfer clock. There can be instances in which arbitration lost detecting flag is turned on. 129 Mitsubishi microcomputers M16C / 30L Group A-D Converter SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER A-D Converter The A-D converter consists of one 10-bit successive approximation A-D converter circuit with a capacitive coupling amplifier. Pins P100 to P107, P95, and P96 also function as the analog signal input pins. The direction registers of these pins for A-D conversion must therefore be set to input. The Vref connect bit (bit 5 at address 03D716) can be used to isolate the resistance ladder of the A-D converter from the reference voltage input pin (VREF) when the A-D converter is not used. Doing so stops any current flowing into the resistance ladder from VREF, reducing the power dissipation. When using the A-D converter, start A-D conversion only after setting bit 5 of 03D716 to connect VREF. The result of A-D conversion is stored in the A-D registers of the selected pins. When set to 10-bit precision, the low 8 bits are stored in the even addresses and the high 2 bits in the odd addresses. When set to 8-bit precision, the low 8 bits are stored in the even addresses. Table 1.17.1 shows the performance of the A-D converter. Figure 1.17.1 shows the block diagram of the A-D converter, and Figures 1.17.2 and 1.17.3 show the A-D converter-related registers. Table 1.17.1. Performance of A-D converter Item Performance Method of A-D conversion Successive approximation (capacitive coupling amplifier) Analog input voltage (Note 1) 0V to AVCC (VCC) Operating clock φAD (Note 2) VCC = 3.3V fAD/divide-by-2 of fAD/divide-by-4 of fAD, fAD=f(XIN) Resolution 8-bit or 10-bit (selectable) Absolute precision VCC = 3.3V • Without sample and hold function ±5LSB • With sample and hold function (8-bit resolution) ±2LSB • With sample and hold function (10-bit resolution) AN0 to AN7 input : ±5LSB ANEX0 and ANEX1 input (including mode in which external operation amp is connected) : ±7LSB Operating modes One-shot mode Analog input pins 8pins (AN0 to AN7) + 2pins (ANEX0 and ANEX1) A-D conversion start condition • Software trigger A-D conversion starts when the A-D conversion start flag changes to “1” • External trigger (can be retriggered) A-D conversion starts when the A-D conversion start flag is “1” and the ADTRG/P97 input changes from “H” to “L” Conversion speed per pin • Without sample and hold function 8-bit resolution: 49 φAD cycles, 10-bit resolution: 59 φAD cycles • With sample and hold function 8-bit resolution: 28 φAD cycles, 10-bit resolution: 33 φAD cycles Note 1: Does not depend on use of sample and hold function. Note 2: Divide the fAD if f(XIN) exceeds 10MHZ, and make φAD frequency equal to or less than 10MHz. And divide the fAD if VCC is less than 3.0V, and make φAD frequency equal to or lower than fAD/2. Without sample and hold function, set the φAD frequency to 250kHZ min. With the sample and hold function, set the φAD frequency to 1MHZ min. 130 Mitsubishi microcomputers M16C / 30L Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER A-D Converter CKS1=1 φAD CKS0=1 fAD 1/2 1/2 CKS0=0 CKS1=0 A-D conversion rate selection V REF VCUT=0 Resistor ladder AV SS VCUT=1 Successive conversion register A-D control register 1 (address 03D716) A-D control register 0 (address 03D616) Addresses (03C116, 03C016) A-D register 0(16) (03C316, 03C216) A-D register 1(16) A-D register 2(16) A-D register 3(16) (03C516, 03C416) (03C716, 03C616) (03C916, 03C816) A-D register 4(16) (03CB16, 03CA16) (03CD16, 03CC16) A-D register 5(16) A-D register 6(16) (03CF16, 03CE16) A-D register 7(16) Vref Decoder VIN Comparator Data bus high-order Data bus low-order AN0 CH2,CH1,CH0=000 AN1 CH2,CH1,CH0=001 AN2 CH2,CH1,CH0=010 AN3 CH2,CH1,CH0=011 AN4 CH2,CH1,CH0=100 AN5 CH2,CH1,CH0=101 AN6 CH2,CH1,CH0=110 AN7 CH2,CH1,CH0=111 OPA1,OPA0=0,0 OPA1, OPA0 OPA1,OPA0=1,1 OPA0=1 0 0 1 1 0 : Normal operation 1 : ANEX0 0 : ANEX1 1 : External op-amp mode ANEX0 OPA1,OPA0=0,1 ANEX1 OPA1=1 Figure 1.17.1. Block diagram of A-D converter 131 Mitsubishi microcomputers M16C / 30L Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER A-D Converter A-D control register 0 (Note) b7 b6 b5 b4 b3 b2 b1 b0 Symbol ADCON0 Bit symbol Address 03D616 When reset 00000XXX2 Bit name Function b2 b1 b0 CH0 Analog input pin select bit CH1 CH2 MD0 A-D operation mode select bit 0 MD1 0 0 0 : AN0 is selected 0 0 1 : AN1 is selected 0 1 0 : AN2 is selected 0 1 1 : AN3 is selected 1 0 0 : AN4 is selected 1 0 1 : AN5 is selected 1 1 0 : AN6 is selected 1 1 1 : AN7 is selected b4 b3 0 0 : One-shot mode Must not be set except “00” Trigger select bit 0 : Software trigger 1 : ADTRG trigger ADST A-D conversion start flag 0 : A-D conversion disabled 1 : A-D conversion started CKS0 Frequency select bit 0 0 : fAD/4 is selected 1 : fAD/2 is selected TRG AA A AA A AA A AA A AA A AA A AA A AA A AA A RW Note: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate. A-D control register 1 (Note) b7 b6 b5 b4 b3 b2 b1 b0 0 0 0 Symbol ADCON1 Bit symbol Address 03D716 When reset 0016 Bit name Reserved bit Function Must always be set to “0” BITS 8/10-bit mode select bit 0 : 8-bit mode 1 : 10-bit mode CKS1 Frequency select bit 1 0 : fAD/2 or fAD/4 is selected 1 : fAD is selected Vref connect bit 0 : Vref not connected 1 : Vref connected External op-amp connection mode bit b7 b6 VCUT OPA0 OPA1 AA A AA A AA A AA A AA A AA A AA A RW 0 0 : ANEX0 and ANEX1 are not used 0 1 : ANEX0 input is A-D converted 1 0 : ANEX1 input is A-D converted 1 1 : External op-amp connection mode Note: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate. Figure 1.17.2. A-D converter-related registers (1) 132 Mitsubishi microcomputers M16C / 30L Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER A-D Converter A-D control register 2 (Note) b7 b6 b5 b4 b3 b2 b1 b0 0 0 0 Symbol Address When reset ADCON2 03D416 0000XXX02 Bit symbol SMP Bit name A-D conversion method select bit Reserved bit Function 0 : Without sample and hold 1 : With sample and hold Must always be set to “0” Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be “0”. AA AA RW Note: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate. Symbol A-D register i (b15) b7 ADi(i=0 to 7) (b8) b0 b7 Address When reset 03C016 to 03CF16 Indeterminate b0 Function Eight low-order bits of A-D conversion result • During 10-bit mode Two high-order bits of A-D conversion result • During 8-bit mode When read, the content is indeterminate A A A R W Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be “0”. Figure 1.17.3. A-D converter-related registers (2) 133 Mitsubishi microcomputers M16C / 30L Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER A-D Converter (1) One-shot mode In one-shot mode, the pin selected using the analog input pin select bit is used for one-shot A-D conversion. Table 1.17.2 shows the specifications of one-shot mode. Figure 1.17.4 shows the A-D control register in one-shot mode. Table 1.17.2. One-shot mode specifications Item Function Start condition Stop condition Interrupt request generation timing Input pin Reading of result of A-D converter Specification The pin selected by the analog input pin select bit is used for one A-D conversion Writing “1” to A-D conversion start flag • End of A-D conversion (A-D conversion start flag changes to “0”, except when external trigger is selected) • Writing “0” to A-D conversion start flag End of A-D conversion One of AN0 to AN7, as selected Read A-D register corresponding to selected pin A-D control register 0 (Note) b7 b6 b5 b4 b3 b2 b1 b0 0 0 Symbol ADCON0 Bit symbol CH0 Address 03D616 Bit name Analog input pin select bit CH1 CH2 MD0 When reset 00000XXX2 Function b2 b1 b0 0 0 0 : AN0 is selected 0 0 1 : AN1 is selected 0 1 0 : AN2 is selected 0 1 1 : AN3 is selected 1 0 0 : AN4 is selected 1 0 1 : AN5 is selected 1 1 0 : AN6 is selected 1 1 1 : AN7 is selected b4 b3 MD1 A-D operation mode select bit 0 TRG Trigger select bit 0 : Software trigger 1 : ADTRG trigger ADST A-D conversion start flag 0 : A-D conversion disabled 1 : A-D conversion started CKS0 Frequency select bit 0 0: fAD/4 is selected 1: fAD/2 is selected 0 0 : One-shot mode AAA AAA AA A AAA AAA AA A AA A AAA RW Note : If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate. A-D control register 1 (Note) b7 b6 b5 1 b4 b3 b2 b1 b0 0 0 0 Symbol ADCON1 Bit symbol Address 03D716 When reset 0016 Bit name Reserved bit Function Must always be set to “0” BITS 8/10-bit mode select bit 0 : 8-bit mode 1 : 10-bit mode CKS1 Frequency select bit1 0 : fAD/2 or fAD/4 is selected 1 : fAD is selected VCUT Vref connect bit OPA0 External op-amp connection mode bit OPA1 1 : Vref connected b7 b6 0 0 : ANEX0 and ANEX1 are not used 0 1 : ANEX0 input is A-D converted 1 0 : ANEX1 input is A-D converted 1 1 : External op-amp connection mode AA A AA A AA A AA A AA A AAA RW Note: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate. Figure 1.17.4. A-D conversion register in one-shot mode 134 Mitsubishi microcomputers M16C / 30L Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER A-D Converter (a) Sample and hold Sample and hold is selected by setting bit 0 of the A-D control register 2 (address 03D416) to “1”. When sample and hold is selected, the rate of conversion of each pin increases. As a result, a 28 φAD cycle is achieved with 8-bit resolution and 33 φAD with 10-bit resolution. Sample and hold can be selected in all modes. However, in all modes, be sure to specify before starting A-D conversion whether sample and hold is to be used. (b) Extended analog input pins In one-shot mode and repeat mode, the input via the extended analog input pins ANEX0 and ANEX1 can also be converted from analog to digital. When bit 6 of the A-D control register 1 (address 03D716) is “1” and bit 7 is “0”, input via ANEX0 is converted from analog to digital. The result of conversion is stored in A-D register 0. When bit 6 of the A-D control register 1 (address 03D716) is “0” and bit 7 is “1”, input via ANEX1 is converted from analog to digital. The result of conversion is stored in A-D register 1. (c) External operation amp connection mode In this mode, multiple external analog inputs via the extended analog input pins, ANEX0 and ANEX1, can be amplified together by just one operation amp and used as the input for A-D conversion. When bit 6 of the A-D control register 1 (address 03D716) is “1” and bit 7 is “1”, input via AN0 to AN7 is output from ANEX0. The input from ANEX1 is converted from analog to digital and the result stored in the corresponding A-D register. The speed of A-D conversion depends on the response of the external operation amp. Do not connect the ANEX0 and ANEX1 pins directly. Figure 1.17.5 is an example of how to connect the pins in external operation amp mode. Resistor ladder Successive conversion register Analog input AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 ANEX0 ANEX1 Comparator External op-amp Figure 1.17.5. Example of external op-amp connection mode 135 Mitsubishi microcomputers M16C / 30L Group Programmable I/O Port SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Programmable I/O Ports There are 87 programmable I/O ports: P0 to P10 (excluding P85). Each port can be set independently for input or output using the direction register. A pull-up resistance for each block of 4 ports can be set. P85 is an input-only port and has no built-in pull-up resistance. Figures 1.20.1 to 1.20.4 show the programmable I/O ports. Figure 1.20.5 shows the I/O pins. Each pin functions as a programmable I/O port and as the I/O for the built-in peripheral devices. To use the pins as the inputs for the built-in peripheral devices, set the direction register of each pin to input mode. When the pins are used as the outputs for the built-in peripheral devices (other than the D-A converter), they function as outputs regardless of the contents of the direction registers. When pins are to be used as the outputs for the D-A converter, do not set the direction registers to output mode. See the descriptions of the respective functions for how to set up the built-in peripheral devices. (1) Direction registers Figure 1.20.6 shows the direction registers. These registers are used to choose the direction of the programmable I/O ports. Each bit in these registers corresponds one for one to each I/O pin. In memory expansion and microprocessor mode, the contents of corresponding direction register of pins _______ _______ _____ ________ ______ ________ _______ _______ __________ _________ A0 to A19, D0 to D15, CS0 to CS3, RD, WRL/WR, WRH/BHE, ALE, RDY, HOLD, HLDA and BCLK cannot be modified. Note: There is no direction register bit for P85. (2) Port registers Figure 1.20.7 shows the port registers. These registers are used to write and read data for input and output to and from an external device. A port register consists of a port latch to hold output data and a circuit to read the status of a pin. Each bit in port registers corresponds one for one to each I/O pin. In memory expansion and microprocessor mode, the contents of corresponding port register of pins A0 to _______ ________ _____ ________ ______ ________ ________ _______ __________ _________ A19, D0 to D15, CS0 to CS3, RD, WRL/WR, WRH/BHE, ALE, RDY, HOLD, HLDA and BCLK cannot be modified. (3) Pull-up control registers Figure 1.20.8 shows the pull-up control registers. The pull-up control register can be set to apply a pull-up resistance to each block of 4 ports. When ports are set to have a pull-up resistance, the pull-up resistance is connected only when the direction register is set for input. However, in memory expansion mode and microprocessor mode, the pull-up control register of P0 to P3, P40 to P43, and P5 is invalid. The contents of register can be changed, but the pull-up resistance is not connected. (4) Port control register Figure 1.20.9 shows the port control register. The bit 0 of port control register is used to read port P1 as follows: 0 : When port P1 is input port, port input level is read. When port P1 is output port , the contents of port P1 register is read. 1 : The contents of port P1 register is read always. This register is valid in the following: • External bus width is 8 bits in microprocessor mode or memory expansion mode. • Port P1 can be used as a port in multiplexed bus for the entire space. 136 Mitsubishi microcomputers M16C / 30L Group Programmable I/O Port SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Pull-up selection Direction register P00 to P07, P20 to P27, P30 to P37, P40 to P47, P50 to P54, P56 Data bus Port latch (Note) Pull-up selection Direction register P10 to P14 Port P1 control register Data bus Port latch (Note) Pull-up selection Direction register P15 to P17 Port P1 control register Data bus Port latch (Note) Input to respective peripheral functions Pull-up selection Direction register P57, P60, P61, P64, P65, P72, P73, P74 "1" Output Data bus Port latch (Note) Input to respective peripheral functions Note: symbolizes a parasitic diode. Do not apply a voltage higher than Vcc to each port. Figure 1.20.1. Programmable I/O ports (1) 137 Mitsubishi microcomputers M16C / 30L Group Programmable I/O Port SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Pull-up selection P82 to P84 Direction register Data bus Port latch (Note1) Input to respective peripheral functions Pull-up selection Direction register P76, P77, P80, P81, P90, P93, P94 (inside dotted-line not included) P55, P62, P66, P75, P91, P92, P97 (inside dotted-line included) Data bus Port latch (Note1) Input to respective peripheral functions (Note 2) Pull-up selection Direction register P63, P67 "1" Data bus Port latch Output (Note1) P85 Data bus NMI interrupt input Note 1: symbolizes a parasitic diode. Do not apply a voltage higher than Vcc to each port. Note 2: In a part of port, the input to a respective peripheral functions does not exist, but schmitt circuit exists. Figure 1.20.2. Programmable I/O ports (2) 138 (Note1) Mitsubishi microcomputers M16C / 30L Group Programmable I/O Port SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Direction register P70, P71 "1" Data bus Port latch Output (Note 2) Input to respective peripheral functions Pull-up selection P96, P100 to P103 (inside dotted-line not included) P95, P104 to P107 (inside dotted-line included) Direction register Data bus Port latch (Note 1) Analog input Input to respective peripheral functions Note 1: symbolizes a parasitic diode. Do not apply a voltage higher than Vcc to each port. Note 2: symbolizes a parasitic diode. Figure 1.20.3. Programmable I/O ports (3) 139 Mitsubishi microcomputers M16C / 30L Group Programmable I/O Port SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Pull-up selection Direction register P87 Data bus Port latch (Note) fc Rf Pull-up selection Rd Direction register P86 "1" Data bus Port latch Output (Note) Note : symbolizes a parasitic diode. Do not apply a voltage higher than Vcc to each port. Figure 1.20.4. Programmable I/O ports (4) BYTE BYTE signal input (Note) CNVSS CNVSS signal input (Note) RESET RESET signal input (Note) Note : Figure 1.20.5. I/O pins 140 symbolizes a parasitic diode. Do not apply a voltage higher than Vcc to each pin. Mitsubishi microcomputers M16C / 30L Group Programmable I/O Port SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Port Pi direction register (Note 1, 2) b7 b6 b5 b4 b3 b2 b1 b0 Symbol PDi (i = 0 to 10, except 8) Bit symbol Address 03E216, 03E316, 03E616, 03E716, 03EA16 03EB16, 03EE16, 03EF16, 03F316, 03F616 Bit name PDi_0 PDi_1 Port Pi0 direction register Port Pi1 direction register PDi_2 Port Pi2 direction register PDi_3 Port Pi3 direction register PDi_4 Port Pi4 direction register PDi_5 Port Pi5 direction register PDi_6 PDi_7 Port Pi6 direction register Port Pi7 direction register When reset 0016 0016 AA AA A A A A AA AA AA AA Function RW 0 : Input mode (Functions as an input port) 1 : Output mode (Functions as an output port) (i = 0 to 10 except 8) Note 1: Set bit 2 of protect register (address 000A16) to “1” before rewriting to the port P9 direction register. Note 2: In memory expansion and microprocessor mode, the contents of corresponding port Pi direction register of pins A0 to A19, D0 to D15, CS0 to CS3, RD, WRL/WR, WRH/BHE, ALE, RDY, HOLD, HLDA and BCLK cannot be modified. Port P8 direction register b7 b6 b5 b4 b3 b2 b1 b0 Symbol PD8 Bit symbol PD8_0 Address 03F216 Bit name When reset 00X000002 Function Port P80 direction register PD8_1 Port P81 direction register PD8_2 Port P82 direction register PD8_3 Port P83 direction register 0 : Input mode (Functions as an input port) 1 : Output mode (Functions as an output port) PD8_4 Port P84 direction register Nothing is assigned. In an attempt to write to this bit, write “0”. The value, if read, turns out to be indeterminate. PD8_6 Port P86 direction register PD8_7 Port P87 direction register A A AA AA A A AA AA AA AA RW 0 : Input mode (Functions as an input port) 1 : Output mode (Functions as an output port) Figure 1.20.6. Direction register 141 Mitsubishi microcomputers M16C / 30L Group Programmable I/O Port SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Port Pi register (Note 2) b7 b6 b5 b4 b3 b2 b1 b0 Symbol Pi (i = 0 to 10, except 8) Bit symbol Address 03E016, 03E116, 03E416, 03E516, 03E816 03E916, 03EC16, 03ED16, 03F116, 03F416 Bit name Pi_0 Port Pi0 register Pi_1 Pi_2 Port Pi1 register Port Pi2 register Pi_3 Port Pi3 register Pi_4 Port Pi4 register Pi_5 Port Pi5 register Pi_6 Port Pi6 register Pi_7 Port Pi7 register Function Data is input and output to and from each pin by reading and writing to and from each corresponding bit 0 : “L” level data 1 : “H” level data (Note 1) (i = 0 to 10 except 8) When reset Indeterminate Indeterminate AA A AAA AA A AA A AA A AAA RW Note 1: Since P70 and P71 are N-channel open drain ports, the data is high-impedance. Note 2: In memory expansion and microprocessor mode, the contents of corresponding port Pi register of pins A0 to A19, D0 to D15, CS0 to CS3, RD, WRL/WR, WRH/BHE, ALE, RDY, HOLD, HLDA and BCLK cannot be modified. Port P8 register b7 b6 b5 b4 b3 b2 b1 b0 Symbol P8 Bit symbol Bit name P8_0 Port P80 register P8_1 Port P81 register P8_2 Port P82 register P8_3 Port P83 register P8_4 Port P84 register P8_5 Port P85 register P8_6 Port P86 register P8_7 Port P87 register Figure 1.20.7. Port register 142 Address 03F016 When reset Indeterminate Function AA A AA A AA A AA A AAA Data is input and output to and from each pin by reading and writing to and from each corresponding bit (except for P85) 0 : “L” level data 1 : “H” level data R W Mitsubishi microcomputers M16C / 30L Group Programmable I/O Port SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Pull-up control register 0 (Note) b7 b6 b5 b4 b3 b2 b1 b0 Symbol PUR0 Address 03FC16 Bit symbol Bit name PU00 P00 to P03 pull-up PU01 P04 to P07 pull-up PU02 P10 to P13 pull-up PU03 P14 to P17 pull-up PU04 P20 to P23 pull-up PU05 P24 to P27 pull-up PU06 P30 to P33 pull-up PU07 P34 to P37 pull-up When reset 0016 Function The corresponding port is pulled high with a pull-up resistor 0 : Not pulled high 1 : Pulled high A A A A A RW Note : In memory expansion and microprocessor mode, the content of this register can be changed, but the pull-up resistance is not connected. Pull-up control register 1 b7 b6 b5 b4 b3 b2 b1 b0 Symbol PUR1 Address 03FD16 Bit symbol PU10 PU11 PU12 PU13 Bit name When reset 0016 (Note 2) Function P40 to P43 pull-up (Note 3) The corresponding port is pulled high with a pull-up resistor P44 to P47 pull-up 0 : Not pulled high P50 to P53 pull-up (Note 3) 1 : Pulled high P54 to P57 pull-up (Note 3) PU14 P60 to P63 pull-up PU15 P64 to P67 pull-up PU16 P72 to P73 pull-up (Note 1) A A A A A A R W PU17 P74 to P77 pull-up Note 1: Since P70 and P71 are N-channel open drain ports, pull-up is not available for them. Note 2: When the VCC level is being impressed to the CNVSS terminal, this register becomes to 0216 when reset (PU11 becomes to “1”). Note 3: In memory expansion and microprocessor mode, the content of these bits can be changed, but the pull-up resistance is not connected. Pull-up control register 2 b7 b6 b5 b4 b3 b2 b1 b0 Symbol PUR2 Address 03FE16 Bit symbol Bit name PU20 P80 to P83 pull-up PU21 PU22 P84 to P87 pull-up (Except P85) P90 to P93 pull-up PU23 PU24 P94 to P97 pull-up P100 to P103 pull-up PU25 P104 to P107 pull-up When reset 0016 Function The corresponding port is pulled high with a pull-up resistor 0 : Not pulled high 1 : Pulled high Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be “0”. A A A A A RW Figure 1.20.8. Pull-up control register 143 Mitsubishi microcomputers M16C / 30L Group Programmable I/O Port SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Port control register b7 b6 b5 b4 b3 b2 b1 b0 Symbpl PCR Address 03FF16 Bit symbol PCR0 Bit name Port P1 control register When reset 0016 Function 0 : When input port, read port input level. When output port, read the contents of port P1 register. 1 : Read the contents of port P1 register though input/output port. Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be “0”. Figure 1.20.9. Port control register 144 R W A Mitsubishi microcomputers M16C / 30L Group Programmable I/O Port SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Table 1.20.1. Example connection of unused pins in single-chip mode Pin name Connection Ports P0 to P10 (excluding P85) After setting for input mode, connect every pin to VSS via a resistor (pull-down); or after setting for output mode, leave these pins open. XOUT (Note) Open NMI Connect via resistor to VCC (pull-up) AVCC Connect to VCC AVSS, VREF, BYTE Connect to VSS Note: With external clock input to XIN pin. Table 1.20.2. Example connection of unused pins in memory expansion mode and microprocessor mode Pin name Connection Ports P6 to P10 (excluding P85) After setting for input mode, connect every pin to VSS via a resistor (pull-down); or after setting for output mode, leave these pins open. P45 / CS1 to P47 / CS3 Set ports to input mode, set output enable bits of CS1 through CS3 to 0, and connect to Vcc via resistors (pull-up). BHE, ALE, HLDA, XOUT (Note 1), BCLK (Note 2) Open HOLD, RDY, NMI Connect via resistor to VCC (pull-up) AVCC Connect to VCC AVSS, VREF Connect to VSS Note 1: With external clock input to XIN pin. Note 2: When the BCLK output disable bit (bit 7 at address 000416) is set to “1”, connect to VCC via a resistor (pull-up). Microcomputer Microcomputer Port P0 to P10 (except for P85) Port P6 to P10 (except for P85) (Input mode) · · · (Input mode) (Output mode) (Input mode) · · · (Input mode) · · · (Output mode) Open AVCC NMI BHE Port P45 / CS1 HLDA to P47 / CS3 ALE XOUT BCLK (Note) BYTE HOLD NMI XOUT Open VCC AVSS RDY VREF AVCC · · · Open Open VCC AVSS VREF VSS VSS In single-chip mode In memory expansion mode or in microprocessor mode Note : When the BCLK output disable bit (bit 7 at address 000416) is set to “1”, connect to VCC via a resistor (pull-up). Figure 1.20.10. Example connection of unused pins 145 Mitsubishi microcomputers M16C / 30L Group Electrical characteristics SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Electrical characteristics Table 1.26.1. Absolute maximum ratings Symbol Parameter Condition Unit Vcc Supply voltage VCC=AVCC - 0.3 to 4.2 V AVcc Analog supply voltage VCC=AVCC - 0.3 to 4.2 V - 0.3 to Vcc + 0.3 V - 0.3 to 4.2 V - 0.3 to Vcc + 0.3 V - 0.3 to 4.2 300 - 20 to 85 / -40 to 85 (Note) V mW C - 65 to 150 C Input voltage VI RESET, CNVSS, BYTE, P00 to P07, P10 to P17, P20 to P27, P30 to P37,P40 to P47, P50 to P57, P60 to P67, P72 to P77, P80 to P87, P90 to P97, P100 to P107, VREF, XIN P70, P71 Output voltage VO Pd P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P60 to P67, P72 to P77, P80 to P84, P86, P87, P90 to P97, P100 to P107, XOUT P70, P71 Power dissipation Operating ambient temperature Topr Storage temperature Tstg Note: Specify a product of -40°C to 85°C to use it. 146 Rated value Topr=25 C Mitsubishi microcomputers M16C / 30L Group Electrical characteristics SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Table 1.26.2. Recommended operating conditions (referenced to VCC = 2.2V to 3.6V at Topr = – 20°C to 85oC / – 40°C to 85oC(Note 3) unless otherwise specified) Parameter Symbol Min. Supply voltage Analog supply voltage Supply voltage Analog supply voltage Vcc AVcc Vss AVss HIGH input voltage VIH 2.2 Standard Typ. Max. 3.3 3.6 Vcc P31 to P37, P40 to P47, P50 to P57, P60 to P67, P72 to P77, P80 to P87, P90 to P97, P100 to P107, XIN, RESET, CNVSS, BYTE P70, P71 Unit V 0 V V 0 V 0.8Vcc V cc V 0.8Vcc 4.2 V 0.8Vcc V cc V 0.5Vcc V cc V 0 0.2Vcc V 0 0.2Vcc V 0 0.16Vcc V HIGH peak output I OH (peak) current - 10.0 mA I OH (avg) - 5.0 mA 10.0 mA 5.0 mA P00 to P07, P10 to P17, P20 to P27, P30 (during single-chip mode) P00 to P07, P10 to P17, P20 to P27, P30 (data input function during memory expansion and microprocessor modes) LOW input voltage VIL P31 to P37, P40 to P47, P50 to P57, P60 to P67, P70 to P77, P80 to P87, P90 to P97, P100 to P107, XIN, RESET, CNVSS, BYTE P00 to P07, P10 to P17, P20 to P27, P30 (during single-chip mode) P00 to P07, P10 to P17, P20 to P27, P30 (data input function during memory expansion and microprocessor modes) I OL (peak) I OL (avg) P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P60 to P67, P72 to P77, P80 to P84, P86, P87, P90 to P97, P100 to P107 HIGH average output P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P60 to P67, P72 to P77, current P80 to P84, P86, P87, P90 to P97, P100 to P107 P00 to P07, P10 to P17, P20 to P27, P30 to P37, LOW peak output P40 to P47, P50 to P57, P60 to P67, P70 to P77, current P80 to P84, P86, P87, P90 to P97, P100 to P107 P00 to P07, P10 to P17, P20 to P27, P30 to P37, LOW average P40 to P47, P50 to P57, P60 to P67, P70 to P77, output current P80 to P84, P86, P87, P90 to P97, P100 to P107 No wait Main clock input oscillation frequency (Note 4) f (XIN) With wait f (XcIN) Vcc=3.0V to 3.6V 0 16 MHz Vcc=2.4V to 3.0V 0 MHz Vcc=2.2V to 2.4V 0 Vcc=3.0V to 3.6V 0 15 X Vcc - 29 17.5 X Vcc - 35 16 Vcc=2.4V to 3.0V 0 Vcc=2.2V to 2.4V 0 Subclock oscillation frequency 32.768 11.25 X Vcc - 17.75 11.25 X Vcc - 17.75 50 MHz MHz MHz MHz kHz Note 1: The mean output current is the mean value within 100ms. Note 2: The total IOL (peak) for ports P0, P1, P2, P86, P87, P9, and P10 must be 80mA max. The total IOH (peak) for ports P0, P1, P2, P86, P87, P9, and P10 must be 80mA max. The total IOL (peak) for ports P3, P4, P5, P6, P7, and P80 to P84 must be 80mA max. The total IOH (peak) for ports P3, P4, P5, P6, P72 to P77, and P80 to P84 must be 80mA max. Note 3: Specify a product of -40°C to 85°C to use it. Note 4: Relationship between main clock oscillation frequency and supply voltage. 16.0 AAAAAA AAAAAA AA AAAAAA AA AAAAAA AA AAAAAA AA AAAAAA AA AAAAAA AA AAAAAA 15 X VCC –29MHZ 17.5 X VCC–35MHZ 7.0 3.5 0.0 2.2 2.4 3.0 3.6 Main clock input oscillation frequency (With wait) Operating maximum frequency [MHZ] Operating maximum frequency [MHZ] Main clock input oscillation frequency (No wait) AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA 11.25 X VCC –17.75MHZ 16.0 9.25 7.0 0.0 2.2 2.4 3.0 Supply voltage[V] Supply voltage[V] (BCLK: no division) (BCLK: no division) 3.6 147 Mitsubishi microcomputers M16C / 30L Group Electrical characteristics SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Table 1.26.3. Electrical characteristics (referenced to VCC = 3.0V to 3.6V, VSS = 0V at Topr = – 20oC to 85oC / – 40oC to 85oC (Note 1), f(XIN) = 16MHZ unless otherwise specified) Symbol VOH VOH Measuring condition Parameter HIGH output P00 to P07, P10 to P17, P20 to P27, voltage P30 to P37, P40 to P47, P50 to P57, IOH = -1mA P60 to P67, P72 to P77, P80 to P84, P86, P87, P90 to P97, P100 to P107 VCC = 3.3V HIGH output voltage XOUT HIGH output voltage XCOUT IOH = -0.1mA, VCC = 3.3V 2 .8 IOH = -50µA, VCC = 3.3V 2 .8 HIGHPOWER With no load applied, VCC = 3.3V 2.8 LOWPOWER With no load applied, VCC = 3.3V 1 .6 VOL LOW output voltage XOUT Hysteresis 0 .5 IOL = 50µA, VCC = 3.3V 0 .5 HIGHPOWER With no load applied, VCC = 3.3V 0 LOWPOWER With no load applied, VCC = 3.3V 0 VCC = 3.3V RESET VCC = 3.3V IIH HIGH input P00 to P07, P10 to P17, P20 to P27, current P30 to P37, P40 to P47 ,P50 to P57, P60 to P67, P70 to P77, P80 to P87, P90 to P97, P100 to P107, XIN, RESET, CNVss, BYTE R PULLUP Pull-up resistance 0 .5 IOL = 0.1mA, VCC = 3.3V Hysteresis I IL V LOWPOWER VT+-VT- LOW input current V HIGHPOWER HOLD, RDY, TA0IN to TA2IN, TB1IN, TB2IN, INT0 to INT2, NMI, ADTRG, CTS0 to CTS2, SCL, SDA CLK0 to CLK2,TA2OUT, KI0 to KI3, RxD0 to RxD2 P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P60 to P67, P70 to P77, P80 to P87, P90 to P97, P100 to P107, XIN, RESET, CNVss, BYTE P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P60 to P67, P72 to P77, P80 to P84, P86, P87, P90 to P97 ,P100 to P107 Unit V 2 .8 LOWPOWER LOW output P00 to P07 ,P10 to P17, P20 to P27, voltage P30 to P37, P40 to P47, P50 to P57, IO L = 1 m A P60 to P67, P70 to P77, P80 to P84, VCC = 3.3V P86, P87, P90 to P97, P100 to P107 VT+-VT- Standard Typ. Max. HIGHPOWER VOL LOW output voltage XCOUT Min V V V 0 .2 0.8 V 0.2 1.8 V VI = 3V VCC = 3.3V 4.0 µA VI = 0V VCC = 3.3V -4.0 µA 500.0 kΩ VI = 0V VCC = 3.3V 20.0 100.0 R fXIN Feedback resistance XIN 3 .0 MΩ R fXCIN Feedback resistance XCIN 10.0 MΩ V RAM RAM retention voltage When clock is stopped In single-chip mode, the output pins are open and other pins are VSS f(XIN) = 16MHz, Square wave, no division f(XCIN) = 32kHz, VCC = 3.3V Square wave V 2 .0 12.5 25.0 mA 40.0 µA 5.8 µA 2 .7 µA f(XCIN) = 32kHz, VCC = 3.3V I cc Power supply current When a WAITinstruction is executed. Oscillation capacity High (Note 2) f(XCIN) = 32kHz, VCC = 3.3V When a WAIT instruction is executed. Oscillation capacity Low (Note 2) Note 1: Specify a product of -40°C to 85°C to use it. Note 2: With one timer operated using fC32. 148 Topr = 25°C, VCC = 3.3V when clock is stopped 0 .1 2.0 Topr = 85°C, VCC = 3.3V when clock is stopped 0 .4 100 µA Mitsubishi microcomputers M16C / 30L Group Electrical characteristics SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Table 1.26.4. A-D conversion characteristics (referenced to VCC = AVCC = VREF = 2.4V to 3.6V, VSS = AVSS = 0V, at Topr = – 20oC to 85oC / – 40oC to 85oC (Note 4), f(XIN) =16MHZ unless otherwise specified) Symbol Paramete Measuring condition Resolution VREF = VCC Absolute accuracy Sample & hold function not available VREF = VCC = 3.3V Sample & hold function available(10bit) VREF=VCC AN0 to AN7 input = 3.3V ANEX0, ANEX1 input Sample & hold function available(8bit) VREF = VCC = 3.3V Standard Min. Typ. Max. 10 ±2 ±2 ±5 ±5 ±7 ±2 40 Unit Bits LSB LSB LSB LSB 10 Ladder resistance VREF = VCC kΩ Conversion time(10bit) µs 3.3 Conversion time(8bit) 2.8 µs Sampling time 0.3 µs 2.4 VCC VREF V Reference voltage 0 VREF V VI A Analog input voltage Note 1: Do f(XIN) in range of main clock input oscillation frequency prescribed with recommended operating conditions of table 1.26.2. Divide the fAD if f(XIN) exceeds 10MHz, and make AD operation clock frequency (ØAD) equal to or lower than 10MHz. And divide the fAD if VCC is less than 3.0V, and make AD operation clock frequency (ØAD) equal to or lower than fAD/2. Note 2: A case without sample & hold function turn AD operation clock frequency (ØAD) into 250 kHz or more in addition to a limit of Note 1. A case with sample & hold function turn AD operation clock frequency (ØAD) into 1MHz or more in addition to a limit of Note 1. Note 3: Connect AVCC pin to VCC pin and apply the same electric potential. Note 4: Specify a product of -40°C to 85°C to use it. RLADDER tCONV tCONV tSAMP 149 Mitsubishi microcomputers M16C / 30L Group Electrical characteristics SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Timing requirements (referenced to VCC = 3.3V, VSS = 0V, at Topr = – 20oC to 85oC / – 40oC to 85oC (*) unless otherwise specified) * : Specify a product of -40°C to 85°C to use it. Table 1.26.8. External clock input Symbol tc Parameter External clock input cycle time External clock input HIGH pulse width External clock input LOW pulse width External clock rise time External clock fall time tw(H) tw(L) tr tf Standard Min. Max. Unit ns 62.5 25 25 15 15 ns ns ns ns Table 1.26.9. Memory expansion and microprocessor modes Symbol Parameter tac1(RD-DB) Data input access time (no wait) tac2(RD-DB) Data input access time (with wait) Data input access time (when accessing multiplex bus area) Data input setup time RDY input setup time HOLD input setup time Data input hold time RDY input hold time HOLD input hold time HLDA output delay time tac3(RD-DB) tsu(DB-RD) tsu(RDY-BCLK ) tsu(HOLD-BCLK ) th(RD-DB) th(BCLK -RDY) th(BCLK-HOLD ) td(BCLK-HLDA ) Note: Calculated according to the BCLK frequency as follows: tac1(RD – DB) = 10 9 – 90 f(BCLK) X 2 tac2(RD – DB) = 3 X 10 – 90 f(BCLK) X 2 tac3(RD – DB) = 3 X 10 – 90 f(BCLK) X 2 [ns] 9 [ns] 9 150 [ns] Standard Max. Min. (Note) (Note) (Note) 50 Unit ns ns ns 100 ns ns ns 0 ns 0 ns 50 ns 0 40 ns Mitsubishi microcomputers M16C / 30L Group Electrical characteristics SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Timing requirements (referenced to VCC = 3.3V, VSS = 0V, at Topr = – 20oC to 85oC / – 40oC to 85oC (*) unless otherwise specified) * : Specify a product of –40°C to 85°C to use it. Table 1.26.10. Timer A input (counter input in event counter mode) Symbol tc(TA) Parameter TAiIN input cycle time tw(TAH) TAiIN input HIGH pulse width tw(TAL) TAiIN input LOW pulse width Standard Min. Max. 100 40 40 Unit ns ns ns Table 1.26.11. Timer A input (gating input in timer mode) Symbol tc(TA) tw(TAH) tw(TAL) Parameter TAiIN input cycle time Standard Min. Max. 400 200 200 TAiIN input HIGH pulse width TAiIN input LOW pulse width Unit ns ns ns Table 1.26.12. Timer A input (external trigger input in one-shot timer mode) Symbol Parameter Standard Max. Min. Unit tc(TA) TAiIN input cycle time 200 ns tw(TAH) tw(TAL) TAiIN input HIGH pulse width TAiIN input LOW pulse width 100 100 ns ns Table 1.26.13. Timer A input (external trigger input in pulse width modulation mode) Symbol tw(TAH) tw(TAL) Parameter TAiIN input HIGH pulse width TAiIN input LOW pulse width Standard Max. Min. 100 100 Unit ns ns Table 1.26.14. Timer A input (up/down input in event counter mode) tc(UP) TAiOUT input cycle time tw(UPH) TAiOUT input HIGH pulse width Standard Min. Max. 2000 1000 tw(UPL) tsu(UP-TIN) th(TIN-UP) TAiOUT input LOW pulse width TAiOUT input setup time TAiOUT input hold time 1000 400 400 Symbol Parameter Unit ns ns ns ns ns 151 Mitsubishi microcomputers M16C / 30L Group Electrical characteristics SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Timing requirements (referenced to VCC = 3.3V, VSS = 0V, at Topr = – 20oC to 85oC / – 40oC to 85oC (*) unless otherwise specified) * : Specify a product of –40°C to 85°C to use it. Table 1.26.15. Timer B input (counter input in event counter mode) Symbol Parameter Standard Min. Max. Unit tc(TB) TBiIN input cycle time (counted on one edge) 100 ns tw(TBH) TBiIN input HIGH pulse width (counted on one edge) 40 ns tw(TBL) TBiIN input LOW pulse width (counted on one edge) TBiIN input cycle time (counted on both edges) 40 200 ns tc(TB) tw(TBH) TBiIN input HIGH pulse width (counted on both edges) 80 ns tw(TBL) TBiIN input LOW pulse width (counted on both edges) 80 ns ns Table 1.26.16. Timer B input (pulse period measurement mode) Symbol Parameter Standard Min. Max. Unit tc(TB) TBiIN input cycle time 400 ns tw(TBH) tw(TBL) TBiIN input HIGH pulse width TBiIN input LOW pulse width 200 200 ns ns Table 1.26.17. Timer B input (pulse width measurement mode) Symbol Parameter Standard Min. Max. Unit tc(TB) TBiIN input cycle time 400 ns tw(TBH) TBiIN input HIGH pulse width 200 ns tw(TBL) TBiIN input LOW pulse width 200 ns Table 1.26.18. A-D trigger input Symbol tc(AD) tw(ADL) Parameter ADTRG input cycle time (trigger able minimum) ADTRG input LOW pulse width Standard Min. 1000 125 Max. Unit ns ns Table 1.26.19. Serial I/O Symbol Parameter Standard Min. Max. Unit tc(CK) CLKi input cycle time 300 ns tw(CKH) CLKi input HIGH pulse width 150 ns 150 tw(CKL) CLKi input LOW pulse width td(C-Q) TxDi output delay time th(C-Q) TxDi hold time tsu(D-C) RxDi input setup time RxDi input hold time th(C-D) ns 100 ns 0 50 ns 90 ns ns _______ Table 1.26.20. External interrupt INTi inputs Symbol 152 Parameter tw(INH) INTi input HIGH pulse width tw(INL) INTi input LOW pulse width Standard Min. 250 250 Max. Unit ns ns Mitsubishi microcomputers M16C / 30L Group Electrical characteristics SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Switching characteristics (referenced to VCC = 3.3V, VSS = 0V at Topr = – 20oC to 85oC / – 40oC to 85oC (Note 3), CM15 = “1” unless otherwise specified) Table 1.26.21. Memory expansion and microprocessor modes (with no wait) Symbol td(BCLK-AD) th(BCLK-AD) th(RD-AD) th(WR-AD) td(BCLK-CS) th(BCLK-CS) td(BCLK-ALE) th(BCLK-ALE) td(BCLK-RD) th(BCLK-RD) td(BCLK-WR) th(BCLK-WR) td(BCLK-DB) th(BCLK-DB) td(DB-WR) th(WR-DB) Measuring condition Parameter Address output delay time Address output hold time (BCLK standard) Address output hold time (RD standard) Address output hold time (WR standard) Chip select output delay time Chip select output hold time (BCLK standard) ALE signal output delay time ALE signal output hold time RD signal output delay time RD signal output hold time WR signal output delay time WR signal output hold time Data output delay time (BCLK standard) Data output hold time (BCLK standard) Data output delay time (WR standard) Data output hold time (WR standard)(Note2) Standard Min. Max. 50 4 0 0 50 4 40 Figure 1.26.1 –4 40 0 40 0 50 4 (Note1) Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 0 Note 1: Calculated according to the BCLK frequency as follows: td(DB – WR) = 10 9 – 50 f(BCLK) X 2 [ns] Note 2: This is standard value shows the timing when the output is off, and doesn't show hold time of data bus. Hold time of data bus is different by capacitor volume and pull-up (pull-down) resistance value. Hold time of data bus is expressed in t = –CR X ln (1 – VOL / VCC) by a circuit of the right figure. For example, when VOL = 0.2VCC, C = 30pF, R = 1kΩ, hold time of output “L” level is t = – 30pF X 1kΩ X ln (1 – 0.2VCC / VCC) = 6.7ns. R DBi C Note 3: Specify a product of -40°C to 85°C to use it. P0 P1 P2 30pF P3 P4 P5 P6 P7 P8 P9 P10 Figure 1.26.1. Port P0 to P10 measurement circuit 153 Mitsubishi microcomputers M16C / 30L Group Electrical characteristics SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Switching characteristics (referenced to VCC = 3.3V, VSS = 0V at Topr = – 20oC to 85oC / – 40oC to 85oC (Note 3), CM15 = “1” unless otherwise specified) Table 1.26.22. Memory expansion and microprocessor modes (when accessing external memory area with wait) Measuring condition Parameter Symbol Standard Min. Max. td(BCLK-AD) th(BCLK-AD) th(RD-AD) th(WR-AD) Address output delay time Address output hold time (BCLK standard) Address output hold time (RD standard) Address output hold time (WR standard) 4 0 0 td(BCLK-CS) th(BCLK-CS) Chip select output delay time Chip select output hold time (BCLK standard) 4 td(BCLK-ALE) th(BCLK-ALE) td(BCLK-RD) ALE signal output delay time ALE signal output hold time RD signal output delay time th(BCLK-RD) td(BCLK-WR) RD signal output hold time WR signal output delay time 0 th(BCLK-WR) td(BCLK-DB) WR signal output hold time Data output delay time (BCLK standard) 0 th(BCLK-DB) td(DB-WR) th(WR-DB) Data output hold time (BCLK standard) Data output delay time (WR standard) Data output hold time (WR standard)(Note2) 50 ns ns ns ns 50 40 ns ns ns ns ns 40 ns ns 50 ns ns 40 Figure 1.26.1 Unit –4 4 (Note1) ns ns ns 0 Note 1: Calculated according to the BCLK frequency as follows: td(DB – WR) = 10 9 f(BCLK) – 50 [ns] Note 2: This is standard value shows the timing when the output is off, and doesn't show hold time of data bus. Hold time of data bus is different by capacitor volume and pull-up (pull-down) resistance value. Hold time of data bus is expressed in t = –CR X ln (1 – VOL / VCC) by a circuit of the right figure. For example, when VOL = 0.2VCC, C = 30pF, R = 1kΩ, hold time of output “L” level is t = – 30pF X 1kΩ X ln (1 – 0.2VCC / VCC) = 6.7ns. Note 3: Specify a product of -40°C to 85°C to use it. 154 R DBi C Mitsubishi microcomputers M16C / 30L Group Electrical characteristics SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Switching characteristics (referenced to VCC = 3.3V, VSS = 0V at Topr = – 20oC to 85oC / – 40oC to 85oC (Note 2), CM15 = “1” unless otherwise specified) Table 1.26.23. Memory expansion and microprocessor modes (when accessing external memory area with wait, and select multiplexed bus) Symbol Measuring condition Parameter Standard Min. Max. 50 Unit td(BCLK-AD) Address output delay time th(BCLK-AD) th(RD-AD) Address output hold time (BCLK standard) Address output hold time (RD standard) (Note1) th(WR-AD) Address output hold time (WR standard) (Note1) td(BCLK-CS) th(BCLK-CS) th(RD-CS) Chip select output delay time Chip select output hold time (BCLK standard) Chip select output hold time (RD standard) th(WR-CS) td(BCLK-RD) th(BCLK-RD) Chip select output hold time (WR standard) RD signal output delay time RD signal output hold time td(BCLK-WR) th(BCLK-WR) td(BCLK-DB) WR signal output delay time WR signal output hold time Data output delay time (BCLK standard) th(BCLK-DB) td(DB-WR) Data output hold time (BCLK standard) Data output delay time (WR standard) th(WR-DB) td(BCLK-ALE) Data output hold time (WR standard) ALE signal output delay time (BCLK standard) th(BCLK-ALE) td(AD-ALE) ALE signal output hold time (BCLK standard) ALE signal output delay time (Address standard) (Note1) ns ns th(ALE-AD) td(AD-RD) ALE signal output hold time (Adderss standard) Post-address RD signal output delay time 30 0 ns ns td(AD-WR) tdZ(RD-AD) Post-address WR signal output delay time Address output floating start time 4 ns ns ns 50 4 (Note1) (Note1) 40 Figure 1.26.1 ns 0 40 0 50 4 ns ns ns ns ns ns ns ns ns ns ns (Note1) (Note1) 40 –4 0 8 ns ns ns ns Note 1: Calculated according to the BCLK frequency as follows: th(RD – AD) = 10 9 +0 f(BCLK) X 2 th(WR – AD) = 10 +0 f(BCLK) X 2 [ns] th(RD – CS) = 10 9 +0 f(BCLK) X 2 [ns] th(WR – CS) = 10 +0 f(BCLK) X 2 td(DB – WR) = 10 X 3 – 50 f(BCLK) X 2 th(WR – DB) = 10 +0 f(BCLK) X 2 [ns] td(AD – ALE) = 10 9 – 40 f(BCLK) X 2 [ns] [ns] 9 9 [ns] 9 [ns] 9 Note 2: Specify a product of -40°C to 85°C to use it. 155 Mitsubishi microcomputers M16C / 30L Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Timing tc(TA) tw(TAH) TAiIN input tw(TAL) tc(UP) tw(UPH) TAiOUT input tw(UPL) TAiOUT input (Up/down input) During event counter mode TAiIN input (When count on falling edge is selected) TAiIN input (When count on rising edge is selected) tsu(UP–TIN) th(TIN–UP) tc(TB) tw(TBH) TBiIN input tw(TBL) tc(AD) tw(ADL) ADTRG input tc(CK) tw(CKH) CLKi tw(CKL) th(C–Q) TxDi td(C–Q) tsu(D–C) RxDi tw(INL) INTi input Figure 1.26.2. Timing diagram (1) 156 tw(INH) th(C–D) Mitsubishi microcomputers M16C / 30L Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Timing Memory Expansion Mode and Microprocessor Mode (Valid only with wait) BCLK RD (Separate bus) WR, WRL, WRH (Separate bus) RD (Multiplexed bus) WR, WRL, WRH (Multiplexed bus) RDY input tsu(RDY–BCLK) th(BCLK–RDY) (Valid with or without wait) BCLK tsu(HOLD–BCLK) th(BCLK–HOLD) HOLD input HLDA output td(BCLK–HLDA) td(BCLK–HLDA) P0, P1, P2, P3, P4, P50 to P52 Hi–Z Note: The above pins are set to high-impedance regardless of the input level of the BYTE pin and bit (PM06) of processor mode register 0 selects the function of ports P40 to P43. Measuring conditions : • VCC=3.3V • Input timing voltage : Determined with VIL=0.66V, VIH=2.64V • Output timing voltage : Determined with VOL=1.65V, VOH=1.65V Figure 1.26.3. Timing diagram (2) 157 Mitsubishi microcomputers M16C / 30L Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Timing Memory Expansion Mode and Microprocessor Mode (With no wait) Read timing BCLK td(BCLK–CS) th(BCLK–CS) 4ns.min 50ns.max CSi th(RD–CS) tcyc 0ns.min td(BCLK–AD) th(BCLK–AD) 50ns.max ADi BHE ALE 4ns.min th(RD–AD) td(BCLK–ALE) th(BCLK–ALE) 0ns.min –4ns.min 40ns.max th(BCLK–RD) td(BCLK–RD) 40ns.max 0ns.min RD tac1(RD–DB) Hi–Z DB tSU(DB–RD) th(RD–DB) 50ns.min 0ns.min td(BCLK–CS) th(BCLK–CS) Write timing BCLK 4ns.min 50ns.max CSi th(WR–CS) tcyc 0ns.min td(BCLK–AD) th(BCLK-AD) 50ns.max ADi BHE 4ns.min td(BCLK–ALE) th(BCLK–ALE) th(WR–AD) 0ns.min –4ns.min ALE 40ns.max th(BCLK–WR) td(BCLK–WR) WR,WRL, WRH DB 0ns.min 40ns.max td(BCLK–DB) 50ns.max Hi-Z th(BCLK–DB) 4ns.min td(DB–WR) (tcyc/2–50)ns.min Figure 1.26.4. Timing diagram (3) 158 th(WR–DB) 0ns.min Mitsubishi microcomputers M16C / 30L Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Timing Memory Expansion Mode and Microprocessor Mode (When accessing external memory area with wait) Read timing BCLK th(BCLK–CS) td(BCLK–CS) 4ns.min 50ns.max CSi th(RD–CS) tcyc 0ns.min td(BCLK–AD) th(BCLK–AD) 50ns.max ADi BHE 4ns.min td(BCLK–ALE) 40ns.max th(BCLK–ALE) th(RD–AD) 0ns.min –4ns.min ALE th(BCLK–RD) td(BCLK–RD) 0ns.min 40ns.max RD tac2(RD–DB) Hi–Z DB tSU(DB–RD) th(RD–DB) 50ns.min 0ns.min Write timing BCLK td(BCLK–CS) th(BCLK–CS) 4ns.min 50ns.max CSi th(WR–CS) tcyc 0ns.min td(BCLK–AD) th(BCLK–AD) 50ns.max ADi BHE 4ns.min td(BCLK–ALE) th(WR–AD) 40ns.max th(BCLK–ALE) 0ns.min –4ns.min ALE td(BCLK–WR) 40ns.max WR,WRL, WRH td(BCLK–DB) 50ns.max th(BCLK–WR) 0ns.min th(BCLK–DB) 4ns.min DBi td(DB–WR) (tcyc–50)ns.min th(WR–DB) 0ns.min Measuring conditions : • VCC=3.3V • Input timing voltage : Determined with: VIL=0.52V, VIH=1.65V • Output timing voltage : Determined with: VOL=1.65V, VOH=1.65V Figure 1.26.5. Timing diagram (4) 159 Mitsubishi microcomputers M16C / 30L Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Timing Memory Expansion Mode and Microprocessor Mode (When accessing external memory area with wait, and select multiplexed bus) Read timing BCLK td(BCLK–CS) tcyc CSi td(AD–ALE) th(BCLK–CS) th(RD–CS) (tcyc/2)ns.min 50ns.max 4ns.min th(ALE–AD) (tcyc/2-40)ns.min 30ns.min ADi /DBi Address Data input tdz(RD–AD) 8ns.max Address th(RD–DB) tac3(RD–DB) tSU(DB–RD) 0ns.min 50ns.min td(AD–RD) 0ns.min td(BCLK–AD) th(BCLK–AD) 50ns.max ADi BHE ALE 4ns.min td(BCLK–ALE) th(BCLK–ALE) th(RD–AD) (tcyc/2)ns.min –4ns.min 40ns.max th(BCLK–RD) td(BCLK–RD) 0ns.min 40ns.max RD Write timing BCLK td(BCLK–CS) th(BCLK–CS) tcyc th(WR–CS) 50ns.max 4ns.min (tcyc/2)ns.min CSi th(BCLK–DB) td(BCLK–DB) 4ns.min 50ns.max ADi /DBi Data output Address td(DB–WR) (tcyc*3/2–50)ns.min td(AD–ALE) (tcyc/2–40)ns.min ADi BHE ALE Address th(WR–DB) (tcyc/2)ns.min td(BCLK–AD) th(BCLK–AD) 50ns.max 4ns.min td(BCLK–ALE) th(BCLK–ALE) –4ns.min td(AD–WR) 0ns.min 40ns.max td(BCLK–WR) 40ns.max WR,WRL, WRH th(WR–AD) (tcyc/2)ns.min th(BCLK–WR) 0ns.min Measuring conditions : • VCC=3.3V • Input timing voltage : Determined with VIL=0.52V, VIH=1.65V • Output timing voltage : Determined with VOL=1.65V, VOH=1.65V Figure 1.26.6. Timing diagram (5) 160 Mitsubishi microcomputers M16C / 30L Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Package Outline Package Outline MMP 100P6S-A EIAJ Package Code QFP100-P-1420-0.65 Plastic 100pin 14✕20mm body QFP Weight(g) 1.58 Lead Material Alloy 42 MD e JEDEC Code – 81 1 b2 100 ME HD D 80 I2 Recommended Mount Pad E 30 HE Symbol 51 50 A L1 c A2 b x A1 F e M L Detail F y MMP EIAJ Package Code LQFP100-P-1414-0.50 Plastic 100pin 14✕14mm body LQFP Weight(g) 0.63 JEDEC Code – Lead Material Cu Alloy MD e 100P6Q-A b2 I2 MD ME b2 HD ME 31 A A1 A2 b c D E e HD HE L L1 x y Dimension in Millimeters Min Nom Max 3.05 – – 0.1 0.2 0 2.8 – – 0.25 0.3 0.4 0.13 0.15 0.2 13.8 14.0 14.2 19.8 20.0 20.2 0.65 – – 16.5 16.8 17.1 22.5 22.8 23.1 0.4 0.6 0.8 1.4 – – – – 0.13 0.1 – – 0° 10° – – – 0.35 1.3 – – 14.6 – – – – 20.6 D 76 100 l2 Recommended Mount Pad 75 1 A A1 A2 b c D E e HD HE L L1 Lp HE E Symbol 51 25 26 50 A L1 F A3 M y L Detail F Lp c x A1 b A3 A2 e x y b2 I2 MD ME Dimension in Millimeters Min Nom Max 1.7 – – 0.1 0.2 0 1.4 – – 0.13 0.18 0.28 0.105 0.125 0.175 13.9 14.0 14.1 13.9 14.0 14.1 0.5 – – 15.8 16.0 16.2 15.8 16.0 16.2 0.3 0.5 0.7 1.0 – – 0.45 0.6 0.75 – 0.25 – – – 0.08 0.1 – – 0° 10° – 0.225 – – 0.9 – – 14.4 – – – – 14.4 161 Mitsubishi microcomputers M16C / 30L Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER SFR difference between M16C/62N and M16C/30L SFR difference between M16C/62N and M16C/30L Address Symbol 0005 PM1 000A PRCR M16C/62N M16C/30L Processor mode register 1 bit0:Reserved bit bit1:Nothing is assigned bit2:Nothing is assigned PM13:Internal reserved area expansion bit PM14:Memory area expantion bit PM15: bit6:Reserved bit PM17:Wait bit Processor mode register 1 bit0:Reserved bit bit1:Nothing is assigned bit2:Nothing is assigned bit3:Reserved bit bit4:Reserved bit bit5:Reserved bit bit6:Reserved bit PM17:Wait bit Protect register PRC0:Enables writing to system clock control registers 0 and 1 PRC1:Enables writing to processor mode registers 0 and 1 PRC2:Enables writing to port P9 direction register and SI/O control register bit3-bit7:Nothing is assigned Protect register PRC0:Enables writing to system clock control registers 0 and 1 PRC1:Enables writing to processor mode registers 0 and 1 PRC2:Enables writing to port P9 direction register bit3-bit7:Nothing is assigned 000B DBR Data bank register Reserved register 0030 SAR1 DMA1 source pointer Reserved register 0031 SAR1 DMA1 source pointer Reserved register 0032 SAR1 DMA1 source pointer Reserved register 0034 DAR1 DMA1 destination pointer Reserved register 0035 DAR1 DMA1 destination pointer Reserved register 0036 DAR1 DMA1 destination pointer Reserved register 0038 TCR1 DMA1 transfer counter Reserved register 0039 TCR1 DMA1 transfer counter Reserved register 003C DM1CON DMA1 control register Reserved register 0044 INT3IC INT3 interrupt control register Reserved register 0045 TB5IC Timer B5 interrupt control register Reserved register 0046 TB4IC Timer B4 interrupt control register Reserved register 0047 TB3IC Timer B3 interrupt control register Reserved register 0048 S4IC/INT5IC SI/O4,INT5 interrupt control register Reserved register 0049 S3IC/INT4IC SI/O3,INT4 interrupt control register Reserved register 004C DM1IC DMA1 interrupt control register Reserved register 0058 TA3IC Timer A3 interrupt control register Reserved register 0059 TA4IC Timer A4 interrupt control register Reserved register 005A TB0IC Timer B0 interrupt control register Reserved register 0340 TBSR Timer B3, 4, 5 count start flag Reserved register 0342 TA11 Timer A1-1 register Reserved register 0343 TA11 Timer A1-1 register Reserved register 0344 TA21 Timer A2-1 register Reserved register 0345 TA21 Timer A2-1 register Reserved register 0346 TA41 Timer A4-1 register Reserved register 0347 TA41 Timer A4-1 register Reserved register 0348 INVC0 Three-phase PWM control register 0 Reserved register 0349 INVC1 Three-phase PWM control register 1 Reserved register 034A IDB0 Three-phase output buffer register 0 Reserved register 034B IDB1 Three-phase output buffer register 1 Reserved register 034C DTT Dead time timer Reserved register 034D ICTB2 Timer B2 interrupt occurrence frequency set counter Reserved register 0350 TB3 Timer B3 register Reserved register 0351 TB3 Timer B3 register Reserved register 0352 TB4 Timer B4 register Reserved register 0353 TB4 Timer B4 register Reserved register 0354 TB5 Timer B5 register Reserved register 0355 TB5 Timer B5 register Reserved register 035B TB3MR Timer B3 mode register Reserved register 035C TB4MR Timer B4 mode register Reserved register 035D TB5MR Timer B5 mode register Reserved register Don't access a Reserved register. 162 Mitsubishi microcomputers M16C / 30L Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER SFR difference between M16C/62N and M16C/30L SFR difference between M16C/62N and M16C/30L Address 035F Symbol M16C/62N M16C/30L IFSR Interrupt cause select register IFSR0:INT0 interrupt polarity switching bit IFSR1:INT1 interrupt polarity switching bit IFSR2:INT2 interrupt polarity switching bit IFSR3:INT3 interrupt polarity switching bit IFSR4:INT4 interrupt polarity switching bit IFSR5:INT5 interrupt polarity switching bit IFSR6:Interrupt request cause select bit IFSR7:Interrupt request cause select bit Interrupt cause select register IFSR0:INT0 interrupt polarity switching bit IFSR1:INT1 interrupt polarity switching bit IFSR2:INT2 interrupt polarity switching bit bit3:Reserved bit bit4:Reserved bit bit5:Reserved bit bit6:Reserved bit bit7:Reserved bit 0360 S3TRR SI/O3 transmit/receive register Reserved register 0362 S3C SI/O3 control register Reserved register 0363 S3BRG SI/O3 bit rate generator Reserved register 0364 S4TRR SI/O4 transmit/receive register Reserved register 0366 S4C SI/O4 control register Reserved register 0367 S4BRG SI/O4 bit rate generator Reserved register 0380 TABSR Count start flag TA0S:Timer A0 count start flag TA1S:Timer A1 count start flag TA2S:Timer A2 count start flag TA3S:Timer A3 count start flag TA4S:Timer A4 count start flag TB0S:Timer B0 count start flag TB1S:Timer B1 count start flag TB2S:Timer B2 count start flag Count start flag TA0S:Timer A0 count start flag TA1S:Timer A1 count start flag TA2S:Timer A2 count start flag bit3:Reserved bit bit4:Reserved bit bit5:Reserved bit TB1S:Timer B1 count start flag TB2S:Timer B2 count start flag 0382 ONSF One-shot start flag TA0OS:Timer A0 one-shot start flag TA1OS:Timer A1 one-shot start flag TA2OS:Timer A2 one-shot start flag TA3OS:Timer A3 one-shot start flag TA4OS:Timer A4 one-shot start flag bit5:Nothing is assigned TA0TGL:Timer A0 event/trigger select bit TA0TGH: "00","01","10"and"11" can be chosen. One-shot start flag TA0OS:Timer A0 one-shot start flag TA1OS:Timer A1 one-shot start flag TA2OS:Timer A2 one-shot start flag bit3:Reserved bit bit3:Reserved bit bit5:Nothing is assigned TA0TGL:Timer A0 event/trigger select bit TA0TGH: "00 ","01"and"11" can be chosen. "10" can't be chosen. 0383 TRGSR Trigger select register TA1TGL:Timer A1 event/trigger select bit TA1TGH: "00","01","10"and"11" can be chosen. TA2TGL:Timer A2 event/trigger select bit TA2TGH: "00","01","10"and"11" can be chosen. Trigger select register TA1TGL:Timer A1 event/trigger select bit TA1TGH: "00","01","10"and"11" can be chosen. TA2TGL:Timer A2 event/trigger select bit TA2TGH: "00","01"and"10" can be chosen. "11" can't be chosen. bit4:Reserved bit bit5:Reserved bit bit6:Reserved bit bit7:Reserved bit TA3TGL:Timer A3 event/trigger select bit TA3TGH: "00","01","10"and"11" can be chosen. TA4TGL:Timer A4 event/trigger select bit TA4TGH: "00","01","10"and"11" can be chosen. 0384 UDF Up-down flag TA0UD:Timer A0 up/down flag TA1UD:Timer A1 up/down flag TA2UD:Timer A2 up/down flag TA3UD:Timer A3 up/down flag TA4UD:Timer A4 up/down flag TA2P:Timer A2 two-phase pulse signal processing select bit TA3P:Timer A3 two-phase pulse signal processing select bit TA4P:Timer A4 two-phase pulse signal processing select bit Up-down flag TA0UD:Timer A0 up/down flag TA1UD:Timer A1 up/down flag TA2UD:Timer A2 up/down flag bit3:Reserved bit bit4:Reserved bit TA2P:Timer A2 two-phase pulse signal processing select bit bit6:Reserved bit bit7:Reserved bit 038C TA3 Timer A3 Reserved register 038D TA3 Timer A3 Reserved register 038E TA4 Timer A4 Reserved register 038F TA4 Timer A4 Reserved register 0390 TB0 Timer B0 Reserved register 0391 TB0 Timer B0 Reserved register 0399 TA3MR Timer A3 mode register Reserved register 039A TA4MR Timer A4 mode register Reserved register 039B TB0MR Timer B0 mode register Reserved register Don't access a Reserved register. 163 Mitsubishi microcomputers M16C / 30L Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER SFR difference between M16C/62N and M16C/30L SFR difference between M16C/62N and M16C/30L Address 039C Symbol M16C/62N TB1MR M16C/30L Timer B1 mode register Event counter mode TMOD0:Operation mode select bit TMOD1: MR0:Count polarity select bit MR1: MR2:Nothing is assigned MR3:Invalid TCK1:Event clock select "0" and "1" can be chosen. Timer B1 mode register Event counter mode TMOD0:Operation mode select bit TMOD1: MR0:Count polarity select bit MR1: MR2:Nothing is assigned MR3:Invalid TCK1:Event clock select "0 " can be chosen. "1" can't be chosen. 03B4 FIDR Flash identification register Reserved register 03B7 03B8 FMR0 DM0SL Flash memory control register 0 Reserved register DMA0 request cause select register DMA0 request factors Falling edge of INT0 pin Software trigger Timer A0 Timer A1 Timer A2 Timer A3 Timer A4 two edges of INT0 pin Timer B0 Timer B1 Timer B2 Timer B3 Timer B4 Timer B5 UART0 transmit UART0 receive UART2 transmit UART2 receive UART1 transmit A-D conversion DMA0 request cause select register DMA0 request factors Falling edge of INT0 pin Software trigger Timer A0 Timer A1 Timer A2 two edges of INT0 pin Timer B1 Timer B2 UART0 transmit UART0 receive UART2 transmit UART2 receive UART1 transmit A-D conversion 03BA DM1SL DMA1 request cause select register Reserved register 03BC CRCD CRC data register Reserved register 03BD CRCIN CRC data register Reserved register 03BE CRCIN CRC input register Reserved register 03D4 ADCON2 A-D control register 2 SMP:A-D conversion method select bit ADGSL0:Analog input group select bit ADGSL1: bit3:Reserved bit bit4-bit7:Nothing is assigned A-D control register 2 SMP:A-D conversion method select bit bit1:Reserved bit bit2:Reserved bit bit3:Reserved bit bit4-bit7:Nothing is assigned 03D6 ADCON0 A-D control register 0 CH0:Analog input pin select bit CH1: CH2: MD0:A-D operation mode select bit 0 MD1: "00","01","10"and"11" can be chosen TRG:Trigger select bit ADST:A-D conversion start flag CKS0:Frequency select bit 0 A-D control register 0 CH0:Analog input pin select bit CH1: CH2: MD0:A-D operation mode select bit 0 MD1: "00 " can be chosen. "01","10"and"11" can't be chosen. TRG:Trigger select bit ADST:A-D conversion start flag CKS0:Frequency select bit 0 A-D control register 1 SCAN0:A-D sweep pin select bit SCAN1: MD2:A-D operation mode select bit 1 BITS:8/10-bit mode select bit CKS1:Frequency select bit 1 VCUT:Vref connect bit OPA0:External op-amp connection mode bit OPA1: A-D control register 1 bit0:Reserved bit bit1:Reserved bit bit2:Reserved bit BITS:8/10-bit mode select bit CKS1:Frequency select bit 1 VCUT:Vref connect bit OPA0:External op-amp connection mode bit OPA1: 03D7 ADCON1 03D8 DA0 D-A register 0 Reserved register 03DA DA1 D-A register 1 Reserved register 03DC DACON D-A control register Reserved register Don't access a Reserved register. 164 Keep safety first in your circuit designs! • Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap. • These materials are intended as a reference to assist our customers in the selection of the Mitsubishi semiconductor product best suited to the customer’s application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Mitsubishi Electric Corporation or a third party. Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement of any third-party’s rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 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