LC78615E CMOS LSI Compact Disc Player IC www.onsemi.com Overview The LC78615E integrates RF signal processor for CD-DA/R/RW, servo control, EFM signal processing and playback controller (Sequencer : 8-bit CPU). It is possible to make CD player system using with micro controller and driver IC’s with less components. PQFP64 14x14 / QIP64E Function RF signal processing for CD-DA/R/RW, servo control and EFM signal processing. Outputs CDDA, CDROM data Outputs CD-TEXT decoded data using the serial interface or Serial communication line with external main controller. CD playback system is realized with simple macro commands by the external controller because of the internal Sequencer (8-bit CPU). Operating Voltage : 3.3V Typical Operating Temperature : 40C to +85C Package : QIP64E(1414) ORDERING INFORMATION See detailed ordering and shipping information on page 24 of this data sheet. © Semiconductor Components Industries, LLC, 2015 January 2015 - Rev. 1 1 Publication Order Number : LC78615E/D LC78615E Detail of Functions [CD-DSP functions] < Playback functions> Playback mode : CLV playback / Jitter free playback (VCEC) Playback speed : Normal speed, double speed, quadruple speed (CLV playback / Jitter free playback) <RF processing block> RF system : AGC, CD-R and CD-R/W playback support, peak hold, bottom hold Error system : TE signal generation, FE signal generation Detection : Track count signal, Jitter, Defect (black, mirror) LASER power controller (APC) DC offset voltage cancellation <Servo control block> All servo systems as tracking, focus, sled and spindle are implemented with digital processing. Automatic adjustment functions : focus gain, focus bias, focus offset, tracking gain, tracking offset and tracking balance Shock detection / Interruption detection <CD signal processing block> EFM signal synchronization detection, protection and interpolation Error detection, correction (C1=double, C2=quadruple/double) Jitter margin ±19 frames <CD-TEXT processing block> Buffers CD-TEXT decoded data to the buffer memory. Starts buffering of CD-TEXT decoded data from desired ID3/ID4. [CD data processing functions] <CDDA data processing block> Interpolation Mute function(12dB, ∞) Digital attenuator De-emphasis filter <CDROM data processing block > CLV playback : Fixed normal speed or double speed Jitter free playback (VCEC) : Free speed within quadruple speed <Outputs format > Digital 3 lines output (LRCK, BCK, DATA) Supports various external audio data output format IIS (48fs), MSB First, Right-Justified, Left-Justified (32fs/48fs), 16 bit data length Slave mode Output DATA synchronized to external Clock input (LRCK/BCK) Digital output (S/PDIF, only CLV playback mode) [Internal Microcontroller functions] <Sequencer control> CD playback control Servo control, CD-TEXT processing, Digital data output control, etc. <Communication control between main controller> The SIO interface using CE,CL,DI,DO and BUSYB pins is available as communication format. External main controller can control this IC directly such as “stop oscillation” or “restart oscillation” or so on at the internal register open mode (REG_READY high condition). Even while the clock is stopped, some of general port can be controlled by host controller. <Peripheral interface block> GPIO port 15 ports maximum(Shared with other functionslerate.) <Program memory block> Mask-ROM type ROM Collect function is built in for the partial change of the program and Host controller can use this. <Others> Watch Dog Timer Notifies to outside from a pin or resets internally. Power management (Two kinds of sleep mode) (1) Only the clock for CPU core is operating and clocks for other blocks are stopping. (2) All clocks are stopping. [Others] <Internal power supply> 1.5V regulator for internal blocks www.onsemi.com 2 LC78615E Specifications Absolute Maximum Ratings at Ta=25°C, DVSS=AVSS=XVSS=VVSS1=0V Parameter Symbol Maximum supply voltage Input voltage 1 VDD max VIN1 Output voltage VOUT Allowable power dissipation Pd max Conditions Ratings DVDD, AVDD, XVDD, VVDD1 unit 0.3 to +3.95 V 0.3 to DVDD+0.3 V 0.3 to DVDD +0.3 V Ta ≤ 85°C 300 Mounted reference PCB (*) mW Operating temperature Topr 40 to +85 °C Storage temperature Tstg 40 to +125 °C (*) Reference PCB : 114.3mm×76.1mm×1.6mm, glass epoxy resin Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. Recommended Operating Conditions at Ta=40 to 85°C, DVSS=AVSS=XVSS=VVSS1=0V Parameter Supply voltage Symbol VDD Pin Name Type Conditions Ratings min typ 3.00 DVDD, AVDD, XVDD, VVDD1 unit max 3.60 V XIN, RESB, MODE,CE, CL, DI, DO CONT00, CONT01, CONT02, High-level input voltage VIH CONT03, CONT04, CONT05, CONT06, CONT07, CONT08, Schmitt 2.00 VDD V Schmitt 0.00 0.80 V CONT09, CONT10, CONT11, CONT12, CONT13, CONT14, XIN, RESB, TEST,CE, CL, DI, DO CONT00, CONT01, CONT02, Low-level input voltage VIL CONT03, CONT04, CONT05, CONT06, CONT07, CONT08, CONT09, CONT10, CONT11, CONT12, CONT13, CONT14, Crystal Oscillator Frequency External clock Input FX XIN, XOUT EXCK XIN Oscillator circuit 16.9344 Schmitt 16.9344 MHz 18.0 MHz Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability. www.onsemi.com 3 LC78615E Electrical Characteristics at Ta=40 to 85°C, VDD=3.0 to 3.6V, DVSS=AVSS=XVSS=VVSS1=0V Parameter Current drain Symbol IDD1 Pin Name Type Conditions Ratings min typ DVDD, AVDD, XVDD, VVDD1 40 RESB, MODE,CE, CL, DI, DO unit max 60 mA VIN=VDD CONT00, CONT01, CONT02, High-level input current IIH CONT03, CONT04, CONT05, CONT06, CONT07, CONT08, Built-in Schmitt CONT09, CONT10, CONT11, 10.00 Pull-down CONT12, CONT13, CONT14, /Pull-up resistor OFF RESB, TEST,CE, CL, DI, DO VIN=0.0V μA CONT00, CONT01, CONT02, Low-level input current IIL CONT03, CONT04, CONT05, CONT06, CONT07, CONT08, Built-in Schmitt CONT09, CONT10, CONT11, CONT12, CONT13, CONT14 Pull-down 10.00 /Pull-up resistor OFF DO, BUSYB, CONT00,CONT01, CONT02, High-level output voltage VOH(1) CONT03,CONT04, CONT05, CONT06,CONT07, CMOS IOH=2mA VDD0.6 CONT09,CONT10, CONT11, CONT12,CONT13, CONT14 VOH(2) CMOS IOH=4mA CMOS IOL=2mA CMOS PDOUT0,PDOUT1 IOL=4mA Hi-Z Out 10.00 10.00 DO Hi-Z Out 10.00 10.00 CONT08 V DO, BUSYB, CONT00,CONT01, CONT02, Low-level output VOL(1) voltage Output off-leakage current CONT03,CONT04, CONT05, CONT06,CONT07, 0.40 CONT09,CONT10, CONT11, CONT12,CONT13, CONT14 VOL(2) IOFF(1) IOFF(2) CONT08 μA CONT01,CONT02, CONT03, Built-in Pull-down resistor Built-in Pull-up CONT04,CONT05, CONT06, RPD CONT07,CONT08, CONT09, RPU CONT00 Charge pump IPDOH PDOUT1,PDOUT0 output current IPDOL PDOUT1,PDOUT0 resistor 50 100 200 kΩ 50 100 200 kΩ 35 50 65 65 50 35 CONT10,CONT11, CONT12, CONT13,CONT14 PCKIST=100kΩ Current value setting:1x μA (Notes) Connect and use the pull-up or the pull-down resister with the outside when you use serial communications because the terminal DO is 3- State output (initial state). Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. www.onsemi.com 4 LC78615E Package Dimensions unit : mm PQFP64 14x14 / QIP64E CASE 122BP ISSUE A 0.8±0.2 17.2±0.2 17.2±0.2 64 14.0±0.1 14.0±0.1 1 2 0.8 0.15 0.35 0.15 (2.7) 0 to 10° 0.1±0.1 3.0 MAX (1.0) 0.10 SOLDERING FOOTPRINT* GENERIC MARKING DIAGRAM* 16.30 XXXXXXXX YMDDD 16.30 (Unit: mm) XXXXX = Specific Device Code Y = Year M = Month DDD = Additional Traceability Data *This information is generic. Please refer to device data sheet for actual part marking. 0.50 may or may not be present. 1.30 0.80 NOTE: The measurements are not to guarantee but for reference only. *For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. www.onsemi.com 5 LC78615E 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 SLCO XVDD XIN XOUT XVSS DVDD DVDD15 MODE CONT14 CONT13 CONT12 CONT11 CONT10 CONT09 CONT08 BUSYB Pin Assignment 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 LC78615 6DXX EFMIN RFOUT LPF PHLPF AIN CIN BIN DIN SLCISET RFMON VREF JITTC EIN FIN TE TEIN www.onsemi.com 6 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 RESB DO DI CL CE CONT07 CONT06 CONT05 CONT04 CONT03 CONT02 CONT01 CONT00 TEST DVSS DVDD LC78615E Pin Description Pin No. Pin name I/O State when “Reset” 1 EFMIN AI Input 2 RFOUT AO Undefined Function RF signal input RF signal output 3 LPF AO Undefined RF signal DC level detection low-pass filter capacitor connection 4 PHLPF AO Undefined Defect detection low-pass filter capacitor connection 5 AIN AI Input A signal input 6 CIN AI Input C signal input 7 BIN AI Input B signal input 8 DIN AI Input D signal input SLCO output current setting resistor connection 9 SLCISET AI Input 10 RFMON AO Undefined 11 VREF AO AVDD/2 12 JITTC AO Undefined 13 EIN AI Input E signal input 14 FIN AI Input F signal input 15 TE AO Undefined 16 TEIN AI Input 17 AVSS 18 AVDD 19 LDD 20 LDS 21 FDO IC internal analog signal monitor Reference voltage output for RF Jitter detection capacitor connection TE signal output TE signal input used for TES signal generation Analog system ground. This pin must be connected to the 0V level. AO Undefined Laser power control signal output AI Input Laser power detection signal input AO AVDD/2 Analog system power supply Focus control signal output 22 TDO AO AVDD/2 Tracking control signal output 23 SLDO AO AVDD/2 Sled control signal output 24 SPDO AO AVDD/2 Spindle control signal output 25 VVSS1 26 PDOUT1 AO Undefined EFMPLL charge pump output 1 27 PDOUT0 AO Undefined EFMPLL charge pump output 0 28 PCKIST AI Input 29 VVDD1 EFMPLL power supply 30 NC NC Pin (Open) 31 NC NC Pin (Open) EFMPLL ground. This pin must be connected to the 0V level. EFMPLL charge pump current setting resistor connection pin 32 DVDD15 AO High 33 DVDD Digital system power supply 34 DVSS Digital system ground. This pin must be connected to the 0V level. 35 TEST I Input 36 CONT00 I/O Input(High) 37 CONT01 I/O Input(Low) 38 CONT02 I/O Input(Low) 39 CONT03 I/O Input(Low) Capacitor connection pin for internal regulator Test input. This pin must be connected to the 0V level. General purpose I/O port with pull up resistor SBCK clock input for CD subcode data (exclusive with CONT07 and CONT11) General purpose I/O port with pull down resistor Block synchronization signal (SBSY) output for CD subcode General purpose I/O port with pull down resistor Frame synchronization signal (SFSY) output for CD subcode General purpose I/O port with pull down resistor PW data output in CD subcode Watch Dog Timer state monitor output General purpose I/O port with pull down resistor LR clock output for CD data 40 CONT04 I/O Input(Low) LR clock input for CD data (exclusive with CONT09 and CONT12) Block synchronization signal (SBSY) output for CD subcode Data request signal input for CD-TEXT interface (exclusive with CONT08, CONT09 and CONT12) www.onsemi.com 7 LC78615E Pin Pin name No. I/O State when Function “Reset” General purpose I/O port with pull down resistor Bit clock output for CD data 41 CONT05 I/O Input(Low) Bit clock input for CD data (exclusive with CONT10 and CONT13) Frame synchronization signal (SFSY) output for CD subcode Clock input/output for CD-TEXT interface (exclusive with CONT10 and CONT13) General purpose I/O port with pull down resistor 42 CONT06 I/O Input(Low) Serial data output for CD data PW data output in CD subcode Serial data output for CD-TEXT interface General purpose I/O port with pull down resistor C2 error flag output for CD data 43 CONT07 I/O Input(Low) Digital audio output<S/PDIF> SBCK clock input for CD subcode data (exclusive with CONT00 and CONT11) Watch Dog Timer state monitor output 44 CE I Input 45 CL I Input 46 DI I Input 47 DO O Low 48 RESB I Input 49 BUSYB O Low Host I/F Enable signal input for serial communication Host I/F Data transfer clock input for serial communication Host I/F Data input for serial communication Host I/F Data output for serial communication IC reset input.(Low active) This pin must be set low once after power is first applied. Host I/F BUSYB output(High : Communication available) General purpose I/O port with pull down resistor LR clock output for CD data 50 CONT08 I/O Input(Low) Digital audio output<S/PDIF> FS384 clock input/output for Audio DAC Data request signal input for CD-TEXT interface (exclusive with CONT04, CONT09 and CONT12) General purpose I/O port with pull down resistor LR clock output for CD data 51 CONT09 I/O Input(Low) LR clock input for CD data (exclusive with CONT04 and CONT12) Frame synchronization signal (SFSY) output for CD subcode Data request signal input for CD-TEXT interface (exclusive with CONT04, CONT08 and CONT12) General purpose I/O port with pull down resistor Bit clock output for CD data 52 CONT10 I/O Input(Low) Bit clock input for CD data(exclusive with CONT05 and CONT13) PW data output in CD subcode Clock input/output for CD-TEXT interface (exclusive with CONT05 and CONT13) General purpose I/O port with pull down resistor Serial data output for CD data 53 CONT11 I/O Input(Low) Digital audio output<S/PDIF> SBCK clock input for CD subcode data (exclusive with CONT00 and CONT07) Serial data output for CD-TEXT interface www.onsemi.com 8 LC78615E Pin No. Pin name I/O State when Function “Reset” General purpose I/O port with pull down resistor LR clock input for CD data (exclusive with CONT04 and CONT09) 54 CONT12 I/O Input(Low) C2 error flag output for CD data Block synchronization signal (SBSY) output for CD subcode Data request signal input for CD-TEXT interface (exclusive with CONT04, CONT08 and CONT09) General purpose I/O port with pull down resistor Bit clock output for CD data 55 CONT13 I/O Input(Low) Bit clock input for CD data(exclusive with CONT05 and CONT10) Frame synchronization signal (SFSY) output for CD subcode Clock input/output for CD-TEXT interface (exclusive with CONT05 and CONT10) General purpose I/O port with pull down resistor Serial data output for CD data 56 CONT14 I/O Input(Low) PW data output in CD subcode Serial data output for CD-TEXT interface Watch Dog Timer state monitor output 57 MODE I Input 58 DVDD15 LSI mode set input. This pin must be connected to the DVDD level. AO High Capacitor connection pin for internal regulator 59 DVDD 60 XVSS 61 XOUT O Oscillation 16.9344MHz oscillator connection 16.9344MHz oscillator connection 62 XIN I Oscillation 63 XVDD 64 SLCO AO Undefined Digital system power supply Oscillator ground. This pin must be connected to the 0V level. Oscillator power supply Slice Level Control output <Notes> (1) For Unused pins : The unused input pins must be connected to the GND(0V) level if there is no individual note in the above table. The unused output pins must be left open(No connection) if there is no individual note in the above table. The unused input/output pins must be connected to the GND(0V) or power supply pin for I/O block with internal pull down/up resistor OFF or be left open with internal pull down/up resistor ON when input pin mode or must be left open(No connection ) when output pin mode if there is no individual note in the above table. When you connect an I/O pin which is an input pin without internal pull-down/up resistor at reset mode to the GND or power supply level, we recommend you to use pull-down resistor or pull-up resistor individually as fail-safe. (2) For Power supply pins : Same voltage level must be supplied to DVDD, AVDD, XVDD and VVDD1 power supply pins. (3) For “Reset” condition : This IC is not reset only by making the RESB pin “Low”. Refer to “4. Power on and Reset control” for detail of “Reset” condition. www.onsemi.com 9 LC78615E Block Diagram CD RF Signal Processor AD/DA CD PLL CD Servo Controller Buffer RAM CD-TEXT Decoder CD EFM/ECC Decoder 8bit-CPU Core BUFRAM I/F DATA Trans Data Output Control CDROM Data CDDA Data DeEMPHASIS/ MUTE/ATT DOUT(S/PDIF) Work RAM Program ROM WatchDog Timer Host-I/F (SIO) Interrupt X'tal (16.9344MHz) PORT Control Regulator 1.5V 3.3V www.onsemi.com 10 LC78615E Power on and Reset control Attention when power on The RESB pin must be set to “Low” level when power is first supplied. At that time, it is necessary to input a stable clock to the XIN pin. You may input the voltage of VDD or less to each input terminal when the power supply is off. 3.3V Power supply RESB tRESW2 tRESW1 During normal operation (Oscillation clock is valid) Power ON stage Parameter Symbol Min Typ Max unit Reset time(Power on) tRESW1 20 ms Reset time(Normal) (*1) tRESW2 1 ms *1 : The oscillation must be stable during tRESW2. When the XIN clock has been stopped by the command etc. , the specification of tRESW2 could be larger than the value shown above, because it takes time that the XIN oscillator becomes stable. www.onsemi.com 11 LC78615E Host interface The four wires serial interface is available as the data transmission protocol between this LSI and Host controller. It is able to know whether the internal sequencer could receive the command or not by the BUSYB pin. BUSYB Low High Command Acceptance situation All address command access disable All address command access disable except A0h to A7h addresses BUSYB becomes Low if the A5h address command is transmitted. All address command except A0h to A7h addresses will be ignored. By setting REG_READY command to High, internal register open mode is available. In this mode, Host controller can access to the all address command (internal sequencer can’t control the CDDSP block). When the A5h address command is transmitted, REG_READY command and BUSYB pin is set to Low, and internal register open mode become finish. Command Transfer Timing 1 : (Normal mode: BUSYB = "H" → "L") CE Tcsu Twl CL DI Trsu BUSYB Tchd Twh Twsu Twhd Trdyoff Trdyon Command Transfer Timing 2 : (Internal register open mode: BUSYB = "H") CE Trsu BUSYB Tce Twl CL DI Tchd Tcsu Twh Twsu Twhd www.onsemi.com 12 LC78615E Command Receive Timing 1 : (Normal mode : BUSYB = "H" ) Tce Tcsu Tchd CE Twl CL Twh DI Ton Trhd DO Toff Trac BUSYB Read Setting Cycle (Write Timing) Read Access Cycle (*1) *1. High level must be supplied to the DI pin during Read Access Cycle. Command Receive Timing 2 : (Internal register open mode: BUSYB = "H") Tcsu Tce Tchd CE Twl CL Twh DI Ton Trhd DO Toff Trac BUSYB Read Access Cycle (*1) Read Setting Cycle (Write Timing) *1. High level must be supplied to the DI pin during Read Access Cycle. Parameter Setup time for READY Setup time for CE Hold time for CE Setup time for DI Hold time for DI High level clock pulse width Low level clock pulse width Access time for read data Symbol Trsu Tcsu Tchd Twsu Twhd Twh Twl Trac Hold time for read data Trhd Turn On Time for DO Ton Turn Off Time for DO Toff Command transfer time Tce Turn Off Time for READY Trdyoff Turn On Time for READY(*1) Trdyon *1. Never communicate in this period. Pin Names CE, BUSYB CE, CL CE, CL DI, CL DI, CL CL CL CL, DO Min 60 400 200 100 100 200 200 0 CL, DO 120 CE, DO CE, DO CE CE, BUSYB CE, BUSYB www.onsemi.com 13 150 0 1 0 0.175 Typ Max unit ns 100 300 200 50000 μs ns μs LC78615E CD data output function Two modes can be available for CD data output. (1) Normal mode In this mode, output signals are LRCK, BCK and DATA. CLV or Jitter-Free(VCEC) playback is supported. When CDDA playback, depending on the specification of Audio DAC, FS384 clock output is also available . (2) Slave mode In ths mode, output signal is DATA, and input signals are LRCK, BCK. The DATA output is synchronized to input clocks (LRCK,BCK). It is enable to output CD data synchronized to Audio DAC without connecting FS384clock. This mode is only available for CD normal playback, and LRCK frequency must be 44.1kHz. 1. Normal mode Available format Mode : IIS, MSB First Right-Justified, MSB First Left-Justified Slot Length : 32fs, 48fs Data Length : 16-bit Used Pin LRCKO BCKO DATAO : CONT04, CONT08, CONT09 : CONT05, CONT10, CONT13 : CONT06, CONT11, CONT14 Note When CDDA Playback, FS384 can be optionally output from CONT08. The signal input from XIN pin is output as FS384 signal. CD Data output timing LRCKO tABK tABK tBLP tBLA 1/fABCK BCKO DATAO tBDS tBDH Parameter Symbol Pin Names Min Typ Max Bit clock Frequency fABCKO BCKO 10.5 Bit clock "H" level width tABKOH BCKO 47.5 Bit clock "L" level width tABKOL BCKO 47.5 BCKO,LRCKO Setup time for LRCK tBLP 0 15 (based on BCK negedge) Hold time for LRCK BCKO,LRCKO tBLA 0 15 (based on BCK negedge) Setup time for DATA output tBDS BCKO,DATAO 30 Hold time for DATA output tBDH BCKO,DATAO 30 * In case of quadruple speed playback, and setting the output format as 48fs slot length. www.onsemi.com 14 unit MHz ns ns ns ns ns ns LC78615E 2. Slave mode In this mode, LRCK (Fs=44.1kHz) and BCK are input from external device, and output data is synchronized with input clocks. So, it is possible to play CDDA without FS384 or SRC (Sampling Rate Converter). Available format Mode : IIS, MSB First Right-Justified, MSB First Left-Justified Slot Length : 32fs, 48fs, 64fs Data Length : 16-bit Used Pin LRCKI BCKI DATAO : CONT04, CONT09, CONT12 : CONT05, CONT10, CONT13 : CONT06, CONT11, CONT14 Slave mode data timing 1/fLRCKI tLRIL tLRIH LRCKI (In) tABKI tABKI tBLIH tBLIS BCKI (In) 1/fABCK DATAO (Out) tDOS tDOH Parameter LRCK frequency LRCK "H" level width LRCK "L" level width Symbol fLRCKI tLRIH tLRIL Bit clock frequency fABCKI Bit clock "H" level width tABKIH Bit clock "L" level width tABKIL Pin Names LRCKI LRCKI LRCKI BCKI BCKI BCKI Min 10.3 10.3 160 160 Setup time for LRCK input tBRIS LRCKI,BCKI Hold time for LRCK input tBLIH LRCKI,BCKI Setup time for DATA output tDOS DATAO,BCKI Hold time for DATA output tDOH DATAO,BCKI *1: In case of setting the output format as 48fs slot length. www.onsemi.com 15 50 50 50 50 Typ 44.1 11.34 11.34 2.1168 *1 236.2 *1 236.2 *1 Max 48.5 3.10 unit kHz s s MHz ns ns ns ns ns ns LC78615E CD Subcode Data Output function It is possible to output the subcode data (PW data) according to the terminal setting when CD playback mode. The PW data are output at the rising edge of SBCK signal when the SBCK clock signal is input. <Note> The CD-TEXT function and the CD Subcode data output function are exclusive functions. It is impossible to use those two functions simultaneously. Used pins SBSY (Subcode Block Synchronous signal) SFSY (Subcode Frame Synchronous signal) PW (Subcode PW data) SBCK (Subcode data read clock) : CONT01, CONT04, CONT12 : CONT02, CONT05, CONT09, CONT13 : CONT03, CONT06, CONT10, CONT14 : CONT00, CONT07, CONT11 Subcode Data Output timing tSBF SFSY (Output) tSBE tSBCK SBCK (Input) PW (Output) tSBCKL P Q S R T U V W "0" P tSBRDL Subcode Block Synchronous Signal Output timing tSBBC SBSY (Output) tSBBH Parameter Symbol Pin Names Subcode Read Cycle time tSBFC SFSY Subcode Read Enable time SBCK clock "H" level width SBCK clock "L" level width PW data output Delay time tSBE tSBCKH tSBCKL tSBRDL SFSY, SBCK SBCK SBCK SBCK, PW SBSY output Cycle time tSBBC SBSY SBSY "H" level width tSBBH SBSY Min Typ 136 *1 400 250 250 0 Max s 100 13.3 *2 272 *2 unit ns ns ns ns ms s <Notes> 1. When playback the CD at the normal speed (CLV playback). This value changes depending on the playback speed. 2. When playback the CD at the normal speed (CLV playback). The SBSY signal becomes high level during the first two subcoding symbols (S0 and S1) are asserted. www.onsemi.com 16 LC78615E CD-TEXT data output function There are two methods to output CD-TEXT data from the Buffer RAM in this IC. (1) Command Communication output mode Outputs the CD-TEXT data using the command communication protocol between this IC and external host controller. (2) Hand shake output mode using with hardware interface function A. Inputs data request signal and transfer clock then outputs CD-TEXT data The CD-TEXT data(CTDATO) will be output synchronizing with the CTCKI clock when the CTCKI clock is input after the CD-TEXT data request signal is input(CTREQI="H"). B. Inputs data request signal then outputs transfer clock and CD-TEXT data The CTCKO and CTDATO synchronized with CTCKO will be output after the CD-TEXT data request signal is input (CTREQI= "H"). In both operation modes (1) and (2), the data transfer unit bit length is 2 Bytes (16 bits). * The CD-TEXT function and CD subcode data output function are exclusive each other, and then those functions can not be used simultaneously. CD-TEXT data output Timing 1 : CTCK input mode CTREQI (Input) CTCKI (Input) CTDATO (Output) tCTCK 1/fSCI tCTC KL tCTC tCTDO <Supplement> Both modes below are available. A. CTCKI="L" start mode The CTDATO is output synchronized with the rising edge of the CTCKI clock. The host controller should latch the CTDATO data at the falling edge of the CTCKI clock. B. CTCKI="H" start mode The CTDATO is output synchronized with the falling edge of the CTCKI clock. The host controller should latch the CTDATO data at the rising edge of the CTCKI clock. * The relationship between the signals in figure 8-1 and the pins is shown below. CTREQI : CONT04, CONT08, CONT09, CONT12 CTCKI : CONT05, CONT10, CONT13 CTDATO : CONT06, CONT11, CONT14 Parameter CTCKI clock Frequency Symbol fSCI Pin Names Min Typ Max CTCKI 1.25 CTREQI, CTCKI clock input start time tCTCKIN 1000 CTCKI CTCKI clock "H" level width tCTCKH CTCKI 400 CTCKI clock "L" level width tCTCKL CTCKI 400 CTCKI, 250 CTDATO output Delay time tCTDODL1 CTDATO Note : The above figure shows the case of mode A that the clock starts low level (CTCKI="L"). The timings are same when the clock starts high level (CTCKI="H"). www.onsemi.com 17 unit MHz ns ns ns ns LC78615E CD-TEXT data output Timing 2 : CTCK output mode tCTOF CTREQI (Input) tCTOA tCTCOtCTCO 1/fSC CTCKO (Output) CTDATO (Output) tCTDO <Supplement> The CTCKO will be output starting with the high level then the CTDATO will be output synchronized with the falling edge of the CTCKO clock. The host controller should latch the CTDATO data at the rising edge of the CTCKO clock. * The relationship between the signals in figure 8-2 and the pins is shown below. CTREQI : CONT04, CONT08, CONT09, CONT12 CTCKO : CONT05, CONT10, CONT13 CTDATO : CONT06, CONT11, CONT14 Parameter CTCKO clock Frequency Symbol fSCO CD-TEXT data output start time tCTOAT CD-TEXT data output stop time tCTOFF CTCKO clock "H" level width CTCKO clock "L" level width tCTCOH tCTCOL CTDATO output Delay time tCTDODL2 Pin Names CTCKO CTREQI, CTCKO CTREQI, CTCKO CTCKO CTCKO CTDATO, CTCKO www.onsemi.com 18 Min 1.05 400 400 0 Typ Max 4.2 (1/fSCO) ×32 (1/fSCO) ×32 100 100 50 unit MHz ns ns ns ns ns LC78615E Internal Voltage Regulator at Ta=40°C to 85°C, DVSS=AVSS=XVSS=VVSS1=0V Parameter Output Voltage Load current Symbol DVDD15 Iope Condition VDD=3.0 to 3.6V VDD=3.3V Min 1.35 Typ 1.50 Max 1.65 50 unit V mA Example circuit for Regulator * Same circuit need to be mounted both for two regulator pins. (No.32 and No.58) LC78615 DVDD DVSS * C1 is the capacitor to avoid oscillation. This capacitor value must be low ESR and greater than 30F in the range of the operating temperature. Because there is a possibility of the oscillation when the capacity value changes by the temperature change etc. (The recommended value is 100F. ) 100F DVDD15 C1 A/D, D/A converter Characteristics for servo at Ta=40°C to 85°C, VDD=3.3V, DVSS=AVSS=XVSS=VVSS1=0V Parameter Symbol Min Typ Max Resolution Res 8 4/5V Maximum input/output range Vaio1 DD 1/5VDD Minimum input/output range Vaio2 unit bit V V Oscillator Example circuit for Oscillator LC78615 XVDD XIN Rd1 XOUT XVSS C1 C1 XIN/XOUT : 16.9344MHz For System clock of internal micro controller, CD control and Audio control Recommended Oscillators Murata Manufacturing Co., Ltd. SMD : CSTCE16M9V53-R0 <Built-in C> : CSTCW16M9X51008-R0 <Built-in C> Lead : CSTLS16M9X53-B0 <Built-in C> <Notes> Because the characteristics of oscillator could be changed according to the circuit board, ask evaluation with the individual original circuit board to the oscillator maker. Concerning about internal circuit for XIN/XOUT, refer to the "Analog Pin Internal Equivalent Circuits" section. The XIN pin can also be supplied from an external clock instead of connecting the oscillator. In this case, XOUT pin must be left open. www.onsemi.com 19 LC78615E Analog Pin Internal Equivalent Circuits Pin Name (Pin No.) Equivalent Circuit AVDD EFMIN (1) AVSS AVDD AVDD RFOUT (2) AVSS AVSS AVDD AVDD LPF (3) AVSS AVSS AVDD PHLPF (4) AVSS AIN (5) CIN (6) BIN (7) DIN (8) AVDD SLCISET (9) AVSS AVDD AVDD RFMON (10) AVSS www.onsemi.com 20 AVSS LC78615E Pin Name (Pin No.) Equivalent Circuit AVDD AVDD VREF (11) AVSS AVSS AVDD JITTC (12) AVSS EIN (13) FIN (14) AVDD AVDD TE (15) AVSS AVSS AVDD TEIN (16) AVSS AVDD AVDD AVDD LDD (19) AVSS AVSS AVDD LDS (20) AVSS www.onsemi.com 21 LC78615E Pin Name (Pin No.) Equivalent Circuit AVDD AVDD FDO (21) TDO (22) SLDO (23) SPDO (24) AVSS AVSS VVDD1 VVDD1 PDOUT1 (26) VVSS1 VVSS1 VVDD1 VVDD1 PDOUT0 (27) VVSS1 VVSS1 VVDD1 PCKIST (28) VVSS1 XVDD XOUT (61) XIN (62) VVSS1 XVDD XIN XOUT XVSS AVDD XVSS AVDD SLCO (64) AVSS www.onsemi.com 22 AVSS LC78615E Application Circuit Example Data Out (LRCK,BCK,DATA) VDD To μ-COM 48 47 46 45 44 43 42 41 40 39 38 37 36 35 33 32 CD SubCode-I/F ) ) AVSS AVDD LDD LDS FDO TDO SLDO SPDO VSS1 PDOUT1 PDOUT0 PCKIST VVDD1 NC NC DVDD15 Vref (Reference voltage) E ( F ( RESB DO DI CL CE CONT07 CONT06 CONT05 CONT04 CONT03 CONT02 CONT01 CONT00 TEST DVSS DVDD 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 To PICKUP ) ) ) ) LC78615 ( ( ( ( EFMIN RFOUT LPF PHLPF AIN CIN BIN DIN SLCISET RFMON VREF JITTC EIN FIN TE TEIN 6DXX A B C D 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 SLCO XVDD XIN XOUT XVSS DVDD DVDD15 MODE CONT14 CONT13 CONT12 CONT11 CONT10 CONT09 CONT08 BUSYB 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 16.9344MHz LD VREF FDO TDO SLDO SPDO MD GND To Driver * This sample circuit is only for CD servo block and each PLL block. The value of each component needs to be adjusted under the target conditions. The circuit for CD servo shown above could be changed depending on the CD mechanism used. * In this sample circuit, CONT00 - CONT14 are used as 3lines outputs (LRCK, BCK, DATA) and CD-Subcode-I/F (SBCK,SBSY,SFSY,PW). For CONT00 - CONT14, use the appropriate pin function according to specifications. www.onsemi.com 23 LC78615E ORDERING INFORMATION Device LC78615E-01US-H Package PQFP64 14x14 / QIP64E (Pb-Free / Halogen Free) Shipping (Qty / Packing) 300 / Tray Foam ON Semiconductor and the ON logo are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries. SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf . 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