LC78616PE Advance Information www.onsemi.com CMOS LSI Compact Disc Player IC Overview The LC78616PE integrates RF signal processor for CD-DA/R/RW, servo control, EFM signal processing, anti-shock processing and playback controller (Sequencer : 8-bit CPU). It is possible to make CD player system using with micro controller, driver and SDRAM IC’s with less components. PQFP100 14x20 / QIP100E Features RF signal processing for CD-DA/R/RW, servo control and EFM signal processing Outputs CDDA, CDROM data Maximum approximately 40 seconds shock protection by shock proof function with external 64M-bit SDRAM CD-TEXT decoded data are stored in external SDRAM. CD playback system is realized with simple macro commands by the external controller because of the internal Sequencer (8-bit CPU). Operating Voltage : 3.3V Typical Operating Temperature : 40C to +85C Package : QIP100E(1420) This document contains information on a new product. Specifications and information herein are subject to change without notice. © Semiconductor Components Industries, LLC, 2015 January 2015 - Rev. P0 1 Publication Order Number : LC78616PE/D LC78616PE Detail of Functions [CD-DSP functions] < Playback functions> Playback mode : CLV playback / Jitter free playback (VCEC) Playback speed : Normal speed, double speed, quadruple speed (CLV playback / Jitter free playback) <RF processing block> RF system : AGC, CD-R and CD-R/W playback support, peak hold, bottom hold Error system : TE signal generation, FE signal generation Detection : Track count signal, Jitter, Defect (black, mirror) LASER power controller (APC) DC offset voltage cancellation <Servo control block> All servo systems as tracking, focus, sled and spindle are implemented with digital processing. Automatic adjustment functions : focus gain, focus bias, focus offset, tracking gain, tracking offset and tracking balance Shock detection / Interruption detection <CD signal processing block> EFM signal synchronization detection, protection and interpolation Error detection, correction (C1=double, C2=quadruple/double) Jitter margin ±19 frames <CD-TEXT processing block> Buffers CD-TEXT decoded data to the buffer memory. Starts buffering of CD-TEXT decoded data from desired ID3/ID4. <Shock proof processing block> Shock proof processing using with external 16M-bit or 64M-bit Memory Approximately 10sec. with 16M-bit or 40sec. with 64M-bit [CD data processing functions] <CDDA data processing block> Interpolation Mute function (12dB, ∞) Digital attenuator De-emphasis filter <CDROM data processing block> CLV playback : Fixed normal speed or double speed Jitter free playback (VCEC) : Free speed within quadruple speed *CDROM Data is not buffering to SDRAM and output directly <Outputs format> Digital 3 lines output(LRCK,BCK,DATA) Supports various external audio data output format IIS (48fs), MSB First, Right-Justified, Left-Justified (32fs/48fs), 16 bit data length Slave mode Output DATA synchronized to external Clock input (LRCK and BCK) Digital output (S/PDIF, only CLV playback mode) [Internal Microcontroller functions] <Sequencer control> CD playback control Servo control, CD-TEXT processing, Digital data output control, etc. <Communication control between main controller> The SIO interface using CE, CL, DI, DO and BUSYB pins is available as communication format. External main controller can control this IC directly such as “stop oscillation” or “restart oscillation” or so on at the internal register open mode (REG_READY high condition). Even while the oscillation is stopped, some of general port can be controlled by host controller. <Peripheral interface block> GPIO port 8 ports maximum (Shared with other functionslerate.) <Program memory block> Mask-ROM type ROM Collect function is built in for the partial change of the program and Host controller can use this. <Others> Watch Dog Timer Notifies to outside from a pin or resets internally. Power management (Two kinds of sleep mode) (1) Only the clock for CPU core is operating and clocks for other blocks are stopping. (2) All clocks are stopping. [Others] <Internal power supply> 1.5V regulator for internal blocks www.onsemi.com 2 LC78616PE Specifications Absolute Maximum Ratings at Ta=25°C, DVSS=AVSS=XVSS=VVSS1=0V Parameter Symbol Maximum supply voltage VDD max Input voltage 1 Output voltage VIN1 VOUT Allowable power dissipation Pd max Operating temperature Conditions Ratings Unit 0.3 to +3.95 DVDD, AVDD, XVDD, VVDD1 0.3 to DVDD+0.3 0.3 to DVDD +0.3 Ta ≤ 85°C Mounted reference PCB(*) 300 40 to +85 Topr 40 to +125 Storage temperature Tstg (*) Reference PCB : 114.3mm×76.1mm×1.6mm, glass epoxy resin V mW °C <Notes> Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. Allowable Operating Ranges at Ta=40 to 85°C, DVSS=AVSS=XVSS=VVSS1=0V Parameter Symbol Supply voltage VDD High-level input voltage VIH Low-level input voltage VIL Crystal Oscillator Frequency FX External clock Input Pin Names DVDD, AVDD, XVDD, VVDD1 XIN,RESB, MODE, MODE3, CE, CL, DI, CONT00, CONT01, CONT02, CONT03, CONT04, CONT05, CONT08, CONT09, CONT10, DO, SDDAT00 to 15, SDADRS11, SDADRS12 XIN, RESB, TEST, MODE3, CE, CL, DI, CONT00, CONT01, CONT02, CONT03, CONT04, CONT05, CONT08, CONT09, CONT10, DO, SDDAT00 to 15, SDADRS11, SDADRS12 Type Schmitt MIN TYP MAX 3.00 3.60 2.00 VDD Unit V Schmitt XIN EXCK Conditions XOUT XIN 0.00 0.80 Oscillator circuit 16.9344 Schmitt 16.9344 MHz 18.0 MHz Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability. www.onsemi.com 3 LC78616PE Electrical Characteristics at Ta=40 to 85°C, VDD=3.0 to 3.6V, DVSS=AVSS=XVSS=VVSS1=0V Parameter Current drain High-level input current Low-level input current High-level output voltage Symbol Output off-leakage current Built-in Pull-down resistor Charge pump output current Type Conditions MIN TYP 40 (T.B.D) MAX 60 (T.B.D) VOL(2) DVDD, AVDD, XVDD, VVDD1 RESB, MODE, MODE3, CE, CL, DI, CONT00, CONT01, CONT02, CONT03, CONT04, CONT05, CONT08, CONT09, CONT10, DO, SDDAT00 to 15, SDADRS11, SDADRS12 RESB, TEST, MODE3, CE, CL, DI, CONT00, CONT01, CONT02, CONT03, CONT04, CONT05, CONT08, CONT09, CONT10, SDDAT00 to 15, SDADRS11, SDADRS12 DO, BUSYB, CONT00, CONT01, CONT02, CONT03, CONT05, CONT08, CONT09, CONT10, SDDAT00 to SDDAT15, SDADRS00 to SDADRS12, SDBA, SDCKE, SDCSB, SDRASB, SDCASB, SDWEB, SDDQM CL, DI, CONT04, SDCLK DO, BUSYB, CONT00, CONT01, CONT02, CONT03, CONT05, CONT08, CONT09, CONT10, SDDAT00 to SDDAT15, SDADRS00 to SDADRS12, SDBA, SDCKE, SDCSB, SDRASB, SDCASB, SDWEB, SDDQM CL, DI, CONT04, SDCLK IOFF(1) PDOUT0, PDOUT1 Hi-Z Out 10.00 10.00 IOFF(2) DO Hi-Z Out 10.00 10.00 IDD1 IIH IIL VOH(1) VOH(2) Low-level output voltage Pin Names VOL(1) RPD IPDOH IPDOL VIN=VDD Built-in Schmitt Pull-down Resistor OFF Unit mA 10.00 μA VIN=0.0V Built-in Schmitt Pull-down Resistor OFF CMOS IOH=2mA CMOS IOH=4mA CMOS IOL=2mA CMOS IOL=4mA CE, CONT00, CONT01, CONT02, CONT03, CONT04, CONT05, CONT08, CONT09, CONT10, SDDAT00 to SDDAT15, SDADRS11,SDADRS12 PCKIST= 100kΩ Current value Setting :1x PDOUT1, PDOUT0 PDOUT1, PDOUT0 10.00 VDD 0.6 V 0.40 μA 50 100 200 35 50 65 kΩ μA 65 50 35 (Notes) Connect and use the pull-up or the pull-down resister with the outside when you use serial communications because the terminal DO is 3- State output (initial state). The DO, BUSYB, CONT00, CONT01, CONT02, CONT03, CONT04, CONT05, CONT08, CONT09 and CONT10 pins can be used as the N channel open drain pins. When used as the N channel open drain pin, external pull-upresistor must be connected to those pins. Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. www.onsemi.com 4 LC78616PE Package Dimensions unit : mm PQFP100 14x20 / QIP100E CASE 122BV ISSUE A 0.8±0.2 23.2±0.2 17.2±0.2 100 14.0±0.1 20.0±0.1 12 0.65 0.3±0.05 0.15 0.13 0.1±0.1 (2.7) 3.0 MAX (0.58) 0 to 10° 0.10 SOLDERING FOOTPRINT* 22.30 GENERIC MARKING DIAGRAM* 16.30 (Unit: mm) 0.43 XXXXX = Specific Device Code Y = Year M = Month DDD = Additional Traceability Data 1.30 0.65 XXXXXXXXX YMDDD NOTE: The measurements are not to guarantee but for reference only. *For additional information on our Pb -Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. www.onsemi.com 5 *This information is generic. Please refer to device data sheet for actual part marking. may or may not be present. LC78616PE 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 AVSS LDS LDD TEIN TE NC FIN EIN JITTC VREF RFMON SLCISET DIN BIN CIN AIN PHLPF LPF RFOUT EFMIN PIN Assignment 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 DVDD DVSS SDDAT12 SDDAT11 SDDAT10 SDDAT09 SDDAT08 SDCLK SDCKE SDADRS09 SDADRS08 SDADRS07 SDADRS06 SDADRS05 SDADRS04 SDADRS03 SDADRS02 SDADRS01 SDADRS00 SDADRS10 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 LC78616 6DXX AVDD FDO TDO SLDO SPDO VVSS1 PDOUT1 PDOUT0 PCKIST VVDD1 MODE CE CL DI DO RESB TEST BUSYB CONT04 CONT05 CONT03 CONT02 CONT01 CONT00 SDDAT15 DVDD DVSS DVDD15 SDDAT14 SDDAT13 www.onsemi.com 6 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 SLCO DVSS CONT10 CONT09 CONT08 DVDD XVDD XIN XOUT XVSS SDADRS12/CONT07 SDADRS11/CONT06 SDDAT00 SDDAT01 SDDAT02 SDDAT03 SDDAT04 DVDD DVSS DVDD15 SDDAT05 SDDAT06 SDDAT07 SDDQM SDWEB SDCASB SDRASB SDCSB SDBA MODE3 LC78616PE Pin Description Pin No. 1 2 3 4 5 6 7 8 9 10 11 AVDD FDO TDO SLDO SPDO VVSS1 PDOUT1 PDOUT0 PCKIST VVDD1 MODE 12 CE I 13 CL I/O 14 DI I/O 15 DO I/O 16 RESB I 17 TEST I 18 BUSYB O 19 CONT04 I/O 20 CONT05 I/O 21 CONT03 I/O 22 CONT02 I/O 23 CONT01 I/O 24 CONT00 I/O 25 SDDAT15 I/O Pin name I/O AO AO AO AO AO AO AI I State when “Reset” AVDD/2 AVDD/2 AVDD/2 AVDD/2 Undefined Undefined Input Input Function Analog system power supply Focus control signal output Tracking control signal output Sled control signal output Spindle control signal output EFMPLL ground. This pin must be connected to the 0V level. EFMPLL charge pump output 1 EFMPLL charge pump output 0 EFMPLL charge pump current setting resistor connection pin EFMPLL power supply LSI mode set pin. This pin must be connected to the DVDD level. Host I/F Input Enable signal input for serial communication This pin must be connected to the 0V level in IIC communication mode. Host I/F Input Data transfer clock input for serial communication Data transfer clock input for IIC communication (N-ch. open drain) Host I/F Input Data input for serial communication Data input/output for IIC communication (N-ch. open drain) Host I/F Data output for serial communication Input This pin must be pulled down to the 0V level or be pulled up to the DVDD level in IIC communication mode. IC reset input.(Low active) Input This pin must be set low once after power is first applied. Test input. This pin must be connected to the 0V level. Input Host I/F Low BUSYB output(High : Communication available) General purpose I/O port with pull down resistor Digital audio output<S/PDIF> Input FS384 clock output for Audio DAC Clock input/output for CDTEXT interface (exclusive with CONT01 and CONT09) Watch Dog Timer state monitor output General purpose I/O port with pull down resistor Input Serial data output for CDTEXT interface General purpose I/O port with pull down resistor Digital audio output<S/PDIF> FS384 clock output for Audio DAC Input SBCK clock input for CD subcode data Data request signal input for CDTEXT interface (exclusive with CONT00 and CONT08) Watch Dog Timer state monitor output General purpose I/O port with pull down resistor Data output for Digital Audio interface Input PW data output in CD subcode Serial data output for CDTEXT interface General purpose I/O port with pull down resistor Bit clock output for CD data Input Bit clock input for CD data (exclusive with CONT09) Frame synchronization signal (SFSY) output for CD subcode Clock input/output for CDTEXT interface (exclusive with CONT04 and CONT09) General purpose I/O port LR clock output for CD data LR clock input for CD data (exclusive with CONT08) Input Block synchronization signal (SBSY) output for CD subcode Data request signal input for CDTEXT interface (exclusive with CONT03 and CONT08) Input(Low) SDRAM data 15 www.onsemi.com 7 LC78616PE Pin No. 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 Pin name I/O DVDD DVSS DVDD15 SDDAT14 SDDAT13 DVDD DVSS SDDAT12 SDDAT11 SDDAT10 SDDAT09 SDDAT08 SDCLK SDCKE SDADRS09 SDADRS08 SDADRS07 SDADRS06 SDADRS05 SDADRS04 SDADRS03 SDADRS02 SDADRS01 SDADRS00 SDADRS10 MODE3 AO I/O I/O I/O I/O I/O I/O I/O O O O O O O O O O O O O O I State when “Reset” High Input(Low) Input(Low) Input(Low) Input(Low) Input(Low) Input(Low) Input(Low) Low Low Low Low Low Low Low Low Low Low Low Low Low Input 52 SDBA O Low 53 54 55 56 SDCSB SDRASB SDCASB SDWEB O O O O Low Low Low Low 57 SDDQM O Low 58 59 60 61 62 63 64 65 66 67 68 SDDAT07 SDDAT06 SDDAT05 DVDD15 DVSS DVDD SDDAT04 SDDAT03 SDDAT02 SDDAT01 SDDAT00 I/O I/O I/O AO I/O I/O I/O I/O I/O Input(Low) Input(Low) Input(Low) High Input(Low) Input(Low) Input(Low) Input(Low) Input(Low) 69 SDADRS11 I/O Input(Low) 70 SDADRS12 I/O Input(Low) 71 72 73 74 75 XVSS XOUT XIN XVDD DVDD O I Oscillation Oscillation Function Digital system power supply Digital system ground. This pin must be connected to the 0V level. Capacitor connection pin for internal regulator SDRAM data 14 SDRAM data 13 Digital system power supply Digital system ground. This pin must be connected to the 0V level. SDRAM data 12 SDRAM data 11 SDRAM data 10 SDRAM data 9 SDRAM data 8 SDRAM system clock output SDRAM clock enable output SDRAM address output 9 SDRAM address output 8 SDRAM address output 7 SDRAM address output 6 SDRAM address output 5 SDRAM address output 4 SDRAM address output 3 SDRAM address output 2 SDRAM address output 1 SDRAM address output 0 SDRAM address output 10 LSI mode set pin SDRAM Bank select Address output Connect SDRAM-BANK pin when 16Mbit SDRAM using Connect SDRAM-BANK1 pin when 64Mbit SDRAM using SDRAM Chip Select output SDRAM Row Address Strobe output SDRAM Column Address Strobe output SDRAM Write Enable output SDRAM Data Mask Control output Common both for 16M/64Mbit-SDRAM : Connect this pin both to SDRAM-DQMH(UDQM) and DQML(LDQM) pins SDRAM data 7 SDRAM data 6 SDRAM data 5 Capacitor connection pin for internal regulator Digital system ground. This pin must be connected to the 0V level. Digital system power supply SDRAM data 4 SDRAM data 3 SDRAM data 2 SDRAM data 1 SDRAM data 0 Connect to SDRAM ADRS11 pin when using 64M bit SDRAM. SDRAM address output 11 CONT06 is available when using 16M bit SDRAM. General purpose I/O port with pull down resistor Connect to SDRAM BANK0 pin when using 64M bit SDRAM. SDRAM address output 12 CONT07 is available when using 16M bit SDRAM. General purpose I/O port with pull down resistor Oscillator ground. This pin must be connected to the 0V level. 16.9344MHz oscillator connection 16.9344MHz oscillator connection Oscillator power supply Digital system power supply www.onsemi.com 8 LC78616PE Pin No. Pin name I/O State when “Reset” 76 CONT08 I/O Input 77 CONT09 I/O Input 78 CONT10 I/O Input 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 DVSS SLCO EFMIN RFOUT LPF PHLPF AIN CIN BIN DIN SLCISET RFMON VREF JITTC EIN FIN NC TE TEIN LDD LDS AVSS AO AI AO AO AO AI AI AI AI AI AO AO AO AI AI AO AI AO AI Undefined Input Undefined Undefined Undefined Input Input Input Input Input Undefined AVDD/2 Undefined Input Input Undefined Input Undefined Input Function General purpose I/O port with LR clock output for CD data LR clock input for CD data (exclusive with CONT00) Data request signal input for CDTEXT interface (exclusive with CONT00 and CONT03) General purpose I/O port with pull down resistor Bit clock output for CD data Bit clock input for CD data (exclusive with CONT01) Clock input/output for CDTEXT interface (exclusive with CONT01 and CONT04) General purpose I/O port with pull down resistor Data output for Digital Audio interface Digital audio output<S/PDIF> Serial data output for CDTEXT interface Watch Dog Timer state monitor output Digital system ground. This pin must be connected to the 0V level. Slice Level Control output RF signal input RF signal output RF signal DC level detection low-pass filter capacitor connection Defect detection low-pass filter capacitor connection A signal input C signal input B signal input D signal input SLCO output current setting resistor connection IC internal analog signal monitor Reference voltage output for RF Jitter detection capacitor connection E signal input F signal input NC Pin (Open) TE signal output TE signal input used for TES signal generation Laser power control signal output Laser power detection signal input Analog system ground. This pin must be connected to the 0V level. <Notes> (1) For Unused pins : The unused input pins must be connected to the GND(0V) level if there is no individual note in the above table. The unused output pins must be left open(No connection) if there is no individual note in the above table. The unused input/output pins must be connected to the GND(0V) or power supply pin for I/O block with internal pull down/up resistor OFF or be left open with internal pull down/up resistor ON when input pin mode or must be left open(No connection ) when output pin mode if there is no individual note in the above table. When you connect an I/O pin which is an input pin without internal pull-down/up resistor at reset mode to the GND or power supply level, we recommend you to use pull-down resistor or pull-up resistor individually as fail-safe. (2) For Power supply pins : Same voltage level must be supplied to DVDD, AVDD, XVDD and VVDD1 power supply pins. (3) For “Reset” condition : This IC is not reset only by making the RESB pin “Low”. Refer to “4. Power on and Reset control” for detail of “Reset” condition. www.onsemi.com 9 LC78616PE Block Diagram External SDRAM CD RF Signal Processor AD/DA CD PLL CD Servo Controller CD-TEXT Decoder CD EFM/ECC Decoder DATA Trans Controller CDDA Anti Shock 8bit-CPU Core BUFRAM I/F Audio Data-I/F External-IN Data Output Control CDROM Data CDDA Data Work RAM Program ROM DeEMPHASIS/ MUTE/ATT DOUT(S/PDIF) Watch Dog Timer Interrupt Host-I/F (SIO) X'tal (16.9344MHz) PORT Control Regulator 1.5V 3.3V www.onsemi.com 10 LC78616PE Power on and Reset control Attention when power on The RESB pin must be set to “Low” level when power is first supplied. At that time, it is necessary to input a stable clock to the XIN pin. You may input the voltage of VDD or less to each input terminal when the power supply is off. 3.3V Power supply RESB tRESW2 tRESW1 During normal operation (Oscillation clock is valid) Power ON stage Parameter Symbol Min Typ Max Unit Reset time(Power on) tRESW1 20 ms Reset time(Normal) (*1) tRESW2 1 ms *1 : The oscillation must be stable during tRESW2. When the XIN clock has been stopped by the command etc. , the specification of tRESW2 could be larger than the value shown above, because it takes time that the XIN oscillator becomes stable. www.onsemi.com 11 LC78616PE Host interface The four wires serial interface is available as the data transmission protocol between this LSI and Host controller. It is able to know whether the internal sequencer could receive the command or not by the BUSYB pin. BUSYB Low High Command Acceptance situation All address command access disable All address command access disable except A0h to A7h addresses BUSYB becomes Low if the A5h address command is transmitted. All address command except A0h to A7h addresses will be ignored. By setting REG_READY command to High, internal register open mode is available. In this mode, Host controller can access to the all address command (internal sequencer can’t control the CDDSP block). When the A5h address command is transmitted, REG_READY command and BUSYB pin is set to Low, and internal register open mode become finish. Command Transfer Timing 1 : (Normal mode: BUSYB = "H" → "L") Tcsu Tchd CE Twl CL Twh DI Trsu Twsu Twhd Trdyoff BUSYB Trdyon Command Transfer Timing 2 : (Internal register open mode: BUSYB = "H") Tchd Tcsu CE Tce Twl CL Twh DI Trsu Twsu Twhd BUSYB www.onsemi.com 12 LC78616PE Command Receive Timing 1 : (Normal mode : BUSYB = "H" ) Tce Tcsu Tchd CE Twl CL Twh DI Ton Trhd DO Toff Trac BUSYB Read Setting Cycle (Write Timing) Read Access Cycle (*1) *1. High level must be supplied to the DI pin during Read Access Cycle. Command Receive Timing 2 : (Internal register open mode: BUSYB = "H") Tce Tcsu Tchd CE Twl CL Twh DI Ton Trhd DO Toff Trac BUSYB Read Access Cycle (*1) Read Setting Cycle (Write Timing) *1. High level must be supplied to the DI pin during Read Access Cycle. Parameter Setup time for READY Setup time for CE Hold time for CE Setup time for DI Hold time for DI High level clock pulse width Low level clock pulse width Access time for read data Symbol Trsu Tcsu Tchd Twsu Twhd Twh Twl Trac Hold time for read data Trhd Turn On Time for DO Turn Off Time for DO Command transfer time Turn Off Time for READY Turn On Time for READY(*1) Ton Toff Tce Trdyoff Trdyon Pin Names CE, BUSYB CE, CL CE, CL DI, CL DI, CL CL CL CL, DO CL, DO CE, DO CE, DO CE CE, BUSYB CE, BUSYB *1. Never communicate in this period. www.onsemi.com 13 Min 60 400 200 100 100 200 200 0 Typ Max Unit ns 100 120 150 0 1 0 0.175 300 200 50000 μs ns μs LC78616PE CD data output function Two modes can be available for CD data output. (1) Normal mode In this mode, output signals are LRCK, BCK and DATA. CLV or Jitter-Free(VCEC) playback is supported. When CDDA playback, depending on the specification of Audio DAC, FS384 clock output is also available . (2) Slave mode In ths mode, output signal is DATA, and input signals are LRCK, BCK. The DATA output is synchronized to input clocks (LRCK,BCK). It is enable to output CD data synchronized to Audio DAC without connecting FS384clock. This mode is only available for CD normal playback, and LRCK frequency must be 44.1kHz. 1. Normal mode Available format Mode Slot Length Data Length : IIS, MSB First Right-Justified, MSB First Left-Justified : 32fs, 48fs : 16-bit Used Pin LRCKO BCKO DATAO : CONT00, CONT08 : CONT01, CONT09 : CONT02, CONT10 Note When CDDA Playback, FS384 can be optionally output from CONT04 or CONT05. The signal input from XIN pin is output as FS384 signal. CD Data output timing LRCKO tABKO tABKO tBLP 1/fABCK tBLA BCKO DATAO tBDS Parameter Bit clock Frequency Bit clock "H" level width Bit clock "L" level width Setup time for LRCK (based on BCK negedge) Hold time for LRCK (based on BCK negedge) Setup time for DATA output Hold time for DATA output Symbol fABCKO tABKOH tABKOL tBLP tBLA tBDS tBDH tBDH Pin Names BCKO BCKO BCKO BCKO, LRCKO BCKO, LRCKO BCKO, DATAO BCKO, DATAO Min Max 10.5 unit MHz ns ns 0 15 ns 0 15 ns 47.5 47.5 30 30 * In case of quadruple speed playback, and setting the output format as 48fs slot length. www.onsemi.com 14 Typ ns ns LC78616PE 2. Slave mode In this mode, LRCK (Fs=44.1kHz) and BCK are input from external device, and output data is synchronized with input clocks. So, it is possible to play CDDA without FS384 or SRC (Sampling Rate Converter). Available format Mode : IIS, MSB First Right-Justified, MSB First Left-Justified Slot Length : 32fs, 48fs, 64fs Data Length : 16-bit Used Pin LRCKI BCKI DATAO : CONT00, CONT08 : CONT01, CONT09 : CONT02, CONT10 Slave mode data timing 1/fLRCKI tLRIL tLRIH LRCKI (In) tABKI tABKIL tBLIH tBLIS 1/fABCK BCKI (In) DATAO (Out) tDOS Parameter LRCK frequency LRCK "H" level width LRCK "L" level width Symbol fLRCKI tLRIH tLRIL Bit clock frequency fABCKI Bit clock "H" level width tABKIH Bit clock "L" level width tABKIL Setup time for LRCK input tBRIS Hold time for LRCK input tBLIH Setup time for DATA output tDOS Hold time for DATA output tDOH Pin Names LRCKI LRCKI LRCKI BCKI BCKI Min 10.3 10.3 160 BCKI 160 LRCKI, BCKI LRCKI, BCKI DATAO, BCKI DATAO, BCKI Typ 44.1 11.34 11.34 2.1168 *1 236.2 *1 236.2 *1 Max 48.5 3.10 unit kHz s s MHz ns ns 50 ns 50 ns 50 ns 50 ns *1: In case of setting the output format as 48fs slot length. www.onsemi.com 15 tDOH LC78616PE CD Subcode Data Output function It is possible to output the subcode data (PW data) according to the terminal setting when CD playback mode. The PW data are output at the rising edge of SBCK signal when the SBCK clock signal is input. <Note> The CD-TEXT function and the CD Subcode data output function are exclusive functions. It is impossible to use those two functions simultaneously. Used pins SBSY (Subcode Block Synchronous signal) SFSY (Subcode Frame Synchronous signal) PW (Subcode PW data) SBCK (Subcode data read clock) : CONT00 : CONT01 : CONT02 : CONT03 Subcode Data Output timing tSBFC SFSY (Output) tSBE tSBCKH SBCK (Input) tSBCKL PW (Output) P Q S R T U V W "0" P tSBRDL Subcode Block Synchronous Signal Output timing tSBBC SBSY (Output) tSBBH Parameter Symbol Pin Names Subcode Read Cycle time tSBFC SFSY Subcode Read Enable time SBCK clock "H" level width SBCK clock "L" level width PW data output Delay time tSBE tSBCKH tSBCKL tSBRDL SFSY, SBCK SBCK SBCK SBCK, PW SBSY output Cycle time tSBBC SBSY SBSY "H" level width tSBBH SBSY Min Typ 136 *1 400 250 250 0 Max us 100 13.3 *2 272 *2 <Notes> *1. When playback the CD at the normal speed (CLV playback). This value changes depending on the playback speed. *2. When playback the CD at the normal speed (CLV playback). The SBSY signal becomes high level during the first two subcoding symbols (S0 and S1) are asserted. www.onsemi.com 16 unit ns ns ns ns ms us LC78616PE CDTEXT data output function CDTEXT data are decoded and buffered to external SDRAM. There are two methods to output CDTEXT data from theSDRAM. (1) Command Communication output mode Outputs the CDTEXT data using the command communication protocol between this IC and external host controller. (2) Hand shake output mode using with hardware interface function A. Inputs data request signal and transfer clock then outputs CDTEXT data The CDTEXT data(CTDATO) will be output synchronizing with the CTCKI clock when the CTCKI clock is input after the CDTEXT data request signal is input(CTREQI="H"). B. Inputs data request signal then outputs transfer clock and CDTEXT data The CTCKO and CTDATO synchronized with CTCKO will be output after the CDTEXT data request signal is input (CTREQI= "H"). In both operation modes (1) and (2), the data transfer unit bit length is 2 Bytes (16 bits). * The CDTEXT function and CD subcode data output function are exclusive each other, and then those functions can not be used simultaneously. CDTEXT data output Timing 1 : CTCK input mode CTREQI (Input) tCTCKIN tCTCKL tCTCK 1/fSCI CTCKI (Input) CTDATO (Output) tCTDOD <Supplement> Both modes below are available. A. CTCKI="L" start mode The CTDATO is output synchronized with the rising edge of the CTCKI clock. The host controller should latch the CTDATO data at the falling edge of the CTCKI clock. B. CTCKI="H" start mode The CTDATO is output synchronized with the falling edge of the CTCKI clock. The host controller should latch the CTDATO data at the rising edge of the CTCKI clock. * The relationship between the signals in figure 8-1 and the pins is shown below. CTREQI : CONT00, CONT03, CONT08 CTCKI : CONT01, CONT04, CONT09 CTDATO :CONT02, CONT05, CONT10 Parameter CTCKI clock Frequency Symbol fSCI CTCKI clock input start time tCTCKIN CTCKI clock "H" level width CTCKI clock "L" level width tCTCKH tCTCKL CTDATO output Delay time tCTDODL1 Pin Names CTCKI CTREQI, CTCKI CTCKI CTCKI CTCKI, CTDATO Min Typ 17 unit MHz 1000 ns 400 400 ns ns Note : The above figure shows the case of mode A that the clock starts low level (CTCKI="L"). The timings are same when the clock starts high level (CTCKI="H"). www.onsemi.com Max 1.25 250 ns LC78616PE CDTEXT data output Timing 2 : CTCK output mod tCTOFF CTREQI (Input) tCTCOHtCTCOL tCTOAT 1/fSCO CTCKO (Output) CTDATO (Output) tCTDOD <Supplement> The CTCKO will be output starting with the high level then the CTDATO will be output synchronized with the falling edge of the CTCKO clock. The host controller should latch the CTDATO data at the rising edge of the CTCKO clock. * The relationship between the signals in figure 8-2 and the pins is shown below. CTREQI : CONT00, CONT03, CONT08 CTCKO : CONT01, CONT04, CONT09 CTDATO : CONT02, CONT05, CONT10 Parameter Symbol Pin Names Min CTCKO clock Frequency fSCO CTCKO 1.05 CDTEXT data output start time tCTOAT CDTEXT data output stop time Max unit 4.2 MHz CTREQI, CTCKO (1/fSCO) ×32 ns tCTOFF CTREQI, CTCKO (1/fSCO) ×32 ns CTCKO clock "H" level width tCTCOH CTCKO 400 100 ns CTCKO clock "L" level width tCTCOL CTCKO 400 100 ns CTDATO output Delay time tCTDODL2 CTDATO, CTCKO 0 50 ns www.onsemi.com 18 Typ LC78616PE Internal Voltage Regulator at Ta=40°C to 85°C, DVSS=AVSS=XVSS=VVSS1=0V Parameter Symbol Output Voltage DVDD15 Load current Iope Condition VDD=3.0 to 3.6V VDD=3.3V Min Typ Max Unit 1.35 1.50 1.65 V 50 mA Example circuit for Regulator * Same circuit need to be mounted both for two regulator pins. (No.28 and No.61) LC78616 DVDD DVSS DVDD15 100F C1 * C1 is the capacitor to avoid oscillation. This capacitor value must be low ESR and greater than 30F in the range of the operating temperature. Because there is a possibility of the oscillation when the capacity value changes by the temperature change etc. (The recommended value is 100F. ) A/D, D/A converter Characteristics for servo at Ta=40°C to 85°C, VDD=3.3V, DVSS=AVSS=XVSS=VVSS1=0V Parameter Symbol Resolution Res Min Typ Maximum input/output range Vaio1 8 4/5VDD Minimum input/output range Vaio2 1/5 VDD Max Unit bit V V Oscillator Example circuit for Oscillator LC78616 XVDD XIN Rd1 XOUT XVSS C1 C1 XIN/XOUT : 16.9344MHz For System clock of internal micro controller, CD control and Audio control Recommended Oscillators Murata Manufacturing Co., Ltd. SMD : CSTCE16M9V53-R0 <Built-in C> : CSTCW16M9X51008-R0 <Built-in C> Lead : CSTLS16M9X53-B0 <Built-in C> <Notes> Because the characteristics of oscillator could be changed according to the circuit board, ask evaluation with the individual original circuit board to the oscillator maker. Concerning about internal circuit for XIN/XOUT, refer to the "Analog Pin Internal Equivalent Circuits" section. The XIN pin can also be supplied from an external clock instead of connecting the oscillator. In this case, XOUT pin must be left open. www.onsemi.com 19 LC78616PE SDRAM Interface (1) Required specification for external SDRAM Memory size : 16M-bit or 64M-bit Data width : 16-bit CAS latency : 2 Burst length : Full (2) Interface pins to external SDRAM Pin Name Function at 16M-bit SDRAM Function at 64M-bit SDRAM Signal name in Figure 12-1, 2, 3 SDDAT15 to SDDAT00 Data Input/Output (16-bit) Data Input/Output (16-bit) DDAT[15:0] DDAT[15:0] SDADRS10 to SDADRS00 Address Output (11-bit) Address Output (11-bit) DADD[10:0] DADD[10:0] SDADRS11 Not used *1 Address(A11) Output DADD[11] SDADRS12 Not used *2 Address(A12) or Bank0 Output DADD[12] SDBA Bank Output Bank or Bank1 Output DADD[11] DADD[13] SDDQM DQMH/DQML (UDQM/LDQM) Output *3 DQMH/DQML (UDQM/LDQM) Output *3 SDDQM SDDQM SDCSB CSB Output CSB Output SDCSB SDCSB SDRASB RASB Output RASB Output SDRASB SDRASB SDCASB CASB Output CASB Output SDCASB SDCASB SDWEB WEB Output WEB Output SDWEB SDWEB SDCKE Clock Enable Output Clock Enable Output SDCKE SDCKE SDCLK Clock Output Clock Output SDCLK SDCLK <Notes> *1. SDADRS11 in 16M-bit SDRAM using mode can be used as CONT06 pin. *2. SDADRS12 in 16M-bit SDRAM using mode can be used as CONT07 pin. *3. The SDRAM access data width of this IC is sixteen bits. Therefore, connect the SDDQM of this IC to both the DQMH(UDQM) and DQML(LDQM) pins of SDRAM. *4. The all pins used for SDRAM interface are input pin mode and internal pull down resistor on mode in initial condition after reset of this IC. All the resistors will be off when the SDRAM use mode is set to be ON. *5. Some signals used in Figure 12-1 to Figure 12-3 use different pins according to the using SDRAM. The signal name in Figure 12-1 to Figure 12-3 for the actual pin is shown at the most right column in above table. Upper step : Signal name in 16M-bit SDRAM using mode Lower step : Signal name in 64M-bit SDRAM using mode www.onsemi.com 20 LC78616PE (3) SDRAM Access Timing SDRAM Read Timing TS2 TS3 TS5 TS6 SDCSB 1/FS1 TS7 SDCLK TS4 SDCKE TS5 TS6 TS7 SDRASB TS5 TS6 TS7 SDCASB SDWEB TS8 TS9 Column Row DADD[13:0] ALL-PRE Row Column SDDQM TS11 TS10 - DDAT[15:0] Read-Data CAS-Latency 2 SDRAM Write Timing TS2 TS3 TS5 TS6 SDCSB 1/FS1 TS7 SDCLK SDCKE TS5 TS6 TS7 SDRASB TS5 TS6 TS7 SDCASB SDWEB DADD[13:0] TS8 TS9 Row Column ALL-PR E Row Column ALL-PRE SDDQM TS13 TS12 DDAT[15:0] Write-Data Write-Data Data Latch Timing (SDRAM) www.onsemi.com 21 LC78616PE SDRAM Refresh Timing (Auto Refresh) TS14 TS5 TS6 SDCSB 1/FS1 TS15 TS7 SDCLK SDCKE TS5 TS6 TS7 SDRASB SDCASB SDWEB DADD[13:0] SDDQM DDAT[15:0] symbol FS1 TS2 TS3 TS4 TS5 TS6 TS7 TS8 TS9 TS10 TS11 TS12 TS13 TS14 TS15 parameter Min SDRAM clock(SDCLK) Frequency Row(SDRASB) Cycle time Row(SDRASB) Active time RASB-CASB Delay time(SDRASB-SDCASB) Command "L" level width (SDCSB, SDCKE, SDRASB, SDCASB, SDWEB) Command Setup time (SDCSB, SDCKE, SDRASB, SDCASB, SDWEB, SDDQMU, SDDQML) Command Hold time (SDCSB, SDCKE, SDRASB, SDCASB, SDWEB, SDDQMU, SDDQML) Address(DADD) Setup time Address(DADD) Hold time SDRAM Read Data Setup time (Data read from SDRAM) SDRAM Read Data Hold time (Data read from SDRAM) SDRAM Write Data Hold time before rising edge of SDCLK (Data write to SDRAM) SDRAM Write Data Hold time after rising edge of SDCLK (Data write to SDRAM) Row(SDRASB) Pre-charge time Row(SDRASB) Active time after Refresh typ max unit 16.9344 (1/FS1)×5 (1/FS1)×3 (1/FS1)×2 MHz ns ns ns 40 ns 10 ns 10 ns 10 10 ns ns 20 ns 0 ns 10 ns 10 ns (1/FS1)×3 (1/FS1)×5 ns ns <Notes> Setup time and Hold time specifications in above table are measured from the rising edge of SDCLK signal. All the specifications in above table are applied to Read mode, Write mode and Refresh mode. www.onsemi.com 22 LC78616PE Analog Pin Internal Equivalent Circuits Pin Name(Pin No.) Equivalent Circuit AVDD EFMIN (81) AVSS AVDD AVDD RFOUT (82) AVSS AVSS AVDD AVDD LPF (83) AVSS AVSS AVDD PHLPF (84) AVSS AVDD AIN (85) CIN (86) BIN (87) DIN (88) AVSS AVDD SLCISET (89) AVSS AVDD AVDD RFMON (90) AVSS www.onsemi.com 23 AVSS LC78616PE Pin Name(Pin No.) Equivalent Circuit AVDD AVDD VREF (91) AVSS AVSS AVDD JITTC (92) AVSS EIN (93) FIN (94) AVDD AVDD TE (96) AVSS AVSS AVDD TEIN (97) AVSS AVDD AVDD AVDD LDD (98) AVSS AVSS AVDD LDS (99) AVSS www.onsemi.com 24 LC78616PE Pin Name(Pin No.) Equivalent Circuit AVDD AVDD FDO (2) TDO (3) SLDO (4) SPDO (5) AVSS AVSS VVDD1 VVDD1 PDOUT1 (7) VVSS1 VVSS1 VVDD1 VVDD1 PDOUT0 (8) VVSS1 VVSS1 VVDD1 PCKIST (9) VVSS1 XVDD XOUT(72) XIN(73) VVSS1 XVDD XIN XOUT XVSS AVDD XVSS AVDD SLCO (80) AVSS www.onsemi.com 25 AVSS LC78616PE Sample Application Circuit VDD 16.9344MHz ( ( ( ( ) ) ) ) Vref (Reference Voltage) E ( F ( ) ) LC78616 6DXX 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 LD MD EFMIN RFOUT LPF PHLPF AIN CIN BIN DIN SLCISET RFMON VREF JITTC EIN FIN NC TE TEIN LDD LDS AVSS AVDD FDO TDO SLDO SPDO VVSS1 PDOUT1 PDOUT0 PCKIST VVDD1 MODE CE CL DI DO RESB TEST BUSYB To PICKUP A B C D 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 SLCO DVSS CONT10 CONT09 CONT08 DVDD XVDD XIN XOUT XVSS 80 79 78 77 76 75 74 73 72 71 GND FDO TDO SLDO SPDO VREF To -COM GND To Driver * This sample circuit is only for CD servo block and each PLL block. The value of each component needs to be adjusted under the target conditions. The circuit for CD servo shown above could be changed depending on the CD mechanism used. ON Semiconductor and the ON logo are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries. SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf . SCILLC reserves the right to make changes without further notice to any products herein. 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