Ordering number : ENA0663A LV5781 Bi-CMOS IC 3A, Point-of-load, Chopper-type Step-down Converter http://onsemi.com Overview The LV5781 is a 1-channel chopper-type (low-side Schottky diode) step-down switching regulator. It incorporates an 80mΩ (typical) power MOSFET to achieve high-efficiency operation for 3A output currents. The output voltage is set internally to 3.3V. By adding two external resistors, it is possible to set the voltage to any desired setting above 0.85V. Inrush current at startup can be prevented by the soft start function. Using the ON/OFF pins, the converter can be set to standby mode in which the current consumption is 10μA or less. Both the load and the IC are protected by means of the overcurrent and thermal protection functions. The converter uses the HSSOP14 miniature package. Functions • 3A, 1-channel chopper-type, step-down switching regulator • Output voltage: 3.3V • Setting of any output voltage enabled (external resistors required) • High efficiency: 90% at IOUT=1A, VO=3.3V • Miniature package: HSSOP14 • Soft start function • Standby mode • Overcurrent protection • Thermal shutdown • Fixed frequency: 180kHz Applications • LCD TVs • Game machines Semiconductor Components Industries, LLC, 2013 August, 2013 13107 MS IM 20070112-S00004 No.A0663-1/7 LV5781 Specifications Absolute Maximum Ratings at Ta=25°C Parameter Symbol Maximum input voltage VIN max Maximum CBOOT pin voltage Maximum SW pin voltage Maximum voltage between CBOOT and VBS max Conditions Ratings V VBT max 13 V VSW max 6.5 V 6.5 V 6.5 V 125 °C SW pins Maximum voltage at FB, SS, and Unit 6.5 Vfs max ENABLE pins Junction temperature Tj max Allowable power dissipation Pd max Operating temperature range Storage temperature range Mounted on a circuit board *1 0.85 W Topr -30 to +80 °C Tstg -40 to +125 °C *1: Mounted on a specified board: 114.3mm×76.1mm×1.6mm, glass epoxy. *2: To ensure that the maximum voltage is not exceeded even for an instant, check that the coil voltage and other surge voltage levels are factored in. Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. Recommended Operating Conditions at Ta=25°C Parameter Symbol Conditions Ratings Unit VIN pin voltage VIN 4.5 to 6 CBOOT pin voltage VBT 0 to 6 V V SW pin voltage VSW 6 V FB, SS, and ENABLE pin voltage VFSO 6 V Electrical Characteristics at Ta=25°C, VIN=5V (Unless specifically specified) Parameter Symbol Ratings Conditions min Output voltage 1 VOUT1 FB2 pin selected Output voltage 2 VOUT2 Dependent on the external voltage divider Standby mode IC consumption current ICC1 ENABLE=0V Operating time IC consumption current ICC2 ENABLE=3V ENABLE high level voltage VENH ENABLE low level voltage VENL Efficiency Effcy IOUT=1A, VO=3.3V Reference voltage Vref VIN=4.5V to 6V(±2%) typ 3.2 Unit max 3.3 3.4 V 1 10 μA 2 5 mA 0.85 V 3 V 0.7 90 0.76 V % 0.8 0.84 50 200 V FB pin bias current Iref On resistance Ron Soft start current ISS Oscillation frequency Fosc Maximum on duty ratio D max 85 % Current limiting value Icl 4.1 A Under voltage detection Vl 3.3 3.7 4.2 V Under voltage detection hysteresis Vlh 0.15 0.185 0.25 V CBOOT=5V Thermal shutdown temperature Ttsd Design guarantee value* Thermal shutdown temperature Dtsd Design guarantee value* hysteresis 80 nA mΩ 3 6.5 13 μA 145 180 225 kHz 180 °C 20 °C *These are design guarantee values and no measurements are made. No.A0663-2/7 LV5781 Package Dimensions unit : mm (typ) 3313 Pd max -- Ta 1.0 0.5 6.4 8 4.4 14 Allowable power dissipation, Pd max - W 6.5 1 7 0.22 1.3 0.15 0.65 1.5max (2.35) 0.85 0.8 0.6 0.4 0.38 0.2 0 -40 0.1 (1.3) 1.5 Mounted on a specified board: 114.3mm×76.1mm×1.6mm, glass epoxy -20 0 20 40 60 80 100 Ambient temperature, Ta - °C SANYO : HSSOP14(225mil) Block Diagram and Sample Application Circuits CBOOT VIN BOOT(SW+VIN) Pre-Drive SW VOUT FB_GND FB0 FB1 OSC 180kHz Error Amp PWM comparator FB2 S/D OERRAMP OCP 6.5μA SS S/D 3.2V Enable Internal Reg Vref 1.25V UVLO S/D TSD ON OFF GND No.A0663-3/7 LV5781 Pin Assignment and Sample Application Circuits G N D G N D 1 FB_GND FB0 14 2 ENABLE FB2 13 ON OFF 3 SS OERRAMP 12 4 FB1 CBOOT 11 5 VIN VIN 10 6 SW SW 9 7 PGND VIN 8 3.3V Sample Application Circuit 1 G N D G N D 1 FB_GND FB0 14 2 ENABLE FB2 13 ON OFF 3 SS OERRAMP 12 4 FB1 CBOOT 11 5 VIN VIN 10 6 SW SW 9 7 PGND VIN 8 VOUT Sample Application Circuit 2 *The capacitor between the FB0 and VOUT pins and capacitor between the OERRAMP pin and GND (the capacitors shown inside the broken lines in the diagram) are used for phase compensation. Their capacitance is intended to stop oscillation when oscillation is caused by the status of the output capacitor. As such, they can be left open under normal circumstances. No.A0663-4/7 LV5781 Pin Functions Pin No. Pin name 1 FB_GND 2 ENABLE Description GND of output voltage setting pins FB0 and FB2. It is connected to GND for use when pin FB2 is used. Output ON/OFF with an active-high polarity. When set to L, the current consumption is reduced to 10μA or less. 3 SS Soft start time constant setting. The charge current is set to approx. 6.5μA and when a capacitor of 0.1μF is connected between this pin and GND, the output rises in approx. 12ms. 4 FB1 Test pin for verifying the internal reference voltage. It must be set to open for actual use. 5, 8, 10 VIN Power input. It is used with voltages ranging from 4.5V to 6V. 6, 9 SW Inductor drive output 7 PGND Power GND pin. This is the output GND. It is connected so that where at all possible, no impedance is shared with other GND pins (GND, FB_GND). 11 CBOOT For generating the gate voltage of the internal high-side n-channel MOS transistor. A capacitor with a capacitance of at least 0.1μF (max. 2.2μF) is connected between this pin and the SW pin for use. 12 OERRAMP Transconductance-type Error_Amp output. An integration constant is provided between this pin and GND to implement phase compensation. 13 FB2 Used to feed back the output voltage to this pin when the output voltage is to be set to 3.3V. In such a case, FB_GND is connected to GND. Refer to application circuit 1. 14 FB0 When the output voltage is to be set to a desired value, connect resistors between FB0 and GND and between FB0 and VOUT to feed back the output voltage to this pin. In such a case, leave FB_GND and FB2 open. Refer to application circuit 2. Heat sink fin GND Analog GND (connected to GND). Input Equivalent Circuits Pin No. Pin Name Equivalent Circuit GND 5, 8, 10 VIN VIN GND 1 FB_GND 4 FB1 13 FB2 14 FB0 VIN 116kΩ FB2 50kΩ FB1 118kΩ FB0 54.5kΩ FB_GND GND Continued on next page No.A0663-5/7 LV5781 Continued from preceding page Pin No. Pin Name 2 ENABLE Equivalent Circuit VIN 55kΩ ENABLE 100kΩ GND 3 SS VIN 6.5μA Vref 300Ω 100Ω SS 300Ω FB0 97kΩ GND 6, 9 SW 7 PGND 11 CBOOT CBOOT VIN SW PGND GND 12 OERRAMP VIN OERRAMP 1kΩ GND No.A0663-6/7 LV5781 ON Semiconductor and the ON logo are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. 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