PYA28HC256 HIGH SPEED 32K x 8 EEPROM FEATURES Access Times of 70, 90 and 120ns Software Data Protection Single 5V±10% Power Supply Simple Byte and Page Write Low Power CMOS: - 80 mA Active Current - 3 mA Standby Current Fast Write Cycle Times CMOS & TTL Compatible Inputs and Outputs Endurance: - 10,000 Write Cycles - 100,000 Write Cycles (optional) Data Retention: 10 Years Available in the following package: – 28-Pin 600 mil Ceramic DIP – 32-Pin Ceramic LCC (450x550 mils) DESCRIPTION The PYA28HC256 is a 5 Volt 32Kx8 EEPROM. The device supports 64-byte page write operation. The PYA28HC256 features DATA and Toggle Bit Polling as well as a system software scheme used to indicate early completion of a Write Cycle. The device also includes user-optional software data protection. Data Retention is 10 Years. The device is available in a 28-Pin 600 mil wide Ceramic DIP and 32-Pin LCC. Functional Block Diagram Pin Configuration DIP (C5-1) Document # EEPROM106 REV 03 LCC (L6) Revised October 2014 PYA28HC256 - HIGH SPEED 32K x 8 EEPROM OPERATION READ Read operations are initiated by both OE and CE LOW. The read operation is terminated by either CE or OE returning HIGH. This two line control architecture eliminates bus contention in a system environment. The data bus will be in a high impedance state when either OE or CE is HIGH. BYTE WRITE Write operations are initiated when both CE and WE are LOW and OE is HIGH. The PYA28HC256 supports both a CE and WE controlled write cycle. That is, the address is latched by the falling edge of either CE or WE, whichever occurs last. Similarly, the data is latched internally by the rising edge of either CE or WE, whichever occurs first. A byte write operation, once initiated, will automatically continue to completion. PAGE WRITE The page write feature of the PYA28HC256 allows 1 to 64 bytes of data to be consecutively written to the PYA28HC256 during a single internal programming cycle. The host can fetch data from another device within the system during a page write operation (change the source address), but the page address (A6 through A14) for each subsequent valid write cycle to the part during this operation must be the same as the initial page address. The bytes within the page to be written are specified with the A0 through A5 inputs. The page write mode can be initiated during any write operation. Following the initial byte write cycle, the host can write an additional 1 to 63 bytes in the same manner as the first byte was written. Each successive byte load cycle, started by the WE HIGH to LOW transition, must begin within 150µs of the falling edge of the preceding WE. If a subsequent WE HIGH to LOW transition is not detected within 150µs, the internal automatic programming cycle will commence. There is no page write window limitation. Effectively, the page write window is infinitely wide, so long as the host continues to access the device within the byte load cycle time of 150µs. WRITE STATUS BITS The PYA28HC256 provides the user two write operation status bits. These can be used to optimize a system write cycle time. The status bits are mapped onto the I/O bus as shown below. DATA POLLING The PYA28HC256 features DATA Polling as a method to indicate to the host system that the byte write or page write cycle has completed. DATA Polling allows a simple bit test operation to determine the status of the PYA28HC256, eliminating additional interrupts or external hardware. During the internal programming cycle, any attempt to read the last byte written will produce the complement of that data on I/O7 (i.e., write data=0xxx xxxx, read data=1xxx xxxx). Once the programming cycle is complete, I/O7 will reflect true data. Note: If the PYA28HC256 is in the protected state and an illegal write operation is attempted, DATA Polling will not operate. TOGGLE BIT The PYA28HC256 also provides another method for determining when the internal write cycle is complete. During the internal programming cycle, I/O6 will toggle from HIGH to LOW and LOW to HIGH on subsequent attempts to read the device. When the internal cycle is complete the toggling will cease and the device will be accessible for addtional read or write operations. DATA PROTECTION Pyramid has incorporated both hardware and software features that will protect the memory against inadvertent writes during transitions of the host system power supply. Hardware Protection Hardware features protect against inadvertent writes to the PYA28C256 in the following ways: (a) VCC sense - if VCC is below 3.8V (typical) the write function is inhibited; (b) VCC power-on delay - once VCC has reached 3.8V the device will automatically time out 5 ms (typical) before allowing a write; (c) write inhibit - holding any one of OE low, CE high or WE high inhibits write cycles; and (d) noise filter - pulses of less than 15 ns (typical) on the WE or CE inputs will not initiate a write cycle. Software Data Protection A software controlled data protection feature has been implemented on the PYA28C256. When enabled, the software data protection (SDP), will prevent inadvertent writes. The SDP feature may be enabled or disabled by the user; the PYA28C256 is shipped from Pyramid with SDP disabled. SDP is enabled by the host system issuing a series of Document # EEPROM106 REV 03 Page 2 PYA28HC256 - HIGH SPEED 32K x 8 EEPROM three write commands; three specific bytes of data are written to the three specific addresses (refer to "Software Data Protection" algorithm). After writing the 3-byte command sequence and after tWC the entire PYA28C256 will be protected against inadvertent write operations. It should be noted, that once protected the host may still perform a byte or page write to the PYA28C256. This is done by preceding the data to be written by the same 3-byte command sequence used to enable SDP. Once set, SDP will remain active unless the disable command sequence is issued. Power transitions do not disable SDP and SDP will protect the PYA28C256 during power-up and power-down conditions. All command sequences must conform to the page write timing specifications. The data in the enable and disable command sequences is not written to the device and the memory addresses used in the sequence may be written with data in either a byte or page write operation. After setting SDP, any attempt to write to the device without the 3-byte command sequence will start the internal write timers. No data will be written to the device; however, for the duration of tWC, read operations will effectively be polling operations. DEVICE IDENTIFICATION An extra 64 bytes of EEPROM memory are available to the user for device identification. By raising A9 to 12V ± 0.5V and using address locations 7FC0H to 7FFFH the additional bytes may be written to or read from in the same manner as the regular memory array. OPTIONAL CHIP ERASE MODE The entire device can be erased using a 6-byte software code. Please see "Software Chip Erase" application note at the end of this datasheet for details. Document # EEPROM106 REV 03 Page 3 PYA28HC256 - HIGH SPEED 32K x 8 EEPROM Maximum Ratings(1) Sym RECOMMENDED OPERATING CONDITIONS Parameter Value Unit Grade(2) Ambient Temp GND VCC Military -55°C to +125°C 0V 5.0V ± 10% VCC Power Supply Pin with Respect to GND -0.3 to +6.25 V VTERM Terminal Voltage with Respect to GND (up to 6.25V) -0.5 to +6.25 V TA Operating Temperature -55 to +125 °C TBIAS Temperature Under Bias -55 to +125 °C TSTG Storage Temperature -65 to +150 °C Sym Parameter CAPACITANCES(4) (VCC = 5.0V, TA = 25°C, f = 1.0MHz) PT Power Dissipation 1.0 W CIN Input Capacitance IOUT DC Output Current 50 mA COUT Output Capacitance Conditions Typ Unit VIN = 0V 10 pF VOUT = 0V 10 pF DC ELECTRICAL CHARACTERISTICS (Over Recommended Operating Temperature & Supply Voltage)(2) Sym Parameter Test Conditions Min Max Unit VIH Input High Voltage 2.0 VCC + 0.3 V VIL Input Low Voltage -0.5(3) 0.8 V VHC CMOS Input High Voltage VCC - 0.2 VCC + 0.5 V VLC CMOS Input Low Voltage -0.5(3) 0.2 V VOL Output Low Voltage (TTL Load) IOL = +2.1 mA, VCC = Min 0.45 V VOH Output High Voltage (TTL Load) IOH = -0.4 mA, VCC = Min ILI Input Leakage Current ILO Output Leakage Current VCC = Max VIN = GND to VCC VCC = Max, CE = VIH, VOUT = GND to VCC CE ≥ VIH, OE = VIL, ISB Standby Power Supply Current (TTL Input Levels) 2.4 VCC = Max, f = Max, Outputs Open 90, 120ns V -10 +10 µA -10 +10 µA — 3 mA 60 mA — 300 µA — 80 mA 70ns CE ≥ VHC, ISB1 Standby Power Supply Current (CMOS Input Levels) VCC = Max, f = 0, Outputs Open, VIN ≤ VLC or VIN ≥ VHC CE = OE = VIL, ICC Supply Current WE = VIH, All I/O's = Open, Inputs = VCC = 5.5V Notes: 1.Stresses greater than those listed under Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to Maximum rating conditions for extended periods may affect reliability. Document # EEPROM106 REV 03 2.Extended temperature operation guaranteed with 400 linear feet per minute of air flow. 3. Transient inputs with VIL and IIL not more negative than -3.0V and -100mA, respectively, are permissible for pulse widths up to 20ns. 4. This parameter is sampled and not 100% tested. Page 4 PYA28HC256 - HIGH SPEED 32K x 8 EEPROM POWER-UP TIMING Symbol Parameter Max Unit tPUR Power-up to Read operation 100 µs tPUW Power-up to Write operation 5 ms AC ELECTRICAL CHARACTERISTICS—READ CYCLE (VCC = 5V ± 10%, All Temperature Ranges)(2) -70 -90 -120 Sym Parameter tAVAV Read Cycle Time tAVQV Address Access Time 70 90 120 ns tELQV Chip Enable Access Time 70 90 120 ns tOLQV Output Enable Access Time 35 40 50 ns tELQX Chip Enable to Output in Low Z tEHQZ Chip Disable to to Output in High Z tOLQX Output Enable to Output in Low Z tOHQZ Output Disable to Output in High Z tAVQX Output Hold from Address Change Min Max 70 Min 90 0 0 Min 0 0 ns 50 0 40 ns ns 50 0 Unit ns 0 40 35 Max 120 0 35 0 Max ns ns TIMING WAVEFORM OF READ CYCLE Document # EEPROM106 REV 03 Page 5 PYA28HC256 - HIGH SPEED 32K x 8 EEPROM AC CHARACTERISTICS—WRITE CYCLE (VCC = 5V ± 10%, All Temperature Ranges)(2) 70 / 90 / 120 Symbol Parameter tWHWL1 tEHEL1 Write Cycle Time tAVEL tAVWL Address Setup Time 0 ns tELAX tWLAX Address Hold Time 50 ns tWLEL tELWL Write Setup Time 0 ns tWHEH Write Hold Time 0 ns tOHEL tOHWL OE Setup Time 10 ns tWHOL OE Hold Time 10 ns tELEH tWLWH WE Pulse Width 100 ns tDVEH tDVWH Data Setup Time 50 ns tEHDX tWHDX Data Hold Time 0 ns tEHEL2 tWHWL2 Byte Load Cycle Time tELWL CE Setup Time 1 µs tOVHWL Output Setup Time 1 µs tEHWH CE Hold Time 1 µs tWHOH OE Hold Time 1 µs Document # EEPROM106 REV 03 Min Max 10 0.2 150 Unit ms µs Page 6 PYA28HC256 - HIGH SPEED 32K x 8 EEPROM TIMING WAVEFORM OF BYTE WRITE Cycle (cE Controlled) TIMING WAVEFORM OF BYTE WRITE Cycle (wE Controlled) Document # EEPROM106 REV 03 Page 7 PYA28HC256 - HIGH SPEED 32K x 8 EEPROM TIMING WAVEFORM OF PAGE WRITE CYCLE NOTES: • For each successive write within the page write operation, A6-A14 should be the same. Otherwise, writes to an unknown address could occur. • Between successive byte writes within a page write operation, OE can be strobed LOW. For example, this can be done with CE and WE HIGH to fetch data from another memory device within the system for the next write. Alternatively, this can be done with WE HIGH and CE LOW, effectively performing a polling operation. • The timings shown above are unique to page write operations. Individual byte load operations within the page write must conform to either the CE or WE controlled write cycle timing. Document # EEPROM106 REV 03 Page 8 PYA28HC256 - HIGH SPEED 32K x 8 EEPROM WRITE SEQUENCE FOR SOFTWARE DATA PROTECTION Document # EEPROM106 REV 03 SOFTWARE SEQUENCE TO DE-ACTIVATE SOFTWARE DATA PROTECTION Page 9 PYA28HC256 - HIGH SPEED 32K x 8 EEPROM AC TEST CONDITIONS Input Pulse Levels TRUTH TABLE GND to 3.0V Input Rise and Fall Times 10ns Input Timing Reference Level 1.5V Output Timing Reference Level 1.5V Output Load See Figure 1 Mode CE OE WE I/O Read L L H DOUT Write L H L DIN Write Inhibit X L X — Write Inhibit X X H — Standby H X X High Z Output Disable X H X High Z Figure 1. Output Load Document # EEPROM106 REV 03 Page 10 PYA28HC256 - HIGH SPEED 32K x 8 EEPROM APPLICATION NOTE - SOFTWARE CHIP ERASE The entire device can be erased at one time by using a 6-byte software code. The software chip erase code consists of 6-byte load commands to specific address locations with specific data patterns. Once the code has been entered, the device will set each byte to the high state (FFH). After the software chip erase has been initiated, the device will internally time the erase operation so that no external clocks are required. The maximum time required to erase the whole chip is tEC (20 ms). The software data protection is still enabled even after the software chip erase is performed. CHIP ERASE CYCLE CHARACTERISTICS Symbol Parameter tEC Chip Erase Cycle Time 20 ms Max CHIP ERASE SOFTWARE ALGORITHM(1)(3) Notes: 1. Data Format: (Hex); Address Format: (Hex). 2. After loading the 6-byte code, no byte loads are allowed until the completion of the erase cycle. The erase cycle will time itself to completion in 20 ms (max). 3. The flow diagram shown is for a x8 part. For a x16 part, the data should be 16 bits long (e.g., the data to be loaded should be AAAA for step 1 in the algorithm). CHIP ERASE CYCLE WAVEFORMS Notes: 1. OE must be high only when WE and CE are both low. Document # EEPROM106 REV 03 Page 11 PYA28HC256 - HIGH SPEED 32K x 8 EEPROM APPLICATION NOTE - SOFTWARE CHIP ERASE The entire device can be erased at one time by using a 6-byte software code. The software chip erase code consists of 6-byte load commands to specific address locations with specific data patterns. Once the code has been entered, the device will set each byte to the high state (FFH). After the software chip erase has been initiated, the device will internally time the erase operation so that no external clocks are required. The maximum time required to erase the whole chip is tEC (20 ms). The software data protection is still enabled even after the software chip erase is performed. CHIP ERASE CYCLE CHARACTERISTICS Symbol Parameter tEC Chip Erase Cycle Time 20 ms Max CHIP ERASE SOFTWARE ALGORITHM(1)(3) Notes: 1. Data Format: (Hex); Address Format: (Hex). 2. After loading the 6-byte code, no byte loads are allowed until the completion of the erase cycle. The erase cycle will time itself to completion in 20 ms (max). 3. The flow diagram shown is for a x8 part. For a x16 part, the data should be 16 bits long (e.g., the data to be loaded should be AAAA for step 1 in the algorithm). CHIP ERASE CYCLE WAVEFORMS Notes: 1. OE must be high only when WE and CE are both low. Document # EEPROM106 REV 03 Page 12 PYA28HC256 - HIGH SPEED 32K x 8 EEPROM ORDERING INFORMATION [1] Parts are not MIL-STD-883 compliant. Parts are processed per Test Method 5004. Document # EEPROM106 REV 03 Page 13 PYA28HC256 - HIGH SPEED 32K x 8 EEPROM SIDE BRAZED DUAL IN-LINE PACKAGE (600 mils) C5-1 Pkg # # Pins 28 (600 mil) Symbol Min Max A - 0.232 b 0.014 0.026 b2 0.045 0.065 C 0.008 0.018 D - 1.490 E 0.500 0.610 eA 0.600 BSC e 0.100 BSC L 0.125 0.200 Q 0.015 0.060 S1 0.005 - S2 0.005 - Pkg # L6 # Pins 32 RECTANGULAR LEADLESS CHIP CARRIER Symbol Min Max A 0.060 0.075 A1 0.050 0.065 B1 0.022 0.028 D 0.442 0.458 D1 0.300 BSC D2 0.150 BSC D3 - 0.458 E 0.540 0.560 E1 0.400 BSC E2 0.200 BSC E3 - 0.558 e 0.050 BSC h 0.040 REF j 0.020 REF L 0.045 0.055 L1 0.045 0.055 L2 0.075 0.095 ND 7 NE 9 Document # EEPROM106 REV 03 Page 14 PYA28HC256 - HIGH SPEED 32K x 8 EEPROM REVISIONS DOCUMENT NUMBER EEPROM106 DOCUMENT TITLE PYA28HC256 - HIGH SPEED 32K x 8 EEPROM REV ISSUE DATE ORIGINATOR OR Jan 2011 JDB New Data Sheet A Nov 2011 JDB Updated Ordering Info 02 Jul 2014 JDB Added Software Chip Erase App Note 03 Oct 2014 JDB Replaced MIL-STD-883 Class B process flow with Test Method 5004 Document # EEPROM106 REV 03 DESCRIPTION OF CHANGE Page 15